1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Global Instruction Selector for the AArch64 target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10const unsigned MAX_SUBTARGET_PREDICATES = 73;
11using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
12#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15 mutable MatcherState State;
16 typedef ComplexRendererFns(AArch64InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17 typedef void(AArch64InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
18 const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
19 static AArch64InstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20 static AArch64InstructionSelector::CustomRendererFn CustomRenderers[];
21 bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22 bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23 bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24 const uint8_t *getMatchTable() const override;
25 bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
26 bool testSimplePredicate(unsigned PredicateID) const override;
27 bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
28#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
29
30#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
31, State(2),
32ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
33#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
34
35#ifdef GET_GLOBALISEL_IMPL
36// LLT Objects.
37enum {
38 GILLT_s8,
39 GILLT_s16,
40 GILLT_s32,
41 GILLT_s64,
42 GILLT_s128,
43 GILLT_v2s32,
44 GILLT_v2s64,
45 GILLT_v4s16,
46 GILLT_v4s32,
47 GILLT_v8s8,
48 GILLT_v8s16,
49 GILLT_v16s8,
50 GILLT_nxv1s1,
51 GILLT_nxv2s1,
52 GILLT_nxv2s16,
53 GILLT_nxv2s32,
54 GILLT_nxv2s64,
55 GILLT_nxv4s1,
56 GILLT_nxv4s16,
57 GILLT_nxv4s32,
58 GILLT_nxv8s1,
59 GILLT_nxv8s16,
60 GILLT_nxv16s1,
61 GILLT_nxv16s8,
62};
63const static size_t NumTypeObjects = 24;
64const static LLT TypeObjects[] = {
65 LLT::scalar(8),
66 LLT::scalar(16),
67 LLT::scalar(32),
68 LLT::scalar(64),
69 LLT::scalar(128),
70 LLT::vector(ElementCount::getFixed(2), 32),
71 LLT::vector(ElementCount::getFixed(2), 64),
72 LLT::vector(ElementCount::getFixed(4), 16),
73 LLT::vector(ElementCount::getFixed(4), 32),
74 LLT::vector(ElementCount::getFixed(8), 8),
75 LLT::vector(ElementCount::getFixed(8), 16),
76 LLT::vector(ElementCount::getFixed(16), 8),
77 LLT::vector(ElementCount::getScalable(1), 1),
78 LLT::vector(ElementCount::getScalable(2), 1),
79 LLT::vector(ElementCount::getScalable(2), 16),
80 LLT::vector(ElementCount::getScalable(2), 32),
81 LLT::vector(ElementCount::getScalable(2), 64),
82 LLT::vector(ElementCount::getScalable(4), 1),
83 LLT::vector(ElementCount::getScalable(4), 16),
84 LLT::vector(ElementCount::getScalable(4), 32),
85 LLT::vector(ElementCount::getScalable(8), 1),
86 LLT::vector(ElementCount::getScalable(8), 16),
87 LLT::vector(ElementCount::getScalable(16), 1),
88 LLT::vector(ElementCount::getScalable(16), 8),
89};
90
91// Bits for subtarget features that participate in instruction matching.
92enum SubtargetFeatureBits : uint8_t {
93 Feature_HasPAuthBit = 8,
94 Feature_HasJSBit = 10,
95 Feature_HasComplxNumBit = 49,
96 Feature_HasRCPC_IMMOBit = 68,
97 Feature_HasFPARMv8Bit = 9,
98 Feature_HasNEONBit = 4,
99 Feature_HasSM4Bit = 48,
100 Feature_HasSHA3Bit = 47,
101 Feature_HasSHA2Bit = 19,
102 Feature_HasAESBit = 18,
103 Feature_HasDotProdBit = 2,
104 Feature_HasCRCBit = 12,
105 Feature_HasCSSCBit = 20,
106 Feature_HasNoCSSCBit = 24,
107 Feature_HasLSEBit = 25,
108 Feature_HasNoLSEBit = 72,
109 Feature_HasRDMBit = 17,
110 Feature_HasFullFP16Bit = 15,
111 Feature_HasNoFullFP16Bit = 65,
112 Feature_HasFP16FMLBit = 7,
113 Feature_HasFuseAESBit = 59,
114 Feature_HasSVEBit = 21,
115 Feature_HasSVE2Bit = 22,
116 Feature_HasSVE2p1Bit = 36,
117 Feature_HasSVE2AESBit = 31,
118 Feature_HasSVE2SM4Bit = 33,
119 Feature_HasSVE2SHA3Bit = 71,
120 Feature_HasSVE2BitPermBit = 32,
121 Feature_HasB16B16Bit = 28,
122 Feature_HasSMEandIsNonStreamingSafeBit = 42,
123 Feature_HasSMEBit = 38,
124 Feature_HasSMEF64F64Bit = 39,
125 Feature_HasSMEI16I64Bit = 41,
126 Feature_HasSME2andIsNonStreamingSafeBit = 45,
127 Feature_HasSME2Bit = 44,
128 Feature_HasSME2p1Bit = 46,
129 Feature_HasSVEorSMEBit = 0,
130 Feature_HasSVE2orSMEBit = 26,
131 Feature_HasSVE2orSME2Bit = 29,
132 Feature_HasSVE2p1_or_HasSMEBit = 43,
133 Feature_HasSVE2p1_or_HasSME2Bit = 23,
134 Feature_HasSVE2p1_or_HasSME2p1Bit = 37,
135 Feature_HasSMEF16F16orSMEF8F16Bit = 40,
136 Feature_HasNEONandIsStreamingSafeBit = 5,
137 Feature_HasRCPCBit = 67,
138 Feature_HasFRInt3264Bit = 16,
139 Feature_HasMTEBit = 13,
140 Feature_HasTMEBit = 11,
141 Feature_HasBF16Bit = 3,
142 Feature_HasNoBF16Bit = 66,
143 Feature_HasMatMulInt8Bit = 6,
144 Feature_HasMatMulFP32Bit = 34,
145 Feature_HasMatMulFP64Bit = 35,
146 Feature_HasLS64Bit = 63,
147 Feature_HasHBCBit = 14,
148 Feature_HasRCPC3Bit = 64,
149 Feature_HasGCSBit = 1,
150 Feature_IsLEBit = 55,
151 Feature_IsBEBit = 60,
152 Feature_UseExperimentalZeroingPseudosBit = 30,
153 Feature_UseAlternateSExtLoadCVTF32Bit = 58,
154 Feature_UseScalarIncVLBit = 27,
155 Feature_NoUseScalarIncVLBit = 70,
156 Feature_UseSVEFPLD1RBit = 69,
157 Feature_NotForCodeSizeBit = 57,
158 Feature_UseSTRQroBit = 56,
159 Feature_TailCallX16X17Bit = 51,
160 Feature_TailCallX17Bit = 61,
161 Feature_TailCallNotX16Bit = 62,
162 Feature_TailCallAnyBit = 50,
163 Feature_SLSBLRMitigationBit = 54,
164 Feature_NoSLSBLRMitigationBit = 53,
165 Feature_OptimizedGISelOrOtherSelectorBit = 52,
166};
167
168PredicateBitset AArch64InstructionSelector::
169computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const {
170 PredicateBitset Features{};
171 if (Subtarget->hasPAuth())
172 Features.set(Feature_HasPAuthBit);
173 if (Subtarget->hasJS())
174 Features.set(Feature_HasJSBit);
175 if (Subtarget->hasComplxNum())
176 Features.set(Feature_HasComplxNumBit);
177 if (Subtarget->hasRCPC_IMMO())
178 Features.set(Feature_HasRCPC_IMMOBit);
179 if (Subtarget->hasFPARMv8())
180 Features.set(Feature_HasFPARMv8Bit);
181 if (Subtarget->isNeonAvailable())
182 Features.set(Feature_HasNEONBit);
183 if (Subtarget->hasSM4())
184 Features.set(Feature_HasSM4Bit);
185 if (Subtarget->hasSHA3())
186 Features.set(Feature_HasSHA3Bit);
187 if (Subtarget->hasSHA2())
188 Features.set(Feature_HasSHA2Bit);
189 if (Subtarget->hasAES())
190 Features.set(Feature_HasAESBit);
191 if (Subtarget->hasDotProd())
192 Features.set(Feature_HasDotProdBit);
193 if (Subtarget->hasCRC())
194 Features.set(Feature_HasCRCBit);
195 if (Subtarget->hasCSSC())
196 Features.set(Feature_HasCSSCBit);
197 if (!Subtarget->hasCSSC())
198 Features.set(Feature_HasNoCSSCBit);
199 if (Subtarget->hasLSE())
200 Features.set(Feature_HasLSEBit);
201 if (!Subtarget->hasLSE())
202 Features.set(Feature_HasNoLSEBit);
203 if (Subtarget->hasRDM())
204 Features.set(Feature_HasRDMBit);
205 if (Subtarget->hasFullFP16())
206 Features.set(Feature_HasFullFP16Bit);
207 if (!Subtarget->hasFullFP16())
208 Features.set(Feature_HasNoFullFP16Bit);
209 if (Subtarget->hasFP16FML())
210 Features.set(Feature_HasFP16FMLBit);
211 if (Subtarget->hasFuseAES())
212 Features.set(Feature_HasFuseAESBit);
213 if (Subtarget->isSVEAvailable())
214 Features.set(Feature_HasSVEBit);
215 if (Subtarget->isSVEAvailable() && Subtarget->hasSVE2())
216 Features.set(Feature_HasSVE2Bit);
217 if (Subtarget->isSVEAvailable() && Subtarget->hasSVE2p1())
218 Features.set(Feature_HasSVE2p1Bit);
219 if (Subtarget->isSVEAvailable() && Subtarget->hasSVE2AES())
220 Features.set(Feature_HasSVE2AESBit);
221 if (Subtarget->isSVEAvailable() && Subtarget->hasSVE2SM4())
222 Features.set(Feature_HasSVE2SM4Bit);
223 if (Subtarget->isSVEAvailable() && Subtarget->hasSVE2SHA3())
224 Features.set(Feature_HasSVE2SHA3Bit);
225 if (Subtarget->isSVEAvailable() && Subtarget->hasSVE2BitPerm())
226 Features.set(Feature_HasSVE2BitPermBit);
227 if (Subtarget->hasB16B16())
228 Features.set(Feature_HasB16B16Bit);
229 if (Subtarget->hasSME())
230 Features.set(Feature_HasSMEandIsNonStreamingSafeBit);
231 if (Subtarget->isStreaming() && Subtarget->hasSME())
232 Features.set(Feature_HasSMEBit);
233 if (Subtarget->isStreaming() && Subtarget->hasSMEF64F64())
234 Features.set(Feature_HasSMEF64F64Bit);
235 if (Subtarget->isStreaming() && Subtarget->hasSMEI16I64())
236 Features.set(Feature_HasSMEI16I64Bit);
237 if (Subtarget->hasSME2())
238 Features.set(Feature_HasSME2andIsNonStreamingSafeBit);
239 if (Subtarget->isStreaming() && Subtarget->hasSME2())
240 Features.set(Feature_HasSME2Bit);
241 if (Subtarget->isStreaming() && Subtarget->hasSME2p1())
242 Features.set(Feature_HasSME2p1Bit);
243 if (Subtarget->hasSVE() || (Subtarget->isStreaming() && Subtarget->hasSME()))
244 Features.set(Feature_HasSVEorSMEBit);
245 if (Subtarget->hasSVE2() || (Subtarget->isStreaming() && Subtarget->hasSME()))
246 Features.set(Feature_HasSVE2orSMEBit);
247 if (Subtarget->hasSVE2() || (Subtarget->isStreaming() && Subtarget->hasSME2()))
248 Features.set(Feature_HasSVE2orSME2Bit);
249 if (Subtarget->hasSVE2p1() || (Subtarget->isStreaming() && Subtarget->hasSME()))
250 Features.set(Feature_HasSVE2p1_or_HasSMEBit);
251 if (Subtarget->hasSVE2p1() || (Subtarget->isStreaming() && Subtarget->hasSME2()))
252 Features.set(Feature_HasSVE2p1_or_HasSME2Bit);
253 if (Subtarget->hasSVE2p1() || (Subtarget->isStreaming() && Subtarget->hasSME2p1()))
254 Features.set(Feature_HasSVE2p1_or_HasSME2p1Bit);
255 if (Subtarget->isStreaming() && (Subtarget->hasSMEF16F16() || Subtarget->hasSMEF8F16()))
256 Features.set(Feature_HasSMEF16F16orSMEF8F16Bit);
257 if (Subtarget->hasNEON())
258 Features.set(Feature_HasNEONandIsStreamingSafeBit);
259 if (Subtarget->hasRCPC())
260 Features.set(Feature_HasRCPCBit);
261 if (Subtarget->hasFRInt3264())
262 Features.set(Feature_HasFRInt3264Bit);
263 if (Subtarget->hasMTE())
264 Features.set(Feature_HasMTEBit);
265 if (Subtarget->hasTME())
266 Features.set(Feature_HasTMEBit);
267 if (Subtarget->hasBF16())
268 Features.set(Feature_HasBF16Bit);
269 if (!Subtarget->hasBF16())
270 Features.set(Feature_HasNoBF16Bit);
271 if (Subtarget->hasMatMulInt8())
272 Features.set(Feature_HasMatMulInt8Bit);
273 if (Subtarget->hasMatMulFP32())
274 Features.set(Feature_HasMatMulFP32Bit);
275 if (Subtarget->hasMatMulFP64())
276 Features.set(Feature_HasMatMulFP64Bit);
277 if (Subtarget->hasLS64())
278 Features.set(Feature_HasLS64Bit);
279 if (Subtarget->hasHBC())
280 Features.set(Feature_HasHBCBit);
281 if (Subtarget->hasRCPC3())
282 Features.set(Feature_HasRCPC3Bit);
283 if (Subtarget->hasGCS())
284 Features.set(Feature_HasGCSBit);
285 if (Subtarget->isLittleEndian())
286 Features.set(Feature_IsLEBit);
287 if (!Subtarget->isLittleEndian())
288 Features.set(Feature_IsBEBit);
289 if (Subtarget->useExperimentalZeroingPseudos())
290 Features.set(Feature_UseExperimentalZeroingPseudosBit);
291 if (Subtarget->useAlternateSExtLoadCVTF32Pattern())
292 Features.set(Feature_UseAlternateSExtLoadCVTF32Bit);
293 if (Subtarget->useScalarIncVL())
294 Features.set(Feature_UseScalarIncVLBit);
295 if (!Subtarget->useScalarIncVL())
296 Features.set(Feature_NoUseScalarIncVLBit);
297 if (!Subtarget->noSVEFPLD1R())
298 Features.set(Feature_UseSVEFPLD1RBit);
299 return Features;
300}
301
302void AArch64InstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
303 AvailableFunctionFeatures = computeAvailableFunctionFeatures((const AArch64Subtarget *)&MF.getSubtarget(), &MF);
304}
305PredicateBitset AArch64InstructionSelector::
306computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget, const MachineFunction *MF) const {
307 PredicateBitset Features{};
308 if (!shouldOptForSize(MF))
309 Features.set(Feature_NotForCodeSizeBit);
310 if (!Subtarget->isSTRQroSlow() || shouldOptForSize(MF))
311 Features.set(Feature_UseSTRQroBit);
312 if ( MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() && !MF->getInfo<AArch64FunctionInfo>()->branchProtectionPAuthLR() )
313 Features.set(Feature_TailCallX16X17Bit);
314 if ( MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() && MF->getInfo<AArch64FunctionInfo>()->branchProtectionPAuthLR() )
315 Features.set(Feature_TailCallX17Bit);
316 if ( !MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() && MF->getInfo<AArch64FunctionInfo>()->branchProtectionPAuthLR() )
317 Features.set(Feature_TailCallNotX16Bit);
318 if ( !MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() && !MF->getInfo<AArch64FunctionInfo>()->branchProtectionPAuthLR() )
319 Features.set(Feature_TailCallAnyBit);
320 if ( MF->getSubtarget<AArch64Subtarget>().hardenSlsBlr() )
321 Features.set(Feature_SLSBLRMitigationBit);
322 if ( !MF->getSubtarget<AArch64Subtarget>().hardenSlsBlr() )
323 Features.set(Feature_NoSLSBLRMitigationBit);
324 if (!MF->getFunction().hasOptNone() || MF->getProperties().hasProperty(MachineFunctionProperties::Property::FailedISel) || !MF->getProperties().hasProperty(MachineFunctionProperties::Property::Legalized))
325 Features.set(Feature_OptimizedGISelOrOtherSelectorBit);
326 return Features;
327}
328
329// Feature bitsets.
330enum {
331 GIFBS_Invalid,
332 GIFBS_HasAES,
333 GIFBS_HasBF16,
334 GIFBS_HasCRC,
335 GIFBS_HasCSSC,
336 GIFBS_HasDotProd,
337 GIFBS_HasFPARMv8,
338 GIFBS_HasFRInt3264,
339 GIFBS_HasFullFP16,
340 GIFBS_HasFuseAES,
341 GIFBS_HasGCS,
342 GIFBS_HasLSE,
343 GIFBS_HasMTE,
344 GIFBS_HasMatMulInt8,
345 GIFBS_HasNEON,
346 GIFBS_HasNEONandIsStreamingSafe,
347 GIFBS_HasNoBF16,
348 GIFBS_HasNoCSSC,
349 GIFBS_HasNoFullFP16,
350 GIFBS_HasNoLSE,
351 GIFBS_HasPAuth,
352 GIFBS_HasRCPC,
353 GIFBS_HasRCPC_IMMO,
354 GIFBS_HasRDM,
355 GIFBS_HasSHA2,
356 GIFBS_HasSHA3,
357 GIFBS_HasSM4,
358 GIFBS_HasSME,
359 GIFBS_HasSME2,
360 GIFBS_HasSMEF16F16orSMEF8F16,
361 GIFBS_HasSMEF64F64,
362 GIFBS_HasSMEI16I64,
363 GIFBS_HasSMEandIsNonStreamingSafe,
364 GIFBS_HasSVE,
365 GIFBS_HasSVE2,
366 GIFBS_HasSVE2AES,
367 GIFBS_HasSVE2BitPerm,
368 GIFBS_HasSVE2SHA3,
369 GIFBS_HasSVE2SM4,
370 GIFBS_HasSVE2orSME,
371 GIFBS_HasSVE2p1_or_HasSME,
372 GIFBS_HasSVE2p1_or_HasSME2,
373 GIFBS_HasSVE2p1_or_HasSME2p1,
374 GIFBS_HasSVEorSME,
375 GIFBS_HasTME,
376 GIFBS_IsBE,
377 GIFBS_IsLE,
378 GIFBS_OptimizedGISelOrOtherSelector,
379 GIFBS_UseSTRQro,
380 GIFBS_HasB16B16_HasSME2,
381 GIFBS_HasB16B16_HasSVE2orSME2,
382 GIFBS_HasBF16_HasNEON,
383 GIFBS_HasBF16_HasNEONandIsStreamingSafe,
384 GIFBS_HasBF16_HasSVE,
385 GIFBS_HasBF16_HasSVEorSME,
386 GIFBS_HasComplxNum_HasNEON,
387 GIFBS_HasFP16FML_HasNEON,
388 GIFBS_HasFPARMv8_HasJS,
389 GIFBS_HasFullFP16_HasNEON,
390 GIFBS_HasFullFP16_HasNEONandIsStreamingSafe,
391 GIFBS_HasMatMulFP32_HasSVE,
392 GIFBS_HasMatMulFP64_HasSVE,
393 GIFBS_HasMatMulFP64_HasSVEorSME,
394 GIFBS_HasMatMulInt8_HasSVE,
395 GIFBS_HasMatMulInt8_HasSVEorSME,
396 GIFBS_HasNEON_HasRCPC3,
397 GIFBS_HasNEON_HasRDM,
398 GIFBS_HasSVEorSME_UseScalarIncVL,
399 GIFBS_IsLE_UseSTRQro,
400 GIFBS_HasComplxNum_HasFullFP16_HasNEON,
401 GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32,
402};
403constexpr static PredicateBitset FeatureBitsets[] {
404 {}, // GIFBS_Invalid
405 {Feature_HasAESBit, },
406 {Feature_HasBF16Bit, },
407 {Feature_HasCRCBit, },
408 {Feature_HasCSSCBit, },
409 {Feature_HasDotProdBit, },
410 {Feature_HasFPARMv8Bit, },
411 {Feature_HasFRInt3264Bit, },
412 {Feature_HasFullFP16Bit, },
413 {Feature_HasFuseAESBit, },
414 {Feature_HasGCSBit, },
415 {Feature_HasLSEBit, },
416 {Feature_HasMTEBit, },
417 {Feature_HasMatMulInt8Bit, },
418 {Feature_HasNEONBit, },
419 {Feature_HasNEONandIsStreamingSafeBit, },
420 {Feature_HasNoBF16Bit, },
421 {Feature_HasNoCSSCBit, },
422 {Feature_HasNoFullFP16Bit, },
423 {Feature_HasNoLSEBit, },
424 {Feature_HasPAuthBit, },
425 {Feature_HasRCPCBit, },
426 {Feature_HasRCPC_IMMOBit, },
427 {Feature_HasRDMBit, },
428 {Feature_HasSHA2Bit, },
429 {Feature_HasSHA3Bit, },
430 {Feature_HasSM4Bit, },
431 {Feature_HasSMEBit, },
432 {Feature_HasSME2Bit, },
433 {Feature_HasSMEF16F16orSMEF8F16Bit, },
434 {Feature_HasSMEF64F64Bit, },
435 {Feature_HasSMEI16I64Bit, },
436 {Feature_HasSMEandIsNonStreamingSafeBit, },
437 {Feature_HasSVEBit, },
438 {Feature_HasSVE2Bit, },
439 {Feature_HasSVE2AESBit, },
440 {Feature_HasSVE2BitPermBit, },
441 {Feature_HasSVE2SHA3Bit, },
442 {Feature_HasSVE2SM4Bit, },
443 {Feature_HasSVE2orSMEBit, },
444 {Feature_HasSVE2p1_or_HasSMEBit, },
445 {Feature_HasSVE2p1_or_HasSME2Bit, },
446 {Feature_HasSVE2p1_or_HasSME2p1Bit, },
447 {Feature_HasSVEorSMEBit, },
448 {Feature_HasTMEBit, },
449 {Feature_IsBEBit, },
450 {Feature_IsLEBit, },
451 {Feature_OptimizedGISelOrOtherSelectorBit, },
452 {Feature_UseSTRQroBit, },
453 {Feature_HasB16B16Bit, Feature_HasSME2Bit, },
454 {Feature_HasB16B16Bit, Feature_HasSVE2orSME2Bit, },
455 {Feature_HasBF16Bit, Feature_HasNEONBit, },
456 {Feature_HasBF16Bit, Feature_HasNEONandIsStreamingSafeBit, },
457 {Feature_HasBF16Bit, Feature_HasSVEBit, },
458 {Feature_HasBF16Bit, Feature_HasSVEorSMEBit, },
459 {Feature_HasComplxNumBit, Feature_HasNEONBit, },
460 {Feature_HasFP16FMLBit, Feature_HasNEONBit, },
461 {Feature_HasFPARMv8Bit, Feature_HasJSBit, },
462 {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
463 {Feature_HasFullFP16Bit, Feature_HasNEONandIsStreamingSafeBit, },
464 {Feature_HasMatMulFP32Bit, Feature_HasSVEBit, },
465 {Feature_HasMatMulFP64Bit, Feature_HasSVEBit, },
466 {Feature_HasMatMulFP64Bit, Feature_HasSVEorSMEBit, },
467 {Feature_HasMatMulInt8Bit, Feature_HasSVEBit, },
468 {Feature_HasMatMulInt8Bit, Feature_HasSVEorSMEBit, },
469 {Feature_HasNEONBit, Feature_HasRCPC3Bit, },
470 {Feature_HasNEONBit, Feature_HasRDMBit, },
471 {Feature_HasSVEorSMEBit, Feature_UseScalarIncVLBit, },
472 {Feature_IsLEBit, Feature_UseSTRQroBit, },
473 {Feature_HasComplxNumBit, Feature_HasFullFP16Bit, Feature_HasNEONBit, },
474 {Feature_HasNEONBit, Feature_NotForCodeSizeBit, Feature_UseAlternateSExtLoadCVTF32Bit, },
475};
476
477// ComplexPattern predicates.
478enum {
479 GICP_Invalid,
480 GICP_gi_addsub_shifted_imm32,
481 GICP_gi_addsub_shifted_imm64,
482 GICP_gi_am_indexed128,
483 GICP_gi_am_indexed16,
484 GICP_gi_am_indexed32,
485 GICP_gi_am_indexed64,
486 GICP_gi_am_indexed8,
487 GICP_gi_am_unscaled128,
488 GICP_gi_am_unscaled16,
489 GICP_gi_am_unscaled32,
490 GICP_gi_am_unscaled64,
491 GICP_gi_am_unscaled8,
492 GICP_gi_arith_extended_reg32_i32,
493 GICP_gi_arith_extended_reg32_i64,
494 GICP_gi_arith_extended_reg32to64_i64,
495 GICP_gi_arith_shifted_reg32,
496 GICP_gi_arith_shifted_reg64,
497 GICP_gi_extract_high_v16i8,
498 GICP_gi_extract_high_v4f32,
499 GICP_gi_extract_high_v4i32,
500 GICP_gi_extract_high_v8f16,
501 GICP_gi_extract_high_v8i16,
502 GICP_gi_logical_shifted_reg32,
503 GICP_gi_logical_shifted_reg64,
504 GICP_gi_neg_addsub_shifted_imm32,
505 GICP_gi_neg_addsub_shifted_imm64,
506 GICP_gi_ro_Windexed128,
507 GICP_gi_ro_Windexed16,
508 GICP_gi_ro_Windexed32,
509 GICP_gi_ro_Windexed64,
510 GICP_gi_ro_Windexed8,
511 GICP_gi_ro_Xindexed128,
512 GICP_gi_ro_Xindexed16,
513 GICP_gi_ro_Xindexed32,
514 GICP_gi_ro_Xindexed64,
515 GICP_gi_ro_Xindexed8,
516};
517// See constructor for table contents
518
519AArch64InstructionSelector::ComplexMatcherMemFn
520AArch64InstructionSelector::ComplexPredicateFns[] = {
521 nullptr, // GICP_Invalid
522 &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm32
523 &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm64
524 &AArch64InstructionSelector::selectAddrModeIndexed<128>, // gi_am_indexed128
525 &AArch64InstructionSelector::selectAddrModeIndexed<16>, // gi_am_indexed16
526 &AArch64InstructionSelector::selectAddrModeIndexed<32>, // gi_am_indexed32
527 &AArch64InstructionSelector::selectAddrModeIndexed<64>, // gi_am_indexed64
528 &AArch64InstructionSelector::selectAddrModeIndexed<8>, // gi_am_indexed8
529 &AArch64InstructionSelector::selectAddrModeUnscaled128, // gi_am_unscaled128
530 &AArch64InstructionSelector::selectAddrModeUnscaled16, // gi_am_unscaled16
531 &AArch64InstructionSelector::selectAddrModeUnscaled32, // gi_am_unscaled32
532 &AArch64InstructionSelector::selectAddrModeUnscaled64, // gi_am_unscaled64
533 &AArch64InstructionSelector::selectAddrModeUnscaled8, // gi_am_unscaled8
534 &AArch64InstructionSelector::selectArithExtendedRegister, // gi_arith_extended_reg32_i32
535 &AArch64InstructionSelector::selectArithExtendedRegister, // gi_arith_extended_reg32_i64
536 &AArch64InstructionSelector::selectArithExtendedRegister, // gi_arith_extended_reg32to64_i64
537 &AArch64InstructionSelector::selectArithShiftedRegister, // gi_arith_shifted_reg32
538 &AArch64InstructionSelector::selectArithShiftedRegister, // gi_arith_shifted_reg64
539 &AArch64InstructionSelector::selectExtractHigh, // gi_extract_high_v16i8
540 &AArch64InstructionSelector::selectExtractHigh, // gi_extract_high_v4f32
541 &AArch64InstructionSelector::selectExtractHigh, // gi_extract_high_v4i32
542 &AArch64InstructionSelector::selectExtractHigh, // gi_extract_high_v8f16
543 &AArch64InstructionSelector::selectExtractHigh, // gi_extract_high_v8i16
544 &AArch64InstructionSelector::selectLogicalShiftedRegister, // gi_logical_shifted_reg32
545 &AArch64InstructionSelector::selectLogicalShiftedRegister, // gi_logical_shifted_reg64
546 &AArch64InstructionSelector::selectNegArithImmed, // gi_neg_addsub_shifted_imm32
547 &AArch64InstructionSelector::selectNegArithImmed, // gi_neg_addsub_shifted_imm64
548 &AArch64InstructionSelector::selectAddrModeWRO<128>, // gi_ro_Windexed128
549 &AArch64InstructionSelector::selectAddrModeWRO<16>, // gi_ro_Windexed16
550 &AArch64InstructionSelector::selectAddrModeWRO<32>, // gi_ro_Windexed32
551 &AArch64InstructionSelector::selectAddrModeWRO<64>, // gi_ro_Windexed64
552 &AArch64InstructionSelector::selectAddrModeWRO<8>, // gi_ro_Windexed8
553 &AArch64InstructionSelector::selectAddrModeXRO<128>, // gi_ro_Xindexed128
554 &AArch64InstructionSelector::selectAddrModeXRO<16>, // gi_ro_Xindexed16
555 &AArch64InstructionSelector::selectAddrModeXRO<32>, // gi_ro_Xindexed32
556 &AArch64InstructionSelector::selectAddrModeXRO<64>, // gi_ro_Xindexed64
557 &AArch64InstructionSelector::selectAddrModeXRO<8>, // gi_ro_Xindexed8
558};
559
560// PatFrag predicates.
561enum {
562 GICXXPred_MI_Predicate_add_and_or_is_add = GICXXPred_Invalid + 1,
563 GICXXPred_MI_Predicate_ldaxr_1,
564 GICXXPred_MI_Predicate_ldaxr_2,
565 GICXXPred_MI_Predicate_ldaxr_4,
566 GICXXPred_MI_Predicate_ldaxr_8,
567 GICXXPred_MI_Predicate_ldxr_1,
568 GICXXPred_MI_Predicate_ldxr_2,
569 GICXXPred_MI_Predicate_ldxr_4,
570 GICXXPred_MI_Predicate_ldxr_8,
571 GICXXPred_MI_Predicate_stlxr_1,
572 GICXXPred_MI_Predicate_stlxr_2,
573 GICXXPred_MI_Predicate_stlxr_4,
574 GICXXPred_MI_Predicate_stlxr_8,
575 GICXXPred_MI_Predicate_stxr_1,
576 GICXXPred_MI_Predicate_stxr_2,
577 GICXXPred_MI_Predicate_stxr_4,
578 GICXXPred_MI_Predicate_stxr_8,
579};
580bool AArch64InstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
581 const MachineFunction &MF = *MI.getParent()->getParent();
582 const MachineRegisterInfo &MRI = MF.getRegInfo();
583 const auto &Operands = State.RecordedOperands;
584 (void)Operands;
585 (void)MRI;
586 switch (PredicateID) {
587 case GICXXPred_MI_Predicate_add_and_or_is_add: {
588
589 // Only handle G_ADD for now. FIXME. build capability to compute whether
590 // operands of G_OR have common bits set or not.
591 return MI.getOpcode() == TargetOpcode::G_ADD;
592
593 llvm_unreachable("add_and_or_is_add should have returned");
594 }
595 case GICXXPred_MI_Predicate_ldaxr_1: {
596 return isLoadStoreOfNumBytes(MI, 1);
597 }
598 case GICXXPred_MI_Predicate_ldaxr_2: {
599 return isLoadStoreOfNumBytes(MI, 2);
600 }
601 case GICXXPred_MI_Predicate_ldaxr_4: {
602 return isLoadStoreOfNumBytes(MI, 4);
603 }
604 case GICXXPred_MI_Predicate_ldaxr_8: {
605 return isLoadStoreOfNumBytes(MI, 8);
606 }
607 case GICXXPred_MI_Predicate_ldxr_1: {
608 return isLoadStoreOfNumBytes(MI, 1);
609 }
610 case GICXXPred_MI_Predicate_ldxr_2: {
611 return isLoadStoreOfNumBytes(MI, 2);
612 }
613 case GICXXPred_MI_Predicate_ldxr_4: {
614 return isLoadStoreOfNumBytes(MI, 4);
615 }
616 case GICXXPred_MI_Predicate_ldxr_8: {
617 return isLoadStoreOfNumBytes(MI, 8);
618 }
619 case GICXXPred_MI_Predicate_stlxr_1: {
620 return isLoadStoreOfNumBytes(MI, 1);
621 }
622 case GICXXPred_MI_Predicate_stlxr_2: {
623 return isLoadStoreOfNumBytes(MI, 2);
624 }
625 case GICXXPred_MI_Predicate_stlxr_4: {
626 return isLoadStoreOfNumBytes(MI, 4);
627 }
628 case GICXXPred_MI_Predicate_stlxr_8: {
629 return isLoadStoreOfNumBytes(MI, 8);
630 }
631 case GICXXPred_MI_Predicate_stxr_1: {
632 return isLoadStoreOfNumBytes(MI, 1);
633 }
634 case GICXXPred_MI_Predicate_stxr_2: {
635 return isLoadStoreOfNumBytes(MI, 2);
636 }
637 case GICXXPred_MI_Predicate_stxr_4: {
638 return isLoadStoreOfNumBytes(MI, 4);
639 }
640 case GICXXPred_MI_Predicate_stxr_8: {
641 return isLoadStoreOfNumBytes(MI, 8);
642 }
643 }
644 llvm_unreachable("Unknown predicate");
645 return false;
646}
647// PatFrag predicates.
648enum {
649 GICXXPred_I64_Predicate_VectorIndex0 = GICXXPred_Invalid + 1,
650 GICXXPred_I64_Predicate_VectorIndex0_timm,
651 GICXXPred_I64_Predicate_VectorIndex1,
652 GICXXPred_I64_Predicate_VectorIndex1_timm,
653 GICXXPred_I64_Predicate_VectorIndex032b,
654 GICXXPred_I64_Predicate_VectorIndex032b_timm,
655 GICXXPred_I64_Predicate_VectorIndex132b,
656 GICXXPred_I64_Predicate_VectorIndex132b_timm,
657 GICXXPred_I64_Predicate_VectorIndexB,
658 GICXXPred_I64_Predicate_VectorIndexB32b,
659 GICXXPred_I64_Predicate_VectorIndexB32b_timm,
660 GICXXPred_I64_Predicate_VectorIndexB_timm,
661 GICXXPred_I64_Predicate_VectorIndexD,
662 GICXXPred_I64_Predicate_VectorIndexD32b,
663 GICXXPred_I64_Predicate_VectorIndexD32b_timm,
664 GICXXPred_I64_Predicate_VectorIndexD_timm,
665 GICXXPred_I64_Predicate_VectorIndexH,
666 GICXXPred_I64_Predicate_VectorIndexH32b,
667 GICXXPred_I64_Predicate_VectorIndexH32b_timm,
668 GICXXPred_I64_Predicate_VectorIndexH_timm,
669 GICXXPred_I64_Predicate_VectorIndexS,
670 GICXXPred_I64_Predicate_VectorIndexS32b,
671 GICXXPred_I64_Predicate_VectorIndexS32b_timm,
672 GICXXPred_I64_Predicate_VectorIndexS_timm,
673 GICXXPred_I64_Predicate_complexrotateop,
674 GICXXPred_I64_Predicate_complexrotateopodd,
675 GICXXPred_I64_Predicate_i64imm_32bit,
676 GICXXPred_I64_Predicate_i64imm_32bit_tgt,
677 GICXXPred_I64_Predicate_imm0_1,
678 GICXXPred_I64_Predicate_imm0_3,
679 GICXXPred_I64_Predicate_imm0_7,
680 GICXXPred_I64_Predicate_imm0_15,
681 GICXXPred_I64_Predicate_imm0_31,
682 GICXXPred_I64_Predicate_imm0_63,
683 GICXXPred_I64_Predicate_imm0_127,
684 GICXXPred_I64_Predicate_imm0_127_64b,
685 GICXXPred_I64_Predicate_imm0_255,
686 GICXXPred_I64_Predicate_imm32_0_15,
687 GICXXPred_I64_Predicate_imm32_0_31,
688 GICXXPred_I64_Predicate_imm64_0_65535,
689 GICXXPred_I64_Predicate_maski8_or_more,
690 GICXXPred_I64_Predicate_maski16_or_more,
691 GICXXPred_I64_Predicate_rprfop,
692 GICXXPred_I64_Predicate_s64imm_32bit,
693 GICXXPred_I64_Predicate_simm4s1,
694 GICXXPred_I64_Predicate_simm4s2,
695 GICXXPred_I64_Predicate_simm4s3,
696 GICXXPred_I64_Predicate_simm4s4,
697 GICXXPred_I64_Predicate_simm4s16,
698 GICXXPred_I64_Predicate_simm4s32,
699 GICXXPred_I64_Predicate_simm5_8b,
700 GICXXPred_I64_Predicate_simm5_8b_tgt,
701 GICXXPred_I64_Predicate_simm5_16b,
702 GICXXPred_I64_Predicate_simm5_16b_tgt,
703 GICXXPred_I64_Predicate_simm5_32b,
704 GICXXPred_I64_Predicate_simm5_32b_tgt,
705 GICXXPred_I64_Predicate_simm5_64b,
706 GICXXPred_I64_Predicate_simm5_64b_tgt,
707 GICXXPred_I64_Predicate_simm6_32b,
708 GICXXPred_I64_Predicate_simm6s1,
709 GICXXPred_I64_Predicate_simm8_32b,
710 GICXXPred_I64_Predicate_simm8_64b,
711 GICXXPred_I64_Predicate_simm9,
712 GICXXPred_I64_Predicate_sme_elm_idx0_0,
713 GICXXPred_I64_Predicate_sme_elm_idx0_1,
714 GICXXPred_I64_Predicate_sme_elm_idx0_3,
715 GICXXPred_I64_Predicate_sme_elm_idx0_7,
716 GICXXPred_I64_Predicate_sme_elm_idx0_15,
717 GICXXPred_I64_Predicate_svcr_op,
718 GICXXPred_I64_Predicate_sve_elm_idx_extdup_b,
719 GICXXPred_I64_Predicate_sve_elm_idx_extdup_b_timm,
720 GICXXPred_I64_Predicate_sve_elm_idx_extdup_d,
721 GICXXPred_I64_Predicate_sve_elm_idx_extdup_d_timm,
722 GICXXPred_I64_Predicate_sve_elm_idx_extdup_h,
723 GICXXPred_I64_Predicate_sve_elm_idx_extdup_h_timm,
724 GICXXPred_I64_Predicate_sve_elm_idx_extdup_q,
725 GICXXPred_I64_Predicate_sve_elm_idx_extdup_q_timm,
726 GICXXPred_I64_Predicate_sve_elm_idx_extdup_s,
727 GICXXPred_I64_Predicate_sve_elm_idx_extdup_s_timm,
728 GICXXPred_I64_Predicate_sve_incdec_imm,
729 GICXXPred_I64_Predicate_sve_pred_enum,
730 GICXXPred_I64_Predicate_sve_prfop,
731 GICXXPred_I64_Predicate_sve_vec_len_specifier_enum,
732 GICXXPred_I64_Predicate_tbz_imm0_31_diag,
733 GICXXPred_I64_Predicate_tbz_imm0_31_nodiag,
734 GICXXPred_I64_Predicate_tbz_imm32_63,
735 GICXXPred_I64_Predicate_timm0_1,
736 GICXXPred_I64_Predicate_timm0_31,
737 GICXXPred_I64_Predicate_timm0_63,
738 GICXXPred_I64_Predicate_timm32_0_0,
739 GICXXPred_I64_Predicate_timm32_0_1,
740 GICXXPred_I64_Predicate_timm32_0_3,
741 GICXXPred_I64_Predicate_timm32_0_7,
742 GICXXPred_I64_Predicate_timm32_0_15,
743 GICXXPred_I64_Predicate_timm32_0_31,
744 GICXXPred_I64_Predicate_timm32_0_255,
745 GICXXPred_I64_Predicate_timm32_0_65535,
746 GICXXPred_I64_Predicate_timm32_1_1,
747 GICXXPred_I64_Predicate_timm32_1_3,
748 GICXXPred_I64_Predicate_timm32_1_7,
749 GICXXPred_I64_Predicate_timm64_0_65535,
750 GICXXPred_I64_Predicate_tuimm5s2,
751 GICXXPred_I64_Predicate_tuimm5s4,
752 GICXXPred_I64_Predicate_tuimm5s8,
753 GICXXPred_I64_Predicate_tvecshiftL8,
754 GICXXPred_I64_Predicate_tvecshiftL16,
755 GICXXPred_I64_Predicate_tvecshiftL32,
756 GICXXPred_I64_Predicate_tvecshiftL64,
757 GICXXPred_I64_Predicate_tvecshiftR8,
758 GICXXPred_I64_Predicate_tvecshiftR16,
759 GICXXPred_I64_Predicate_tvecshiftR32,
760 GICXXPred_I64_Predicate_tvecshiftR64,
761 GICXXPred_I64_Predicate_ubsan_trap_imm,
762 GICXXPred_I64_Predicate_uimm0s2range,
763 GICXXPred_I64_Predicate_uimm0s4range,
764 GICXXPred_I64_Predicate_uimm1s2range,
765 GICXXPred_I64_Predicate_uimm1s4range,
766 GICXXPred_I64_Predicate_uimm2s2range,
767 GICXXPred_I64_Predicate_uimm2s4range,
768 GICXXPred_I64_Predicate_uimm3s2range,
769 GICXXPred_I64_Predicate_uimm3s8,
770 GICXXPred_I64_Predicate_uimm5s2,
771 GICXXPred_I64_Predicate_uimm5s4,
772 GICXXPred_I64_Predicate_uimm5s8,
773 GICXXPred_I64_Predicate_uimm6,
774 GICXXPred_I64_Predicate_uimm6s1,
775 GICXXPred_I64_Predicate_uimm6s2,
776 GICXXPred_I64_Predicate_uimm6s4,
777 GICXXPred_I64_Predicate_uimm6s8,
778 GICXXPred_I64_Predicate_uimm6s16,
779 GICXXPred_I64_Predicate_uimm8_32b,
780 GICXXPred_I64_Predicate_uimm8_64b,
781 GICXXPred_I64_Predicate_uimm16,
782 GICXXPred_I64_Predicate_vecshiftL8,
783 GICXXPred_I64_Predicate_vecshiftL16,
784 GICXXPred_I64_Predicate_vecshiftL32,
785 GICXXPred_I64_Predicate_vecshiftL64,
786 GICXXPred_I64_Predicate_vecshiftR8,
787 GICXXPred_I64_Predicate_vecshiftR16,
788 GICXXPred_I64_Predicate_vecshiftR16Narrow,
789 GICXXPred_I64_Predicate_vecshiftR32,
790 GICXXPred_I64_Predicate_vecshiftR32Narrow,
791 GICXXPred_I64_Predicate_vecshiftR64,
792 GICXXPred_I64_Predicate_vecshiftR64Narrow,
793};
794bool AArch64InstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
795 switch (PredicateID) {
796 case GICXXPred_I64_Predicate_VectorIndex0: {
797 return ((uint64_t)Imm) == 0;
798 }
799 case GICXXPred_I64_Predicate_VectorIndex0_timm: {
800 return ((uint64_t)Imm) == 0;
801 }
802 case GICXXPred_I64_Predicate_VectorIndex1: {
803 return ((uint64_t)Imm) == 1;
804 }
805 case GICXXPred_I64_Predicate_VectorIndex1_timm: {
806 return ((uint64_t)Imm) == 1;
807 }
808 case GICXXPred_I64_Predicate_VectorIndex032b: {
809 return ((uint32_t)Imm) == 0;
810 }
811 case GICXXPred_I64_Predicate_VectorIndex032b_timm: {
812 return ((uint32_t)Imm) == 0;
813 }
814 case GICXXPred_I64_Predicate_VectorIndex132b: {
815 return ((uint64_t)Imm) == 1;
816 }
817 case GICXXPred_I64_Predicate_VectorIndex132b_timm: {
818 return ((uint64_t)Imm) == 1;
819 }
820 case GICXXPred_I64_Predicate_VectorIndexB: {
821 return ((uint64_t)Imm) < 16;
822 }
823 case GICXXPred_I64_Predicate_VectorIndexB32b: {
824 return ((uint64_t)Imm) < 16;
825 }
826 case GICXXPred_I64_Predicate_VectorIndexB32b_timm: {
827 return ((uint64_t)Imm) < 16;
828 }
829 case GICXXPred_I64_Predicate_VectorIndexB_timm: {
830 return ((uint64_t)Imm) < 16;
831 }
832 case GICXXPred_I64_Predicate_VectorIndexD: {
833 return ((uint64_t)Imm) < 2;
834 }
835 case GICXXPred_I64_Predicate_VectorIndexD32b: {
836 return ((uint64_t)Imm) < 2;
837 }
838 case GICXXPred_I64_Predicate_VectorIndexD32b_timm: {
839 return ((uint64_t)Imm) < 2;
840 }
841 case GICXXPred_I64_Predicate_VectorIndexD_timm: {
842 return ((uint64_t)Imm) < 2;
843 }
844 case GICXXPred_I64_Predicate_VectorIndexH: {
845 return ((uint64_t)Imm) < 8;
846 }
847 case GICXXPred_I64_Predicate_VectorIndexH32b: {
848 return ((uint64_t)Imm) < 8;
849 }
850 case GICXXPred_I64_Predicate_VectorIndexH32b_timm: {
851 return ((uint64_t)Imm) < 8;
852 }
853 case GICXXPred_I64_Predicate_VectorIndexH_timm: {
854 return ((uint64_t)Imm) < 8;
855 }
856 case GICXXPred_I64_Predicate_VectorIndexS: {
857 return ((uint64_t)Imm) < 4;
858 }
859 case GICXXPred_I64_Predicate_VectorIndexS32b: {
860 return ((uint64_t)Imm) < 4;
861 }
862 case GICXXPred_I64_Predicate_VectorIndexS32b_timm: {
863 return ((uint64_t)Imm) < 4;
864 }
865 case GICXXPred_I64_Predicate_VectorIndexS_timm: {
866 return ((uint64_t)Imm) < 4;
867 }
868 case GICXXPred_I64_Predicate_complexrotateop: {
869 return Imm >= 0 && Imm <= 270;
870 }
871 case GICXXPred_I64_Predicate_complexrotateopodd: {
872 return Imm >= 0 && Imm <= 270;
873 }
874 case GICXXPred_I64_Predicate_i64imm_32bit: {
875
876 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
877
878 }
879 case GICXXPred_I64_Predicate_i64imm_32bit_tgt: {
880
881 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
882
883 }
884 case GICXXPred_I64_Predicate_imm0_1: {
885
886 return ((uint64_t)Imm) < 2;
887
888 }
889 case GICXXPred_I64_Predicate_imm0_3: {
890
891 return ((uint64_t)Imm) < 4;
892
893 }
894 case GICXXPred_I64_Predicate_imm0_7: {
895
896 return ((uint64_t)Imm) < 8;
897
898 }
899 case GICXXPred_I64_Predicate_imm0_15: {
900
901 return ((uint64_t)Imm) < 16;
902
903 }
904 case GICXXPred_I64_Predicate_imm0_31: {
905
906 return ((uint64_t)Imm) < 32;
907
908 }
909 case GICXXPred_I64_Predicate_imm0_63: {
910
911 return ((uint64_t)Imm) < 64;
912
913 }
914 case GICXXPred_I64_Predicate_imm0_127: {
915
916 return ((uint32_t)Imm) < 128;
917
918 }
919 case GICXXPred_I64_Predicate_imm0_127_64b: {
920
921 return ((uint64_t)Imm) < 128;
922
923 }
924 case GICXXPred_I64_Predicate_imm0_255: {
925
926 return ((uint32_t)Imm) < 256;
927
928 }
929 case GICXXPred_I64_Predicate_imm32_0_15: {
930
931 return ((uint32_t)Imm) < 16;
932
933 }
934 case GICXXPred_I64_Predicate_imm32_0_31: {
935
936 return ((uint64_t)Imm) < 32;
937
938 }
939 case GICXXPred_I64_Predicate_imm64_0_65535: {
940
941 return ((uint64_t)Imm) < 65536;
942
943 }
944 case GICXXPred_I64_Predicate_maski8_or_more: {
945 return (Imm & 0xff) == 0xff;
946 }
947 case GICXXPred_I64_Predicate_maski16_or_more: {
948 return (Imm & 0xffff) == 0xffff;
949 }
950 case GICXXPred_I64_Predicate_rprfop: {
951
952 return (((uint32_t)Imm) <= 63);
953
954 }
955 case GICXXPred_I64_Predicate_s64imm_32bit: {
956
957 int64_t Imm64 = static_cast<int64_t>(Imm);
958 return Imm64 >= std::numeric_limits<int32_t>::min() &&
959 Imm64 <= std::numeric_limits<int32_t>::max();
960
961 llvm_unreachable("s64imm_32bit should have returned");
962 }
963 case GICXXPred_I64_Predicate_simm4s1: {
964 return Imm >=-8 && Imm <= 7;
965 }
966 case GICXXPred_I64_Predicate_simm4s2: {
967 return Imm >=-16 && Imm <= 14 && (Imm % 2) == 0x0;
968 }
969 case GICXXPred_I64_Predicate_simm4s3: {
970 return Imm >=-24 && Imm <= 21 && (Imm % 3) == 0x0;
971 }
972 case GICXXPred_I64_Predicate_simm4s4: {
973 return Imm >=-32 && Imm <= 28 && (Imm % 4) == 0x0;
974 }
975 case GICXXPred_I64_Predicate_simm4s16: {
976 return Imm >=-128 && Imm <= 112 && (Imm % 16) == 0x0;
977 }
978 case GICXXPred_I64_Predicate_simm4s32: {
979 return Imm >=-256 && Imm <= 224 && (Imm % 32) == 0x0;
980 }
981 case GICXXPred_I64_Predicate_simm5_8b: {
982 return (int8_t)Imm >= -16 && (int8_t)Imm < 16;
983 }
984 case GICXXPred_I64_Predicate_simm5_8b_tgt: {
985 return (int8_t)Imm >= -16 && (int8_t)Imm < 16;
986 }
987 case GICXXPred_I64_Predicate_simm5_16b: {
988 return (int16_t)Imm >= -16 && (int16_t)Imm < 16;
989 }
990 case GICXXPred_I64_Predicate_simm5_16b_tgt: {
991 return (int16_t)Imm >= -16 && (int16_t)Imm < 16;
992 }
993 case GICXXPred_I64_Predicate_simm5_32b: {
994 return Imm >= -16 && Imm < 16;
995 }
996 case GICXXPred_I64_Predicate_simm5_32b_tgt: {
997 return (int32_t)Imm >= -16 && (int32_t)Imm < 16;
998 }
999 case GICXXPred_I64_Predicate_simm5_64b: {
1000 return Imm >= -16 && Imm < 16;
1001 }
1002 case GICXXPred_I64_Predicate_simm5_64b_tgt: {
1003 return (int64_t)Imm >= -16 && (int64_t)Imm < 16;
1004 }
1005 case GICXXPred_I64_Predicate_simm6_32b: {
1006 return Imm >= -32 && Imm < 32;
1007 }
1008 case GICXXPred_I64_Predicate_simm6s1: {
1009 return Imm >= -32 && Imm < 32;
1010 }
1011 case GICXXPred_I64_Predicate_simm8_32b: {
1012 return Imm >= -128 && Imm < 128;
1013 }
1014 case GICXXPred_I64_Predicate_simm8_64b: {
1015 return Imm >= -128 && Imm < 128;
1016 }
1017 case GICXXPred_I64_Predicate_simm9: {
1018 return Imm >= -256 && Imm < 256;
1019 }
1020 case GICXXPred_I64_Predicate_sme_elm_idx0_0: {
1021
1022 return ((uint32_t)Imm) == 0;
1023
1024 }
1025 case GICXXPred_I64_Predicate_sme_elm_idx0_1: {
1026
1027 return ((uint32_t)Imm) <= 1;
1028
1029 }
1030 case GICXXPred_I64_Predicate_sme_elm_idx0_3: {
1031
1032 return ((uint32_t)Imm) <= 3;
1033
1034 }
1035 case GICXXPred_I64_Predicate_sme_elm_idx0_7: {
1036
1037 return ((uint32_t)Imm) <= 7;
1038
1039 }
1040 case GICXXPred_I64_Predicate_sme_elm_idx0_15: {
1041
1042 return ((uint32_t)Imm) <= 15;
1043
1044 }
1045 case GICXXPred_I64_Predicate_svcr_op: {
1046
1047 return AArch64SVCR::lookupSVCRByEncoding(Imm) != nullptr;
1048
1049 }
1050 case GICXXPred_I64_Predicate_sve_elm_idx_extdup_b: {
1051 return ((uint64_t)Imm) < 64;
1052 }
1053 case GICXXPred_I64_Predicate_sve_elm_idx_extdup_b_timm: {
1054 return ((uint64_t)Imm) < 64;
1055 }
1056 case GICXXPred_I64_Predicate_sve_elm_idx_extdup_d: {
1057 return ((uint64_t)Imm) < 8;
1058 }
1059 case GICXXPred_I64_Predicate_sve_elm_idx_extdup_d_timm: {
1060 return ((uint64_t)Imm) < 8;
1061 }
1062 case GICXXPred_I64_Predicate_sve_elm_idx_extdup_h: {
1063 return ((uint64_t)Imm) < 32;
1064 }
1065 case GICXXPred_I64_Predicate_sve_elm_idx_extdup_h_timm: {
1066 return ((uint64_t)Imm) < 32;
1067 }
1068 case GICXXPred_I64_Predicate_sve_elm_idx_extdup_q: {
1069 return ((uint64_t)Imm) < 4;
1070 }
1071 case GICXXPred_I64_Predicate_sve_elm_idx_extdup_q_timm: {
1072 return ((uint64_t)Imm) < 4;
1073 }
1074 case GICXXPred_I64_Predicate_sve_elm_idx_extdup_s: {
1075 return ((uint64_t)Imm) < 16;
1076 }
1077 case GICXXPred_I64_Predicate_sve_elm_idx_extdup_s_timm: {
1078 return ((uint64_t)Imm) < 16;
1079 }
1080 case GICXXPred_I64_Predicate_sve_incdec_imm: {
1081
1082 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
1083
1084 }
1085 case GICXXPred_I64_Predicate_sve_pred_enum: {
1086
1087 return (((uint32_t)Imm) < 32);
1088
1089 }
1090 case GICXXPred_I64_Predicate_sve_prfop: {
1091
1092 return (((uint32_t)Imm) <= 15);
1093
1094 }
1095 case GICXXPred_I64_Predicate_sve_vec_len_specifier_enum: {
1096
1097 return (((uint32_t)Imm) < 2);
1098
1099 }
1100 case GICXXPred_I64_Predicate_tbz_imm0_31_diag: {
1101
1102 return (((uint32_t)Imm) < 32);
1103
1104 }
1105 case GICXXPred_I64_Predicate_tbz_imm0_31_nodiag: {
1106
1107 return (((uint32_t)Imm) < 32);
1108
1109 }
1110 case GICXXPred_I64_Predicate_tbz_imm32_63: {
1111
1112 return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64);
1113
1114 }
1115 case GICXXPred_I64_Predicate_timm0_1: {
1116
1117 return ((uint64_t)Imm) < 2;
1118
1119 }
1120 case GICXXPred_I64_Predicate_timm0_31: {
1121
1122 return ((uint64_t)Imm) < 32;
1123
1124 }
1125 case GICXXPred_I64_Predicate_timm0_63: {
1126
1127 return ((uint64_t)Imm) < 64;
1128
1129 }
1130 case GICXXPred_I64_Predicate_timm32_0_0: {
1131
1132 return ((uint32_t)Imm) == 0;
1133
1134 }
1135 case GICXXPred_I64_Predicate_timm32_0_1: {
1136
1137 return ((uint32_t)Imm) < 2;
1138
1139 }
1140 case GICXXPred_I64_Predicate_timm32_0_3: {
1141
1142 return ((uint32_t)Imm) < 4;
1143
1144 }
1145 case GICXXPred_I64_Predicate_timm32_0_7: {
1146
1147 return ((uint32_t)Imm) < 8;
1148
1149 }
1150 case GICXXPred_I64_Predicate_timm32_0_15: {
1151
1152 return ((uint32_t)Imm) < 16;
1153
1154 }
1155 case GICXXPred_I64_Predicate_timm32_0_31: {
1156
1157 return ((uint32_t)Imm) < 32;
1158
1159 }
1160 case GICXXPred_I64_Predicate_timm32_0_255: {
1161
1162 return ((uint32_t)Imm) < 256;
1163
1164 }
1165 case GICXXPred_I64_Predicate_timm32_0_65535: {
1166
1167 return ((uint32_t)Imm) < 65536;
1168
1169 }
1170 case GICXXPred_I64_Predicate_timm32_1_1: {
1171
1172 return ((uint32_t)Imm) == 1;
1173
1174 }
1175 case GICXXPred_I64_Predicate_timm32_1_3: {
1176
1177 return ((uint32_t)Imm) > 0 && ((uint32_t)Imm) < 4;
1178
1179 }
1180 case GICXXPred_I64_Predicate_timm32_1_7: {
1181
1182 return ((uint32_t)Imm) > 0 && ((uint32_t)Imm) < 8;
1183
1184 }
1185 case GICXXPred_I64_Predicate_timm64_0_65535: {
1186
1187 return ((uint64_t)Imm) < 65536;
1188
1189 }
1190 case GICXXPred_I64_Predicate_tuimm5s2: {
1191 return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0);
1192 }
1193 case GICXXPred_I64_Predicate_tuimm5s4: {
1194 return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0);
1195 }
1196 case GICXXPred_I64_Predicate_tuimm5s8: {
1197 return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0);
1198 }
1199 case GICXXPred_I64_Predicate_tvecshiftL8: {
1200
1201 return (((uint32_t)Imm) < 8);
1202
1203 }
1204 case GICXXPred_I64_Predicate_tvecshiftL16: {
1205
1206 return (((uint32_t)Imm) < 16);
1207
1208 }
1209 case GICXXPred_I64_Predicate_tvecshiftL32: {
1210
1211 return (((uint32_t)Imm) < 32);
1212
1213 }
1214 case GICXXPred_I64_Predicate_tvecshiftL64: {
1215
1216 return (((uint32_t)Imm) < 64);
1217
1218 }
1219 case GICXXPred_I64_Predicate_tvecshiftR8: {
1220
1221 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
1222
1223 }
1224 case GICXXPred_I64_Predicate_tvecshiftR16: {
1225
1226 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
1227
1228 }
1229 case GICXXPred_I64_Predicate_tvecshiftR32: {
1230
1231 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
1232
1233 }
1234 case GICXXPred_I64_Predicate_tvecshiftR64: {
1235
1236 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
1237
1238 }
1239 case GICXXPred_I64_Predicate_ubsan_trap_imm: {
1240
1241 return isUInt<8>(Imm);
1242
1243 }
1244 case GICXXPred_I64_Predicate_uimm0s2range: {
1245 return Imm == 0;
1246 }
1247 case GICXXPred_I64_Predicate_uimm0s4range: {
1248 return Imm == 0;
1249 }
1250 case GICXXPred_I64_Predicate_uimm1s2range: {
1251 return Imm >= 0 && Imm <= 2 && ((Imm % 2) == 0);
1252 }
1253 case GICXXPred_I64_Predicate_uimm1s4range: {
1254 return Imm >= 0 && Imm <= 4 && ((Imm % 4) == 0);
1255 }
1256 case GICXXPred_I64_Predicate_uimm2s2range: {
1257 return Imm >= 0 && Imm <= 6 && ((Imm % 2) == 0);
1258 }
1259 case GICXXPred_I64_Predicate_uimm2s4range: {
1260 return Imm >= 0 && Imm <= 12 && ((Imm % 4) == 0);
1261 }
1262 case GICXXPred_I64_Predicate_uimm3s2range: {
1263 return Imm >= 0 && Imm <= 14 && ((Imm % 2) == 0);
1264 }
1265 case GICXXPred_I64_Predicate_uimm3s8: {
1266 return Imm >= 0 && Imm <= 56 && ((Imm % 8) == 0);
1267 }
1268 case GICXXPred_I64_Predicate_uimm5s2: {
1269 return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0);
1270 }
1271 case GICXXPred_I64_Predicate_uimm5s4: {
1272 return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0);
1273 }
1274 case GICXXPred_I64_Predicate_uimm5s8: {
1275 return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0);
1276 }
1277 case GICXXPred_I64_Predicate_uimm6: {
1278 return Imm >= 0 && Imm < 64;
1279 }
1280 case GICXXPred_I64_Predicate_uimm6s1: {
1281 return Imm >= 0 && Imm < 64;
1282 }
1283 case GICXXPred_I64_Predicate_uimm6s2: {
1284 return Imm >= 0 && Imm < (64*2) && ((Imm % 2) == 0);
1285 }
1286 case GICXXPred_I64_Predicate_uimm6s4: {
1287 return Imm >= 0 && Imm < (64*4) && ((Imm % 4) == 0);
1288 }
1289 case GICXXPred_I64_Predicate_uimm6s8: {
1290 return Imm >= 0 && Imm < (64*8) && ((Imm % 8) == 0);
1291 }
1292 case GICXXPred_I64_Predicate_uimm6s16: {
1293 return Imm >= 0 && Imm < (64*16) && ((Imm % 16) == 0);
1294 }
1295 case GICXXPred_I64_Predicate_uimm8_32b: {
1296 return Imm >= 0 && Imm < 256;
1297 }
1298 case GICXXPred_I64_Predicate_uimm8_64b: {
1299 return Imm >= 0 && Imm < 256;
1300 }
1301 case GICXXPred_I64_Predicate_uimm16: {
1302 return Imm >= 0 && Imm < 65536;
1303 }
1304 case GICXXPred_I64_Predicate_vecshiftL8: {
1305
1306 return (((uint32_t)Imm) < 8);
1307
1308 }
1309 case GICXXPred_I64_Predicate_vecshiftL16: {
1310
1311 return (((uint32_t)Imm) < 16);
1312
1313 }
1314 case GICXXPred_I64_Predicate_vecshiftL32: {
1315
1316 return (((uint32_t)Imm) < 32);
1317
1318 }
1319 case GICXXPred_I64_Predicate_vecshiftL64: {
1320
1321 return (((uint32_t)Imm) < 64);
1322
1323 }
1324 case GICXXPred_I64_Predicate_vecshiftR8: {
1325
1326 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
1327
1328 }
1329 case GICXXPred_I64_Predicate_vecshiftR16: {
1330
1331 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
1332
1333 }
1334 case GICXXPred_I64_Predicate_vecshiftR16Narrow: {
1335
1336 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
1337
1338 }
1339 case GICXXPred_I64_Predicate_vecshiftR32: {
1340
1341 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
1342
1343 }
1344 case GICXXPred_I64_Predicate_vecshiftR32Narrow: {
1345
1346 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
1347
1348 }
1349 case GICXXPred_I64_Predicate_vecshiftR64: {
1350
1351 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
1352
1353 }
1354 case GICXXPred_I64_Predicate_vecshiftR64Narrow: {
1355
1356 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
1357
1358 }
1359 }
1360 llvm_unreachable("Unknown predicate");
1361 return false;
1362}
1363// PatFrag predicates.
1364enum {
1365 GICXXPred_APFloat_Predicate_fpimm0 = GICXXPred_Invalid + 1,
1366 GICXXPred_APFloat_Predicate_fpimm16,
1367 GICXXPred_APFloat_Predicate_fpimm32,
1368 GICXXPred_APFloat_Predicate_fpimm32SIMDModImmType4,
1369 GICXXPred_APFloat_Predicate_fpimm64,
1370 GICXXPred_APFloat_Predicate_fpimm_half,
1371 GICXXPred_APFloat_Predicate_fpimm_minus0,
1372 GICXXPred_APFloat_Predicate_fpimm_one,
1373 GICXXPred_APFloat_Predicate_fpimm_two,
1374 GICXXPred_APFloat_Predicate_fpimmbf16,
1375 GICXXPred_APFloat_Predicate_simdimmtype10,
1376};
1377bool AArch64InstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
1378 switch (PredicateID) {
1379 case GICXXPred_APFloat_Predicate_fpimm0: {
1380
1381 return Imm.isExactlyValue(+0.0);
1382
1383 }
1384 case GICXXPred_APFloat_Predicate_fpimm16: {
1385
1386 return AArch64_AM::getFP16Imm(Imm) != -1;
1387
1388 }
1389 case GICXXPred_APFloat_Predicate_fpimm32: {
1390
1391 return AArch64_AM::getFP32Imm(Imm) != -1;
1392
1393 }
1394 case GICXXPred_APFloat_Predicate_fpimm32SIMDModImmType4: {
1395
1396 uint64_t Enc = Imm.bitcastToAPInt().getZExtValue();
1397 return Enc != 0 && AArch64_AM::isAdvSIMDModImmType4(Enc << 32 | Enc);
1398
1399 llvm_unreachable("fpimm32SIMDModImmType4 should have returned");
1400 }
1401 case GICXXPred_APFloat_Predicate_fpimm64: {
1402
1403 return AArch64_AM::getFP64Imm(Imm) != -1;
1404
1405 }
1406 case GICXXPred_APFloat_Predicate_fpimm_half: {
1407
1408 return Imm.isExactlyValue(+0.5);
1409
1410 }
1411 case GICXXPred_APFloat_Predicate_fpimm_minus0: {
1412
1413 return Imm.isExactlyValue(-0.0);
1414
1415 }
1416 case GICXXPred_APFloat_Predicate_fpimm_one: {
1417
1418 return Imm.isExactlyValue(+1.0);
1419
1420 }
1421 case GICXXPred_APFloat_Predicate_fpimm_two: {
1422
1423 return Imm.isExactlyValue(+2.0);
1424
1425 }
1426 case GICXXPred_APFloat_Predicate_fpimmbf16: {
1427
1428 return AArch64_AM::getFP16Imm(Imm) != -1;
1429
1430 }
1431 case GICXXPred_APFloat_Predicate_simdimmtype10: {
1432
1433 return AArch64_AM::isAdvSIMDModImmType10(
1434 Imm.bitcastToAPInt().getZExtValue());
1435
1436 }
1437 }
1438 llvm_unreachable("Unknown predicate");
1439 return false;
1440}
1441// PatFrag predicates.
1442enum {
1443 GICXXPred_APInt_Predicate_logical_imm32 = GICXXPred_Invalid + 1,
1444 GICXXPred_APInt_Predicate_logical_imm64,
1445};
1446bool AArch64InstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
1447 switch (PredicateID) {
1448 case GICXXPred_APInt_Predicate_logical_imm32: {
1449
1450 return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 32);
1451
1452 }
1453 case GICXXPred_APInt_Predicate_logical_imm64: {
1454
1455 return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 64);
1456
1457 }
1458 }
1459 llvm_unreachable("Unknown predicate");
1460 return false;
1461}
1462bool AArch64InstructionSelector::testSimplePredicate(unsigned) const {
1463 llvm_unreachable("AArch64InstructionSelector does not support simple predicates!");
1464 return false;
1465}
1466// Custom renderers.
1467enum {
1468 GICR_Invalid,
1469 GICR_renderFPImm16,
1470 GICR_renderFPImm32,
1471 GICR_renderFPImm32SIMDModImmType4,
1472 GICR_renderFPImm64,
1473 GICR_renderLogicalImm32,
1474 GICR_renderLogicalImm64,
1475 GICR_renderTruncImm,
1476 GICR_renderUbsanTrap,
1477};
1478AArch64InstructionSelector::CustomRendererFn
1479AArch64InstructionSelector::CustomRenderers[] = {
1480 nullptr, // GICR_Invalid
1481 &AArch64InstructionSelector::renderFPImm16,
1482 &AArch64InstructionSelector::renderFPImm32,
1483 &AArch64InstructionSelector::renderFPImm32SIMDModImmType4,
1484 &AArch64InstructionSelector::renderFPImm64,
1485 &AArch64InstructionSelector::renderLogicalImm32,
1486 &AArch64InstructionSelector::renderLogicalImm64,
1487 &AArch64InstructionSelector::renderTruncImm,
1488 &AArch64InstructionSelector::renderUbsanTrap,
1489};
1490
1491bool AArch64InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
1492 const PredicateBitset AvailableFeatures = getAvailableFeatures();
1493 MachineIRBuilder B(I);
1494 State.MIs.clear();
1495 State.MIs.push_back(&I);
1496
1497 if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
1498 return true;
1499 }
1500
1501 return false;
1502}
1503
1504bool AArch64InstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
1505 llvm_unreachable("AArch64InstructionSelector does not support custom C++ actions!");
1506}
1507#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
1508#define GIMT_Encode2(Val) uint8_t(Val), uint8_t((uint16_t)Val >> 8)
1509#define GIMT_Encode4(Val) uint8_t(Val), uint8_t((uint32_t)Val >> 8), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 24)
1510#define GIMT_Encode8(Val) uint8_t(Val), uint8_t((uint64_t)Val >> 8), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 56)
1511#else
1512#define GIMT_Encode2(Val) uint8_t((uint16_t)Val >> 8), uint8_t(Val)
1513#define GIMT_Encode4(Val) uint8_t((uint32_t)Val >> 24), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 8), uint8_t(Val)
1514#define GIMT_Encode8(Val) uint8_t((uint64_t)Val >> 56), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 8), uint8_t(Val)
1515#endif
1516const uint8_t *AArch64InstructionSelector::getMatchTable() const {
1517 constexpr static uint8_t MatchTable0[] = {
1518 GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(51), GIMT_Encode2(802), /*)*//*default:*//*Label 146*/ GIMT_Encode4(357622),
1519 /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(3014),
1520 /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(22013),
1521 /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(29003),
1522 /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(30375),
1523 /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(30457), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1524 /*TargetOpcode::G_AND*//*Label 5*/ GIMT_Encode4(30539),
1525 /*TargetOpcode::G_OR*//*Label 6*/ GIMT_Encode4(34221),
1526 /*TargetOpcode::G_XOR*//*Label 7*/ GIMT_Encode4(46268), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1527 /*TargetOpcode::G_CONCAT_VECTORS*//*Label 8*/ GIMT_Encode4(50459), GIMT_Encode4(0), GIMT_Encode4(0),
1528 /*TargetOpcode::G_BITCAST*//*Label 9*/ GIMT_Encode4(60840), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1529 /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 10*/ GIMT_Encode4(72596),
1530 /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 11*/ GIMT_Encode4(74019),
1531 /*TargetOpcode::G_INTRINSIC_LRINT*//*Label 12*/ GIMT_Encode4(75442),
1532 /*TargetOpcode::G_INTRINSIC_LLRINT*//*Label 13*/ GIMT_Encode4(75710),
1533 /*TargetOpcode::G_INTRINSIC_ROUNDEVEN*//*Label 14*/ GIMT_Encode4(75860),
1534 /*TargetOpcode::G_READCYCLECOUNTER*//*Label 15*/ GIMT_Encode4(77283), GIMT_Encode4(0),
1535 /*TargetOpcode::G_LOAD*//*Label 16*/ GIMT_Encode4(77316),
1536 /*TargetOpcode::G_SEXTLOAD*//*Label 17*/ GIMT_Encode4(86382),
1537 /*TargetOpcode::G_ZEXTLOAD*//*Label 18*/ GIMT_Encode4(87474), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1538 /*TargetOpcode::G_STORE*//*Label 19*/ GIMT_Encode4(90488), GIMT_Encode4(0), GIMT_Encode4(0),
1539 /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 20*/ GIMT_Encode4(104565),
1540 /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 21*/ GIMT_Encode4(105916),
1541 /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 22*/ GIMT_Encode4(106908),
1542 /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 23*/ GIMT_Encode4(107900),
1543 /*TargetOpcode::G_ATOMICRMW_AND*//*Label 24*/ GIMT_Encode4(109392), GIMT_Encode4(0),
1544 /*TargetOpcode::G_ATOMICRMW_OR*//*Label 25*/ GIMT_Encode4(110884),
1545 /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 26*/ GIMT_Encode4(111876),
1546 /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 27*/ GIMT_Encode4(112868),
1547 /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 28*/ GIMT_Encode4(113860),
1548 /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 29*/ GIMT_Encode4(114852),
1549 /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 30*/ GIMT_Encode4(115844), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1550 /*TargetOpcode::G_FENCE*//*Label 31*/ GIMT_Encode4(116836), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1551 /*TargetOpcode::G_INTRINSIC*//*Label 32*/ GIMT_Encode4(116887),
1552 /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 33*/ GIMT_Encode4(221357), GIMT_Encode4(0), GIMT_Encode4(0),
1553 /*TargetOpcode::G_ANYEXT*//*Label 34*/ GIMT_Encode4(229185),
1554 /*TargetOpcode::G_TRUNC*//*Label 35*/ GIMT_Encode4(229475),
1555 /*TargetOpcode::G_CONSTANT*//*Label 36*/ GIMT_Encode4(230678),
1556 /*TargetOpcode::G_FCONSTANT*//*Label 37*/ GIMT_Encode4(230798), GIMT_Encode4(0), GIMT_Encode4(0),
1557 /*TargetOpcode::G_SEXT*//*Label 38*/ GIMT_Encode4(231087), GIMT_Encode4(0),
1558 /*TargetOpcode::G_ZEXT*//*Label 39*/ GIMT_Encode4(232985),
1559 /*TargetOpcode::G_SHL*//*Label 40*/ GIMT_Encode4(235764),
1560 /*TargetOpcode::G_LSHR*//*Label 41*/ GIMT_Encode4(236089),
1561 /*TargetOpcode::G_ASHR*//*Label 42*/ GIMT_Encode4(236482), GIMT_Encode4(0),
1562 /*TargetOpcode::G_FSHR*//*Label 43*/ GIMT_Encode4(236990),
1563 /*TargetOpcode::G_ROTR*//*Label 44*/ GIMT_Encode4(237120), GIMT_Encode4(0),
1564 /*TargetOpcode::G_ICMP*//*Label 45*/ GIMT_Encode4(237613), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1565 /*TargetOpcode::G_SELECT*//*Label 46*/ GIMT_Encode4(242189), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1566 /*TargetOpcode::G_UMULH*//*Label 47*/ GIMT_Encode4(242675),
1567 /*TargetOpcode::G_SMULH*//*Label 48*/ GIMT_Encode4(243159),
1568 /*TargetOpcode::G_UADDSAT*//*Label 49*/ GIMT_Encode4(243643),
1569 /*TargetOpcode::G_SADDSAT*//*Label 50*/ GIMT_Encode4(244073),
1570 /*TargetOpcode::G_USUBSAT*//*Label 51*/ GIMT_Encode4(244503),
1571 /*TargetOpcode::G_SSUBSAT*//*Label 52*/ GIMT_Encode4(244933), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1572 /*TargetOpcode::G_FADD*//*Label 53*/ GIMT_Encode4(245363),
1573 /*TargetOpcode::G_FSUB*//*Label 54*/ GIMT_Encode4(248037),
1574 /*TargetOpcode::G_FMUL*//*Label 55*/ GIMT_Encode4(250073),
1575 /*TargetOpcode::G_FMA*//*Label 56*/ GIMT_Encode4(255139), GIMT_Encode4(0),
1576 /*TargetOpcode::G_FDIV*//*Label 57*/ GIMT_Encode4(267389), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1577 /*TargetOpcode::G_FNEG*//*Label 58*/ GIMT_Encode4(269282),
1578 /*TargetOpcode::G_FPEXT*//*Label 59*/ GIMT_Encode4(272108),
1579 /*TargetOpcode::G_FPTRUNC*//*Label 60*/ GIMT_Encode4(272372),
1580 /*TargetOpcode::G_FPTOSI*//*Label 61*/ GIMT_Encode4(272700),
1581 /*TargetOpcode::G_FPTOUI*//*Label 62*/ GIMT_Encode4(273763),
1582 /*TargetOpcode::G_SITOFP*//*Label 63*/ GIMT_Encode4(274826),
1583 /*TargetOpcode::G_UITOFP*//*Label 64*/ GIMT_Encode4(279000),
1584 /*TargetOpcode::G_FABS*//*Label 65*/ GIMT_Encode4(282655), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1585 /*TargetOpcode::G_FMINNUM*//*Label 66*/ GIMT_Encode4(283725),
1586 /*TargetOpcode::G_FMAXNUM*//*Label 67*/ GIMT_Encode4(284103), GIMT_Encode4(0), GIMT_Encode4(0),
1587 /*TargetOpcode::G_FMINIMUM*//*Label 68*/ GIMT_Encode4(284481),
1588 /*TargetOpcode::G_FMAXIMUM*//*Label 69*/ GIMT_Encode4(284859), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1589 /*TargetOpcode::G_SMIN*//*Label 70*/ GIMT_Encode4(285237),
1590 /*TargetOpcode::G_SMAX*//*Label 71*/ GIMT_Encode4(285641),
1591 /*TargetOpcode::G_UMIN*//*Label 72*/ GIMT_Encode4(286045),
1592 /*TargetOpcode::G_UMAX*//*Label 73*/ GIMT_Encode4(286449),
1593 /*TargetOpcode::G_ABS*//*Label 74*/ GIMT_Encode4(286853),
1594 /*TargetOpcode::G_LROUND*//*Label 75*/ GIMT_Encode4(287668),
1595 /*TargetOpcode::G_LLROUND*//*Label 76*/ GIMT_Encode4(287834),
1596 /*TargetOpcode::G_BR*//*Label 77*/ GIMT_Encode4(287933), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1597 /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 78*/ GIMT_Encode4(287949),
1598 /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 79*/ GIMT_Encode4(303316), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1599 /*TargetOpcode::G_CTTZ*//*Label 80*/ GIMT_Encode4(306867), GIMT_Encode4(0),
1600 /*TargetOpcode::G_CTLZ*//*Label 81*/ GIMT_Encode4(307019), GIMT_Encode4(0),
1601 /*TargetOpcode::G_CTPOP*//*Label 82*/ GIMT_Encode4(307693),
1602 /*TargetOpcode::G_BSWAP*//*Label 83*/ GIMT_Encode4(307853),
1603 /*TargetOpcode::G_BITREVERSE*//*Label 84*/ GIMT_Encode4(308167),
1604 /*TargetOpcode::G_FCEIL*//*Label 85*/ GIMT_Encode4(308321), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1605 /*TargetOpcode::G_FSQRT*//*Label 86*/ GIMT_Encode4(309744),
1606 /*TargetOpcode::G_FFLOOR*//*Label 87*/ GIMT_Encode4(310044),
1607 /*TargetOpcode::G_FRINT*//*Label 88*/ GIMT_Encode4(311467),
1608 /*TargetOpcode::G_FNEARBYINT*//*Label 89*/ GIMT_Encode4(312890), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1609 /*TargetOpcode::G_STRICT_FADD*//*Label 90*/ GIMT_Encode4(314313),
1610 /*TargetOpcode::G_STRICT_FSUB*//*Label 91*/ GIMT_Encode4(316716),
1611 /*TargetOpcode::G_STRICT_FMUL*//*Label 92*/ GIMT_Encode4(318609),
1612 /*TargetOpcode::G_STRICT_FDIV*//*Label 93*/ GIMT_Encode4(323280), GIMT_Encode4(0),
1613 /*TargetOpcode::G_STRICT_FMA*//*Label 94*/ GIMT_Encode4(325173),
1614 /*TargetOpcode::G_STRICT_FSQRT*//*Label 95*/ GIMT_Encode4(336757), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1615 /*TargetOpcode::G_TRAP*//*Label 96*/ GIMT_Encode4(337057),
1616 /*TargetOpcode::G_DEBUGTRAP*//*Label 97*/ GIMT_Encode4(337071),
1617 /*TargetOpcode::G_UBSANTRAP*//*Label 98*/ GIMT_Encode4(337092), GIMT_Encode4(0), GIMT_Encode4(0),
1618 /*TargetOpcode::G_VECREDUCE_FADD*//*Label 99*/ GIMT_Encode4(337117), GIMT_Encode4(0),
1619 /*TargetOpcode::G_VECREDUCE_FMAX*//*Label 100*/ GIMT_Encode4(337427),
1620 /*TargetOpcode::G_VECREDUCE_FMIN*//*Label 101*/ GIMT_Encode4(337598),
1621 /*TargetOpcode::G_VECREDUCE_FMAXIMUM*//*Label 102*/ GIMT_Encode4(337769),
1622 /*TargetOpcode::G_VECREDUCE_FMINIMUM*//*Label 103*/ GIMT_Encode4(337940),
1623 /*TargetOpcode::G_VECREDUCE_ADD*//*Label 104*/ GIMT_Encode4(338111), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1624 /*TargetOpcode::G_VECREDUCE_SMAX*//*Label 105*/ GIMT_Encode4(339240),
1625 /*TargetOpcode::G_VECREDUCE_SMIN*//*Label 106*/ GIMT_Encode4(339443),
1626 /*TargetOpcode::G_VECREDUCE_UMAX*//*Label 107*/ GIMT_Encode4(339646),
1627 /*TargetOpcode::G_VECREDUCE_UMIN*//*Label 108*/ GIMT_Encode4(339849), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1628 /*AArch64::G_AARCH64_PREFETCH*//*Label 109*/ GIMT_Encode4(340052), GIMT_Encode4(0),
1629 /*AArch64::G_BSP*//*Label 110*/ GIMT_Encode4(340192),
1630 /*AArch64::G_DUP*//*Label 111*/ GIMT_Encode4(340732),
1631 /*AArch64::G_DUPLANE16*//*Label 112*/ GIMT_Encode4(342823),
1632 /*AArch64::G_DUPLANE32*//*Label 113*/ GIMT_Encode4(343144),
1633 /*AArch64::G_DUPLANE64*//*Label 114*/ GIMT_Encode4(343399),
1634 /*AArch64::G_DUPLANE8*//*Label 115*/ GIMT_Encode4(343545),
1635 /*AArch64::G_EXT*//*Label 116*/ GIMT_Encode4(343724),
1636 /*AArch64::G_FCMEQ*//*Label 117*/ GIMT_Encode4(344595),
1637 /*AArch64::G_FCMEQZ*//*Label 118*/ GIMT_Encode4(344934),
1638 /*AArch64::G_FCMGE*//*Label 119*/ GIMT_Encode4(345164),
1639 /*AArch64::G_FCMGEZ*//*Label 120*/ GIMT_Encode4(345828),
1640 /*AArch64::G_FCMGT*//*Label 121*/ GIMT_Encode4(346058),
1641 /*AArch64::G_FCMGTZ*//*Label 122*/ GIMT_Encode4(346722),
1642 /*AArch64::G_FCMLEZ*//*Label 123*/ GIMT_Encode4(346952),
1643 /*AArch64::G_FCMLTZ*//*Label 124*/ GIMT_Encode4(347182),
1644 /*AArch64::G_REV16*//*Label 125*/ GIMT_Encode4(347412),
1645 /*AArch64::G_REV32*//*Label 126*/ GIMT_Encode4(347490),
1646 /*AArch64::G_REV64*//*Label 127*/ GIMT_Encode4(347690),
1647 /*AArch64::G_SADDLP*//*Label 128*/ GIMT_Encode4(347988),
1648 /*AArch64::G_SADDLV*//*Label 129*/ GIMT_Encode4(348194),
1649 /*AArch64::G_SDOT*//*Label 130*/ GIMT_Encode4(348515),
1650 /*AArch64::G_SITOF*//*Label 131*/ GIMT_Encode4(348885),
1651 /*AArch64::G_SMULL*//*Label 132*/ GIMT_Encode4(349002),
1652 /*AArch64::G_TRN1*//*Label 133*/ GIMT_Encode4(349523),
1653 /*AArch64::G_TRN2*//*Label 134*/ GIMT_Encode4(350348),
1654 /*AArch64::G_UADDLP*//*Label 135*/ GIMT_Encode4(351173),
1655 /*AArch64::G_UADDLV*//*Label 136*/ GIMT_Encode4(351379),
1656 /*AArch64::G_UDOT*//*Label 137*/ GIMT_Encode4(352160),
1657 /*AArch64::G_UITOF*//*Label 138*/ GIMT_Encode4(352530),
1658 /*AArch64::G_UMULL*//*Label 139*/ GIMT_Encode4(352647),
1659 /*AArch64::G_UZP1*//*Label 140*/ GIMT_Encode4(353168),
1660 /*AArch64::G_UZP2*//*Label 141*/ GIMT_Encode4(353993),
1661 /*AArch64::G_VASHR*//*Label 142*/ GIMT_Encode4(354818),
1662 /*AArch64::G_VLSHR*//*Label 143*/ GIMT_Encode4(355516),
1663 /*AArch64::G_ZIP1*//*Label 144*/ GIMT_Encode4(355972),
1664 /*AArch64::G_ZIP2*//*Label 145*/ GIMT_Encode4(356797),
1665 // Label 0: @3014
1666 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(24), /*)*//*default:*//*Label 160*/ GIMT_Encode4(22012),
1667 /*GILLT_s32*//*Label 147*/ GIMT_Encode4(3113),
1668 /*GILLT_s64*//*Label 148*/ GIMT_Encode4(4636), GIMT_Encode4(0),
1669 /*GILLT_v2s32*//*Label 149*/ GIMT_Encode4(7230),
1670 /*GILLT_v2s64*//*Label 150*/ GIMT_Encode4(8230),
1671 /*GILLT_v4s16*//*Label 151*/ GIMT_Encode4(12128),
1672 /*GILLT_v4s32*//*Label 152*/ GIMT_Encode4(13128),
1673 /*GILLT_v8s8*//*Label 153*/ GIMT_Encode4(17302),
1674 /*GILLT_v8s16*//*Label 154*/ GIMT_Encode4(17886),
1675 /*GILLT_v16s8*//*Label 155*/ GIMT_Encode4(21324), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1676 /*GILLT_nxv2s64*//*Label 156*/ GIMT_Encode4(21908), GIMT_Encode4(0), GIMT_Encode4(0),
1677 /*GILLT_nxv4s32*//*Label 157*/ GIMT_Encode4(21934), GIMT_Encode4(0),
1678 /*GILLT_nxv8s16*//*Label 158*/ GIMT_Encode4(21960), GIMT_Encode4(0),
1679 /*GILLT_nxv16s8*//*Label 159*/ GIMT_Encode4(21986),
1680 // Label 147: @3113
1681 GIM_Try, /*On fail goto*//*Label 161*/ GIMT_Encode4(4635),
1682 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1683 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1684 GIM_Try, /*On fail goto*//*Label 162*/ GIMT_Encode4(3157), // Rule ID 12450 //
1685 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
1686 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
1687 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_addsub_shifted_imm32),
1688 // (add:{ *:[i32] } addsub_shifted_imm32:{ *:[i32] }:$imm, GPR32sp:{ *:[i32] }:$Rn) => (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
1689 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWri),
1690 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1691 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1692 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
1693 GIR_RootConstrainSelectedInstOperands,
1694 // GIR_Coverage, 12450,
1695 GIR_EraseRootFromParent_Done,
1696 // Label 162: @3157
1697 GIM_Try, /*On fail goto*//*Label 163*/ GIMT_Encode4(3309), // Rule ID 12877 //
1698 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
1699 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
1700 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1701 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
1702 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1703 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1704 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
1705 GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
1706 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
1707 // MIs[2] pattern
1708 GIM_CheckIsImm, /*MI*/2, /*Op*/2,
1709 GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
1710 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
1711 GIM_CheckIsSafeToFold, /*NumInsns*/2,
1712 // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1148:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)), GPR32:{ *:[i32] }:$Rdn) => (EXTRACT_SUBREG:{ *:[i32] } (INCB_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
1713 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
1714 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
1715 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
1716 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
1717 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1718 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
1719 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
1720 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1721 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
1722 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rdn
1723 GIR_AddImm8, /*InsnID*/2, /*Imm*/16,
1724 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
1725 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
1726 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
1727 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCB_XPiI),
1728 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1729 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
1730 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
1731 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
1732 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1733 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
1734 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
1735 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
1736 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
1737 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
1738 // GIR_Coverage, 12877,
1739 GIR_EraseRootFromParent_Done,
1740 // Label 163: @3309
1741 GIM_Try, /*On fail goto*//*Label 164*/ GIMT_Encode4(3461), // Rule ID 14745 //
1742 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
1743 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
1744 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1745 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
1746 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1747 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1748 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
1749 GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
1750 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
1751 // MIs[2] pattern
1752 GIM_CheckIsImm, /*MI*/2, /*Op*/2,
1753 GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
1754 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
1755 GIM_CheckIsSafeToFold, /*NumInsns*/2,
1756 // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1150:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)), GPR32:{ *:[i32] }:$Rdn) => (EXTRACT_SUBREG:{ *:[i32] } (INCH_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
1757 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
1758 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
1759 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
1760 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
1761 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1762 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
1763 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
1764 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1765 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
1766 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rdn
1767 GIR_AddImm8, /*InsnID*/2, /*Imm*/16,
1768 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
1769 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
1770 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
1771 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCH_XPiI),
1772 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1773 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
1774 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
1775 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
1776 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1777 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
1778 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
1779 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
1780 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
1781 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
1782 // GIR_Coverage, 14745,
1783 GIR_EraseRootFromParent_Done,
1784 // Label 164: @3461
1785 GIM_Try, /*On fail goto*//*Label 165*/ GIMT_Encode4(3613), // Rule ID 14757 //
1786 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
1787 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
1788 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1789 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
1790 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1791 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1792 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
1793 GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
1794 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
1795 // MIs[2] pattern
1796 GIM_CheckIsImm, /*MI*/2, /*Op*/2,
1797 GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
1798 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
1799 GIM_CheckIsSafeToFold, /*NumInsns*/2,
1800 // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1156:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)), GPR32:{ *:[i32] }:$Rdn) => (EXTRACT_SUBREG:{ *:[i32] } (INCW_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
1801 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
1802 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
1803 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
1804 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
1805 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1806 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
1807 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
1808 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1809 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
1810 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rdn
1811 GIR_AddImm8, /*InsnID*/2, /*Imm*/16,
1812 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
1813 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
1814 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
1815 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCW_XPiI),
1816 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1817 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
1818 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
1819 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
1820 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1821 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
1822 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
1823 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
1824 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
1825 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
1826 // GIR_Coverage, 14757,
1827 GIR_EraseRootFromParent_Done,
1828 // Label 165: @3613
1829 GIM_Try, /*On fail goto*//*Label 166*/ GIMT_Encode4(3765), // Rule ID 14769 //
1830 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
1831 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
1832 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1833 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
1834 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1835 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1836 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
1837 GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
1838 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
1839 // MIs[2] pattern
1840 GIM_CheckIsImm, /*MI*/2, /*Op*/2,
1841 GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
1842 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
1843 GIM_CheckIsSafeToFold, /*NumInsns*/2,
1844 // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1149:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)), GPR32:{ *:[i32] }:$Rdn) => (EXTRACT_SUBREG:{ *:[i32] } (INCD_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
1845 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
1846 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
1847 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
1848 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
1849 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1850 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
1851 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
1852 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1853 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
1854 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rdn
1855 GIR_AddImm8, /*InsnID*/2, /*Imm*/16,
1856 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
1857 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
1858 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
1859 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCD_XPiI),
1860 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1861 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
1862 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
1863 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
1864 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1865 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
1866 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
1867 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
1868 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
1869 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
1870 // GIR_Coverage, 14769,
1871 GIR_EraseRootFromParent_Done,
1872 // Label 166: @3765
1873 GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(3798), // Rule ID 102 //
1874 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
1875 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
1876 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_addsub_shifted_imm32),
1877 // (add:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) => (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
1878 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWri),
1879 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1880 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1881 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
1882 GIR_RootConstrainSelectedInstOperands,
1883 // GIR_Coverage, 102,
1884 GIR_EraseRootFromParent_Done,
1885 // Label 167: @3798
1886 GIM_Try, /*On fail goto*//*Label 168*/ GIMT_Encode4(3950), // Rule ID 2555 //
1887 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
1888 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
1889 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
1890 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1891 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
1892 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1893 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1894 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
1895 GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
1896 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
1897 // MIs[2] pattern
1898 GIM_CheckIsImm, /*MI*/2, /*Op*/2,
1899 GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
1900 GIM_CheckIsSafeToFold, /*NumInsns*/2,
1901 // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1148:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))) => (EXTRACT_SUBREG:{ *:[i32] } (INCB_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
1902 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
1903 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
1904 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
1905 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
1906 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1907 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
1908 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
1909 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1910 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
1911 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
1912 GIR_AddImm8, /*InsnID*/2, /*Imm*/16,
1913 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
1914 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
1915 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
1916 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCB_XPiI),
1917 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1918 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
1919 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
1920 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
1921 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1922 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
1923 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
1924 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
1925 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
1926 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
1927 // GIR_Coverage, 2555,
1928 GIR_EraseRootFromParent_Done,
1929 // Label 168: @3950
1930 GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(4102), // Rule ID 9631 //
1931 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
1932 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
1933 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
1934 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1935 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
1936 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1937 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1938 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
1939 GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
1940 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
1941 // MIs[2] pattern
1942 GIM_CheckIsImm, /*MI*/2, /*Op*/2,
1943 GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
1944 GIM_CheckIsSafeToFold, /*NumInsns*/2,
1945 // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1150:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))) => (EXTRACT_SUBREG:{ *:[i32] } (INCH_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
1946 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
1947 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
1948 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
1949 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
1950 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1951 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
1952 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
1953 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1954 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
1955 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
1956 GIR_AddImm8, /*InsnID*/2, /*Imm*/16,
1957 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
1958 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
1959 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
1960 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCH_XPiI),
1961 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1962 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
1963 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
1964 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
1965 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
1966 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
1967 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
1968 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
1969 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
1970 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
1971 // GIR_Coverage, 9631,
1972 GIR_EraseRootFromParent_Done,
1973 // Label 169: @4102
1974 GIM_Try, /*On fail goto*//*Label 170*/ GIMT_Encode4(4254), // Rule ID 9643 //
1975 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
1976 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
1977 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
1978 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1979 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
1980 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
1981 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1982 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
1983 GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
1984 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
1985 // MIs[2] pattern
1986 GIM_CheckIsImm, /*MI*/2, /*Op*/2,
1987 GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
1988 GIM_CheckIsSafeToFold, /*NumInsns*/2,
1989 // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1156:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))) => (EXTRACT_SUBREG:{ *:[i32] } (INCW_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
1990 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
1991 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
1992 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
1993 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
1994 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1995 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
1996 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
1997 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
1998 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
1999 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
2000 GIR_AddImm8, /*InsnID*/2, /*Imm*/16,
2001 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
2002 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
2003 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
2004 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCW_XPiI),
2005 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
2006 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
2007 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
2008 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
2009 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
2010 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
2011 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
2012 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
2013 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
2014 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
2015 // GIR_Coverage, 9643,
2016 GIR_EraseRootFromParent_Done,
2017 // Label 170: @4254
2018 GIM_Try, /*On fail goto*//*Label 171*/ GIMT_Encode4(4406), // Rule ID 9655 //
2019 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
2020 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2021 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2022 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2023 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
2024 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2025 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2026 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2027 GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
2028 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
2029 // MIs[2] pattern
2030 GIM_CheckIsImm, /*MI*/2, /*Op*/2,
2031 GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
2032 GIM_CheckIsSafeToFold, /*NumInsns*/2,
2033 // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1149:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))) => (EXTRACT_SUBREG:{ *:[i32] } (INCD_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
2034 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
2035 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
2036 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
2037 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
2038 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
2039 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
2040 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
2041 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
2042 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
2043 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
2044 GIR_AddImm8, /*InsnID*/2, /*Imm*/16,
2045 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
2046 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
2047 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
2048 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCD_XPiI),
2049 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
2050 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
2051 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
2052 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
2053 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
2054 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
2055 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
2056 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
2057 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
2058 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
2059 // GIR_Coverage, 9655,
2060 GIR_EraseRootFromParent_Done,
2061 // Label 171: @4406
2062 GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(4439), // Rule ID 12454 //
2063 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
2064 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
2065 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_extended_reg32_i32),
2066 // (add:{ *:[i32] } arith_extended_reg32_i32:{ *:[i32] }:$Rm_and_extend, GPR32sp:{ *:[i32] }:$Rn) => (ADDWrx:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, arith_extended_reg32_i32:{ *:[i32] }:$Rm_and_extend)
2067 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWrx),
2068 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2069 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2070 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_extend
2071 GIR_RootConstrainSelectedInstOperands,
2072 // GIR_Coverage, 12454,
2073 GIR_EraseRootFromParent_Done,
2074 // Label 172: @4439
2075 GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(4475), // Rule ID 13017 //
2076 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2077 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2078 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_neg_addsub_shifted_imm32),
2079 // (add:{ *:[i32] } neg_addsub_shifted_imm32:{ *:[i32] }:$imm, GPR32:{ *:[i32] }:$Rn) => (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm)
2080 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSWri),
2081 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2082 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2083 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
2084 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
2085 GIR_RootConstrainSelectedInstOperands,
2086 // GIR_Coverage, 13017,
2087 GIR_EraseRootFromParent_Done,
2088 // Label 173: @4475
2089 GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(4508), // Rule ID 108 //
2090 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
2091 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
2092 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_extended_reg32_i32),
2093 // (add:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, arith_extended_reg32_i32:{ *:[i32] }:$Rm_and_extend) => (ADDWrx:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, arith_extended_reg32_i32:{ *:[i32] }:$Rm_and_extend)
2094 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWrx),
2095 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2096 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2097 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_extend
2098 GIR_RootConstrainSelectedInstOperands,
2099 // GIR_Coverage, 108,
2100 GIR_EraseRootFromParent_Done,
2101 // Label 174: @4508
2102 GIM_Try, /*On fail goto*//*Label 175*/ GIMT_Encode4(4544), // Rule ID 3790 //
2103 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2104 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2105 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_neg_addsub_shifted_imm32),
2106 // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm) => (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm)
2107 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSWri),
2108 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2109 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2110 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
2111 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
2112 GIR_RootConstrainSelectedInstOperands,
2113 // GIR_Coverage, 3790,
2114 GIR_EraseRootFromParent_Done,
2115 // Label 175: @4544
2116 GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(4577), // Rule ID 12452 //
2117 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2118 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2119 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg32),
2120 // (add:{ *:[i32] } arith_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn) => (ADDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
2121 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWrs),
2122 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2123 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2124 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
2125 GIR_RootConstrainSelectedInstOperands,
2126 // GIR_Coverage, 12452,
2127 GIR_EraseRootFromParent_Done,
2128 // Label 176: @4577
2129 GIM_Try, /*On fail goto*//*Label 177*/ GIMT_Encode4(4610), // Rule ID 106 //
2130 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2131 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2132 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg32),
2133 // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm_and_shift) => (ADDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
2134 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWrs),
2135 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2136 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2137 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
2138 GIR_RootConstrainSelectedInstOperands,
2139 // GIR_Coverage, 106,
2140 GIR_EraseRootFromParent_Done,
2141 // Label 177: @4610
2142 GIM_Try, /*On fail goto*//*Label 178*/ GIMT_Encode4(4634), // Rule ID 104 //
2143 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2144 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2145 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2146 // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (ADDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
2147 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDWrr),
2148 GIR_RootConstrainSelectedInstOperands,
2149 // GIR_Coverage, 104,
2150 GIR_Done,
2151 // Label 178: @4634
2152 GIM_Reject,
2153 // Label 161: @4635
2154 GIM_Reject,
2155 // Label 148: @4636
2156 GIM_Try, /*On fail goto*//*Label 179*/ GIMT_Encode4(7229),
2157 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2158 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2159 GIM_Try, /*On fail goto*//*Label 180*/ GIMT_Encode4(4715), // Rule ID 6602 //
2160 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2161 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2162 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
2163 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
2164 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2165 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
2166 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
2167 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2168 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
2169 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
2170 // MIs[2] Rn
2171 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
2172 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
2173 GIM_CheckIsSafeToFold, /*NumInsns*/2,
2174 // (add:{ *:[i64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] })) => (ADDPv2i64p:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn)
2175 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64p),
2176 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2177 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2178 GIR_RootConstrainSelectedInstOperands,
2179 // GIR_Coverage, 6602,
2180 GIR_EraseRootFromParent_Done,
2181 // Label 180: @4715
2182 GIM_Try, /*On fail goto*//*Label 181*/ GIMT_Encode4(4783), // Rule ID 13188 //
2183 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2184 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2185 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
2186 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
2187 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2188 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
2189 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
2190 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2191 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
2192 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
2193 // MIs[2] Rn
2194 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
2195 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
2196 GIM_CheckIsSafeToFold, /*NumInsns*/2,
2197 // (add:{ *:[i64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] })) => (ADDPv2i64p:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn)
2198 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64p),
2199 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2200 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2201 GIR_RootConstrainSelectedInstOperands,
2202 // GIR_Coverage, 13188,
2203 GIR_EraseRootFromParent_Done,
2204 // Label 181: @4783
2205 GIM_Try, /*On fail goto*//*Label 182*/ GIMT_Encode4(4816), // Rule ID 12451 //
2206 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
2207 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
2208 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_addsub_shifted_imm64),
2209 // (add:{ *:[i64] } addsub_shifted_imm64:{ *:[i64] }:$imm, GPR64sp:{ *:[i64] }:$Rn) => (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
2210 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXri),
2211 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2212 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2213 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
2214 GIR_RootConstrainSelectedInstOperands,
2215 // GIR_Coverage, 12451,
2216 GIR_EraseRootFromParent_Done,
2217 // Label 182: @4816
2218 GIM_Try, /*On fail goto*//*Label 183*/ GIMT_Encode4(4911), // Rule ID 3840 //
2219 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2220 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2221 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2222 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2223 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2224 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2225 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
2226 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
2227 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2228 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
2229 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2230 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
2231 // MIs[3] Operand 1
2232 // No operand predicates
2233 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2234 GIM_CheckIsSafeToFold, /*NumInsns*/3,
2235 // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
2236 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
2237 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
2238 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
2239 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
2240 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
2241 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
2242 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2243 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
2244 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
2245 GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2246 GIR_RootConstrainSelectedInstOperands,
2247 // GIR_Coverage, 3840,
2248 GIR_EraseRootFromParent_Done,
2249 // Label 183: @4911
2250 GIM_Try, /*On fail goto*//*Label 184*/ GIMT_Encode4(5006), // Rule ID 3841 //
2251 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2252 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2253 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2254 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2255 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2256 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2257 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
2258 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
2259 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2260 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
2261 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2262 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i64imm_32bit),
2263 // MIs[3] Operand 1
2264 // No operand predicates
2265 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2266 GIM_CheckIsSafeToFold, /*NumInsns*/3,
2267 // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
2268 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
2269 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
2270 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
2271 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
2272 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
2273 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
2274 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2275 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
2276 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
2277 GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2278 GIR_RootConstrainSelectedInstOperands,
2279 // GIR_Coverage, 3841,
2280 GIR_EraseRootFromParent_Done,
2281 // Label 184: @5006
2282 GIM_Try, /*On fail goto*//*Label 185*/ GIMT_Encode4(5039), // Rule ID 103 //
2283 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
2284 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
2285 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_addsub_shifted_imm64),
2286 // (add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) => (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
2287 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXri),
2288 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2289 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2290 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
2291 GIR_RootConstrainSelectedInstOperands,
2292 // GIR_Coverage, 103,
2293 GIR_EraseRootFromParent_Done,
2294 // Label 185: @5039
2295 GIM_Try, /*On fail goto*//*Label 186*/ GIMT_Encode4(5134), // Rule ID 13025 //
2296 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2297 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2298 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2299 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2300 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2301 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2302 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2303 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
2304 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
2305 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2306 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
2307 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2308 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
2309 // MIs[3] Operand 1
2310 // No operand predicates
2311 GIM_CheckIsSafeToFold, /*NumInsns*/3,
2312 // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C)) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
2313 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
2314 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
2315 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
2316 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
2317 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
2318 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
2319 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
2321 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
2322 GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2323 GIR_RootConstrainSelectedInstOperands,
2324 // GIR_Coverage, 13025,
2325 GIR_EraseRootFromParent_Done,
2326 // Label 186: @5134
2327 GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(5229), // Rule ID 13026 //
2328 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2329 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2330 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2331 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2332 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2333 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2334 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2335 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
2336 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
2337 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2338 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
2339 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2340 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i64imm_32bit),
2341 // MIs[3] Operand 1
2342 // No operand predicates
2343 GIM_CheckIsSafeToFold, /*NumInsns*/3,
2344 // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C)) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
2345 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
2346 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
2347 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
2348 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
2349 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
2350 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
2351 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2352 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
2353 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
2354 GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2355 GIR_RootConstrainSelectedInstOperands,
2356 // GIR_Coverage, 13026,
2357 GIR_EraseRootFromParent_Done,
2358 // Label 187: @5229
2359 GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(5311), // Rule ID 12462 //
2360 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2361 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2362 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2363 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2364 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2365 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2366 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
2367 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
2368 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2369 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
2370 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT),
2371 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
2372 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2373 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2374 GIM_CheckIsSafeToFold, /*NumInsns*/3,
2375 // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
2376 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
2377 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2378 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
2379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
2380 GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2381 GIR_RootConstrainSelectedInstOperands,
2382 // GIR_Coverage, 12462,
2383 GIR_EraseRootFromParent_Done,
2384 // Label 188: @5311
2385 GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(5393), // Rule ID 12463 //
2386 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2387 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2388 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2389 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2390 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2391 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2392 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
2393 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
2394 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2395 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
2396 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
2397 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
2398 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2399 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2400 GIM_CheckIsSafeToFold, /*NumInsns*/3,
2401 // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
2402 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
2403 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
2405 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
2406 GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2407 GIR_RootConstrainSelectedInstOperands,
2408 // GIR_Coverage, 12463,
2409 GIR_EraseRootFromParent_Done,
2410 // Label 189: @5393
2411 GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(5475), // Rule ID 134 //
2412 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2413 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2414 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2415 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2416 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2417 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2418 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2419 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
2420 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
2421 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2422 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
2423 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT),
2424 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
2425 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2426 GIM_CheckIsSafeToFold, /*NumInsns*/3,
2427 // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
2428 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
2429 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2430 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
2431 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
2432 GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2433 GIR_RootConstrainSelectedInstOperands,
2434 // GIR_Coverage, 134,
2435 GIR_EraseRootFromParent_Done,
2436 // Label 190: @5475
2437 GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(5557), // Rule ID 136 //
2438 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2439 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2440 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2441 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2442 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2443 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2444 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2445 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
2446 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
2447 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2448 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
2449 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
2450 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
2451 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
2452 GIM_CheckIsSafeToFold, /*NumInsns*/3,
2453 // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
2454 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
2455 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2456 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
2457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
2458 GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2459 GIR_RootConstrainSelectedInstOperands,
2460 // GIR_Coverage, 136,
2461 GIR_EraseRootFromParent_Done,
2462 // Label 191: @5557
2463 GIM_Try, /*On fail goto*//*Label 192*/ GIMT_Encode4(5615), // Rule ID 12872 //
2464 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
2465 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2466 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2467 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2468 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2469 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
2470 // MIs[1] pattern
2471 GIM_CheckIsImm, /*MI*/1, /*Op*/2,
2472 GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
2473 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2474 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2475 // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1148:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern), GPR64:{ *:[i64] }:$Rdn) => (INCB_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
2476 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCB_XPiI),
2477 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
2478 GIR_RootToRootCopy, /*OpIdx*/2, // Rdn
2479 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
2480 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
2481 GIR_RootConstrainSelectedInstOperands,
2482 // GIR_Coverage, 12872,
2483 GIR_EraseRootFromParent_Done,
2484 // Label 192: @5615
2485 GIM_Try, /*On fail goto*//*Label 193*/ GIMT_Encode4(5673), // Rule ID 14740 //
2486 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
2487 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2488 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2489 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2490 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2491 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
2492 // MIs[1] pattern
2493 GIM_CheckIsImm, /*MI*/1, /*Op*/2,
2494 GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
2495 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2496 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2497 // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1150:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern), GPR64:{ *:[i64] }:$Rdn) => (INCH_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
2498 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCH_XPiI),
2499 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
2500 GIR_RootToRootCopy, /*OpIdx*/2, // Rdn
2501 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
2502 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
2503 GIR_RootConstrainSelectedInstOperands,
2504 // GIR_Coverage, 14740,
2505 GIR_EraseRootFromParent_Done,
2506 // Label 193: @5673
2507 GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(5731), // Rule ID 14752 //
2508 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
2509 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2510 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2511 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2512 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2513 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
2514 // MIs[1] pattern
2515 GIM_CheckIsImm, /*MI*/1, /*Op*/2,
2516 GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
2517 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2518 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2519 // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1156:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern), GPR64:{ *:[i64] }:$Rdn) => (INCW_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
2520 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCW_XPiI),
2521 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
2522 GIR_RootToRootCopy, /*OpIdx*/2, // Rdn
2523 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
2524 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
2525 GIR_RootConstrainSelectedInstOperands,
2526 // GIR_Coverage, 14752,
2527 GIR_EraseRootFromParent_Done,
2528 // Label 194: @5731
2529 GIM_Try, /*On fail goto*//*Label 195*/ GIMT_Encode4(5789), // Rule ID 14764 //
2530 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
2531 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2532 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2533 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2534 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2535 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
2536 // MIs[1] pattern
2537 GIM_CheckIsImm, /*MI*/1, /*Op*/2,
2538 GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
2539 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2540 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2541 // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1149:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern), GPR64:{ *:[i64] }:$Rdn) => (INCD_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
2542 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCD_XPiI),
2543 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
2544 GIR_RootToRootCopy, /*OpIdx*/2, // Rdn
2545 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
2546 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
2547 GIR_RootConstrainSelectedInstOperands,
2548 // GIR_Coverage, 14764,
2549 GIR_EraseRootFromParent_Done,
2550 // Label 195: @5789
2551 GIM_Try, /*On fail goto*//*Label 196*/ GIMT_Encode4(5847), // Rule ID 2552 //
2552 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
2553 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2554 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2555 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2556 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2557 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2558 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
2559 // MIs[1] pattern
2560 GIM_CheckIsImm, /*MI*/1, /*Op*/2,
2561 GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
2562 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2563 // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1148:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)) => (INCB_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
2564 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCB_XPiI),
2565 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
2566 GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
2567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
2568 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
2569 GIR_RootConstrainSelectedInstOperands,
2570 // GIR_Coverage, 2552,
2571 GIR_EraseRootFromParent_Done,
2572 // Label 196: @5847
2573 GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(5905), // Rule ID 9628 //
2574 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
2575 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2576 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2577 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2578 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2579 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2580 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
2581 // MIs[1] pattern
2582 GIM_CheckIsImm, /*MI*/1, /*Op*/2,
2583 GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
2584 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2585 // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1150:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)) => (INCH_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
2586 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCH_XPiI),
2587 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
2588 GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
2589 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
2590 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
2591 GIR_RootConstrainSelectedInstOperands,
2592 // GIR_Coverage, 9628,
2593 GIR_EraseRootFromParent_Done,
2594 // Label 197: @5905
2595 GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(5963), // Rule ID 9640 //
2596 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
2597 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2598 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2599 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2600 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2601 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2602 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
2603 // MIs[1] pattern
2604 GIM_CheckIsImm, /*MI*/1, /*Op*/2,
2605 GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
2606 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2607 // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1156:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)) => (INCW_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
2608 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCW_XPiI),
2609 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
2610 GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
2611 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
2612 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
2613 GIR_RootConstrainSelectedInstOperands,
2614 // GIR_Coverage, 9640,
2615 GIR_EraseRootFromParent_Done,
2616 // Label 198: @5963
2617 GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(6021), // Rule ID 9652 //
2618 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
2619 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2620 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2621 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2622 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2623 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2624 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
2625 // MIs[1] pattern
2626 GIM_CheckIsImm, /*MI*/1, /*Op*/2,
2627 GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
2628 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2629 // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1149:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)) => (INCD_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
2630 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCD_XPiI),
2631 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
2632 GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
2633 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
2634 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
2635 GIR_RootConstrainSelectedInstOperands,
2636 // GIR_Coverage, 9652,
2637 GIR_EraseRootFromParent_Done,
2638 // Label 199: @6021
2639 GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(6054), // Rule ID 12455 //
2640 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
2641 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
2642 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_extended_reg32to64_i64),
2643 // (add:{ *:[i64] } arith_extended_reg32to64_i64:{ *:[i64] }:$Rm_and_extend, GPR64sp:{ *:[i64] }:$Rn) => (ADDXrx:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, arith_extended_reg32to64_i64:{ *:[i64] }:$Rm_and_extend)
2644 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXrx),
2645 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2646 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2647 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_extend
2648 GIR_RootConstrainSelectedInstOperands,
2649 // GIR_Coverage, 12455,
2650 GIR_EraseRootFromParent_Done,
2651 // Label 200: @6054
2652 GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(6090), // Rule ID 13018 //
2653 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2654 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2655 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_neg_addsub_shifted_imm64),
2656 // (add:{ *:[i64] } neg_addsub_shifted_imm64:{ *:[i64] }:$imm, GPR64:{ *:[i64] }:$Rn) => (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm)
2657 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSXri),
2658 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2659 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2660 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
2661 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
2662 GIR_RootConstrainSelectedInstOperands,
2663 // GIR_Coverage, 13018,
2664 GIR_EraseRootFromParent_Done,
2665 // Label 201: @6090
2666 GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(6123), // Rule ID 109 //
2667 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
2668 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
2669 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_extended_reg32to64_i64),
2670 // (add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, arith_extended_reg32to64_i64:{ *:[i64] }:$Rm_and_extend) => (ADDXrx:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, arith_extended_reg32to64_i64:{ *:[i64] }:$Rm_and_extend)
2671 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXrx),
2672 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2673 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2674 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_extend
2675 GIR_RootConstrainSelectedInstOperands,
2676 // GIR_Coverage, 109,
2677 GIR_EraseRootFromParent_Done,
2678 // Label 202: @6123
2679 GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(6159), // Rule ID 3791 //
2680 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2681 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2682 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_neg_addsub_shifted_imm64),
2683 // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm) => (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm)
2684 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSXri),
2685 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2686 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2687 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
2688 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
2689 GIR_RootConstrainSelectedInstOperands,
2690 // GIR_Coverage, 3791,
2691 GIR_EraseRootFromParent_Done,
2692 // Label 203: @6159
2693 GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(6192), // Rule ID 12453 //
2694 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2695 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2696 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg64),
2697 // (add:{ *:[i64] } arith_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn) => (ADDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
2698 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXrs),
2699 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2700 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2701 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
2702 GIR_RootConstrainSelectedInstOperands,
2703 // GIR_Coverage, 12453,
2704 GIR_EraseRootFromParent_Done,
2705 // Label 204: @6192
2706 GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(6225), // Rule ID 107 //
2707 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2708 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
2709 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg64),
2710 // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm_and_shift) => (ADDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
2711 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXrs),
2712 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2713 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2714 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
2715 GIR_RootConstrainSelectedInstOperands,
2716 // GIR_Coverage, 107,
2717 GIR_EraseRootFromParent_Done,
2718 // Label 205: @6225
2719 GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(6281), // Rule ID 12561 //
2720 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2721 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2722 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2723 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2724 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2725 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
2726 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
2727 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2728 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2729 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2730 // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 622:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd) => (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
2731 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv2i32_v1i64),
2732 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
2733 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
2734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2735 GIR_RootConstrainSelectedInstOperands,
2736 // GIR_Coverage, 12561,
2737 GIR_EraseRootFromParent_Done,
2738 // Label 206: @6281
2739 GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(6337), // Rule ID 12573 //
2740 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2741 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2742 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2743 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2744 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2745 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
2746 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
2747 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2748 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2749 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2750 // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 687:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd) => (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
2751 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv2i32_v1i64),
2752 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
2753 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
2754 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2755 GIR_RootConstrainSelectedInstOperands,
2756 // GIR_Coverage, 12573,
2757 GIR_EraseRootFromParent_Done,
2758 // Label 207: @6337
2759 GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(6404), // Rule ID 12779 //
2760 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2761 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2762 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2763 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
2764 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2765 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2766 // MIs[1] imm
2767 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
2768 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2769 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
2770 // MIs[2] Operand 1
2771 // No operand predicates
2772 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2773 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
2774 GIM_CheckIsSafeToFold, /*NumInsns*/2,
2775 // (add:{ *:[i64] } (AArch64vashr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[i64] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (SSRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
2776 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAd),
2777 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
2778 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
2779 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2780 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
2781 GIR_RootConstrainSelectedInstOperands,
2782 // GIR_Coverage, 12779,
2783 GIR_EraseRootFromParent_Done,
2784 // Label 208: @6404
2785 GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(6471), // Rule ID 13177 //
2786 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2787 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2788 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2789 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
2790 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2791 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2792 // MIs[1] imm
2793 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
2794 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2795 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
2796 // MIs[2] Operand 1
2797 // No operand predicates
2798 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2799 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
2800 GIM_CheckIsSafeToFold, /*NumInsns*/2,
2801 // (add:{ *:[v1i64] } (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[v1i64] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (SSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
2802 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAd),
2803 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
2804 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
2805 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2806 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
2807 GIR_RootConstrainSelectedInstOperands,
2808 // GIR_Coverage, 13177,
2809 GIR_EraseRootFromParent_Done,
2810 // Label 209: @6471
2811 GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(6538), // Rule ID 12782 //
2812 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2813 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2814 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2815 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
2816 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2817 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2818 // MIs[1] imm
2819 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
2820 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2821 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
2822 // MIs[2] Operand 1
2823 // No operand predicates
2824 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2825 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
2826 GIM_CheckIsSafeToFold, /*NumInsns*/2,
2827 // (add:{ *:[i64] } (AArch64vlshr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[i64] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (USRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
2828 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAd),
2829 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
2830 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
2831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2832 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
2833 GIR_RootConstrainSelectedInstOperands,
2834 // GIR_Coverage, 12782,
2835 GIR_EraseRootFromParent_Done,
2836 // Label 210: @6538
2837 GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(6605), // Rule ID 13180 //
2838 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2839 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2840 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2841 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
2842 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2843 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2844 // MIs[1] imm
2845 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
2846 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2847 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
2848 // MIs[2] Operand 1
2849 // No operand predicates
2850 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2851 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
2852 GIM_CheckIsSafeToFold, /*NumInsns*/2,
2853 // (add:{ *:[v1i64] } (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[v1i64] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (USRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
2854 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAd),
2855 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
2856 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
2857 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2858 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
2859 GIR_RootConstrainSelectedInstOperands,
2860 // GIR_Coverage, 13180,
2861 GIR_EraseRootFromParent_Done,
2862 // Label 211: @6605
2863 GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(6661), // Rule ID 984 //
2864 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2865 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2866 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2867 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2868 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2869 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2870 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
2871 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
2872 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2873 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2874 // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 622:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)) => (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
2875 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv2i32_v1i64),
2876 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
2877 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
2878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2879 GIR_RootConstrainSelectedInstOperands,
2880 // GIR_Coverage, 984,
2881 GIR_EraseRootFromParent_Done,
2882 // Label 212: @6661
2883 GIM_Try, /*On fail goto*//*Label 213*/ GIMT_Encode4(6717), // Rule ID 1045 //
2884 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2885 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2886 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2887 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2888 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
2889 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
2890 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
2891 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
2892 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2893 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2894 // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 687:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)) => (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
2895 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv2i32_v1i64),
2896 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
2897 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
2898 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2899 GIR_RootConstrainSelectedInstOperands,
2900 // GIR_Coverage, 1045,
2901 GIR_EraseRootFromParent_Done,
2902 // Label 213: @6717
2903 GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(6784), // Rule ID 2106 //
2904 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2905 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2906 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2907 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2908 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
2909 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2910 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2911 // MIs[1] imm
2912 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
2913 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2914 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
2915 // MIs[2] Operand 1
2916 // No operand predicates
2917 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
2918 GIM_CheckIsSafeToFold, /*NumInsns*/2,
2919 // (add:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, (AArch64vashr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>> => (SSRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
2920 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAd),
2921 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
2922 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
2923 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2924 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
2925 GIR_RootConstrainSelectedInstOperands,
2926 // GIR_Coverage, 2106,
2927 GIR_EraseRootFromParent_Done,
2928 // Label 214: @6784
2929 GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(6851), // Rule ID 5881 //
2930 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2931 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2932 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2933 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2934 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
2935 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2936 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2937 // MIs[1] imm
2938 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
2939 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2940 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
2941 // MIs[2] Operand 1
2942 // No operand predicates
2943 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
2944 GIM_CheckIsSafeToFold, /*NumInsns*/2,
2945 // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>> => (SSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
2946 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAd),
2947 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
2948 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
2949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2950 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
2951 GIR_RootConstrainSelectedInstOperands,
2952 // GIR_Coverage, 5881,
2953 GIR_EraseRootFromParent_Done,
2954 // Label 215: @6851
2955 GIM_Try, /*On fail goto*//*Label 216*/ GIMT_Encode4(6918), // Rule ID 2115 //
2956 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2957 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2958 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2959 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2960 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
2961 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2962 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2963 // MIs[1] imm
2964 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
2965 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2966 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
2967 // MIs[2] Operand 1
2968 // No operand predicates
2969 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
2970 GIM_CheckIsSafeToFold, /*NumInsns*/2,
2971 // (add:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, (AArch64vlshr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>> => (USRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
2972 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAd),
2973 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
2974 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
2975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2976 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
2977 GIR_RootConstrainSelectedInstOperands,
2978 // GIR_Coverage, 2115,
2979 GIR_EraseRootFromParent_Done,
2980 // Label 216: @6918
2981 GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(6985), // Rule ID 5887 //
2982 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2983 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2984 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2985 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2986 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
2987 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2988 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
2989 // MIs[1] imm
2990 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
2991 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2992 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
2993 // MIs[2] Operand 1
2994 // No operand predicates
2995 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
2996 GIM_CheckIsSafeToFold, /*NumInsns*/2,
2997 // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>> => (USRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
2998 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAd),
2999 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3000 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
3001 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3002 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
3003 GIR_RootConstrainSelectedInstOperands,
3004 // GIR_Coverage, 5887,
3005 GIR_EraseRootFromParent_Done,
3006 // Label 217: @6985
3007 GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(7033), // Rule ID 12560 //
3008 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3009 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3010 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3011 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
3012 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3013 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3014 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3015 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3016 // (add:{ *:[v1i64] } (AArch64saddlp_n:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd) => (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
3017 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv2i32_v1i64),
3018 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3019 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3020 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3021 GIR_RootConstrainSelectedInstOperands,
3022 // GIR_Coverage, 12560,
3023 GIR_EraseRootFromParent_Done,
3024 // Label 218: @7033
3025 GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(7081), // Rule ID 12572 //
3026 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3027 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3028 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3029 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
3030 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3031 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3032 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3033 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3034 // (add:{ *:[v1i64] } (AArch64uaddlp_n:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd) => (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
3035 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv2i32_v1i64),
3036 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3037 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3038 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3039 GIR_RootConstrainSelectedInstOperands,
3040 // GIR_Coverage, 12572,
3041 GIR_EraseRootFromParent_Done,
3042 // Label 219: @7081
3043 GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(7129), // Rule ID 983 //
3044 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3045 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3046 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3047 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3048 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
3049 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3050 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3051 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3052 // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (AArch64saddlp_n:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn)) => (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
3053 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv2i32_v1i64),
3054 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3055 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
3056 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3057 GIR_RootConstrainSelectedInstOperands,
3058 // GIR_Coverage, 983,
3059 GIR_EraseRootFromParent_Done,
3060 // Label 220: @7129
3061 GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(7177), // Rule ID 1044 //
3062 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3063 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3064 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3065 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3066 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
3067 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3068 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3069 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3070 // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (AArch64uaddlp_n:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn)) => (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
3071 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv2i32_v1i64),
3072 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3073 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
3074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3075 GIR_RootConstrainSelectedInstOperands,
3076 // GIR_Coverage, 1044,
3077 GIR_EraseRootFromParent_Done,
3078 // Label 221: @7177
3079 GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(7201), // Rule ID 105 //
3080 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
3081 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
3082 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
3083 // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ADDXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
3084 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDXrr),
3085 GIR_RootConstrainSelectedInstOperands,
3086 // GIR_Coverage, 105,
3087 GIR_Done,
3088 // Label 222: @7201
3089 GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(7228), // Rule ID 1594 //
3090 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3091 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3092 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3093 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3094 // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (ADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
3095 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv1i64),
3096 GIR_RootConstrainSelectedInstOperands,
3097 // GIR_Coverage, 1594,
3098 GIR_Done,
3099 // Label 223: @7228
3100 GIM_Reject,
3101 // Label 179: @7229
3102 GIM_Reject,
3103 // Label 149: @7230
3104 GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(8229),
3105 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
3106 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
3107 GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(7310), // Rule ID 12595 //
3108 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3109 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3110 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3111 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3112 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3113 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
3114 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3115 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
3116 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3117 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3118 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3119 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3120 // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 621:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd) => (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
3121 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv2i32),
3122 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3123 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3124 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3126 GIR_RootConstrainSelectedInstOperands,
3127 // GIR_Coverage, 12595,
3128 GIR_EraseRootFromParent_Done,
3129 // Label 225: @7310
3130 GIM_Try, /*On fail goto*//*Label 226*/ GIMT_Encode4(7379), // Rule ID 12607 //
3131 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3132 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3133 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3134 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3135 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3136 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
3137 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3138 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
3139 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3140 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3141 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3142 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3143 // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 686:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd) => (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
3144 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv2i32),
3145 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3146 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3147 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3148 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3149 GIR_RootConstrainSelectedInstOperands,
3150 // GIR_Coverage, 12607,
3151 GIR_EraseRootFromParent_Done,
3152 // Label 226: @7379
3153 GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(7435), // Rule ID 12557 //
3154 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3155 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3156 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3157 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3158 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3159 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
3160 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3161 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3162 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3163 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3164 // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 622:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd) => (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
3165 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i16_v2i32),
3166 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3167 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3168 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3169 GIR_RootConstrainSelectedInstOperands,
3170 // GIR_Coverage, 12557,
3171 GIR_EraseRootFromParent_Done,
3172 // Label 227: @7435
3173 GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(7491), // Rule ID 12569 //
3174 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3175 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3176 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3177 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3178 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3179 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
3180 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3181 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3182 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3183 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3184 // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 687:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd) => (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
3185 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i16_v2i32),
3186 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3187 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3189 GIR_RootConstrainSelectedInstOperands,
3190 // GIR_Coverage, 12569,
3191 GIR_EraseRootFromParent_Done,
3192 // Label 228: @7491
3193 GIM_Try, /*On fail goto*//*Label 229*/ GIMT_Encode4(7558), // Rule ID 12799 //
3194 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3195 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3196 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3197 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
3198 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3199 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3200 // MIs[1] imm
3201 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
3202 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
3203 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
3204 // MIs[2] Operand 1
3205 // No operand predicates
3206 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3207 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
3208 GIM_CheckIsSafeToFold, /*NumInsns*/2,
3209 // (add:{ *:[v2i32] } (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V64:{ *:[v2i32] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (SSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3210 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i32_shift),
3211 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3212 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3213 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3214 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
3215 GIR_RootConstrainSelectedInstOperands,
3216 // GIR_Coverage, 12799,
3217 GIR_EraseRootFromParent_Done,
3218 // Label 229: @7558
3219 GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(7625), // Rule ID 12820 //
3220 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3221 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3222 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3223 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
3224 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3225 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3226 // MIs[1] imm
3227 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
3228 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
3229 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
3230 // MIs[2] Operand 1
3231 // No operand predicates
3232 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3233 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
3234 GIM_CheckIsSafeToFold, /*NumInsns*/2,
3235 // (add:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V64:{ *:[v2i32] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (USRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3236 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i32_shift),
3237 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3238 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3239 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3240 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
3241 GIR_RootConstrainSelectedInstOperands,
3242 // GIR_Coverage, 12820,
3243 GIR_EraseRootFromParent_Done,
3244 // Label 230: @7625
3245 GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(7694), // Rule ID 1352 //
3246 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3247 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3248 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3249 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3250 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3251 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3252 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
3253 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3254 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
3255 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3256 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3257 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3258 // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 621:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
3259 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv2i32),
3260 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3261 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
3262 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3263 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3264 GIR_RootConstrainSelectedInstOperands,
3265 // GIR_Coverage, 1352,
3266 GIR_EraseRootFromParent_Done,
3267 // Label 231: @7694
3268 GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(7763), // Rule ID 1475 //
3269 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3270 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3271 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3272 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3273 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3274 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3275 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
3276 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3277 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
3278 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3279 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3280 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3281 // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 686:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
3282 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv2i32),
3283 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3284 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
3285 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3286 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
3287 GIR_RootConstrainSelectedInstOperands,
3288 // GIR_Coverage, 1475,
3289 GIR_EraseRootFromParent_Done,
3290 // Label 232: @7763
3291 GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(7819), // Rule ID 980 //
3292 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3293 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3294 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3295 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3296 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3297 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3298 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
3299 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3300 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3301 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3302 // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 622:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)) => (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
3303 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i16_v2i32),
3304 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3305 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
3306 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3307 GIR_RootConstrainSelectedInstOperands,
3308 // GIR_Coverage, 980,
3309 GIR_EraseRootFromParent_Done,
3310 // Label 233: @7819
3311 GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(7875), // Rule ID 1041 //
3312 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3313 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3314 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3315 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3316 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3317 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
3318 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
3319 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3320 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3321 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3322 // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 687:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)) => (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
3323 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i16_v2i32),
3324 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3325 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
3326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3327 GIR_RootConstrainSelectedInstOperands,
3328 // GIR_Coverage, 1041,
3329 GIR_EraseRootFromParent_Done,
3330 // Label 234: @7875
3331 GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(7942), // Rule ID 2223 //
3332 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3333 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3334 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3335 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3336 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
3337 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3338 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3339 // MIs[1] imm
3340 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
3341 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
3342 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
3343 // MIs[2] Operand 1
3344 // No operand predicates
3345 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
3346 GIM_CheckIsSafeToFold, /*NumInsns*/2,
3347 // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>> => (SSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3348 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i32_shift),
3349 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3350 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
3351 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3352 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
3353 GIR_RootConstrainSelectedInstOperands,
3354 // GIR_Coverage, 2223,
3355 GIR_EraseRootFromParent_Done,
3356 // Label 235: @7942
3357 GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(8009), // Rule ID 2282 //
3358 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3359 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3360 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3361 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3362 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
3363 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3364 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3365 // MIs[1] imm
3366 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
3367 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
3368 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
3369 // MIs[2] Operand 1
3370 // No operand predicates
3371 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
3372 GIM_CheckIsSafeToFold, /*NumInsns*/2,
3373 // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>> => (USRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3374 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i32_shift),
3375 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3376 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
3377 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3378 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
3379 GIR_RootConstrainSelectedInstOperands,
3380 // GIR_Coverage, 2282,
3381 GIR_EraseRootFromParent_Done,
3382 // Label 236: @8009
3383 GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(8057), // Rule ID 12556 //
3384 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3385 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3386 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3387 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
3388 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3389 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3390 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3391 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3392 // (add:{ *:[v2i32] } (AArch64saddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd) => (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
3393 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i16_v2i32),
3394 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3395 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3396 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3397 GIR_RootConstrainSelectedInstOperands,
3398 // GIR_Coverage, 12556,
3399 GIR_EraseRootFromParent_Done,
3400 // Label 237: @8057
3401 GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(8105), // Rule ID 12568 //
3402 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3403 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3404 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3405 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
3406 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3407 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3408 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3409 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3410 // (add:{ *:[v2i32] } (AArch64uaddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd) => (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
3411 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i16_v2i32),
3412 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3413 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3414 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3415 GIR_RootConstrainSelectedInstOperands,
3416 // GIR_Coverage, 12568,
3417 GIR_EraseRootFromParent_Done,
3418 // Label 238: @8105
3419 GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(8153), // Rule ID 979 //
3420 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3421 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3422 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3423 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3424 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
3425 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3426 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3427 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3428 // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64saddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)) => (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
3429 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i16_v2i32),
3430 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3431 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
3432 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3433 GIR_RootConstrainSelectedInstOperands,
3434 // GIR_Coverage, 979,
3435 GIR_EraseRootFromParent_Done,
3436 // Label 239: @8153
3437 GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(8201), // Rule ID 1040 //
3438 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3439 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3440 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3441 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3442 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
3443 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3444 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3445 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3446 // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64uaddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)) => (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
3447 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i16_v2i32),
3448 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3449 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
3450 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3451 GIR_RootConstrainSelectedInstOperands,
3452 // GIR_Coverage, 1040,
3453 GIR_EraseRootFromParent_Done,
3454 // Label 240: @8201
3455 GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(8228), // Rule ID 1091 //
3456 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3457 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3458 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3459 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3460 // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (ADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
3461 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv2i32),
3462 GIR_RootConstrainSelectedInstOperands,
3463 // GIR_Coverage, 1091,
3464 GIR_Done,
3465 // Label 241: @8228
3466 GIM_Reject,
3467 // Label 224: @8229
3468 GIM_Reject,
3469 // Label 150: @8230
3470 GIM_Try, /*On fail goto*//*Label 242*/ GIMT_Encode4(12127),
3471 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3472 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
3473 GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(8328), // Rule ID 12639 //
3474 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3475 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3476 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3477 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3478 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3479 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3480 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3481 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3482 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
3483 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
3484 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
3485 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3486 GIM_CheckIsSafeToFold, /*NumInsns*/2,
3487 GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3488 GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3489 // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 621:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))), V128:{ *:[v2i64] }:$Rd) => (SABALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
3490 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv4i32_v2i64),
3491 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3492 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3493 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
3494 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
3495 GIR_RootConstrainSelectedInstOperands,
3496 // GIR_Coverage, 12639,
3497 GIR_EraseRootFromParent_Done,
3498 // Label 243: @8328
3499 GIM_Try, /*On fail goto*//*Label 244*/ GIMT_Encode4(8415), // Rule ID 12663 //
3500 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3502 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3503 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3504 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3505 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3506 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3507 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3508 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
3509 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
3510 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
3511 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3512 GIM_CheckIsSafeToFold, /*NumInsns*/2,
3513 GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3514 GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3515 // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 686:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))), V128:{ *:[v2i64] }:$Rd) => (UABALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
3516 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv4i32_v2i64),
3517 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3518 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3519 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
3520 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
3521 GIR_RootConstrainSelectedInstOperands,
3522 // GIR_Coverage, 12663,
3523 GIR_EraseRootFromParent_Done,
3524 // Label 244: @8415
3525 GIM_Try, /*On fail goto*//*Label 245*/ GIMT_Encode4(8502), // Rule ID 1686 //
3526 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3527 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3528 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3529 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3530 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3531 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3532 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3533 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3534 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3535 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
3536 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
3537 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
3538 GIM_CheckIsSafeToFold, /*NumInsns*/2,
3539 GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3540 GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3541 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 621:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))) => (SABALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
3542 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv4i32_v2i64),
3543 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3544 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
3545 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
3546 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
3547 GIR_RootConstrainSelectedInstOperands,
3548 // GIR_Coverage, 1686,
3549 GIR_EraseRootFromParent_Done,
3550 // Label 245: @8502
3551 GIM_Try, /*On fail goto*//*Label 246*/ GIMT_Encode4(8589), // Rule ID 1764 //
3552 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3553 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3554 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3555 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3556 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3557 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3558 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3559 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3560 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3561 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
3562 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
3563 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
3564 GIM_CheckIsSafeToFold, /*NumInsns*/2,
3565 GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3566 GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3567 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 686:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))) => (UABALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
3568 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv4i32_v2i64),
3569 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3570 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
3571 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
3572 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
3573 GIR_RootConstrainSelectedInstOperands,
3574 // GIR_Coverage, 1764,
3575 GIR_EraseRootFromParent_Done,
3576 // Label 246: @8589
3577 GIM_Try, /*On fail goto*//*Label 247*/ GIMT_Encode4(8658), // Rule ID 1788 //
3578 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3579 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3580 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3581 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3582 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3583 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3584 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3585 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3586 GIM_CheckIsSafeToFold, /*NumInsns*/2,
3587 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3588 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3589 // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (UADDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
3590 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i32_v2i64),
3591 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
3592 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
3593 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
3594 GIR_RootConstrainSelectedInstOperands,
3595 // GIR_Coverage, 1788,
3596 GIR_EraseRootFromParent_Done,
3597 // Label 247: @8658
3598 GIM_Try, /*On fail goto*//*Label 248*/ GIMT_Encode4(8727), // Rule ID 1787 //
3599 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3600 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3601 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3602 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3603 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3604 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3605 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
3606 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3607 GIM_CheckIsSafeToFold, /*NumInsns*/2,
3608 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3609 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3610 // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (UADDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
3611 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i32_v2i64),
3612 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
3613 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
3614 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
3615 GIR_RootConstrainSelectedInstOperands,
3616 // GIR_Coverage, 1787,
3617 GIR_EraseRootFromParent_Done,
3618 // Label 248: @8727
3619 GIM_Try, /*On fail goto*//*Label 249*/ GIMT_Encode4(8796), // Rule ID 1704 //
3620 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3621 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3622 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3623 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3624 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3625 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3626 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
3627 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3628 GIM_CheckIsSafeToFold, /*NumInsns*/2,
3629 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3630 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3631 // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (SADDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
3632 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLv4i32_v2i64),
3633 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
3634 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
3635 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
3636 GIR_RootConstrainSelectedInstOperands,
3637 // GIR_Coverage, 1704,
3638 GIR_EraseRootFromParent_Done,
3639 // Label 249: @8796
3640 GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(8865), // Rule ID 1786 //
3641 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3642 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3643 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3644 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3645 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3646 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3647 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3648 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3649 GIM_CheckIsSafeToFold, /*NumInsns*/2,
3650 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3651 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3652 // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (UADDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
3653 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i32_v2i64),
3654 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
3655 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
3656 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
3657 GIR_RootConstrainSelectedInstOperands,
3658 // GIR_Coverage, 1786,
3659 GIR_EraseRootFromParent_Done,
3660 // Label 250: @8865
3661 GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(8934), // Rule ID 1785 //
3662 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3663 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3664 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3665 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3666 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3667 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3668 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
3669 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3670 GIM_CheckIsSafeToFold, /*NumInsns*/2,
3671 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3672 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3673 // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (UADDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
3674 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i32_v2i64),
3675 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
3676 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
3677 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
3678 GIR_RootConstrainSelectedInstOperands,
3679 // GIR_Coverage, 1785,
3680 GIR_EraseRootFromParent_Done,
3681 // Label 251: @8934
3682 GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(9001), // Rule ID 12651 //
3683 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3684 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3685 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3686 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
3687 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3688 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3689 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3690 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3691 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3692 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3693 // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd) => (SMLALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
3694 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i32_v2i64),
3695 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3696 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3697 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
3698 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
3699 GIR_RootConstrainSelectedInstOperands,
3700 // GIR_Coverage, 12651,
3701 GIR_EraseRootFromParent_Done,
3702 // Label 252: @9001
3703 GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(9068), // Rule ID 12681 //
3704 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3705 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3706 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3707 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
3708 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3709 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3710 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3711 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3712 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3713 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3714 // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd) => (UMLALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
3715 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i32_v2i64),
3716 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3717 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3718 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
3719 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
3720 GIR_RootConstrainSelectedInstOperands,
3721 // GIR_Coverage, 12681,
3722 GIR_EraseRootFromParent_Done,
3723 // Label 253: @9068
3724 GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(9135), // Rule ID 1716 //
3725 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3726 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3727 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3728 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3729 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
3730 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3731 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3732 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3733 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3734 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3735 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (SMLALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
3736 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i32_v2i64),
3737 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3738 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
3739 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
3740 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
3741 GIR_RootConstrainSelectedInstOperands,
3742 // GIR_Coverage, 1716,
3743 GIR_EraseRootFromParent_Done,
3744 // Label 254: @9135
3745 GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(9202), // Rule ID 1806 //
3746 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3747 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3748 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3749 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3750 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
3751 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3752 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3753 GIM_CheckIsSafeToFold, /*NumInsns*/1,
3754 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3755 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
3756 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (UMLALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
3757 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i32_v2i64),
3758 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3759 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
3760 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
3761 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
3762 GIR_RootConstrainSelectedInstOperands,
3763 // GIR_Coverage, 1806,
3764 GIR_EraseRootFromParent_Done,
3765 // Label 255: @9202
3766 GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(9283), // Rule ID 12637 //
3767 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3768 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3769 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3770 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3771 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3772 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3773 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3774 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3775 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
3776 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
3777 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
3778 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3779 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3780 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3781 GIM_CheckIsSafeToFold, /*NumInsns*/2,
3782 // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 621:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd) => (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
3783 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv2i32_v2i64),
3784 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3785 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
3787 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
3788 GIR_RootConstrainSelectedInstOperands,
3789 // GIR_Coverage, 12637,
3790 GIR_EraseRootFromParent_Done,
3791 // Label 256: @9283
3792 GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(9364), // Rule ID 12661 //
3793 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3794 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3795 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3796 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3797 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3798 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3799 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3800 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3801 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
3802 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
3803 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
3804 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3805 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3806 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3807 GIM_CheckIsSafeToFold, /*NumInsns*/2,
3808 // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 686:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd) => (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
3809 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv2i32_v2i64),
3810 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3811 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
3813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
3814 GIR_RootConstrainSelectedInstOperands,
3815 // GIR_Coverage, 12661,
3816 GIR_EraseRootFromParent_Done,
3817 // Label 257: @9364
3818 GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(9445), // Rule ID 1684 //
3819 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3820 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3821 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3822 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3823 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3824 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3825 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3826 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3827 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3828 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
3829 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
3830 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
3831 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3832 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3833 GIM_CheckIsSafeToFold, /*NumInsns*/2,
3834 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 621:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))) => (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
3835 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv2i32_v2i64),
3836 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3837 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
3838 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
3839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
3840 GIR_RootConstrainSelectedInstOperands,
3841 // GIR_Coverage, 1684,
3842 GIR_EraseRootFromParent_Done,
3843 // Label 258: @9445
3844 GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(9526), // Rule ID 1762 //
3845 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3846 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3847 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3848 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3849 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3850 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3851 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3852 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
3853 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3854 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
3855 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
3856 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
3857 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3858 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3859 GIM_CheckIsSafeToFold, /*NumInsns*/2,
3860 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 686:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))) => (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
3861 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv2i32_v2i64),
3862 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3863 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
3864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
3865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
3866 GIR_RootConstrainSelectedInstOperands,
3867 // GIR_Coverage, 1762,
3868 GIR_EraseRootFromParent_Done,
3869 // Label 259: @9526
3870 GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(9618), // Rule ID 12732 //
3871 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3872 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3873 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3874 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
3875 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3876 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3877 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3878 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
3879 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3880 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
3881 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3882 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
3883 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
3884 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
3885 // MIs[3] Operand 1
3886 // No operand predicates
3887 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3888 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3889 GIM_CheckIsSafeToFold, /*NumInsns*/3,
3890 // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn), V128:{ *:[v2i64] }:$Rd) => (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
3891 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
3892 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3893 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3894 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
3896 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
3897 GIR_RootConstrainSelectedInstOperands,
3898 // GIR_Coverage, 12732,
3899 GIR_EraseRootFromParent_Done,
3900 // Label 260: @9618
3901 GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(9710), // Rule ID 12731 //
3902 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3903 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3904 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3905 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
3906 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3907 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3908 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3909 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
3910 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
3911 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3912 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
3913 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3914 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
3915 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
3916 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
3917 // MIs[3] Operand 1
3918 // No operand predicates
3919 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3920 GIM_CheckIsSafeToFold, /*NumInsns*/3,
3921 // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v2i64] }:$Rd) => (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
3922 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
3923 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3924 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3925 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3926 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
3927 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
3928 GIR_RootConstrainSelectedInstOperands,
3929 // GIR_Coverage, 12731,
3930 GIR_EraseRootFromParent_Done,
3931 // Label 261: @9710
3932 GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(9802), // Rule ID 12762 //
3933 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3934 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3935 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3936 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
3937 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3938 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3939 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3940 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
3941 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3942 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
3943 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3944 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
3945 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
3946 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
3947 // MIs[3] Operand 1
3948 // No operand predicates
3949 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3950 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3951 GIM_CheckIsSafeToFold, /*NumInsns*/3,
3952 // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn), V128:{ *:[v2i64] }:$Rd) => (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
3953 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
3954 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3955 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3956 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
3957 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
3958 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
3959 GIR_RootConstrainSelectedInstOperands,
3960 // GIR_Coverage, 12762,
3961 GIR_EraseRootFromParent_Done,
3962 // Label 262: @9802
3963 GIM_Try, /*On fail goto*//*Label 263*/ GIMT_Encode4(9894), // Rule ID 12761 //
3964 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3965 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3966 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3967 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
3968 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3969 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3970 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
3971 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
3972 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
3973 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
3974 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
3975 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3976 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
3977 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
3978 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
3979 // MIs[3] Operand 1
3980 // No operand predicates
3981 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3982 GIM_CheckIsSafeToFold, /*NumInsns*/3,
3983 // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v2i64] }:$Rd) => (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
3984 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
3985 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3986 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
3987 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3988 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
3989 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
3990 GIR_RootConstrainSelectedInstOperands,
3991 // GIR_Coverage, 12761,
3992 GIR_EraseRootFromParent_Done,
3993 // Label 263: @9894
3994 GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(9986), // Rule ID 12730 //
3995 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3996 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3997 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
3998 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3999 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
4000 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4001 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4002 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4003 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
4004 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4005 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4006 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4007 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
4008 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4009 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
4010 // MIs[3] Operand 1
4011 // No operand predicates
4012 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4013 GIM_CheckIsSafeToFold, /*NumInsns*/3,
4014 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn)) => (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
4015 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
4016 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4017 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
4018 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4020 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
4021 GIR_RootConstrainSelectedInstOperands,
4022 // GIR_Coverage, 12730,
4023 GIR_EraseRootFromParent_Done,
4024 // Label 264: @9986
4025 GIM_Try, /*On fail goto*//*Label 265*/ GIMT_Encode4(10078), // Rule ID 2028 //
4026 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4027 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4028 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4029 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4030 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
4031 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4032 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4033 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4034 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4035 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
4036 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4037 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4038 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4039 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
4040 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4041 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
4042 // MIs[3] Operand 1
4043 // No operand predicates
4044 GIM_CheckIsSafeToFold, /*NumInsns*/3,
4045 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
4046 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
4047 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4048 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
4049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4051 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
4052 GIR_RootConstrainSelectedInstOperands,
4053 // GIR_Coverage, 2028,
4054 GIR_EraseRootFromParent_Done,
4055 // Label 265: @10078
4056 GIM_Try, /*On fail goto*//*Label 266*/ GIMT_Encode4(10170), // Rule ID 12760 //
4057 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4058 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4059 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4060 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4061 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
4062 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4063 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4064 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4065 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
4066 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4067 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4068 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4069 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
4070 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4071 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
4072 // MIs[3] Operand 1
4073 // No operand predicates
4074 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4075 GIM_CheckIsSafeToFold, /*NumInsns*/3,
4076 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn)) => (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
4077 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
4078 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4079 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
4080 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4081 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4082 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
4083 GIR_RootConstrainSelectedInstOperands,
4084 // GIR_Coverage, 12760,
4085 GIR_EraseRootFromParent_Done,
4086 // Label 266: @10170
4087 GIM_Try, /*On fail goto*//*Label 267*/ GIMT_Encode4(10262), // Rule ID 2080 //
4088 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4089 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4090 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4091 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4092 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
4093 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4094 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4095 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4096 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4097 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
4098 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
4099 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4100 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4101 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
4102 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4103 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
4104 // MIs[3] Operand 1
4105 // No operand predicates
4106 GIM_CheckIsSafeToFold, /*NumInsns*/3,
4107 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
4108 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
4109 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4110 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
4111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4112 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4113 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
4114 GIR_RootConstrainSelectedInstOperands,
4115 // GIR_Coverage, 2080,
4116 GIR_EraseRootFromParent_Done,
4117 // Label 267: @10262
4118 GIM_Try, /*On fail goto*//*Label 268*/ GIMT_Encode4(10313), // Rule ID 12675 //
4119 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4120 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4121 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4122 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4123 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4124 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4125 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4126 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
4127 // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)), V128:{ *:[v2i64] }:$Rn) => (UADDWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
4128 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i32_v2i64),
4129 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4130 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
4131 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
4132 GIR_RootConstrainSelectedInstOperands,
4133 // GIR_Coverage, 12675,
4134 GIR_EraseRootFromParent_Done,
4135 // Label 268: @10313
4136 GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(10364), // Rule ID 12645 //
4137 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4138 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4139 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4140 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4141 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4142 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4143 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4144 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
4145 // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)), V128:{ *:[v2i64] }:$Rn) => (SADDWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
4146 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv4i32_v2i64),
4147 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4148 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
4149 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
4150 GIR_RootConstrainSelectedInstOperands,
4151 // GIR_Coverage, 12645,
4152 GIR_EraseRootFromParent_Done,
4153 // Label 269: @10364
4154 GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(10415), // Rule ID 12674 //
4155 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4156 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4157 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4158 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4159 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4160 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4161 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4162 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
4163 // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)), V128:{ *:[v2i64] }:$Rn) => (UADDWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
4164 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i32_v2i64),
4165 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4166 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
4167 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
4168 GIR_RootConstrainSelectedInstOperands,
4169 // GIR_Coverage, 12674,
4170 GIR_EraseRootFromParent_Done,
4171 // Label 270: @10415
4172 GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(10466), // Rule ID 1800 //
4173 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4174 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4175 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4176 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4177 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4178 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4179 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4180 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
4181 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (UADDWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
4182 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i32_v2i64),
4183 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4184 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
4185 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
4186 GIR_RootConstrainSelectedInstOperands,
4187 // GIR_Coverage, 1800,
4188 GIR_EraseRootFromParent_Done,
4189 // Label 271: @10466
4190 GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(10517), // Rule ID 1710 //
4191 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4192 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4193 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4194 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4195 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4196 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4197 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4198 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
4199 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (SADDWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
4200 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv4i32_v2i64),
4201 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4202 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
4203 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
4204 GIR_RootConstrainSelectedInstOperands,
4205 // GIR_Coverage, 1710,
4206 GIR_EraseRootFromParent_Done,
4207 // Label 272: @10517
4208 GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(10568), // Rule ID 1799 //
4209 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4210 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4211 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4212 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4213 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4214 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4215 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4216 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
4217 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (UADDWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
4218 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i32_v2i64),
4219 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4220 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
4221 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
4222 GIR_RootConstrainSelectedInstOperands,
4223 // GIR_Coverage, 1799,
4224 GIR_EraseRootFromParent_Done,
4225 // Label 273: @10568
4226 GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(10624), // Rule ID 12563 //
4227 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4228 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4229 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4230 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
4231 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
4232 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
4233 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4234 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4235 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4236 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4237 // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 622:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd) => (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
4238 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i32_v2i64),
4239 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4240 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
4241 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4242 GIR_RootConstrainSelectedInstOperands,
4243 // GIR_Coverage, 12563,
4244 GIR_EraseRootFromParent_Done,
4245 // Label 274: @10624
4246 GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(10680), // Rule ID 12575 //
4247 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4248 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4249 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4250 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
4251 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
4252 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
4253 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4254 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4255 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4256 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4257 // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 687:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd) => (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
4258 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i32_v2i64),
4259 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4260 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
4261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4262 GIR_RootConstrainSelectedInstOperands,
4263 // GIR_Coverage, 12575,
4264 GIR_EraseRootFromParent_Done,
4265 // Label 275: @10680
4266 GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(10747), // Rule ID 12803 //
4267 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4268 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4269 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4270 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
4271 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
4272 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4273 // MIs[1] imm
4274 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4275 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4276 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
4277 // MIs[2] Operand 1
4278 // No operand predicates
4279 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4280 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
4281 GIM_CheckIsSafeToFold, /*NumInsns*/2,
4282 // (add:{ *:[v2i64] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), V128:{ *:[v2i64] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (SSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
4283 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i64_shift),
4284 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4285 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
4286 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4287 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4288 GIR_RootConstrainSelectedInstOperands,
4289 // GIR_Coverage, 12803,
4290 GIR_EraseRootFromParent_Done,
4291 // Label 276: @10747
4292 GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(10814), // Rule ID 12824 //
4293 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4294 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4295 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4296 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
4297 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
4298 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4299 // MIs[1] imm
4300 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4301 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4302 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
4303 // MIs[2] Operand 1
4304 // No operand predicates
4305 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4306 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
4307 GIM_CheckIsSafeToFold, /*NumInsns*/2,
4308 // (add:{ *:[v2i64] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), V128:{ *:[v2i64] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (USRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
4309 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i64_shift),
4310 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4311 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
4312 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4313 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4314 GIR_RootConstrainSelectedInstOperands,
4315 // GIR_Coverage, 12824,
4316 GIR_EraseRootFromParent_Done,
4317 // Label 277: @10814
4318 GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(10870), // Rule ID 986 //
4319 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4320 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4321 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4322 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4323 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
4324 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
4325 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
4326 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4327 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4328 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4329 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 622:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
4330 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i32_v2i64),
4331 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4332 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
4333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4334 GIR_RootConstrainSelectedInstOperands,
4335 // GIR_Coverage, 986,
4336 GIR_EraseRootFromParent_Done,
4337 // Label 278: @10870
4338 GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(10926), // Rule ID 1047 //
4339 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4340 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4341 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4342 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4343 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
4344 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
4345 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
4346 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4347 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4348 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4349 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 687:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
4350 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i32_v2i64),
4351 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4352 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
4353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4354 GIR_RootConstrainSelectedInstOperands,
4355 // GIR_Coverage, 1047,
4356 GIR_EraseRootFromParent_Done,
4357 // Label 279: @10926
4358 GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(10993), // Rule ID 2227 //
4359 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4360 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4361 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4362 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4363 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
4364 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
4365 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4366 // MIs[1] imm
4367 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4368 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4369 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
4370 // MIs[2] Operand 1
4371 // No operand predicates
4372 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
4373 GIM_CheckIsSafeToFold, /*NumInsns*/2,
4374 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>> => (SSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
4375 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i64_shift),
4376 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4377 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
4378 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4379 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4380 GIR_RootConstrainSelectedInstOperands,
4381 // GIR_Coverage, 2227,
4382 GIR_EraseRootFromParent_Done,
4383 // Label 280: @10993
4384 GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(11060), // Rule ID 2286 //
4385 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4386 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4387 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4388 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4389 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
4390 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
4391 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4392 // MIs[1] imm
4393 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4394 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4395 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
4396 // MIs[2] Operand 1
4397 // No operand predicates
4398 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
4399 GIM_CheckIsSafeToFold, /*NumInsns*/2,
4400 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>> => (USRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
4401 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i64_shift),
4402 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4403 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
4404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4405 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4406 GIR_RootConstrainSelectedInstOperands,
4407 // GIR_Coverage, 2286,
4408 GIR_EraseRootFromParent_Done,
4409 // Label 281: @11060
4410 GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(11123), // Rule ID 1784 //
4411 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4412 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4413 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4414 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4415 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4416 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4417 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4418 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4419 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4420 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4421 GIM_CheckIsSafeToFold, /*NumInsns*/2,
4422 // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4423 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
4424 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4425 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4426 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4427 GIR_RootConstrainSelectedInstOperands,
4428 // GIR_Coverage, 1784,
4429 GIR_EraseRootFromParent_Done,
4430 // Label 282: @11123
4431 GIM_Try, /*On fail goto*//*Label 283*/ GIMT_Encode4(11186), // Rule ID 1783 //
4432 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4433 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4434 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4435 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4436 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4437 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4438 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4439 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4440 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4441 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4442 GIM_CheckIsSafeToFold, /*NumInsns*/2,
4443 // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4444 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
4445 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4447 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4448 GIR_RootConstrainSelectedInstOperands,
4449 // GIR_Coverage, 1783,
4450 GIR_EraseRootFromParent_Done,
4451 // Label 283: @11186
4452 GIM_Try, /*On fail goto*//*Label 284*/ GIMT_Encode4(11249), // Rule ID 1703 //
4453 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4454 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4455 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4456 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4457 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4458 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4459 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4460 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
4461 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4462 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4463 GIM_CheckIsSafeToFold, /*NumInsns*/2,
4464 // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4465 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLv2i32_v2i64),
4466 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4467 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4468 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4469 GIR_RootConstrainSelectedInstOperands,
4470 // GIR_Coverage, 1703,
4471 GIR_EraseRootFromParent_Done,
4472 // Label 284: @11249
4473 GIM_Try, /*On fail goto*//*Label 285*/ GIMT_Encode4(11312), // Rule ID 1782 //
4474 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4475 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4476 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4477 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4478 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4479 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4480 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4481 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4482 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4483 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4484 GIM_CheckIsSafeToFold, /*NumInsns*/2,
4485 // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4486 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
4487 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4488 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4489 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4490 GIR_RootConstrainSelectedInstOperands,
4491 // GIR_Coverage, 1782,
4492 GIR_EraseRootFromParent_Done,
4493 // Label 285: @11312
4494 GIM_Try, /*On fail goto*//*Label 286*/ GIMT_Encode4(11375), // Rule ID 1781 //
4495 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4496 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4497 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4498 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4499 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4500 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4501 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4502 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4503 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4504 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4505 GIM_CheckIsSafeToFold, /*NumInsns*/2,
4506 // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4507 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
4508 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4509 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4510 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4511 GIR_RootConstrainSelectedInstOperands,
4512 // GIR_Coverage, 1781,
4513 GIR_EraseRootFromParent_Done,
4514 // Label 286: @11375
4515 GIM_Try, /*On fail goto*//*Label 287*/ GIMT_Encode4(11436), // Rule ID 12650 //
4516 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4517 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4518 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4519 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
4520 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4521 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4522 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4523 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4524 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4525 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4526 // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd) => (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4527 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_v2i64),
4528 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4529 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
4530 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4531 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4532 GIR_RootConstrainSelectedInstOperands,
4533 // GIR_Coverage, 12650,
4534 GIR_EraseRootFromParent_Done,
4535 // Label 287: @11436
4536 GIM_Try, /*On fail goto*//*Label 288*/ GIMT_Encode4(11497), // Rule ID 12680 //
4537 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4538 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4539 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4540 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
4541 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4542 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4543 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4544 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4545 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4546 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4547 // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd) => (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4548 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_v2i64),
4549 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4550 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
4551 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4552 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4553 GIR_RootConstrainSelectedInstOperands,
4554 // GIR_Coverage, 12680,
4555 GIR_EraseRootFromParent_Done,
4556 // Label 288: @11497
4557 GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(11545), // Rule ID 12673 //
4558 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4559 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4560 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4561 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4562 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4563 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4564 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4565 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4566 // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn) => (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4567 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
4568 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4569 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
4570 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4571 GIR_RootConstrainSelectedInstOperands,
4572 // GIR_Coverage, 12673,
4573 GIR_EraseRootFromParent_Done,
4574 // Label 289: @11545
4575 GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(11593), // Rule ID 12562 //
4576 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4577 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4578 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4579 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
4580 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4581 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4582 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4583 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4584 // (add:{ *:[v2i64] } (AArch64saddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd) => (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
4585 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i32_v2i64),
4586 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4587 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
4588 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4589 GIR_RootConstrainSelectedInstOperands,
4590 // GIR_Coverage, 12562,
4591 GIR_EraseRootFromParent_Done,
4592 // Label 290: @11593
4593 GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(11641), // Rule ID 12644 //
4594 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4595 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4596 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4597 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4598 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4599 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4600 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4601 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4602 // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn) => (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4603 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv2i32_v2i64),
4604 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4605 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
4606 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4607 GIR_RootConstrainSelectedInstOperands,
4608 // GIR_Coverage, 12644,
4609 GIR_EraseRootFromParent_Done,
4610 // Label 291: @11641
4611 GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(11689), // Rule ID 12574 //
4612 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4613 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4614 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4615 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
4616 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4617 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4618 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4619 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4620 // (add:{ *:[v2i64] } (AArch64uaddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd) => (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
4621 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i32_v2i64),
4622 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4623 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
4624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4625 GIR_RootConstrainSelectedInstOperands,
4626 // GIR_Coverage, 12574,
4627 GIR_EraseRootFromParent_Done,
4628 // Label 292: @11689
4629 GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(11737), // Rule ID 12672 //
4630 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4631 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4632 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4633 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4634 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4635 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4636 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4637 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4638 // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn) => (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4639 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
4640 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4641 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
4642 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4643 GIR_RootConstrainSelectedInstOperands,
4644 // GIR_Coverage, 12672,
4645 GIR_EraseRootFromParent_Done,
4646 // Label 293: @11737
4647 GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(11798), // Rule ID 1715 //
4648 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4649 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4650 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4651 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4652 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
4653 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4654 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4655 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4656 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4657 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4658 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4659 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_v2i64),
4660 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4661 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
4662 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4663 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4664 GIR_RootConstrainSelectedInstOperands,
4665 // GIR_Coverage, 1715,
4666 GIR_EraseRootFromParent_Done,
4667 // Label 294: @11798
4668 GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(11859), // Rule ID 1805 //
4669 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4670 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4671 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4672 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4673 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
4674 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4675 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4676 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4677 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4678 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4679 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4680 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_v2i64),
4681 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4682 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
4683 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4684 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4685 GIR_RootConstrainSelectedInstOperands,
4686 // GIR_Coverage, 1805,
4687 GIR_EraseRootFromParent_Done,
4688 // Label 295: @11859
4689 GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(11907), // Rule ID 1798 //
4690 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4691 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4692 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4693 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4694 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4695 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4696 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4697 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4698 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4699 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
4700 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4701 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
4702 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4703 GIR_RootConstrainSelectedInstOperands,
4704 // GIR_Coverage, 1798,
4705 GIR_EraseRootFromParent_Done,
4706 // Label 296: @11907
4707 GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(11955), // Rule ID 985 //
4708 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4709 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4710 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4711 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4712 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
4713 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4714 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4715 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4716 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64saddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)) => (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
4717 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i32_v2i64),
4718 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4719 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
4720 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4721 GIR_RootConstrainSelectedInstOperands,
4722 // GIR_Coverage, 985,
4723 GIR_EraseRootFromParent_Done,
4724 // Label 297: @11955
4725 GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(12003), // Rule ID 1709 //
4726 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4727 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4728 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4729 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4730 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4731 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4732 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4733 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4734 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4735 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv2i32_v2i64),
4736 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4737 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
4738 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4739 GIR_RootConstrainSelectedInstOperands,
4740 // GIR_Coverage, 1709,
4741 GIR_EraseRootFromParent_Done,
4742 // Label 298: @12003
4743 GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(12051), // Rule ID 1046 //
4744 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4745 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4746 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4747 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4748 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
4749 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4750 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4751 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4752 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64uaddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)) => (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
4753 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i32_v2i64),
4754 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4755 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
4756 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4757 GIR_RootConstrainSelectedInstOperands,
4758 // GIR_Coverage, 1046,
4759 GIR_EraseRootFromParent_Done,
4760 // Label 299: @12051
4761 GIM_Try, /*On fail goto*//*Label 300*/ GIMT_Encode4(12099), // Rule ID 1797 //
4762 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4763 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4764 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4765 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4766 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4767 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4768 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4769 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4770 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
4771 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
4772 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4773 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
4774 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4775 GIR_RootConstrainSelectedInstOperands,
4776 // GIR_Coverage, 1797,
4777 GIR_EraseRootFromParent_Done,
4778 // Label 300: @12099
4779 GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(12126), // Rule ID 1093 //
4780 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4781 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4782 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4783 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
4784 // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
4785 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv2i64),
4786 GIR_RootConstrainSelectedInstOperands,
4787 // GIR_Coverage, 1093,
4788 GIR_Done,
4789 // Label 301: @12126
4790 GIM_Reject,
4791 // Label 242: @12127
4792 GIM_Reject,
4793 // Label 151: @12128
4794 GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(13127),
4795 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
4796 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
4797 GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(12208), // Rule ID 12591 //
4798 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4799 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4800 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4801 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
4802 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4803 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
4804 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
4805 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
4806 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4807 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4808 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4809 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4810 // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 621:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd) => (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4811 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv4i16),
4812 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4813 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
4814 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4815 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4816 GIR_RootConstrainSelectedInstOperands,
4817 // GIR_Coverage, 12591,
4818 GIR_EraseRootFromParent_Done,
4819 // Label 303: @12208
4820 GIM_Try, /*On fail goto*//*Label 304*/ GIMT_Encode4(12277), // Rule ID 12603 //
4821 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4822 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4823 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4824 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
4825 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4826 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
4827 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
4828 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
4829 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4830 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4831 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4832 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4833 // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 686:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd) => (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4834 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv4i16),
4835 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4836 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
4837 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4838 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4839 GIR_RootConstrainSelectedInstOperands,
4840 // GIR_Coverage, 12603,
4841 GIR_EraseRootFromParent_Done,
4842 // Label 304: @12277
4843 GIM_Try, /*On fail goto*//*Label 305*/ GIMT_Encode4(12333), // Rule ID 12553 //
4844 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4845 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4846 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4847 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
4848 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
4849 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
4850 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4851 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4852 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4853 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4854 // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 622:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd) => (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
4855 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i8_v4i16),
4856 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4857 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
4858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4859 GIR_RootConstrainSelectedInstOperands,
4860 // GIR_Coverage, 12553,
4861 GIR_EraseRootFromParent_Done,
4862 // Label 305: @12333
4863 GIM_Try, /*On fail goto*//*Label 306*/ GIMT_Encode4(12389), // Rule ID 12565 //
4864 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4865 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4866 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4867 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
4868 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
4869 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
4870 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4871 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4872 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4873 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4874 // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 687:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd) => (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
4875 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i8_v4i16),
4876 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4877 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
4878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4879 GIR_RootConstrainSelectedInstOperands,
4880 // GIR_Coverage, 12565,
4881 GIR_EraseRootFromParent_Done,
4882 // Label 306: @12389
4883 GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(12456), // Rule ID 12795 //
4884 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4885 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4886 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4887 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
4888 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4889 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4890 // MIs[1] imm
4891 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4892 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4893 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
4894 // MIs[2] Operand 1
4895 // No operand predicates
4896 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4897 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
4898 GIM_CheckIsSafeToFold, /*NumInsns*/2,
4899 // (add:{ *:[v4i16] } (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V64:{ *:[v4i16] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (SSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
4900 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i16_shift),
4901 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4902 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
4903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4904 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4905 GIR_RootConstrainSelectedInstOperands,
4906 // GIR_Coverage, 12795,
4907 GIR_EraseRootFromParent_Done,
4908 // Label 307: @12456
4909 GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(12523), // Rule ID 12816 //
4910 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4911 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4912 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4913 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
4914 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4915 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4916 // MIs[1] imm
4917 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4918 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4919 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
4920 // MIs[2] Operand 1
4921 // No operand predicates
4922 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4923 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
4924 GIM_CheckIsSafeToFold, /*NumInsns*/2,
4925 // (add:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V64:{ *:[v4i16] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (USRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
4926 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i16_shift),
4927 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4928 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
4929 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4930 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4931 GIR_RootConstrainSelectedInstOperands,
4932 // GIR_Coverage, 12816,
4933 GIR_EraseRootFromParent_Done,
4934 // Label 308: @12523
4935 GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(12592), // Rule ID 1348 //
4936 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4937 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4938 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4939 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4940 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
4941 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4942 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
4943 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
4944 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
4945 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4946 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4947 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4948 // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 621:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4949 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv4i16),
4950 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4951 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
4952 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4954 GIR_RootConstrainSelectedInstOperands,
4955 // GIR_Coverage, 1348,
4956 GIR_EraseRootFromParent_Done,
4957 // Label 309: @12592
4958 GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(12661), // Rule ID 1471 //
4959 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4960 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4961 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4962 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4963 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
4964 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
4965 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
4966 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
4967 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
4968 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4969 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4970 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4971 // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 686:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
4972 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv4i16),
4973 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4974 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
4975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4976 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
4977 GIR_RootConstrainSelectedInstOperands,
4978 // GIR_Coverage, 1471,
4979 GIR_EraseRootFromParent_Done,
4980 // Label 310: @12661
4981 GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(12717), // Rule ID 976 //
4982 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4983 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4984 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4985 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4986 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
4987 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
4988 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
4989 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4990 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
4991 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4992 // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 622:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)) => (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
4993 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i8_v4i16),
4994 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4995 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
4996 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
4997 GIR_RootConstrainSelectedInstOperands,
4998 // GIR_Coverage, 976,
4999 GIR_EraseRootFromParent_Done,
5000 // Label 311: @12717
5001 GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(12773), // Rule ID 1037 //
5002 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5003 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5004 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5005 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5006 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
5007 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
5008 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
5009 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
5010 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5011 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5012 // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 687:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)) => (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
5013 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i8_v4i16),
5014 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5015 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
5016 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
5017 GIR_RootConstrainSelectedInstOperands,
5018 // GIR_Coverage, 1037,
5019 GIR_EraseRootFromParent_Done,
5020 // Label 312: @12773
5021 GIM_Try, /*On fail goto*//*Label 313*/ GIMT_Encode4(12840), // Rule ID 2219 //
5022 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5023 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5024 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5025 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5026 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
5027 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5028 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5029 // MIs[1] imm
5030 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5031 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5032 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
5033 // MIs[2] Operand 1
5034 // No operand predicates
5035 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
5036 GIM_CheckIsSafeToFold, /*NumInsns*/2,
5037 // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>> => (SSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
5038 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i16_shift),
5039 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5040 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
5041 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5042 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5043 GIR_RootConstrainSelectedInstOperands,
5044 // GIR_Coverage, 2219,
5045 GIR_EraseRootFromParent_Done,
5046 // Label 313: @12840
5047 GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(12907), // Rule ID 2278 //
5048 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5049 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5050 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5051 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5052 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
5053 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5054 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5055 // MIs[1] imm
5056 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5057 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5058 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
5059 // MIs[2] Operand 1
5060 // No operand predicates
5061 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
5062 GIM_CheckIsSafeToFold, /*NumInsns*/2,
5063 // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>> => (USRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
5064 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i16_shift),
5065 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5066 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
5067 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5068 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5069 GIR_RootConstrainSelectedInstOperands,
5070 // GIR_Coverage, 2278,
5071 GIR_EraseRootFromParent_Done,
5072 // Label 314: @12907
5073 GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(12955), // Rule ID 12552 //
5074 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5075 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5076 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5077 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
5078 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5079 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5080 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5081 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5082 // (add:{ *:[v4i16] } (AArch64saddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd) => (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
5083 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i8_v4i16),
5084 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5085 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
5086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5087 GIR_RootConstrainSelectedInstOperands,
5088 // GIR_Coverage, 12552,
5089 GIR_EraseRootFromParent_Done,
5090 // Label 315: @12955
5091 GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(13003), // Rule ID 12564 //
5092 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5093 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5094 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5095 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
5096 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5097 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5098 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5099 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5100 // (add:{ *:[v4i16] } (AArch64uaddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd) => (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
5101 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i8_v4i16),
5102 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5103 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
5104 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5105 GIR_RootConstrainSelectedInstOperands,
5106 // GIR_Coverage, 12564,
5107 GIR_EraseRootFromParent_Done,
5108 // Label 316: @13003
5109 GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(13051), // Rule ID 975 //
5110 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5111 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5112 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5113 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5114 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
5115 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5116 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5117 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5118 // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64saddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)) => (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
5119 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i8_v4i16),
5120 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5121 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
5122 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5123 GIR_RootConstrainSelectedInstOperands,
5124 // GIR_Coverage, 975,
5125 GIR_EraseRootFromParent_Done,
5126 // Label 317: @13051
5127 GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(13099), // Rule ID 1036 //
5128 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5129 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5130 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5131 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5132 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
5133 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5134 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5135 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5136 // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64uaddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)) => (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
5137 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i8_v4i16),
5138 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5139 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
5140 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5141 GIR_RootConstrainSelectedInstOperands,
5142 // GIR_Coverage, 1036,
5143 GIR_EraseRootFromParent_Done,
5144 // Label 318: @13099
5145 GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(13126), // Rule ID 1089 //
5146 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5147 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5148 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5149 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5150 // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (ADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
5151 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i16),
5152 GIR_RootConstrainSelectedInstOperands,
5153 // GIR_Coverage, 1089,
5154 GIR_Done,
5155 // Label 319: @13126
5156 GIM_Reject,
5157 // Label 302: @13127
5158 GIM_Reject,
5159 // Label 152: @13128
5160 GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(17301),
5161 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
5162 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
5163 GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(13226), // Rule ID 12635 //
5164 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5165 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5166 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5167 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5168 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5169 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5170 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
5171 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
5172 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
5173 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
5174 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
5175 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5176 GIM_CheckIsSafeToFold, /*NumInsns*/2,
5177 GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5178 GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5179 // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 621:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))), V128:{ *:[v4i32] }:$Rd) => (SABALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
5180 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv8i16_v4i32),
5181 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5182 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
5183 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
5184 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
5185 GIR_RootConstrainSelectedInstOperands,
5186 // GIR_Coverage, 12635,
5187 GIR_EraseRootFromParent_Done,
5188 // Label 321: @13226
5189 GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(13313), // Rule ID 12659 //
5190 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5191 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5192 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5193 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5194 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5195 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5196 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
5197 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
5198 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
5199 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
5200 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
5201 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5202 GIM_CheckIsSafeToFold, /*NumInsns*/2,
5203 GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5204 GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5205 // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 686:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))), V128:{ *:[v4i32] }:$Rd) => (UABALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
5206 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv8i16_v4i32),
5207 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5208 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
5209 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
5210 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
5211 GIR_RootConstrainSelectedInstOperands,
5212 // GIR_Coverage, 12659,
5213 GIR_EraseRootFromParent_Done,
5214 // Label 322: @13313
5215 GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(13400), // Rule ID 1682 //
5216 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5217 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5218 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5219 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5220 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5221 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5222 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5223 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
5224 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
5225 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
5226 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
5227 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
5228 GIM_CheckIsSafeToFold, /*NumInsns*/2,
5229 GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5230 GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5231 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 621:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))) => (SABALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
5232 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv8i16_v4i32),
5233 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5234 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
5235 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
5236 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
5237 GIR_RootConstrainSelectedInstOperands,
5238 // GIR_Coverage, 1682,
5239 GIR_EraseRootFromParent_Done,
5240 // Label 323: @13400
5241 GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(13487), // Rule ID 1760 //
5242 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5243 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5244 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5245 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5246 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5247 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5248 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5249 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
5250 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
5251 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
5252 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
5253 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
5254 GIM_CheckIsSafeToFold, /*NumInsns*/2,
5255 GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5256 GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5257 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 686:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))) => (UABALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
5258 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv8i16_v4i32),
5259 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5260 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
5261 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
5262 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
5263 GIR_RootConstrainSelectedInstOperands,
5264 // GIR_Coverage, 1760,
5265 GIR_EraseRootFromParent_Done,
5266 // Label 324: @13487
5267 GIM_Try, /*On fail goto*//*Label 325*/ GIMT_Encode4(13556), // Rule ID 1780 //
5268 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5269 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5270 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5271 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5272 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5273 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5274 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5275 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5276 GIM_CheckIsSafeToFold, /*NumInsns*/2,
5277 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5278 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5279 // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (UADDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
5280 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i16_v4i32),
5281 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5282 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
5283 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
5284 GIR_RootConstrainSelectedInstOperands,
5285 // GIR_Coverage, 1780,
5286 GIR_EraseRootFromParent_Done,
5287 // Label 325: @13556
5288 GIM_Try, /*On fail goto*//*Label 326*/ GIMT_Encode4(13625), // Rule ID 1779 //
5289 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5290 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5291 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5292 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5293 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5294 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5295 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5296 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5297 GIM_CheckIsSafeToFold, /*NumInsns*/2,
5298 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5299 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5300 // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (UADDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
5301 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i16_v4i32),
5302 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5303 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
5304 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
5305 GIR_RootConstrainSelectedInstOperands,
5306 // GIR_Coverage, 1779,
5307 GIR_EraseRootFromParent_Done,
5308 // Label 326: @13625
5309 GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(13694), // Rule ID 1702 //
5310 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5311 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5312 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5313 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5314 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5315 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5316 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
5317 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5318 GIM_CheckIsSafeToFold, /*NumInsns*/2,
5319 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5320 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5321 // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (SADDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
5322 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLv8i16_v4i32),
5323 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5324 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
5325 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
5326 GIR_RootConstrainSelectedInstOperands,
5327 // GIR_Coverage, 1702,
5328 GIR_EraseRootFromParent_Done,
5329 // Label 327: @13694
5330 GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(13763), // Rule ID 1778 //
5331 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5332 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5333 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5334 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5335 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5336 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5337 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5338 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5339 GIM_CheckIsSafeToFold, /*NumInsns*/2,
5340 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5341 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5342 // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (UADDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
5343 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i16_v4i32),
5344 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5345 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
5346 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
5347 GIR_RootConstrainSelectedInstOperands,
5348 // GIR_Coverage, 1778,
5349 GIR_EraseRootFromParent_Done,
5350 // Label 328: @13763
5351 GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(13832), // Rule ID 1777 //
5352 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5353 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5354 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5355 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5356 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5357 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5358 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5359 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5360 GIM_CheckIsSafeToFold, /*NumInsns*/2,
5361 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5362 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5363 // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (UADDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
5364 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i16_v4i32),
5365 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5366 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
5367 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
5368 GIR_RootConstrainSelectedInstOperands,
5369 // GIR_Coverage, 1777,
5370 GIR_EraseRootFromParent_Done,
5371 // Label 329: @13832
5372 GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(13899), // Rule ID 12649 //
5373 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5374 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5375 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5376 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
5377 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5378 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
5379 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5380 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5381 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5382 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5383 // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd) => (SMLALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
5384 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i16_v4i32),
5385 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5386 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
5387 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
5388 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
5389 GIR_RootConstrainSelectedInstOperands,
5390 // GIR_Coverage, 12649,
5391 GIR_EraseRootFromParent_Done,
5392 // Label 330: @13899
5393 GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(13966), // Rule ID 12679 //
5394 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5395 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5396 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5397 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
5398 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5399 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
5400 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5401 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5402 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5403 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5404 // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd) => (UMLALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
5405 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i16_v4i32),
5406 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5407 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
5408 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
5409 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
5410 GIR_RootConstrainSelectedInstOperands,
5411 // GIR_Coverage, 12679,
5412 GIR_EraseRootFromParent_Done,
5413 // Label 331: @13966
5414 GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(14033), // Rule ID 1714 //
5415 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5416 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5417 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5418 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5419 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
5420 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5421 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
5422 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5423 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5424 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5425 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (SMLALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
5426 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i16_v4i32),
5427 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5428 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
5429 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
5430 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
5431 GIR_RootConstrainSelectedInstOperands,
5432 // GIR_Coverage, 1714,
5433 GIR_EraseRootFromParent_Done,
5434 // Label 332: @14033
5435 GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(14100), // Rule ID 1804 //
5436 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5437 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5438 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5439 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5440 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
5441 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5442 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
5443 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5444 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5445 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5446 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (UMLALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
5447 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i16_v4i32),
5448 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5449 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
5450 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
5451 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
5452 GIR_RootConstrainSelectedInstOperands,
5453 // GIR_Coverage, 1804,
5454 GIR_EraseRootFromParent_Done,
5455 // Label 333: @14100
5456 GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(14181), // Rule ID 12633 //
5457 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5458 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5459 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5460 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5461 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5462 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5463 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
5464 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
5465 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
5466 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
5467 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
5468 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5469 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5470 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5471 GIM_CheckIsSafeToFold, /*NumInsns*/2,
5472 // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 621:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd) => (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
5473 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv4i16_v4i32),
5474 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5475 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
5476 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
5477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
5478 GIR_RootConstrainSelectedInstOperands,
5479 // GIR_Coverage, 12633,
5480 GIR_EraseRootFromParent_Done,
5481 // Label 334: @14181
5482 GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(14262), // Rule ID 12657 //
5483 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5484 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5485 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5486 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5487 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5488 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5489 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
5490 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
5491 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
5492 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
5493 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
5494 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5495 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5496 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5497 GIM_CheckIsSafeToFold, /*NumInsns*/2,
5498 // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 686:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd) => (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
5499 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv4i16_v4i32),
5500 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5501 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
5502 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
5503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
5504 GIR_RootConstrainSelectedInstOperands,
5505 // GIR_Coverage, 12657,
5506 GIR_EraseRootFromParent_Done,
5507 // Label 335: @14262
5508 GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(14343), // Rule ID 1680 //
5509 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5510 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5511 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5512 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5513 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5514 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5515 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5516 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
5517 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
5518 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
5519 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
5520 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
5521 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5522 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5523 GIM_CheckIsSafeToFold, /*NumInsns*/2,
5524 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 621:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))) => (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
5525 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv4i16_v4i32),
5526 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5527 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
5528 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
5529 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
5530 GIR_RootConstrainSelectedInstOperands,
5531 // GIR_Coverage, 1680,
5532 GIR_EraseRootFromParent_Done,
5533 // Label 336: @14343
5534 GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(14424), // Rule ID 1758 //
5535 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5536 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5537 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5538 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5539 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5540 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5541 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5542 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
5543 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
5544 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
5545 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
5546 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
5547 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5548 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5549 GIM_CheckIsSafeToFold, /*NumInsns*/2,
5550 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 686:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))) => (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
5551 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv4i16_v4i32),
5552 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5553 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
5554 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
5555 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
5556 GIR_RootConstrainSelectedInstOperands,
5557 // GIR_Coverage, 1758,
5558 GIR_EraseRootFromParent_Done,
5559 // Label 337: @14424
5560 GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(14516), // Rule ID 12723 //
5561 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5562 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5563 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5564 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
5565 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5566 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
5567 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5568 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
5569 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
5570 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5571 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
5572 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5573 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5574 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
5575 // MIs[3] Operand 1
5576 // No operand predicates
5577 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5578 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5579 GIM_CheckIsSafeToFold, /*NumInsns*/3,
5580 // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn), V128:{ *:[v4i32] }:$Rd) => (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
5581 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
5582 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5583 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
5584 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
5585 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5586 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
5587 GIR_RootConstrainSelectedInstOperands,
5588 // GIR_Coverage, 12723,
5589 GIR_EraseRootFromParent_Done,
5590 // Label 338: @14516
5591 GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(14608), // Rule ID 12722 //
5592 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5593 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5594 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5595 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
5596 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5597 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
5598 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5599 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5600 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
5601 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
5602 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5603 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
5604 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5605 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5606 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
5607 // MIs[3] Operand 1
5608 // No operand predicates
5609 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5610 GIM_CheckIsSafeToFold, /*NumInsns*/3,
5611 // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v4i32] }:$Rd) => (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
5612 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
5613 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5614 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
5615 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5616 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5617 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
5618 GIR_RootConstrainSelectedInstOperands,
5619 // GIR_Coverage, 12722,
5620 GIR_EraseRootFromParent_Done,
5621 // Label 339: @14608
5622 GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(14700), // Rule ID 12753 //
5623 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5624 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5625 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5626 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
5627 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5628 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
5629 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5630 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
5631 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
5632 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5633 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
5634 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5635 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5636 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
5637 // MIs[3] Operand 1
5638 // No operand predicates
5639 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5640 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5641 GIM_CheckIsSafeToFold, /*NumInsns*/3,
5642 // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn), V128:{ *:[v4i32] }:$Rd) => (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
5643 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
5644 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5645 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
5646 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
5647 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5648 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
5649 GIR_RootConstrainSelectedInstOperands,
5650 // GIR_Coverage, 12753,
5651 GIR_EraseRootFromParent_Done,
5652 // Label 340: @14700
5653 GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(14792), // Rule ID 12752 //
5654 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5655 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5656 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5657 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
5658 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5659 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
5660 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5661 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5662 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
5663 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
5664 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5665 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
5666 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5667 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5668 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
5669 // MIs[3] Operand 1
5670 // No operand predicates
5671 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5672 GIM_CheckIsSafeToFold, /*NumInsns*/3,
5673 // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v4i32] }:$Rd) => (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
5674 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
5675 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5676 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
5677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5679 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
5680 GIR_RootConstrainSelectedInstOperands,
5681 // GIR_Coverage, 12752,
5682 GIR_EraseRootFromParent_Done,
5683 // Label 341: @14792
5684 GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(14884), // Rule ID 12721 //
5685 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5686 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5687 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5688 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5689 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
5690 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5691 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
5692 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5693 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
5694 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
5695 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5696 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
5697 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5698 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5699 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
5700 // MIs[3] Operand 1
5701 // No operand predicates
5702 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5703 GIM_CheckIsSafeToFold, /*NumInsns*/3,
5704 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn)) => (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
5705 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
5706 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5707 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
5708 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
5709 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5710 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
5711 GIR_RootConstrainSelectedInstOperands,
5712 // GIR_Coverage, 12721,
5713 GIR_EraseRootFromParent_Done,
5714 // Label 342: @14884
5715 GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(14976), // Rule ID 2025 //
5716 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5717 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5718 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5719 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5720 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
5721 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5722 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
5723 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5724 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5725 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
5726 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
5727 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5728 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
5729 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5730 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5731 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
5732 // MIs[3] Operand 1
5733 // No operand predicates
5734 GIM_CheckIsSafeToFold, /*NumInsns*/3,
5735 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))) => (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
5736 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
5737 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5738 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
5739 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5740 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5741 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
5742 GIR_RootConstrainSelectedInstOperands,
5743 // GIR_Coverage, 2025,
5744 GIR_EraseRootFromParent_Done,
5745 // Label 343: @14976
5746 GIM_Try, /*On fail goto*//*Label 344*/ GIMT_Encode4(15068), // Rule ID 12751 //
5747 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5748 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5749 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5750 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5751 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
5752 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5753 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
5754 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5755 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
5756 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
5757 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5758 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
5759 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5760 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5761 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
5762 // MIs[3] Operand 1
5763 // No operand predicates
5764 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5765 GIM_CheckIsSafeToFold, /*NumInsns*/3,
5766 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn)) => (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
5767 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
5768 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5769 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
5770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
5771 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5772 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
5773 GIR_RootConstrainSelectedInstOperands,
5774 // GIR_Coverage, 12751,
5775 GIR_EraseRootFromParent_Done,
5776 // Label 344: @15068
5777 GIM_Try, /*On fail goto*//*Label 345*/ GIMT_Encode4(15160), // Rule ID 2077 //
5778 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5779 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5780 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5781 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5782 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
5783 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5784 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
5785 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
5786 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5787 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
5788 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
5789 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5790 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
5791 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5792 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5793 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
5794 // MIs[3] Operand 1
5795 // No operand predicates
5796 GIM_CheckIsSafeToFold, /*NumInsns*/3,
5797 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))) => (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
5798 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
5799 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5800 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
5801 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5802 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5803 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
5804 GIR_RootConstrainSelectedInstOperands,
5805 // GIR_Coverage, 2077,
5806 GIR_EraseRootFromParent_Done,
5807 // Label 345: @15160
5808 GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(15211), // Rule ID 12671 //
5809 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5810 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5811 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5812 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5813 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5814 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5815 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5816 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5817 // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)), V128:{ *:[v4i32] }:$Rn) => (UADDWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
5818 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i16_v4i32),
5819 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5820 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
5821 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
5822 GIR_RootConstrainSelectedInstOperands,
5823 // GIR_Coverage, 12671,
5824 GIR_EraseRootFromParent_Done,
5825 // Label 346: @15211
5826 GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(15262), // Rule ID 12643 //
5827 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5828 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5829 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5830 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5831 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5832 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5833 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5834 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5835 // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)), V128:{ *:[v4i32] }:$Rn) => (SADDWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
5836 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv8i16_v4i32),
5837 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5838 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
5839 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
5840 GIR_RootConstrainSelectedInstOperands,
5841 // GIR_Coverage, 12643,
5842 GIR_EraseRootFromParent_Done,
5843 // Label 347: @15262
5844 GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(15313), // Rule ID 12670 //
5845 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5846 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5847 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5848 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5849 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5850 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5851 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5852 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5853 // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)), V128:{ *:[v4i32] }:$Rn) => (UADDWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
5854 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i16_v4i32),
5855 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5856 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
5857 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
5858 GIR_RootConstrainSelectedInstOperands,
5859 // GIR_Coverage, 12670,
5860 GIR_EraseRootFromParent_Done,
5861 // Label 348: @15313
5862 GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(15364), // Rule ID 1796 //
5863 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5864 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5865 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5866 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5867 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5868 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5869 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5870 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5871 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (UADDWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
5872 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i16_v4i32),
5873 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5874 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
5875 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
5876 GIR_RootConstrainSelectedInstOperands,
5877 // GIR_Coverage, 1796,
5878 GIR_EraseRootFromParent_Done,
5879 // Label 349: @15364
5880 GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(15415), // Rule ID 1708 //
5881 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5882 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5883 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5884 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5885 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5886 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5887 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5888 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5889 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (SADDWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
5890 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv8i16_v4i32),
5891 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5892 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
5893 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
5894 GIR_RootConstrainSelectedInstOperands,
5895 // GIR_Coverage, 1708,
5896 GIR_EraseRootFromParent_Done,
5897 // Label 350: @15415
5898 GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(15466), // Rule ID 1795 //
5899 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5900 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5901 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5902 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5903 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5904 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5905 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5906 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
5907 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (UADDWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
5908 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i16_v4i32),
5909 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5910 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
5911 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
5912 GIR_RootConstrainSelectedInstOperands,
5913 // GIR_Coverage, 1795,
5914 GIR_EraseRootFromParent_Done,
5915 // Label 351: @15466
5916 GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(15535), // Rule ID 12597 //
5917 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5918 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5919 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5920 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
5921 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
5922 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
5923 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5924 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
5925 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5926 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5927 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5928 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5929 // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 621:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd) => (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
5930 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv4i32),
5931 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5932 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
5933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
5934 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
5935 GIR_RootConstrainSelectedInstOperands,
5936 // GIR_Coverage, 12597,
5937 GIR_EraseRootFromParent_Done,
5938 // Label 352: @15535
5939 GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(15604), // Rule ID 12609 //
5940 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5941 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5942 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5943 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
5944 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
5945 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
5946 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5947 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
5948 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5949 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5950 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5951 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5952 // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 686:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd) => (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
5953 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv4i32),
5954 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5955 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
5956 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
5957 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
5958 GIR_RootConstrainSelectedInstOperands,
5959 // GIR_Coverage, 12609,
5960 GIR_EraseRootFromParent_Done,
5961 // Label 353: @15604
5962 GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(15660), // Rule ID 12559 //
5963 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5964 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5965 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5966 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
5967 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
5968 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
5969 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
5970 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5971 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5972 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5973 // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 622:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd) => (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
5974 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i16_v4i32),
5975 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5976 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
5977 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
5978 GIR_RootConstrainSelectedInstOperands,
5979 // GIR_Coverage, 12559,
5980 GIR_EraseRootFromParent_Done,
5981 // Label 354: @15660
5982 GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(15716), // Rule ID 12571 //
5983 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5984 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5985 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5986 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
5987 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
5988 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
5989 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
5990 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5991 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
5992 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5993 // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 687:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd) => (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
5994 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i16_v4i32),
5995 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
5996 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
5997 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
5998 GIR_RootConstrainSelectedInstOperands,
5999 // GIR_Coverage, 12571,
6000 GIR_EraseRootFromParent_Done,
6001 // Label 355: @15716
6002 GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(15783), // Rule ID 12801 //
6003 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6004 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6005 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6006 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
6007 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6008 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6009 // MIs[1] imm
6010 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6011 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6012 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
6013 // MIs[2] Operand 1
6014 // No operand predicates
6015 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6016 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
6017 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6018 // (add:{ *:[v4i32] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V128:{ *:[v4i32] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (SSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6019 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i32_shift),
6020 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6021 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
6022 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6023 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6024 GIR_RootConstrainSelectedInstOperands,
6025 // GIR_Coverage, 12801,
6026 GIR_EraseRootFromParent_Done,
6027 // Label 356: @15783
6028 GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(15850), // Rule ID 12822 //
6029 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6030 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6031 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6032 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
6033 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6034 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6035 // MIs[1] imm
6036 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6037 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6038 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
6039 // MIs[2] Operand 1
6040 // No operand predicates
6041 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6042 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
6043 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6044 // (add:{ *:[v4i32] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V128:{ *:[v4i32] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (USRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6045 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i32_shift),
6046 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6047 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
6048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6049 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6050 GIR_RootConstrainSelectedInstOperands,
6051 // GIR_Coverage, 12822,
6052 GIR_EraseRootFromParent_Done,
6053 // Label 357: @15850
6054 GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(15919), // Rule ID 1354 //
6055 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6056 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6057 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6058 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6059 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
6060 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
6061 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
6062 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6063 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
6064 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6065 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6066 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6067 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 621:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
6068 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv4i32),
6069 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6070 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
6071 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
6072 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
6073 GIR_RootConstrainSelectedInstOperands,
6074 // GIR_Coverage, 1354,
6075 GIR_EraseRootFromParent_Done,
6076 // Label 358: @15919
6077 GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(15988), // Rule ID 1477 //
6078 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6079 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6080 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6081 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6082 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
6083 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
6084 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
6085 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
6086 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
6087 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6088 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6089 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6090 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 686:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
6091 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv4i32),
6092 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6093 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
6094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
6095 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
6096 GIR_RootConstrainSelectedInstOperands,
6097 // GIR_Coverage, 1477,
6098 GIR_EraseRootFromParent_Done,
6099 // Label 359: @15988
6100 GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(16044), // Rule ID 982 //
6101 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6102 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6103 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6104 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6105 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
6106 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
6107 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
6108 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
6109 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6110 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6111 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 622:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
6112 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i16_v4i32),
6113 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6114 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
6115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
6116 GIR_RootConstrainSelectedInstOperands,
6117 // GIR_Coverage, 982,
6118 GIR_EraseRootFromParent_Done,
6119 // Label 360: @16044
6120 GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(16100), // Rule ID 1043 //
6121 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6122 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6123 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6124 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6125 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
6126 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
6127 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
6128 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
6129 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6130 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6131 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 687:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
6132 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i16_v4i32),
6133 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6134 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
6135 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
6136 GIR_RootConstrainSelectedInstOperands,
6137 // GIR_Coverage, 1043,
6138 GIR_EraseRootFromParent_Done,
6139 // Label 361: @16100
6140 GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(16167), // Rule ID 2225 //
6141 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6142 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6143 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6144 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6145 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
6146 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6147 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6148 // MIs[1] imm
6149 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6150 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6151 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
6152 // MIs[2] Operand 1
6153 // No operand predicates
6154 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
6155 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6156 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>> => (SSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6157 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i32_shift),
6158 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6159 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
6160 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6161 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6162 GIR_RootConstrainSelectedInstOperands,
6163 // GIR_Coverage, 2225,
6164 GIR_EraseRootFromParent_Done,
6165 // Label 362: @16167
6166 GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(16234), // Rule ID 2284 //
6167 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6168 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6169 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6170 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6171 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
6172 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6173 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6174 // MIs[1] imm
6175 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6176 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6177 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
6178 // MIs[2] Operand 1
6179 // No operand predicates
6180 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
6181 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6182 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>> => (USRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6183 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i32_shift),
6184 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6185 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
6186 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6187 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6188 GIR_RootConstrainSelectedInstOperands,
6189 // GIR_Coverage, 2284,
6190 GIR_EraseRootFromParent_Done,
6191 // Label 363: @16234
6192 GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(16297), // Rule ID 1776 //
6193 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6194 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6195 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6196 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
6197 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
6198 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6199 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6200 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
6201 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
6202 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6203 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6204 // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
6205 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
6206 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6207 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6208 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6209 GIR_RootConstrainSelectedInstOperands,
6210 // GIR_Coverage, 1776,
6211 GIR_EraseRootFromParent_Done,
6212 // Label 364: @16297
6213 GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(16360), // Rule ID 1775 //
6214 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6215 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6216 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6217 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
6218 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
6219 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6220 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6221 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
6222 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
6223 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6224 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6225 // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
6226 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
6227 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6228 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6229 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6230 GIR_RootConstrainSelectedInstOperands,
6231 // GIR_Coverage, 1775,
6232 GIR_EraseRootFromParent_Done,
6233 // Label 365: @16360
6234 GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(16423), // Rule ID 1701 //
6235 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6236 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6237 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6238 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
6239 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
6240 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6241 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6242 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
6243 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
6244 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6245 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6246 // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
6247 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLv4i16_v4i32),
6248 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6249 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6251 GIR_RootConstrainSelectedInstOperands,
6252 // GIR_Coverage, 1701,
6253 GIR_EraseRootFromParent_Done,
6254 // Label 366: @16423
6255 GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(16486), // Rule ID 1774 //
6256 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6257 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6258 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6259 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
6260 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
6261 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6262 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6263 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
6264 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
6265 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6266 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6267 // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
6268 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
6269 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6271 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6272 GIR_RootConstrainSelectedInstOperands,
6273 // GIR_Coverage, 1774,
6274 GIR_EraseRootFromParent_Done,
6275 // Label 367: @16486
6276 GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(16549), // Rule ID 1773 //
6277 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6278 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6279 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6280 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
6281 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
6282 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6283 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6284 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
6285 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
6286 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6287 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6288 // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
6289 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
6290 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6293 GIR_RootConstrainSelectedInstOperands,
6294 // GIR_Coverage, 1773,
6295 GIR_EraseRootFromParent_Done,
6296 // Label 368: @16549
6297 GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(16610), // Rule ID 12648 //
6298 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6299 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6300 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6301 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
6302 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
6303 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
6304 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6305 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6306 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6307 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6308 // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd) => (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
6309 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_v4i32),
6310 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6311 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
6312 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6313 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
6314 GIR_RootConstrainSelectedInstOperands,
6315 // GIR_Coverage, 12648,
6316 GIR_EraseRootFromParent_Done,
6317 // Label 369: @16610
6318 GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(16671), // Rule ID 12678 //
6319 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6320 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6321 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6322 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
6323 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
6324 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
6325 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6326 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6327 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6328 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6329 // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd) => (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
6330 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_v4i32),
6331 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6332 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
6333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6334 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
6335 GIR_RootConstrainSelectedInstOperands,
6336 // GIR_Coverage, 12678,
6337 GIR_EraseRootFromParent_Done,
6338 // Label 370: @16671
6339 GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(16719), // Rule ID 12669 //
6340 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6341 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6342 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6343 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
6344 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
6345 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6346 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6347 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6348 // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn) => (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
6349 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
6350 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6351 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6352 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6353 GIR_RootConstrainSelectedInstOperands,
6354 // GIR_Coverage, 12669,
6355 GIR_EraseRootFromParent_Done,
6356 // Label 371: @16719
6357 GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(16767), // Rule ID 12558 //
6358 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6359 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6360 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6361 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
6362 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
6363 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6364 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6365 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6366 // (add:{ *:[v4i32] } (AArch64saddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd) => (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
6367 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i16_v4i32),
6368 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6369 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
6370 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6371 GIR_RootConstrainSelectedInstOperands,
6372 // GIR_Coverage, 12558,
6373 GIR_EraseRootFromParent_Done,
6374 // Label 372: @16767
6375 GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(16815), // Rule ID 12642 //
6376 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6377 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6378 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6379 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
6380 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
6381 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6382 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6383 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6384 // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn) => (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
6385 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv4i16_v4i32),
6386 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6387 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6389 GIR_RootConstrainSelectedInstOperands,
6390 // GIR_Coverage, 12642,
6391 GIR_EraseRootFromParent_Done,
6392 // Label 373: @16815
6393 GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(16863), // Rule ID 12570 //
6394 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6395 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6396 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6397 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
6398 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
6399 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6400 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6401 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6402 // (add:{ *:[v4i32] } (AArch64uaddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd) => (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
6403 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i16_v4i32),
6404 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6405 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
6406 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6407 GIR_RootConstrainSelectedInstOperands,
6408 // GIR_Coverage, 12570,
6409 GIR_EraseRootFromParent_Done,
6410 // Label 374: @16863
6411 GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(16911), // Rule ID 12668 //
6412 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6413 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6414 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6415 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
6416 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
6417 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6418 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6419 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6420 // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn) => (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
6421 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
6422 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6423 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6424 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6425 GIR_RootConstrainSelectedInstOperands,
6426 // GIR_Coverage, 12668,
6427 GIR_EraseRootFromParent_Done,
6428 // Label 375: @16911
6429 GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(16972), // Rule ID 1713 //
6430 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6431 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6432 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6433 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6434 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
6435 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
6436 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
6437 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6438 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6439 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6440 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
6441 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_v4i32),
6442 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6443 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
6444 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6445 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
6446 GIR_RootConstrainSelectedInstOperands,
6447 // GIR_Coverage, 1713,
6448 GIR_EraseRootFromParent_Done,
6449 // Label 376: @16972
6450 GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(17033), // Rule ID 1803 //
6451 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6452 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6453 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6454 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6455 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
6456 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
6457 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
6458 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6459 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6460 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6461 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
6462 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_v4i32),
6463 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6464 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
6465 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6466 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
6467 GIR_RootConstrainSelectedInstOperands,
6468 // GIR_Coverage, 1803,
6469 GIR_EraseRootFromParent_Done,
6470 // Label 377: @17033
6471 GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(17081), // Rule ID 1794 //
6472 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6473 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6474 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6475 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6476 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
6477 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
6478 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6479 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6480 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
6481 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
6482 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6483 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6485 GIR_RootConstrainSelectedInstOperands,
6486 // GIR_Coverage, 1794,
6487 GIR_EraseRootFromParent_Done,
6488 // Label 378: @17081
6489 GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(17129), // Rule ID 981 //
6490 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6491 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6492 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6493 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6494 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
6495 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
6496 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6497 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6498 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64saddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)) => (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
6499 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i16_v4i32),
6500 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6501 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
6502 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6503 GIR_RootConstrainSelectedInstOperands,
6504 // GIR_Coverage, 981,
6505 GIR_EraseRootFromParent_Done,
6506 // Label 379: @17129
6507 GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(17177), // Rule ID 1707 //
6508 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6509 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6510 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6511 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6512 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
6513 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
6514 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6515 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6516 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
6517 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv4i16_v4i32),
6518 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6519 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6520 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6521 GIR_RootConstrainSelectedInstOperands,
6522 // GIR_Coverage, 1707,
6523 GIR_EraseRootFromParent_Done,
6524 // Label 380: @17177
6525 GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(17225), // Rule ID 1042 //
6526 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6527 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6528 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6529 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6530 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
6531 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
6532 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6533 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6534 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64uaddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)) => (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
6535 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i16_v4i32),
6536 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6537 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
6538 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6539 GIR_RootConstrainSelectedInstOperands,
6540 // GIR_Coverage, 1042,
6541 GIR_EraseRootFromParent_Done,
6542 // Label 381: @17225
6543 GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(17273), // Rule ID 1793 //
6544 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6545 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6546 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6547 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6548 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
6549 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
6550 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6551 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6552 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
6553 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
6554 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6555 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6556 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6557 GIR_RootConstrainSelectedInstOperands,
6558 // GIR_Coverage, 1793,
6559 GIR_EraseRootFromParent_Done,
6560 // Label 382: @17273
6561 GIM_Try, /*On fail goto*//*Label 383*/ GIMT_Encode4(17300), // Rule ID 1092 //
6562 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6563 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6564 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6565 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6566 // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
6567 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
6568 GIR_RootConstrainSelectedInstOperands,
6569 // GIR_Coverage, 1092,
6570 GIR_Done,
6571 // Label 383: @17300
6572 GIM_Reject,
6573 // Label 320: @17301
6574 GIM_Reject,
6575 // Label 153: @17302
6576 GIM_Try, /*On fail goto*//*Label 384*/ GIMT_Encode4(17885),
6577 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
6578 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
6579 GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(17382), // Rule ID 12587 //
6580 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6581 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6582 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6583 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
6584 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
6585 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
6586 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
6587 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
6588 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6589 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6590 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6591 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6592 // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 621:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd) => (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
6593 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv8i8),
6594 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6595 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
6596 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
6597 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
6598 GIR_RootConstrainSelectedInstOperands,
6599 // GIR_Coverage, 12587,
6600 GIR_EraseRootFromParent_Done,
6601 // Label 385: @17382
6602 GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(17451), // Rule ID 12599 //
6603 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6604 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6605 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6606 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
6607 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
6608 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
6609 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
6610 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
6611 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6612 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6613 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6614 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6615 // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 686:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd) => (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
6616 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv8i8),
6617 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6618 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
6619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
6620 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
6621 GIR_RootConstrainSelectedInstOperands,
6622 // GIR_Coverage, 12599,
6623 GIR_EraseRootFromParent_Done,
6624 // Label 386: @17451
6625 GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(17518), // Rule ID 12791 //
6626 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6627 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6628 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6629 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
6630 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
6631 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6632 // MIs[1] imm
6633 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6634 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6635 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
6636 // MIs[2] Operand 1
6637 // No operand predicates
6638 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6639 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
6640 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6641 // (add:{ *:[v8i8] } (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V64:{ *:[v8i8] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (SSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
6642 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i8_shift),
6643 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6644 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
6645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6646 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6647 GIR_RootConstrainSelectedInstOperands,
6648 // GIR_Coverage, 12791,
6649 GIR_EraseRootFromParent_Done,
6650 // Label 387: @17518
6651 GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(17585), // Rule ID 12812 //
6652 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6653 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6654 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6655 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
6656 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
6657 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6658 // MIs[1] imm
6659 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6660 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6661 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
6662 // MIs[2] Operand 1
6663 // No operand predicates
6664 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6665 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
6666 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6667 // (add:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V64:{ *:[v8i8] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (USRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
6668 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i8_shift),
6669 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6670 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
6671 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6672 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6673 GIR_RootConstrainSelectedInstOperands,
6674 // GIR_Coverage, 12812,
6675 GIR_EraseRootFromParent_Done,
6676 // Label 388: @17585
6677 GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(17654), // Rule ID 1344 //
6678 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6679 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6680 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6681 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6682 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
6683 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
6684 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
6685 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
6686 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
6687 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6688 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6689 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6690 // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 621:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
6691 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv8i8),
6692 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6693 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
6694 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
6695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
6696 GIR_RootConstrainSelectedInstOperands,
6697 // GIR_Coverage, 1344,
6698 GIR_EraseRootFromParent_Done,
6699 // Label 389: @17654
6700 GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(17723), // Rule ID 1467 //
6701 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6702 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6703 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6704 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6705 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
6706 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
6707 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
6708 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
6709 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
6710 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6711 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6712 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6713 // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 686:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
6714 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv8i8),
6715 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6716 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
6717 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
6718 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
6719 GIR_RootConstrainSelectedInstOperands,
6720 // GIR_Coverage, 1467,
6721 GIR_EraseRootFromParent_Done,
6722 // Label 390: @17723
6723 GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(17790), // Rule ID 2215 //
6724 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6725 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6726 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6727 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6728 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
6729 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
6730 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6731 // MIs[1] imm
6732 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6733 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6734 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
6735 // MIs[2] Operand 1
6736 // No operand predicates
6737 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
6738 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6739 // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>> => (SSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
6740 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i8_shift),
6741 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6742 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
6743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6744 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6745 GIR_RootConstrainSelectedInstOperands,
6746 // GIR_Coverage, 2215,
6747 GIR_EraseRootFromParent_Done,
6748 // Label 391: @17790
6749 GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(17857), // Rule ID 2274 //
6750 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6751 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6752 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6753 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6754 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
6755 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
6756 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6757 // MIs[1] imm
6758 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6759 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6760 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
6761 // MIs[2] Operand 1
6762 // No operand predicates
6763 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
6764 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6765 // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>> => (USRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
6766 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i8_shift),
6767 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6768 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
6769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6770 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6771 GIR_RootConstrainSelectedInstOperands,
6772 // GIR_Coverage, 2274,
6773 GIR_EraseRootFromParent_Done,
6774 // Label 392: @17857
6775 GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(17884), // Rule ID 1087 //
6776 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6777 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6778 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6779 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
6780 // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
6781 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv8i8),
6782 GIR_RootConstrainSelectedInstOperands,
6783 // GIR_Coverage, 1087,
6784 GIR_Done,
6785 // Label 393: @17884
6786 GIM_Reject,
6787 // Label 384: @17885
6788 GIM_Reject,
6789 // Label 154: @17886
6790 GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(21323),
6791 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
6792 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
6793 GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(17984), // Rule ID 12631 //
6794 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6795 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6796 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6797 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
6798 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
6799 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6800 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
6801 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
6802 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
6803 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
6804 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
6805 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6806 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6807 GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
6808 GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
6809 // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 621:{ *:[iPTR] }, (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))), V128:{ *:[v8i16] }:$Rd) => (SABALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
6810 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv16i8_v8i16),
6811 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6812 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
6813 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
6814 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
6815 GIR_RootConstrainSelectedInstOperands,
6816 // GIR_Coverage, 12631,
6817 GIR_EraseRootFromParent_Done,
6818 // Label 395: @17984
6819 GIM_Try, /*On fail goto*//*Label 396*/ GIMT_Encode4(18071), // Rule ID 12655 //
6820 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6821 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6822 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6823 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
6824 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
6825 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6826 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
6827 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
6828 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
6829 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
6830 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
6831 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6832 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6833 GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
6834 GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
6835 // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 686:{ *:[iPTR] }, (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))), V128:{ *:[v8i16] }:$Rd) => (UABALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
6836 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv16i8_v8i16),
6837 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6838 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
6839 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
6840 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
6841 GIR_RootConstrainSelectedInstOperands,
6842 // GIR_Coverage, 12655,
6843 GIR_EraseRootFromParent_Done,
6844 // Label 396: @18071
6845 GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(18158), // Rule ID 1678 //
6846 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6847 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6848 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6849 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6850 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
6851 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
6852 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6853 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
6854 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
6855 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
6856 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
6857 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
6858 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6859 GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
6860 GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
6861 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 621:{ *:[iPTR] }, (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))) => (SABALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
6862 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv16i8_v8i16),
6863 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6864 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
6865 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
6866 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
6867 GIR_RootConstrainSelectedInstOperands,
6868 // GIR_Coverage, 1678,
6869 GIR_EraseRootFromParent_Done,
6870 // Label 397: @18158
6871 GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(18245), // Rule ID 1756 //
6872 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6873 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6874 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6875 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6876 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
6877 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
6878 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6879 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
6880 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
6881 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
6882 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
6883 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
6884 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6885 GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
6886 GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
6887 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 686:{ *:[iPTR] }, (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))) => (UABALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
6888 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv16i8_v8i16),
6889 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
6890 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
6891 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
6892 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
6893 GIR_RootConstrainSelectedInstOperands,
6894 // GIR_Coverage, 1756,
6895 GIR_EraseRootFromParent_Done,
6896 // Label 398: @18245
6897 GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(18314), // Rule ID 1772 //
6898 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6899 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6900 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6901 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
6902 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
6903 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6904 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
6905 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
6906 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6907 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
6908 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
6909 // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (UADDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
6910 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv16i8_v8i16),
6911 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6912 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
6913 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
6914 GIR_RootConstrainSelectedInstOperands,
6915 // GIR_Coverage, 1772,
6916 GIR_EraseRootFromParent_Done,
6917 // Label 399: @18314
6918 GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(18383), // Rule ID 1771 //
6919 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6920 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6921 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6922 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
6923 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
6924 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6925 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
6926 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
6927 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6928 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
6929 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
6930 // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (UADDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
6931 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv16i8_v8i16),
6932 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6933 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
6934 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
6935 GIR_RootConstrainSelectedInstOperands,
6936 // GIR_Coverage, 1771,
6937 GIR_EraseRootFromParent_Done,
6938 // Label 400: @18383
6939 GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(18452), // Rule ID 1700 //
6940 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6941 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6942 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6943 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
6944 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
6945 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6946 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
6947 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
6948 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6949 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
6950 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
6951 // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (SADDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
6952 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLv16i8_v8i16),
6953 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6954 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
6955 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
6956 GIR_RootConstrainSelectedInstOperands,
6957 // GIR_Coverage, 1700,
6958 GIR_EraseRootFromParent_Done,
6959 // Label 401: @18452
6960 GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(18521), // Rule ID 1770 //
6961 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6962 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6963 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6964 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
6965 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
6966 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6967 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
6968 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
6969 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6970 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
6971 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
6972 // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (UADDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
6973 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv16i8_v8i16),
6974 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6975 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
6976 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
6977 GIR_RootConstrainSelectedInstOperands,
6978 // GIR_Coverage, 1770,
6979 GIR_EraseRootFromParent_Done,
6980 // Label 402: @18521
6981 GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(18590), // Rule ID 1769 //
6982 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6983 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
6984 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6985 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
6986 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
6987 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6988 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
6989 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
6990 GIM_CheckIsSafeToFold, /*NumInsns*/2,
6991 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
6992 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
6993 // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (UADDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
6994 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv16i8_v8i16),
6995 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6996 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
6997 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
6998 GIR_RootConstrainSelectedInstOperands,
6999 // GIR_Coverage, 1769,
7000 GIR_EraseRootFromParent_Done,
7001 // Label 403: @18590
7002 GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(18657), // Rule ID 12647 //
7003 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7004 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7005 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7006 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
7007 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7008 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
7009 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7010 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7011 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
7012 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
7013 // (add:{ *:[v8i16] } (AArch64smull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd) => (SMLALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
7014 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv16i8_v8i16),
7015 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7016 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
7017 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
7018 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
7019 GIR_RootConstrainSelectedInstOperands,
7020 // GIR_Coverage, 12647,
7021 GIR_EraseRootFromParent_Done,
7022 // Label 404: @18657
7023 GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(18724), // Rule ID 12677 //
7024 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7025 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7026 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7027 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
7028 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7029 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
7030 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7031 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7032 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
7033 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
7034 // (add:{ *:[v8i16] } (AArch64umull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd) => (UMLALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
7035 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv16i8_v8i16),
7036 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7037 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
7038 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
7039 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
7040 GIR_RootConstrainSelectedInstOperands,
7041 // GIR_Coverage, 12677,
7042 GIR_EraseRootFromParent_Done,
7043 // Label 405: @18724
7044 GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(18791), // Rule ID 1712 //
7045 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7046 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7047 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7048 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7049 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
7050 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7051 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
7052 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7053 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
7054 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
7055 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64smull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (SMLALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
7056 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv16i8_v8i16),
7057 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7058 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
7059 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
7060 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
7061 GIR_RootConstrainSelectedInstOperands,
7062 // GIR_Coverage, 1712,
7063 GIR_EraseRootFromParent_Done,
7064 // Label 406: @18791
7065 GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(18858), // Rule ID 1802 //
7066 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7067 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7068 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7069 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7070 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
7071 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7072 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
7073 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7074 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
7075 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
7076 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64umull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (UMLALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
7077 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv16i8_v8i16),
7078 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7079 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
7080 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
7081 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
7082 GIR_RootConstrainSelectedInstOperands,
7083 // GIR_Coverage, 1802,
7084 GIR_EraseRootFromParent_Done,
7085 // Label 407: @18858
7086 GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(18939), // Rule ID 12629 //
7087 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7088 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7089 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7090 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
7091 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7092 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7093 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
7094 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
7095 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
7096 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
7097 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
7098 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7099 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7100 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7101 GIM_CheckIsSafeToFold, /*NumInsns*/2,
7102 // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 621:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd) => (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
7103 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv8i8_v8i16),
7104 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7105 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
7106 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
7107 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
7108 GIR_RootConstrainSelectedInstOperands,
7109 // GIR_Coverage, 12629,
7110 GIR_EraseRootFromParent_Done,
7111 // Label 408: @18939
7112 GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(19020), // Rule ID 12653 //
7113 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7114 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7115 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7116 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
7117 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7118 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7119 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
7120 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
7121 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
7122 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
7123 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
7124 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7125 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7126 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7127 GIM_CheckIsSafeToFold, /*NumInsns*/2,
7128 // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 686:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd) => (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
7129 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv8i8_v8i16),
7130 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7131 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
7132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
7133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
7134 GIR_RootConstrainSelectedInstOperands,
7135 // GIR_Coverage, 12653,
7136 GIR_EraseRootFromParent_Done,
7137 // Label 409: @19020
7138 GIM_Try, /*On fail goto*//*Label 410*/ GIMT_Encode4(19101), // Rule ID 1676 //
7139 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7140 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7141 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7142 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7143 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
7144 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7145 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7146 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
7147 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
7148 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
7149 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
7150 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
7151 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7152 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7153 GIM_CheckIsSafeToFold, /*NumInsns*/2,
7154 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 621:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))) => (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
7155 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv8i8_v8i16),
7156 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7157 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
7158 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
7159 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
7160 GIR_RootConstrainSelectedInstOperands,
7161 // GIR_Coverage, 1676,
7162 GIR_EraseRootFromParent_Done,
7163 // Label 410: @19101
7164 GIM_Try, /*On fail goto*//*Label 411*/ GIMT_Encode4(19182), // Rule ID 1754 //
7165 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7166 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7167 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7168 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7169 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
7170 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7171 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7172 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
7173 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
7174 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
7175 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
7176 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
7177 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7178 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7179 GIM_CheckIsSafeToFold, /*NumInsns*/2,
7180 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 686:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))) => (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
7181 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv8i8_v8i16),
7182 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7183 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
7184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rn
7185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Rm
7186 GIR_RootConstrainSelectedInstOperands,
7187 // GIR_Coverage, 1754,
7188 GIR_EraseRootFromParent_Done,
7189 // Label 411: @19182
7190 GIM_Try, /*On fail goto*//*Label 412*/ GIMT_Encode4(19233), // Rule ID 12667 //
7191 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7192 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7193 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7194 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
7195 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7196 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7197 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7198 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
7199 // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)), V128:{ *:[v8i16] }:$Rn) => (UADDWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
7200 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv16i8_v8i16),
7201 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7202 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
7203 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
7204 GIR_RootConstrainSelectedInstOperands,
7205 // GIR_Coverage, 12667,
7206 GIR_EraseRootFromParent_Done,
7207 // Label 412: @19233
7208 GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(19284), // Rule ID 12641 //
7209 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7210 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7211 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7212 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
7213 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7214 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7215 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7216 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
7217 // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)), V128:{ *:[v8i16] }:$Rn) => (SADDWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
7218 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv16i8_v8i16),
7219 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7220 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
7221 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
7222 GIR_RootConstrainSelectedInstOperands,
7223 // GIR_Coverage, 12641,
7224 GIR_EraseRootFromParent_Done,
7225 // Label 413: @19284
7226 GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(19335), // Rule ID 12666 //
7227 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7228 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7229 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7230 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
7231 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7232 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7233 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7234 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
7235 // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)), V128:{ *:[v8i16] }:$Rn) => (UADDWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
7236 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv16i8_v8i16),
7237 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7238 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
7239 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
7240 GIR_RootConstrainSelectedInstOperands,
7241 // GIR_Coverage, 12666,
7242 GIR_EraseRootFromParent_Done,
7243 // Label 414: @19335
7244 GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(19386), // Rule ID 1792 //
7245 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7246 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7247 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7248 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7249 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
7250 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7251 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7252 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
7253 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (UADDWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
7254 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv16i8_v8i16),
7255 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7256 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7257 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
7258 GIR_RootConstrainSelectedInstOperands,
7259 // GIR_Coverage, 1792,
7260 GIR_EraseRootFromParent_Done,
7261 // Label 415: @19386
7262 GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(19437), // Rule ID 1706 //
7263 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7264 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7265 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7266 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7267 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
7268 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7269 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7270 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
7271 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (SADDWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
7272 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv16i8_v8i16),
7273 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7274 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7275 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
7276 GIR_RootConstrainSelectedInstOperands,
7277 // GIR_Coverage, 1706,
7278 GIR_EraseRootFromParent_Done,
7279 // Label 416: @19437
7280 GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(19488), // Rule ID 1791 //
7281 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7282 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7283 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7284 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7285 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
7286 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7287 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7288 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
7289 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (UADDWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
7290 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv16i8_v8i16),
7291 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7292 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7293 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
7294 GIR_RootConstrainSelectedInstOperands,
7295 // GIR_Coverage, 1791,
7296 GIR_EraseRootFromParent_Done,
7297 // Label 417: @19488
7298 GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(19557), // Rule ID 12593 //
7299 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7300 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7301 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7302 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
7303 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
7304 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
7305 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
7306 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
7307 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7308 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7309 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7310 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7311 // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 621:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd) => (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
7312 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv8i16),
7313 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7314 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
7315 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
7316 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
7317 GIR_RootConstrainSelectedInstOperands,
7318 // GIR_Coverage, 12593,
7319 GIR_EraseRootFromParent_Done,
7320 // Label 418: @19557
7321 GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(19626), // Rule ID 12605 //
7322 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7323 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7324 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7325 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
7326 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
7327 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
7328 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
7329 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
7330 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7331 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7332 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7333 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7334 // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 686:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd) => (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
7335 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv8i16),
7336 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7337 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
7338 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
7339 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
7340 GIR_RootConstrainSelectedInstOperands,
7341 // GIR_Coverage, 12605,
7342 GIR_EraseRootFromParent_Done,
7343 // Label 419: @19626
7344 GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(19682), // Rule ID 12555 //
7345 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7346 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7347 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7348 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
7349 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
7350 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
7351 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
7352 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7353 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7354 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7355 // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 622:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd) => (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
7356 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv16i8_v8i16),
7357 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7358 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
7359 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
7360 GIR_RootConstrainSelectedInstOperands,
7361 // GIR_Coverage, 12555,
7362 GIR_EraseRootFromParent_Done,
7363 // Label 420: @19682
7364 GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(19738), // Rule ID 12567 //
7365 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7366 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7367 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7368 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
7369 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
7370 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
7371 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
7372 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7373 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7374 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7375 // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 687:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd) => (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
7376 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv16i8_v8i16),
7377 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7378 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
7379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
7380 GIR_RootConstrainSelectedInstOperands,
7381 // GIR_Coverage, 12567,
7382 GIR_EraseRootFromParent_Done,
7383 // Label 421: @19738
7384 GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(19805), // Rule ID 12797 //
7385 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7386 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7387 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7388 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
7389 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
7390 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7391 // MIs[1] imm
7392 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7393 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7394 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
7395 // MIs[2] Operand 1
7396 // No operand predicates
7397 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7398 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
7399 GIM_CheckIsSafeToFold, /*NumInsns*/2,
7400 // (add:{ *:[v8i16] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V128:{ *:[v8i16] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (SSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
7401 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i16_shift),
7402 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7403 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
7404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7405 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7406 GIR_RootConstrainSelectedInstOperands,
7407 // GIR_Coverage, 12797,
7408 GIR_EraseRootFromParent_Done,
7409 // Label 422: @19805
7410 GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(19872), // Rule ID 12818 //
7411 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7412 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7413 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7414 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
7415 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
7416 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7417 // MIs[1] imm
7418 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7419 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7420 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
7421 // MIs[2] Operand 1
7422 // No operand predicates
7423 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7424 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
7425 GIM_CheckIsSafeToFold, /*NumInsns*/2,
7426 // (add:{ *:[v8i16] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V128:{ *:[v8i16] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (USRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
7427 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i16_shift),
7428 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7429 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
7430 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7431 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7432 GIR_RootConstrainSelectedInstOperands,
7433 // GIR_Coverage, 12818,
7434 GIR_EraseRootFromParent_Done,
7435 // Label 423: @19872
7436 GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(19941), // Rule ID 1350 //
7437 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7438 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7439 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7440 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7441 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
7442 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
7443 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
7444 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
7445 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
7446 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7447 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7448 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7449 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 621:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
7450 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv8i16),
7451 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7452 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
7453 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
7454 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
7455 GIR_RootConstrainSelectedInstOperands,
7456 // GIR_Coverage, 1350,
7457 GIR_EraseRootFromParent_Done,
7458 // Label 424: @19941
7459 GIM_Try, /*On fail goto*//*Label 425*/ GIMT_Encode4(20010), // Rule ID 1473 //
7460 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7461 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7462 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7463 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7464 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
7465 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
7466 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
7467 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
7468 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
7469 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7470 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7471 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7472 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 686:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
7473 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv8i16),
7474 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7475 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
7476 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
7477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
7478 GIR_RootConstrainSelectedInstOperands,
7479 // GIR_Coverage, 1473,
7480 GIR_EraseRootFromParent_Done,
7481 // Label 425: @20010
7482 GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(20066), // Rule ID 978 //
7483 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7484 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7485 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7486 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7487 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
7488 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
7489 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
7490 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
7491 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7492 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7493 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 622:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)) => (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
7494 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv16i8_v8i16),
7495 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7496 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
7497 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
7498 GIR_RootConstrainSelectedInstOperands,
7499 // GIR_Coverage, 978,
7500 GIR_EraseRootFromParent_Done,
7501 // Label 426: @20066
7502 GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(20122), // Rule ID 1039 //
7503 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7504 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7505 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7506 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7507 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
7508 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
7509 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
7510 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
7511 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7512 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7513 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 687:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)) => (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
7514 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv16i8_v8i16),
7515 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7516 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
7517 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
7518 GIR_RootConstrainSelectedInstOperands,
7519 // GIR_Coverage, 1039,
7520 GIR_EraseRootFromParent_Done,
7521 // Label 427: @20122
7522 GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(20189), // Rule ID 2221 //
7523 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7524 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7525 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7526 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7527 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
7528 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
7529 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7530 // MIs[1] imm
7531 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7532 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7533 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
7534 // MIs[2] Operand 1
7535 // No operand predicates
7536 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
7537 GIM_CheckIsSafeToFold, /*NumInsns*/2,
7538 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>> => (SSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
7539 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i16_shift),
7540 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7541 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
7542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7543 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7544 GIR_RootConstrainSelectedInstOperands,
7545 // GIR_Coverage, 2221,
7546 GIR_EraseRootFromParent_Done,
7547 // Label 428: @20189
7548 GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(20256), // Rule ID 2280 //
7549 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7550 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7551 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7552 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7553 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
7554 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
7555 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7556 // MIs[1] imm
7557 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7558 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7559 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
7560 // MIs[2] Operand 1
7561 // No operand predicates
7562 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
7563 GIM_CheckIsSafeToFold, /*NumInsns*/2,
7564 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>> => (USRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
7565 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i16_shift),
7566 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7567 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
7568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7569 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7570 GIR_RootConstrainSelectedInstOperands,
7571 // GIR_Coverage, 2280,
7572 GIR_EraseRootFromParent_Done,
7573 // Label 429: @20256
7574 GIM_Try, /*On fail goto*//*Label 430*/ GIMT_Encode4(20319), // Rule ID 1768 //
7575 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7576 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7577 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7578 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
7579 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7580 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7581 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7582 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
7583 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
7584 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7585 GIM_CheckIsSafeToFold, /*NumInsns*/2,
7586 // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
7587 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
7588 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7589 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7590 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7591 GIR_RootConstrainSelectedInstOperands,
7592 // GIR_Coverage, 1768,
7593 GIR_EraseRootFromParent_Done,
7594 // Label 430: @20319
7595 GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(20382), // Rule ID 1767 //
7596 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7597 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7598 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7599 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
7600 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7601 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7602 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7603 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
7604 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
7605 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7606 GIM_CheckIsSafeToFold, /*NumInsns*/2,
7607 // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
7608 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
7609 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7610 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7611 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7612 GIR_RootConstrainSelectedInstOperands,
7613 // GIR_Coverage, 1767,
7614 GIR_EraseRootFromParent_Done,
7615 // Label 431: @20382
7616 GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(20445), // Rule ID 1699 //
7617 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7618 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7619 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7620 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
7621 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7622 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7623 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7624 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
7625 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
7626 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7627 GIM_CheckIsSafeToFold, /*NumInsns*/2,
7628 // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
7629 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLv8i8_v8i16),
7630 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7631 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7632 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7633 GIR_RootConstrainSelectedInstOperands,
7634 // GIR_Coverage, 1699,
7635 GIR_EraseRootFromParent_Done,
7636 // Label 432: @20445
7637 GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(20508), // Rule ID 1766 //
7638 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7639 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7640 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7641 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
7642 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7643 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7644 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7645 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
7646 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
7647 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7648 GIM_CheckIsSafeToFold, /*NumInsns*/2,
7649 // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
7650 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
7651 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7652 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7653 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7654 GIR_RootConstrainSelectedInstOperands,
7655 // GIR_Coverage, 1766,
7656 GIR_EraseRootFromParent_Done,
7657 // Label 433: @20508
7658 GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(20571), // Rule ID 1765 //
7659 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7660 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7661 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7662 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
7663 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7664 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7665 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7666 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
7667 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
7668 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7669 GIM_CheckIsSafeToFold, /*NumInsns*/2,
7670 // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
7671 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
7672 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7675 GIR_RootConstrainSelectedInstOperands,
7676 // GIR_Coverage, 1765,
7677 GIR_EraseRootFromParent_Done,
7678 // Label 434: @20571
7679 GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(20632), // Rule ID 12646 //
7680 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7681 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7682 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7683 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
7684 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7685 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
7686 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7687 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7688 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7689 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7690 // (add:{ *:[v8i16] } (AArch64smull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd) => (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
7691 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i8_v8i16),
7692 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7693 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
7694 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
7696 GIR_RootConstrainSelectedInstOperands,
7697 // GIR_Coverage, 12646,
7698 GIR_EraseRootFromParent_Done,
7699 // Label 435: @20632
7700 GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(20693), // Rule ID 12676 //
7701 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7702 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7703 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7704 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
7705 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7706 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
7707 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7708 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7709 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7710 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7711 // (add:{ *:[v8i16] } (AArch64umull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd) => (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
7712 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i8_v8i16),
7713 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7714 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
7715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
7717 GIR_RootConstrainSelectedInstOperands,
7718 // GIR_Coverage, 12676,
7719 GIR_EraseRootFromParent_Done,
7720 // Label 436: @20693
7721 GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(20741), // Rule ID 12665 //
7722 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7723 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7724 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7725 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
7726 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7727 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7728 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7729 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7730 // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn) => (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
7731 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
7732 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7733 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
7734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7735 GIR_RootConstrainSelectedInstOperands,
7736 // GIR_Coverage, 12665,
7737 GIR_EraseRootFromParent_Done,
7738 // Label 437: @20741
7739 GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(20789), // Rule ID 12554 //
7740 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7741 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7742 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7743 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
7744 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
7745 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7746 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7747 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7748 // (add:{ *:[v8i16] } (AArch64saddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd) => (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
7749 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv16i8_v8i16),
7750 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7751 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
7752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7753 GIR_RootConstrainSelectedInstOperands,
7754 // GIR_Coverage, 12554,
7755 GIR_EraseRootFromParent_Done,
7756 // Label 438: @20789
7757 GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(20837), // Rule ID 12640 //
7758 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7759 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7760 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7761 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
7762 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7763 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7764 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7765 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7766 // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn) => (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
7767 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv8i8_v8i16),
7768 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7769 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
7770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7771 GIR_RootConstrainSelectedInstOperands,
7772 // GIR_Coverage, 12640,
7773 GIR_EraseRootFromParent_Done,
7774 // Label 439: @20837
7775 GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(20885), // Rule ID 12566 //
7776 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7777 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7778 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7779 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
7780 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
7781 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7782 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7783 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7784 // (add:{ *:[v8i16] } (AArch64uaddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd) => (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
7785 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv16i8_v8i16),
7786 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7787 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
7788 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7789 GIR_RootConstrainSelectedInstOperands,
7790 // GIR_Coverage, 12566,
7791 GIR_EraseRootFromParent_Done,
7792 // Label 440: @20885
7793 GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(20933), // Rule ID 12664 //
7794 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7795 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7796 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7797 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
7798 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7799 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7800 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7801 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7802 // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn) => (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
7803 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
7804 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7805 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
7806 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7807 GIR_RootConstrainSelectedInstOperands,
7808 // GIR_Coverage, 12664,
7809 GIR_EraseRootFromParent_Done,
7810 // Label 441: @20933
7811 GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(20994), // Rule ID 1711 //
7812 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7813 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7814 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7815 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7816 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
7817 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7818 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
7819 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7820 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7821 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7822 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64smull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
7823 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i8_v8i16),
7824 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7825 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
7826 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
7828 GIR_RootConstrainSelectedInstOperands,
7829 // GIR_Coverage, 1711,
7830 GIR_EraseRootFromParent_Done,
7831 // Label 442: @20994
7832 GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(21055), // Rule ID 1801 //
7833 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7834 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7835 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7836 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7837 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
7838 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7839 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
7840 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7841 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7842 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7843 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64umull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
7844 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i8_v8i16),
7845 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7846 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
7847 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7848 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
7849 GIR_RootConstrainSelectedInstOperands,
7850 // GIR_Coverage, 1801,
7851 GIR_EraseRootFromParent_Done,
7852 // Label 443: @21055
7853 GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(21103), // Rule ID 1790 //
7854 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7855 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7856 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7857 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7858 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
7859 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7860 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7861 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7862 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
7863 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
7864 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7865 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7866 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7867 GIR_RootConstrainSelectedInstOperands,
7868 // GIR_Coverage, 1790,
7869 GIR_EraseRootFromParent_Done,
7870 // Label 444: @21103
7871 GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(21151), // Rule ID 977 //
7872 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7873 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7874 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7875 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7876 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
7877 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
7878 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7879 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7880 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64saddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)) => (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
7881 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv16i8_v8i16),
7882 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7883 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
7884 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7885 GIR_RootConstrainSelectedInstOperands,
7886 // GIR_Coverage, 977,
7887 GIR_EraseRootFromParent_Done,
7888 // Label 445: @21151
7889 GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(21199), // Rule ID 1705 //
7890 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7891 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7892 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7893 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7894 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
7895 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7896 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7897 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7898 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
7899 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv8i8_v8i16),
7900 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7901 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7902 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7903 GIR_RootConstrainSelectedInstOperands,
7904 // GIR_Coverage, 1705,
7905 GIR_EraseRootFromParent_Done,
7906 // Label 446: @21199
7907 GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(21247), // Rule ID 1038 //
7908 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7909 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7910 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7911 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7912 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
7913 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
7914 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7915 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7916 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64uaddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)) => (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
7917 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv16i8_v8i16),
7918 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7919 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
7920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7921 GIR_RootConstrainSelectedInstOperands,
7922 // GIR_Coverage, 1038,
7923 GIR_EraseRootFromParent_Done,
7924 // Label 447: @21247
7925 GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(21295), // Rule ID 1789 //
7926 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7927 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7928 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7929 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7930 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
7931 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
7932 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
7933 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7934 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
7935 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
7936 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7937 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7939 GIR_RootConstrainSelectedInstOperands,
7940 // GIR_Coverage, 1789,
7941 GIR_EraseRootFromParent_Done,
7942 // Label 448: @21295
7943 GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(21322), // Rule ID 1090 //
7944 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7945 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7946 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7947 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7948 // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
7949 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv8i16),
7950 GIR_RootConstrainSelectedInstOperands,
7951 // GIR_Coverage, 1090,
7952 GIR_Done,
7953 // Label 449: @21322
7954 GIM_Reject,
7955 // Label 394: @21323
7956 GIM_Reject,
7957 // Label 155: @21324
7958 GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(21907),
7959 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
7960 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
7961 GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(21404), // Rule ID 12589 //
7962 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7963 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7964 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7965 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
7966 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
7967 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
7968 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
7969 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
7970 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7971 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7972 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7973 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7974 // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 621:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd) => (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
7975 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv16i8),
7976 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7977 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
7978 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
7979 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
7980 GIR_RootConstrainSelectedInstOperands,
7981 // GIR_Coverage, 12589,
7982 GIR_EraseRootFromParent_Done,
7983 // Label 451: @21404
7984 GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(21473), // Rule ID 12601 //
7985 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7986 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7987 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7988 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
7989 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
7990 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
7991 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
7992 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
7993 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7994 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7995 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
7996 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7997 // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 686:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd) => (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
7998 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv16i8),
7999 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
8000 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
8001 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
8002 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
8003 GIR_RootConstrainSelectedInstOperands,
8004 // GIR_Coverage, 12601,
8005 GIR_EraseRootFromParent_Done,
8006 // Label 452: @21473
8007 GIM_Try, /*On fail goto*//*Label 453*/ GIMT_Encode4(21540), // Rule ID 12793 //
8008 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8009 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8010 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8011 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
8012 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
8013 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8014 // MIs[1] imm
8015 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8016 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8017 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
8018 // MIs[2] Operand 1
8019 // No operand predicates
8020 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8021 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
8022 GIM_CheckIsSafeToFold, /*NumInsns*/2,
8023 // (add:{ *:[v16i8] } (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V128:{ *:[v16i8] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (SSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
8024 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv16i8_shift),
8025 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
8026 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
8027 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8028 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
8029 GIR_RootConstrainSelectedInstOperands,
8030 // GIR_Coverage, 12793,
8031 GIR_EraseRootFromParent_Done,
8032 // Label 453: @21540
8033 GIM_Try, /*On fail goto*//*Label 454*/ GIMT_Encode4(21607), // Rule ID 12814 //
8034 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8035 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8036 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8037 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
8038 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
8039 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8040 // MIs[1] imm
8041 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8042 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8043 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
8044 // MIs[2] Operand 1
8045 // No operand predicates
8046 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8047 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
8048 GIM_CheckIsSafeToFold, /*NumInsns*/2,
8049 // (add:{ *:[v16i8] } (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V128:{ *:[v16i8] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (USRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
8050 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv16i8_shift),
8051 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
8052 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
8053 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8054 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
8055 GIR_RootConstrainSelectedInstOperands,
8056 // GIR_Coverage, 12814,
8057 GIR_EraseRootFromParent_Done,
8058 // Label 454: @21607
8059 GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(21676), // Rule ID 1346 //
8060 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8061 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8062 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8063 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8064 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
8065 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
8066 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
8067 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
8068 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
8069 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8070 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8071 GIM_CheckIsSafeToFold, /*NumInsns*/1,
8072 // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 621:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)) => (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
8073 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv16i8),
8074 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
8075 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
8076 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
8077 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
8078 GIR_RootConstrainSelectedInstOperands,
8079 // GIR_Coverage, 1346,
8080 GIR_EraseRootFromParent_Done,
8081 // Label 455: @21676
8082 GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(21745), // Rule ID 1469 //
8083 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8084 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8085 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8086 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8087 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
8088 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
8089 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
8090 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
8091 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
8092 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8093 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8094 GIM_CheckIsSafeToFold, /*NumInsns*/1,
8095 // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (intrinsic_wo_chain:{ *:[v16i8] } 686:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)) => (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
8096 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv16i8),
8097 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
8098 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
8099 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
8100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
8101 GIR_RootConstrainSelectedInstOperands,
8102 // GIR_Coverage, 1469,
8103 GIR_EraseRootFromParent_Done,
8104 // Label 456: @21745
8105 GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(21812), // Rule ID 2217 //
8106 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8107 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8108 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8109 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8110 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
8111 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
8112 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8113 // MIs[1] imm
8114 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8115 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8116 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
8117 // MIs[2] Operand 1
8118 // No operand predicates
8119 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
8120 GIM_CheckIsSafeToFold, /*NumInsns*/2,
8121 // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>> => (SSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
8122 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv16i8_shift),
8123 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
8124 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
8125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8126 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
8127 GIR_RootConstrainSelectedInstOperands,
8128 // GIR_Coverage, 2217,
8129 GIR_EraseRootFromParent_Done,
8130 // Label 457: @21812
8131 GIM_Try, /*On fail goto*//*Label 458*/ GIMT_Encode4(21879), // Rule ID 2276 //
8132 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8133 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8134 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8135 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8136 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
8137 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
8138 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8139 // MIs[1] imm
8140 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8141 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8142 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
8143 // MIs[2] Operand 1
8144 // No operand predicates
8145 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
8146 GIM_CheckIsSafeToFold, /*NumInsns*/2,
8147 // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>> => (USRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
8148 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv16i8_shift),
8149 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
8150 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
8151 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8152 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
8153 GIR_RootConstrainSelectedInstOperands,
8154 // GIR_Coverage, 2276,
8155 GIR_EraseRootFromParent_Done,
8156 // Label 458: @21879
8157 GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(21906), // Rule ID 1088 //
8158 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8159 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8160 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8161 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
8162 // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
8163 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv16i8),
8164 GIR_RootConstrainSelectedInstOperands,
8165 // GIR_Coverage, 1088,
8166 GIR_Done,
8167 // Label 459: @21906
8168 GIM_Reject,
8169 // Label 450: @21907
8170 GIM_Reject,
8171 // Label 156: @21908
8172 GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(21933), // Rule ID 2684 //
8173 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
8174 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
8175 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
8176 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
8177 // (add:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (ADD_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
8178 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADD_ZZZ_D),
8179 GIR_RootConstrainSelectedInstOperands,
8180 // GIR_Coverage, 2684,
8181 GIR_Done,
8182 // Label 460: @21933
8183 GIM_Reject,
8184 // Label 157: @21934
8185 GIM_Try, /*On fail goto*//*Label 461*/ GIMT_Encode4(21959), // Rule ID 2683 //
8186 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
8187 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
8188 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
8189 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
8190 // (add:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (ADD_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
8191 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADD_ZZZ_S),
8192 GIR_RootConstrainSelectedInstOperands,
8193 // GIR_Coverage, 2683,
8194 GIR_Done,
8195 // Label 461: @21959
8196 GIM_Reject,
8197 // Label 158: @21960
8198 GIM_Try, /*On fail goto*//*Label 462*/ GIMT_Encode4(21985), // Rule ID 2682 //
8199 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
8200 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
8201 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
8202 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
8203 // (add:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (ADD_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
8204 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADD_ZZZ_H),
8205 GIR_RootConstrainSelectedInstOperands,
8206 // GIR_Coverage, 2682,
8207 GIR_Done,
8208 // Label 462: @21985
8209 GIM_Reject,
8210 // Label 159: @21986
8211 GIM_Try, /*On fail goto*//*Label 463*/ GIMT_Encode4(22011), // Rule ID 2681 //
8212 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
8213 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
8214 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
8215 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
8216 // (add:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (ADD_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
8217 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADD_ZZZ_B),
8218 GIR_RootConstrainSelectedInstOperands,
8219 // GIR_Coverage, 2681,
8220 GIR_Done,
8221 // Label 463: @22011
8222 GIM_Reject,
8223 // Label 160: @22012
8224 GIM_Reject,
8225 // Label 1: @22013
8226 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(24), /*)*//*default:*//*Label 477*/ GIMT_Encode4(29002),
8227 /*GILLT_s32*//*Label 464*/ GIMT_Encode4(22112),
8228 /*GILLT_s64*//*Label 465*/ GIMT_Encode4(22966), GIMT_Encode4(0),
8229 /*GILLT_v2s32*//*Label 466*/ GIMT_Encode4(24270),
8230 /*GILLT_v2s64*//*Label 467*/ GIMT_Encode4(24345),
8231 /*GILLT_v4s16*//*Label 468*/ GIMT_Encode4(25905),
8232 /*GILLT_v4s32*//*Label 469*/ GIMT_Encode4(25980),
8233 /*GILLT_v8s8*//*Label 470*/ GIMT_Encode4(27540),
8234 /*GILLT_v8s16*//*Label 471*/ GIMT_Encode4(27615),
8235 /*GILLT_v16s8*//*Label 472*/ GIMT_Encode4(28823), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
8236 /*GILLT_nxv2s64*//*Label 473*/ GIMT_Encode4(28898), GIMT_Encode4(0), GIMT_Encode4(0),
8237 /*GILLT_nxv4s32*//*Label 474*/ GIMT_Encode4(28924), GIMT_Encode4(0),
8238 /*GILLT_nxv8s16*//*Label 475*/ GIMT_Encode4(28950), GIMT_Encode4(0),
8239 /*GILLT_nxv16s8*//*Label 476*/ GIMT_Encode4(28976),
8240 // Label 464: @22112
8241 GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(22965),
8242 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
8243 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8244 GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(22275), // Rule ID 9625 //
8245 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
8246 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8247 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8248 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8249 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
8250 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
8251 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8252 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
8253 GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
8254 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
8255 // MIs[2] pattern
8256 GIM_CheckIsImm, /*MI*/2, /*Op*/2,
8257 GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
8258 GIM_CheckIsSafeToFold, /*NumInsns*/2,
8259 // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1148:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))) => (EXTRACT_SUBREG:{ *:[i32] } (DECB_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
8260 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
8261 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
8262 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
8263 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
8264 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8265 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8266 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
8267 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8268 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
8269 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
8270 GIR_AddImm8, /*InsnID*/2, /*Imm*/16,
8271 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
8272 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
8273 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
8274 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECB_XPiI),
8275 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8276 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
8277 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
8278 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
8279 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8280 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8281 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
8282 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
8283 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
8284 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
8285 // GIR_Coverage, 9625,
8286 GIR_EraseRootFromParent_Done,
8287 // Label 479: @22275
8288 GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(22427), // Rule ID 9637 //
8289 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
8290 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8291 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8292 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8293 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
8294 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
8295 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8296 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
8297 GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
8298 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
8299 // MIs[2] pattern
8300 GIM_CheckIsImm, /*MI*/2, /*Op*/2,
8301 GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
8302 GIM_CheckIsSafeToFold, /*NumInsns*/2,
8303 // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1150:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))) => (EXTRACT_SUBREG:{ *:[i32] } (DECH_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
8304 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
8305 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
8306 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
8307 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
8308 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8309 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8310 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
8311 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8312 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
8313 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
8314 GIR_AddImm8, /*InsnID*/2, /*Imm*/16,
8315 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
8316 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
8317 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
8318 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECH_XPiI),
8319 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8320 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
8321 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
8322 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
8323 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8324 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8325 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
8326 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
8327 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
8328 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
8329 // GIR_Coverage, 9637,
8330 GIR_EraseRootFromParent_Done,
8331 // Label 480: @22427
8332 GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(22579), // Rule ID 9649 //
8333 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
8334 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8335 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8336 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8337 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
8338 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
8339 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8340 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
8341 GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
8342 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
8343 // MIs[2] pattern
8344 GIM_CheckIsImm, /*MI*/2, /*Op*/2,
8345 GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
8346 GIM_CheckIsSafeToFold, /*NumInsns*/2,
8347 // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1156:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))) => (EXTRACT_SUBREG:{ *:[i32] } (DECW_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
8348 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
8349 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
8350 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
8351 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
8352 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8353 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8354 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
8355 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8356 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
8357 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
8358 GIR_AddImm8, /*InsnID*/2, /*Imm*/16,
8359 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
8360 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
8361 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
8362 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECW_XPiI),
8363 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8364 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
8365 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
8366 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
8367 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8368 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8369 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
8370 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
8371 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
8372 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
8373 // GIR_Coverage, 9649,
8374 GIR_EraseRootFromParent_Done,
8375 // Label 481: @22579
8376 GIM_Try, /*On fail goto*//*Label 482*/ GIMT_Encode4(22731), // Rule ID 9661 //
8377 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
8378 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8379 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8380 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8381 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
8382 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
8383 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8384 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
8385 GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
8386 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
8387 // MIs[2] pattern
8388 GIM_CheckIsImm, /*MI*/2, /*Op*/2,
8389 GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
8390 GIM_CheckIsSafeToFold, /*NumInsns*/2,
8391 // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1149:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))) => (EXTRACT_SUBREG:{ *:[i32] } (DECD_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
8392 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
8393 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
8394 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
8395 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
8396 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8397 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8398 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
8399 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8400 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
8401 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
8402 GIR_AddImm8, /*InsnID*/2, /*Imm*/16,
8403 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
8404 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
8405 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
8406 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECD_XPiI),
8407 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8408 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
8409 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
8410 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
8411 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8412 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8413 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
8414 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
8415 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
8416 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
8417 // GIR_Coverage, 9661,
8418 GIR_EraseRootFromParent_Done,
8419 // Label 482: @22731
8420 GIM_Try, /*On fail goto*//*Label 483*/ GIMT_Encode4(22793), // Rule ID 3822 //
8421 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8422 GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
8423 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8424 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
8425 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8426 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8427 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8428 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8429 GIM_CheckIsSafeToFold, /*NumInsns*/1,
8430 // (sub:{ *:[i32] } 0:{ *:[i32] }, (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)) => (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
8431 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBWrrr),
8432 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
8435 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8436 GIR_RootConstrainSelectedInstOperands,
8437 // GIR_Coverage, 3822,
8438 GIR_EraseRootFromParent_Done,
8439 // Label 483: @22793
8440 GIM_Try, /*On fail goto*//*Label 484*/ GIMT_Encode4(22829), // Rule ID 3787 //
8441 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8442 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
8443 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_extended_reg32_i32),
8444 // (sub:{ *:[i32] } GPR32sp:{ *:[i32] }:$R2, arith_extended_reg32_i32:{ *:[i32] }:$R3) => (SUBSWrx:{ *:[i32] }:{ *:[i32] } GPR32sp:{ *:[i32] }:$R2, arith_extended_reg32_i32:{ *:[i32] }:$R3)
8445 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSWrx),
8446 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8447 GIR_RootToRootCopy, /*OpIdx*/1, // R2
8448 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // R3
8449 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
8450 GIR_RootConstrainSelectedInstOperands,
8451 // GIR_Coverage, 3787,
8452 GIR_EraseRootFromParent_Done,
8453 // Label 484: @22829
8454 GIM_Try, /*On fail goto*//*Label 485*/ GIMT_Encode4(22862), // Rule ID 3792 //
8455 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
8456 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8457 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_neg_addsub_shifted_imm32),
8458 // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm) => (ADDWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm)
8459 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWri),
8460 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8461 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8462 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
8463 GIR_RootConstrainSelectedInstOperands,
8464 // GIR_Coverage, 3792,
8465 GIR_EraseRootFromParent_Done,
8466 // Label 485: @22862
8467 GIM_Try, /*On fail goto*//*Label 486*/ GIMT_Encode4(22898), // Rule ID 3781 //
8468 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8469 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
8470 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_addsub_shifted_imm32),
8471 // (sub:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm) => (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
8472 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSWri),
8473 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8474 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8475 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
8476 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
8477 GIR_RootConstrainSelectedInstOperands,
8478 // GIR_Coverage, 3781,
8479 GIR_EraseRootFromParent_Done,
8480 // Label 486: @22898
8481 GIM_Try, /*On fail goto*//*Label 487*/ GIMT_Encode4(22934), // Rule ID 3785 //
8482 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8483 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8484 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg32),
8485 // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm) => (SUBSWrs:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm)
8486 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSWrs),
8487 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8488 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8489 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm
8490 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
8491 GIR_RootConstrainSelectedInstOperands,
8492 // GIR_Coverage, 3785,
8493 GIR_EraseRootFromParent_Done,
8494 // Label 487: @22934
8495 GIM_Try, /*On fail goto*//*Label 488*/ GIMT_Encode4(22964), // Rule ID 3783 //
8496 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8497 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8498 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8499 // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (SUBSWrr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
8500 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBSWrr),
8501 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AArch64::NZCV), GIMT_Encode2(RegState::Dead),
8502 GIR_RootConstrainSelectedInstOperands,
8503 // GIR_Coverage, 3783,
8504 GIR_Done,
8505 // Label 488: @22964
8506 GIM_Reject,
8507 // Label 478: @22965
8508 GIM_Reject,
8509 // Label 465: @22966
8510 GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(24269),
8511 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
8512 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
8513 GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(23076), // Rule ID 3837 //
8514 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8515 GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
8516 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8517 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
8518 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
8519 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
8520 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8521 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
8522 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8523 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8524 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
8525 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8526 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
8527 // MIs[3] Operand 1
8528 // No operand predicates
8529 GIM_CheckIsSafeToFold, /*NumInsns*/3,
8530 // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C)) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
8531 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8532 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
8533 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8534 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
8535 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8536 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMSUBLrrr),
8537 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8538 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
8539 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8540 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8541 GIR_RootConstrainSelectedInstOperands,
8542 // GIR_Coverage, 3837,
8543 GIR_EraseRootFromParent_Done,
8544 // Label 490: @23076
8545 GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(23175), // Rule ID 3838 //
8546 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8547 GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
8548 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8549 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
8550 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
8551 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
8552 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8553 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
8554 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8555 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8556 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
8557 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8558 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i64imm_32bit),
8559 // MIs[3] Operand 1
8560 // No operand predicates
8561 GIM_CheckIsSafeToFold, /*NumInsns*/3,
8562 // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C)) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
8563 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8564 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
8565 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8566 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
8567 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8568 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
8569 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8570 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
8571 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8572 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8573 GIR_RootConstrainSelectedInstOperands,
8574 // GIR_Coverage, 3838,
8575 GIR_EraseRootFromParent_Done,
8576 // Label 491: @23175
8577 GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(23261), // Rule ID 3832 //
8578 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8579 GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
8580 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8581 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
8582 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
8583 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
8584 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8585 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
8586 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8587 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8588 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
8589 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT),
8590 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8591 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8592 GIM_CheckIsSafeToFold, /*NumInsns*/3,
8593 // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
8594 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMSUBLrrr),
8595 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8596 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
8597 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
8598 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8599 GIR_RootConstrainSelectedInstOperands,
8600 // GIR_Coverage, 3832,
8601 GIR_EraseRootFromParent_Done,
8602 // Label 492: @23261
8603 GIM_Try, /*On fail goto*//*Label 493*/ GIMT_Encode4(23347), // Rule ID 3833 //
8604 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8605 GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
8606 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8607 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
8608 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
8609 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
8610 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8611 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
8612 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8613 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8614 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
8615 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
8616 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8617 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8618 GIM_CheckIsSafeToFold, /*NumInsns*/3,
8619 // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
8620 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
8621 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8622 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
8623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
8624 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8625 GIR_RootConstrainSelectedInstOperands,
8626 // GIR_Coverage, 3833,
8627 GIR_EraseRootFromParent_Done,
8628 // Label 493: @23347
8629 GIM_Try, /*On fail goto*//*Label 494*/ GIMT_Encode4(23442), // Rule ID 3843 //
8630 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8631 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8632 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8633 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
8634 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
8635 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
8636 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8637 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
8638 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8639 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8640 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
8641 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8642 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
8643 // MIs[3] Operand 1
8644 // No operand predicates
8645 GIM_CheckIsSafeToFold, /*NumInsns*/3,
8646 // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C)) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
8647 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8648 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
8649 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8650 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
8651 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8652 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMSUBLrrr),
8653 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
8655 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8656 GIR_RootToRootCopy, /*OpIdx*/1, // Ra
8657 GIR_RootConstrainSelectedInstOperands,
8658 // GIR_Coverage, 3843,
8659 GIR_EraseRootFromParent_Done,
8660 // Label 494: @23442
8661 GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(23537), // Rule ID 3844 //
8662 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8663 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8664 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8665 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
8666 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
8667 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
8668 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8669 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
8670 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8671 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8672 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
8673 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8674 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i64imm_32bit),
8675 // MIs[3] Operand 1
8676 // No operand predicates
8677 GIM_CheckIsSafeToFold, /*NumInsns*/3,
8678 // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C)) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
8679 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8680 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
8681 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
8682 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
8683 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8684 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
8685 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8686 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
8687 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8688 GIR_RootToRootCopy, /*OpIdx*/1, // Ra
8689 GIR_RootConstrainSelectedInstOperands,
8690 // GIR_Coverage, 3844,
8691 GIR_EraseRootFromParent_Done,
8692 // Label 495: @23537
8693 GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(23619), // Rule ID 135 //
8694 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8695 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8696 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8697 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
8698 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
8699 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
8700 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8701 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
8702 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8703 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8704 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
8705 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT),
8706 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8707 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8708 GIM_CheckIsSafeToFold, /*NumInsns*/3,
8709 // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
8710 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMSUBLrrr),
8711 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8712 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
8713 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
8714 GIR_RootToRootCopy, /*OpIdx*/1, // Ra
8715 GIR_RootConstrainSelectedInstOperands,
8716 // GIR_Coverage, 135,
8717 GIR_EraseRootFromParent_Done,
8718 // Label 496: @23619
8719 GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(23701), // Rule ID 137 //
8720 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8721 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8722 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8723 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
8724 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
8725 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
8726 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8727 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
8728 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8729 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8730 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
8731 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
8732 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8733 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
8734 GIM_CheckIsSafeToFold, /*NumInsns*/3,
8735 // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))) => (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
8736 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
8737 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8738 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
8739 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
8740 GIR_RootToRootCopy, /*OpIdx*/1, // Ra
8741 GIR_RootConstrainSelectedInstOperands,
8742 // GIR_Coverage, 137,
8743 GIR_EraseRootFromParent_Done,
8744 // Label 497: @23701
8745 GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(23763), // Rule ID 3823 //
8746 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8747 GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
8748 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8749 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
8750 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
8751 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
8752 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8753 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8754 GIM_CheckIsSafeToFold, /*NumInsns*/1,
8755 // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)) => (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
8756 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBXrrr),
8757 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8758 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8759 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
8760 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8761 GIR_RootConstrainSelectedInstOperands,
8762 // GIR_Coverage, 3823,
8763 GIR_EraseRootFromParent_Done,
8764 // Label 498: @23763
8765 GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(23821), // Rule ID 9622 //
8766 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
8767 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8768 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8769 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8770 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
8771 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
8772 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
8773 // MIs[1] pattern
8774 GIM_CheckIsImm, /*MI*/1, /*Op*/2,
8775 GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
8776 GIM_CheckIsSafeToFold, /*NumInsns*/1,
8777 // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1148:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)) => (DECB_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
8778 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECB_XPiI),
8779 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
8780 GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
8781 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
8782 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
8783 GIR_RootConstrainSelectedInstOperands,
8784 // GIR_Coverage, 9622,
8785 GIR_EraseRootFromParent_Done,
8786 // Label 499: @23821
8787 GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(23879), // Rule ID 9634 //
8788 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
8789 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8790 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8791 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8792 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
8793 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
8794 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
8795 // MIs[1] pattern
8796 GIM_CheckIsImm, /*MI*/1, /*Op*/2,
8797 GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
8798 GIM_CheckIsSafeToFold, /*NumInsns*/1,
8799 // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1150:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)) => (DECH_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
8800 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECH_XPiI),
8801 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
8802 GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
8803 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
8804 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
8805 GIR_RootConstrainSelectedInstOperands,
8806 // GIR_Coverage, 9634,
8807 GIR_EraseRootFromParent_Done,
8808 // Label 500: @23879
8809 GIM_Try, /*On fail goto*//*Label 501*/ GIMT_Encode4(23937), // Rule ID 9646 //
8810 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
8811 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8812 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8813 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8814 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
8815 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
8816 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
8817 // MIs[1] pattern
8818 GIM_CheckIsImm, /*MI*/1, /*Op*/2,
8819 GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
8820 GIM_CheckIsSafeToFold, /*NumInsns*/1,
8821 // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1156:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)) => (DECW_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
8822 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECW_XPiI),
8823 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
8824 GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
8825 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
8826 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
8827 GIR_RootConstrainSelectedInstOperands,
8828 // GIR_Coverage, 9646,
8829 GIR_EraseRootFromParent_Done,
8830 // Label 501: @23937
8831 GIM_Try, /*On fail goto*//*Label 502*/ GIMT_Encode4(23995), // Rule ID 9658 //
8832 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME_UseScalarIncVL),
8833 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8834 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8835 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8836 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
8837 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
8838 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
8839 // MIs[1] pattern
8840 GIM_CheckIsImm, /*MI*/1, /*Op*/2,
8841 GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
8842 GIM_CheckIsSafeToFold, /*NumInsns*/1,
8843 // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1149:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)) => (DECD_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
8844 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECD_XPiI),
8845 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
8846 GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
8847 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
8848 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
8849 GIR_RootConstrainSelectedInstOperands,
8850 // GIR_Coverage, 9658,
8851 GIR_EraseRootFromParent_Done,
8852 // Label 502: @23995
8853 GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(24031), // Rule ID 3788 //
8854 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8855 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
8856 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_extended_reg32to64_i64),
8857 // (sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$R2, arith_extended_reg32to64_i64:{ *:[i64] }:$R3) => (SUBSXrx:{ *:[i64] }:{ *:[i32] } GPR64sp:{ *:[i64] }:$R2, arith_extended_reg32to64_i64:{ *:[i64] }:$R3)
8858 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSXrx),
8859 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8860 GIR_RootToRootCopy, /*OpIdx*/1, // R2
8861 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // R3
8862 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
8863 GIR_RootConstrainSelectedInstOperands,
8864 // GIR_Coverage, 3788,
8865 GIR_EraseRootFromParent_Done,
8866 // Label 503: @24031
8867 GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(24064), // Rule ID 3793 //
8868 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
8869 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8870 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_neg_addsub_shifted_imm64),
8871 // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm) => (ADDXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm)
8872 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXri),
8873 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8874 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8875 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
8876 GIR_RootConstrainSelectedInstOperands,
8877 // GIR_Coverage, 3793,
8878 GIR_EraseRootFromParent_Done,
8879 // Label 504: @24064
8880 GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(24100), // Rule ID 3782 //
8881 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8882 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
8883 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_addsub_shifted_imm64),
8884 // (sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm) => (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
8885 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSXri),
8886 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8887 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8888 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
8889 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
8890 GIR_RootConstrainSelectedInstOperands,
8891 // GIR_Coverage, 3782,
8892 GIR_EraseRootFromParent_Done,
8893 // Label 505: @24100
8894 GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(24136), // Rule ID 3786 //
8895 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8896 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8897 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg64),
8898 // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm) => (SUBSXrs:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm)
8899 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSXrs),
8900 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8901 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8902 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm
8903 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
8904 GIR_RootConstrainSelectedInstOperands,
8905 // GIR_Coverage, 3786,
8906 GIR_EraseRootFromParent_Done,
8907 // Label 506: @24136
8908 GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(24175), // Rule ID 1642 //
8909 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8910 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
8911 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8912 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8913 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
8914 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
8915 GIM_CheckIsSafeToFold, /*NumInsns*/1,
8916 // (sub:{ *:[v1i64] } immAllZerosV:{ *:[v1i64] }, FPR64:{ *:[v1i64] }:$Rn) => (NEGv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
8917 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv1i64),
8918 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8919 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
8920 GIR_RootConstrainSelectedInstOperands,
8921 // GIR_Coverage, 1642,
8922 GIR_EraseRootFromParent_Done,
8923 // Label 507: @24175
8924 GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(24211), // Rule ID 4895 //
8925 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
8926 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8927 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8928 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
8929 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
8930 GIM_CheckIsSafeToFold, /*NumInsns*/1,
8931 // (sub:{ *:[i64] } immAllZerosV:{ *:[i64] }, FPR64:{ *:[i64] }:$Rn) => (NEGv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn)
8932 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv1i64),
8933 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8934 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
8935 GIR_RootConstrainSelectedInstOperands,
8936 // GIR_Coverage, 4895,
8937 GIR_EraseRootFromParent_Done,
8938 // Label 508: @24211
8939 GIM_Try, /*On fail goto*//*Label 509*/ GIMT_Encode4(24238), // Rule ID 1631 //
8940 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8941 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
8942 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
8943 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
8944 // (sub:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
8945 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv1i64),
8946 GIR_RootConstrainSelectedInstOperands,
8947 // GIR_Coverage, 1631,
8948 GIR_Done,
8949 // Label 509: @24238
8950 GIM_Try, /*On fail goto*//*Label 510*/ GIMT_Encode4(24268), // Rule ID 3784 //
8951 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8952 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8953 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
8954 // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SUBSXrr:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
8955 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBSXrr),
8956 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AArch64::NZCV), GIMT_Encode2(RegState::Dead),
8957 GIR_RootConstrainSelectedInstOperands,
8958 // GIR_Coverage, 3784,
8959 GIR_Done,
8960 // Label 510: @24268
8961 GIM_Reject,
8962 // Label 489: @24269
8963 GIM_Reject,
8964 // Label 466: @24270
8965 GIM_Try, /*On fail goto*//*Label 511*/ GIMT_Encode4(24344),
8966 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
8967 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
8968 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
8969 GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(24320), // Rule ID 956 //
8970 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8971 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8972 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
8973 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
8974 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
8975 GIM_CheckIsSafeToFold, /*NumInsns*/1,
8976 // (sub:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn) => (NEGv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
8977 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv2i32),
8978 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8979 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
8980 GIR_RootConstrainSelectedInstOperands,
8981 // GIR_Coverage, 956,
8982 GIR_EraseRootFromParent_Done,
8983 // Label 512: @24320
8984 GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(24343), // Rule ID 1463 //
8985 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
8986 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
8987 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
8988 // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
8989 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv2i32),
8990 GIR_RootConstrainSelectedInstOperands,
8991 // GIR_Coverage, 1463,
8992 GIR_Done,
8993 // Label 513: @24343
8994 GIM_Reject,
8995 // Label 511: @24344
8996 GIM_Reject,
8997 // Label 467: @24345
8998 GIM_Try, /*On fail goto*//*Label 514*/ GIMT_Encode4(25904),
8999 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
9000 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9001 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9002 GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(24425), // Rule ID 1842 //
9003 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9004 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9005 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
9006 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9007 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9008 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
9009 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
9010 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9011 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
9012 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
9013 // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (USUBLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
9014 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i32_v2i64),
9015 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9016 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
9017 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
9018 GIR_RootConstrainSelectedInstOperands,
9019 // GIR_Coverage, 1842,
9020 GIR_EraseRootFromParent_Done,
9021 // Label 515: @24425
9022 GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(24490), // Rule ID 1841 //
9023 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9024 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9025 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
9026 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9027 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9028 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
9029 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
9030 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9031 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
9032 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
9033 // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (USUBLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
9034 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i32_v2i64),
9035 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9036 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
9037 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
9038 GIR_RootConstrainSelectedInstOperands,
9039 // GIR_Coverage, 1841,
9040 GIR_EraseRootFromParent_Done,
9041 // Label 516: @24490
9042 GIM_Try, /*On fail goto*//*Label 517*/ GIMT_Encode4(24555), // Rule ID 1746 //
9043 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9044 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9045 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
9046 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9047 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9048 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
9049 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
9050 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9051 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
9052 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
9053 // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (SSUBLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
9054 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv4i32_v2i64),
9055 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9056 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
9057 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
9058 GIR_RootConstrainSelectedInstOperands,
9059 // GIR_Coverage, 1746,
9060 GIR_EraseRootFromParent_Done,
9061 // Label 517: @24555
9062 GIM_Try, /*On fail goto*//*Label 518*/ GIMT_Encode4(24620), // Rule ID 1840 //
9063 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9064 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9065 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
9066 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9067 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9068 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
9069 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
9070 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9071 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
9072 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
9073 // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (USUBLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
9074 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i32_v2i64),
9075 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9076 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
9077 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
9078 GIR_RootConstrainSelectedInstOperands,
9079 // GIR_Coverage, 1840,
9080 GIR_EraseRootFromParent_Done,
9081 // Label 518: @24620
9082 GIM_Try, /*On fail goto*//*Label 519*/ GIMT_Encode4(24685), // Rule ID 1839 //
9083 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9084 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9085 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
9086 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9087 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9088 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
9089 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
9090 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9091 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
9092 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
9093 // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (USUBLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
9094 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i32_v2i64),
9095 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9096 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
9097 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
9098 GIR_RootConstrainSelectedInstOperands,
9099 // GIR_Coverage, 1839,
9100 GIR_EraseRootFromParent_Done,
9101 // Label 519: @24685
9102 GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(24748), // Rule ID 1722 //
9103 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9104 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9105 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9106 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
9107 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9108 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
9109 GIM_CheckIsSafeToFold, /*NumInsns*/1,
9110 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
9111 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
9112 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (SMLSLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
9113 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i32_v2i64),
9114 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9115 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
9116 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
9117 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
9118 GIR_RootConstrainSelectedInstOperands,
9119 // GIR_Coverage, 1722,
9120 GIR_EraseRootFromParent_Done,
9121 // Label 520: @24748
9122 GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(24811), // Rule ID 1812 //
9123 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9124 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9125 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9126 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
9127 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9128 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
9129 GIM_CheckIsSafeToFold, /*NumInsns*/1,
9130 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
9131 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
9132 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (UMLSLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
9133 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i32_v2i64),
9134 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9135 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
9136 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
9137 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
9138 GIR_RootConstrainSelectedInstOperands,
9139 // GIR_Coverage, 1812,
9140 GIR_EraseRootFromParent_Done,
9141 // Label 521: @24811
9142 GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(24899), // Rule ID 12740 //
9143 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9144 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9145 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9146 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
9147 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9148 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
9149 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9150 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
9151 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9152 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
9153 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9154 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
9155 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9156 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
9157 // MIs[3] Operand 1
9158 // No operand predicates
9159 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9160 GIM_CheckIsSafeToFold, /*NumInsns*/3,
9161 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn)) => (SMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
9162 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv2i32_indexed),
9163 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9164 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
9165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
9166 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
9167 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
9168 GIR_RootConstrainSelectedInstOperands,
9169 // GIR_Coverage, 12740,
9170 GIR_EraseRootFromParent_Done,
9171 // Label 522: @24899
9172 GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(24987), // Rule ID 2034 //
9173 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9174 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9175 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9176 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
9177 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9178 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
9179 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9180 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
9181 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
9182 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9183 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
9184 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9185 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
9186 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9187 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
9188 // MIs[3] Operand 1
9189 // No operand predicates
9190 GIM_CheckIsSafeToFold, /*NumInsns*/3,
9191 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
9192 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv2i32_indexed),
9193 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9194 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
9195 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
9196 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
9197 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
9198 GIR_RootConstrainSelectedInstOperands,
9199 // GIR_Coverage, 2034,
9200 GIR_EraseRootFromParent_Done,
9201 // Label 523: @24987
9202 GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(25075), // Rule ID 12770 //
9203 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9204 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9205 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9206 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
9207 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9208 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
9209 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9210 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
9211 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9212 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
9213 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9214 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
9215 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9216 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
9217 // MIs[3] Operand 1
9218 // No operand predicates
9219 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9220 GIM_CheckIsSafeToFold, /*NumInsns*/3,
9221 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn)) => (UMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
9222 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv2i32_indexed),
9223 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9224 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
9225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
9226 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
9227 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
9228 GIR_RootConstrainSelectedInstOperands,
9229 // GIR_Coverage, 12770,
9230 GIR_EraseRootFromParent_Done,
9231 // Label 524: @25075
9232 GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(25163), // Rule ID 2086 //
9233 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9234 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9235 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9236 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
9237 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9238 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
9239 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9240 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
9241 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
9242 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
9243 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
9244 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9245 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
9246 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9247 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
9248 // MIs[3] Operand 1
9249 // No operand predicates
9250 GIM_CheckIsSafeToFold, /*NumInsns*/3,
9251 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (UMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
9252 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv2i32_indexed),
9253 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9254 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
9255 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
9256 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
9257 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
9258 GIR_RootConstrainSelectedInstOperands,
9259 // GIR_Coverage, 2086,
9260 GIR_EraseRootFromParent_Done,
9261 // Label 525: @25163
9262 GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(25210), // Rule ID 1854 //
9263 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9264 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9265 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9266 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
9267 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9268 GIM_CheckIsSafeToFold, /*NumInsns*/1,
9269 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
9270 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (USUBWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
9271 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv4i32_v2i64),
9272 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9273 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9274 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
9275 GIR_RootConstrainSelectedInstOperands,
9276 // GIR_Coverage, 1854,
9277 GIR_EraseRootFromParent_Done,
9278 // Label 526: @25210
9279 GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(25257), // Rule ID 1752 //
9280 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9281 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9282 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9283 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
9284 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9285 GIM_CheckIsSafeToFold, /*NumInsns*/1,
9286 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
9287 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (SSUBWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
9288 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv4i32_v2i64),
9289 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9290 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9291 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
9292 GIR_RootConstrainSelectedInstOperands,
9293 // GIR_Coverage, 1752,
9294 GIR_EraseRootFromParent_Done,
9295 // Label 527: @25257
9296 GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(25304), // Rule ID 1853 //
9297 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9298 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9299 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9300 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
9301 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9302 GIM_CheckIsSafeToFold, /*NumInsns*/1,
9303 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
9304 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (USUBWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
9305 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv4i32_v2i64),
9306 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9307 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9308 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
9309 GIR_RootConstrainSelectedInstOperands,
9310 // GIR_Coverage, 1853,
9311 GIR_EraseRootFromParent_Done,
9312 // Label 528: @25304
9313 GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(25363), // Rule ID 1838 //
9314 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9315 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9316 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
9317 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9318 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9319 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9320 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
9321 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
9322 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9323 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9324 // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
9325 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
9326 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9327 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
9328 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
9329 GIR_RootConstrainSelectedInstOperands,
9330 // GIR_Coverage, 1838,
9331 GIR_EraseRootFromParent_Done,
9332 // Label 529: @25363
9333 GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(25422), // Rule ID 1837 //
9334 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9335 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9336 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
9337 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9338 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9339 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9340 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
9341 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
9342 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9343 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9344 // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
9345 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
9346 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9347 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
9348 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
9349 GIR_RootConstrainSelectedInstOperands,
9350 // GIR_Coverage, 1837,
9351 GIR_EraseRootFromParent_Done,
9352 // Label 530: @25422
9353 GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(25481), // Rule ID 1745 //
9354 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9355 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9356 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
9357 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9358 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9359 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9360 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
9361 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
9362 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9363 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9364 // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SSUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
9365 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv2i32_v2i64),
9366 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9367 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
9368 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
9369 GIR_RootConstrainSelectedInstOperands,
9370 // GIR_Coverage, 1745,
9371 GIR_EraseRootFromParent_Done,
9372 // Label 531: @25481
9373 GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(25540), // Rule ID 1836 //
9374 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9375 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9376 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
9377 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9378 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9379 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9380 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
9381 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
9382 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9383 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9384 // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
9385 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
9386 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9387 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
9388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
9389 GIR_RootConstrainSelectedInstOperands,
9390 // GIR_Coverage, 1836,
9391 GIR_EraseRootFromParent_Done,
9392 // Label 532: @25540
9393 GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(25599), // Rule ID 1835 //
9394 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9395 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9396 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
9397 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9398 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9399 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9400 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
9401 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
9402 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9403 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9404 // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
9405 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
9406 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9407 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
9408 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
9409 GIR_RootConstrainSelectedInstOperands,
9410 // GIR_Coverage, 1835,
9411 GIR_EraseRootFromParent_Done,
9412 // Label 533: @25599
9413 GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(25634), // Rule ID 958 //
9414 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9415 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9416 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9417 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
9418 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9419 GIM_CheckIsSafeToFold, /*NumInsns*/1,
9420 // (sub:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn) => (NEGv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
9421 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv2i64),
9422 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9423 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
9424 GIR_RootConstrainSelectedInstOperands,
9425 // GIR_Coverage, 958,
9426 GIR_EraseRootFromParent_Done,
9427 // Label 534: @25634
9428 GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(25691), // Rule ID 1721 //
9429 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9430 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9431 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9432 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
9433 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9434 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
9435 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9436 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9437 GIM_CheckIsSafeToFold, /*NumInsns*/1,
9438 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
9439 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv2i32_v2i64),
9440 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9441 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
9442 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
9443 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
9444 GIR_RootConstrainSelectedInstOperands,
9445 // GIR_Coverage, 1721,
9446 GIR_EraseRootFromParent_Done,
9447 // Label 535: @25691
9448 GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(25748), // Rule ID 1811 //
9449 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9450 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9451 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9452 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
9453 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9454 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
9455 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9456 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9457 GIM_CheckIsSafeToFold, /*NumInsns*/1,
9458 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (UMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
9459 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv2i32_v2i64),
9460 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9461 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
9462 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
9463 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
9464 GIR_RootConstrainSelectedInstOperands,
9465 // GIR_Coverage, 1811,
9466 GIR_EraseRootFromParent_Done,
9467 // Label 536: @25748
9468 GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(25792), // Rule ID 1852 //
9469 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9470 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9471 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9472 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
9473 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9474 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9475 GIM_CheckIsSafeToFold, /*NumInsns*/1,
9476 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
9477 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv2i32_v2i64),
9478 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9479 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9480 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
9481 GIR_RootConstrainSelectedInstOperands,
9482 // GIR_Coverage, 1852,
9483 GIR_EraseRootFromParent_Done,
9484 // Label 537: @25792
9485 GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(25836), // Rule ID 1751 //
9486 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9487 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9488 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9489 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
9490 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9491 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9492 GIM_CheckIsSafeToFold, /*NumInsns*/1,
9493 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (SSUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
9494 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv2i32_v2i64),
9495 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9496 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9497 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
9498 GIR_RootConstrainSelectedInstOperands,
9499 // GIR_Coverage, 1751,
9500 GIR_EraseRootFromParent_Done,
9501 // Label 538: @25836
9502 GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(25880), // Rule ID 1851 //
9503 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9504 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9505 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9506 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
9507 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
9508 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9509 GIM_CheckIsSafeToFold, /*NumInsns*/1,
9510 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm)) => (USUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
9511 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv2i32_v2i64),
9512 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9513 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9514 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
9515 GIR_RootConstrainSelectedInstOperands,
9516 // GIR_Coverage, 1851,
9517 GIR_EraseRootFromParent_Done,
9518 // Label 539: @25880
9519 GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(25903), // Rule ID 1465 //
9520 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9521 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9522 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9523 // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
9524 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv2i64),
9525 GIR_RootConstrainSelectedInstOperands,
9526 // GIR_Coverage, 1465,
9527 GIR_Done,
9528 // Label 540: @25903
9529 GIM_Reject,
9530 // Label 514: @25904
9531 GIM_Reject,
9532 // Label 468: @25905
9533 GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(25979),
9534 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
9535 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
9536 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9537 GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(25955), // Rule ID 954 //
9538 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9539 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9540 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9541 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
9542 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9543 GIM_CheckIsSafeToFold, /*NumInsns*/1,
9544 // (sub:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn) => (NEGv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
9545 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv4i16),
9546 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9547 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
9548 GIR_RootConstrainSelectedInstOperands,
9549 // GIR_Coverage, 954,
9550 GIR_EraseRootFromParent_Done,
9551 // Label 542: @25955
9552 GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(25978), // Rule ID 1461 //
9553 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9554 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9555 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9556 // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
9557 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv4i16),
9558 GIR_RootConstrainSelectedInstOperands,
9559 // GIR_Coverage, 1461,
9560 GIR_Done,
9561 // Label 543: @25978
9562 GIM_Reject,
9563 // Label 541: @25979
9564 GIM_Reject,
9565 // Label 469: @25980
9566 GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(27539),
9567 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
9568 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9569 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9570 GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(26060), // Rule ID 1834 //
9571 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9572 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9573 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
9574 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
9575 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9576 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
9577 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
9578 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9579 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
9580 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
9581 // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (USUBLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
9582 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i16_v4i32),
9583 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9584 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
9585 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
9586 GIR_RootConstrainSelectedInstOperands,
9587 // GIR_Coverage, 1834,
9588 GIR_EraseRootFromParent_Done,
9589 // Label 545: @26060
9590 GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(26125), // Rule ID 1833 //
9591 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9592 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9593 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
9594 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
9595 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9596 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
9597 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
9598 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9599 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
9600 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
9601 // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (USUBLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
9602 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i16_v4i32),
9603 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9604 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
9605 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
9606 GIR_RootConstrainSelectedInstOperands,
9607 // GIR_Coverage, 1833,
9608 GIR_EraseRootFromParent_Done,
9609 // Label 546: @26125
9610 GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(26190), // Rule ID 1744 //
9611 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9612 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9613 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
9614 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
9615 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9616 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
9617 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
9618 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9619 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
9620 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
9621 // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (SSUBLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
9622 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv8i16_v4i32),
9623 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9624 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
9625 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
9626 GIR_RootConstrainSelectedInstOperands,
9627 // GIR_Coverage, 1744,
9628 GIR_EraseRootFromParent_Done,
9629 // Label 547: @26190
9630 GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(26255), // Rule ID 1832 //
9631 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9632 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9633 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
9634 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
9635 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9636 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
9637 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
9638 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9639 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
9640 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
9641 // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (USUBLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
9642 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i16_v4i32),
9643 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9644 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
9645 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
9646 GIR_RootConstrainSelectedInstOperands,
9647 // GIR_Coverage, 1832,
9648 GIR_EraseRootFromParent_Done,
9649 // Label 548: @26255
9650 GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(26320), // Rule ID 1831 //
9651 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9652 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9653 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
9654 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
9655 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9656 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
9657 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
9658 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9659 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
9660 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
9661 // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (USUBLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
9662 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i16_v4i32),
9663 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9664 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
9665 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
9666 GIR_RootConstrainSelectedInstOperands,
9667 // GIR_Coverage, 1831,
9668 GIR_EraseRootFromParent_Done,
9669 // Label 549: @26320
9670 GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(26383), // Rule ID 1720 //
9671 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9672 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9673 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9674 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
9675 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
9676 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
9677 GIM_CheckIsSafeToFold, /*NumInsns*/1,
9678 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
9679 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
9680 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (SMLSLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
9681 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv8i16_v4i32),
9682 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9683 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
9684 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
9685 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
9686 GIR_RootConstrainSelectedInstOperands,
9687 // GIR_Coverage, 1720,
9688 GIR_EraseRootFromParent_Done,
9689 // Label 550: @26383
9690 GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(26446), // Rule ID 1810 //
9691 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9692 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9693 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9694 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
9695 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
9696 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
9697 GIM_CheckIsSafeToFold, /*NumInsns*/1,
9698 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
9699 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
9700 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (UMLSLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
9701 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv8i16_v4i32),
9702 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9703 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
9704 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
9705 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
9706 GIR_RootConstrainSelectedInstOperands,
9707 // GIR_Coverage, 1810,
9708 GIR_EraseRootFromParent_Done,
9709 // Label 551: @26446
9710 GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(26534), // Rule ID 12737 //
9711 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9712 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9713 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9714 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
9715 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
9716 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
9717 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9718 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
9719 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
9720 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
9721 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
9722 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
9723 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9724 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
9725 // MIs[3] Operand 1
9726 // No operand predicates
9727 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9728 GIM_CheckIsSafeToFold, /*NumInsns*/3,
9729 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn)) => (SMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
9730 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i16_indexed),
9731 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9732 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
9733 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
9734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
9735 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
9736 GIR_RootConstrainSelectedInstOperands,
9737 // GIR_Coverage, 12737,
9738 GIR_EraseRootFromParent_Done,
9739 // Label 552: @26534
9740 GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(26622), // Rule ID 2031 //
9741 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9742 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9743 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9744 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
9745 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
9746 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
9747 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9748 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
9749 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
9750 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
9751 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
9752 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
9753 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
9754 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9755 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
9756 // MIs[3] Operand 1
9757 // No operand predicates
9758 GIM_CheckIsSafeToFold, /*NumInsns*/3,
9759 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))) => (SMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
9760 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i16_indexed),
9761 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9762 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
9763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
9764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
9765 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
9766 GIR_RootConstrainSelectedInstOperands,
9767 // GIR_Coverage, 2031,
9768 GIR_EraseRootFromParent_Done,
9769 // Label 553: @26622
9770 GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(26710), // Rule ID 12767 //
9771 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9772 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9773 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9774 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
9775 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
9776 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
9777 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
9778 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
9779 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
9780 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
9781 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
9782 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
9783 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9784 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
9785 // MIs[3] Operand 1
9786 // No operand predicates
9787 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9788 GIM_CheckIsSafeToFold, /*NumInsns*/3,
9789 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn)) => (UMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
9790 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i16_indexed),
9791 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9792 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
9793 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
9794 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
9795 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
9796 GIR_RootConstrainSelectedInstOperands,
9797 // GIR_Coverage, 12767,
9798 GIR_EraseRootFromParent_Done,
9799 // Label 554: @26710
9800 GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(26798), // Rule ID 2083 //
9801 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9802 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9803 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9804 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
9805 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
9806 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
9807 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9808 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
9809 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
9810 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
9811 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
9812 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
9813 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
9814 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9815 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
9816 // MIs[3] Operand 1
9817 // No operand predicates
9818 GIM_CheckIsSafeToFold, /*NumInsns*/3,
9819 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))) => (UMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
9820 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i16_indexed),
9821 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9822 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
9823 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
9824 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
9825 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
9826 GIR_RootConstrainSelectedInstOperands,
9827 // GIR_Coverage, 2083,
9828 GIR_EraseRootFromParent_Done,
9829 // Label 555: @26798
9830 GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(26845), // Rule ID 1850 //
9831 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9832 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9833 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9834 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
9835 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
9836 GIM_CheckIsSafeToFold, /*NumInsns*/1,
9837 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
9838 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (USUBWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
9839 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv8i16_v4i32),
9840 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9841 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9842 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
9843 GIR_RootConstrainSelectedInstOperands,
9844 // GIR_Coverage, 1850,
9845 GIR_EraseRootFromParent_Done,
9846 // Label 556: @26845
9847 GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(26892), // Rule ID 1750 //
9848 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9849 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9850 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9851 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
9852 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
9853 GIM_CheckIsSafeToFold, /*NumInsns*/1,
9854 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
9855 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (SSUBWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
9856 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv8i16_v4i32),
9857 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9858 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9859 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
9860 GIR_RootConstrainSelectedInstOperands,
9861 // GIR_Coverage, 1750,
9862 GIR_EraseRootFromParent_Done,
9863 // Label 557: @26892
9864 GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(26939), // Rule ID 1849 //
9865 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9866 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9867 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9868 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
9869 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
9870 GIM_CheckIsSafeToFold, /*NumInsns*/1,
9871 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
9872 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (USUBWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
9873 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv8i16_v4i32),
9874 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9875 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9876 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
9877 GIR_RootConstrainSelectedInstOperands,
9878 // GIR_Coverage, 1849,
9879 GIR_EraseRootFromParent_Done,
9880 // Label 558: @26939
9881 GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(26998), // Rule ID 1830 //
9882 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9883 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9884 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
9885 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
9886 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9887 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9888 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
9889 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
9890 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9891 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9892 // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
9893 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
9894 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
9896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
9897 GIR_RootConstrainSelectedInstOperands,
9898 // GIR_Coverage, 1830,
9899 GIR_EraseRootFromParent_Done,
9900 // Label 559: @26998
9901 GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(27057), // Rule ID 1829 //
9902 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9903 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9904 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
9905 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
9906 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9907 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9908 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
9909 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
9910 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9911 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9912 // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
9913 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
9914 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9915 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
9916 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
9917 GIR_RootConstrainSelectedInstOperands,
9918 // GIR_Coverage, 1829,
9919 GIR_EraseRootFromParent_Done,
9920 // Label 560: @27057
9921 GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(27116), // Rule ID 1743 //
9922 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9923 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9924 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
9925 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
9926 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9927 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9928 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
9929 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
9930 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9931 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9932 // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SSUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
9933 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv4i16_v4i32),
9934 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9935 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
9936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
9937 GIR_RootConstrainSelectedInstOperands,
9938 // GIR_Coverage, 1743,
9939 GIR_EraseRootFromParent_Done,
9940 // Label 561: @27116
9941 GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(27175), // Rule ID 1828 //
9942 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9943 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9944 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
9945 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
9946 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9947 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9948 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
9949 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
9950 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9951 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9952 // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
9953 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
9954 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
9956 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
9957 GIR_RootConstrainSelectedInstOperands,
9958 // GIR_Coverage, 1828,
9959 GIR_EraseRootFromParent_Done,
9960 // Label 562: @27175
9961 GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(27234), // Rule ID 1827 //
9962 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9963 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9964 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
9965 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
9966 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9967 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
9968 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
9969 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
9970 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
9971 GIM_CheckIsSafeToFold, /*NumInsns*/2,
9972 // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
9973 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
9974 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
9976 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
9977 GIR_RootConstrainSelectedInstOperands,
9978 // GIR_Coverage, 1827,
9979 GIR_EraseRootFromParent_Done,
9980 // Label 563: @27234
9981 GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(27269), // Rule ID 957 //
9982 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9983 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9984 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
9985 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
9986 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9987 GIM_CheckIsSafeToFold, /*NumInsns*/1,
9988 // (sub:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn) => (NEGv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
9989 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv4i32),
9990 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9991 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
9992 GIR_RootConstrainSelectedInstOperands,
9993 // GIR_Coverage, 957,
9994 GIR_EraseRootFromParent_Done,
9995 // Label 564: @27269
9996 GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(27326), // Rule ID 1719 //
9997 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9998 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
9999 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10000 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
10001 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
10002 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
10003 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10004 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10005 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10006 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
10007 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i16_v4i32),
10008 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10009 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
10010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
10011 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
10012 GIR_RootConstrainSelectedInstOperands,
10013 // GIR_Coverage, 1719,
10014 GIR_EraseRootFromParent_Done,
10015 // Label 565: @27326
10016 GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(27383), // Rule ID 1809 //
10017 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10018 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10019 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10020 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
10021 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
10022 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
10023 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10024 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10025 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10026 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (UMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
10027 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i16_v4i32),
10028 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10029 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
10030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
10031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
10032 GIR_RootConstrainSelectedInstOperands,
10033 // GIR_Coverage, 1809,
10034 GIR_EraseRootFromParent_Done,
10035 // Label 566: @27383
10036 GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(27427), // Rule ID 1848 //
10037 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10038 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10039 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10040 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
10041 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
10042 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10043 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10044 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
10045 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv4i16_v4i32),
10046 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10047 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
10048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
10049 GIR_RootConstrainSelectedInstOperands,
10050 // GIR_Coverage, 1848,
10051 GIR_EraseRootFromParent_Done,
10052 // Label 567: @27427
10053 GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(27471), // Rule ID 1749 //
10054 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10055 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10056 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10057 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
10058 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
10059 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10060 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10061 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (SSUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
10062 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv4i16_v4i32),
10063 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10064 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
10065 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
10066 GIR_RootConstrainSelectedInstOperands,
10067 // GIR_Coverage, 1749,
10068 GIR_EraseRootFromParent_Done,
10069 // Label 568: @27471
10070 GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(27515), // Rule ID 1847 //
10071 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10072 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10073 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10074 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
10075 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
10076 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10077 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10078 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm)) => (USUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
10079 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv4i16_v4i32),
10080 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10081 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
10082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
10083 GIR_RootConstrainSelectedInstOperands,
10084 // GIR_Coverage, 1847,
10085 GIR_EraseRootFromParent_Done,
10086 // Label 569: @27515
10087 GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(27538), // Rule ID 1464 //
10088 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10089 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10090 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10091 // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
10092 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv4i32),
10093 GIR_RootConstrainSelectedInstOperands,
10094 // GIR_Coverage, 1464,
10095 GIR_Done,
10096 // Label 570: @27538
10097 GIM_Reject,
10098 // Label 544: @27539
10099 GIM_Reject,
10100 // Label 470: @27540
10101 GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(27614),
10102 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
10103 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
10104 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10105 GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(27590), // Rule ID 952 //
10106 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10107 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10108 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10109 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
10110 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10111 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10112 // (sub:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn) => (NEGv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
10113 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv8i8),
10114 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10115 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
10116 GIR_RootConstrainSelectedInstOperands,
10117 // GIR_Coverage, 952,
10118 GIR_EraseRootFromParent_Done,
10119 // Label 572: @27590
10120 GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(27613), // Rule ID 1459 //
10121 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10122 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10123 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10124 // (sub:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
10125 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv8i8),
10126 GIR_RootConstrainSelectedInstOperands,
10127 // GIR_Coverage, 1459,
10128 GIR_Done,
10129 // Label 573: @27613
10130 GIM_Reject,
10131 // Label 571: @27614
10132 GIM_Reject,
10133 // Label 471: @27615
10134 GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(28822),
10135 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10136 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10137 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10138 GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(27695), // Rule ID 1826 //
10139 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10140 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10141 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
10142 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10143 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
10144 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
10145 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
10146 GIM_CheckIsSafeToFold, /*NumInsns*/2,
10147 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
10148 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
10149 // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (USUBLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
10150 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv16i8_v8i16),
10151 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10152 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
10153 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
10154 GIR_RootConstrainSelectedInstOperands,
10155 // GIR_Coverage, 1826,
10156 GIR_EraseRootFromParent_Done,
10157 // Label 575: @27695
10158 GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(27760), // Rule ID 1825 //
10159 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10160 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10161 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
10162 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10163 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
10164 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
10165 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
10166 GIM_CheckIsSafeToFold, /*NumInsns*/2,
10167 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
10168 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
10169 // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (USUBLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
10170 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv16i8_v8i16),
10171 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10172 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
10173 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
10174 GIR_RootConstrainSelectedInstOperands,
10175 // GIR_Coverage, 1825,
10176 GIR_EraseRootFromParent_Done,
10177 // Label 576: @27760
10178 GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(27825), // Rule ID 1742 //
10179 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10180 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10181 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
10182 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10183 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
10184 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
10185 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
10186 GIM_CheckIsSafeToFold, /*NumInsns*/2,
10187 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
10188 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
10189 // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (SSUBLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
10190 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv16i8_v8i16),
10191 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10192 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
10193 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
10194 GIR_RootConstrainSelectedInstOperands,
10195 // GIR_Coverage, 1742,
10196 GIR_EraseRootFromParent_Done,
10197 // Label 577: @27825
10198 GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(27890), // Rule ID 1824 //
10199 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10200 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10201 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
10202 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10203 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
10204 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
10205 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
10206 GIM_CheckIsSafeToFold, /*NumInsns*/2,
10207 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
10208 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
10209 // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (USUBLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
10210 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv16i8_v8i16),
10211 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10212 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
10213 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
10214 GIR_RootConstrainSelectedInstOperands,
10215 // GIR_Coverage, 1824,
10216 GIR_EraseRootFromParent_Done,
10217 // Label 578: @27890
10218 GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(27955), // Rule ID 1823 //
10219 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10220 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10221 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
10222 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10223 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
10224 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
10225 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
10226 GIM_CheckIsSafeToFold, /*NumInsns*/2,
10227 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
10228 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
10229 // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (USUBLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
10230 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv16i8_v8i16),
10231 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10232 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
10233 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
10234 GIR_RootConstrainSelectedInstOperands,
10235 // GIR_Coverage, 1823,
10236 GIR_EraseRootFromParent_Done,
10237 // Label 579: @27955
10238 GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(28018), // Rule ID 1718 //
10239 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10240 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10241 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10242 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
10243 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10244 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
10245 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10246 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
10247 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
10248 // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64smull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (SMLSLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
10249 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv16i8_v8i16),
10250 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10251 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
10252 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
10253 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
10254 GIR_RootConstrainSelectedInstOperands,
10255 // GIR_Coverage, 1718,
10256 GIR_EraseRootFromParent_Done,
10257 // Label 580: @28018
10258 GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(28081), // Rule ID 1808 //
10259 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10260 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10261 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10262 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
10263 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10264 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
10265 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10266 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
10267 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
10268 // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64umull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (UMLSLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
10269 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv16i8_v8i16),
10270 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10271 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
10272 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
10273 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
10274 GIR_RootConstrainSelectedInstOperands,
10275 // GIR_Coverage, 1808,
10276 GIR_EraseRootFromParent_Done,
10277 // Label 581: @28081
10278 GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(28128), // Rule ID 1846 //
10279 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10280 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10281 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10282 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
10283 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10284 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10285 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
10286 // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (USUBWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
10287 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv16i8_v8i16),
10288 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10289 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
10290 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
10291 GIR_RootConstrainSelectedInstOperands,
10292 // GIR_Coverage, 1846,
10293 GIR_EraseRootFromParent_Done,
10294 // Label 582: @28128
10295 GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(28175), // Rule ID 1748 //
10296 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10297 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10298 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10299 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
10300 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10301 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10302 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
10303 // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (SSUBWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
10304 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv16i8_v8i16),
10305 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10306 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
10307 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
10308 GIR_RootConstrainSelectedInstOperands,
10309 // GIR_Coverage, 1748,
10310 GIR_EraseRootFromParent_Done,
10311 // Label 583: @28175
10312 GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(28222), // Rule ID 1845 //
10313 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10314 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10315 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10316 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
10317 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10318 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10319 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
10320 // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (USUBWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
10321 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv16i8_v8i16),
10322 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10323 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
10324 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
10325 GIR_RootConstrainSelectedInstOperands,
10326 // GIR_Coverage, 1845,
10327 GIR_EraseRootFromParent_Done,
10328 // Label 584: @28222
10329 GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(28281), // Rule ID 1822 //
10330 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10331 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10332 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
10333 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10334 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10335 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
10336 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
10337 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
10338 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10339 GIM_CheckIsSafeToFold, /*NumInsns*/2,
10340 // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
10341 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
10342 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10343 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
10344 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
10345 GIR_RootConstrainSelectedInstOperands,
10346 // GIR_Coverage, 1822,
10347 GIR_EraseRootFromParent_Done,
10348 // Label 585: @28281
10349 GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(28340), // Rule ID 1821 //
10350 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10351 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10352 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
10353 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10354 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10355 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
10356 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
10357 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
10358 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10359 GIM_CheckIsSafeToFold, /*NumInsns*/2,
10360 // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
10361 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
10362 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
10364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
10365 GIR_RootConstrainSelectedInstOperands,
10366 // GIR_Coverage, 1821,
10367 GIR_EraseRootFromParent_Done,
10368 // Label 586: @28340
10369 GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(28399), // Rule ID 1741 //
10370 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10371 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10372 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
10373 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10374 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10375 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
10376 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
10377 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
10378 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10379 GIM_CheckIsSafeToFold, /*NumInsns*/2,
10380 // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SSUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
10381 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv8i8_v8i16),
10382 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
10384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
10385 GIR_RootConstrainSelectedInstOperands,
10386 // GIR_Coverage, 1741,
10387 GIR_EraseRootFromParent_Done,
10388 // Label 587: @28399
10389 GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(28458), // Rule ID 1820 //
10390 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10391 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10392 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
10393 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10394 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10395 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
10396 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
10397 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
10398 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10399 GIM_CheckIsSafeToFold, /*NumInsns*/2,
10400 // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
10401 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
10402 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
10404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
10405 GIR_RootConstrainSelectedInstOperands,
10406 // GIR_Coverage, 1820,
10407 GIR_EraseRootFromParent_Done,
10408 // Label 588: @28458
10409 GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(28517), // Rule ID 1819 //
10410 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10411 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10412 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
10413 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10414 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10415 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
10416 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
10417 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
10418 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10419 GIM_CheckIsSafeToFold, /*NumInsns*/2,
10420 // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
10421 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
10422 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10423 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
10424 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
10425 GIR_RootConstrainSelectedInstOperands,
10426 // GIR_Coverage, 1819,
10427 GIR_EraseRootFromParent_Done,
10428 // Label 589: @28517
10429 GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(28552), // Rule ID 955 //
10430 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10431 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10432 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10433 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
10434 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10435 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10436 // (sub:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn) => (NEGv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
10437 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv8i16),
10438 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10439 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
10440 GIR_RootConstrainSelectedInstOperands,
10441 // GIR_Coverage, 955,
10442 GIR_EraseRootFromParent_Done,
10443 // Label 590: @28552
10444 GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(28609), // Rule ID 1717 //
10445 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10446 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10447 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10448 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
10449 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10450 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
10451 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10452 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10453 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10454 // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64smull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (SMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
10455 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv8i8_v8i16),
10456 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10457 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
10458 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
10459 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
10460 GIR_RootConstrainSelectedInstOperands,
10461 // GIR_Coverage, 1717,
10462 GIR_EraseRootFromParent_Done,
10463 // Label 591: @28609
10464 GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(28666), // Rule ID 1807 //
10465 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10466 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10467 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10468 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
10469 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10470 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
10471 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10472 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10473 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10474 // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64umull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (UMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
10475 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv8i8_v8i16),
10476 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10477 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
10478 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
10479 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
10480 GIR_RootConstrainSelectedInstOperands,
10481 // GIR_Coverage, 1807,
10482 GIR_EraseRootFromParent_Done,
10483 // Label 592: @28666
10484 GIM_Try, /*On fail goto*//*Label 593*/ GIMT_Encode4(28710), // Rule ID 1844 //
10485 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10486 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10487 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10488 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
10489 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10490 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10491 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10492 // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
10493 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv8i8_v8i16),
10494 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10495 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
10496 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
10497 GIR_RootConstrainSelectedInstOperands,
10498 // GIR_Coverage, 1844,
10499 GIR_EraseRootFromParent_Done,
10500 // Label 593: @28710
10501 GIM_Try, /*On fail goto*//*Label 594*/ GIMT_Encode4(28754), // Rule ID 1747 //
10502 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10503 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10504 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10505 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
10506 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10507 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10508 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10509 // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (SSUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
10510 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv8i8_v8i16),
10511 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10512 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
10513 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
10514 GIR_RootConstrainSelectedInstOperands,
10515 // GIR_Coverage, 1747,
10516 GIR_EraseRootFromParent_Done,
10517 // Label 594: @28754
10518 GIM_Try, /*On fail goto*//*Label 595*/ GIMT_Encode4(28798), // Rule ID 1843 //
10519 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10520 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10521 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10522 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
10523 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
10524 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10525 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10526 // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm)) => (USUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
10527 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv8i8_v8i16),
10528 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10529 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
10530 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
10531 GIR_RootConstrainSelectedInstOperands,
10532 // GIR_Coverage, 1843,
10533 GIR_EraseRootFromParent_Done,
10534 // Label 595: @28798
10535 GIM_Try, /*On fail goto*//*Label 596*/ GIMT_Encode4(28821), // Rule ID 1462 //
10536 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10537 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10538 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10539 // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
10540 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv8i16),
10541 GIR_RootConstrainSelectedInstOperands,
10542 // GIR_Coverage, 1462,
10543 GIR_Done,
10544 // Label 596: @28821
10545 GIM_Reject,
10546 // Label 574: @28822
10547 GIM_Reject,
10548 // Label 472: @28823
10549 GIM_Try, /*On fail goto*//*Label 597*/ GIMT_Encode4(28897),
10550 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10551 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10552 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10553 GIM_Try, /*On fail goto*//*Label 598*/ GIMT_Encode4(28873), // Rule ID 953 //
10554 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10555 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10556 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
10557 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
10558 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10559 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10560 // (sub:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn) => (NEGv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
10561 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv16i8),
10562 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10563 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
10564 GIR_RootConstrainSelectedInstOperands,
10565 // GIR_Coverage, 953,
10566 GIR_EraseRootFromParent_Done,
10567 // Label 598: @28873
10568 GIM_Try, /*On fail goto*//*Label 599*/ GIMT_Encode4(28896), // Rule ID 1460 //
10569 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10570 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10571 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10572 // (sub:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
10573 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv16i8),
10574 GIR_RootConstrainSelectedInstOperands,
10575 // GIR_Coverage, 1460,
10576 GIR_Done,
10577 // Label 599: @28896
10578 GIM_Reject,
10579 // Label 597: @28897
10580 GIM_Reject,
10581 // Label 473: @28898
10582 GIM_Try, /*On fail goto*//*Label 600*/ GIMT_Encode4(28923), // Rule ID 7103 //
10583 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
10584 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
10585 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
10586 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
10587 // (sub:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (SUB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
10588 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUB_ZZZ_D),
10589 GIR_RootConstrainSelectedInstOperands,
10590 // GIR_Coverage, 7103,
10591 GIR_Done,
10592 // Label 600: @28923
10593 GIM_Reject,
10594 // Label 474: @28924
10595 GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(28949), // Rule ID 7102 //
10596 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
10597 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
10598 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
10599 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
10600 // (sub:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SUB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
10601 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUB_ZZZ_S),
10602 GIR_RootConstrainSelectedInstOperands,
10603 // GIR_Coverage, 7102,
10604 GIR_Done,
10605 // Label 601: @28949
10606 GIM_Reject,
10607 // Label 475: @28950
10608 GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(28975), // Rule ID 7101 //
10609 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
10610 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
10611 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
10612 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
10613 // (sub:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SUB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
10614 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUB_ZZZ_H),
10615 GIR_RootConstrainSelectedInstOperands,
10616 // GIR_Coverage, 7101,
10617 GIR_Done,
10618 // Label 602: @28975
10619 GIM_Reject,
10620 // Label 476: @28976
10621 GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(29001), // Rule ID 7100 //
10622 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
10623 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
10624 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
10625 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
10626 // (sub:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SUB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
10627 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUB_ZZZ_B),
10628 GIR_RootConstrainSelectedInstOperands,
10629 // GIR_Coverage, 7100,
10630 GIR_Done,
10631 // Label 603: @29001
10632 GIM_Reject,
10633 // Label 477: @29002
10634 GIM_Reject,
10635 // Label 2: @29003
10636 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 612*/ GIMT_Encode4(30374),
10637 /*GILLT_s32*//*Label 604*/ GIMT_Encode4(29054),
10638 /*GILLT_s64*//*Label 605*/ GIMT_Encode4(29211), GIMT_Encode4(0),
10639 /*GILLT_v2s32*//*Label 606*/ GIMT_Encode4(29642), GIMT_Encode4(0),
10640 /*GILLT_v4s16*//*Label 607*/ GIMT_Encode4(29808),
10641 /*GILLT_v4s32*//*Label 608*/ GIMT_Encode4(29974),
10642 /*GILLT_v8s8*//*Label 609*/ GIMT_Encode4(30140),
10643 /*GILLT_v8s16*//*Label 610*/ GIMT_Encode4(30174),
10644 /*GILLT_v16s8*//*Label 611*/ GIMT_Encode4(30340),
10645 // Label 604: @29054
10646 GIM_Try, /*On fail goto*//*Label 613*/ GIMT_Encode4(29210),
10647 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
10648 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
10649 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
10650 GIM_Try, /*On fail goto*//*Label 614*/ GIMT_Encode4(29124), // Rule ID 3824 //
10651 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10652 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
10653 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
10654 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
10655 GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0,
10656 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
10657 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
10658 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10659 // (mul:{ *:[i32] } (sub:{ *:[i32] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rn), GPR32:{ *:[i32] }:$Rm) => (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
10660 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBWrrr),
10661 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10662 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
10663 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
10664 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10665 GIR_RootConstrainSelectedInstOperands,
10666 // GIR_Coverage, 3824,
10667 GIR_EraseRootFromParent_Done,
10668 // Label 614: @29124
10669 GIM_Try, /*On fail goto*//*Label 615*/ GIMT_Encode4(29179), // Rule ID 13021 //
10670 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
10671 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10672 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
10673 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
10674 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
10675 GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0,
10676 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
10677 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10678 // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, (sub:{ *:[i32] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rn)) => (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
10679 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBWrrr),
10680 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10681 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
10682 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
10683 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10684 GIR_RootConstrainSelectedInstOperands,
10685 // GIR_Coverage, 13021,
10686 GIR_EraseRootFromParent_Done,
10687 // Label 615: @29179
10688 GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(29209), // Rule ID 3820 //
10689 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
10690 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
10691 // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (MADDWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
10692 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MADDWrrr),
10693 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10694 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
10695 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
10696 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10697 GIR_RootConstrainSelectedInstOperands,
10698 // GIR_Coverage, 3820,
10699 GIR_EraseRootFromParent_Done,
10700 // Label 616: @29209
10701 GIM_Reject,
10702 // Label 613: @29210
10703 GIM_Reject,
10704 // Label 605: @29211
10705 GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(29641),
10706 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
10707 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
10708 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
10709 GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(29281), // Rule ID 3825 //
10710 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10711 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
10712 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
10713 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
10714 GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0,
10715 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
10716 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
10717 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10718 // (mul:{ *:[i64] } (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rn), GPR64:{ *:[i64] }:$Rm) => (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
10719 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBXrrr),
10720 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10721 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
10722 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
10723 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10724 GIR_RootConstrainSelectedInstOperands,
10725 // GIR_Coverage, 3825,
10726 GIR_EraseRootFromParent_Done,
10727 // Label 618: @29281
10728 GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(29336), // Rule ID 13022 //
10729 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
10730 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10731 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
10732 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
10733 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
10734 GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0,
10735 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
10736 GIM_CheckIsSafeToFold, /*NumInsns*/1,
10737 // (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rn)) => (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
10738 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBXrrr),
10739 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10740 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
10741 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
10742 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10743 GIR_RootConstrainSelectedInstOperands,
10744 // GIR_Coverage, 13022,
10745 GIR_EraseRootFromParent_Done,
10746 // Label 619: @29336
10747 GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(29411), // Rule ID 3834 //
10748 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10749 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
10750 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
10751 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
10752 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
10753 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
10754 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
10755 // MIs[2] Operand 1
10756 // No operand predicates
10757 GIM_CheckIsSafeToFold, /*NumInsns*/2,
10758 // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
10759 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
10760 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
10761 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
10762 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
10763 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
10764 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
10765 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10766 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
10767 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10768 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10769 GIR_RootConstrainSelectedInstOperands,
10770 // GIR_Coverage, 3834,
10771 GIR_EraseRootFromParent_Done,
10772 // Label 620: @29411
10773 GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(29486), // Rule ID 3835 //
10774 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10775 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
10776 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
10777 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
10778 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
10779 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
10780 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i64imm_32bit),
10781 // MIs[2] Operand 1
10782 // No operand predicates
10783 GIM_CheckIsSafeToFold, /*NumInsns*/2,
10784 // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
10785 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
10786 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
10787 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
10788 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
10789 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
10790 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
10791 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10792 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
10793 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10794 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10795 GIR_RootConstrainSelectedInstOperands,
10796 // GIR_Coverage, 3835,
10797 GIR_EraseRootFromParent_Done,
10798 // Label 621: @29486
10799 GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(29548), // Rule ID 3828 //
10800 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10801 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
10802 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
10803 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
10804 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
10805 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
10806 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
10807 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
10808 GIM_CheckIsSafeToFold, /*NumInsns*/2,
10809 // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
10810 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
10811 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
10813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
10814 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10815 GIR_RootConstrainSelectedInstOperands,
10816 // GIR_Coverage, 3828,
10817 GIR_EraseRootFromParent_Done,
10818 // Label 622: @29548
10819 GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(29610), // Rule ID 3831 //
10820 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10821 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
10822 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
10823 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
10824 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
10825 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
10826 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
10827 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
10828 GIM_CheckIsSafeToFold, /*NumInsns*/2,
10829 // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
10830 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
10831 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10832 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
10833 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
10834 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10835 GIR_RootConstrainSelectedInstOperands,
10836 // GIR_Coverage, 3831,
10837 GIR_EraseRootFromParent_Done,
10838 // Label 623: @29610
10839 GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(29640), // Rule ID 3821 //
10840 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
10841 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
10842 // (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (MADDXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
10843 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MADDXrrr),
10844 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10845 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
10846 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
10847 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10848 GIR_RootConstrainSelectedInstOperands,
10849 // GIR_Coverage, 3821,
10850 GIR_EraseRootFromParent_Done,
10851 // Label 624: @29640
10852 GIM_Reject,
10853 // Label 617: @29641
10854 GIM_Reject,
10855 // Label 606: @29642
10856 GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(29807),
10857 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
10858 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
10859 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10860 GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(29720), // Rule ID 12716 //
10861 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10862 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10863 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
10864 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10865 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
10866 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10867 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
10868 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
10869 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
10870 // MIs[2] Operand 1
10871 // No operand predicates
10872 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10873 GIM_CheckIsSafeToFold, /*NumInsns*/2,
10874 // (mul:{ *:[v2i32] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn) => (MULv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
10875 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv2i32_indexed),
10876 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10877 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
10878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
10879 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
10880 GIR_RootConstrainSelectedInstOperands,
10881 // GIR_Coverage, 12716,
10882 GIR_EraseRootFromParent_Done,
10883 // Label 626: @29720
10884 GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(29783), // Rule ID 2022 //
10885 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10886 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10887 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10888 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
10889 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10890 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
10891 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10892 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
10893 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
10894 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
10895 // MIs[2] Operand 1
10896 // No operand predicates
10897 GIM_CheckIsSafeToFold, /*NumInsns*/2,
10898 // (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (MULv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
10899 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv2i32_indexed),
10900 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10901 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
10902 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
10903 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
10904 GIR_RootConstrainSelectedInstOperands,
10905 // GIR_Coverage, 2022,
10906 GIR_EraseRootFromParent_Done,
10907 // Label 627: @29783
10908 GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(29806), // Rule ID 1339 //
10909 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10910 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10911 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10912 // (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (MULv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
10913 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::MULv2i32),
10914 GIR_RootConstrainSelectedInstOperands,
10915 // GIR_Coverage, 1339,
10916 GIR_Done,
10917 // Label 628: @29806
10918 GIM_Reject,
10919 // Label 625: @29807
10920 GIM_Reject,
10921 // Label 607: @29808
10922 GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(29973),
10923 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
10924 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
10925 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10926 GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(29886), // Rule ID 12713 //
10927 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10928 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10929 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
10930 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
10931 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
10932 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
10933 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
10934 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
10935 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
10936 // MIs[2] Operand 1
10937 // No operand predicates
10938 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10939 GIM_CheckIsSafeToFold, /*NumInsns*/2,
10940 // (mul:{ *:[v4i16] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn) => (MULv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
10941 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv4i16_indexed),
10942 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10943 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
10944 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
10945 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
10946 GIR_RootConstrainSelectedInstOperands,
10947 // GIR_Coverage, 12713,
10948 GIR_EraseRootFromParent_Done,
10949 // Label 630: @29886
10950 GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(29949), // Rule ID 2019 //
10951 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10952 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10953 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10954 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
10955 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
10956 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
10957 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
10958 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
10959 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
10960 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
10961 // MIs[2] Operand 1
10962 // No operand predicates
10963 GIM_CheckIsSafeToFold, /*NumInsns*/2,
10964 // (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (MULv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
10965 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv4i16_indexed),
10966 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
10967 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
10968 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
10969 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
10970 GIR_RootConstrainSelectedInstOperands,
10971 // GIR_Coverage, 2019,
10972 GIR_EraseRootFromParent_Done,
10973 // Label 631: @29949
10974 GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(29972), // Rule ID 1337 //
10975 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10976 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10977 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
10978 // (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (MULv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
10979 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::MULv4i16),
10980 GIR_RootConstrainSelectedInstOperands,
10981 // GIR_Coverage, 1337,
10982 GIR_Done,
10983 // Label 632: @29972
10984 GIM_Reject,
10985 // Label 629: @29973
10986 GIM_Reject,
10987 // Label 608: @29974
10988 GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(30139),
10989 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10990 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10991 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10992 GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(30052), // Rule ID 12717 //
10993 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10994 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
10995 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
10996 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
10997 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
10998 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
10999 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
11000 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
11001 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
11002 // MIs[2] Operand 1
11003 // No operand predicates
11004 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11005 GIM_CheckIsSafeToFold, /*NumInsns*/2,
11006 // (mul:{ *:[v4i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4i32] }:$Rn) => (MULv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
11007 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv4i32_indexed),
11008 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11009 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
11010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
11011 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
11012 GIR_RootConstrainSelectedInstOperands,
11013 // GIR_Coverage, 12717,
11014 GIR_EraseRootFromParent_Done,
11015 // Label 634: @30052
11016 GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(30115), // Rule ID 2023 //
11017 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11018 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11019 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
11020 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
11021 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
11022 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
11023 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11024 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
11025 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
11026 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
11027 // MIs[2] Operand 1
11028 // No operand predicates
11029 GIM_CheckIsSafeToFold, /*NumInsns*/2,
11030 // (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (MULv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
11031 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv4i32_indexed),
11032 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11033 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
11034 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
11035 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
11036 GIR_RootConstrainSelectedInstOperands,
11037 // GIR_Coverage, 2023,
11038 GIR_EraseRootFromParent_Done,
11039 // Label 635: @30115
11040 GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(30138), // Rule ID 1340 //
11041 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11042 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11043 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11044 // (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (MULv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
11045 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::MULv4i32),
11046 GIR_RootConstrainSelectedInstOperands,
11047 // GIR_Coverage, 1340,
11048 GIR_Done,
11049 // Label 636: @30138
11050 GIM_Reject,
11051 // Label 633: @30139
11052 GIM_Reject,
11053 // Label 609: @30140
11054 GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(30173), // Rule ID 1335 //
11055 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11056 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
11057 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
11058 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
11059 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
11060 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
11061 // (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (MULv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
11062 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::MULv8i8),
11063 GIR_RootConstrainSelectedInstOperands,
11064 // GIR_Coverage, 1335,
11065 GIR_Done,
11066 // Label 637: @30173
11067 GIM_Reject,
11068 // Label 610: @30174
11069 GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(30339),
11070 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
11071 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11072 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11073 GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(30252), // Rule ID 12714 //
11074 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11075 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11076 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
11077 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
11078 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
11079 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
11080 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
11081 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
11082 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
11083 // MIs[2] Operand 1
11084 // No operand predicates
11085 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11086 GIM_CheckIsSafeToFold, /*NumInsns*/2,
11087 // (mul:{ *:[v8i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8i16] }:$Rn) => (MULv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
11088 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv8i16_indexed),
11089 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11090 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
11091 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
11092 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
11093 GIR_RootConstrainSelectedInstOperands,
11094 // GIR_Coverage, 12714,
11095 GIR_EraseRootFromParent_Done,
11096 // Label 639: @30252
11097 GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(30315), // Rule ID 2020 //
11098 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11099 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11100 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
11101 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
11102 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
11103 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
11104 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
11105 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
11106 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
11107 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
11108 // MIs[2] Operand 1
11109 // No operand predicates
11110 GIM_CheckIsSafeToFold, /*NumInsns*/2,
11111 // (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (MULv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
11112 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv8i16_indexed),
11113 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11114 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
11115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
11116 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
11117 GIR_RootConstrainSelectedInstOperands,
11118 // GIR_Coverage, 2020,
11119 GIR_EraseRootFromParent_Done,
11120 // Label 640: @30315
11121 GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(30338), // Rule ID 1338 //
11122 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11123 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11124 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11125 // (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (MULv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
11126 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::MULv8i16),
11127 GIR_RootConstrainSelectedInstOperands,
11128 // GIR_Coverage, 1338,
11129 GIR_Done,
11130 // Label 641: @30338
11131 GIM_Reject,
11132 // Label 638: @30339
11133 GIM_Reject,
11134 // Label 611: @30340
11135 GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(30373), // Rule ID 1336 //
11136 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11137 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
11138 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11139 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11140 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11141 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11142 // (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (MULv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
11143 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::MULv16i8),
11144 GIR_RootConstrainSelectedInstOperands,
11145 // GIR_Coverage, 1336,
11146 GIR_Done,
11147 // Label 642: @30373
11148 GIM_Reject,
11149 // Label 612: @30374
11150 GIM_Reject,
11151 // Label 3: @30375
11152 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 645*/ GIMT_Encode4(30456),
11153 /*GILLT_s32*//*Label 643*/ GIMT_Encode4(30394),
11154 /*GILLT_s64*//*Label 644*/ GIMT_Encode4(30425),
11155 // Label 643: @30394
11156 GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(30424), // Rule ID 128 //
11157 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
11158 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11159 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11160 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11161 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11162 // (sdiv:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (SDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
11163 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SDIVWr),
11164 GIR_RootConstrainSelectedInstOperands,
11165 // GIR_Coverage, 128,
11166 GIR_Done,
11167 // Label 646: @30424
11168 GIM_Reject,
11169 // Label 644: @30425
11170 GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(30455), // Rule ID 129 //
11171 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11172 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
11173 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11174 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11175 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11176 // (sdiv:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
11177 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SDIVXr),
11178 GIR_RootConstrainSelectedInstOperands,
11179 // GIR_Coverage, 129,
11180 GIR_Done,
11181 // Label 647: @30455
11182 GIM_Reject,
11183 // Label 645: @30456
11184 GIM_Reject,
11185 // Label 4: @30457
11186 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 650*/ GIMT_Encode4(30538),
11187 /*GILLT_s32*//*Label 648*/ GIMT_Encode4(30476),
11188 /*GILLT_s64*//*Label 649*/ GIMT_Encode4(30507),
11189 // Label 648: @30476
11190 GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(30506), // Rule ID 126 //
11191 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
11192 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11193 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11194 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11195 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11196 // (udiv:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (UDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
11197 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UDIVWr),
11198 GIR_RootConstrainSelectedInstOperands,
11199 // GIR_Coverage, 126,
11200 GIR_Done,
11201 // Label 651: @30506
11202 GIM_Reject,
11203 // Label 649: @30507
11204 GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(30537), // Rule ID 127 //
11205 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11206 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
11207 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11208 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11209 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11210 // (udiv:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (UDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
11211 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UDIVXr),
11212 GIR_RootConstrainSelectedInstOperands,
11213 // GIR_Coverage, 127,
11214 GIR_Done,
11215 // Label 652: @30537
11216 GIM_Reject,
11217 // Label 650: @30538
11218 GIM_Reject,
11219 // Label 5: @30539
11220 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(24), /*)*//*default:*//*Label 671*/ GIMT_Encode4(34220),
11221 /*GILLT_s32*//*Label 653*/ GIMT_Encode4(30638),
11222 /*GILLT_s64*//*Label 654*/ GIMT_Encode4(31136), GIMT_Encode4(0),
11223 /*GILLT_v2s32*//*Label 655*/ GIMT_Encode4(32571),
11224 /*GILLT_v2s64*//*Label 656*/ GIMT_Encode4(32731),
11225 /*GILLT_v4s16*//*Label 657*/ GIMT_Encode4(32891),
11226 /*GILLT_v4s32*//*Label 658*/ GIMT_Encode4(33051),
11227 /*GILLT_v8s8*//*Label 659*/ GIMT_Encode4(33211),
11228 /*GILLT_v8s16*//*Label 660*/ GIMT_Encode4(33371),
11229 /*GILLT_v16s8*//*Label 661*/ GIMT_Encode4(33531),
11230 /*GILLT_nxv1s1*//*Label 662*/ GIMT_Encode4(33691),
11231 /*GILLT_nxv2s1*//*Label 663*/ GIMT_Encode4(33776), GIMT_Encode4(0), GIMT_Encode4(0),
11232 /*GILLT_nxv2s64*//*Label 664*/ GIMT_Encode4(33861),
11233 /*GILLT_nxv4s1*//*Label 665*/ GIMT_Encode4(33887), GIMT_Encode4(0),
11234 /*GILLT_nxv4s32*//*Label 666*/ GIMT_Encode4(33972),
11235 /*GILLT_nxv8s1*//*Label 667*/ GIMT_Encode4(33998),
11236 /*GILLT_nxv8s16*//*Label 668*/ GIMT_Encode4(34083),
11237 /*GILLT_nxv16s1*//*Label 669*/ GIMT_Encode4(34109),
11238 /*GILLT_nxv16s8*//*Label 670*/ GIMT_Encode4(34194),
11239 // Label 653: @30638
11240 GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(31135),
11241 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
11242 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11243 GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(30704), // Rule ID 12474 //
11244 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11245 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11246 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11247 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
11248 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
11249 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
11250 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11251 GIM_CheckIsSafeToFold, /*NumInsns*/1,
11252 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
11253 // (and:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (BICWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
11254 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICWrs),
11255 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11256 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
11257 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
11258 GIR_RootConstrainSelectedInstOperands,
11259 // GIR_Coverage, 12474,
11260 GIR_EraseRootFromParent_Done,
11261 // Label 673: @30704
11262 GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(30759), // Rule ID 173 //
11263 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11264 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11265 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
11266 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11267 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
11268 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
11269 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
11270 GIM_CheckIsSafeToFold, /*NumInsns*/1,
11271 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
11272 // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] })) => (BICWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
11273 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICWrs),
11274 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11275 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
11276 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
11277 GIR_RootConstrainSelectedInstOperands,
11278 // GIR_Coverage, 173,
11279 GIR_EraseRootFromParent_Done,
11280 // Label 674: @30759
11281 GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(30828), // Rule ID 5314 //
11282 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11283 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11284 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
11285 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
11286 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
11287 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11288 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
11289 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
11290 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
11291 // MIs[2] Operand 1
11292 // No operand predicates
11293 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
11294 GIM_CheckIsSafeToFold, /*NumInsns*/2,
11295 // (and:{ *:[i32] } (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), 255:{ *:[i32] }) => (UMOVvi8:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)
11296 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi8),
11297 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11298 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
11299 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
11300 GIR_RootConstrainSelectedInstOperands,
11301 // GIR_Coverage, 5314,
11302 GIR_EraseRootFromParent_Done,
11303 // Label 675: @30828
11304 GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(30897), // Rule ID 5315 //
11305 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11306 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11307 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
11308 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
11309 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
11310 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11311 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
11312 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
11313 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
11314 // MIs[2] Operand 1
11315 // No operand predicates
11316 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
11317 GIM_CheckIsSafeToFold, /*NumInsns*/2,
11318 // (and:{ *:[i32] } (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 65535:{ *:[i32] }) => (UMOVvi16:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
11319 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi16),
11320 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
11322 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
11323 GIR_RootConstrainSelectedInstOperands,
11324 // GIR_Coverage, 5315,
11325 GIR_EraseRootFromParent_Done,
11326 // Label 676: @30897
11327 GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(30950), // Rule ID 12472 //
11328 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11329 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11330 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11331 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
11332 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
11333 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11334 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
11335 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11336 GIM_CheckIsSafeToFold, /*NumInsns*/1,
11337 // (and:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (BICWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
11338 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICWrr),
11339 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11340 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
11341 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
11342 GIR_RootConstrainSelectedInstOperands,
11343 // GIR_Coverage, 12472,
11344 GIR_EraseRootFromParent_Done,
11345 // Label 677: @30950
11346 GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(31003), // Rule ID 171 //
11347 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11348 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11349 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
11350 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11351 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
11352 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
11353 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11354 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
11355 GIM_CheckIsSafeToFold, /*NumInsns*/1,
11356 // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (BICWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
11357 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICWrr),
11358 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11359 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
11360 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
11361 GIR_RootConstrainSelectedInstOperands,
11362 // GIR_Coverage, 171,
11363 GIR_EraseRootFromParent_Done,
11364 // Label 678: @31003
11365 GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(31044), // Rule ID 153 //
11366 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
11367 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11368 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
11369 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
11370 GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_logical_imm32),
11371 // MIs[1] Operand 1
11372 // No operand predicates
11373 GIM_CheckIsSafeToFold, /*NumInsns*/1,
11374 // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_logical_imm32>><<X:logical_imm32_XFORM>>:$imm) => (ANDWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (logical_imm32_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm))
11375 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDWri),
11376 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11377 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
11378 GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm32), // imm
11379 GIR_RootConstrainSelectedInstOperands,
11380 // GIR_Coverage, 153,
11381 GIR_EraseRootFromParent_Done,
11382 // Label 679: @31044
11383 GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(31077), // Rule ID 12470 //
11384 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11385 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11386 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
11387 // (and:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn) => (ANDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
11388 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDWrs),
11389 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11390 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
11391 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
11392 GIR_RootConstrainSelectedInstOperands,
11393 // GIR_Coverage, 12470,
11394 GIR_EraseRootFromParent_Done,
11395 // Label 680: @31077
11396 GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(31110), // Rule ID 169 //
11397 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11398 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11399 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
11400 // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) => (ANDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
11401 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDWrs),
11402 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11403 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
11404 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
11405 GIR_RootConstrainSelectedInstOperands,
11406 // GIR_Coverage, 169,
11407 GIR_EraseRootFromParent_Done,
11408 // Label 681: @31110
11409 GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(31134), // Rule ID 167 //
11410 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11411 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11412 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
11413 // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (ANDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
11414 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDWrr),
11415 GIR_RootConstrainSelectedInstOperands,
11416 // GIR_Coverage, 167,
11417 GIR_Done,
11418 // Label 682: @31134
11419 GIM_Reject,
11420 // Label 672: @31135
11421 GIM_Reject,
11422 // Label 654: @31136
11423 GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(32570),
11424 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11425 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
11426 GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(31202), // Rule ID 12475 //
11427 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11428 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11429 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11430 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
11431 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
11432 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
11433 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11434 GIM_CheckIsSafeToFold, /*NumInsns*/1,
11435 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
11436 // (and:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (BICXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
11437 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICXrs),
11438 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11439 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
11440 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
11441 GIR_RootConstrainSelectedInstOperands,
11442 // GIR_Coverage, 12475,
11443 GIR_EraseRootFromParent_Done,
11444 // Label 684: @31202
11445 GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(31257), // Rule ID 174 //
11446 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11447 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11448 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
11449 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11450 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
11451 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
11452 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
11453 GIM_CheckIsSafeToFold, /*NumInsns*/1,
11454 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
11455 // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] })) => (BICXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
11456 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICXrs),
11457 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11458 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
11459 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
11460 GIR_RootConstrainSelectedInstOperands,
11461 // GIR_Coverage, 174,
11462 GIR_EraseRootFromParent_Done,
11463 // Label 685: @31257
11464 GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(31370), // Rule ID 5316 //
11465 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
11466 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11467 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
11468 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
11469 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11470 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
11471 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
11472 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
11473 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11474 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11475 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
11476 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
11477 // MIs[3] Operand 1
11478 // No operand predicates
11479 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
11480 GIM_CheckIsSafeToFold, /*NumInsns*/3,
11481 // (and:{ *:[i64] } (anyext:{ *:[i64] } (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)), 255:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (UMOVvi8:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), sub_32:{ *:[i32] })
11482 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
11483 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi8),
11484 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
11485 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
11486 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // idx
11487 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
11488 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
11489 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
11490 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11491 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11492 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
11493 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
11494 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
11495 // GIR_Coverage, 5316,
11496 GIR_EraseRootFromParent_Done,
11497 // Label 686: @31370
11498 GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(31483), // Rule ID 5317 //
11499 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
11500 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11501 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
11502 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
11503 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
11504 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
11505 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
11506 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
11507 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11508 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
11509 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
11510 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
11511 // MIs[3] Operand 1
11512 // No operand predicates
11513 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
11514 GIM_CheckIsSafeToFold, /*NumInsns*/3,
11515 // (and:{ *:[i64] } (anyext:{ *:[i64] } (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), 65535:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (UMOVvi16:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), sub_32:{ *:[i32] })
11516 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
11517 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi16),
11518 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
11519 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
11520 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // idx
11521 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
11522 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
11523 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
11524 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11525 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11526 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
11527 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
11528 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
11529 // GIR_Coverage, 5317,
11530 GIR_EraseRootFromParent_Done,
11531 // Label 687: @31483
11532 GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(31582), // Rule ID 6822 //
11533 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
11534 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11535 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
11536 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
11537 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
11538 // MIs[1] addr
11539 GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64,
11540 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
11541 GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_1),
11542 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
11543 GIM_CheckIsSafeToFold, /*NumInsns*/1,
11544 // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 548:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_1>>, 255:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
11545 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
11546 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDXRB),
11547 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
11548 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr
11549 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
11550 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
11551 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
11552 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
11553 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11554 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11555 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
11556 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
11557 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
11558 // GIR_Coverage, 6822,
11559 GIR_EraseRootFromParent_Done,
11560 // Label 688: @31582
11561 GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(31681), // Rule ID 6823 //
11562 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
11563 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11564 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
11565 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
11566 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
11567 // MIs[1] addr
11568 GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64,
11569 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
11570 GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_2),
11571 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
11572 GIM_CheckIsSafeToFold, /*NumInsns*/1,
11573 // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 548:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_2>>, 65535:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
11574 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
11575 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDXRH),
11576 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
11577 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr
11578 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
11579 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
11580 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
11581 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
11582 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11583 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11584 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
11585 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
11586 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
11587 // GIR_Coverage, 6823,
11588 GIR_EraseRootFromParent_Done,
11589 // Label 689: @31681
11590 GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(31780), // Rule ID 6824 //
11591 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
11592 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11593 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
11594 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
11595 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
11596 // MIs[1] addr
11597 GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64,
11598 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
11599 GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_4),
11600 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294967295),
11601 GIM_CheckIsSafeToFold, /*NumInsns*/1,
11602 // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 548:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_4>>, 4294967295:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
11603 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
11604 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDXRW),
11605 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
11606 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr
11607 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
11608 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
11609 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
11610 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
11611 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11612 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11613 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
11614 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
11615 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
11616 // GIR_Coverage, 6824,
11617 GIR_EraseRootFromParent_Done,
11618 // Label 690: @31780
11619 GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(31879), // Rule ID 6829 //
11620 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
11621 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11622 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
11623 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
11624 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
11625 // MIs[1] addr
11626 GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64,
11627 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
11628 GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_1),
11629 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
11630 GIM_CheckIsSafeToFold, /*NumInsns*/1,
11631 // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 545:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_1>>, 255:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
11632 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
11633 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDAXRB),
11634 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
11635 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr
11636 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
11637 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
11638 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
11639 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
11640 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11641 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11642 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
11643 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
11644 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
11645 // GIR_Coverage, 6829,
11646 GIR_EraseRootFromParent_Done,
11647 // Label 691: @31879
11648 GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(31978), // Rule ID 6830 //
11649 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
11650 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11651 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
11652 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
11653 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
11654 // MIs[1] addr
11655 GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64,
11656 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
11657 GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_2),
11658 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
11659 GIM_CheckIsSafeToFold, /*NumInsns*/1,
11660 // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 545:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_2>>, 65535:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
11661 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
11662 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDAXRH),
11663 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
11664 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr
11665 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
11666 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
11667 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
11668 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
11669 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11670 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11671 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
11672 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
11673 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
11674 // GIR_Coverage, 6830,
11675 GIR_EraseRootFromParent_Done,
11676 // Label 692: @31978
11677 GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(32077), // Rule ID 6831 //
11678 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
11679 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11680 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
11681 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
11682 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
11683 // MIs[1] addr
11684 GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64,
11685 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
11686 GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_4),
11687 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294967295),
11688 GIM_CheckIsSafeToFold, /*NumInsns*/1,
11689 // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 545:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_4>>, 4294967295:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
11690 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
11691 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDAXRW),
11692 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
11693 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr
11694 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
11695 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
11696 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
11697 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
11698 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11699 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11700 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
11701 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
11702 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
11703 // GIR_Coverage, 6831,
11704 GIR_EraseRootFromParent_Done,
11705 // Label 693: @32077
11706 GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(32130), // Rule ID 12473 //
11707 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11708 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11709 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11710 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
11711 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
11712 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11713 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
11714 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11715 GIM_CheckIsSafeToFold, /*NumInsns*/1,
11716 // (and:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (BICXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
11717 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICXrr),
11718 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11719 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
11720 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
11721 GIR_RootConstrainSelectedInstOperands,
11722 // GIR_Coverage, 12473,
11723 GIR_EraseRootFromParent_Done,
11724 // Label 694: @32130
11725 GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(32183), // Rule ID 172 //
11726 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11727 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11728 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
11729 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11730 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
11731 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
11732 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11733 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
11734 GIM_CheckIsSafeToFold, /*NumInsns*/1,
11735 // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] })) => (BICXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
11736 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICXrr),
11737 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11738 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
11739 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
11740 GIR_RootConstrainSelectedInstOperands,
11741 // GIR_Coverage, 172,
11742 GIR_EraseRootFromParent_Done,
11743 // Label 695: @32183
11744 GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(32283), // Rule ID 3873 //
11745 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
11746 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11747 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294967295),
11748 // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 4294967295:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (ORRWrr:{ *:[i32] } WZR:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
11749 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
11750 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
11751 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11752 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
11753 GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(16), // Rn
11754 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
11755 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
11756 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORRWrr),
11757 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
11758 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11759 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
11760 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
11761 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
11762 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
11763 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11764 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11765 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
11766 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
11767 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
11768 // GIR_Coverage, 3873,
11769 GIR_EraseRootFromParent_Done,
11770 // Label 696: @32283
11771 GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(32324), // Rule ID 154 //
11772 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
11773 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11774 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
11775 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
11776 GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_logical_imm64),
11777 // MIs[1] Operand 1
11778 // No operand predicates
11779 GIM_CheckIsSafeToFold, /*NumInsns*/1,
11780 // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_logical_imm64>><<X:logical_imm64_XFORM>>:$imm) => (ANDXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (logical_imm64_XFORM:{ *:[i64] } (imm:{ *:[i64] }):$imm))
11781 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDXri),
11782 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11783 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
11784 GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm64), // imm
11785 GIR_RootConstrainSelectedInstOperands,
11786 // GIR_Coverage, 154,
11787 GIR_EraseRootFromParent_Done,
11788 // Label 697: @32324
11789 GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(32357), // Rule ID 12471 //
11790 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11791 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11792 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
11793 // (and:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn) => (ANDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
11794 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDXrs),
11795 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11796 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
11797 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
11798 GIR_RootConstrainSelectedInstOperands,
11799 // GIR_Coverage, 12471,
11800 GIR_EraseRootFromParent_Done,
11801 // Label 698: @32357
11802 GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(32390), // Rule ID 170 //
11803 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11804 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11805 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
11806 // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) => (ANDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
11807 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDXrs),
11808 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11809 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
11810 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
11811 GIR_RootConstrainSelectedInstOperands,
11812 // GIR_Coverage, 170,
11813 GIR_EraseRootFromParent_Done,
11814 // Label 699: @32390
11815 GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(32454), // Rule ID 13136 //
11816 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11817 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
11818 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11819 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11820 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
11821 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
11822 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
11823 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
11824 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11825 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
11826 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
11827 GIM_CheckIsSafeToFold, /*NumInsns*/2,
11828 // (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$LHS) => (BICv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
11829 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
11830 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11831 GIR_RootToRootCopy, /*OpIdx*/2, // LHS
11832 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
11833 GIR_RootConstrainSelectedInstOperands,
11834 // GIR_Coverage, 13136,
11835 GIR_EraseRootFromParent_Done,
11836 // Label 700: @32454
11837 GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(32518), // Rule ID 4692 //
11838 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11839 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
11840 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
11841 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
11842 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11843 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
11844 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
11845 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
11846 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
11847 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11848 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
11849 GIM_CheckIsSafeToFold, /*NumInsns*/2,
11850 // (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] })) => (BICv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
11851 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
11852 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11853 GIR_RootToRootCopy, /*OpIdx*/1, // LHS
11854 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
11855 GIR_RootConstrainSelectedInstOperands,
11856 // GIR_Coverage, 4692,
11857 GIR_EraseRootFromParent_Done,
11858 // Label 701: @32518
11859 GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(32542), // Rule ID 168 //
11860 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11861 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11862 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
11863 // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ANDXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
11864 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDXrr),
11865 GIR_RootConstrainSelectedInstOperands,
11866 // GIR_Coverage, 168,
11867 GIR_Done,
11868 // Label 702: @32542
11869 GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(32569), // Rule ID 2410 //
11870 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11871 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
11872 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
11873 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
11874 // (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) => (ANDv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
11875 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv8i8),
11876 GIR_RootConstrainSelectedInstOperands,
11877 // GIR_Coverage, 2410,
11878 GIR_Done,
11879 // Label 703: @32569
11880 GIM_Reject,
11881 // Label 683: @32570
11882 GIM_Reject,
11883 // Label 655: @32571
11884 GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(32730),
11885 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11886 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
11887 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
11888 GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(32646), // Rule ID 13135 //
11889 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11890 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11891 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11892 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
11893 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
11894 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
11895 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
11896 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11897 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
11898 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
11899 GIM_CheckIsSafeToFold, /*NumInsns*/2,
11900 // (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$LHS) => (BICv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
11901 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
11902 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11903 GIR_RootToRootCopy, /*OpIdx*/2, // LHS
11904 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
11905 GIR_RootConstrainSelectedInstOperands,
11906 // GIR_Coverage, 13135,
11907 GIR_EraseRootFromParent_Done,
11908 // Label 705: @32646
11909 GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(32706), // Rule ID 4691 //
11910 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11911 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
11912 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
11913 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11914 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
11915 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
11916 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
11917 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
11918 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11919 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
11920 GIM_CheckIsSafeToFold, /*NumInsns*/2,
11921 // (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] })) => (BICv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
11922 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
11923 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11924 GIR_RootToRootCopy, /*OpIdx*/1, // LHS
11925 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
11926 GIR_RootConstrainSelectedInstOperands,
11927 // GIR_Coverage, 4691,
11928 GIR_EraseRootFromParent_Done,
11929 // Label 706: @32706
11930 GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(32729), // Rule ID 2409 //
11931 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11932 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
11933 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
11934 // (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (ANDv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
11935 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv8i8),
11936 GIR_RootConstrainSelectedInstOperands,
11937 // GIR_Coverage, 2409,
11938 GIR_Done,
11939 // Label 707: @32729
11940 GIM_Reject,
11941 // Label 704: @32730
11942 GIM_Reject,
11943 // Label 656: @32731
11944 GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(32890),
11945 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
11946 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11947 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11948 GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(32806), // Rule ID 13139 //
11949 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11950 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
11951 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11952 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
11953 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
11954 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11955 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
11956 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11957 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
11958 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11959 GIM_CheckIsSafeToFold, /*NumInsns*/2,
11960 // (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$LHS) => (BICv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
11961 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
11962 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11963 GIR_RootToRootCopy, /*OpIdx*/2, // LHS
11964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
11965 GIR_RootConstrainSelectedInstOperands,
11966 // GIR_Coverage, 13139,
11967 GIR_EraseRootFromParent_Done,
11968 // Label 709: @32806
11969 GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(32866), // Rule ID 4695 //
11970 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11971 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11972 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
11973 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
11974 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
11975 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
11976 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11977 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
11978 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
11979 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
11980 GIM_CheckIsSafeToFold, /*NumInsns*/2,
11981 // (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] })) => (BICv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
11982 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
11983 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
11984 GIR_RootToRootCopy, /*OpIdx*/1, // LHS
11985 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
11986 GIR_RootConstrainSelectedInstOperands,
11987 // GIR_Coverage, 4695,
11988 GIR_EraseRootFromParent_Done,
11989 // Label 710: @32866
11990 GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(32889), // Rule ID 2413 //
11991 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11992 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11993 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
11994 // (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (ANDv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
11995 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
11996 GIR_RootConstrainSelectedInstOperands,
11997 // GIR_Coverage, 2413,
11998 GIR_Done,
11999 // Label 711: @32889
12000 GIM_Reject,
12001 // Label 708: @32890
12002 GIM_Reject,
12003 // Label 657: @32891
12004 GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(33050),
12005 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
12006 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
12007 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12008 GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(32966), // Rule ID 13134 //
12009 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12010 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12011 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12012 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
12013 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
12014 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12015 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
12016 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12017 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
12018 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12019 GIM_CheckIsSafeToFold, /*NumInsns*/2,
12020 // (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$LHS) => (BICv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
12021 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
12022 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12023 GIR_RootToRootCopy, /*OpIdx*/2, // LHS
12024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
12025 GIR_RootConstrainSelectedInstOperands,
12026 // GIR_Coverage, 13134,
12027 GIR_EraseRootFromParent_Done,
12028 // Label 713: @32966
12029 GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(33026), // Rule ID 4690 //
12030 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12031 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12032 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12033 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12034 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
12035 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
12036 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12037 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
12038 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12039 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
12040 GIM_CheckIsSafeToFold, /*NumInsns*/2,
12041 // (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] })) => (BICv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
12042 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
12043 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12044 GIR_RootToRootCopy, /*OpIdx*/1, // LHS
12045 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
12046 GIR_RootConstrainSelectedInstOperands,
12047 // GIR_Coverage, 4690,
12048 GIR_EraseRootFromParent_Done,
12049 // Label 714: @33026
12050 GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(33049), // Rule ID 2408 //
12051 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12052 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12053 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12054 // (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (ANDv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
12055 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv8i8),
12056 GIR_RootConstrainSelectedInstOperands,
12057 // GIR_Coverage, 2408,
12058 GIR_Done,
12059 // Label 715: @33049
12060 GIM_Reject,
12061 // Label 712: @33050
12062 GIM_Reject,
12063 // Label 658: @33051
12064 GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(33210),
12065 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12066 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12067 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12068 GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(33126), // Rule ID 13138 //
12069 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12070 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12071 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12072 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12073 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12074 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12075 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
12076 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12077 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
12078 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12079 GIM_CheckIsSafeToFold, /*NumInsns*/2,
12080 // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$LHS) => (BICv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
12081 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
12082 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12083 GIR_RootToRootCopy, /*OpIdx*/2, // LHS
12084 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
12085 GIR_RootConstrainSelectedInstOperands,
12086 // GIR_Coverage, 13138,
12087 GIR_EraseRootFromParent_Done,
12088 // Label 717: @33126
12089 GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(33186), // Rule ID 4694 //
12090 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12091 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12092 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12093 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12094 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
12095 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
12096 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12097 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
12098 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12099 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
12100 GIM_CheckIsSafeToFold, /*NumInsns*/2,
12101 // (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] })) => (BICv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
12102 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
12103 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12104 GIR_RootToRootCopy, /*OpIdx*/1, // LHS
12105 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
12106 GIR_RootConstrainSelectedInstOperands,
12107 // GIR_Coverage, 4694,
12108 GIR_EraseRootFromParent_Done,
12109 // Label 718: @33186
12110 GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(33209), // Rule ID 2412 //
12111 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12112 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12113 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12114 // (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (ANDv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
12115 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
12116 GIR_RootConstrainSelectedInstOperands,
12117 // GIR_Coverage, 2412,
12118 GIR_Done,
12119 // Label 719: @33209
12120 GIM_Reject,
12121 // Label 716: @33210
12122 GIM_Reject,
12123 // Label 659: @33211
12124 GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(33370),
12125 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
12126 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
12127 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12128 GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(33286), // Rule ID 12610 //
12129 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12130 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12131 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12132 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
12133 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
12134 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12135 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
12136 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12137 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
12138 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12139 GIM_CheckIsSafeToFold, /*NumInsns*/2,
12140 // (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rn) => (BICv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
12141 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
12142 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12143 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
12144 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
12145 GIR_RootConstrainSelectedInstOperands,
12146 // GIR_Coverage, 12610,
12147 GIR_EraseRootFromParent_Done,
12148 // Label 721: @33286
12149 GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(33346), // Rule ID 1584 //
12150 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12151 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12152 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12153 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12154 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
12155 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
12156 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12157 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
12158 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12159 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
12160 GIM_CheckIsSafeToFold, /*NumInsns*/2,
12161 // (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] })) => (BICv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
12162 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
12163 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12164 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
12165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
12166 GIR_RootConstrainSelectedInstOperands,
12167 // GIR_Coverage, 1584,
12168 GIR_EraseRootFromParent_Done,
12169 // Label 722: @33346
12170 GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(33369), // Rule ID 1582 //
12171 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12172 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12173 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12174 // (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ANDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
12175 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv8i8),
12176 GIR_RootConstrainSelectedInstOperands,
12177 // GIR_Coverage, 1582,
12178 GIR_Done,
12179 // Label 723: @33369
12180 GIM_Reject,
12181 // Label 720: @33370
12182 GIM_Reject,
12183 // Label 660: @33371
12184 GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(33530),
12185 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12186 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12187 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12188 GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(33446), // Rule ID 13137 //
12189 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12190 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12191 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12192 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
12193 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
12194 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12195 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
12196 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12197 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
12198 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12199 GIM_CheckIsSafeToFold, /*NumInsns*/2,
12200 // (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$LHS) => (BICv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
12201 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
12202 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12203 GIR_RootToRootCopy, /*OpIdx*/2, // LHS
12204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
12205 GIR_RootConstrainSelectedInstOperands,
12206 // GIR_Coverage, 13137,
12207 GIR_EraseRootFromParent_Done,
12208 // Label 725: @33446
12209 GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(33506), // Rule ID 4693 //
12210 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12211 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12212 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12213 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12214 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
12215 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
12216 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12217 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
12218 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12219 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
12220 GIM_CheckIsSafeToFold, /*NumInsns*/2,
12221 // (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] })) => (BICv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
12222 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
12223 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12224 GIR_RootToRootCopy, /*OpIdx*/1, // LHS
12225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
12226 GIR_RootConstrainSelectedInstOperands,
12227 // GIR_Coverage, 4693,
12228 GIR_EraseRootFromParent_Done,
12229 // Label 726: @33506
12230 GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(33529), // Rule ID 2411 //
12231 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12232 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12233 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12234 // (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (ANDv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
12235 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
12236 GIR_RootConstrainSelectedInstOperands,
12237 // GIR_Coverage, 2411,
12238 GIR_Done,
12239 // Label 727: @33529
12240 GIM_Reject,
12241 // Label 724: @33530
12242 GIM_Reject,
12243 // Label 661: @33531
12244 GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(33690),
12245 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
12246 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
12247 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12248 GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(33606), // Rule ID 12611 //
12249 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12250 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12251 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12252 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
12253 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
12254 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12255 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
12256 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12257 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
12258 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12259 GIM_CheckIsSafeToFold, /*NumInsns*/2,
12260 // (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rn) => (BICv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
12261 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
12262 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12263 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
12264 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
12265 GIR_RootConstrainSelectedInstOperands,
12266 // GIR_Coverage, 12611,
12267 GIR_EraseRootFromParent_Done,
12268 // Label 729: @33606
12269 GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(33666), // Rule ID 1585 //
12270 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12271 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12272 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12273 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12274 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
12275 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
12276 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12277 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
12278 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12279 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
12280 GIM_CheckIsSafeToFold, /*NumInsns*/2,
12281 // (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] })) => (BICv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
12282 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
12283 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12284 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
12285 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
12286 GIR_RootConstrainSelectedInstOperands,
12287 // GIR_Coverage, 1585,
12288 GIR_EraseRootFromParent_Done,
12289 // Label 730: @33666
12290 GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(33689), // Rule ID 1583 //
12291 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12292 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12293 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
12294 // (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ANDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
12295 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
12296 GIR_RootConstrainSelectedInstOperands,
12297 // GIR_Coverage, 1583,
12298 GIR_Done,
12299 // Label 731: @33689
12300 GIM_Reject,
12301 // Label 728: @33690
12302 GIM_Reject,
12303 // Label 662: @33691
12304 GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(33775),
12305 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1,
12306 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
12307 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
12308 GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(33753), // Rule ID 10330 //
12309 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
12310 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
12311 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
12312 // (and:{ *:[nxv1i1] } PPR:{ *:[nxv1i1] }:$Ps1, PPR:{ *:[nxv1i1] }:$Ps2) => (AND_PPzPP:{ *:[nxv1i1] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv1i1] }:$Ps1, PPR:{ *:[nxv1i1] }:$Ps2)
12313 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
12314 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
12315 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
12316 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
12317 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12318 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
12319 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
12320 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12321 GIR_RootToRootCopy, /*OpIdx*/1, // Ps1
12322 GIR_RootToRootCopy, /*OpIdx*/2, // Ps2
12323 GIR_RootConstrainSelectedInstOperands,
12324 // GIR_Coverage, 10330,
12325 GIR_EraseRootFromParent_Done,
12326 // Label 733: @33753
12327 GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(33774), // Rule ID 2657 //
12328 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
12329 // (and:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2) => (AND_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
12330 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
12331 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
12332 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
12333 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
12334 GIR_RootToRootCopy, /*OpIdx*/2, // Op2
12335 GIR_RootConstrainSelectedInstOperands,
12336 // GIR_Coverage, 2657,
12337 GIR_EraseRootFromParent_Done,
12338 // Label 734: @33774
12339 GIM_Reject,
12340 // Label 732: @33775
12341 GIM_Reject,
12342 // Label 663: @33776
12343 GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(33860),
12344 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
12345 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
12346 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
12347 GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(33838), // Rule ID 10329 //
12348 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
12349 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
12350 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
12351 // (and:{ *:[nxv2i1] } PPR:{ *:[nxv2i1] }:$Ps1, PPR:{ *:[nxv2i1] }:$Ps2) => (AND_PPzPP:{ *:[nxv2i1] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv2i1] }:$Ps1, PPR:{ *:[nxv2i1] }:$Ps2)
12352 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
12353 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
12354 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
12355 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
12356 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12357 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
12358 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
12359 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12360 GIR_RootToRootCopy, /*OpIdx*/1, // Ps1
12361 GIR_RootToRootCopy, /*OpIdx*/2, // Ps2
12362 GIR_RootConstrainSelectedInstOperands,
12363 // GIR_Coverage, 10329,
12364 GIR_EraseRootFromParent_Done,
12365 // Label 736: @33838
12366 GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(33859), // Rule ID 2656 //
12367 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
12368 // (and:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2) => (AND_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
12369 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
12370 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
12371 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
12372 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
12373 GIR_RootToRootCopy, /*OpIdx*/2, // Op2
12374 GIR_RootConstrainSelectedInstOperands,
12375 // GIR_Coverage, 2656,
12376 GIR_EraseRootFromParent_Done,
12377 // Label 737: @33859
12378 GIM_Reject,
12379 // Label 735: @33860
12380 GIM_Reject,
12381 // Label 664: @33861
12382 GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(33886), // Rule ID 3071 //
12383 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
12384 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
12385 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
12386 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
12387 // (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (AND_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
12388 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::AND_ZZZ),
12389 GIR_RootConstrainSelectedInstOperands,
12390 // GIR_Coverage, 3071,
12391 GIR_Done,
12392 // Label 738: @33886
12393 GIM_Reject,
12394 // Label 665: @33887
12395 GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(33971),
12396 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
12397 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
12398 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
12399 GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(33949), // Rule ID 10328 //
12400 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
12401 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
12402 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
12403 // (and:{ *:[nxv4i1] } PPR:{ *:[nxv4i1] }:$Ps1, PPR:{ *:[nxv4i1] }:$Ps2) => (AND_PPzPP:{ *:[nxv4i1] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv4i1] }:$Ps1, PPR:{ *:[nxv4i1] }:$Ps2)
12404 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
12405 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
12406 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
12407 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
12408 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12409 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
12410 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
12411 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12412 GIR_RootToRootCopy, /*OpIdx*/1, // Ps1
12413 GIR_RootToRootCopy, /*OpIdx*/2, // Ps2
12414 GIR_RootConstrainSelectedInstOperands,
12415 // GIR_Coverage, 10328,
12416 GIR_EraseRootFromParent_Done,
12417 // Label 740: @33949
12418 GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(33970), // Rule ID 2655 //
12419 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
12420 // (and:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2) => (AND_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
12421 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
12422 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
12423 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
12424 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
12425 GIR_RootToRootCopy, /*OpIdx*/2, // Op2
12426 GIR_RootConstrainSelectedInstOperands,
12427 // GIR_Coverage, 2655,
12428 GIR_EraseRootFromParent_Done,
12429 // Label 741: @33970
12430 GIM_Reject,
12431 // Label 739: @33971
12432 GIM_Reject,
12433 // Label 666: @33972
12434 GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(33997), // Rule ID 3070 //
12435 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
12436 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
12437 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
12438 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
12439 // (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (AND_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
12440 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::AND_ZZZ),
12441 GIR_RootConstrainSelectedInstOperands,
12442 // GIR_Coverage, 3070,
12443 GIR_Done,
12444 // Label 742: @33997
12445 GIM_Reject,
12446 // Label 667: @33998
12447 GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(34082),
12448 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
12449 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
12450 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
12451 GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(34060), // Rule ID 10327 //
12452 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
12453 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
12454 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
12455 // (and:{ *:[nxv8i1] } PPR:{ *:[nxv8i1] }:$Ps1, PPR:{ *:[nxv8i1] }:$Ps2) => (AND_PPzPP:{ *:[nxv8i1] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv8i1] }:$Ps1, PPR:{ *:[nxv8i1] }:$Ps2)
12456 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
12457 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
12458 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
12459 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
12460 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12461 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
12462 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
12463 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12464 GIR_RootToRootCopy, /*OpIdx*/1, // Ps1
12465 GIR_RootToRootCopy, /*OpIdx*/2, // Ps2
12466 GIR_RootConstrainSelectedInstOperands,
12467 // GIR_Coverage, 10327,
12468 GIR_EraseRootFromParent_Done,
12469 // Label 744: @34060
12470 GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(34081), // Rule ID 2654 //
12471 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
12472 // (and:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2) => (AND_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
12473 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
12474 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
12475 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
12476 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
12477 GIR_RootToRootCopy, /*OpIdx*/2, // Op2
12478 GIR_RootConstrainSelectedInstOperands,
12479 // GIR_Coverage, 2654,
12480 GIR_EraseRootFromParent_Done,
12481 // Label 745: @34081
12482 GIM_Reject,
12483 // Label 743: @34082
12484 GIM_Reject,
12485 // Label 668: @34083
12486 GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(34108), // Rule ID 3069 //
12487 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
12488 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
12489 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
12490 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
12491 // (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (AND_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
12492 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::AND_ZZZ),
12493 GIR_RootConstrainSelectedInstOperands,
12494 // GIR_Coverage, 3069,
12495 GIR_Done,
12496 // Label 746: @34108
12497 GIM_Reject,
12498 // Label 669: @34109
12499 GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(34193),
12500 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
12501 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
12502 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
12503 GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(34171), // Rule ID 10326 //
12504 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
12505 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
12506 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
12507 // (and:{ *:[nxv16i1] } PPR:{ *:[nxv16i1] }:$Ps1, PPR:{ *:[nxv16i1] }:$Ps2) => (AND_PPzPP:{ *:[nxv16i1] } (PTRUE_B:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv16i1] }:$Ps1, PPR:{ *:[nxv16i1] }:$Ps2)
12508 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
12509 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_B),
12510 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
12511 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
12512 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
12513 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
12514 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
12515 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12516 GIR_RootToRootCopy, /*OpIdx*/1, // Ps1
12517 GIR_RootToRootCopy, /*OpIdx*/2, // Ps2
12518 GIR_RootConstrainSelectedInstOperands,
12519 // GIR_Coverage, 10326,
12520 GIR_EraseRootFromParent_Done,
12521 // Label 748: @34171
12522 GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(34192), // Rule ID 2653 //
12523 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
12524 // (and:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2) => (AND_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
12525 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
12526 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
12527 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
12528 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
12529 GIR_RootToRootCopy, /*OpIdx*/2, // Op2
12530 GIR_RootConstrainSelectedInstOperands,
12531 // GIR_Coverage, 2653,
12532 GIR_EraseRootFromParent_Done,
12533 // Label 749: @34192
12534 GIM_Reject,
12535 // Label 747: @34193
12536 GIM_Reject,
12537 // Label 670: @34194
12538 GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(34219), // Rule ID 3068 //
12539 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
12540 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
12541 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
12542 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
12543 // (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (AND_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
12544 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::AND_ZZZ),
12545 GIR_RootConstrainSelectedInstOperands,
12546 // GIR_Coverage, 3068,
12547 GIR_Done,
12548 // Label 750: @34219
12549 GIM_Reject,
12550 // Label 671: @34220
12551 GIM_Reject,
12552 // Label 6: @34221
12553 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(24), /*)*//*default:*//*Label 769*/ GIMT_Encode4(46267),
12554 /*GILLT_s32*//*Label 751*/ GIMT_Encode4(34320),
12555 /*GILLT_s64*//*Label 752*/ GIMT_Encode4(34680), GIMT_Encode4(0),
12556 /*GILLT_v2s32*//*Label 753*/ GIMT_Encode4(36847),
12557 /*GILLT_v2s64*//*Label 754*/ GIMT_Encode4(38155),
12558 /*GILLT_v4s16*//*Label 755*/ GIMT_Encode4(39463),
12559 /*GILLT_v4s32*//*Label 756*/ GIMT_Encode4(40771),
12560 /*GILLT_v8s8*//*Label 757*/ GIMT_Encode4(42079),
12561 /*GILLT_v8s16*//*Label 758*/ GIMT_Encode4(43387),
12562 /*GILLT_v16s8*//*Label 759*/ GIMT_Encode4(44695),
12563 /*GILLT_nxv1s1*//*Label 760*/ GIMT_Encode4(46003),
12564 /*GILLT_nxv2s1*//*Label 761*/ GIMT_Encode4(46035), GIMT_Encode4(0), GIMT_Encode4(0),
12565 /*GILLT_nxv2s64*//*Label 762*/ GIMT_Encode4(46067),
12566 /*GILLT_nxv4s1*//*Label 763*/ GIMT_Encode4(46093), GIMT_Encode4(0),
12567 /*GILLT_nxv4s32*//*Label 764*/ GIMT_Encode4(46125),
12568 /*GILLT_nxv8s1*//*Label 765*/ GIMT_Encode4(46151),
12569 /*GILLT_nxv8s16*//*Label 766*/ GIMT_Encode4(46183),
12570 /*GILLT_nxv16s1*//*Label 767*/ GIMT_Encode4(46209),
12571 /*GILLT_nxv16s8*//*Label 768*/ GIMT_Encode4(46241),
12572 // Label 751: @34320
12573 GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(34679),
12574 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
12575 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12576 GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(34386), // Rule ID 12494 //
12577 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
12578 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12579 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12580 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12581 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12582 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
12583 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
12584 GIM_CheckIsSafeToFold, /*NumInsns*/1,
12585 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
12586 // (or:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (ORNWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
12587 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNWrs),
12588 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12589 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
12590 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
12591 GIR_RootConstrainSelectedInstOperands,
12592 // GIR_Coverage, 12494,
12593 GIR_EraseRootFromParent_Done,
12594 // Label 771: @34386
12595 GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(34441), // Rule ID 185 //
12596 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
12597 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
12598 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12599 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12600 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12601 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12602 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
12603 GIM_CheckIsSafeToFold, /*NumInsns*/1,
12604 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
12605 // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] })) => (ORNWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
12606 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNWrs),
12607 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12608 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
12609 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
12610 GIR_RootConstrainSelectedInstOperands,
12611 // GIR_Coverage, 185,
12612 GIR_EraseRootFromParent_Done,
12613 // Label 772: @34441
12614 GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(34482), // Rule ID 157 //
12615 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
12616 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
12617 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12618 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
12619 GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_logical_imm32),
12620 // MIs[1] Operand 1
12621 // No operand predicates
12622 GIM_CheckIsSafeToFold, /*NumInsns*/1,
12623 // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_logical_imm32>><<X:logical_imm32_XFORM>>:$imm) => (ORRWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (logical_imm32_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm))
12624 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORRWri),
12625 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12626 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
12627 GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm32), // imm
12628 GIR_RootConstrainSelectedInstOperands,
12629 // GIR_Coverage, 157,
12630 GIR_EraseRootFromParent_Done,
12631 // Label 773: @34482
12632 GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(34515), // Rule ID 12496 //
12633 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
12634 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
12635 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
12636 // (or:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn) => (ORRWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
12637 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORRWrs),
12638 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12639 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
12640 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
12641 GIR_RootConstrainSelectedInstOperands,
12642 // GIR_Coverage, 12496,
12643 GIR_EraseRootFromParent_Done,
12644 // Label 774: @34515
12645 GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(34548), // Rule ID 189 //
12646 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
12647 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
12648 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
12649 // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) => (ORRWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
12650 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORRWrs),
12651 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12652 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
12653 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
12654 GIR_RootConstrainSelectedInstOperands,
12655 // GIR_Coverage, 189,
12656 GIR_EraseRootFromParent_Done,
12657 // Label 775: @34548
12658 GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(34601), // Rule ID 12492 //
12659 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
12660 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12661 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12662 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12663 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12664 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
12665 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
12666 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
12667 GIM_CheckIsSafeToFold, /*NumInsns*/1,
12668 // (or:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (ORNWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
12669 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
12670 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12671 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
12672 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
12673 GIR_RootConstrainSelectedInstOperands,
12674 // GIR_Coverage, 12492,
12675 GIR_EraseRootFromParent_Done,
12676 // Label 776: @34601
12677 GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(34654), // Rule ID 183 //
12678 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
12679 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
12680 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12681 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12682 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
12683 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
12684 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
12685 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
12686 GIM_CheckIsSafeToFold, /*NumInsns*/1,
12687 // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (ORNWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
12688 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
12689 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12690 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
12691 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
12692 GIR_RootConstrainSelectedInstOperands,
12693 // GIR_Coverage, 183,
12694 GIR_EraseRootFromParent_Done,
12695 // Label 777: @34654
12696 GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(34678), // Rule ID 187 //
12697 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
12698 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
12699 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
12700 // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (ORRWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
12701 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRWrr),
12702 GIR_RootConstrainSelectedInstOperands,
12703 // GIR_Coverage, 187,
12704 GIR_Done,
12705 // Label 778: @34678
12706 GIM_Reject,
12707 // Label 770: @34679
12708 GIM_Reject,
12709 // Label 752: @34680
12710 GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(36846),
12711 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
12712 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
12713 GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(34813), // Rule ID 3884 //
12714 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
12715 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12716 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
12717 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
12718 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
12719 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12720 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
12721 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
12722 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
12723 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
12724 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8,
12725 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(71777214294589695),
12726 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
12727 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
12728 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
12729 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
12730 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
12731 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
12732 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
12733 // MIs[4] Rn
12734 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
12735 GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
12736 GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(-71777214294589696),
12737 GIM_CheckIsSafeToFold, /*NumInsns*/4,
12738 // (or:{ *:[i64] } (and:{ *:[i64] } (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 8:{ *:[i64] }), 71777214294589695:{ *:[i64] }), (and:{ *:[i64] } (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 8:{ *:[i64] }), -71777214294589696:{ *:[i64] })) => (REV16Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
12739 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV16Xr),
12740 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12741 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
12742 GIR_RootConstrainSelectedInstOperands,
12743 // GIR_Coverage, 3884,
12744 GIR_EraseRootFromParent_Done,
12745 // Label 780: @34813
12746 GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(34935), // Rule ID 13044 //
12747 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
12748 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12749 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
12750 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
12751 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
12752 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12753 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
12754 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
12755 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
12756 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
12757 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8,
12758 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(-71777214294589696),
12759 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
12760 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
12761 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
12762 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
12763 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
12764 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
12765 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
12766 // MIs[4] Rn
12767 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
12768 GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
12769 GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(71777214294589695),
12770 GIM_CheckIsSafeToFold, /*NumInsns*/4,
12771 // (or:{ *:[i64] } (and:{ *:[i64] } (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 8:{ *:[i64] }), -71777214294589696:{ *:[i64] }), (and:{ *:[i64] } (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 8:{ *:[i64] }), 71777214294589695:{ *:[i64] })) => (REV16Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
12772 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV16Xr),
12773 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12774 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
12775 GIR_RootConstrainSelectedInstOperands,
12776 // GIR_Coverage, 13044,
12777 GIR_EraseRootFromParent_Done,
12778 // Label 781: @34935
12779 GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(34990), // Rule ID 12495 //
12780 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
12781 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12782 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12783 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
12784 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
12785 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
12786 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
12787 GIM_CheckIsSafeToFold, /*NumInsns*/1,
12788 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
12789 // (or:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (ORNXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
12790 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNXrs),
12791 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12792 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
12793 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
12794 GIR_RootConstrainSelectedInstOperands,
12795 // GIR_Coverage, 12495,
12796 GIR_EraseRootFromParent_Done,
12797 // Label 782: @34990
12798 GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(35045), // Rule ID 186 //
12799 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
12800 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
12801 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
12802 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
12803 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
12804 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
12805 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
12806 GIM_CheckIsSafeToFold, /*NumInsns*/1,
12807 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
12808 // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] })) => (ORNXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
12809 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNXrs),
12810 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
12811 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
12812 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
12813 GIR_RootConstrainSelectedInstOperands,
12814 // GIR_Coverage, 186,
12815 GIR_EraseRootFromParent_Done,
12816 // Label 783: @35045
12817 GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(35154), // Rule ID 12844 //
12818 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12819 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12820 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12821 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
12822 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
12823 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
12824 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12825 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
12826 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
12827 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
12828 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12829 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12830 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12831 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
12832 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12833 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
12834 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
12835 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64,
12836 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12837 // MIs[4] LHS
12838 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
12839 GIM_CheckIsSafeToFold, /*NumInsns*/4,
12840 // (or:{ *:[v1i64] } (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
12841 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
12842 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
12843 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
12844 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
12845 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
12846 GIR_RootConstrainSelectedInstOperands,
12847 // GIR_Coverage, 12844,
12848 GIR_EraseRootFromParent_Done,
12849 // Label 784: @35154
12850 GIM_Try, /*On fail goto*//*Label 785*/ GIMT_Encode4(35263), // Rule ID 12843 //
12851 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12852 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12853 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12854 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
12855 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
12856 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
12857 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
12858 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
12859 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
12860 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
12861 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12862 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12863 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12864 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
12865 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12866 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
12867 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
12868 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
12869 // MIs[4] LHS
12870 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
12871 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12872 GIM_CheckIsSafeToFold, /*NumInsns*/4,
12873 // (or:{ *:[v1i64] } (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
12874 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
12875 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
12876 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
12877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
12878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
12879 GIR_RootConstrainSelectedInstOperands,
12880 // GIR_Coverage, 12843,
12881 GIR_EraseRootFromParent_Done,
12882 // Label 785: @35263
12883 GIM_Try, /*On fail goto*//*Label 786*/ GIMT_Encode4(35372), // Rule ID 12846 //
12884 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12885 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12886 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12887 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
12888 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
12889 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
12890 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12891 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
12892 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
12893 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
12894 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
12895 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12896 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12897 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12898 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
12899 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
12900 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
12901 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64,
12902 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12903 // MIs[4] LHS
12904 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
12905 GIM_CheckIsSafeToFold, /*NumInsns*/4,
12906 // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] })), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
12907 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
12908 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
12909 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
12910 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
12911 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
12912 GIR_RootConstrainSelectedInstOperands,
12913 // GIR_Coverage, 12846,
12914 GIR_EraseRootFromParent_Done,
12915 // Label 786: @35372
12916 GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(35481), // Rule ID 12845 //
12917 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12918 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12919 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12920 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
12921 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
12922 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
12923 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12924 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
12925 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
12926 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
12927 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
12928 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12929 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
12930 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12931 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
12932 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
12933 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
12934 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
12935 // MIs[4] LHS
12936 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
12937 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12938 GIM_CheckIsSafeToFold, /*NumInsns*/4,
12939 // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] })), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
12940 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
12941 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
12942 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
12943 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
12944 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
12945 GIR_RootConstrainSelectedInstOperands,
12946 // GIR_Coverage, 12845,
12947 GIR_EraseRootFromParent_Done,
12948 // Label 787: @35481
12949 GIM_Try, /*On fail goto*//*Label 788*/ GIMT_Encode4(35590), // Rule ID 2397 //
12950 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12951 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12952 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12953 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
12954 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
12955 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
12956 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12957 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12958 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
12959 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
12960 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
12961 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
12962 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
12963 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
12964 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
12965 // MIs[3] LHS
12966 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
12967 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
12968 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
12969 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
12970 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12971 GIM_CheckIsSafeToFold, /*NumInsns*/4,
12972 // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS), (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
12973 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
12974 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
12975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
12976 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
12977 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
12978 GIR_RootConstrainSelectedInstOperands,
12979 // GIR_Coverage, 2397,
12980 GIR_EraseRootFromParent_Done,
12981 // Label 788: @35590
12982 GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(35699), // Rule ID 12841 //
12983 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12984 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12985 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
12986 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
12987 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
12988 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
12989 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12990 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
12991 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
12992 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
12993 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
12994 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
12995 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
12996 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
12997 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
12998 // MIs[3] LHS
12999 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
13000 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
13001 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13002 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13003 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13004 GIM_CheckIsSafeToFold, /*NumInsns*/4,
13005 // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS), (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS)) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
13006 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
13007 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
13009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
13010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
13011 GIR_RootConstrainSelectedInstOperands,
13012 // GIR_Coverage, 12841,
13013 GIR_EraseRootFromParent_Done,
13014 // Label 789: @35699
13015 GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(35808), // Rule ID 12840 //
13016 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13017 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13018 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13019 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
13020 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13021 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
13022 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13023 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13024 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
13025 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
13026 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
13027 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
13028 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13029 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13030 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
13031 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
13032 // MIs[3] LHS
13033 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
13034 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
13035 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13036 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13037 GIM_CheckIsSafeToFold, /*NumInsns*/4,
13038 // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }))) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
13039 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
13040 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13041 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
13042 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
13043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
13044 GIR_RootConstrainSelectedInstOperands,
13045 // GIR_Coverage, 12840,
13046 GIR_EraseRootFromParent_Done,
13047 // Label 790: @35808
13048 GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(35917), // Rule ID 12842 //
13049 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13050 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13051 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13052 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
13053 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13054 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
13055 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13056 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13057 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
13058 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
13059 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
13060 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
13061 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13062 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13063 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
13064 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
13065 // MIs[3] LHS
13066 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
13067 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
13068 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13069 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13070 GIM_CheckIsSafeToFold, /*NumInsns*/4,
13071 // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }))) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
13072 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
13073 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
13075 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
13076 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
13077 GIR_RootConstrainSelectedInstOperands,
13078 // GIR_Coverage, 12842,
13079 GIR_EraseRootFromParent_Done,
13080 // Label 791: @35917
13081 GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(35958), // Rule ID 158 //
13082 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
13083 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
13084 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13085 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13086 GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_logical_imm64),
13087 // MIs[1] Operand 1
13088 // No operand predicates
13089 GIM_CheckIsSafeToFold, /*NumInsns*/1,
13090 // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_logical_imm64>><<X:logical_imm64_XFORM>>:$imm) => (ORRXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (logical_imm64_XFORM:{ *:[i64] } (imm:{ *:[i64] }):$imm))
13091 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORRXri),
13092 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
13093 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
13094 GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm64), // imm
13095 GIR_RootConstrainSelectedInstOperands,
13096 // GIR_Coverage, 158,
13097 GIR_EraseRootFromParent_Done,
13098 // Label 792: @35958
13099 GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(35991), // Rule ID 12497 //
13100 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
13101 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
13102 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
13103 // (or:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn) => (ORRXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
13104 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORRXrs),
13105 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
13106 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
13107 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
13108 GIR_RootConstrainSelectedInstOperands,
13109 // GIR_Coverage, 12497,
13110 GIR_EraseRootFromParent_Done,
13111 // Label 793: @35991
13112 GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(36024), // Rule ID 190 //
13113 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
13114 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
13115 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
13116 // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) => (ORRXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
13117 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORRXrs),
13118 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
13119 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
13120 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
13121 GIR_RootConstrainSelectedInstOperands,
13122 // GIR_Coverage, 190,
13123 GIR_EraseRootFromParent_Done,
13124 // Label 794: @36024
13125 GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(36091), // Rule ID 12780 //
13126 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13127 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13128 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13129 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
13130 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13131 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13132 // MIs[1] imm
13133 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13134 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13135 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
13136 // MIs[2] Operand 1
13137 // No operand predicates
13138 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13139 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
13140 GIM_CheckIsSafeToFold, /*NumInsns*/2,
13141 // (or:{ *:[i64] } (AArch64vashr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[i64] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (SSRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
13142 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAd),
13143 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13144 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
13145 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
13146 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
13147 GIR_RootConstrainSelectedInstOperands,
13148 // GIR_Coverage, 12780,
13149 GIR_EraseRootFromParent_Done,
13150 // Label 795: @36091
13151 GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(36158), // Rule ID 13178 //
13152 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13153 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13154 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13155 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
13156 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13157 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13158 // MIs[1] imm
13159 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13160 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13161 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
13162 // MIs[2] Operand 1
13163 // No operand predicates
13164 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13165 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
13166 GIM_CheckIsSafeToFold, /*NumInsns*/2,
13167 // (or:{ *:[v1i64] } (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[v1i64] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (SSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
13168 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAd),
13169 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13170 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
13171 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
13172 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
13173 GIR_RootConstrainSelectedInstOperands,
13174 // GIR_Coverage, 13178,
13175 GIR_EraseRootFromParent_Done,
13176 // Label 796: @36158
13177 GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(36225), // Rule ID 12783 //
13178 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13179 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13180 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13181 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
13182 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13183 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13184 // MIs[1] imm
13185 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13186 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13187 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
13188 // MIs[2] Operand 1
13189 // No operand predicates
13190 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13191 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
13192 GIM_CheckIsSafeToFold, /*NumInsns*/2,
13193 // (or:{ *:[i64] } (AArch64vlshr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[i64] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (USRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
13194 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAd),
13195 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13196 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
13197 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
13198 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
13199 GIR_RootConstrainSelectedInstOperands,
13200 // GIR_Coverage, 12783,
13201 GIR_EraseRootFromParent_Done,
13202 // Label 797: @36225
13203 GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(36292), // Rule ID 13181 //
13204 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13205 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13206 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13207 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
13208 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13209 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13210 // MIs[1] imm
13211 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13212 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13213 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
13214 // MIs[2] Operand 1
13215 // No operand predicates
13216 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13217 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
13218 GIM_CheckIsSafeToFold, /*NumInsns*/2,
13219 // (or:{ *:[v1i64] } (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[v1i64] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (USRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
13220 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAd),
13221 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13222 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
13223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
13224 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
13225 GIR_RootConstrainSelectedInstOperands,
13226 // GIR_Coverage, 13181,
13227 GIR_EraseRootFromParent_Done,
13228 // Label 798: @36292
13229 GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(36345), // Rule ID 12493 //
13230 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
13231 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13232 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13233 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13234 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
13235 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
13236 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
13237 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
13238 GIM_CheckIsSafeToFold, /*NumInsns*/1,
13239 // (or:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (ORNXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
13240 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
13241 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
13242 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
13243 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
13244 GIR_RootConstrainSelectedInstOperands,
13245 // GIR_Coverage, 12493,
13246 GIR_EraseRootFromParent_Done,
13247 // Label 799: @36345
13248 GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(36412), // Rule ID 2107 //
13249 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13250 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13251 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13252 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13253 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
13254 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13255 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13256 // MIs[1] imm
13257 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13258 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13259 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
13260 // MIs[2] Operand 1
13261 // No operand predicates
13262 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
13263 GIM_CheckIsSafeToFold, /*NumInsns*/2,
13264 // (or:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, (AArch64vashr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>> => (SSRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
13265 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAd),
13266 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13267 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
13268 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
13269 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
13270 GIR_RootConstrainSelectedInstOperands,
13271 // GIR_Coverage, 2107,
13272 GIR_EraseRootFromParent_Done,
13273 // Label 800: @36412
13274 GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(36479), // Rule ID 5882 //
13275 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13276 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13277 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13278 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13279 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
13280 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13281 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13282 // MIs[1] imm
13283 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13284 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13285 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
13286 // MIs[2] Operand 1
13287 // No operand predicates
13288 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
13289 GIM_CheckIsSafeToFold, /*NumInsns*/2,
13290 // (or:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>> => (SSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
13291 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAd),
13292 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13293 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
13294 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
13295 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
13296 GIR_RootConstrainSelectedInstOperands,
13297 // GIR_Coverage, 5882,
13298 GIR_EraseRootFromParent_Done,
13299 // Label 801: @36479
13300 GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(36546), // Rule ID 2116 //
13301 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13302 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13303 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13304 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13305 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
13306 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13307 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13308 // MIs[1] imm
13309 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13310 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13311 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
13312 // MIs[2] Operand 1
13313 // No operand predicates
13314 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
13315 GIM_CheckIsSafeToFold, /*NumInsns*/2,
13316 // (or:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, (AArch64vlshr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>> => (USRAd:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
13317 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAd),
13318 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13319 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
13320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
13321 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
13322 GIR_RootConstrainSelectedInstOperands,
13323 // GIR_Coverage, 2116,
13324 GIR_EraseRootFromParent_Done,
13325 // Label 802: @36546
13326 GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(36613), // Rule ID 5888 //
13327 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13328 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13329 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13330 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13331 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
13332 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13333 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13334 // MIs[1] imm
13335 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13336 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13337 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
13338 // MIs[2] Operand 1
13339 // No operand predicates
13340 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
13341 GIM_CheckIsSafeToFold, /*NumInsns*/2,
13342 // (or:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>> => (USRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
13343 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAd),
13344 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13345 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
13346 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
13347 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
13348 GIR_RootConstrainSelectedInstOperands,
13349 // GIR_Coverage, 5888,
13350 GIR_EraseRootFromParent_Done,
13351 // Label 803: @36613
13352 GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(36666), // Rule ID 184 //
13353 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
13354 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
13355 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13356 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13357 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13358 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
13359 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
13360 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
13361 GIM_CheckIsSafeToFold, /*NumInsns*/1,
13362 // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] })) => (ORNXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
13363 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
13364 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
13365 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
13366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
13367 GIR_RootConstrainSelectedInstOperands,
13368 // GIR_Coverage, 184,
13369 GIR_EraseRootFromParent_Done,
13370 // Label 804: @36666
13371 GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(36730), // Rule ID 13142 //
13372 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13373 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13374 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13375 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13376 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13377 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
13378 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13379 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13380 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13381 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
13382 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13383 GIM_CheckIsSafeToFold, /*NumInsns*/2,
13384 // (or:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$LHS) => (ORNv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
13385 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
13386 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
13387 GIR_RootToRootCopy, /*OpIdx*/2, // LHS
13388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
13389 GIR_RootConstrainSelectedInstOperands,
13390 // GIR_Coverage, 13142,
13391 GIR_EraseRootFromParent_Done,
13392 // Label 805: @36730
13393 GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(36794), // Rule ID 4704 //
13394 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13395 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13396 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13397 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13398 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13399 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
13400 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
13401 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13402 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13403 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13404 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
13405 GIM_CheckIsSafeToFold, /*NumInsns*/2,
13406 // (or:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] })) => (ORNv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
13407 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
13408 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
13409 GIR_RootToRootCopy, /*OpIdx*/1, // LHS
13410 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
13411 GIR_RootConstrainSelectedInstOperands,
13412 // GIR_Coverage, 4704,
13413 GIR_EraseRootFromParent_Done,
13414 // Label 806: @36794
13415 GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(36818), // Rule ID 188 //
13416 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
13417 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
13418 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
13419 // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ORRXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
13420 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRXrr),
13421 GIR_RootConstrainSelectedInstOperands,
13422 // GIR_Coverage, 188,
13423 GIR_Done,
13424 // Label 807: @36818
13425 GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(36845), // Rule ID 4710 //
13426 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13427 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13428 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13429 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13430 // (or:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) => (ORRv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
13431 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv8i8),
13432 GIR_RootConstrainSelectedInstOperands,
13433 // GIR_Coverage, 4710,
13434 GIR_Done,
13435 // Label 808: @36845
13436 GIM_Reject,
13437 // Label 779: @36846
13438 GIM_Reject,
13439 // Label 753: @36847
13440 GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(38154),
13441 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
13442 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
13443 GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(36967), // Rule ID 12837 //
13444 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13445 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13446 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13447 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
13448 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
13449 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
13450 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13451 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
13452 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
13453 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
13454 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13455 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13456 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13457 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
13458 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13459 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
13460 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
13461 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
13462 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13463 // MIs[4] LHS
13464 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
13465 GIM_CheckIsSafeToFold, /*NumInsns*/4,
13466 // (or:{ *:[v2i32] } (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
13467 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
13468 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13469 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
13470 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
13471 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
13472 GIR_RootConstrainSelectedInstOperands,
13473 // GIR_Coverage, 12837,
13474 GIR_EraseRootFromParent_Done,
13475 // Label 810: @36967
13476 GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(37076), // Rule ID 12836 //
13477 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13478 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13479 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13480 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
13481 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
13482 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
13483 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13484 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
13485 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
13486 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
13487 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13488 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13489 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13490 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
13491 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13492 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
13493 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
13494 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s32,
13495 // MIs[4] LHS
13496 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13497 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13498 GIM_CheckIsSafeToFold, /*NumInsns*/4,
13499 // (or:{ *:[v2i32] } (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
13500 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
13501 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13502 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
13503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
13504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
13505 GIR_RootConstrainSelectedInstOperands,
13506 // GIR_Coverage, 12836,
13507 GIR_EraseRootFromParent_Done,
13508 // Label 811: @37076
13509 GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(37185), // Rule ID 12839 //
13510 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13511 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13512 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13513 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
13514 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
13515 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
13516 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13517 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13518 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
13519 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
13520 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
13521 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13522 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13523 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13524 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
13525 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
13526 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
13527 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
13528 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13529 // MIs[4] LHS
13530 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
13531 GIM_CheckIsSafeToFold, /*NumInsns*/4,
13532 // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] })), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
13533 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
13534 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
13536 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
13537 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
13538 GIR_RootConstrainSelectedInstOperands,
13539 // GIR_Coverage, 12839,
13540 GIR_EraseRootFromParent_Done,
13541 // Label 812: @37185
13542 GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(37294), // Rule ID 12838 //
13543 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13544 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13545 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13546 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
13547 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
13548 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
13549 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13550 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13551 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
13552 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
13553 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
13554 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13555 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13556 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13557 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
13558 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
13559 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
13560 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s32,
13561 // MIs[4] LHS
13562 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13563 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13564 GIM_CheckIsSafeToFold, /*NumInsns*/4,
13565 // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] })), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
13566 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
13567 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
13569 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
13570 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
13571 GIR_RootConstrainSelectedInstOperands,
13572 // GIR_Coverage, 12838,
13573 GIR_EraseRootFromParent_Done,
13574 // Label 813: @37294
13575 GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(37403), // Rule ID 2396 //
13576 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13577 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13578 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13579 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
13580 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
13581 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
13582 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13583 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13584 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
13585 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
13586 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
13587 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
13588 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
13589 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
13590 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32,
13591 // MIs[3] LHS
13592 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
13593 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
13594 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13595 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13596 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13597 GIM_CheckIsSafeToFold, /*NumInsns*/4,
13598 // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS), (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
13599 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
13600 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
13602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
13603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
13604 GIR_RootConstrainSelectedInstOperands,
13605 // GIR_Coverage, 2396,
13606 GIR_EraseRootFromParent_Done,
13607 // Label 814: @37403
13608 GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(37512), // Rule ID 12834 //
13609 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13610 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13611 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13612 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
13613 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
13614 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
13615 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13616 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13617 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
13618 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
13619 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
13620 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
13621 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
13622 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
13623 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32,
13624 // MIs[3] LHS
13625 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
13626 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
13627 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13628 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13629 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13630 GIM_CheckIsSafeToFold, /*NumInsns*/4,
13631 // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS), (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS)) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
13632 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
13633 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13634 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
13635 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
13636 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
13637 GIR_RootConstrainSelectedInstOperands,
13638 // GIR_Coverage, 12834,
13639 GIR_EraseRootFromParent_Done,
13640 // Label 815: @37512
13641 GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(37621), // Rule ID 12833 //
13642 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13643 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13644 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13645 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
13646 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
13647 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
13648 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13649 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13650 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
13651 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
13652 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
13653 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
13654 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13655 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13656 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
13657 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32,
13658 // MIs[3] LHS
13659 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
13660 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
13661 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13662 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13663 GIM_CheckIsSafeToFold, /*NumInsns*/4,
13664 // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }))) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
13665 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
13666 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13667 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
13668 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
13669 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
13670 GIR_RootConstrainSelectedInstOperands,
13671 // GIR_Coverage, 12833,
13672 GIR_EraseRootFromParent_Done,
13673 // Label 816: @37621
13674 GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(37730), // Rule ID 12835 //
13675 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13676 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13677 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13678 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
13679 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
13680 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
13681 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13682 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13683 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
13684 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
13685 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
13686 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
13687 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13688 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13689 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
13690 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32,
13691 // MIs[3] LHS
13692 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
13693 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
13694 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13695 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
13696 GIM_CheckIsSafeToFold, /*NumInsns*/4,
13697 // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }))) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
13698 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
13699 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13700 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
13701 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
13702 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
13703 GIR_RootConstrainSelectedInstOperands,
13704 // GIR_Coverage, 12835,
13705 GIR_EraseRootFromParent_Done,
13706 // Label 817: @37730
13707 GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(37797), // Rule ID 12800 //
13708 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13709 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13710 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13711 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
13712 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
13713 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13714 // MIs[1] imm
13715 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13716 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13717 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
13718 // MIs[2] Operand 1
13719 // No operand predicates
13720 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13721 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
13722 GIM_CheckIsSafeToFold, /*NumInsns*/2,
13723 // (or:{ *:[v2i32] } (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V64:{ *:[v2i32] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (SSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
13724 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i32_shift),
13725 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13726 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
13727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
13728 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
13729 GIR_RootConstrainSelectedInstOperands,
13730 // GIR_Coverage, 12800,
13731 GIR_EraseRootFromParent_Done,
13732 // Label 818: @37797
13733 GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(37864), // Rule ID 12821 //
13734 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13735 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13736 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13737 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
13738 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
13739 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13740 // MIs[1] imm
13741 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13742 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13743 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
13744 // MIs[2] Operand 1
13745 // No operand predicates
13746 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13747 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
13748 GIM_CheckIsSafeToFold, /*NumInsns*/2,
13749 // (or:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V64:{ *:[v2i32] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (USRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
13750 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i32_shift),
13751 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13752 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
13753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
13754 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
13755 GIR_RootConstrainSelectedInstOperands,
13756 // GIR_Coverage, 12821,
13757 GIR_EraseRootFromParent_Done,
13758 // Label 819: @37864
13759 GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(37931), // Rule ID 2224 //
13760 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13761 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13762 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13763 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13764 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
13765 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
13766 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13767 // MIs[1] imm
13768 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13769 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13770 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
13771 // MIs[2] Operand 1
13772 // No operand predicates
13773 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
13774 GIM_CheckIsSafeToFold, /*NumInsns*/2,
13775 // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>> => (SSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
13776 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i32_shift),
13777 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13778 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
13779 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
13780 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
13781 GIR_RootConstrainSelectedInstOperands,
13782 // GIR_Coverage, 2224,
13783 GIR_EraseRootFromParent_Done,
13784 // Label 820: @37931
13785 GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(37998), // Rule ID 2283 //
13786 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13787 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13788 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13789 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13790 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
13791 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
13792 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13793 // MIs[1] imm
13794 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13795 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13796 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
13797 // MIs[2] Operand 1
13798 // No operand predicates
13799 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
13800 GIM_CheckIsSafeToFold, /*NumInsns*/2,
13801 // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>> => (USRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
13802 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i32_shift),
13803 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13804 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
13805 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
13806 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
13807 GIR_RootConstrainSelectedInstOperands,
13808 // GIR_Coverage, 2283,
13809 GIR_EraseRootFromParent_Done,
13810 // Label 821: @37998
13811 GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(38062), // Rule ID 13141 //
13812 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13813 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13814 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13815 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13816 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
13817 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
13818 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13819 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13820 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13821 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
13822 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13823 GIM_CheckIsSafeToFold, /*NumInsns*/2,
13824 // (or:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$LHS) => (ORNv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
13825 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
13826 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
13827 GIR_RootToRootCopy, /*OpIdx*/2, // LHS
13828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
13829 GIR_RootConstrainSelectedInstOperands,
13830 // GIR_Coverage, 13141,
13831 GIR_EraseRootFromParent_Done,
13832 // Label 822: @38062
13833 GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(38126), // Rule ID 4703 //
13834 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13835 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13836 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13837 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
13838 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
13839 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
13840 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
13841 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13842 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13843 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13844 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
13845 GIM_CheckIsSafeToFold, /*NumInsns*/2,
13846 // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] })) => (ORNv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
13847 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
13848 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
13849 GIR_RootToRootCopy, /*OpIdx*/1, // LHS
13850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
13851 GIR_RootConstrainSelectedInstOperands,
13852 // GIR_Coverage, 4703,
13853 GIR_EraseRootFromParent_Done,
13854 // Label 823: @38126
13855 GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(38153), // Rule ID 4709 //
13856 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13857 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13858 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13859 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
13860 // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (ORRv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
13861 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv8i8),
13862 GIR_RootConstrainSelectedInstOperands,
13863 // GIR_Coverage, 4709,
13864 GIR_Done,
13865 // Label 824: @38153
13866 GIM_Reject,
13867 // Label 809: @38154
13868 GIM_Reject,
13869 // Label 754: @38155
13870 GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(39462),
13871 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13872 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
13873 GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(38275), // Rule ID 12865 //
13874 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13875 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
13876 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13877 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
13878 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
13879 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
13880 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13881 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
13882 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
13883 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
13884 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
13885 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13886 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13887 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
13888 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
13889 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
13890 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
13891 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64,
13892 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
13893 // MIs[4] LHS
13894 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
13895 GIM_CheckIsSafeToFold, /*NumInsns*/4,
13896 // (or:{ *:[v2i64] } (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
13897 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
13898 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13899 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
13900 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
13901 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
13902 GIR_RootConstrainSelectedInstOperands,
13903 // GIR_Coverage, 12865,
13904 GIR_EraseRootFromParent_Done,
13905 // Label 826: @38275
13906 GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(38384), // Rule ID 12864 //
13907 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13908 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
13909 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13910 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
13911 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
13912 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
13913 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
13914 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
13915 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
13916 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
13917 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
13918 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13919 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13920 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
13921 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
13922 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
13923 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
13924 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s64,
13925 // MIs[4] LHS
13926 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13927 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
13928 GIM_CheckIsSafeToFold, /*NumInsns*/4,
13929 // (or:{ *:[v2i64] } (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
13930 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
13931 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13932 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
13933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
13934 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
13935 GIR_RootConstrainSelectedInstOperands,
13936 // GIR_Coverage, 12864,
13937 GIR_EraseRootFromParent_Done,
13938 // Label 827: @38384
13939 GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(38493), // Rule ID 12867 //
13940 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13941 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
13942 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13943 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
13944 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
13945 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
13946 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
13947 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13948 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
13949 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
13950 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
13951 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
13952 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13953 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13954 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
13955 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
13956 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
13957 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64,
13958 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
13959 // MIs[4] LHS
13960 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
13961 GIM_CheckIsSafeToFold, /*NumInsns*/4,
13962 // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] })), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
13963 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
13964 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
13966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
13967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
13968 GIR_RootConstrainSelectedInstOperands,
13969 // GIR_Coverage, 12867,
13970 GIR_EraseRootFromParent_Done,
13971 // Label 828: @38493
13972 GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(38602), // Rule ID 12866 //
13973 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13974 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
13975 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13976 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
13977 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
13978 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
13979 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
13980 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13981 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
13982 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
13983 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
13984 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
13985 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
13986 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
13987 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
13988 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
13989 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
13990 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s64,
13991 // MIs[4] LHS
13992 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
13993 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
13994 GIM_CheckIsSafeToFold, /*NumInsns*/4,
13995 // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] })), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
13996 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
13997 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13998 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
13999 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
14000 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
14001 GIR_RootConstrainSelectedInstOperands,
14002 // GIR_Coverage, 12866,
14003 GIR_EraseRootFromParent_Done,
14004 // Label 829: @38602
14005 GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(38711), // Rule ID 2400 //
14006 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14007 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14008 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14009 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14010 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
14011 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
14012 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14013 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14014 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
14015 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
14016 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
14017 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
14018 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14019 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
14020 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
14021 // MIs[3] LHS
14022 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
14023 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
14024 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14025 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14026 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14027 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14028 // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS), (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
14029 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
14030 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
14032 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
14033 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
14034 GIR_RootConstrainSelectedInstOperands,
14035 // GIR_Coverage, 2400,
14036 GIR_EraseRootFromParent_Done,
14037 // Label 830: @38711
14038 GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(38820), // Rule ID 12862 //
14039 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14040 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14041 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14042 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14043 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
14044 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
14045 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14046 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14047 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
14048 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
14049 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
14050 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
14051 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14052 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
14053 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
14054 // MIs[3] LHS
14055 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
14056 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
14057 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14058 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14059 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14060 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14061 // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS), (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS)) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
14062 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
14063 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14064 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
14065 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
14066 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
14067 GIR_RootConstrainSelectedInstOperands,
14068 // GIR_Coverage, 12862,
14069 GIR_EraseRootFromParent_Done,
14070 // Label 831: @38820
14071 GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(38929), // Rule ID 12861 //
14072 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14073 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14074 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14075 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14076 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
14077 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
14078 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14079 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14080 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
14081 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
14082 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
14083 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
14084 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14085 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14086 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
14087 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
14088 // MIs[3] LHS
14089 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
14090 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
14091 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14092 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14093 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14094 // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }))) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
14095 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
14096 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14097 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
14098 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
14099 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
14100 GIR_RootConstrainSelectedInstOperands,
14101 // GIR_Coverage, 12861,
14102 GIR_EraseRootFromParent_Done,
14103 // Label 832: @38929
14104 GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(39038), // Rule ID 12863 //
14105 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14106 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14107 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14108 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14109 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
14110 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
14111 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14112 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14113 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
14114 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
14115 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
14116 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
14117 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14118 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14119 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
14120 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
14121 // MIs[3] LHS
14122 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
14123 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
14124 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14125 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14126 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14127 // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }))) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
14128 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
14129 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14130 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
14131 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
14132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
14133 GIR_RootConstrainSelectedInstOperands,
14134 // GIR_Coverage, 12863,
14135 GIR_EraseRootFromParent_Done,
14136 // Label 833: @39038
14137 GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(39105), // Rule ID 12804 //
14138 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14139 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14140 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14141 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
14142 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
14143 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14144 // MIs[1] imm
14145 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14146 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14147 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
14148 // MIs[2] Operand 1
14149 // No operand predicates
14150 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14151 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
14152 GIM_CheckIsSafeToFold, /*NumInsns*/2,
14153 // (or:{ *:[v2i64] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), V128:{ *:[v2i64] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (SSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
14154 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i64_shift),
14155 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14156 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
14157 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
14158 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
14159 GIR_RootConstrainSelectedInstOperands,
14160 // GIR_Coverage, 12804,
14161 GIR_EraseRootFromParent_Done,
14162 // Label 834: @39105
14163 GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(39172), // Rule ID 12825 //
14164 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14165 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14166 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14167 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
14168 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
14169 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14170 // MIs[1] imm
14171 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14172 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14173 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
14174 // MIs[2] Operand 1
14175 // No operand predicates
14176 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14177 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
14178 GIM_CheckIsSafeToFold, /*NumInsns*/2,
14179 // (or:{ *:[v2i64] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), V128:{ *:[v2i64] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (USRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
14180 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i64_shift),
14181 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14182 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
14183 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
14184 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
14185 GIR_RootConstrainSelectedInstOperands,
14186 // GIR_Coverage, 12825,
14187 GIR_EraseRootFromParent_Done,
14188 // Label 835: @39172
14189 GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(39239), // Rule ID 2228 //
14190 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14191 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14192 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14193 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14194 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
14195 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
14196 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14197 // MIs[1] imm
14198 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14199 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14200 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
14201 // MIs[2] Operand 1
14202 // No operand predicates
14203 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
14204 GIM_CheckIsSafeToFold, /*NumInsns*/2,
14205 // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>> => (SSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
14206 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i64_shift),
14207 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14208 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
14209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
14210 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
14211 GIR_RootConstrainSelectedInstOperands,
14212 // GIR_Coverage, 2228,
14213 GIR_EraseRootFromParent_Done,
14214 // Label 836: @39239
14215 GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(39306), // Rule ID 2287 //
14216 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14217 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14218 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14219 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14220 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
14221 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
14222 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14223 // MIs[1] imm
14224 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14225 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14226 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
14227 // MIs[2] Operand 1
14228 // No operand predicates
14229 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
14230 GIM_CheckIsSafeToFold, /*NumInsns*/2,
14231 // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>> => (USRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
14232 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i64_shift),
14233 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14234 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
14235 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
14236 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
14237 GIR_RootConstrainSelectedInstOperands,
14238 // GIR_Coverage, 2287,
14239 GIR_EraseRootFromParent_Done,
14240 // Label 837: @39306
14241 GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(39370), // Rule ID 13145 //
14242 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14243 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14244 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14245 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14246 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
14247 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
14248 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14249 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14250 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14251 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
14252 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14253 GIM_CheckIsSafeToFold, /*NumInsns*/2,
14254 // (or:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$LHS) => (ORNv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
14255 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
14256 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
14257 GIR_RootToRootCopy, /*OpIdx*/2, // LHS
14258 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
14259 GIR_RootConstrainSelectedInstOperands,
14260 // GIR_Coverage, 13145,
14261 GIR_EraseRootFromParent_Done,
14262 // Label 838: @39370
14263 GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(39434), // Rule ID 4707 //
14264 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14265 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14266 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14267 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14268 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14269 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
14270 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
14271 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14272 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14273 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14274 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
14275 GIM_CheckIsSafeToFold, /*NumInsns*/2,
14276 // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] })) => (ORNv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
14277 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
14278 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
14279 GIR_RootToRootCopy, /*OpIdx*/1, // LHS
14280 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
14281 GIR_RootConstrainSelectedInstOperands,
14282 // GIR_Coverage, 4707,
14283 GIR_EraseRootFromParent_Done,
14284 // Label 839: @39434
14285 GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(39461), // Rule ID 4713 //
14286 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14287 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14288 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14289 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14290 // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (ORRv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
14291 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv16i8),
14292 GIR_RootConstrainSelectedInstOperands,
14293 // GIR_Coverage, 4713,
14294 GIR_Done,
14295 // Label 840: @39461
14296 GIM_Reject,
14297 // Label 825: @39462
14298 GIM_Reject,
14299 // Label 755: @39463
14300 GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(40770),
14301 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
14302 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
14303 GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(39583), // Rule ID 12830 //
14304 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14305 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14306 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14307 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14308 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
14309 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
14310 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14311 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14312 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
14313 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
14314 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14315 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14316 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14317 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14318 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14319 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
14320 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
14321 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
14322 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14323 // MIs[4] LHS
14324 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
14325 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14326 // (or:{ *:[v4i16] } (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
14327 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
14328 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
14330 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
14331 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
14332 GIR_RootConstrainSelectedInstOperands,
14333 // GIR_Coverage, 12830,
14334 GIR_EraseRootFromParent_Done,
14335 // Label 842: @39583
14336 GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(39692), // Rule ID 12829 //
14337 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14338 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14339 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14340 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14341 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
14342 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
14343 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14344 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14345 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
14346 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
14347 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14348 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14349 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14350 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14351 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14352 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
14353 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
14354 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s16,
14355 // MIs[4] LHS
14356 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
14357 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14358 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14359 // (or:{ *:[v4i16] } (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
14360 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
14361 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14362 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
14363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
14364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
14365 GIR_RootConstrainSelectedInstOperands,
14366 // GIR_Coverage, 12829,
14367 GIR_EraseRootFromParent_Done,
14368 // Label 843: @39692
14369 GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(39801), // Rule ID 12832 //
14370 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14371 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14372 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14373 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14374 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
14375 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
14376 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14377 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14378 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14379 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
14380 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
14381 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14382 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14383 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14384 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14385 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
14386 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
14387 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
14388 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14389 // MIs[4] LHS
14390 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
14391 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14392 // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] })), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
14393 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
14394 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
14396 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
14397 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
14398 GIR_RootConstrainSelectedInstOperands,
14399 // GIR_Coverage, 12832,
14400 GIR_EraseRootFromParent_Done,
14401 // Label 844: @39801
14402 GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(39910), // Rule ID 12831 //
14403 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14404 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14405 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14406 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14407 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
14408 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
14409 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14410 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14411 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14412 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
14413 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
14414 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14415 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14416 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14417 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14418 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
14419 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
14420 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s16,
14421 // MIs[4] LHS
14422 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
14423 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14424 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14425 // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] })), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
14426 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
14427 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14428 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
14429 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
14430 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
14431 GIR_RootConstrainSelectedInstOperands,
14432 // GIR_Coverage, 12831,
14433 GIR_EraseRootFromParent_Done,
14434 // Label 845: @39910
14435 GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(40019), // Rule ID 2395 //
14436 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14437 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14438 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14439 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14440 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
14441 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
14442 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14443 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14444 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
14445 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
14446 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
14447 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
14448 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14449 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
14450 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16,
14451 // MIs[3] LHS
14452 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
14453 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
14454 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14455 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14456 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14457 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14458 // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS), (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
14459 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
14460 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14461 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
14462 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
14463 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
14464 GIR_RootConstrainSelectedInstOperands,
14465 // GIR_Coverage, 2395,
14466 GIR_EraseRootFromParent_Done,
14467 // Label 846: @40019
14468 GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(40128), // Rule ID 12827 //
14469 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14470 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14471 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14472 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14473 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
14474 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
14475 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14476 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14477 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
14478 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
14479 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
14480 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
14481 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14482 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
14483 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16,
14484 // MIs[3] LHS
14485 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
14486 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
14487 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14488 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14489 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14490 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14491 // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS), (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS)) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
14492 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
14493 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14494 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
14495 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
14496 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
14497 GIR_RootConstrainSelectedInstOperands,
14498 // GIR_Coverage, 12827,
14499 GIR_EraseRootFromParent_Done,
14500 // Label 847: @40128
14501 GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(40237), // Rule ID 12826 //
14502 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14503 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14504 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14505 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14506 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
14507 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
14508 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14509 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14510 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
14511 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
14512 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
14513 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
14514 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14515 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14516 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
14517 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16,
14518 // MIs[3] LHS
14519 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
14520 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
14521 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14522 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14523 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14524 // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }))) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
14525 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
14526 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
14528 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
14529 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
14530 GIR_RootConstrainSelectedInstOperands,
14531 // GIR_Coverage, 12826,
14532 GIR_EraseRootFromParent_Done,
14533 // Label 848: @40237
14534 GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(40346), // Rule ID 12828 //
14535 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14536 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14537 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14538 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14539 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
14540 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
14541 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14542 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14543 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
14544 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
14545 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
14546 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
14547 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14548 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14549 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
14550 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16,
14551 // MIs[3] LHS
14552 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
14553 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
14554 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14555 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14556 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14557 // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }))) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
14558 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
14559 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14560 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
14561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
14562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
14563 GIR_RootConstrainSelectedInstOperands,
14564 // GIR_Coverage, 12828,
14565 GIR_EraseRootFromParent_Done,
14566 // Label 849: @40346
14567 GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(40413), // Rule ID 12796 //
14568 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14569 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14570 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14571 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
14572 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
14573 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14574 // MIs[1] imm
14575 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14576 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14577 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
14578 // MIs[2] Operand 1
14579 // No operand predicates
14580 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14581 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
14582 GIM_CheckIsSafeToFold, /*NumInsns*/2,
14583 // (or:{ *:[v4i16] } (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V64:{ *:[v4i16] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (SSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
14584 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i16_shift),
14585 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14586 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
14587 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
14588 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
14589 GIR_RootConstrainSelectedInstOperands,
14590 // GIR_Coverage, 12796,
14591 GIR_EraseRootFromParent_Done,
14592 // Label 850: @40413
14593 GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(40480), // Rule ID 12817 //
14594 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14595 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14596 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14597 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
14598 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
14599 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14600 // MIs[1] imm
14601 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14602 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14603 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
14604 // MIs[2] Operand 1
14605 // No operand predicates
14606 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14607 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
14608 GIM_CheckIsSafeToFold, /*NumInsns*/2,
14609 // (or:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V64:{ *:[v4i16] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (USRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
14610 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i16_shift),
14611 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14612 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
14613 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
14614 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
14615 GIR_RootConstrainSelectedInstOperands,
14616 // GIR_Coverage, 12817,
14617 GIR_EraseRootFromParent_Done,
14618 // Label 851: @40480
14619 GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(40547), // Rule ID 2220 //
14620 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14621 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14622 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14623 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14624 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
14625 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
14626 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14627 // MIs[1] imm
14628 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14629 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14630 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
14631 // MIs[2] Operand 1
14632 // No operand predicates
14633 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
14634 GIM_CheckIsSafeToFold, /*NumInsns*/2,
14635 // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>> => (SSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
14636 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i16_shift),
14637 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14638 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
14639 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
14640 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
14641 GIR_RootConstrainSelectedInstOperands,
14642 // GIR_Coverage, 2220,
14643 GIR_EraseRootFromParent_Done,
14644 // Label 852: @40547
14645 GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(40614), // Rule ID 2279 //
14646 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14647 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14648 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14649 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14650 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
14651 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
14652 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14653 // MIs[1] imm
14654 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14655 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14656 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
14657 // MIs[2] Operand 1
14658 // No operand predicates
14659 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
14660 GIM_CheckIsSafeToFold, /*NumInsns*/2,
14661 // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>> => (USRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
14662 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i16_shift),
14663 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14664 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
14665 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
14666 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
14667 GIR_RootConstrainSelectedInstOperands,
14668 // GIR_Coverage, 2279,
14669 GIR_EraseRootFromParent_Done,
14670 // Label 853: @40614
14671 GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(40678), // Rule ID 13140 //
14672 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14673 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14674 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14675 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14676 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
14677 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
14678 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14679 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14680 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14681 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
14682 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14683 GIM_CheckIsSafeToFold, /*NumInsns*/2,
14684 // (or:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$LHS) => (ORNv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
14685 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
14686 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
14687 GIR_RootToRootCopy, /*OpIdx*/2, // LHS
14688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
14689 GIR_RootConstrainSelectedInstOperands,
14690 // GIR_Coverage, 13140,
14691 GIR_EraseRootFromParent_Done,
14692 // Label 854: @40678
14693 GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(40742), // Rule ID 4702 //
14694 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14695 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14696 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14697 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14698 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
14699 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
14700 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
14701 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14702 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14703 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14704 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
14705 GIM_CheckIsSafeToFold, /*NumInsns*/2,
14706 // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] })) => (ORNv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
14707 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
14708 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
14709 GIR_RootToRootCopy, /*OpIdx*/1, // LHS
14710 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
14711 GIR_RootConstrainSelectedInstOperands,
14712 // GIR_Coverage, 4702,
14713 GIR_EraseRootFromParent_Done,
14714 // Label 855: @40742
14715 GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(40769), // Rule ID 4708 //
14716 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14717 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14718 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14719 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
14720 // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (ORRv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
14721 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv8i8),
14722 GIR_RootConstrainSelectedInstOperands,
14723 // GIR_Coverage, 4708,
14724 GIR_Done,
14725 // Label 856: @40769
14726 GIM_Reject,
14727 // Label 841: @40770
14728 GIM_Reject,
14729 // Label 756: @40771
14730 GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(42078),
14731 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14732 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
14733 GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(40891), // Rule ID 12858 //
14734 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14735 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14736 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14737 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14738 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14739 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14740 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14741 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14742 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14743 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14744 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14745 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14746 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14747 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14748 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14749 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
14750 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
14751 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
14752 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14753 // MIs[4] LHS
14754 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
14755 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14756 // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
14757 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
14758 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14759 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
14760 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
14761 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
14762 GIR_RootConstrainSelectedInstOperands,
14763 // GIR_Coverage, 12858,
14764 GIR_EraseRootFromParent_Done,
14765 // Label 858: @40891
14766 GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(41000), // Rule ID 12857 //
14767 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14768 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14769 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14770 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14771 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14772 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14773 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14774 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14775 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14776 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14777 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14778 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14779 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14780 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14781 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14782 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
14783 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
14784 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
14785 // MIs[4] LHS
14786 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
14787 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14788 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14789 // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
14790 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
14791 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14792 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
14793 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
14794 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
14795 GIR_RootConstrainSelectedInstOperands,
14796 // GIR_Coverage, 12857,
14797 GIR_EraseRootFromParent_Done,
14798 // Label 859: @41000
14799 GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(41109), // Rule ID 12860 //
14800 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14801 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14802 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14803 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14804 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14805 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14806 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14807 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14808 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14809 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14810 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14811 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14812 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14813 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14814 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14815 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
14816 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
14817 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
14818 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14819 // MIs[4] LHS
14820 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
14821 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14822 // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] })), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
14823 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
14824 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14825 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
14826 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
14827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
14828 GIR_RootConstrainSelectedInstOperands,
14829 // GIR_Coverage, 12860,
14830 GIR_EraseRootFromParent_Done,
14831 // Label 860: @41109
14832 GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(41218), // Rule ID 12859 //
14833 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14834 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14835 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14836 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14837 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14838 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14839 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14840 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14841 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
14842 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14843 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14844 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14845 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14846 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14847 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
14848 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
14849 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
14850 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
14851 // MIs[4] LHS
14852 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
14853 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14854 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14855 // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] })), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
14856 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
14857 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
14859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
14860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
14861 GIR_RootConstrainSelectedInstOperands,
14862 // GIR_Coverage, 12859,
14863 GIR_EraseRootFromParent_Done,
14864 // Label 861: @41218
14865 GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(41327), // Rule ID 2399 //
14866 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14867 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14868 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14869 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14870 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14871 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14872 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14873 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14874 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
14875 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
14876 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14877 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14878 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14879 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
14880 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
14881 // MIs[3] LHS
14882 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
14883 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
14884 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14885 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14886 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14887 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14888 // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS), (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
14889 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
14890 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14891 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
14892 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
14893 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
14894 GIR_RootConstrainSelectedInstOperands,
14895 // GIR_Coverage, 2399,
14896 GIR_EraseRootFromParent_Done,
14897 // Label 862: @41327
14898 GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(41436), // Rule ID 12855 //
14899 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14900 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14901 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14902 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14903 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14904 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14905 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14906 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14907 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
14908 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
14909 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14910 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14911 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14912 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
14913 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
14914 // MIs[3] LHS
14915 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
14916 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
14917 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14918 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14919 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14920 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14921 // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS), (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS)) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
14922 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
14923 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14924 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
14925 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
14926 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
14927 GIR_RootConstrainSelectedInstOperands,
14928 // GIR_Coverage, 12855,
14929 GIR_EraseRootFromParent_Done,
14930 // Label 863: @41436
14931 GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(41545), // Rule ID 12854 //
14932 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14933 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14934 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14935 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14936 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14937 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14938 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14939 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14940 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
14941 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
14942 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14943 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14944 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14945 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14946 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
14947 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
14948 // MIs[3] LHS
14949 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
14950 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
14951 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14952 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14953 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14954 // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }))) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
14955 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
14956 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14957 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
14958 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
14959 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
14960 GIR_RootConstrainSelectedInstOperands,
14961 // GIR_Coverage, 12854,
14962 GIR_EraseRootFromParent_Done,
14963 // Label 864: @41545
14964 GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(41654), // Rule ID 12856 //
14965 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14966 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14967 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14968 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14969 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14970 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14971 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14972 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14973 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
14974 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
14975 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
14976 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
14977 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
14978 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
14979 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
14980 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
14981 // MIs[3] LHS
14982 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
14983 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
14984 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
14985 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
14986 GIM_CheckIsSafeToFold, /*NumInsns*/4,
14987 // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }))) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
14988 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
14989 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
14991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
14992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
14993 GIR_RootConstrainSelectedInstOperands,
14994 // GIR_Coverage, 12856,
14995 GIR_EraseRootFromParent_Done,
14996 // Label 865: @41654
14997 GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(41721), // Rule ID 12802 //
14998 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
14999 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15000 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15001 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
15002 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15003 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15004 // MIs[1] imm
15005 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15006 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15007 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
15008 // MIs[2] Operand 1
15009 // No operand predicates
15010 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15011 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
15012 GIM_CheckIsSafeToFold, /*NumInsns*/2,
15013 // (or:{ *:[v4i32] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V128:{ *:[v4i32] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (SSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
15014 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i32_shift),
15015 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15016 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
15017 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
15018 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
15019 GIR_RootConstrainSelectedInstOperands,
15020 // GIR_Coverage, 12802,
15021 GIR_EraseRootFromParent_Done,
15022 // Label 866: @41721
15023 GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(41788), // Rule ID 12823 //
15024 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15025 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15026 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15027 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
15028 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15029 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15030 // MIs[1] imm
15031 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15032 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15033 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
15034 // MIs[2] Operand 1
15035 // No operand predicates
15036 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15037 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
15038 GIM_CheckIsSafeToFold, /*NumInsns*/2,
15039 // (or:{ *:[v4i32] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V128:{ *:[v4i32] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (USRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
15040 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i32_shift),
15041 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15042 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
15043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
15044 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
15045 GIR_RootConstrainSelectedInstOperands,
15046 // GIR_Coverage, 12823,
15047 GIR_EraseRootFromParent_Done,
15048 // Label 867: @41788
15049 GIM_Try, /*On fail goto*//*Label 868*/ GIMT_Encode4(41855), // Rule ID 2226 //
15050 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15051 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15052 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15053 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15054 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
15055 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15056 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15057 // MIs[1] imm
15058 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15059 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15060 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
15061 // MIs[2] Operand 1
15062 // No operand predicates
15063 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
15064 GIM_CheckIsSafeToFold, /*NumInsns*/2,
15065 // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>> => (SSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
15066 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i32_shift),
15067 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15068 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
15069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
15070 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
15071 GIR_RootConstrainSelectedInstOperands,
15072 // GIR_Coverage, 2226,
15073 GIR_EraseRootFromParent_Done,
15074 // Label 868: @41855
15075 GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(41922), // Rule ID 2285 //
15076 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15077 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15078 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15079 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15080 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
15081 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15082 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15083 // MIs[1] imm
15084 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15085 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15086 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
15087 // MIs[2] Operand 1
15088 // No operand predicates
15089 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
15090 GIM_CheckIsSafeToFold, /*NumInsns*/2,
15091 // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>> => (USRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
15092 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i32_shift),
15093 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15094 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
15095 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
15096 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
15097 GIR_RootConstrainSelectedInstOperands,
15098 // GIR_Coverage, 2285,
15099 GIR_EraseRootFromParent_Done,
15100 // Label 869: @41922
15101 GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(41986), // Rule ID 13144 //
15102 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15103 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15104 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15105 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
15106 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15107 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
15108 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15109 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15110 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15111 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
15112 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15113 GIM_CheckIsSafeToFold, /*NumInsns*/2,
15114 // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$LHS) => (ORNv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
15115 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
15116 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
15117 GIR_RootToRootCopy, /*OpIdx*/2, // LHS
15118 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
15119 GIR_RootConstrainSelectedInstOperands,
15120 // GIR_Coverage, 13144,
15121 GIR_EraseRootFromParent_Done,
15122 // Label 870: @41986
15123 GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(42050), // Rule ID 4706 //
15124 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15125 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15126 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15127 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15128 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
15129 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15130 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
15131 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15132 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15133 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15134 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
15135 GIM_CheckIsSafeToFold, /*NumInsns*/2,
15136 // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] })) => (ORNv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
15137 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
15138 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
15139 GIR_RootToRootCopy, /*OpIdx*/1, // LHS
15140 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
15141 GIR_RootConstrainSelectedInstOperands,
15142 // GIR_Coverage, 4706,
15143 GIR_EraseRootFromParent_Done,
15144 // Label 871: @42050
15145 GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(42077), // Rule ID 4712 //
15146 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15147 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15148 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15149 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15150 // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (ORRv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
15151 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv16i8),
15152 GIR_RootConstrainSelectedInstOperands,
15153 // GIR_Coverage, 4712,
15154 GIR_Done,
15155 // Label 872: @42077
15156 GIM_Reject,
15157 // Label 857: @42078
15158 GIM_Reject,
15159 // Label 757: @42079
15160 GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(43386),
15161 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
15162 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
15163 GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(42199), // Rule ID 12618 //
15164 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15165 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15166 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15167 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15168 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
15169 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
15170 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15171 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
15172 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
15173 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
15174 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15175 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
15176 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15177 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
15178 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15179 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
15180 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
15181 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
15182 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15183 // MIs[4] Rd
15184 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
15185 GIM_CheckIsSafeToFold, /*NumInsns*/4,
15186 // (or:{ *:[v8i8] } (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
15187 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
15188 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
15190 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
15191 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
15192 GIR_RootConstrainSelectedInstOperands,
15193 // GIR_Coverage, 12618,
15194 GIR_EraseRootFromParent_Done,
15195 // Label 874: @42199
15196 GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(42308), // Rule ID 12617 //
15197 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15198 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15199 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15200 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15201 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
15202 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
15203 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15204 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
15205 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
15206 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
15207 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15208 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
15209 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15210 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
15211 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15212 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
15213 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
15214 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s8,
15215 // MIs[4] Rd
15216 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
15217 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15218 GIM_CheckIsSafeToFold, /*NumInsns*/4,
15219 // (or:{ *:[v8i8] } (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
15220 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
15221 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15222 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
15223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn
15224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
15225 GIR_RootConstrainSelectedInstOperands,
15226 // GIR_Coverage, 12617,
15227 GIR_EraseRootFromParent_Done,
15228 // Label 875: @42308
15229 GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(42417), // Rule ID 12620 //
15230 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15231 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15232 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15233 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15234 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
15235 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
15236 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15237 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15238 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
15239 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
15240 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
15241 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15242 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
15243 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15244 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
15245 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
15246 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
15247 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
15248 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15249 // MIs[4] Rd
15250 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
15251 GIM_CheckIsSafeToFold, /*NumInsns*/4,
15252 // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] })), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
15253 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
15254 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15255 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
15256 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
15257 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
15258 GIR_RootConstrainSelectedInstOperands,
15259 // GIR_Coverage, 12620,
15260 GIR_EraseRootFromParent_Done,
15261 // Label 876: @42417
15262 GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(42526), // Rule ID 12619 //
15263 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15264 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15265 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15266 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15267 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
15268 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
15269 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15270 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15271 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
15272 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
15273 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
15274 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15275 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
15276 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15277 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
15278 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
15279 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
15280 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s8,
15281 // MIs[4] Rd
15282 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
15283 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15284 GIM_CheckIsSafeToFold, /*NumInsns*/4,
15285 // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] })), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
15286 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
15287 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15288 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
15289 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn
15290 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
15291 GIR_RootConstrainSelectedInstOperands,
15292 // GIR_Coverage, 12619,
15293 GIR_EraseRootFromParent_Done,
15294 // Label 877: @42526
15295 GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(42635), // Rule ID 1592 //
15296 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15297 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15298 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15299 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15300 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
15301 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
15302 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15303 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15304 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
15305 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
15306 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
15307 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
15308 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15309 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
15310 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8,
15311 // MIs[3] Rd
15312 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
15313 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
15314 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15315 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
15316 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15317 GIM_CheckIsSafeToFold, /*NumInsns*/4,
15318 // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn), (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
15319 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
15320 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd
15322 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
15323 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
15324 GIR_RootConstrainSelectedInstOperands,
15325 // GIR_Coverage, 1592,
15326 GIR_EraseRootFromParent_Done,
15327 // Label 878: @42635
15328 GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(42744), // Rule ID 12615 //
15329 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15330 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15331 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15332 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15333 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
15334 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
15335 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15336 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15337 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
15338 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
15339 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
15340 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
15341 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15342 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
15343 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8,
15344 // MIs[3] Rd
15345 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
15346 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
15347 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15348 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
15349 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15350 GIM_CheckIsSafeToFold, /*NumInsns*/4,
15351 // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd), (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm)) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
15352 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
15353 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd
15355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
15356 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
15357 GIR_RootConstrainSelectedInstOperands,
15358 // GIR_Coverage, 12615,
15359 GIR_EraseRootFromParent_Done,
15360 // Label 879: @42744
15361 GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(42853), // Rule ID 12614 //
15362 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15363 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15364 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15365 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15366 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
15367 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
15368 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15369 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15370 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
15371 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
15372 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
15373 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
15374 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15375 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
15376 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
15377 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8,
15378 // MIs[3] Rd
15379 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
15380 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
15381 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15382 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
15383 GIM_CheckIsSafeToFold, /*NumInsns*/4,
15384 // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }))) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
15385 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
15386 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15387 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd
15388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
15389 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
15390 GIR_RootConstrainSelectedInstOperands,
15391 // GIR_Coverage, 12614,
15392 GIR_EraseRootFromParent_Done,
15393 // Label 880: @42853
15394 GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(42962), // Rule ID 12616 //
15395 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15396 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15397 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15398 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15399 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
15400 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
15401 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15402 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15403 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
15404 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
15405 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
15406 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
15407 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15408 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
15409 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
15410 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8,
15411 // MIs[3] Rd
15412 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
15413 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
15414 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15415 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
15416 GIM_CheckIsSafeToFold, /*NumInsns*/4,
15417 // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }))) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
15418 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
15419 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15420 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd
15421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
15422 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
15423 GIR_RootConstrainSelectedInstOperands,
15424 // GIR_Coverage, 12616,
15425 GIR_EraseRootFromParent_Done,
15426 // Label 881: @42962
15427 GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(43029), // Rule ID 12792 //
15428 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15429 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15430 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15431 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
15432 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
15433 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15434 // MIs[1] imm
15435 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15436 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15437 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
15438 // MIs[2] Operand 1
15439 // No operand predicates
15440 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15441 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
15442 GIM_CheckIsSafeToFold, /*NumInsns*/2,
15443 // (or:{ *:[v8i8] } (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V64:{ *:[v8i8] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (SSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
15444 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i8_shift),
15445 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15446 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
15447 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
15448 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
15449 GIR_RootConstrainSelectedInstOperands,
15450 // GIR_Coverage, 12792,
15451 GIR_EraseRootFromParent_Done,
15452 // Label 882: @43029
15453 GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(43096), // Rule ID 12813 //
15454 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15455 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15456 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15457 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
15458 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
15459 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15460 // MIs[1] imm
15461 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15462 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15463 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
15464 // MIs[2] Operand 1
15465 // No operand predicates
15466 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15467 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
15468 GIM_CheckIsSafeToFold, /*NumInsns*/2,
15469 // (or:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V64:{ *:[v8i8] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (USRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
15470 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i8_shift),
15471 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15472 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
15473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
15474 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
15475 GIR_RootConstrainSelectedInstOperands,
15476 // GIR_Coverage, 12813,
15477 GIR_EraseRootFromParent_Done,
15478 // Label 883: @43096
15479 GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(43163), // Rule ID 2216 //
15480 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15481 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15482 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15483 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15484 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
15485 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
15486 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15487 // MIs[1] imm
15488 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15489 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15490 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
15491 // MIs[2] Operand 1
15492 // No operand predicates
15493 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
15494 GIM_CheckIsSafeToFold, /*NumInsns*/2,
15495 // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>> => (SSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
15496 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i8_shift),
15497 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15498 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
15499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
15500 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
15501 GIR_RootConstrainSelectedInstOperands,
15502 // GIR_Coverage, 2216,
15503 GIR_EraseRootFromParent_Done,
15504 // Label 884: @43163
15505 GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(43230), // Rule ID 2275 //
15506 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15507 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15508 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15509 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15510 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
15511 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
15512 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15513 // MIs[1] imm
15514 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15515 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15516 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
15517 // MIs[2] Operand 1
15518 // No operand predicates
15519 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
15520 GIM_CheckIsSafeToFold, /*NumInsns*/2,
15521 // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>> => (USRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
15522 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i8_shift),
15523 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15524 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
15525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
15526 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
15527 GIR_RootConstrainSelectedInstOperands,
15528 // GIR_Coverage, 2275,
15529 GIR_EraseRootFromParent_Done,
15530 // Label 885: @43230
15531 GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(43294), // Rule ID 12612 //
15532 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15533 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15534 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15535 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
15536 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
15537 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
15538 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15539 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15540 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15541 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
15542 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15543 GIM_CheckIsSafeToFold, /*NumInsns*/2,
15544 // (or:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rn) => (ORNv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
15545 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
15546 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
15547 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
15548 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
15549 GIR_RootConstrainSelectedInstOperands,
15550 // GIR_Coverage, 12612,
15551 GIR_EraseRootFromParent_Done,
15552 // Label 886: @43294
15553 GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(43358), // Rule ID 1588 //
15554 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15555 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15556 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15557 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15558 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
15559 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
15560 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
15561 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15562 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15563 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15564 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
15565 GIM_CheckIsSafeToFold, /*NumInsns*/2,
15566 // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] })) => (ORNv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
15567 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
15568 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
15569 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
15570 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
15571 GIR_RootConstrainSelectedInstOperands,
15572 // GIR_Coverage, 1588,
15573 GIR_EraseRootFromParent_Done,
15574 // Label 887: @43358
15575 GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(43385), // Rule ID 1590 //
15576 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15577 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15578 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15579 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
15580 // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ORRv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
15581 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv8i8),
15582 GIR_RootConstrainSelectedInstOperands,
15583 // GIR_Coverage, 1590,
15584 GIR_Done,
15585 // Label 888: @43385
15586 GIM_Reject,
15587 // Label 873: @43386
15588 GIM_Reject,
15589 // Label 758: @43387
15590 GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(44694),
15591 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
15592 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15593 GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(43507), // Rule ID 12851 //
15594 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15595 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15596 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15597 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15598 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15599 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15600 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15601 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
15602 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
15603 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
15604 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15605 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
15606 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15607 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
15608 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15609 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
15610 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
15611 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
15612 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15613 // MIs[4] LHS
15614 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
15615 GIM_CheckIsSafeToFold, /*NumInsns*/4,
15616 // (or:{ *:[v8i16] } (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
15617 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
15618 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
15620 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
15621 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
15622 GIR_RootConstrainSelectedInstOperands,
15623 // GIR_Coverage, 12851,
15624 GIR_EraseRootFromParent_Done,
15625 // Label 890: @43507
15626 GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(43616), // Rule ID 12850 //
15627 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15628 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15629 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15630 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15631 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15632 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15633 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15634 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
15635 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
15636 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
15637 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15638 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
15639 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15640 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
15641 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15642 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
15643 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
15644 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s16,
15645 // MIs[4] LHS
15646 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
15647 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15648 GIM_CheckIsSafeToFold, /*NumInsns*/4,
15649 // (or:{ *:[v8i16] } (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
15650 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
15651 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15652 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
15653 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
15654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
15655 GIR_RootConstrainSelectedInstOperands,
15656 // GIR_Coverage, 12850,
15657 GIR_EraseRootFromParent_Done,
15658 // Label 891: @43616
15659 GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(43725), // Rule ID 12853 //
15660 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15661 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15662 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15663 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15664 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15665 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15666 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15667 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15668 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
15669 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
15670 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
15671 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15672 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
15673 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15674 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
15675 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
15676 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
15677 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
15678 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15679 // MIs[4] LHS
15680 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
15681 GIM_CheckIsSafeToFold, /*NumInsns*/4,
15682 // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] })), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
15683 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
15684 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15685 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
15686 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
15687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
15688 GIR_RootConstrainSelectedInstOperands,
15689 // GIR_Coverage, 12853,
15690 GIR_EraseRootFromParent_Done,
15691 // Label 892: @43725
15692 GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(43834), // Rule ID 12852 //
15693 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15694 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15695 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15696 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15697 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15698 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15699 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15700 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15701 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
15702 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
15703 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
15704 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15705 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
15706 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15707 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
15708 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
15709 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
15710 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s16,
15711 // MIs[4] LHS
15712 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
15713 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15714 GIM_CheckIsSafeToFold, /*NumInsns*/4,
15715 // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] })), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
15716 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
15717 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15718 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
15719 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
15720 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
15721 GIR_RootConstrainSelectedInstOperands,
15722 // GIR_Coverage, 12852,
15723 GIR_EraseRootFromParent_Done,
15724 // Label 893: @43834
15725 GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(43943), // Rule ID 2398 //
15726 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15727 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15728 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15729 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15730 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15731 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15732 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15733 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15734 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
15735 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
15736 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
15737 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
15738 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15739 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
15740 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
15741 // MIs[3] LHS
15742 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
15743 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
15744 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15745 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
15746 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15747 GIM_CheckIsSafeToFold, /*NumInsns*/4,
15748 // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS), (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
15749 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
15750 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15751 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
15752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
15753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
15754 GIR_RootConstrainSelectedInstOperands,
15755 // GIR_Coverage, 2398,
15756 GIR_EraseRootFromParent_Done,
15757 // Label 894: @43943
15758 GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(44052), // Rule ID 12848 //
15759 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15760 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15761 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15762 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15763 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15764 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15765 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15766 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15767 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
15768 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
15769 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
15770 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
15771 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15772 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
15773 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
15774 // MIs[3] LHS
15775 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
15776 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
15777 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15778 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
15779 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15780 GIM_CheckIsSafeToFold, /*NumInsns*/4,
15781 // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS), (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS)) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
15782 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
15783 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
15785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
15786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
15787 GIR_RootConstrainSelectedInstOperands,
15788 // GIR_Coverage, 12848,
15789 GIR_EraseRootFromParent_Done,
15790 // Label 895: @44052
15791 GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(44161), // Rule ID 12847 //
15792 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15793 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15794 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15795 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15796 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15797 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15798 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15799 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15800 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
15801 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
15802 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
15803 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
15804 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15805 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
15806 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
15807 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
15808 // MIs[3] LHS
15809 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
15810 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
15811 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15812 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
15813 GIM_CheckIsSafeToFold, /*NumInsns*/4,
15814 // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }))) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
15815 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
15816 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15817 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
15818 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
15819 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
15820 GIR_RootConstrainSelectedInstOperands,
15821 // GIR_Coverage, 12847,
15822 GIR_EraseRootFromParent_Done,
15823 // Label 896: @44161
15824 GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(44270), // Rule ID 12849 //
15825 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15826 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15827 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15828 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15829 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15830 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15831 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15832 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15833 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
15834 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
15835 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
15836 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
15837 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15838 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
15839 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
15840 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
15841 // MIs[3] LHS
15842 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
15843 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
15844 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15845 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
15846 GIM_CheckIsSafeToFold, /*NumInsns*/4,
15847 // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }))) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
15848 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
15849 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
15851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
15852 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
15853 GIR_RootConstrainSelectedInstOperands,
15854 // GIR_Coverage, 12849,
15855 GIR_EraseRootFromParent_Done,
15856 // Label 897: @44270
15857 GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(44337), // Rule ID 12798 //
15858 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15859 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15860 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15861 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
15862 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15863 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15864 // MIs[1] imm
15865 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15866 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15867 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
15868 // MIs[2] Operand 1
15869 // No operand predicates
15870 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15871 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
15872 GIM_CheckIsSafeToFold, /*NumInsns*/2,
15873 // (or:{ *:[v8i16] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V128:{ *:[v8i16] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (SSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
15874 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i16_shift),
15875 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15876 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
15877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
15878 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
15879 GIR_RootConstrainSelectedInstOperands,
15880 // GIR_Coverage, 12798,
15881 GIR_EraseRootFromParent_Done,
15882 // Label 898: @44337
15883 GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(44404), // Rule ID 12819 //
15884 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15885 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15886 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15887 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
15888 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15889 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15890 // MIs[1] imm
15891 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15892 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15893 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
15894 // MIs[2] Operand 1
15895 // No operand predicates
15896 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15897 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
15898 GIM_CheckIsSafeToFold, /*NumInsns*/2,
15899 // (or:{ *:[v8i16] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V128:{ *:[v8i16] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (USRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
15900 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i16_shift),
15901 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15902 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
15903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
15904 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
15905 GIR_RootConstrainSelectedInstOperands,
15906 // GIR_Coverage, 12819,
15907 GIR_EraseRootFromParent_Done,
15908 // Label 899: @44404
15909 GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(44471), // Rule ID 2222 //
15910 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15911 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15912 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15913 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15914 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
15915 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15916 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15917 // MIs[1] imm
15918 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15919 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15920 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
15921 // MIs[2] Operand 1
15922 // No operand predicates
15923 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
15924 GIM_CheckIsSafeToFold, /*NumInsns*/2,
15925 // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>> => (SSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
15926 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i16_shift),
15927 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15928 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
15929 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
15930 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
15931 GIR_RootConstrainSelectedInstOperands,
15932 // GIR_Coverage, 2222,
15933 GIR_EraseRootFromParent_Done,
15934 // Label 900: @44471
15935 GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(44538), // Rule ID 2281 //
15936 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15937 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15938 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15939 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15940 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
15941 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15942 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15943 // MIs[1] imm
15944 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15945 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15946 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
15947 // MIs[2] Operand 1
15948 // No operand predicates
15949 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
15950 GIM_CheckIsSafeToFold, /*NumInsns*/2,
15951 // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>> => (USRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
15952 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i16_shift),
15953 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15954 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
15955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
15956 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
15957 GIR_RootConstrainSelectedInstOperands,
15958 // GIR_Coverage, 2281,
15959 GIR_EraseRootFromParent_Done,
15960 // Label 901: @44538
15961 GIM_Try, /*On fail goto*//*Label 902*/ GIMT_Encode4(44602), // Rule ID 13143 //
15962 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15963 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15964 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15965 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
15966 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15967 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15968 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15969 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15970 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15971 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
15972 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15973 GIM_CheckIsSafeToFold, /*NumInsns*/2,
15974 // (or:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$LHS) => (ORNv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
15975 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
15976 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
15977 GIR_RootToRootCopy, /*OpIdx*/2, // LHS
15978 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
15979 GIR_RootConstrainSelectedInstOperands,
15980 // GIR_Coverage, 13143,
15981 GIR_EraseRootFromParent_Done,
15982 // Label 902: @44602
15983 GIM_Try, /*On fail goto*//*Label 903*/ GIMT_Encode4(44666), // Rule ID 4705 //
15984 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15985 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15986 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15987 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15988 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
15989 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15990 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15991 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
15992 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15993 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
15994 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
15995 GIM_CheckIsSafeToFold, /*NumInsns*/2,
15996 // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] })) => (ORNv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
15997 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
15998 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
15999 GIR_RootToRootCopy, /*OpIdx*/1, // LHS
16000 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
16001 GIR_RootConstrainSelectedInstOperands,
16002 // GIR_Coverage, 4705,
16003 GIR_EraseRootFromParent_Done,
16004 // Label 903: @44666
16005 GIM_Try, /*On fail goto*//*Label 904*/ GIMT_Encode4(44693), // Rule ID 4711 //
16006 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16007 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16008 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16009 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16010 // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (ORRv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
16011 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv16i8),
16012 GIR_RootConstrainSelectedInstOperands,
16013 // GIR_Coverage, 4711,
16014 GIR_Done,
16015 // Label 904: @44693
16016 GIM_Reject,
16017 // Label 889: @44694
16018 GIM_Reject,
16019 // Label 759: @44695
16020 GIM_Try, /*On fail goto*//*Label 905*/ GIMT_Encode4(46002),
16021 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
16022 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
16023 GIM_Try, /*On fail goto*//*Label 906*/ GIMT_Encode4(44815), // Rule ID 12625 //
16024 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16025 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16026 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16027 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16028 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16029 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16030 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16031 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
16032 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
16033 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
16034 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16035 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
16036 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
16037 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
16038 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16039 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
16040 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
16041 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v16s8,
16042 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16043 // MIs[4] Rd
16044 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
16045 GIM_CheckIsSafeToFold, /*NumInsns*/4,
16046 // (or:{ *:[v16i8] } (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
16047 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
16048 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
16050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
16051 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
16052 GIR_RootConstrainSelectedInstOperands,
16053 // GIR_Coverage, 12625,
16054 GIR_EraseRootFromParent_Done,
16055 // Label 906: @44815
16056 GIM_Try, /*On fail goto*//*Label 907*/ GIMT_Encode4(44924), // Rule ID 12624 //
16057 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16058 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16059 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16060 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16061 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16062 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16063 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16064 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
16065 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
16066 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
16067 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16068 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
16069 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
16070 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
16071 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16072 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
16073 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
16074 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v16s8,
16075 // MIs[4] Rd
16076 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
16077 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16078 GIM_CheckIsSafeToFold, /*NumInsns*/4,
16079 // (or:{ *:[v16i8] } (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
16080 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
16081 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
16083 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn
16084 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
16085 GIR_RootConstrainSelectedInstOperands,
16086 // GIR_Coverage, 12624,
16087 GIR_EraseRootFromParent_Done,
16088 // Label 907: @44924
16089 GIM_Try, /*On fail goto*//*Label 908*/ GIMT_Encode4(45033), // Rule ID 12627 //
16090 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16091 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16092 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16093 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16094 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16095 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16096 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16097 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16098 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
16099 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
16100 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
16101 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16102 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
16103 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
16104 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
16105 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
16106 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
16107 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v16s8,
16108 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16109 // MIs[4] Rd
16110 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
16111 GIM_CheckIsSafeToFold, /*NumInsns*/4,
16112 // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] })), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
16113 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
16114 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
16116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
16117 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
16118 GIR_RootConstrainSelectedInstOperands,
16119 // GIR_Coverage, 12627,
16120 GIR_EraseRootFromParent_Done,
16121 // Label 908: @45033
16122 GIM_Try, /*On fail goto*//*Label 909*/ GIMT_Encode4(45142), // Rule ID 12626 //
16123 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16124 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16125 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16126 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16127 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16128 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16129 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16130 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16131 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
16132 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
16133 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
16134 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16135 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
16136 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
16137 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
16138 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
16139 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
16140 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v16s8,
16141 // MIs[4] Rd
16142 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
16143 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16144 GIM_CheckIsSafeToFold, /*NumInsns*/4,
16145 // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] })), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
16146 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
16147 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16148 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
16149 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn
16150 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
16151 GIR_RootConstrainSelectedInstOperands,
16152 // GIR_Coverage, 12626,
16153 GIR_EraseRootFromParent_Done,
16154 // Label 909: @45142
16155 GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(45251), // Rule ID 1593 //
16156 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16157 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16158 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16159 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16160 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16161 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16162 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16163 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16164 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
16165 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
16166 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
16167 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
16168 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16169 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
16170 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8,
16171 // MIs[3] Rd
16172 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
16173 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
16174 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
16175 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
16176 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16177 GIM_CheckIsSafeToFold, /*NumInsns*/4,
16178 // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn), (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
16179 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
16180 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16181 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd
16182 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16183 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
16184 GIR_RootConstrainSelectedInstOperands,
16185 // GIR_Coverage, 1593,
16186 GIR_EraseRootFromParent_Done,
16187 // Label 910: @45251
16188 GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(45360), // Rule ID 12622 //
16189 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16190 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16191 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16192 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16193 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16194 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16195 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16196 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16197 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
16198 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
16199 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
16200 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
16201 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16202 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
16203 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8,
16204 // MIs[3] Rd
16205 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
16206 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
16207 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
16208 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
16209 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16210 GIM_CheckIsSafeToFold, /*NumInsns*/4,
16211 // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd), (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm)) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
16212 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
16213 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16214 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd
16215 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
16216 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
16217 GIR_RootConstrainSelectedInstOperands,
16218 // GIR_Coverage, 12622,
16219 GIR_EraseRootFromParent_Done,
16220 // Label 911: @45360
16221 GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(45469), // Rule ID 12621 //
16222 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16223 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16224 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16225 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16226 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16227 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16228 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16229 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16230 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
16231 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
16232 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
16233 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
16234 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16235 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
16236 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
16237 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8,
16238 // MIs[3] Rd
16239 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
16240 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
16241 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
16242 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
16243 GIM_CheckIsSafeToFold, /*NumInsns*/4,
16244 // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }))) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
16245 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
16246 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16247 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd
16248 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16249 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
16250 GIR_RootConstrainSelectedInstOperands,
16251 // GIR_Coverage, 12621,
16252 GIR_EraseRootFromParent_Done,
16253 // Label 912: @45469
16254 GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(45578), // Rule ID 12623 //
16255 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16256 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16257 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16258 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16259 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16260 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16261 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16262 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16263 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
16264 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
16265 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
16266 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
16267 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16268 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
16269 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
16270 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8,
16271 // MIs[3] Rd
16272 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
16273 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
16274 GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
16275 GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
16276 GIM_CheckIsSafeToFold, /*NumInsns*/4,
16277 // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }))) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
16278 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
16279 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16280 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd
16281 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
16282 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
16283 GIR_RootConstrainSelectedInstOperands,
16284 // GIR_Coverage, 12623,
16285 GIR_EraseRootFromParent_Done,
16286 // Label 913: @45578
16287 GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(45645), // Rule ID 12794 //
16288 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16289 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16290 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16291 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
16292 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16293 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16294 // MIs[1] imm
16295 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16296 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16297 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
16298 // MIs[2] Operand 1
16299 // No operand predicates
16300 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16301 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
16302 GIM_CheckIsSafeToFold, /*NumInsns*/2,
16303 // (or:{ *:[v16i8] } (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V128:{ *:[v16i8] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (SSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
16304 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv16i8_shift),
16305 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16306 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
16307 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
16308 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
16309 GIR_RootConstrainSelectedInstOperands,
16310 // GIR_Coverage, 12794,
16311 GIR_EraseRootFromParent_Done,
16312 // Label 914: @45645
16313 GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(45712), // Rule ID 12815 //
16314 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16315 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16316 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16317 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
16318 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16319 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16320 // MIs[1] imm
16321 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16322 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16323 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
16324 // MIs[2] Operand 1
16325 // No operand predicates
16326 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16327 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
16328 GIM_CheckIsSafeToFold, /*NumInsns*/2,
16329 // (or:{ *:[v16i8] } (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V128:{ *:[v16i8] }:$Rd)<<P:Predicate_add_and_or_is_add>> => (USRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
16330 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv16i8_shift),
16331 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16332 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
16333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
16334 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
16335 GIR_RootConstrainSelectedInstOperands,
16336 // GIR_Coverage, 12815,
16337 GIR_EraseRootFromParent_Done,
16338 // Label 915: @45712
16339 GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(45779), // Rule ID 2218 //
16340 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16341 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16342 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16343 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16344 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
16345 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16346 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16347 // MIs[1] imm
16348 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16349 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16350 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
16351 // MIs[2] Operand 1
16352 // No operand predicates
16353 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
16354 GIM_CheckIsSafeToFold, /*NumInsns*/2,
16355 // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>> => (SSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
16356 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv16i8_shift),
16357 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16358 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
16359 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
16360 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
16361 GIR_RootConstrainSelectedInstOperands,
16362 // GIR_Coverage, 2218,
16363 GIR_EraseRootFromParent_Done,
16364 // Label 916: @45779
16365 GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(45846), // Rule ID 2277 //
16366 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16367 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16368 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16369 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16370 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
16371 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16372 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16373 // MIs[1] imm
16374 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16375 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16376 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
16377 // MIs[2] Operand 1
16378 // No operand predicates
16379 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
16380 GIM_CheckIsSafeToFold, /*NumInsns*/2,
16381 // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>> => (USRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
16382 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv16i8_shift),
16383 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16384 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
16385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
16386 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
16387 GIR_RootConstrainSelectedInstOperands,
16388 // GIR_Coverage, 2277,
16389 GIR_EraseRootFromParent_Done,
16390 // Label 917: @45846
16391 GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(45910), // Rule ID 12613 //
16392 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16393 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16394 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16395 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16396 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16397 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16398 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16399 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16400 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
16401 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
16402 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16403 GIM_CheckIsSafeToFold, /*NumInsns*/2,
16404 // (or:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rn) => (ORNv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
16405 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
16406 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16407 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16408 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
16409 GIR_RootConstrainSelectedInstOperands,
16410 // GIR_Coverage, 12613,
16411 GIR_EraseRootFromParent_Done,
16412 // Label 918: @45910
16413 GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(45974), // Rule ID 1589 //
16414 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16415 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16416 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16417 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16418 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16419 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16420 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16421 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16422 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16423 GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
16424 GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
16425 GIM_CheckIsSafeToFold, /*NumInsns*/2,
16426 // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] })) => (ORNv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
16427 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
16428 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16429 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
16430 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
16431 GIR_RootConstrainSelectedInstOperands,
16432 // GIR_Coverage, 1589,
16433 GIR_EraseRootFromParent_Done,
16434 // Label 919: @45974
16435 GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(46001), // Rule ID 1591 //
16436 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16437 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16438 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16439 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
16440 // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ORRv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
16441 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv16i8),
16442 GIR_RootConstrainSelectedInstOperands,
16443 // GIR_Coverage, 1591,
16444 GIR_Done,
16445 // Label 920: @46001
16446 GIM_Reject,
16447 // Label 905: @46002
16448 GIM_Reject,
16449 // Label 760: @46003
16450 GIM_Try, /*On fail goto*//*Label 921*/ GIMT_Encode4(46034), // Rule ID 8103 //
16451 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
16452 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1,
16453 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
16454 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
16455 // (or:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2) => (SEL_PPPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
16456 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
16457 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
16458 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
16459 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
16460 GIR_RootToRootCopy, /*OpIdx*/2, // Op2
16461 GIR_RootConstrainSelectedInstOperands,
16462 // GIR_Coverage, 8103,
16463 GIR_EraseRootFromParent_Done,
16464 // Label 921: @46034
16465 GIM_Reject,
16466 // Label 761: @46035
16467 GIM_Try, /*On fail goto*//*Label 922*/ GIMT_Encode4(46066), // Rule ID 8102 //
16468 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
16469 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
16470 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
16471 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
16472 // (or:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2) => (SEL_PPPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
16473 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
16474 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
16475 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
16476 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
16477 GIR_RootToRootCopy, /*OpIdx*/2, // Op2
16478 GIR_RootConstrainSelectedInstOperands,
16479 // GIR_Coverage, 8102,
16480 GIR_EraseRootFromParent_Done,
16481 // Label 922: @46066
16482 GIM_Reject,
16483 // Label 762: @46067
16484 GIM_Try, /*On fail goto*//*Label 923*/ GIMT_Encode4(46092), // Rule ID 7123 //
16485 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
16486 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
16487 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
16488 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
16489 // (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (ORR_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
16490 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORR_ZZZ),
16491 GIR_RootConstrainSelectedInstOperands,
16492 // GIR_Coverage, 7123,
16493 GIR_Done,
16494 // Label 923: @46092
16495 GIM_Reject,
16496 // Label 763: @46093
16497 GIM_Try, /*On fail goto*//*Label 924*/ GIMT_Encode4(46124), // Rule ID 8101 //
16498 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
16499 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
16500 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
16501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
16502 // (or:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2) => (SEL_PPPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
16503 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
16504 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
16505 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
16506 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
16507 GIR_RootToRootCopy, /*OpIdx*/2, // Op2
16508 GIR_RootConstrainSelectedInstOperands,
16509 // GIR_Coverage, 8101,
16510 GIR_EraseRootFromParent_Done,
16511 // Label 924: @46124
16512 GIM_Reject,
16513 // Label 764: @46125
16514 GIM_Try, /*On fail goto*//*Label 925*/ GIMT_Encode4(46150), // Rule ID 7122 //
16515 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
16516 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
16517 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
16518 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
16519 // (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (ORR_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
16520 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORR_ZZZ),
16521 GIR_RootConstrainSelectedInstOperands,
16522 // GIR_Coverage, 7122,
16523 GIR_Done,
16524 // Label 925: @46150
16525 GIM_Reject,
16526 // Label 765: @46151
16527 GIM_Try, /*On fail goto*//*Label 926*/ GIMT_Encode4(46182), // Rule ID 8100 //
16528 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
16529 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
16530 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
16531 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
16532 // (or:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2) => (SEL_PPPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
16533 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
16534 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
16535 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
16536 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
16537 GIR_RootToRootCopy, /*OpIdx*/2, // Op2
16538 GIR_RootConstrainSelectedInstOperands,
16539 // GIR_Coverage, 8100,
16540 GIR_EraseRootFromParent_Done,
16541 // Label 926: @46182
16542 GIM_Reject,
16543 // Label 766: @46183
16544 GIM_Try, /*On fail goto*//*Label 927*/ GIMT_Encode4(46208), // Rule ID 7121 //
16545 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
16546 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
16547 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
16548 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
16549 // (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (ORR_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
16550 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORR_ZZZ),
16551 GIR_RootConstrainSelectedInstOperands,
16552 // GIR_Coverage, 7121,
16553 GIR_Done,
16554 // Label 927: @46208
16555 GIM_Reject,
16556 // Label 767: @46209
16557 GIM_Try, /*On fail goto*//*Label 928*/ GIMT_Encode4(46240), // Rule ID 8099 //
16558 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
16559 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
16560 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
16561 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
16562 // (or:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2) => (SEL_PPPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
16563 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
16564 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
16565 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
16566 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
16567 GIR_RootToRootCopy, /*OpIdx*/2, // Op2
16568 GIR_RootConstrainSelectedInstOperands,
16569 // GIR_Coverage, 8099,
16570 GIR_EraseRootFromParent_Done,
16571 // Label 928: @46240
16572 GIM_Reject,
16573 // Label 768: @46241
16574 GIM_Try, /*On fail goto*//*Label 929*/ GIMT_Encode4(46266), // Rule ID 7120 //
16575 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
16576 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
16577 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
16578 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
16579 // (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (ORR_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
16580 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORR_ZZZ),
16581 GIR_RootConstrainSelectedInstOperands,
16582 // GIR_Coverage, 7120,
16583 GIR_Done,
16584 // Label 929: @46266
16585 GIM_Reject,
16586 // Label 769: @46267
16587 GIM_Reject,
16588 // Label 7: @46268
16589 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(24), /*)*//*default:*//*Label 948*/ GIMT_Encode4(50458),
16590 /*GILLT_s32*//*Label 930*/ GIMT_Encode4(46367),
16591 /*GILLT_s64*//*Label 931*/ GIMT_Encode4(47047), GIMT_Encode4(0),
16592 /*GILLT_v2s32*//*Label 932*/ GIMT_Encode4(47790),
16593 /*GILLT_v2s64*//*Label 933*/ GIMT_Encode4(47858),
16594 /*GILLT_v4s16*//*Label 934*/ GIMT_Encode4(48384),
16595 /*GILLT_v4s32*//*Label 935*/ GIMT_Encode4(48452),
16596 /*GILLT_v8s8*//*Label 936*/ GIMT_Encode4(48978),
16597 /*GILLT_v8s16*//*Label 937*/ GIMT_Encode4(49049),
16598 /*GILLT_v16s8*//*Label 938*/ GIMT_Encode4(49575),
16599 /*GILLT_nxv1s1*//*Label 939*/ GIMT_Encode4(50104),
16600 /*GILLT_nxv2s1*//*Label 940*/ GIMT_Encode4(50154), GIMT_Encode4(0), GIMT_Encode4(0),
16601 /*GILLT_nxv2s64*//*Label 941*/ GIMT_Encode4(50204),
16602 /*GILLT_nxv4s1*//*Label 942*/ GIMT_Encode4(50230), GIMT_Encode4(0),
16603 /*GILLT_nxv4s32*//*Label 943*/ GIMT_Encode4(50280),
16604 /*GILLT_nxv8s1*//*Label 944*/ GIMT_Encode4(50306),
16605 /*GILLT_nxv8s16*//*Label 945*/ GIMT_Encode4(50356),
16606 /*GILLT_nxv16s1*//*Label 946*/ GIMT_Encode4(50382),
16607 /*GILLT_nxv16s8*//*Label 947*/ GIMT_Encode4(50432),
16608 // Label 930: @46367
16609 GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(47046),
16610 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
16611 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16612 GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(46436), // Rule ID 12483 //
16613 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16614 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16615 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16616 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16617 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16618 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16619 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
16620 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16621 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
16622 // (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] })) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
16623 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
16624 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
16626 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
16627 GIR_RootConstrainSelectedInstOperands,
16628 // GIR_Coverage, 12483,
16629 GIR_EraseRootFromParent_Done,
16630 // Label 950: @46436
16631 GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(46491), // Rule ID 12482 //
16632 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16633 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16634 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16635 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16636 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16637 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
16638 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16639 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16640 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
16641 // (xor:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
16642 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
16643 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16644 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16645 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
16646 GIR_RootConstrainSelectedInstOperands,
16647 // GIR_Coverage, 12482,
16648 GIR_EraseRootFromParent_Done,
16649 // Label 951: @46491
16650 GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(46549), // Rule ID 12480 //
16651 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16652 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16653 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16654 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16655 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16656 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16657 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16658 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16659 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
16660 // (xor:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn), -1:{ *:[i32] }) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
16661 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
16662 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16663 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16664 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
16665 GIR_RootConstrainSelectedInstOperands,
16666 // GIR_Coverage, 12480,
16667 GIR_EraseRootFromParent_Done,
16668 // Label 952: @46549
16669 GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(46607), // Rule ID 177 //
16670 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16671 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16672 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16673 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16674 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16675 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16676 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16677 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16678 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
16679 // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift), -1:{ *:[i32] }) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
16680 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
16681 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16682 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
16683 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
16684 GIR_RootConstrainSelectedInstOperands,
16685 // GIR_Coverage, 177,
16686 GIR_EraseRootFromParent_Done,
16687 // Label 953: @46607
16688 GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(46665), // Rule ID 12481 //
16689 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16690 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16691 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16692 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16693 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16694 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16695 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
16696 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16697 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
16698 // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] }), logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
16699 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
16700 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16701 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
16702 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
16703 GIR_RootConstrainSelectedInstOperands,
16704 // GIR_Coverage, 12481,
16705 GIR_EraseRootFromParent_Done,
16706 // Label 954: @46665
16707 GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(46720), // Rule ID 12484 //
16708 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16709 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16710 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16711 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16712 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16713 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16714 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
16715 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16716 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
16717 // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] })) => (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
16718 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
16719 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16720 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
16721 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
16722 GIR_RootConstrainSelectedInstOperands,
16723 // GIR_Coverage, 12484,
16724 GIR_EraseRootFromParent_Done,
16725 // Label 955: @46720
16726 GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(46761), // Rule ID 155 //
16727 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
16728 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16729 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16730 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16731 GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_logical_imm32),
16732 // MIs[1] Operand 1
16733 // No operand predicates
16734 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16735 // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_logical_imm32>><<X:logical_imm32_XFORM>>:$imm) => (EORWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (logical_imm32_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm))
16736 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORWri),
16737 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16738 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
16739 GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm32), // imm
16740 GIR_RootConstrainSelectedInstOperands,
16741 // GIR_Coverage, 155,
16742 GIR_EraseRootFromParent_Done,
16743 // Label 956: @46761
16744 GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(46794), // Rule ID 12490 //
16745 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16746 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16747 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
16748 // (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn) => (EORWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
16749 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORWrs),
16750 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16751 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16752 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
16753 GIR_RootConstrainSelectedInstOperands,
16754 // GIR_Coverage, 12490,
16755 GIR_EraseRootFromParent_Done,
16756 // Label 957: @46794
16757 GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(46827), // Rule ID 181 //
16758 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16759 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16760 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
16761 // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift) => (EORWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
16762 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORWrs),
16763 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16764 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
16765 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
16766 GIR_RootConstrainSelectedInstOperands,
16767 // GIR_Coverage, 181,
16768 GIR_EraseRootFromParent_Done,
16769 // Label 958: @46827
16770 GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(46880), // Rule ID 12476 //
16771 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16772 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16773 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16774 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16775 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16776 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16777 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
16778 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16779 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16780 // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rm) => (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
16781 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrr),
16782 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16783 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
16784 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
16785 GIR_RootConstrainSelectedInstOperands,
16786 // GIR_Coverage, 12476,
16787 GIR_EraseRootFromParent_Done,
16788 // Label 959: @46880
16789 GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(46936), // Rule ID 175 //
16790 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16791 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16792 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16793 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16794 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16795 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16796 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16797 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16798 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16799 // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm), -1:{ *:[i32] }) => (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
16800 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrr),
16801 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16802 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
16803 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
16804 GIR_RootConstrainSelectedInstOperands,
16805 // GIR_Coverage, 175,
16806 GIR_EraseRootFromParent_Done,
16807 // Label 960: @46936
16808 GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(46989), // Rule ID 12477 //
16809 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16810 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16811 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16812 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16813 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16814 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16815 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16816 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
16817 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16818 // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] })) => (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
16819 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrr),
16820 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16821 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
16822 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
16823 GIR_RootConstrainSelectedInstOperands,
16824 // GIR_Coverage, 12477,
16825 GIR_EraseRootFromParent_Done,
16826 // Label 961: @46989
16827 GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(47021), // Rule ID 3871 //
16828 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16829 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16830 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16831 // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Wm, -1:{ *:[i32] }) => (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Wm)
16832 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
16833 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16834 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16835 GIR_RootToRootCopy, /*OpIdx*/1, // Wm
16836 GIR_RootConstrainSelectedInstOperands,
16837 // GIR_Coverage, 3871,
16838 GIR_EraseRootFromParent_Done,
16839 // Label 962: @47021
16840 GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(47045), // Rule ID 179 //
16841 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16842 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16843 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
16844 // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (EORWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
16845 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORWrr),
16846 GIR_RootConstrainSelectedInstOperands,
16847 // GIR_Coverage, 179,
16848 GIR_Done,
16849 // Label 963: @47045
16850 GIM_Reject,
16851 // Label 949: @47046
16852 GIM_Reject,
16853 // Label 931: @47047
16854 GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(47789),
16855 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
16856 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
16857 GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(47116), // Rule ID 12488 //
16858 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
16859 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16860 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16861 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
16862 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16863 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
16864 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
16865 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16866 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
16867 // (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] })) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
16868 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
16869 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16870 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
16871 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
16872 GIR_RootConstrainSelectedInstOperands,
16873 // GIR_Coverage, 12488,
16874 GIR_EraseRootFromParent_Done,
16875 // Label 965: @47116
16876 GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(47171), // Rule ID 12487 //
16877 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
16878 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16879 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16880 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
16881 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16882 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
16883 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
16884 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16885 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
16886 // (xor:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
16887 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
16888 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16889 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16890 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
16891 GIR_RootConstrainSelectedInstOperands,
16892 // GIR_Coverage, 12487,
16893 GIR_EraseRootFromParent_Done,
16894 // Label 966: @47171
16895 GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(47229), // Rule ID 12485 //
16896 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
16897 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16898 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16899 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
16900 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16901 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
16902 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16903 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16904 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
16905 // (xor:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn), -1:{ *:[i64] }) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
16906 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
16907 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16909 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
16910 GIR_RootConstrainSelectedInstOperands,
16911 // GIR_Coverage, 12485,
16912 GIR_EraseRootFromParent_Done,
16913 // Label 967: @47229
16914 GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(47287), // Rule ID 178 //
16915 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
16916 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16917 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16918 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
16919 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16920 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
16921 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
16922 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16923 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
16924 // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift), -1:{ *:[i64] }) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
16925 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
16926 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16927 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
16928 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
16929 GIR_RootConstrainSelectedInstOperands,
16930 // GIR_Coverage, 178,
16931 GIR_EraseRootFromParent_Done,
16932 // Label 968: @47287
16933 GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(47345), // Rule ID 12486 //
16934 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
16935 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16936 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16937 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
16938 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16939 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
16940 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
16941 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16942 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
16943 // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] }), logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
16944 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
16945 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
16947 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
16948 GIR_RootConstrainSelectedInstOperands,
16949 // GIR_Coverage, 12486,
16950 GIR_EraseRootFromParent_Done,
16951 // Label 969: @47345
16952 GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(47400), // Rule ID 12489 //
16953 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
16954 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
16955 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16956 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
16957 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
16958 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16959 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
16960 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16961 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
16962 // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] })) => (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
16963 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
16964 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16965 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
16966 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
16967 GIR_RootConstrainSelectedInstOperands,
16968 // GIR_Coverage, 12489,
16969 GIR_EraseRootFromParent_Done,
16970 // Label 970: @47400
16971 GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(47441), // Rule ID 156 //
16972 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
16973 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
16974 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16975 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16976 GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_logical_imm64),
16977 // MIs[1] Operand 1
16978 // No operand predicates
16979 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16980 // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_logical_imm64>><<X:logical_imm64_XFORM>>:$imm) => (EORXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (logical_imm64_XFORM:{ *:[i64] } (imm:{ *:[i64] }):$imm))
16981 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORXri),
16982 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16983 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
16984 GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm64), // imm
16985 GIR_RootConstrainSelectedInstOperands,
16986 // GIR_Coverage, 156,
16987 GIR_EraseRootFromParent_Done,
16988 // Label 971: @47441
16989 GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(47474), // Rule ID 12491 //
16990 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
16991 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
16992 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
16993 // (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn) => (EORXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
16994 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORXrs),
16995 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16996 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16997 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
16998 GIR_RootConstrainSelectedInstOperands,
16999 // GIR_Coverage, 12491,
17000 GIR_EraseRootFromParent_Done,
17001 // Label 972: @47474
17002 GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(47507), // Rule ID 182 //
17003 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
17004 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
17005 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
17006 // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift) => (EORXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
17007 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORXrs),
17008 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17009 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
17010 GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
17011 GIR_RootConstrainSelectedInstOperands,
17012 // GIR_Coverage, 182,
17013 GIR_EraseRootFromParent_Done,
17014 // Label 973: @47507
17015 GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(47560), // Rule ID 12478 //
17016 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
17017 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17018 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17019 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
17020 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17021 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
17022 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
17023 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
17024 GIM_CheckIsSafeToFold, /*NumInsns*/1,
17025 // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rm) => (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
17026 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrr),
17027 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17028 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
17029 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
17030 GIR_RootConstrainSelectedInstOperands,
17031 // GIR_Coverage, 12478,
17032 GIR_EraseRootFromParent_Done,
17033 // Label 974: @47560
17034 GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(47616), // Rule ID 176 //
17035 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
17036 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17037 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17038 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
17039 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17040 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
17041 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
17042 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
17043 GIM_CheckIsSafeToFold, /*NumInsns*/1,
17044 // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm), -1:{ *:[i64] }) => (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
17045 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrr),
17046 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
17048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
17049 GIR_RootConstrainSelectedInstOperands,
17050 // GIR_Coverage, 176,
17051 GIR_EraseRootFromParent_Done,
17052 // Label 975: @47616
17053 GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(47669), // Rule ID 12479 //
17054 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
17055 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
17056 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17057 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17058 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
17059 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
17060 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
17061 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
17062 GIM_CheckIsSafeToFold, /*NumInsns*/1,
17063 // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] })) => (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
17064 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrr),
17065 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17066 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
17067 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
17068 GIR_RootConstrainSelectedInstOperands,
17069 // GIR_Coverage, 12479,
17070 GIR_EraseRootFromParent_Done,
17071 // Label 976: @47669
17072 GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(47701), // Rule ID 3872 //
17073 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
17074 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
17075 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
17076 // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Xm, -1:{ *:[i64] }) => (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Xm)
17077 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
17078 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17079 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17080 GIR_RootToRootCopy, /*OpIdx*/1, // Xm
17081 GIR_RootConstrainSelectedInstOperands,
17082 // GIR_Coverage, 3872,
17083 GIR_EraseRootFromParent_Done,
17084 // Label 977: @47701
17085 GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(47737), // Rule ID 4601 //
17086 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
17087 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
17088 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17089 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17090 GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
17091 GIM_CheckIsSafeToFold, /*NumInsns*/1,
17092 // (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, immAllOnesV:{ *:[v1i64] }) => (NOTv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn)
17093 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv8i8),
17094 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17095 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
17096 GIR_RootConstrainSelectedInstOperands,
17097 // GIR_Coverage, 4601,
17098 GIR_EraseRootFromParent_Done,
17099 // Label 978: @47737
17100 GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(47761), // Rule ID 180 //
17101 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
17102 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
17103 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
17104 // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (EORXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
17105 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORXrr),
17106 GIR_RootConstrainSelectedInstOperands,
17107 // GIR_Coverage, 180,
17108 GIR_Done,
17109 // Label 979: @47761
17110 GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(47788), // Rule ID 4698 //
17111 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
17112 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
17113 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
17114 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
17115 // (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS) => (EORv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
17116 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv8i8),
17117 GIR_RootConstrainSelectedInstOperands,
17118 // GIR_Coverage, 4698,
17119 GIR_Done,
17120 // Label 980: @47788
17121 GIM_Reject,
17122 // Label 964: @47789
17123 GIM_Reject,
17124 // Label 932: @47790
17125 GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(47857),
17126 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
17127 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
17128 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
17129 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
17130 GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(47837), // Rule ID 4599 //
17131 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17132 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17133 GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
17134 GIM_CheckIsSafeToFold, /*NumInsns*/1,
17135 // (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllOnesV:{ *:[v2i32] }) => (NOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
17136 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv8i8),
17137 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17138 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
17139 GIR_RootConstrainSelectedInstOperands,
17140 // GIR_Coverage, 4599,
17141 GIR_EraseRootFromParent_Done,
17142 // Label 982: @47837
17143 GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(47856), // Rule ID 4697 //
17144 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
17145 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
17146 // (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (EORv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
17147 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv8i8),
17148 GIR_RootConstrainSelectedInstOperands,
17149 // GIR_Coverage, 4697,
17150 GIR_Done,
17151 // Label 983: @47856
17152 GIM_Reject,
17153 // Label 981: @47857
17154 GIM_Reject,
17155 // Label 933: @47858
17156 GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(48383),
17157 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
17158 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
17159 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17160 GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(47958), // Rule ID 13013 //
17161 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17162 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17163 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17164 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
17165 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
17166 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17167 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17168 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
17169 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
17170 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17171 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
17172 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17173 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17174 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17175 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17176 GIM_CheckIsSafeToFold, /*NumInsns*/3,
17177 // (xor:{ *:[v2i64] } (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$Vm), V128:{ *:[v2i64] }:$Vn) => (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va)
17178 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
17179 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17180 GIR_RootToRootCopy, /*OpIdx*/2, // Vn
17181 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
17182 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
17183 GIR_RootConstrainSelectedInstOperands,
17184 // GIR_Coverage, 13013,
17185 GIR_EraseRootFromParent_Done,
17186 // Label 985: @47958
17187 GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(48043), // Rule ID 13012 //
17188 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17189 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17190 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17191 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
17192 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
17193 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17194 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17195 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17196 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
17197 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
17198 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17199 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
17200 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17201 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17202 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17203 GIM_CheckIsSafeToFold, /*NumInsns*/3,
17204 // (xor:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vm, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, immAllOnesV:{ *:[v2i64] })), V128:{ *:[v2i64] }:$Vn) => (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va)
17205 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
17206 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17207 GIR_RootToRootCopy, /*OpIdx*/2, // Vn
17208 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
17209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
17210 GIR_RootConstrainSelectedInstOperands,
17211 // GIR_Coverage, 13012,
17212 GIR_EraseRootFromParent_Done,
17213 // Label 986: @48043
17214 GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(48128), // Rule ID 13011 //
17215 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17216 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17217 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17218 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17219 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
17220 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
17221 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17222 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17223 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
17224 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
17225 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17226 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
17227 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17228 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17229 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17230 GIM_CheckIsSafeToFold, /*NumInsns*/3,
17231 // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$Vm)) => (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va)
17232 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
17233 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17234 GIR_RootToRootCopy, /*OpIdx*/1, // Vn
17235 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
17236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
17237 GIR_RootConstrainSelectedInstOperands,
17238 // GIR_Coverage, 13011,
17239 GIR_EraseRootFromParent_Done,
17240 // Label 987: @48128
17241 GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(48213), // Rule ID 3699 //
17242 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17243 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17244 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17245 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17246 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
17247 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
17248 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17249 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17250 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17251 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
17252 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
17253 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17254 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
17255 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17256 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17257 GIM_CheckIsSafeToFold, /*NumInsns*/3,
17258 // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vm, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, immAllOnesV:{ *:[v2i64] }))) => (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va)
17259 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
17260 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17261 GIR_RootToRootCopy, /*OpIdx*/1, // Vn
17262 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
17263 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
17264 GIR_RootConstrainSelectedInstOperands,
17265 // GIR_Coverage, 3699,
17266 GIR_EraseRootFromParent_Done,
17267 // Label 988: @48213
17268 GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(48245), // Rule ID 4602 //
17269 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17270 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17271 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17272 GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
17273 GIM_CheckIsSafeToFold, /*NumInsns*/1,
17274 // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllOnesV:{ *:[v2i64] }) => (NOTv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
17275 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv16i8),
17276 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17277 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
17278 GIR_RootConstrainSelectedInstOperands,
17279 // GIR_Coverage, 4602,
17280 GIR_EraseRootFromParent_Done,
17281 // Label 989: @48245
17282 GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(48302), // Rule ID 3695 //
17283 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17284 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17285 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17286 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
17287 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
17288 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17289 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17290 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17291 GIM_CheckIsSafeToFold, /*NumInsns*/1,
17292 // (xor:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm), V128:{ *:[v2i64] }:$Va) => (EOR3:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va)
17293 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
17294 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17295 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
17296 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
17297 GIR_RootToRootCopy, /*OpIdx*/2, // Va
17298 GIR_RootConstrainSelectedInstOperands,
17299 // GIR_Coverage, 3695,
17300 GIR_EraseRootFromParent_Done,
17301 // Label 990: @48302
17302 GIM_Try, /*On fail goto*//*Label 991*/ GIMT_Encode4(48359), // Rule ID 13001 //
17303 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17304 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17305 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17306 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17307 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
17308 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
17309 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17310 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17311 GIM_CheckIsSafeToFold, /*NumInsns*/1,
17312 // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)) => (EOR3:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va)
17313 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
17314 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17315 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
17316 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
17317 GIR_RootToRootCopy, /*OpIdx*/1, // Va
17318 GIR_RootConstrainSelectedInstOperands,
17319 // GIR_Coverage, 13001,
17320 GIR_EraseRootFromParent_Done,
17321 // Label 991: @48359
17322 GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(48382), // Rule ID 4701 //
17323 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
17324 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17325 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17326 // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (EORv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
17327 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv16i8),
17328 GIR_RootConstrainSelectedInstOperands,
17329 // GIR_Coverage, 4701,
17330 GIR_Done,
17331 // Label 992: @48382
17332 GIM_Reject,
17333 // Label 984: @48383
17334 GIM_Reject,
17335 // Label 934: @48384
17336 GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(48451),
17337 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
17338 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
17339 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
17340 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
17341 GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(48431), // Rule ID 4597 //
17342 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17343 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17344 GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
17345 GIM_CheckIsSafeToFold, /*NumInsns*/1,
17346 // (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllOnesV:{ *:[v4i16] }) => (NOTv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
17347 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv8i8),
17348 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17349 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
17350 GIR_RootConstrainSelectedInstOperands,
17351 // GIR_Coverage, 4597,
17352 GIR_EraseRootFromParent_Done,
17353 // Label 994: @48431
17354 GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(48450), // Rule ID 4696 //
17355 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
17356 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
17357 // (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (EORv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
17358 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv8i8),
17359 GIR_RootConstrainSelectedInstOperands,
17360 // GIR_Coverage, 4696,
17361 GIR_Done,
17362 // Label 995: @48450
17363 GIM_Reject,
17364 // Label 993: @48451
17365 GIM_Reject,
17366 // Label 935: @48452
17367 GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(48977),
17368 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
17369 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17370 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17371 GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(48552), // Rule ID 13010 //
17372 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17373 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17374 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17375 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17376 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17377 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17378 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17379 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17380 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17381 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17382 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
17383 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17384 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17385 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17386 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17387 GIM_CheckIsSafeToFold, /*NumInsns*/3,
17388 // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$Vm), V128:{ *:[v4i32] }:$Vn) => (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
17389 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
17390 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17391 GIR_RootToRootCopy, /*OpIdx*/2, // Vn
17392 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
17393 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
17394 GIR_RootConstrainSelectedInstOperands,
17395 // GIR_Coverage, 13010,
17396 GIR_EraseRootFromParent_Done,
17397 // Label 997: @48552
17398 GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(48637), // Rule ID 13009 //
17399 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17400 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17401 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17402 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17403 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17404 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17405 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17406 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17407 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17408 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17409 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17410 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
17411 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17412 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17413 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17414 GIM_CheckIsSafeToFold, /*NumInsns*/3,
17415 // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vm, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, immAllOnesV:{ *:[v4i32] })), V128:{ *:[v4i32] }:$Vn) => (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
17416 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
17417 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17418 GIR_RootToRootCopy, /*OpIdx*/2, // Vn
17419 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
17420 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
17421 GIR_RootConstrainSelectedInstOperands,
17422 // GIR_Coverage, 13009,
17423 GIR_EraseRootFromParent_Done,
17424 // Label 998: @48637
17425 GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(48722), // Rule ID 13008 //
17426 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17427 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17428 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17429 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17430 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17431 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17432 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17433 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17434 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17435 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17436 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17437 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
17438 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17439 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17440 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17441 GIM_CheckIsSafeToFold, /*NumInsns*/3,
17442 // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$Vm)) => (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
17443 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
17444 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17445 GIR_RootToRootCopy, /*OpIdx*/1, // Vn
17446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
17447 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
17448 GIR_RootConstrainSelectedInstOperands,
17449 // GIR_Coverage, 13008,
17450 GIR_EraseRootFromParent_Done,
17451 // Label 999: @48722
17452 GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(48807), // Rule ID 3698 //
17453 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17454 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17455 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17456 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17457 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17458 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17459 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17460 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17461 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17462 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17463 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
17464 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17465 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
17466 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17467 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17468 GIM_CheckIsSafeToFold, /*NumInsns*/3,
17469 // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vm, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, immAllOnesV:{ *:[v4i32] }))) => (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
17470 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
17471 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17472 GIR_RootToRootCopy, /*OpIdx*/1, // Vn
17473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
17474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
17475 GIR_RootConstrainSelectedInstOperands,
17476 // GIR_Coverage, 3698,
17477 GIR_EraseRootFromParent_Done,
17478 // Label 1000: @48807
17479 GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(48839), // Rule ID 4600 //
17480 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17481 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17482 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17483 GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
17484 GIM_CheckIsSafeToFold, /*NumInsns*/1,
17485 // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllOnesV:{ *:[v4i32] }) => (NOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
17486 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv16i8),
17487 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17488 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
17489 GIR_RootConstrainSelectedInstOperands,
17490 // GIR_Coverage, 4600,
17491 GIR_EraseRootFromParent_Done,
17492 // Label 1001: @48839
17493 GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(48896), // Rule ID 3694 //
17494 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17495 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17496 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17497 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17498 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17499 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17500 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17501 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17502 GIM_CheckIsSafeToFold, /*NumInsns*/1,
17503 // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm), V128:{ *:[v4i32] }:$Va) => (EOR3:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
17504 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
17505 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
17507 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
17508 GIR_RootToRootCopy, /*OpIdx*/2, // Va
17509 GIR_RootConstrainSelectedInstOperands,
17510 // GIR_Coverage, 3694,
17511 GIR_EraseRootFromParent_Done,
17512 // Label 1002: @48896
17513 GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(48953), // Rule ID 13000 //
17514 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17515 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17516 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17517 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17518 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17519 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17520 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17521 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17522 GIM_CheckIsSafeToFold, /*NumInsns*/1,
17523 // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)) => (EOR3:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
17524 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
17525 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
17527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
17528 GIR_RootToRootCopy, /*OpIdx*/1, // Va
17529 GIR_RootConstrainSelectedInstOperands,
17530 // GIR_Coverage, 13000,
17531 GIR_EraseRootFromParent_Done,
17532 // Label 1003: @48953
17533 GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(48976), // Rule ID 4700 //
17534 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
17535 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17536 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17537 // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (EORv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
17538 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv16i8),
17539 GIR_RootConstrainSelectedInstOperands,
17540 // GIR_Coverage, 4700,
17541 GIR_Done,
17542 // Label 1004: @48976
17543 GIM_Reject,
17544 // Label 996: @48977
17545 GIM_Reject,
17546 // Label 936: @48978
17547 GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(49048),
17548 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
17549 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
17550 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
17551 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
17552 GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(49028), // Rule ID 959 //
17553 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
17554 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17555 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17556 GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
17557 GIM_CheckIsSafeToFold, /*NumInsns*/1,
17558 // (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllOnesV:{ *:[v8i8] }) => (NOTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
17559 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv8i8),
17560 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17561 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
17562 GIR_RootConstrainSelectedInstOperands,
17563 // GIR_Coverage, 959,
17564 GIR_EraseRootFromParent_Done,
17565 // Label 1006: @49028
17566 GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(49047), // Rule ID 1586 //
17567 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
17568 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
17569 // (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (EORv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
17570 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv8i8),
17571 GIR_RootConstrainSelectedInstOperands,
17572 // GIR_Coverage, 1586,
17573 GIR_Done,
17574 // Label 1007: @49047
17575 GIM_Reject,
17576 // Label 1005: @49048
17577 GIM_Reject,
17578 // Label 937: @49049
17579 GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(49574),
17580 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
17581 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17582 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17583 GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(49149), // Rule ID 13007 //
17584 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17585 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17586 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17587 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17588 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
17589 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17590 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17591 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
17592 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
17593 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17594 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
17595 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17596 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17597 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17598 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17599 GIM_CheckIsSafeToFold, /*NumInsns*/3,
17600 // (xor:{ *:[v8i16] } (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$Vm), V128:{ *:[v8i16] }:$Vn) => (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va)
17601 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
17602 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17603 GIR_RootToRootCopy, /*OpIdx*/2, // Vn
17604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
17605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
17606 GIR_RootConstrainSelectedInstOperands,
17607 // GIR_Coverage, 13007,
17608 GIR_EraseRootFromParent_Done,
17609 // Label 1009: @49149
17610 GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(49234), // Rule ID 13006 //
17611 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17612 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17613 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17614 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17615 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
17616 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17617 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17618 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17619 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
17620 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
17621 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17622 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
17623 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17624 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17625 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17626 GIM_CheckIsSafeToFold, /*NumInsns*/3,
17627 // (xor:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vm, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, immAllOnesV:{ *:[v8i16] })), V128:{ *:[v8i16] }:$Vn) => (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va)
17628 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
17629 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17630 GIR_RootToRootCopy, /*OpIdx*/2, // Vn
17631 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
17632 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
17633 GIR_RootConstrainSelectedInstOperands,
17634 // GIR_Coverage, 13006,
17635 GIR_EraseRootFromParent_Done,
17636 // Label 1010: @49234
17637 GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(49319), // Rule ID 13005 //
17638 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17639 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17640 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17641 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17642 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17643 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
17644 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17645 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17646 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
17647 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
17648 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17649 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
17650 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17651 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17652 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17653 GIM_CheckIsSafeToFold, /*NumInsns*/3,
17654 // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$Vm)) => (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va)
17655 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
17656 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17657 GIR_RootToRootCopy, /*OpIdx*/1, // Vn
17658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
17659 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
17660 GIR_RootConstrainSelectedInstOperands,
17661 // GIR_Coverage, 13005,
17662 GIR_EraseRootFromParent_Done,
17663 // Label 1011: @49319
17664 GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(49404), // Rule ID 3697 //
17665 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17666 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17667 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17668 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17669 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17670 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
17671 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17672 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17673 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17674 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
17675 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
17676 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17677 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
17678 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17679 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17680 GIM_CheckIsSafeToFold, /*NumInsns*/3,
17681 // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vm, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, immAllOnesV:{ *:[v8i16] }))) => (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va)
17682 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
17683 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17684 GIR_RootToRootCopy, /*OpIdx*/1, // Vn
17685 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
17686 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
17687 GIR_RootConstrainSelectedInstOperands,
17688 // GIR_Coverage, 3697,
17689 GIR_EraseRootFromParent_Done,
17690 // Label 1012: @49404
17691 GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(49436), // Rule ID 4598 //
17692 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17693 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17694 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17695 GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
17696 GIM_CheckIsSafeToFold, /*NumInsns*/1,
17697 // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllOnesV:{ *:[v8i16] }) => (NOTv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
17698 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv16i8),
17699 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17700 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
17701 GIR_RootConstrainSelectedInstOperands,
17702 // GIR_Coverage, 4598,
17703 GIR_EraseRootFromParent_Done,
17704 // Label 1013: @49436
17705 GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(49493), // Rule ID 3693 //
17706 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17707 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17708 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17709 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17710 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
17711 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17712 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17713 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17714 GIM_CheckIsSafeToFold, /*NumInsns*/1,
17715 // (xor:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm), V128:{ *:[v8i16] }:$Va) => (EOR3:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va)
17716 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
17717 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17718 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
17719 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
17720 GIR_RootToRootCopy, /*OpIdx*/2, // Va
17721 GIR_RootConstrainSelectedInstOperands,
17722 // GIR_Coverage, 3693,
17723 GIR_EraseRootFromParent_Done,
17724 // Label 1014: @49493
17725 GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(49550), // Rule ID 12999 //
17726 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17727 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17728 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17729 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17730 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17731 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
17732 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17733 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17734 GIM_CheckIsSafeToFold, /*NumInsns*/1,
17735 // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)) => (EOR3:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va)
17736 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
17737 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17738 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
17739 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
17740 GIR_RootToRootCopy, /*OpIdx*/1, // Va
17741 GIR_RootConstrainSelectedInstOperands,
17742 // GIR_Coverage, 12999,
17743 GIR_EraseRootFromParent_Done,
17744 // Label 1015: @49550
17745 GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(49573), // Rule ID 4699 //
17746 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
17747 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17748 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17749 // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (EORv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
17750 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv16i8),
17751 GIR_RootConstrainSelectedInstOperands,
17752 // GIR_Coverage, 4699,
17753 GIR_Done,
17754 // Label 1016: @49573
17755 GIM_Reject,
17756 // Label 1008: @49574
17757 GIM_Reject,
17758 // Label 938: @49575
17759 GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(50103),
17760 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
17761 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
17762 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17763 GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(49675), // Rule ID 13004 //
17764 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17765 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17766 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17767 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
17768 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
17769 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17770 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17771 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
17772 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
17773 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17774 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
17775 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17776 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17777 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17778 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17779 GIM_CheckIsSafeToFold, /*NumInsns*/3,
17780 // (xor:{ *:[v16i8] } (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Vm), V128:{ *:[v16i8] }:$Vn) => (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va)
17781 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
17782 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17783 GIR_RootToRootCopy, /*OpIdx*/2, // Vn
17784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
17785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
17786 GIR_RootConstrainSelectedInstOperands,
17787 // GIR_Coverage, 13004,
17788 GIR_EraseRootFromParent_Done,
17789 // Label 1018: @49675
17790 GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(49760), // Rule ID 13003 //
17791 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17792 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17793 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17794 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
17795 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
17796 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17797 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17798 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17799 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
17800 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
17801 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17802 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
17803 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17804 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17805 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17806 GIM_CheckIsSafeToFold, /*NumInsns*/3,
17807 // (xor:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, immAllOnesV:{ *:[v16i8] })), V128:{ *:[v16i8] }:$Vn) => (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va)
17808 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
17809 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17810 GIR_RootToRootCopy, /*OpIdx*/2, // Vn
17811 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
17812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
17813 GIR_RootConstrainSelectedInstOperands,
17814 // GIR_Coverage, 13003,
17815 GIR_EraseRootFromParent_Done,
17816 // Label 1019: @49760
17817 GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(49845), // Rule ID 13002 //
17818 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17819 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17820 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17821 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17822 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
17823 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
17824 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17825 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17826 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
17827 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
17828 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17829 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
17830 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17831 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17832 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17833 GIM_CheckIsSafeToFold, /*NumInsns*/3,
17834 // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Vm)) => (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va)
17835 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
17836 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17837 GIR_RootToRootCopy, /*OpIdx*/1, // Vn
17838 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
17839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
17840 GIR_RootConstrainSelectedInstOperands,
17841 // GIR_Coverage, 13002,
17842 GIR_EraseRootFromParent_Done,
17843 // Label 1020: @49845
17844 GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(49930), // Rule ID 3696 //
17845 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17846 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17847 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17848 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17849 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
17850 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
17851 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17852 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17853 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
17854 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
17855 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
17856 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17857 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
17858 GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17859 GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
17860 GIM_CheckIsSafeToFold, /*NumInsns*/3,
17861 // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, immAllOnesV:{ *:[v16i8] }))) => (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va)
17862 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
17863 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17864 GIR_RootToRootCopy, /*OpIdx*/1, // Vn
17865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
17866 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
17867 GIR_RootConstrainSelectedInstOperands,
17868 // GIR_Coverage, 3696,
17869 GIR_EraseRootFromParent_Done,
17870 // Label 1021: @49930
17871 GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(49965), // Rule ID 960 //
17872 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
17873 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17874 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17875 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
17876 GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
17877 GIM_CheckIsSafeToFold, /*NumInsns*/1,
17878 // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllOnesV:{ *:[v16i8] }) => (NOTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
17879 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv16i8),
17880 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17881 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
17882 GIR_RootConstrainSelectedInstOperands,
17883 // GIR_Coverage, 960,
17884 GIR_EraseRootFromParent_Done,
17885 // Label 1022: @49965
17886 GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(50022), // Rule ID 3692 //
17887 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17888 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
17889 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17890 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
17891 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
17892 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17893 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17894 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17895 GIM_CheckIsSafeToFold, /*NumInsns*/1,
17896 // (xor:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm), V128:{ *:[v16i8] }:$Va) => (EOR3:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va)
17897 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
17898 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17899 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
17900 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
17901 GIR_RootToRootCopy, /*OpIdx*/2, // Va
17902 GIR_RootConstrainSelectedInstOperands,
17903 // GIR_Coverage, 3692,
17904 GIR_EraseRootFromParent_Done,
17905 // Label 1023: @50022
17906 GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(50079), // Rule ID 12998 //
17907 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
17908 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17909 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17910 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
17911 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
17912 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
17913 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17914 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17915 GIM_CheckIsSafeToFold, /*NumInsns*/1,
17916 // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)) => (EOR3:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va)
17917 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
17918 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17919 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
17920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
17921 GIR_RootToRootCopy, /*OpIdx*/1, // Va
17922 GIR_RootConstrainSelectedInstOperands,
17923 // GIR_Coverage, 12998,
17924 GIR_EraseRootFromParent_Done,
17925 // Label 1024: @50079
17926 GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(50102), // Rule ID 1587 //
17927 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
17928 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17929 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
17930 // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (EORv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
17931 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv16i8),
17932 GIR_RootConstrainSelectedInstOperands,
17933 // GIR_Coverage, 1587,
17934 GIR_Done,
17935 // Label 1025: @50102
17936 GIM_Reject,
17937 // Label 1017: @50103
17938 GIM_Reject,
17939 // Label 939: @50104
17940 GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(50153), // Rule ID 8093 //
17941 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
17942 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1,
17943 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
17944 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
17945 // (xor:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2) => (EOR_PPzPP:{ *:[nxv1i1] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
17946 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
17947 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
17948 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17949 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
17950 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17951 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
17952 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
17953 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17954 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
17955 GIR_RootToRootCopy, /*OpIdx*/2, // Op2
17956 GIR_RootConstrainSelectedInstOperands,
17957 // GIR_Coverage, 8093,
17958 GIR_EraseRootFromParent_Done,
17959 // Label 1026: @50153
17960 GIM_Reject,
17961 // Label 940: @50154
17962 GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(50203), // Rule ID 8092 //
17963 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
17964 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
17965 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
17966 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
17967 // (xor:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2) => (EOR_PPzPP:{ *:[nxv2i1] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
17968 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
17969 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
17970 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17971 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
17972 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17973 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
17974 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
17975 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17976 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
17977 GIR_RootToRootCopy, /*OpIdx*/2, // Op2
17978 GIR_RootConstrainSelectedInstOperands,
17979 // GIR_Coverage, 8092,
17980 GIR_EraseRootFromParent_Done,
17981 // Label 1027: @50203
17982 GIM_Reject,
17983 // Label 941: @50204
17984 GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(50229), // Rule ID 7127 //
17985 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
17986 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
17987 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
17988 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
17989 // (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (EOR_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
17990 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EOR_ZZZ),
17991 GIR_RootConstrainSelectedInstOperands,
17992 // GIR_Coverage, 7127,
17993 GIR_Done,
17994 // Label 1028: @50229
17995 GIM_Reject,
17996 // Label 942: @50230
17997 GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(50279), // Rule ID 8091 //
17998 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
17999 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
18000 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
18001 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
18002 // (xor:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2) => (EOR_PPzPP:{ *:[nxv4i1] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
18003 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
18004 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
18005 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18006 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
18007 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18008 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
18009 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
18010 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18011 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
18012 GIR_RootToRootCopy, /*OpIdx*/2, // Op2
18013 GIR_RootConstrainSelectedInstOperands,
18014 // GIR_Coverage, 8091,
18015 GIR_EraseRootFromParent_Done,
18016 // Label 1029: @50279
18017 GIM_Reject,
18018 // Label 943: @50280
18019 GIM_Try, /*On fail goto*//*Label 1030*/ GIMT_Encode4(50305), // Rule ID 7126 //
18020 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
18021 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
18022 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
18023 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
18024 // (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (EOR_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
18025 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EOR_ZZZ),
18026 GIR_RootConstrainSelectedInstOperands,
18027 // GIR_Coverage, 7126,
18028 GIR_Done,
18029 // Label 1030: @50305
18030 GIM_Reject,
18031 // Label 944: @50306
18032 GIM_Try, /*On fail goto*//*Label 1031*/ GIMT_Encode4(50355), // Rule ID 8090 //
18033 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
18034 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
18035 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
18036 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
18037 // (xor:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2) => (EOR_PPzPP:{ *:[nxv8i1] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
18038 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
18039 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
18040 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18041 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
18042 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18043 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
18044 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
18045 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18046 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
18047 GIR_RootToRootCopy, /*OpIdx*/2, // Op2
18048 GIR_RootConstrainSelectedInstOperands,
18049 // GIR_Coverage, 8090,
18050 GIR_EraseRootFromParent_Done,
18051 // Label 1031: @50355
18052 GIM_Reject,
18053 // Label 945: @50356
18054 GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(50381), // Rule ID 7125 //
18055 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
18056 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
18057 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
18058 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
18059 // (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (EOR_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
18060 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EOR_ZZZ),
18061 GIR_RootConstrainSelectedInstOperands,
18062 // GIR_Coverage, 7125,
18063 GIR_Done,
18064 // Label 1032: @50381
18065 GIM_Reject,
18066 // Label 946: @50382
18067 GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(50431), // Rule ID 8089 //
18068 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
18069 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
18070 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
18071 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
18072 // (xor:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2) => (EOR_PPzPP:{ *:[nxv16i1] } (PTRUE_B:{ *:[nxv1i1] } 31:{ *:[i32] }), ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
18073 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
18074 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_B),
18075 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18076 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
18077 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18078 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
18079 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
18080 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18081 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
18082 GIR_RootToRootCopy, /*OpIdx*/2, // Op2
18083 GIR_RootConstrainSelectedInstOperands,
18084 // GIR_Coverage, 8089,
18085 GIR_EraseRootFromParent_Done,
18086 // Label 1033: @50431
18087 GIM_Reject,
18088 // Label 947: @50432
18089 GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(50457), // Rule ID 7124 //
18090 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
18091 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
18092 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
18093 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
18094 // (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (EOR_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
18095 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EOR_ZZZ),
18096 GIR_RootConstrainSelectedInstOperands,
18097 // GIR_Coverage, 7124,
18098 GIR_Done,
18099 // Label 1034: @50457
18100 GIM_Reject,
18101 // Label 948: @50458
18102 GIM_Reject,
18103 // Label 8: @50459
18104 GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(60839),
18105 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
18106 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(23), /*)*//*default:*//*Label 1047*/ GIMT_Encode4(60838),
18107 /*GILLT_v2s64*//*Label 1036*/ GIMT_Encode4(50546), GIMT_Encode4(0),
18108 /*GILLT_v4s32*//*Label 1037*/ GIMT_Encode4(51067), GIMT_Encode4(0),
18109 /*GILLT_v8s16*//*Label 1038*/ GIMT_Encode4(54316),
18110 /*GILLT_v16s8*//*Label 1039*/ GIMT_Encode4(57824), GIMT_Encode4(0),
18111 /*GILLT_nxv2s1*//*Label 1040*/ GIMT_Encode4(60614), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
18112 /*GILLT_nxv4s1*//*Label 1041*/ GIMT_Encode4(60640),
18113 /*GILLT_nxv4s16*//*Label 1042*/ GIMT_Encode4(60666),
18114 /*GILLT_nxv4s32*//*Label 1043*/ GIMT_Encode4(60713),
18115 /*GILLT_nxv8s1*//*Label 1044*/ GIMT_Encode4(60739),
18116 /*GILLT_nxv8s16*//*Label 1045*/ GIMT_Encode4(60765),
18117 /*GILLT_nxv16s1*//*Label 1046*/ GIMT_Encode4(60812),
18118 // Label 1036: @50546
18119 GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(51066),
18120 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
18121 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
18122 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18123 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18124 GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(50627), // Rule ID 5406 //
18125 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18126 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
18127 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
18128 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18129 // (concat_vectors:{ *:[v2i64] } V64:{ *:[v1i64] }:$Rn, immAllZerosV:{ *:[v1i64] }) => (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v1i64] }:$Rn), dsub:{ *:[i32] })
18130 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18131 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
18132 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18133 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
18134 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18135 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
18136 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18137 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18138 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18139 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
18140 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18141 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18142 // GIR_Coverage, 5406,
18143 GIR_EraseRootFromParent_Done,
18144 // Label 1049: @50627
18145 GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(50689), // Rule ID 5409 //
18146 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18147 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
18148 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
18149 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18150 // (concat_vectors:{ *:[v2f64] } V64:{ *:[v1f64] }:$Rn, immAllZerosV:{ *:[v1f64] }) => (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v1f64] }:$Rn), dsub:{ *:[i32] })
18151 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18152 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
18153 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18154 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
18155 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18156 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
18157 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18158 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18159 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18160 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
18161 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18162 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18163 // GIR_Coverage, 5409,
18164 GIR_EraseRootFromParent_Done,
18165 // Label 1050: @50689
18166 GIM_Try, /*On fail goto*//*Label 1051*/ GIMT_Encode4(50747), // Rule ID 5407 //
18167 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18168 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
18169 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18170 // (concat_vectors:{ *:[v2i64] } V64:{ *:[v1i64] }:$Rn, (undef:{ *:[v1i64] })) => (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] })
18171 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
18172 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18173 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18174 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18175 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18176 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18177 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18178 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
18179 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
18180 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18181 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18182 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18183 // GIR_Coverage, 5407,
18184 GIR_EraseRootFromParent_Done,
18185 // Label 1051: @50747
18186 GIM_Try, /*On fail goto*//*Label 1052*/ GIMT_Encode4(50805), // Rule ID 5410 //
18187 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18188 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
18189 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18190 // (concat_vectors:{ *:[v2f64] } V64:{ *:[v1f64] }:$Rn, (undef:{ *:[v1f64] })) => (INSERT_SUBREG:{ *:[v2f64] } (IMPLICIT_DEF:{ *:[v2f64] }), V64:{ *:[v1f64] }:$Rn, dsub:{ *:[i32] })
18191 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
18192 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18193 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18194 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18195 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18196 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18197 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18198 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
18199 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
18200 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18201 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18202 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18203 // GIR_Coverage, 5410,
18204 GIR_EraseRootFromParent_Done,
18205 // Label 1052: @50805
18206 GIM_Try, /*On fail goto*//*Label 1053*/ GIMT_Encode4(50935), // Rule ID 5405 //
18207 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18208 // (concat_vectors:{ *:[v2i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v1i64] }:$Rn) => (INSvi64lane:{ *:[v2i64] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1i64] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
18209 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18210 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
18211 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
18212 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
18213 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18214 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18215 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
18216 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18217 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18218 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
18219 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18220 GIR_AddImm8, /*InsnID*/3, /*Imm*/2,
18221 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18222 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18223 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18224 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18225 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18226 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18227 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18228 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18229 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18230 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
18231 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18232 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18233 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18234 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18235 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
18236 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18237 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18238 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18239 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
18240 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18241 GIR_RootConstrainSelectedInstOperands,
18242 // GIR_Coverage, 5405,
18243 GIR_EraseRootFromParent_Done,
18244 // Label 1053: @50935
18245 GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(51065), // Rule ID 5408 //
18246 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18247 // (concat_vectors:{ *:[v2f64] } V64:{ *:[v1f64] }:$Rd, V64:{ *:[v1f64] }:$Rn) => (INSvi64lane:{ *:[v2f64] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1f64] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1f64] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
18248 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18249 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
18250 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
18251 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
18252 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18253 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18254 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
18255 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18256 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18257 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
18258 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18259 GIR_AddImm8, /*InsnID*/3, /*Imm*/2,
18260 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18261 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18262 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18263 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18264 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18265 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18266 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18267 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18268 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18269 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
18270 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18271 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18272 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18273 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18274 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
18275 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18276 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18277 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18278 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
18279 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18280 GIR_RootConstrainSelectedInstOperands,
18281 // GIR_Coverage, 5408,
18282 GIR_EraseRootFromParent_Done,
18283 // Label 1054: @51065
18284 GIM_Reject,
18285 // Label 1048: @51066
18286 GIM_Reject,
18287 // Label 1037: @51067
18288 GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(54315),
18289 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
18290 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
18291 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18292 GIM_Try, /*On fail goto*//*Label 1056*/ GIMT_Encode4(51204), // Rule ID 5068 //
18293 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18294 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18295 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
18296 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
18297 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
18298 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
18299 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
18300 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
18301 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ADD),
18302 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
18303 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
18304 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18305 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18306 // MIs[2] Operand 2
18307 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
18308 GIM_CheckIsSafeToFold, /*NumInsns*/3,
18309 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] }))) => (ADDHNv2i64_v4i32:{ *:[v4i32] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
18310 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18311 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
18312 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18313 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
18314 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
18315 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18316 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18317 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18318 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv2i64_v4i32),
18319 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18320 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
18322 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
18323 GIR_RootConstrainSelectedInstOperands,
18324 // GIR_Coverage, 5068,
18325 GIR_EraseRootFromParent_Done,
18326 // Label 1056: @51204
18327 GIM_Try, /*On fail goto*//*Label 1057*/ GIMT_Encode4(51326), // Rule ID 5074 //
18328 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18329 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18330 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
18331 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
18332 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
18333 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
18334 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
18335 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
18336 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SUB),
18337 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
18338 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
18339 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18340 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18341 // MIs[2] Operand 2
18342 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
18343 GIM_CheckIsSafeToFold, /*NumInsns*/3,
18344 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] }))) => (SUBHNv2i64_v4i32:{ *:[v4i32] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
18345 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18346 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
18347 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18348 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
18349 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
18350 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18351 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18352 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18353 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv2i64_v4i32),
18354 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18355 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18356 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
18357 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
18358 GIR_RootConstrainSelectedInstOperands,
18359 // GIR_Coverage, 5074,
18360 GIR_EraseRootFromParent_Done,
18361 // Label 1057: @51326
18362 GIM_Try, /*On fail goto*//*Label 1058*/ GIMT_Encode4(51428), // Rule ID 5235 //
18363 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18364 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
18365 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
18366 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
18367 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
18368 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
18369 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18370 // MIs[2] Operand 2
18371 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
18372 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
18373 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC),
18374 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
18375 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
18376 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_VLSHR),
18377 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64,
18378 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18379 // MIs[4] Operand 2
18380 GIM_CheckLiteralInt, /*MI*/4, /*Op*/2, GIMT_Encode8(32),
18381 GIM_CheckIsSafeToFold, /*NumInsns*/4,
18382 // (concat_vectors:{ *:[v4i32] } (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, 32:{ *:[i32] })), (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vm, 32:{ *:[i32] }))) => (UZP2v4i32:{ *:[v4i32] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
18383 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i32),
18384 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
18386 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Vm
18387 GIR_RootConstrainSelectedInstOperands,
18388 // GIR_Coverage, 5235,
18389 GIR_EraseRootFromParent_Done,
18390 // Label 1058: @51428
18391 GIM_Try, /*On fail goto*//*Label 1059*/ GIMT_Encode4(51557), // Rule ID 5935 //
18392 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18393 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18394 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
18395 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
18396 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
18397 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
18398 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18399 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18400 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 32,
18401 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18402 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Vd, (intrinsic_wo_chain:{ *:[v2i32] } 619:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vn, 32:{ *:[i32] })) => (RADDHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Vd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Vn, (MOVIv2d_ns:{ *:[v2i64] } 0:{ *:[i32] }))
18403 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18404 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
18405 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
18406 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
18407 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18408 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
18409 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
18410 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18411 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18412 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18413 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18414 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18415 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18416 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vd
18417 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18418 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18419 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18420 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18421 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv2i64_v4i32),
18422 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18423 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18424 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
18425 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
18426 GIR_RootConstrainSelectedInstOperands,
18427 // GIR_Coverage, 5935,
18428 GIR_EraseRootFromParent_Done,
18429 // Label 1059: @51557
18430 GIM_Try, /*On fail goto*//*Label 1060*/ GIMT_Encode4(51680), // Rule ID 2488 //
18431 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18432 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18433 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18434 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
18435 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
18436 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
18437 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
18438 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18439 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18440 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
18441 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18442 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
18443 // MIs[2] Operand 1
18444 // No operand predicates
18445 GIM_CheckIsSafeToFold, /*NumInsns*/2,
18446 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 619:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)) => (RSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
18447 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18448 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
18449 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18450 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18451 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18452 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18453 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18454 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18455 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
18456 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18457 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18458 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18459 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18460 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNv4i32_shift),
18461 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18462 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18463 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
18464 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
18465 GIR_RootConstrainSelectedInstOperands,
18466 // GIR_Coverage, 2488,
18467 GIR_EraseRootFromParent_Done,
18468 // Label 1060: @51680
18469 GIM_Try, /*On fail goto*//*Label 1061*/ GIMT_Encode4(51803), // Rule ID 5907 //
18470 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18471 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18472 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18473 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
18474 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
18475 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshrn),
18476 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
18477 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18478 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18479 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
18480 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18481 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
18482 // MIs[2] Operand 1
18483 // No operand predicates
18484 GIM_CheckIsSafeToFold, /*NumInsns*/2,
18485 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 654:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)) => (SQRSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
18486 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18487 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
18488 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18489 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18490 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18491 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18492 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18493 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18494 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
18495 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18496 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18497 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18498 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18499 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNv4i32_shift),
18500 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18501 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18502 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
18503 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
18504 GIR_RootConstrainSelectedInstOperands,
18505 // GIR_Coverage, 5907,
18506 GIR_EraseRootFromParent_Done,
18507 // Label 1061: @51803
18508 GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(51926), // Rule ID 5910 //
18509 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18510 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18511 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18512 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
18513 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
18514 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshrun),
18515 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
18516 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18517 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18518 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
18519 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18520 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
18521 // MIs[2] Operand 1
18522 // No operand predicates
18523 GIM_CheckIsSafeToFold, /*NumInsns*/2,
18524 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 655:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)) => (SQRSHRUNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
18525 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18526 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
18527 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18528 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18529 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18530 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18531 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18532 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18533 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
18534 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18535 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18536 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18537 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18538 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNv4i32_shift),
18539 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18540 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18541 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
18542 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
18543 GIR_RootConstrainSelectedInstOperands,
18544 // GIR_Coverage, 5910,
18545 GIR_EraseRootFromParent_Done,
18546 // Label 1062: @51926
18547 GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(52049), // Rule ID 5913 //
18548 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18549 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18550 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18551 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
18552 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
18553 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshrn),
18554 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
18555 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18556 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18557 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
18558 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18559 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
18560 // MIs[2] Operand 1
18561 // No operand predicates
18562 GIM_CheckIsSafeToFold, /*NumInsns*/2,
18563 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 658:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)) => (SQSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
18564 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18565 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
18566 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18567 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18568 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18569 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18570 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18571 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18572 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
18573 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18574 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18575 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18576 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18577 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNv4i32_shift),
18578 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18579 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18580 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
18581 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
18582 GIR_RootConstrainSelectedInstOperands,
18583 // GIR_Coverage, 5913,
18584 GIR_EraseRootFromParent_Done,
18585 // Label 1063: @52049
18586 GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(52172), // Rule ID 5916 //
18587 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18588 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18589 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18590 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
18591 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
18592 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshrun),
18593 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
18594 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18595 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18596 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
18597 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18598 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
18599 // MIs[2] Operand 1
18600 // No operand predicates
18601 GIM_CheckIsSafeToFold, /*NumInsns*/2,
18602 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 659:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)) => (SQSHRUNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
18603 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18604 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
18605 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18606 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18607 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18608 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18609 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18610 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18611 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
18612 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18613 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18614 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18615 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18616 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNv4i32_shift),
18617 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18618 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
18620 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
18621 GIR_RootConstrainSelectedInstOperands,
18622 // GIR_Coverage, 5916,
18623 GIR_EraseRootFromParent_Done,
18624 // Label 1064: @52172
18625 GIM_Try, /*On fail goto*//*Label 1065*/ GIMT_Encode4(52295), // Rule ID 5920 //
18626 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18627 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18628 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18629 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
18630 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
18631 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshrn),
18632 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
18633 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18634 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18635 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
18636 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18637 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
18638 // MIs[2] Operand 1
18639 // No operand predicates
18640 GIM_CheckIsSafeToFold, /*NumInsns*/2,
18641 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 703:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)) => (UQRSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
18642 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18643 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
18644 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18645 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18646 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18647 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18648 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18649 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18650 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
18651 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18652 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18653 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18654 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18655 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNv4i32_shift),
18656 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18657 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
18659 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
18660 GIR_RootConstrainSelectedInstOperands,
18661 // GIR_Coverage, 5920,
18662 GIR_EraseRootFromParent_Done,
18663 // Label 1065: @52295
18664 GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(52418), // Rule ID 5923 //
18665 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18666 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18667 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18668 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
18669 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
18670 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshrn),
18671 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
18672 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18673 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18674 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
18675 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18676 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
18677 // MIs[2] Operand 1
18678 // No operand predicates
18679 GIM_CheckIsSafeToFold, /*NumInsns*/2,
18680 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 705:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)) => (UQSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
18681 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18682 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
18683 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18684 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18685 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18686 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18687 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18688 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18689 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
18690 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18691 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18692 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18693 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18694 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNv4i32_shift),
18695 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18696 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18697 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
18698 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
18699 GIR_RootConstrainSelectedInstOperands,
18700 // GIR_Coverage, 5923,
18701 GIR_EraseRootFromParent_Done,
18702 // Label 1066: @52418
18703 GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(52541), // Rule ID 5903 //
18704 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18705 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18706 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18707 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
18708 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
18709 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
18710 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VASHR),
18711 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
18712 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18713 // MIs[2] imm
18714 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
18715 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18716 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
18717 // MIs[3] Operand 1
18718 // No operand predicates
18719 GIM_CheckIsSafeToFold, /*NumInsns*/3,
18720 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm))) => (SHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
18721 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18722 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
18723 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18724 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18725 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18726 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18727 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18728 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18729 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
18730 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18731 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18732 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18733 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18734 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv4i32_shift),
18735 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18736 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18737 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
18738 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm
18739 GIR_RootConstrainSelectedInstOperands,
18740 // GIR_Coverage, 5903,
18741 GIR_EraseRootFromParent_Done,
18742 // Label 1067: @52541
18743 GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(52661), // Rule ID 5941 //
18744 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18745 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18746 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
18747 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
18748 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
18749 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
18750 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
18751 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18752 // MIs[2] imm
18753 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
18754 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18755 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
18756 // MIs[3] Operand 1
18757 // No operand predicates
18758 GIM_CheckIsSafeToFold, /*NumInsns*/3,
18759 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm))) => (SHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
18760 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18761 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
18762 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18763 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18764 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18765 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18766 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18767 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18768 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
18769 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18770 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18771 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18772 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18773 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv4i32_shift),
18774 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18775 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18776 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
18777 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm
18778 GIR_RootConstrainSelectedInstOperands,
18779 // GIR_Coverage, 5941,
18780 GIR_EraseRootFromParent_Done,
18781 // Label 1068: @52661
18782 GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(52778), // Rule ID 2421 //
18783 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18784 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18785 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18786 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
18787 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
18788 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addhn),
18789 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
18790 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
18791 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18792 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18793 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18794 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 551:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)) => (ADDHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
18795 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18796 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
18797 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18798 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18799 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18800 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18801 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18802 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18803 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
18804 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18805 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18806 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18807 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18808 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv2i64_v4i32),
18809 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18810 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18811 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
18812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
18813 GIR_RootConstrainSelectedInstOperands,
18814 // GIR_Coverage, 2421,
18815 GIR_EraseRootFromParent_Done,
18816 // Label 1069: @52778
18817 GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(52895), // Rule ID 4996 //
18818 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18819 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18820 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18821 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
18822 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
18823 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_subhn),
18824 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
18825 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
18826 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18827 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18828 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18829 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 676:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)) => (SUBHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
18830 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18831 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
18832 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18833 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18834 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18835 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18836 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18837 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18838 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
18839 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18840 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18841 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18842 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18843 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv2i64_v4i32),
18844 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18845 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18846 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
18847 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
18848 GIR_RootConstrainSelectedInstOperands,
18849 // GIR_Coverage, 4996,
18850 GIR_EraseRootFromParent_Done,
18851 // Label 1070: @52895
18852 GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(53012), // Rule ID 4999 //
18853 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18854 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18855 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18856 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
18857 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
18858 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_raddhn),
18859 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
18860 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
18861 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18862 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18863 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18864 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 618:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)) => (RADDHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
18865 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18866 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
18867 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18868 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18869 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18870 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18871 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18872 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18873 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
18874 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18875 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18876 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18877 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18878 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv2i64_v4i32),
18879 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18880 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
18882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
18883 GIR_RootConstrainSelectedInstOperands,
18884 // GIR_Coverage, 4999,
18885 GIR_EraseRootFromParent_Done,
18886 // Label 1071: @53012
18887 GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(53129), // Rule ID 5002 //
18888 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18889 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18890 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18891 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
18892 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
18893 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rsubhn),
18894 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
18895 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
18896 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18897 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18898 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18899 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 620:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)) => (RSUBHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
18900 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18901 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
18902 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18903 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18904 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18905 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18906 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18907 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18908 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
18909 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18910 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18911 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18912 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18913 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNv2i64_v4i32),
18914 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18915 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18916 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
18917 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
18918 GIR_RootConstrainSelectedInstOperands,
18919 // GIR_Coverage, 5002,
18920 GIR_EraseRootFromParent_Done,
18921 // Label 1072: @53129
18922 GIM_Try, /*On fail goto*//*Label 1073*/ GIMT_Encode4(53233), // Rule ID 2416 //
18923 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18924 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18925 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18926 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
18927 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
18928 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqxtn),
18929 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
18930 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18931 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18932 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 661:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)) => (SQXTNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn)
18933 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18934 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
18935 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18936 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18937 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18938 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18939 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18940 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18941 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
18942 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18943 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18944 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18945 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18946 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNv4i32),
18947 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18948 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
18950 GIR_RootConstrainSelectedInstOperands,
18951 // GIR_Coverage, 2416,
18952 GIR_EraseRootFromParent_Done,
18953 // Label 1073: @53233
18954 GIM_Try, /*On fail goto*//*Label 1074*/ GIMT_Encode4(53337), // Rule ID 2417 //
18955 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18956 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18957 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18958 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
18959 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
18960 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtxn),
18961 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
18962 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18963 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18964 // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rd, (intrinsic_wo_chain:{ *:[v2f32] } 574:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)) => (FCVTXNv4f32:{ *:[v4f32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rn)
18965 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18966 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
18967 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18968 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18969 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18970 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
18971 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18972 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
18973 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
18974 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
18975 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
18976 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
18977 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
18978 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTXNv4f32),
18979 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18980 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18981 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
18982 GIR_RootConstrainSelectedInstOperands,
18983 // GIR_Coverage, 2417,
18984 GIR_EraseRootFromParent_Done,
18985 // Label 1074: @53337
18986 GIM_Try, /*On fail goto*//*Label 1075*/ GIMT_Encode4(53441), // Rule ID 4605 //
18987 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18988 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
18989 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18990 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
18991 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
18992 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqxtun),
18993 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
18994 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
18995 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18996 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 662:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)) => (SQXTUNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn)
18997 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
18998 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
18999 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19000 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19001 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19002 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19003 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19004 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19005 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19006 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19007 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19008 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19009 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19010 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNv4i32),
19011 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19012 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
19014 GIR_RootConstrainSelectedInstOperands,
19015 // GIR_Coverage, 4605,
19016 GIR_EraseRootFromParent_Done,
19017 // Label 1075: @53441
19018 GIM_Try, /*On fail goto*//*Label 1076*/ GIMT_Encode4(53545), // Rule ID 4608 //
19019 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19020 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19021 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19022 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
19023 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
19024 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqxtn),
19025 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
19026 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19027 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19028 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 707:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)) => (UQXTNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn)
19029 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19030 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19031 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19032 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19033 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19034 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19035 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19036 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19037 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19038 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19039 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19040 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19041 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19042 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNv4i32),
19043 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19044 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19045 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
19046 GIR_RootConstrainSelectedInstOperands,
19047 // GIR_Coverage, 4608,
19048 GIR_EraseRootFromParent_Done,
19049 // Label 1076: @53545
19050 GIM_Try, /*On fail goto*//*Label 1077*/ GIMT_Encode4(53601), // Rule ID 5168 //
19051 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19052 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
19053 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
19054 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19055 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
19056 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
19057 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
19058 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19059 GIM_CheckIsSafeToFold, /*NumInsns*/2,
19060 // (concat_vectors:{ *:[v4i32] } (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Vn), (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Vm)) => (UZP1v4i32:{ *:[v4i32] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
19061 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i32),
19062 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19063 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
19064 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
19065 GIR_RootConstrainSelectedInstOperands,
19066 // GIR_Coverage, 5168,
19067 GIR_EraseRootFromParent_Done,
19068 // Label 1077: @53601
19069 GIM_Try, /*On fail goto*//*Label 1078*/ GIMT_Encode4(53667), // Rule ID 5412 //
19070 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19071 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19072 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
19073 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
19074 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19075 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }) => (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] })
19076 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19077 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
19078 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19079 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
19080 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19081 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
19082 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19083 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
19084 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19085 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
19086 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19087 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19088 // GIR_Coverage, 5412,
19089 GIR_EraseRootFromParent_Done,
19090 // Label 1078: @53667
19091 GIM_Try, /*On fail goto*//*Label 1079*/ GIMT_Encode4(53733), // Rule ID 5415 //
19092 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19093 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19094 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
19095 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
19096 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19097 // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rn, immAllZerosV:{ *:[v2f32] }) => (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v2f32] }:$Rn), dsub:{ *:[i32] })
19098 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19099 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
19100 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19101 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
19102 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19103 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
19104 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19105 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
19106 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19107 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
19108 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19109 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19110 // GIR_Coverage, 5415,
19111 GIR_EraseRootFromParent_Done,
19112 // Label 1079: @53733
19113 GIM_Try, /*On fail goto*//*Label 1080*/ GIMT_Encode4(53826), // Rule ID 4574 //
19114 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19115 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19116 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
19117 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
19118 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19119 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19120 // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rd, (fpround:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn)) => (FCVTNv4i32:{ *:[v4f32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rn)
19121 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19122 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19123 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19124 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19125 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19126 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19127 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19128 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19129 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19130 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19131 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19132 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19133 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19134 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i32),
19135 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19136 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
19138 GIR_RootConstrainSelectedInstOperands,
19139 // GIR_Coverage, 4574,
19140 GIR_EraseRootFromParent_Done,
19141 // Label 1080: @53826
19142 GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(53922), // Rule ID 4611 //
19143 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19144 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19145 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19146 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
19147 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
19148 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19149 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19150 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn)) => (XTNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn)
19151 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19152 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19153 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19154 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19155 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19156 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19157 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19158 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19159 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19160 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19161 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19162 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19163 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19164 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XTNv4i32),
19165 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19166 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19167 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
19168 GIR_RootConstrainSelectedInstOperands,
19169 // GIR_Coverage, 4611,
19170 GIR_EraseRootFromParent_Done,
19171 // Label 1081: @53922
19172 GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(53984), // Rule ID 5413 //
19173 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19174 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19175 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
19176 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19177 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rn, (undef:{ *:[v2i32] })) => (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] })
19178 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
19179 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19180 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19181 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19182 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19183 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19184 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19185 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
19186 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
19187 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19188 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19189 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19190 // GIR_Coverage, 5413,
19191 GIR_EraseRootFromParent_Done,
19192 // Label 1082: @53984
19193 GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(54046), // Rule ID 5416 //
19194 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19195 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19196 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
19197 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19198 // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rn, (undef:{ *:[v2f32] })) => (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] })
19199 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
19200 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19201 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19202 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19203 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19204 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19205 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19206 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
19207 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
19208 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19209 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19210 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19211 // GIR_Coverage, 5416,
19212 GIR_EraseRootFromParent_Done,
19213 // Label 1083: @54046
19214 GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(54180), // Rule ID 5411 //
19215 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19216 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19217 // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) => (INSvi64lane:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
19218 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19219 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19220 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
19221 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
19222 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19223 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19224 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
19225 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19226 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19227 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
19228 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19229 GIR_AddImm8, /*InsnID*/3, /*Imm*/2,
19230 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19231 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19232 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19233 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19234 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19235 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19236 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19237 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19238 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19239 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19240 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19241 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19242 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19243 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19244 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
19245 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19246 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19247 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19248 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
19249 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
19250 GIR_RootConstrainSelectedInstOperands,
19251 // GIR_Coverage, 5411,
19252 GIR_EraseRootFromParent_Done,
19253 // Label 1084: @54180
19254 GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(54314), // Rule ID 5414 //
19255 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19256 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19257 // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn) => (INSvi64lane:{ *:[v4f32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
19258 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19259 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19260 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
19261 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
19262 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19263 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19264 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
19265 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19266 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19267 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
19268 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19269 GIR_AddImm8, /*InsnID*/3, /*Imm*/2,
19270 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19271 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19272 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19273 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19274 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19275 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19276 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19277 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19278 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19279 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19280 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19281 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19282 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19283 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19284 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
19285 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19286 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19287 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19288 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
19289 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
19290 GIR_RootConstrainSelectedInstOperands,
19291 // GIR_Coverage, 5414,
19292 GIR_EraseRootFromParent_Done,
19293 // Label 1085: @54314
19294 GIM_Reject,
19295 // Label 1055: @54315
19296 GIM_Reject,
19297 // Label 1038: @54316
19298 GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(57823),
19299 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
19300 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
19301 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19302 GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(54453), // Rule ID 5067 //
19303 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19304 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19305 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
19306 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
19307 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
19308 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
19309 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
19310 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
19311 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ADD),
19312 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
19313 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
19314 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19315 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19316 // MIs[2] Operand 2
19317 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
19318 GIM_CheckIsSafeToFold, /*NumInsns*/3,
19319 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] }))) => (ADDHNv4i32_v8i16:{ *:[v8i16] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
19320 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19321 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
19322 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19323 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
19324 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19325 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19326 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19327 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19328 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv4i32_v8i16),
19329 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19330 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19331 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
19332 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
19333 GIR_RootConstrainSelectedInstOperands,
19334 // GIR_Coverage, 5067,
19335 GIR_EraseRootFromParent_Done,
19336 // Label 1087: @54453
19337 GIM_Try, /*On fail goto*//*Label 1088*/ GIMT_Encode4(54575), // Rule ID 5073 //
19338 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19339 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19340 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
19341 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
19342 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
19343 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
19344 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
19345 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
19346 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SUB),
19347 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
19348 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
19349 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19350 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19351 // MIs[2] Operand 2
19352 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
19353 GIM_CheckIsSafeToFold, /*NumInsns*/3,
19354 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] }))) => (SUBHNv4i32_v8i16:{ *:[v8i16] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
19355 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19356 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
19357 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19358 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
19359 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19360 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19361 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19362 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19363 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv4i32_v8i16),
19364 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19365 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
19367 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
19368 GIR_RootConstrainSelectedInstOperands,
19369 // GIR_Coverage, 5073,
19370 GIR_EraseRootFromParent_Done,
19371 // Label 1088: @54575
19372 GIM_Try, /*On fail goto*//*Label 1089*/ GIMT_Encode4(54677), // Rule ID 5234 //
19373 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19374 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
19375 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
19376 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
19377 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
19378 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
19379 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19380 // MIs[2] Operand 2
19381 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
19382 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
19383 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC),
19384 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
19385 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
19386 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_VLSHR),
19387 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
19388 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19389 // MIs[4] Operand 2
19390 GIM_CheckLiteralInt, /*MI*/4, /*Op*/2, GIMT_Encode8(16),
19391 GIM_CheckIsSafeToFold, /*NumInsns*/4,
19392 // (concat_vectors:{ *:[v8i16] } (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, 16:{ *:[i32] })), (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vm, 16:{ *:[i32] }))) => (UZP2v8i16:{ *:[v8i16] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
19393 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
19394 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
19396 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Vm
19397 GIR_RootConstrainSelectedInstOperands,
19398 // GIR_Coverage, 5234,
19399 GIR_EraseRootFromParent_Done,
19400 // Label 1089: @54677
19401 GIM_Try, /*On fail goto*//*Label 1090*/ GIMT_Encode4(54806), // Rule ID 5934 //
19402 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19403 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19404 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
19405 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
19406 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
19407 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
19408 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19409 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19410 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 16,
19411 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19412 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Vd, (intrinsic_wo_chain:{ *:[v4i16] } 619:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vn, 16:{ *:[i32] })) => (RADDHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Vd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Vn, (MOVIv2d_ns:{ *:[v4i32] } 0:{ *:[i32] }))
19413 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19414 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19415 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
19416 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
19417 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19418 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
19419 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
19420 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19421 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19422 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19423 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19424 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19425 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19426 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vd
19427 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19428 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19429 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19430 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19431 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv4i32_v8i16),
19432 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19433 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
19435 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
19436 GIR_RootConstrainSelectedInstOperands,
19437 // GIR_Coverage, 5934,
19438 GIR_EraseRootFromParent_Done,
19439 // Label 1090: @54806
19440 GIM_Try, /*On fail goto*//*Label 1091*/ GIMT_Encode4(54929), // Rule ID 2486 //
19441 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19442 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19443 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19444 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
19445 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
19446 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
19447 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
19448 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19449 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19450 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
19451 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
19452 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
19453 // MIs[2] Operand 1
19454 // No operand predicates
19455 GIM_CheckIsSafeToFold, /*NumInsns*/2,
19456 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 619:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)) => (RSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
19457 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19458 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19459 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19460 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19461 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19462 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19463 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19464 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19465 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19466 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19467 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19468 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19469 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19470 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNv8i16_shift),
19471 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19472 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
19474 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
19475 GIR_RootConstrainSelectedInstOperands,
19476 // GIR_Coverage, 2486,
19477 GIR_EraseRootFromParent_Done,
19478 // Label 1091: @54929
19479 GIM_Try, /*On fail goto*//*Label 1092*/ GIMT_Encode4(55052), // Rule ID 5906 //
19480 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19481 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19482 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19483 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
19484 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
19485 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshrn),
19486 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
19487 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19488 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19489 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
19490 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
19491 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
19492 // MIs[2] Operand 1
19493 // No operand predicates
19494 GIM_CheckIsSafeToFold, /*NumInsns*/2,
19495 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 654:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)) => (SQRSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
19496 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19497 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19498 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19499 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19500 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19501 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19502 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19503 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19504 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19505 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19506 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19507 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19508 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19509 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNv8i16_shift),
19510 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19511 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19512 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
19513 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
19514 GIR_RootConstrainSelectedInstOperands,
19515 // GIR_Coverage, 5906,
19516 GIR_EraseRootFromParent_Done,
19517 // Label 1092: @55052
19518 GIM_Try, /*On fail goto*//*Label 1093*/ GIMT_Encode4(55175), // Rule ID 5909 //
19519 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19520 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19521 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19522 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
19523 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
19524 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshrun),
19525 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
19526 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19527 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19528 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
19529 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
19530 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
19531 // MIs[2] Operand 1
19532 // No operand predicates
19533 GIM_CheckIsSafeToFold, /*NumInsns*/2,
19534 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 655:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)) => (SQRSHRUNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
19535 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19536 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19537 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19538 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19539 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19540 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19541 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19542 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19543 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19544 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19545 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19546 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19547 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19548 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNv8i16_shift),
19549 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19550 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19551 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
19552 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
19553 GIR_RootConstrainSelectedInstOperands,
19554 // GIR_Coverage, 5909,
19555 GIR_EraseRootFromParent_Done,
19556 // Label 1093: @55175
19557 GIM_Try, /*On fail goto*//*Label 1094*/ GIMT_Encode4(55298), // Rule ID 5912 //
19558 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19559 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19560 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19561 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
19562 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
19563 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshrn),
19564 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
19565 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19566 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19567 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
19568 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
19569 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
19570 // MIs[2] Operand 1
19571 // No operand predicates
19572 GIM_CheckIsSafeToFold, /*NumInsns*/2,
19573 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 658:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)) => (SQSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
19574 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19575 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19576 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19577 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19578 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19579 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19580 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19581 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19582 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19583 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19584 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19585 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19586 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19587 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNv8i16_shift),
19588 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19589 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19590 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
19591 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
19592 GIR_RootConstrainSelectedInstOperands,
19593 // GIR_Coverage, 5912,
19594 GIR_EraseRootFromParent_Done,
19595 // Label 1094: @55298
19596 GIM_Try, /*On fail goto*//*Label 1095*/ GIMT_Encode4(55421), // Rule ID 5915 //
19597 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19598 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19599 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19600 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
19601 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
19602 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshrun),
19603 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
19604 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19605 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19606 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
19607 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
19608 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
19609 // MIs[2] Operand 1
19610 // No operand predicates
19611 GIM_CheckIsSafeToFold, /*NumInsns*/2,
19612 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 659:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)) => (SQSHRUNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
19613 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19614 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19615 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19616 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19617 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19618 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19619 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19620 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19621 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19622 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19623 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19624 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19625 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19626 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNv8i16_shift),
19627 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19628 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19629 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
19630 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
19631 GIR_RootConstrainSelectedInstOperands,
19632 // GIR_Coverage, 5915,
19633 GIR_EraseRootFromParent_Done,
19634 // Label 1095: @55421
19635 GIM_Try, /*On fail goto*//*Label 1096*/ GIMT_Encode4(55544), // Rule ID 5919 //
19636 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19637 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19638 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19639 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
19640 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
19641 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshrn),
19642 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
19643 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19644 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19645 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
19646 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
19647 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
19648 // MIs[2] Operand 1
19649 // No operand predicates
19650 GIM_CheckIsSafeToFold, /*NumInsns*/2,
19651 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 703:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)) => (UQRSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
19652 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19653 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19654 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19655 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19656 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19657 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19658 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19659 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19660 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19661 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19662 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19663 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19664 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19665 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNv8i16_shift),
19666 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19667 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19668 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
19669 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
19670 GIR_RootConstrainSelectedInstOperands,
19671 // GIR_Coverage, 5919,
19672 GIR_EraseRootFromParent_Done,
19673 // Label 1096: @55544
19674 GIM_Try, /*On fail goto*//*Label 1097*/ GIMT_Encode4(55667), // Rule ID 5922 //
19675 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19676 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19677 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19678 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
19679 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
19680 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshrn),
19681 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
19682 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19683 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19684 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
19685 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
19686 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
19687 // MIs[2] Operand 1
19688 // No operand predicates
19689 GIM_CheckIsSafeToFold, /*NumInsns*/2,
19690 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 705:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)) => (UQSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
19691 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19692 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19693 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19694 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19695 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19696 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19697 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19698 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19699 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19700 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19701 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19702 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19703 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19704 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNv8i16_shift),
19705 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19706 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19707 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
19708 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
19709 GIR_RootConstrainSelectedInstOperands,
19710 // GIR_Coverage, 5922,
19711 GIR_EraseRootFromParent_Done,
19712 // Label 1097: @55667
19713 GIM_Try, /*On fail goto*//*Label 1098*/ GIMT_Encode4(55790), // Rule ID 5902 //
19714 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19715 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19716 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19717 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
19718 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
19719 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
19720 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VASHR),
19721 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
19722 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19723 // MIs[2] imm
19724 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
19725 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
19726 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
19727 // MIs[3] Operand 1
19728 // No operand predicates
19729 GIM_CheckIsSafeToFold, /*NumInsns*/3,
19730 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm))) => (SHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
19731 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19732 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19733 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19734 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19735 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19736 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19737 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19738 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19739 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19740 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19741 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19742 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19743 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19744 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv8i16_shift),
19745 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19746 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19747 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
19748 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm
19749 GIR_RootConstrainSelectedInstOperands,
19750 // GIR_Coverage, 5902,
19751 GIR_EraseRootFromParent_Done,
19752 // Label 1098: @55790
19753 GIM_Try, /*On fail goto*//*Label 1099*/ GIMT_Encode4(55910), // Rule ID 5940 //
19754 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19755 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19756 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
19757 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
19758 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
19759 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
19760 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
19761 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19762 // MIs[2] imm
19763 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
19764 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
19765 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
19766 // MIs[3] Operand 1
19767 // No operand predicates
19768 GIM_CheckIsSafeToFold, /*NumInsns*/3,
19769 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm))) => (SHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
19770 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19771 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19772 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19773 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19774 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19775 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19776 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19777 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19778 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19779 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19780 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19781 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19782 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19783 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv8i16_shift),
19784 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19785 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
19787 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm
19788 GIR_RootConstrainSelectedInstOperands,
19789 // GIR_Coverage, 5940,
19790 GIR_EraseRootFromParent_Done,
19791 // Label 1099: @55910
19792 GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(56027), // Rule ID 2420 //
19793 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19794 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19795 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19796 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
19797 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
19798 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addhn),
19799 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
19800 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
19801 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19802 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19803 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19804 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 551:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (ADDHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
19805 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19806 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19807 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19808 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19809 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19810 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19811 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19812 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19813 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19814 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19815 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19816 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19817 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19818 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv4i32_v8i16),
19819 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19820 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19821 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
19822 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
19823 GIR_RootConstrainSelectedInstOperands,
19824 // GIR_Coverage, 2420,
19825 GIR_EraseRootFromParent_Done,
19826 // Label 1100: @56027
19827 GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(56144), // Rule ID 4995 //
19828 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19829 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19830 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19831 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
19832 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
19833 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_subhn),
19834 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
19835 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
19836 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19837 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19838 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19839 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 676:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (SUBHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
19840 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19841 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19842 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19843 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19844 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19845 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19846 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19847 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19848 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19849 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19850 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19851 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19852 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19853 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv4i32_v8i16),
19854 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19855 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
19857 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
19858 GIR_RootConstrainSelectedInstOperands,
19859 // GIR_Coverage, 4995,
19860 GIR_EraseRootFromParent_Done,
19861 // Label 1101: @56144
19862 GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(56261), // Rule ID 4998 //
19863 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19864 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19865 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19866 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
19867 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
19868 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_raddhn),
19869 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
19870 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
19871 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19872 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19873 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19874 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 618:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (RADDHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
19875 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19876 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19877 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19878 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19879 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19880 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19881 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19882 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19883 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19884 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19885 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19886 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19887 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19888 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv4i32_v8i16),
19889 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19890 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19891 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
19892 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
19893 GIR_RootConstrainSelectedInstOperands,
19894 // GIR_Coverage, 4998,
19895 GIR_EraseRootFromParent_Done,
19896 // Label 1102: @56261
19897 GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(56378), // Rule ID 5001 //
19898 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19899 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19900 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19901 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
19902 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
19903 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rsubhn),
19904 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
19905 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
19906 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19907 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19908 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19909 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 620:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)) => (RSUBHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
19910 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19911 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19912 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19913 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19914 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19915 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19916 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19917 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19918 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19919 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19920 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19921 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19922 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19923 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNv4i32_v8i16),
19924 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19925 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19926 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
19927 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
19928 GIR_RootConstrainSelectedInstOperands,
19929 // GIR_Coverage, 5001,
19930 GIR_EraseRootFromParent_Done,
19931 // Label 1103: @56378
19932 GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(56482), // Rule ID 2415 //
19933 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19934 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19935 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19936 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
19937 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
19938 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqxtn),
19939 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
19940 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19941 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19942 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 661:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (SQXTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn)
19943 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19944 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19945 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19946 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19947 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19948 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19949 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19950 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19951 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19952 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19953 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19954 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19955 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19956 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNv8i16),
19957 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19958 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19959 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
19960 GIR_RootConstrainSelectedInstOperands,
19961 // GIR_Coverage, 2415,
19962 GIR_EraseRootFromParent_Done,
19963 // Label 1104: @56482
19964 GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(56583), // Rule ID 4568 //
19965 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19966 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19967 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
19968 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
19969 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2hf),
19970 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
19971 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
19972 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19973 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 726:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)) => (FCVTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rn)
19974 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
19975 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
19976 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
19977 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19978 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19979 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
19980 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19981 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
19982 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
19983 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
19984 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
19985 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
19986 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
19987 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
19988 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19989 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
19991 GIR_RootConstrainSelectedInstOperands,
19992 // GIR_Coverage, 4568,
19993 GIR_EraseRootFromParent_Done,
19994 // Label 1105: @56583
19995 GIM_Try, /*On fail goto*//*Label 1106*/ GIMT_Encode4(56687), // Rule ID 4604 //
19996 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
19997 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
19998 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19999 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
20000 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
20001 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqxtun),
20002 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
20003 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20004 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20005 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 662:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (SQXTUNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn)
20006 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20007 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20008 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20009 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20010 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20011 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20012 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20013 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20014 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20015 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20016 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20017 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20018 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20019 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNv8i16),
20020 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20021 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20022 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
20023 GIR_RootConstrainSelectedInstOperands,
20024 // GIR_Coverage, 4604,
20025 GIR_EraseRootFromParent_Done,
20026 // Label 1106: @56687
20027 GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(56791), // Rule ID 4607 //
20028 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20029 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20030 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20031 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
20032 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
20033 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqxtn),
20034 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
20035 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20036 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20037 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 707:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (UQXTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn)
20038 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20039 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20040 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20041 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20042 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20043 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20044 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20045 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20046 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20047 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20048 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20049 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20050 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20051 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNv8i16),
20052 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20053 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
20055 GIR_RootConstrainSelectedInstOperands,
20056 // GIR_Coverage, 4607,
20057 GIR_EraseRootFromParent_Done,
20058 // Label 1107: @56791
20059 GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(56847), // Rule ID 5159 //
20060 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20061 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
20062 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
20063 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20064 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
20065 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
20066 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
20067 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20068 GIM_CheckIsSafeToFold, /*NumInsns*/2,
20069 // (concat_vectors:{ *:[v8i16] } (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Vn), (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Vm)) => (UZP1v8i16:{ *:[v8i16] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
20070 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1v8i16),
20071 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
20072 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
20073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
20074 GIR_RootConstrainSelectedInstOperands,
20075 // GIR_Coverage, 5159,
20076 GIR_EraseRootFromParent_Done,
20077 // Label 1108: @56847
20078 GIM_Try, /*On fail goto*//*Label 1109*/ GIMT_Encode4(56913), // Rule ID 5418 //
20079 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20080 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20081 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
20082 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
20083 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20084 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }) => (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v4i16] }:$Rn), dsub:{ *:[i32] })
20085 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20086 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
20087 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20088 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
20089 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20090 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
20091 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20092 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
20093 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20094 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
20095 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20096 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20097 // GIR_Coverage, 5418,
20098 GIR_EraseRootFromParent_Done,
20099 // Label 1109: @56913
20100 GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(56979), // Rule ID 5421 //
20101 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20102 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20103 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
20104 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
20105 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20106 // (concat_vectors:{ *:[v8f16] } V64:{ *:[v4f16] }:$Rn, immAllZerosV:{ *:[v4f16] }) => (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v4f16] }:$Rn), dsub:{ *:[i32] })
20107 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20108 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
20109 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20110 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
20111 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20112 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
20113 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20114 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
20115 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20116 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
20117 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20118 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20119 // GIR_Coverage, 5421,
20120 GIR_EraseRootFromParent_Done,
20121 // Label 1110: @56979
20122 GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(57045), // Rule ID 5424 //
20123 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20124 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20125 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
20126 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
20127 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20128 // (concat_vectors:{ *:[v8bf16] } V64:{ *:[v4bf16] }:$Rn, immAllZerosV:{ *:[v4bf16] }) => (SUBREG_TO_REG:{ *:[v8bf16] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v4bf16] }:$Rn), dsub:{ *:[i32] })
20129 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20130 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
20131 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20132 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
20133 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20134 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
20135 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20136 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
20137 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20138 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
20139 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20140 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20141 // GIR_Coverage, 5424,
20142 GIR_EraseRootFromParent_Done,
20143 // Label 1111: @57045
20144 GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(57138), // Rule ID 4576 //
20145 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20146 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20147 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
20148 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
20149 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20150 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20151 // (concat_vectors:{ *:[v8f16] } V64:{ *:[v4f16] }:$Rd, (fpround:{ *:[v4f16] } V128:{ *:[v4f32] }:$Rn)) => (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4f16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rn)
20152 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20153 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20154 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20155 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20156 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20157 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20158 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20159 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20160 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20161 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20162 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20163 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20164 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20165 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
20166 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20167 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20168 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
20169 GIR_RootConstrainSelectedInstOperands,
20170 // GIR_Coverage, 4576,
20171 GIR_EraseRootFromParent_Done,
20172 // Label 1112: @57138
20173 GIM_Try, /*On fail goto*//*Label 1113*/ GIMT_Encode4(57234), // Rule ID 4610 //
20174 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20175 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20176 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20177 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
20178 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
20179 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20180 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20181 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn)) => (XTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn)
20182 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20183 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20184 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20185 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20186 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20187 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20188 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20189 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20190 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20191 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20192 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20193 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20194 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20195 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XTNv8i16),
20196 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20197 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20198 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
20199 GIR_RootConstrainSelectedInstOperands,
20200 // GIR_Coverage, 4610,
20201 GIR_EraseRootFromParent_Done,
20202 // Label 1113: @57234
20203 GIM_Try, /*On fail goto*//*Label 1114*/ GIMT_Encode4(57296), // Rule ID 5419 //
20204 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20205 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20206 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
20207 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20208 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rn, (undef:{ *:[v4i16] })) => (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] })
20209 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
20210 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20211 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20212 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20213 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20214 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20215 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20216 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
20217 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
20218 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20219 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20220 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20221 // GIR_Coverage, 5419,
20222 GIR_EraseRootFromParent_Done,
20223 // Label 1114: @57296
20224 GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(57358), // Rule ID 5422 //
20225 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20226 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20227 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
20228 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20229 // (concat_vectors:{ *:[v8f16] } V64:{ *:[v4f16] }:$Rn, (undef:{ *:[v4f16] })) => (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] })
20230 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
20231 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20232 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20233 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20234 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20235 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20236 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20237 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
20238 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
20239 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20240 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20241 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20242 // GIR_Coverage, 5422,
20243 GIR_EraseRootFromParent_Done,
20244 // Label 1115: @57358
20245 GIM_Try, /*On fail goto*//*Label 1116*/ GIMT_Encode4(57420), // Rule ID 5425 //
20246 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20247 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20248 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
20249 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20250 // (concat_vectors:{ *:[v8bf16] } V64:{ *:[v4bf16] }:$Rn, (undef:{ *:[v4bf16] })) => (INSERT_SUBREG:{ *:[v8bf16] } (IMPLICIT_DEF:{ *:[v8bf16] }), V64:{ *:[v4bf16] }:$Rn, dsub:{ *:[i32] })
20251 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
20252 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20253 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20254 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20255 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20256 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20257 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20258 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
20259 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
20260 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20261 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20262 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20263 // GIR_Coverage, 5425,
20264 GIR_EraseRootFromParent_Done,
20265 // Label 1116: @57420
20266 GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(57554), // Rule ID 5417 //
20267 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20268 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20269 // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) => (INSvi64lane:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
20270 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20271 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20272 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
20273 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
20274 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20275 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20276 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
20277 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20278 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20279 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
20280 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20281 GIR_AddImm8, /*InsnID*/3, /*Imm*/2,
20282 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20283 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20284 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20285 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20286 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20287 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20288 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20289 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20290 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20291 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20292 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20293 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20294 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20295 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20296 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
20297 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20298 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20299 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
20300 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
20301 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
20302 GIR_RootConstrainSelectedInstOperands,
20303 // GIR_Coverage, 5417,
20304 GIR_EraseRootFromParent_Done,
20305 // Label 1117: @57554
20306 GIM_Try, /*On fail goto*//*Label 1118*/ GIMT_Encode4(57688), // Rule ID 5420 //
20307 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20308 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20309 // (concat_vectors:{ *:[v8f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn) => (INSvi64lane:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4f16] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
20310 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20311 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20312 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
20313 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
20314 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20315 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20316 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
20317 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20318 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20319 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
20320 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20321 GIR_AddImm8, /*InsnID*/3, /*Imm*/2,
20322 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20323 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20324 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20325 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20326 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20327 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20328 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20329 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20330 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20331 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20332 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20333 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20334 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20335 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20336 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
20337 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20338 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20339 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
20340 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
20341 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
20342 GIR_RootConstrainSelectedInstOperands,
20343 // GIR_Coverage, 5420,
20344 GIR_EraseRootFromParent_Done,
20345 // Label 1118: @57688
20346 GIM_Try, /*On fail goto*//*Label 1119*/ GIMT_Encode4(57822), // Rule ID 5423 //
20347 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20348 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20349 // (concat_vectors:{ *:[v8bf16] } V64:{ *:[v4bf16] }:$Rd, V64:{ *:[v4bf16] }:$Rn) => (INSvi64lane:{ *:[v8bf16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4bf16] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4bf16] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
20350 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20351 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20352 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
20353 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
20354 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20355 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20356 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
20357 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20358 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20359 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
20360 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20361 GIR_AddImm8, /*InsnID*/3, /*Imm*/2,
20362 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20363 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20364 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20365 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20366 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20367 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20368 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20369 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20370 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20371 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20372 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20373 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20374 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20375 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20376 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
20377 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20378 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20379 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
20380 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
20381 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
20382 GIR_RootConstrainSelectedInstOperands,
20383 // GIR_Coverage, 5423,
20384 GIR_EraseRootFromParent_Done,
20385 // Label 1119: @57822
20386 GIM_Reject,
20387 // Label 1086: @57823
20388 GIM_Reject,
20389 // Label 1039: @57824
20390 GIM_Try, /*On fail goto*//*Label 1120*/ GIMT_Encode4(60613),
20391 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
20392 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20393 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20394 GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(57961), // Rule ID 5066 //
20395 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20396 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20397 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
20398 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
20399 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
20400 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
20401 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
20402 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
20403 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ADD),
20404 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
20405 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
20406 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20407 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20408 // MIs[2] Operand 2
20409 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8),
20410 GIM_CheckIsSafeToFold, /*NumInsns*/3,
20411 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] }))) => (ADDHNv8i16_v16i8:{ *:[v16i8] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
20412 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20413 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
20414 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20415 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
20416 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20417 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20418 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20419 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20420 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv8i16_v16i8),
20421 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20422 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20423 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
20424 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
20425 GIR_RootConstrainSelectedInstOperands,
20426 // GIR_Coverage, 5066,
20427 GIR_EraseRootFromParent_Done,
20428 // Label 1121: @57961
20429 GIM_Try, /*On fail goto*//*Label 1122*/ GIMT_Encode4(58083), // Rule ID 5072 //
20430 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20431 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20432 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
20433 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
20434 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
20435 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
20436 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
20437 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
20438 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SUB),
20439 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
20440 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
20441 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20442 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20443 // MIs[2] Operand 2
20444 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8),
20445 GIM_CheckIsSafeToFold, /*NumInsns*/3,
20446 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] }))) => (SUBHNv8i16_v16i8:{ *:[v16i8] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
20447 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20448 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
20449 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20450 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
20451 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20452 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20453 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20454 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20455 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv8i16_v16i8),
20456 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20457 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20458 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
20459 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
20460 GIR_RootConstrainSelectedInstOperands,
20461 // GIR_Coverage, 5072,
20462 GIR_EraseRootFromParent_Done,
20463 // Label 1122: @58083
20464 GIM_Try, /*On fail goto*//*Label 1123*/ GIMT_Encode4(58185), // Rule ID 5233 //
20465 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20466 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
20467 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
20468 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
20469 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
20470 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
20471 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20472 // MIs[2] Operand 2
20473 GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8),
20474 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
20475 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC),
20476 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
20477 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
20478 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_VLSHR),
20479 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
20480 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20481 // MIs[4] Operand 2
20482 GIM_CheckLiteralInt, /*MI*/4, /*Op*/2, GIMT_Encode8(8),
20483 GIM_CheckIsSafeToFold, /*NumInsns*/4,
20484 // (concat_vectors:{ *:[v16i8] } (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, 8:{ *:[i32] })), (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vm, 8:{ *:[i32] }))) => (UZP2v16i8:{ *:[v16i8] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)
20485 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v16i8),
20486 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
20487 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
20488 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Vm
20489 GIR_RootConstrainSelectedInstOperands,
20490 // GIR_Coverage, 5233,
20491 GIR_EraseRootFromParent_Done,
20492 // Label 1123: @58185
20493 GIM_Try, /*On fail goto*//*Label 1124*/ GIMT_Encode4(58314), // Rule ID 5933 //
20494 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20495 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20496 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
20497 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
20498 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
20499 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
20500 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20501 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20502 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 8,
20503 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20504 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Vd, (intrinsic_wo_chain:{ *:[v8i8] } 619:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vn, 8:{ *:[i32] })) => (RADDHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Vd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Vn, (MOVIv2d_ns:{ *:[v8i16] } 0:{ *:[i32] }))
20505 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20506 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20507 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
20508 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
20509 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20510 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
20511 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
20512 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20513 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20514 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20515 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20516 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20517 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20518 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vd
20519 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20520 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20521 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20522 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20523 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv8i16_v16i8),
20524 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20525 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
20527 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
20528 GIR_RootConstrainSelectedInstOperands,
20529 // GIR_Coverage, 5933,
20530 GIR_EraseRootFromParent_Done,
20531 // Label 1124: @58314
20532 GIM_Try, /*On fail goto*//*Label 1125*/ GIMT_Encode4(58437), // Rule ID 2484 //
20533 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20534 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20535 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20536 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
20537 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
20538 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
20539 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
20540 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20541 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20542 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
20543 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
20544 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
20545 // MIs[2] Operand 1
20546 // No operand predicates
20547 GIM_CheckIsSafeToFold, /*NumInsns*/2,
20548 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 619:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)) => (RSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
20549 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20550 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20551 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20552 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20553 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20554 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20555 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20556 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20557 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20558 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20559 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20560 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20561 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20562 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNv16i8_shift),
20563 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20564 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20565 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
20566 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
20567 GIR_RootConstrainSelectedInstOperands,
20568 // GIR_Coverage, 2484,
20569 GIR_EraseRootFromParent_Done,
20570 // Label 1125: @58437
20571 GIM_Try, /*On fail goto*//*Label 1126*/ GIMT_Encode4(58560), // Rule ID 5905 //
20572 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20573 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20574 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20575 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
20576 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
20577 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshrn),
20578 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
20579 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20580 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20581 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
20582 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
20583 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
20584 // MIs[2] Operand 1
20585 // No operand predicates
20586 GIM_CheckIsSafeToFold, /*NumInsns*/2,
20587 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 654:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)) => (SQRSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
20588 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20589 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20590 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20591 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20592 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20593 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20594 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20595 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20596 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20597 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20598 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20599 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20600 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20601 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNv16i8_shift),
20602 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20603 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
20605 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
20606 GIR_RootConstrainSelectedInstOperands,
20607 // GIR_Coverage, 5905,
20608 GIR_EraseRootFromParent_Done,
20609 // Label 1126: @58560
20610 GIM_Try, /*On fail goto*//*Label 1127*/ GIMT_Encode4(58683), // Rule ID 5908 //
20611 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20612 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20613 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20614 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
20615 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
20616 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshrun),
20617 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
20618 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20619 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20620 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
20621 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
20622 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
20623 // MIs[2] Operand 1
20624 // No operand predicates
20625 GIM_CheckIsSafeToFold, /*NumInsns*/2,
20626 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 655:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)) => (SQRSHRUNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
20627 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20628 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20629 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20630 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20631 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20632 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20633 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20634 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20635 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20636 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20637 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20638 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20639 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20640 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNv16i8_shift),
20641 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20642 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20643 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
20644 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
20645 GIR_RootConstrainSelectedInstOperands,
20646 // GIR_Coverage, 5908,
20647 GIR_EraseRootFromParent_Done,
20648 // Label 1127: @58683
20649 GIM_Try, /*On fail goto*//*Label 1128*/ GIMT_Encode4(58806), // Rule ID 5911 //
20650 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20651 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20652 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20653 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
20654 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
20655 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshrn),
20656 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
20657 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20658 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20659 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
20660 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
20661 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
20662 // MIs[2] Operand 1
20663 // No operand predicates
20664 GIM_CheckIsSafeToFold, /*NumInsns*/2,
20665 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 658:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)) => (SQSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
20666 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20667 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20668 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20669 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20670 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20671 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20672 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20673 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20674 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20675 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20676 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20677 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20678 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20679 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNv16i8_shift),
20680 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20681 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20682 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
20683 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
20684 GIR_RootConstrainSelectedInstOperands,
20685 // GIR_Coverage, 5911,
20686 GIR_EraseRootFromParent_Done,
20687 // Label 1128: @58806
20688 GIM_Try, /*On fail goto*//*Label 1129*/ GIMT_Encode4(58929), // Rule ID 5914 //
20689 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20690 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20691 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20692 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
20693 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
20694 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshrun),
20695 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
20696 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20697 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20698 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
20699 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
20700 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
20701 // MIs[2] Operand 1
20702 // No operand predicates
20703 GIM_CheckIsSafeToFold, /*NumInsns*/2,
20704 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 659:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)) => (SQSHRUNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
20705 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20706 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20707 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20708 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20709 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20710 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20711 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20712 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20713 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20714 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20715 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20716 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20717 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20718 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNv16i8_shift),
20719 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20720 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20721 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
20722 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
20723 GIR_RootConstrainSelectedInstOperands,
20724 // GIR_Coverage, 5914,
20725 GIR_EraseRootFromParent_Done,
20726 // Label 1129: @58929
20727 GIM_Try, /*On fail goto*//*Label 1130*/ GIMT_Encode4(59052), // Rule ID 5918 //
20728 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20729 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20730 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20731 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
20732 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
20733 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshrn),
20734 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
20735 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20736 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20737 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
20738 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
20739 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
20740 // MIs[2] Operand 1
20741 // No operand predicates
20742 GIM_CheckIsSafeToFold, /*NumInsns*/2,
20743 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 703:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)) => (UQRSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
20744 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20745 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20746 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20747 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20748 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20749 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20750 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20751 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20752 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20753 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20754 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20755 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20756 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20757 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNv16i8_shift),
20758 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20759 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20760 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
20761 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
20762 GIR_RootConstrainSelectedInstOperands,
20763 // GIR_Coverage, 5918,
20764 GIR_EraseRootFromParent_Done,
20765 // Label 1130: @59052
20766 GIM_Try, /*On fail goto*//*Label 1131*/ GIMT_Encode4(59175), // Rule ID 5921 //
20767 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20768 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20769 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20770 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
20771 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
20772 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshrn),
20773 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
20774 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20775 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20776 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
20777 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
20778 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
20779 // MIs[2] Operand 1
20780 // No operand predicates
20781 GIM_CheckIsSafeToFold, /*NumInsns*/2,
20782 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 705:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)) => (UQSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
20783 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20784 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20785 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20786 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20787 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20788 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20789 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20790 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20791 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20792 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20793 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20794 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20795 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20796 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNv16i8_shift),
20797 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20798 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
20800 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
20801 GIR_RootConstrainSelectedInstOperands,
20802 // GIR_Coverage, 5921,
20803 GIR_EraseRootFromParent_Done,
20804 // Label 1131: @59175
20805 GIM_Try, /*On fail goto*//*Label 1132*/ GIMT_Encode4(59298), // Rule ID 5901 //
20806 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20807 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20808 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20809 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
20810 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
20811 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
20812 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VASHR),
20813 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
20814 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20815 // MIs[2] imm
20816 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
20817 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
20818 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
20819 // MIs[3] Operand 1
20820 // No operand predicates
20821 GIM_CheckIsSafeToFold, /*NumInsns*/3,
20822 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm))) => (SHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
20823 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20824 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20825 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20826 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20827 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20828 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20829 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20830 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20831 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20832 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20833 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20834 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20835 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20836 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv16i8_shift),
20837 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20838 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
20840 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm
20841 GIR_RootConstrainSelectedInstOperands,
20842 // GIR_Coverage, 5901,
20843 GIR_EraseRootFromParent_Done,
20844 // Label 1132: @59298
20845 GIM_Try, /*On fail goto*//*Label 1133*/ GIMT_Encode4(59418), // Rule ID 5939 //
20846 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20847 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20848 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
20849 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
20850 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
20851 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
20852 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
20853 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20854 // MIs[2] imm
20855 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
20856 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
20857 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
20858 // MIs[3] Operand 1
20859 // No operand predicates
20860 GIM_CheckIsSafeToFold, /*NumInsns*/3,
20861 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm))) => (SHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
20862 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20863 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20864 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20865 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20866 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20867 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20868 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20869 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20870 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20871 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20872 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20873 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20874 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20875 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv16i8_shift),
20876 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20877 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
20879 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm
20880 GIR_RootConstrainSelectedInstOperands,
20881 // GIR_Coverage, 5939,
20882 GIR_EraseRootFromParent_Done,
20883 // Label 1133: @59418
20884 GIM_Try, /*On fail goto*//*Label 1134*/ GIMT_Encode4(59535), // Rule ID 2419 //
20885 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20886 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20887 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20888 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
20889 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
20890 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addhn),
20891 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
20892 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
20893 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20894 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20895 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20896 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 551:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (ADDHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
20897 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20898 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20899 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20900 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20901 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20902 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20903 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20904 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20905 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20906 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20907 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20908 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20909 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20910 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv8i16_v16i8),
20911 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20912 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20913 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
20914 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
20915 GIR_RootConstrainSelectedInstOperands,
20916 // GIR_Coverage, 2419,
20917 GIR_EraseRootFromParent_Done,
20918 // Label 1134: @59535
20919 GIM_Try, /*On fail goto*//*Label 1135*/ GIMT_Encode4(59652), // Rule ID 4994 //
20920 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20921 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20922 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20923 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
20924 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
20925 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_subhn),
20926 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
20927 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
20928 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20929 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20930 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20931 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 676:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (SUBHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
20932 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20933 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20934 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20935 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20936 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20937 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20938 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20939 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20940 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20941 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20942 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20943 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20944 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20945 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv8i16_v16i8),
20946 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20947 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20948 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
20949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
20950 GIR_RootConstrainSelectedInstOperands,
20951 // GIR_Coverage, 4994,
20952 GIR_EraseRootFromParent_Done,
20953 // Label 1135: @59652
20954 GIM_Try, /*On fail goto*//*Label 1136*/ GIMT_Encode4(59769), // Rule ID 4997 //
20955 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20956 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20957 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20958 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
20959 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
20960 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_raddhn),
20961 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
20962 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
20963 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20964 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20965 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20966 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 618:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (RADDHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
20967 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
20968 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
20969 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
20970 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20971 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20972 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
20973 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20974 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
20975 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
20976 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
20977 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
20978 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
20979 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
20980 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv8i16_v16i8),
20981 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
20982 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20983 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
20984 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
20985 GIR_RootConstrainSelectedInstOperands,
20986 // GIR_Coverage, 4997,
20987 GIR_EraseRootFromParent_Done,
20988 // Label 1136: @59769
20989 GIM_Try, /*On fail goto*//*Label 1137*/ GIMT_Encode4(59886), // Rule ID 5000 //
20990 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20991 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
20992 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20993 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
20994 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
20995 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rsubhn),
20996 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
20997 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
20998 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
20999 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
21000 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21001 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 620:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)) => (RSUBHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
21002 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
21003 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
21004 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
21005 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21006 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
21007 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
21008 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21009 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
21010 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
21011 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
21012 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
21013 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
21014 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
21015 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNv8i16_v16i8),
21016 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
21017 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21018 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
21019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
21020 GIR_RootConstrainSelectedInstOperands,
21021 // GIR_Coverage, 5000,
21022 GIR_EraseRootFromParent_Done,
21023 // Label 1137: @59886
21024 GIM_Try, /*On fail goto*//*Label 1138*/ GIMT_Encode4(59990), // Rule ID 2414 //
21025 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21026 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21027 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
21028 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
21029 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
21030 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqxtn),
21031 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
21032 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
21033 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21034 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 661:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (SQXTNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn)
21035 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
21036 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
21037 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
21038 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21039 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
21040 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
21041 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21042 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
21043 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
21044 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
21045 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
21046 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
21047 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
21048 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNv16i8),
21049 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
21050 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21051 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
21052 GIR_RootConstrainSelectedInstOperands,
21053 // GIR_Coverage, 2414,
21054 GIR_EraseRootFromParent_Done,
21055 // Label 1138: @59990
21056 GIM_Try, /*On fail goto*//*Label 1139*/ GIMT_Encode4(60094), // Rule ID 4603 //
21057 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21058 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21059 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
21060 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
21061 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
21062 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqxtun),
21063 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
21064 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
21065 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21066 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 662:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (SQXTUNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn)
21067 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
21068 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
21069 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
21070 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21071 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
21072 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
21073 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21074 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
21075 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
21076 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
21077 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
21078 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
21079 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
21080 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNv16i8),
21081 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
21082 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21083 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
21084 GIR_RootConstrainSelectedInstOperands,
21085 // GIR_Coverage, 4603,
21086 GIR_EraseRootFromParent_Done,
21087 // Label 1139: @60094
21088 GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(60198), // Rule ID 4606 //
21089 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21090 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21091 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
21092 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
21093 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
21094 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqxtn),
21095 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
21096 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
21097 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21098 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 707:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (UQXTNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn)
21099 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
21100 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
21101 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
21102 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21103 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
21104 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
21105 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21106 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
21107 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
21108 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
21109 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
21110 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
21111 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
21112 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNv16i8),
21113 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
21114 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
21116 GIR_RootConstrainSelectedInstOperands,
21117 // GIR_Coverage, 4606,
21118 GIR_EraseRootFromParent_Done,
21119 // Label 1140: @60198
21120 GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(60254), // Rule ID 5150 //
21121 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21122 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
21123 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
21124 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
21125 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
21126 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
21127 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
21128 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
21129 GIM_CheckIsSafeToFold, /*NumInsns*/2,
21130 // (concat_vectors:{ *:[v16i8] } (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Vn), (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Vm)) => (UZP1v16i8:{ *:[v16i8] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)
21131 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1v16i8),
21132 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
21133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
21134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
21135 GIR_RootConstrainSelectedInstOperands,
21136 // GIR_Coverage, 5150,
21137 GIR_EraseRootFromParent_Done,
21138 // Label 1141: @60254
21139 GIM_Try, /*On fail goto*//*Label 1142*/ GIMT_Encode4(60320), // Rule ID 5427 //
21140 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21141 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
21142 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
21143 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
21144 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21145 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }) => (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v8i8] }:$Rn), dsub:{ *:[i32] })
21146 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21147 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
21148 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21149 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
21150 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21151 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
21152 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
21153 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
21154 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21155 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
21156 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
21157 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
21158 // GIR_Coverage, 5427,
21159 GIR_EraseRootFromParent_Done,
21160 // Label 1142: @60320
21161 GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(60416), // Rule ID 4609 //
21162 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21163 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21164 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
21165 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
21166 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
21167 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
21168 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21169 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn)) => (XTNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn)
21170 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
21171 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
21172 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
21173 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21174 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
21175 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
21176 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21177 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
21178 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
21179 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
21180 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
21181 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
21182 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
21183 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XTNv16i8),
21184 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
21185 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21186 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
21187 GIR_RootConstrainSelectedInstOperands,
21188 // GIR_Coverage, 4609,
21189 GIR_EraseRootFromParent_Done,
21190 // Label 1143: @60416
21191 GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(60478), // Rule ID 5428 //
21192 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21193 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
21194 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
21195 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21196 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rn, (undef:{ *:[v8i8] })) => (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] })
21197 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
21198 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
21199 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21200 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21201 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
21202 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
21203 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21204 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
21205 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
21206 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
21207 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
21208 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
21209 // GIR_Coverage, 5428,
21210 GIR_EraseRootFromParent_Done,
21211 // Label 1144: @60478
21212 GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(60612), // Rule ID 5426 //
21213 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21214 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21215 // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) => (INSvi64lane:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
21216 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
21217 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
21218 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
21219 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
21220 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
21221 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21222 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
21223 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
21224 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21225 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
21226 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
21227 GIR_AddImm8, /*InsnID*/3, /*Imm*/2,
21228 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
21229 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
21230 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
21231 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
21232 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21233 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
21234 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
21235 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21236 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
21237 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
21238 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
21239 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
21240 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
21241 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
21242 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
21243 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
21244 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21245 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
21246 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
21247 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
21248 GIR_RootConstrainSelectedInstOperands,
21249 // GIR_Coverage, 5426,
21250 GIR_EraseRootFromParent_Done,
21251 // Label 1145: @60612
21252 GIM_Reject,
21253 // Label 1120: @60613
21254 GIM_Reject,
21255 // Label 1040: @60614
21256 GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(60639), // Rule ID 8752 //
21257 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
21258 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1,
21259 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
21260 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
21261 // (concat_vectors:{ *:[nxv2i1] } nxv1i1:{ *:[nxv1i1] }:$p1, nxv1i1:{ *:[nxv1i1] }:$p2) => (UZP1_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv1i1] }:$p1, ?:{ *:[nxv1i1] }:$p2)
21262 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_D),
21263 GIR_RootConstrainSelectedInstOperands,
21264 // GIR_Coverage, 8752,
21265 GIR_Done,
21266 // Label 1146: @60639
21267 GIM_Reject,
21268 // Label 1041: @60640
21269 GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(60665), // Rule ID 8753 //
21270 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
21271 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
21272 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
21273 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
21274 // (concat_vectors:{ *:[nxv4i1] } nxv2i1:{ *:[nxv2i1] }:$p1, nxv2i1:{ *:[nxv2i1] }:$p2) => (UZP1_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv2i1] }:$p1, ?:{ *:[nxv2i1] }:$p2)
21275 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_S),
21276 GIR_RootConstrainSelectedInstOperands,
21277 // GIR_Coverage, 8753,
21278 GIR_Done,
21279 // Label 1147: @60665
21280 GIM_Reject,
21281 // Label 1042: @60666
21282 GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(60712),
21283 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
21284 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
21285 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
21286 GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(60696), // Rule ID 8756 //
21287 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
21288 // (concat_vectors:{ *:[nxv4f16] } nxv2f16:{ *:[nxv2f16] }:$v1, nxv2f16:{ *:[nxv2f16] }:$v2) => (UZP1_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv2f16] }:$v1, ?:{ *:[nxv2f16] }:$v2)
21289 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_S),
21290 GIR_RootConstrainSelectedInstOperands,
21291 // GIR_Coverage, 8756,
21292 GIR_Done,
21293 // Label 1149: @60696
21294 GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(60711), // Rule ID 8759 //
21295 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
21296 // (concat_vectors:{ *:[nxv4bf16] } nxv2bf16:{ *:[nxv2bf16] }:$v1, nxv2bf16:{ *:[nxv2bf16] }:$v2) => (UZP1_ZZZ_S:{ *:[nxv4bf16] } ?:{ *:[nxv2bf16] }:$v1, ?:{ *:[nxv2bf16] }:$v2)
21297 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_S),
21298 GIR_RootConstrainSelectedInstOperands,
21299 // GIR_Coverage, 8759,
21300 GIR_Done,
21301 // Label 1150: @60711
21302 GIM_Reject,
21303 // Label 1148: @60712
21304 GIM_Reject,
21305 // Label 1043: @60713
21306 GIM_Try, /*On fail goto*//*Label 1151*/ GIMT_Encode4(60738), // Rule ID 8758 //
21307 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
21308 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
21309 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
21310 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
21311 // (concat_vectors:{ *:[nxv4f32] } nxv2f32:{ *:[nxv2f32] }:$v1, nxv2f32:{ *:[nxv2f32] }:$v2) => (UZP1_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv2f32] }:$v1, ?:{ *:[nxv2f32] }:$v2)
21312 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_S),
21313 GIR_RootConstrainSelectedInstOperands,
21314 // GIR_Coverage, 8758,
21315 GIR_Done,
21316 // Label 1151: @60738
21317 GIM_Reject,
21318 // Label 1044: @60739
21319 GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(60764), // Rule ID 8754 //
21320 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
21321 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
21322 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
21323 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
21324 // (concat_vectors:{ *:[nxv8i1] } nxv4i1:{ *:[nxv4i1] }:$p1, nxv4i1:{ *:[nxv4i1] }:$p2) => (UZP1_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv4i1] }:$p1, ?:{ *:[nxv4i1] }:$p2)
21325 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_H),
21326 GIR_RootConstrainSelectedInstOperands,
21327 // GIR_Coverage, 8754,
21328 GIR_Done,
21329 // Label 1152: @60764
21330 GIM_Reject,
21331 // Label 1045: @60765
21332 GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(60811),
21333 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
21334 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
21335 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
21336 GIM_Try, /*On fail goto*//*Label 1154*/ GIMT_Encode4(60795), // Rule ID 8757 //
21337 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
21338 // (concat_vectors:{ *:[nxv8f16] } nxv4f16:{ *:[nxv4f16] }:$v1, nxv4f16:{ *:[nxv4f16] }:$v2) => (UZP1_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv4f16] }:$v1, ?:{ *:[nxv4f16] }:$v2)
21339 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_H),
21340 GIR_RootConstrainSelectedInstOperands,
21341 // GIR_Coverage, 8757,
21342 GIR_Done,
21343 // Label 1154: @60795
21344 GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(60810), // Rule ID 8760 //
21345 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
21346 // (concat_vectors:{ *:[nxv8bf16] } nxv4bf16:{ *:[nxv4bf16] }:$v1, nxv4bf16:{ *:[nxv4bf16] }:$v2) => (UZP1_ZZZ_H:{ *:[nxv8bf16] } ?:{ *:[nxv4bf16] }:$v1, ?:{ *:[nxv4bf16] }:$v2)
21347 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_H),
21348 GIR_RootConstrainSelectedInstOperands,
21349 // GIR_Coverage, 8760,
21350 GIR_Done,
21351 // Label 1155: @60810
21352 GIM_Reject,
21353 // Label 1153: @60811
21354 GIM_Reject,
21355 // Label 1046: @60812
21356 GIM_Try, /*On fail goto*//*Label 1156*/ GIMT_Encode4(60837), // Rule ID 8755 //
21357 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
21358 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
21359 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
21360 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
21361 // (concat_vectors:{ *:[nxv16i1] } nxv8i1:{ *:[nxv8i1] }:$p1, nxv8i1:{ *:[nxv8i1] }:$p2) => (UZP1_PPP_B:{ *:[nxv16i1] } ?:{ *:[nxv8i1] }:$p1, ?:{ *:[nxv8i1] }:$p2)
21362 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_B),
21363 GIR_RootConstrainSelectedInstOperands,
21364 // GIR_Coverage, 8755,
21365 GIR_Done,
21366 // Label 1156: @60837
21367 GIM_Reject,
21368 // Label 1047: @60838
21369 GIM_Reject,
21370 // Label 1035: @60839
21371 GIM_Reject,
21372 // Label 9: @60840
21373 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(24), /*)*//*default:*//*Label 1172*/ GIMT_Encode4(72595),
21374 /*GILLT_s16*//*Label 1157*/ GIMT_Encode4(60943),
21375 /*GILLT_s32*//*Label 1158*/ GIMT_Encode4(60997),
21376 /*GILLT_s64*//*Label 1159*/ GIMT_Encode4(61378),
21377 /*GILLT_s128*//*Label 1160*/ GIMT_Encode4(63589),
21378 /*GILLT_v2s32*//*Label 1161*/ GIMT_Encode4(64338),
21379 /*GILLT_v2s64*//*Label 1162*/ GIMT_Encode4(65363),
21380 /*GILLT_v4s16*//*Label 1163*/ GIMT_Encode4(66248),
21381 /*GILLT_v4s32*//*Label 1164*/ GIMT_Encode4(67640),
21382 /*GILLT_v8s8*//*Label 1165*/ GIMT_Encode4(68601),
21383 /*GILLT_v8s16*//*Label 1166*/ GIMT_Encode4(69217),
21384 /*GILLT_v16s8*//*Label 1167*/ GIMT_Encode4(70513), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
21385 /*GILLT_nxv2s64*//*Label 1168*/ GIMT_Encode4(71023), GIMT_Encode4(0), GIMT_Encode4(0),
21386 /*GILLT_nxv4s32*//*Label 1169*/ GIMT_Encode4(71416), GIMT_Encode4(0),
21387 /*GILLT_nxv8s16*//*Label 1170*/ GIMT_Encode4(71809), GIMT_Encode4(0),
21388 /*GILLT_nxv16s8*//*Label 1171*/ GIMT_Encode4(72398),
21389 // Label 1157: @60943
21390 GIM_Try, /*On fail goto*//*Label 1173*/ GIMT_Encode4(60996),
21391 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
21392 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
21393 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
21394 GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(60977), // Rule ID 6312 //
21395 // (bitconvert:{ *:[f16] } FPR16:{ *:[bf16] }:$src) => FPR16:{ *:[f16] }:$src
21396 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21397 GIR_RootToRootCopy, /*OpIdx*/0, // dst
21398 GIR_RootToRootCopy, /*OpIdx*/1, // src
21399 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
21400 // GIR_Coverage, 6312,
21401 GIR_EraseRootFromParent_Done,
21402 // Label 1174: @60977
21403 GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(60995), // Rule ID 6313 //
21404 // (bitconvert:{ *:[bf16] } FPR16:{ *:[f16] }:$src) => FPR16:{ *:[bf16] }:$src
21405 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21406 GIR_RootToRootCopy, /*OpIdx*/0, // dst
21407 GIR_RootToRootCopy, /*OpIdx*/1, // src
21408 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
21409 // GIR_Coverage, 6313,
21410 GIR_EraseRootFromParent_Done,
21411 // Label 1175: @60995
21412 GIM_Reject,
21413 // Label 1173: @60996
21414 GIM_Reject,
21415 // Label 1158: @60997
21416 GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(61377),
21417 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21418 GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(61075), // Rule ID 6782 //
21419 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
21420 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21421 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
21422 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(4),
21423 GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
21424 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
21425 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
21426 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21427 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
21428 // (bitconvert:{ *:[f32] } (atomic_load:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_32>><<P:Predicate_anonymous_14592>>) => (LDRSroW:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
21429 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
21430 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
21431 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
21432 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
21433 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
21434 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
21435 GIR_RootConstrainSelectedInstOperands,
21436 // GIR_Coverage, 6782,
21437 GIR_EraseRootFromParent_Done,
21438 // Label 1177: @61075
21439 GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(61145), // Rule ID 6783 //
21440 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
21441 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21442 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
21443 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(4),
21444 GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
21445 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
21446 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
21447 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21448 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
21449 // (bitconvert:{ *:[f32] } (atomic_load:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_32>><<P:Predicate_anonymous_14592>>) => (LDRSroX:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
21450 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
21451 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
21452 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
21453 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
21454 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
21455 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
21456 GIR_RootConstrainSelectedInstOperands,
21457 // GIR_Coverage, 6783,
21458 GIR_EraseRootFromParent_Done,
21459 // Label 1178: @61145
21460 GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(61210), // Rule ID 6784 //
21461 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
21462 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21463 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
21464 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(4),
21465 GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
21466 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
21467 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
21468 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21469 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
21470 // (bitconvert:{ *:[f32] } (atomic_load:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_32>><<P:Predicate_anonymous_14592>>) => (LDRSui:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
21471 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
21472 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
21473 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
21474 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
21475 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
21476 GIR_RootConstrainSelectedInstOperands,
21477 // GIR_Coverage, 6784,
21478 GIR_EraseRootFromParent_Done,
21479 // Label 1179: @61210
21480 GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(61275), // Rule ID 6785 //
21481 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
21482 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21483 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
21484 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(4),
21485 GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
21486 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
21487 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
21488 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21489 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
21490 // (bitconvert:{ *:[f32] } (atomic_load:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_32>><<P:Predicate_anonymous_14592>>) => (LDURSi:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
21491 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
21492 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
21493 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
21494 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
21495 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
21496 GIR_RootConstrainSelectedInstOperands,
21497 // GIR_Coverage, 6785,
21498 GIR_EraseRootFromParent_Done,
21499 // Label 1180: @61275
21500 GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(61328), // Rule ID 5394 //
21501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
21502 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21503 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
21504 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
21505 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21506 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
21507 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21508 // (bitconvert:{ *:[f32] } (vector_extract:{ *:[i32] } v4i32:{ *:[v4i32] }:$src, 0:{ *:[i64] })) => (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4i32] }:$src, ssub:{ *:[i32] })
21509 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21510 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
21511 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // src
21512 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
21513 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
21514 // GIR_Coverage, 5394,
21515 GIR_EraseRootFromParent_Done,
21516 // Label 1181: @61328
21517 GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(61352), // Rule ID 6307 //
21518 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
21519 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
21520 // (bitconvert:{ *:[f32] } GPR32:{ *:[i32] }:$Xn) => (COPY_TO_REGCLASS:{ *:[f32] } GPR32:{ *:[i32] }:$Xn, FPR32:{ *:[i32] })
21521 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21522 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
21523 // GIR_Coverage, 6307,
21524 GIR_Done,
21525 // Label 1182: @61352
21526 GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(61376), // Rule ID 6308 //
21527 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
21528 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
21529 // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Xn) => (COPY_TO_REGCLASS:{ *:[i32] } FPR32:{ *:[f32] }:$Xn, GPR32:{ *:[i32] })
21530 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21531 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
21532 // GIR_Coverage, 6308,
21533 GIR_Done,
21534 // Label 1183: @61376
21535 GIM_Reject,
21536 // Label 1176: @61377
21537 GIM_Reject,
21538 // Label 1159: @61378
21539 GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(61451), // Rule ID 6786 //
21540 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
21541 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21542 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21543 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
21544 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(8),
21545 GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
21546 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
21547 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
21548 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21549 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
21550 // (bitconvert:{ *:[f64] } (atomic_load:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_64>><<P:Predicate_anonymous_14600>>) => (LDRDroW:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
21551 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
21552 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
21553 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
21554 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
21555 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
21556 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
21557 GIR_RootConstrainSelectedInstOperands,
21558 // GIR_Coverage, 6786,
21559 GIR_EraseRootFromParent_Done,
21560 // Label 1184: @61451
21561 GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(61524), // Rule ID 6787 //
21562 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
21563 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21564 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21565 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
21566 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(8),
21567 GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
21568 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
21569 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
21570 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21571 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
21572 // (bitconvert:{ *:[f64] } (atomic_load:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_64>><<P:Predicate_anonymous_14600>>) => (LDRDroX:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
21573 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
21574 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
21575 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
21576 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
21577 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
21578 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
21579 GIR_RootConstrainSelectedInstOperands,
21580 // GIR_Coverage, 6787,
21581 GIR_EraseRootFromParent_Done,
21582 // Label 1185: @61524
21583 GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(61592), // Rule ID 6788 //
21584 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
21585 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21586 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21587 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
21588 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(8),
21589 GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
21590 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
21591 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
21592 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21593 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
21594 // (bitconvert:{ *:[f64] } (atomic_load:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_64>><<P:Predicate_anonymous_14600>>) => (LDRDui:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
21595 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
21596 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
21597 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
21598 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
21599 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
21600 GIR_RootConstrainSelectedInstOperands,
21601 // GIR_Coverage, 6788,
21602 GIR_EraseRootFromParent_Done,
21603 // Label 1186: @61592
21604 GIM_Try, /*On fail goto*//*Label 1187*/ GIMT_Encode4(61660), // Rule ID 6789 //
21605 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
21606 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21607 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21608 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
21609 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(8),
21610 GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
21611 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
21612 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
21613 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21614 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
21615 // (bitconvert:{ *:[f64] } (atomic_load:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_64>><<P:Predicate_anonymous_14600>>) => (LDURDi:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
21616 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
21617 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
21618 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
21619 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
21620 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
21621 GIR_RootConstrainSelectedInstOperands,
21622 // GIR_Coverage, 6789,
21623 GIR_EraseRootFromParent_Done,
21624 // Label 1187: @61660
21625 GIM_Try, /*On fail goto*//*Label 1188*/ GIMT_Encode4(61716), // Rule ID 5396 //
21626 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
21627 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
21628 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21629 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
21630 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
21631 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21632 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
21633 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21634 // (bitconvert:{ *:[f64] } (vector_extract:{ *:[i64] } v2i64:{ *:[v2i64] }:$src, 0:{ *:[i64] })) => (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2i64] }:$src, dsub:{ *:[i32] })
21635 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21636 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
21637 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // src
21638 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
21639 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
21640 // GIR_Coverage, 5396,
21641 GIR_EraseRootFromParent_Done,
21642 // Label 1188: @61716
21643 GIM_Try, /*On fail goto*//*Label 1189*/ GIMT_Encode4(61746), // Rule ID 6282 //
21644 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
21645 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
21646 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
21647 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21648 // (bitconvert:{ *:[i64] } V64:{ *:[v8i8] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v8i8] }:$Vn, GPR64:{ *:[i32] })
21649 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21650 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
21651 // GIR_Coverage, 6282,
21652 GIR_Done,
21653 // Label 1189: @61746
21654 GIM_Try, /*On fail goto*//*Label 1190*/ GIMT_Encode4(61776), // Rule ID 6283 //
21655 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
21656 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
21657 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
21658 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21659 // (bitconvert:{ *:[i64] } V64:{ *:[v4i16] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4i16] }:$Vn, GPR64:{ *:[i32] })
21660 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21661 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
21662 // GIR_Coverage, 6283,
21663 GIR_Done,
21664 // Label 1190: @61776
21665 GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(61806), // Rule ID 6284 //
21666 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
21667 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
21668 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
21669 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21670 // (bitconvert:{ *:[i64] } V64:{ *:[v2i32] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2i32] }:$Vn, GPR64:{ *:[i32] })
21671 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21672 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
21673 // GIR_Coverage, 6284,
21674 GIR_Done,
21675 // Label 1191: @61806
21676 GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(61836), // Rule ID 6285 //
21677 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
21678 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
21679 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
21680 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21681 // (bitconvert:{ *:[i64] } V64:{ *:[v4f16] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4f16] }:$Vn, GPR64:{ *:[i32] })
21682 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21683 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
21684 // GIR_Coverage, 6285,
21685 GIR_Done,
21686 // Label 1192: @61836
21687 GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(61866), // Rule ID 6286 //
21688 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
21689 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
21690 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
21691 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21692 // (bitconvert:{ *:[i64] } V64:{ *:[v4bf16] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4bf16] }:$Vn, GPR64:{ *:[i32] })
21693 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21694 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
21695 // GIR_Coverage, 6286,
21696 GIR_Done,
21697 // Label 1193: @61866
21698 GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(61896), // Rule ID 6287 //
21699 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
21700 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
21701 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
21702 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21703 // (bitconvert:{ *:[i64] } V64:{ *:[v2f32] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2f32] }:$Vn, GPR64:{ *:[i32] })
21704 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21705 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
21706 // GIR_Coverage, 6287,
21707 GIR_Done,
21708 // Label 1194: @61896
21709 GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(61926), // Rule ID 6288 //
21710 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
21711 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
21712 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
21713 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21714 // (bitconvert:{ *:[i64] } V64:{ *:[v1f64] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1f64] }:$Vn, GPR64:{ *:[i32] })
21715 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21716 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
21717 // GIR_Coverage, 6288,
21718 GIR_Done,
21719 // Label 1195: @61926
21720 GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(61973), // Rule ID 6295 //
21721 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
21722 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
21723 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21724 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21725 // (bitconvert:{ *:[i64] } V64:{ *:[v8i8] }:$Vn) => (REV64v8i8:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v8i8] }:$Vn, GPR64:{ *:[i32] }))
21726 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21727 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21728 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21729 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn
21730 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21731 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
21732 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
21733 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21734 GIR_RootConstrainSelectedInstOperands,
21735 // GIR_Coverage, 6295,
21736 GIR_EraseRootFromParent_Done,
21737 // Label 1196: @61973
21738 GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(62020), // Rule ID 6296 //
21739 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
21740 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
21741 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21742 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21743 // (bitconvert:{ *:[i64] } V64:{ *:[v4i16] }:$Vn) => (REV64v4i16:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4i16] }:$Vn, GPR64:{ *:[i32] }))
21744 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21745 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21746 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21747 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn
21748 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21749 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
21750 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
21751 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21752 GIR_RootConstrainSelectedInstOperands,
21753 // GIR_Coverage, 6296,
21754 GIR_EraseRootFromParent_Done,
21755 // Label 1197: @62020
21756 GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(62067), // Rule ID 6297 //
21757 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
21758 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
21759 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21760 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21761 // (bitconvert:{ *:[i64] } V64:{ *:[v2i32] }:$Vn) => (REV64v2i32:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2i32] }:$Vn, GPR64:{ *:[i32] }))
21762 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21763 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21764 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21765 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn
21766 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21767 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
21768 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
21769 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21770 GIR_RootConstrainSelectedInstOperands,
21771 // GIR_Coverage, 6297,
21772 GIR_EraseRootFromParent_Done,
21773 // Label 1198: @62067
21774 GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(62114), // Rule ID 6298 //
21775 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
21776 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
21777 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21778 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21779 // (bitconvert:{ *:[i64] } V64:{ *:[v4f16] }:$Vn) => (REV64v4i16:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4f16] }:$Vn, GPR64:{ *:[i32] }))
21780 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21781 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21782 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21783 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn
21784 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21785 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
21786 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
21787 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21788 GIR_RootConstrainSelectedInstOperands,
21789 // GIR_Coverage, 6298,
21790 GIR_EraseRootFromParent_Done,
21791 // Label 1199: @62114
21792 GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(62161), // Rule ID 6299 //
21793 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
21794 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
21795 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21796 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21797 // (bitconvert:{ *:[i64] } V64:{ *:[v4bf16] }:$Vn) => (REV64v4i16:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4bf16] }:$Vn, GPR64:{ *:[i32] }))
21798 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21799 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21800 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21801 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn
21802 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21803 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
21804 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
21805 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21806 GIR_RootConstrainSelectedInstOperands,
21807 // GIR_Coverage, 6299,
21808 GIR_EraseRootFromParent_Done,
21809 // Label 1200: @62161
21810 GIM_Try, /*On fail goto*//*Label 1201*/ GIMT_Encode4(62208), // Rule ID 6300 //
21811 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
21812 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
21813 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21814 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21815 // (bitconvert:{ *:[i64] } V64:{ *:[v2f32] }:$Vn) => (REV64v2i32:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2f32] }:$Vn, GPR64:{ *:[i32] }))
21816 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21817 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21818 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21819 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn
21820 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21821 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
21822 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
21823 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21824 GIR_RootConstrainSelectedInstOperands,
21825 // GIR_Coverage, 6300,
21826 GIR_EraseRootFromParent_Done,
21827 // Label 1201: @62208
21828 GIM_Try, /*On fail goto*//*Label 1202*/ GIMT_Encode4(62235), // Rule ID 6301 //
21829 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
21830 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21831 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
21832 // (bitconvert:{ *:[v1i64] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v1i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
21833 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21834 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
21835 // GIR_Coverage, 6301,
21836 GIR_Done,
21837 // Label 1202: @62235
21838 GIM_Try, /*On fail goto*//*Label 1203*/ GIMT_Encode4(62262), // Rule ID 6302 //
21839 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
21840 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21841 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
21842 // (bitconvert:{ *:[v1f64] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v1f64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
21843 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21844 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
21845 // GIR_Coverage, 6302,
21846 GIR_Done,
21847 // Label 1203: @62262
21848 GIM_Try, /*On fail goto*//*Label 1204*/ GIMT_Encode4(62289), // Rule ID 6303 //
21849 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
21850 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
21851 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21852 // (bitconvert:{ *:[i64] } V64:{ *:[v1i64] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1i64] }:$Vn, GPR64:{ *:[i32] })
21853 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21854 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
21855 // GIR_Coverage, 6303,
21856 GIR_Done,
21857 // Label 1204: @62289
21858 GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(62316), // Rule ID 6309 //
21859 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
21860 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21861 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
21862 // (bitconvert:{ *:[f64] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[f64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
21863 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21864 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
21865 // GIR_Coverage, 6309,
21866 GIR_Done,
21867 // Label 1205: @62316
21868 GIM_Try, /*On fail goto*//*Label 1206*/ GIMT_Encode4(62343), // Rule ID 6310 //
21869 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
21870 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
21871 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21872 // (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[i64] } FPR64:{ *:[f64] }:$Xn, GPR64:{ *:[i32] })
21873 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21874 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
21875 // GIR_Coverage, 6310,
21876 GIR_Done,
21877 // Label 1206: @62343
21878 GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(62370), // Rule ID 6311 //
21879 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
21880 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
21881 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21882 // (bitconvert:{ *:[i64] } V64:{ *:[v1f64] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1f64] }:$Vn, GPR64:{ *:[i32] })
21883 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21884 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
21885 // GIR_Coverage, 6311,
21886 GIR_Done,
21887 // Label 1207: @62370
21888 GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(62402), // Rule ID 6314 //
21889 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
21890 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
21891 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21892 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21893 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v1i64] }:$src
21894 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21895 GIR_RootToRootCopy, /*OpIdx*/0, // dst
21896 GIR_RootToRootCopy, /*OpIdx*/1, // src
21897 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
21898 // GIR_Coverage, 6314,
21899 GIR_EraseRootFromParent_Done,
21900 // Label 1208: @62402
21901 GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(62434), // Rule ID 6315 //
21902 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
21903 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
21904 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21905 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21906 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v1i64] }:$src
21907 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21908 GIR_RootToRootCopy, /*OpIdx*/0, // dst
21909 GIR_RootToRootCopy, /*OpIdx*/1, // src
21910 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
21911 // GIR_Coverage, 6315,
21912 GIR_EraseRootFromParent_Done,
21913 // Label 1209: @62434
21914 GIM_Try, /*On fail goto*//*Label 1210*/ GIMT_Encode4(62466), // Rule ID 6316 //
21915 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
21916 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
21917 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21918 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21919 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v1i64] }:$src
21920 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21921 GIR_RootToRootCopy, /*OpIdx*/0, // dst
21922 GIR_RootToRootCopy, /*OpIdx*/1, // src
21923 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
21924 // GIR_Coverage, 6316,
21925 GIR_EraseRootFromParent_Done,
21926 // Label 1210: @62466
21927 GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(62498), // Rule ID 6317 //
21928 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
21929 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
21930 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21931 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21932 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v1i64] }:$src
21933 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21934 GIR_RootToRootCopy, /*OpIdx*/0, // dst
21935 GIR_RootToRootCopy, /*OpIdx*/1, // src
21936 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
21937 // GIR_Coverage, 6317,
21938 GIR_EraseRootFromParent_Done,
21939 // Label 1211: @62498
21940 GIM_Try, /*On fail goto*//*Label 1212*/ GIMT_Encode4(62530), // Rule ID 6318 //
21941 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
21942 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
21943 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21944 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21945 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[v1i64] }:$src
21946 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21947 GIR_RootToRootCopy, /*OpIdx*/0, // dst
21948 GIR_RootToRootCopy, /*OpIdx*/1, // src
21949 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
21950 // GIR_Coverage, 6318,
21951 GIR_EraseRootFromParent_Done,
21952 // Label 1212: @62530
21953 GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(62562), // Rule ID 6319 //
21954 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
21955 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
21956 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21957 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21958 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v1i64] }:$src
21959 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
21960 GIR_RootToRootCopy, /*OpIdx*/0, // dst
21961 GIR_RootToRootCopy, /*OpIdx*/1, // src
21962 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
21963 // GIR_Coverage, 6319,
21964 GIR_EraseRootFromParent_Done,
21965 // Label 1213: @62562
21966 GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(62588), // Rule ID 6320 //
21967 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
21968 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
21969 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21970 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21971 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src) => (REV64v2i32:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src)
21972 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
21973 GIR_RootConstrainSelectedInstOperands,
21974 // GIR_Coverage, 6320,
21975 GIR_Done,
21976 // Label 1214: @62588
21977 GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(62614), // Rule ID 6321 //
21978 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
21979 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
21980 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21981 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21982 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src) => (REV64v4i16:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src)
21983 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
21984 GIR_RootConstrainSelectedInstOperands,
21985 // GIR_Coverage, 6321,
21986 GIR_Done,
21987 // Label 1215: @62614
21988 GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(62640), // Rule ID 6322 //
21989 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
21990 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
21991 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21992 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
21993 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src) => (REV64v8i8:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src)
21994 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
21995 GIR_RootConstrainSelectedInstOperands,
21996 // GIR_Coverage, 6322,
21997 GIR_Done,
21998 // Label 1216: @62640
21999 GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(62666), // Rule ID 6323 //
22000 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22001 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22002 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22003 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22004 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src) => (REV64v4i16:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src)
22005 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
22006 GIR_RootConstrainSelectedInstOperands,
22007 // GIR_Coverage, 6323,
22008 GIR_Done,
22009 // Label 1217: @62666
22010 GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(62692), // Rule ID 6324 //
22011 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22012 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22013 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22014 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22015 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4bf16] }:$src) => (REV64v4i16:{ *:[v1i64] } FPR64:{ *:[v4bf16] }:$src)
22016 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
22017 GIR_RootConstrainSelectedInstOperands,
22018 // GIR_Coverage, 6324,
22019 GIR_Done,
22020 // Label 1218: @62692
22021 GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(62718), // Rule ID 6325 //
22022 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22023 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
22024 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22025 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22026 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src) => (REV64v2i32:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src)
22027 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
22028 GIR_RootConstrainSelectedInstOperands,
22029 // GIR_Coverage, 6325,
22030 GIR_Done,
22031 // Label 1219: @62718
22032 GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(62747), // Rule ID 6326 //
22033 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22034 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22035 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22036 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v1i64] }:$src
22037 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22038 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22039 GIR_RootToRootCopy, /*OpIdx*/1, // src
22040 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22041 // GIR_Coverage, 6326,
22042 GIR_EraseRootFromParent_Done,
22043 // Label 1220: @62747
22044 GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(62776), // Rule ID 6327 //
22045 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22046 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22047 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22048 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v1i64] }:$src
22049 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22050 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22051 GIR_RootToRootCopy, /*OpIdx*/1, // src
22052 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22053 // GIR_Coverage, 6327,
22054 GIR_EraseRootFromParent_Done,
22055 // Label 1221: @62776
22056 GIM_Try, /*On fail goto*//*Label 1222*/ GIMT_Encode4(62808), // Rule ID 6399 //
22057 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22058 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
22059 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22060 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22061 // (bitconvert:{ *:[f64] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[f64] }:$src
22062 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22063 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22064 GIR_RootToRootCopy, /*OpIdx*/1, // src
22065 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22066 // GIR_Coverage, 6399,
22067 GIR_EraseRootFromParent_Done,
22068 // Label 1222: @62808
22069 GIM_Try, /*On fail goto*//*Label 1223*/ GIMT_Encode4(62840), // Rule ID 6400 //
22070 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22071 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22072 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22073 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22074 // (bitconvert:{ *:[f64] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[f64] }:$src
22075 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22076 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22077 GIR_RootToRootCopy, /*OpIdx*/1, // src
22078 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22079 // GIR_Coverage, 6400,
22080 GIR_EraseRootFromParent_Done,
22081 // Label 1223: @62840
22082 GIM_Try, /*On fail goto*//*Label 1224*/ GIMT_Encode4(62872), // Rule ID 6401 //
22083 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22084 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
22085 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22086 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22087 // (bitconvert:{ *:[f64] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[f64] }:$src
22088 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22089 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22090 GIR_RootToRootCopy, /*OpIdx*/1, // src
22091 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22092 // GIR_Coverage, 6401,
22093 GIR_EraseRootFromParent_Done,
22094 // Label 1224: @62872
22095 GIM_Try, /*On fail goto*//*Label 1225*/ GIMT_Encode4(62904), // Rule ID 6402 //
22096 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22097 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
22098 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22099 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22100 // (bitconvert:{ *:[f64] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[f64] }:$src
22101 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22102 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22103 GIR_RootToRootCopy, /*OpIdx*/1, // src
22104 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22105 // GIR_Coverage, 6402,
22106 GIR_EraseRootFromParent_Done,
22107 // Label 1225: @62904
22108 GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(62936), // Rule ID 6403 //
22109 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22110 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22111 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22112 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22113 // (bitconvert:{ *:[f64] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[f64] }:$src
22114 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22115 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22116 GIR_RootToRootCopy, /*OpIdx*/1, // src
22117 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22118 // GIR_Coverage, 6403,
22119 GIR_EraseRootFromParent_Done,
22120 // Label 1226: @62936
22121 GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(62968), // Rule ID 6404 //
22122 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22123 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22124 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22125 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22126 // (bitconvert:{ *:[f64] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[f64] }:$src
22127 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22128 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22129 GIR_RootToRootCopy, /*OpIdx*/1, // src
22130 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22131 // GIR_Coverage, 6404,
22132 GIR_EraseRootFromParent_Done,
22133 // Label 1227: @62968
22134 GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(62994), // Rule ID 6405 //
22135 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22136 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
22137 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22138 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22139 // (bitconvert:{ *:[f64] } FPR64:{ *:[v2i32] }:$src) => (REV64v2i32:{ *:[f64] } FPR64:{ *:[v2i32] }:$src)
22140 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
22141 GIR_RootConstrainSelectedInstOperands,
22142 // GIR_Coverage, 6405,
22143 GIR_Done,
22144 // Label 1228: @62994
22145 GIM_Try, /*On fail goto*//*Label 1229*/ GIMT_Encode4(63020), // Rule ID 6406 //
22146 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22147 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22148 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22149 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22150 // (bitconvert:{ *:[f64] } FPR64:{ *:[v4i16] }:$src) => (REV64v4i16:{ *:[f64] } FPR64:{ *:[v4i16] }:$src)
22151 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
22152 GIR_RootConstrainSelectedInstOperands,
22153 // GIR_Coverage, 6406,
22154 GIR_Done,
22155 // Label 1229: @63020
22156 GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(63046), // Rule ID 6407 //
22157 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22158 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
22159 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22160 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22161 // (bitconvert:{ *:[f64] } FPR64:{ *:[v2f32] }:$src) => (REV64v2i32:{ *:[f64] } FPR64:{ *:[v2f32] }:$src)
22162 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
22163 GIR_RootConstrainSelectedInstOperands,
22164 // GIR_Coverage, 6407,
22165 GIR_Done,
22166 // Label 1230: @63046
22167 GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(63072), // Rule ID 6408 //
22168 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22169 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
22170 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22171 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22172 // (bitconvert:{ *:[f64] } FPR64:{ *:[v8i8] }:$src) => (REV64v8i8:{ *:[f64] } FPR64:{ *:[v8i8] }:$src)
22173 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
22174 GIR_RootConstrainSelectedInstOperands,
22175 // GIR_Coverage, 6408,
22176 GIR_Done,
22177 // Label 1231: @63072
22178 GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(63098), // Rule ID 6409 //
22179 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22180 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22181 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22182 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22183 // (bitconvert:{ *:[f64] } FPR64:{ *:[v4f16] }:$src) => (REV64v4i16:{ *:[f64] } FPR64:{ *:[v4f16] }:$src)
22184 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
22185 GIR_RootConstrainSelectedInstOperands,
22186 // GIR_Coverage, 6409,
22187 GIR_Done,
22188 // Label 1232: @63098
22189 GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(63124), // Rule ID 6410 //
22190 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22191 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22192 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22193 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22194 // (bitconvert:{ *:[f64] } FPR64:{ *:[v4bf16] }:$src) => (REV64v4i16:{ *:[f64] } FPR64:{ *:[v4bf16] }:$src)
22195 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
22196 GIR_RootConstrainSelectedInstOperands,
22197 // GIR_Coverage, 6410,
22198 GIR_Done,
22199 // Label 1233: @63124
22200 GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(63153), // Rule ID 6411 //
22201 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22202 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22203 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22204 // (bitconvert:{ *:[f64] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[f64] }:$src
22205 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22206 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22207 GIR_RootToRootCopy, /*OpIdx*/1, // src
22208 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22209 // GIR_Coverage, 6411,
22210 GIR_EraseRootFromParent_Done,
22211 // Label 1234: @63153
22212 GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(63182), // Rule ID 6412 //
22213 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22214 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22215 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22216 // (bitconvert:{ *:[f64] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[f64] }:$src
22217 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22218 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22219 GIR_RootToRootCopy, /*OpIdx*/1, // src
22220 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22221 // GIR_Coverage, 6412,
22222 GIR_EraseRootFromParent_Done,
22223 // Label 1235: @63182
22224 GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(63214), // Rule ID 6413 //
22225 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22226 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
22227 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22228 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22229 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v1f64] }:$src
22230 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22231 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22232 GIR_RootToRootCopy, /*OpIdx*/1, // src
22233 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22234 // GIR_Coverage, 6413,
22235 GIR_EraseRootFromParent_Done,
22236 // Label 1236: @63214
22237 GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(63246), // Rule ID 6414 //
22238 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22239 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22240 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22241 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22242 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v1f64] }:$src
22243 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22244 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22245 GIR_RootToRootCopy, /*OpIdx*/1, // src
22246 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22247 // GIR_Coverage, 6414,
22248 GIR_EraseRootFromParent_Done,
22249 // Label 1237: @63246
22250 GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(63278), // Rule ID 6415 //
22251 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22252 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
22253 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22254 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22255 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v1f64] }:$src
22256 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22257 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22258 GIR_RootToRootCopy, /*OpIdx*/1, // src
22259 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22260 // GIR_Coverage, 6415,
22261 GIR_EraseRootFromParent_Done,
22262 // Label 1238: @63278
22263 GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(63310), // Rule ID 6416 //
22264 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22265 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
22266 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22267 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22268 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v1f64] }:$src
22269 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22270 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22271 GIR_RootToRootCopy, /*OpIdx*/1, // src
22272 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22273 // GIR_Coverage, 6416,
22274 GIR_EraseRootFromParent_Done,
22275 // Label 1239: @63310
22276 GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(63342), // Rule ID 6417 //
22277 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22278 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22279 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22280 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22281 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v1f64] }:$src
22282 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22283 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22284 GIR_RootToRootCopy, /*OpIdx*/1, // src
22285 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22286 // GIR_Coverage, 6417,
22287 GIR_EraseRootFromParent_Done,
22288 // Label 1240: @63342
22289 GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(63374), // Rule ID 6418 //
22290 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22291 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22292 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22293 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22294 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[v1f64] }:$src
22295 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22296 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22297 GIR_RootToRootCopy, /*OpIdx*/1, // src
22298 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22299 // GIR_Coverage, 6418,
22300 GIR_EraseRootFromParent_Done,
22301 // Label 1241: @63374
22302 GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(63400), // Rule ID 6419 //
22303 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22304 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
22305 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22306 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22307 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src) => (REV64v2i32:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src)
22308 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
22309 GIR_RootConstrainSelectedInstOperands,
22310 // GIR_Coverage, 6419,
22311 GIR_Done,
22312 // Label 1242: @63400
22313 GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(63426), // Rule ID 6420 //
22314 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22315 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22316 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22317 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22318 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src) => (REV64v4i16:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src)
22319 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
22320 GIR_RootConstrainSelectedInstOperands,
22321 // GIR_Coverage, 6420,
22322 GIR_Done,
22323 // Label 1243: @63426
22324 GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(63452), // Rule ID 6421 //
22325 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22326 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
22327 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22328 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22329 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src) => (REV64v8i8:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src)
22330 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
22331 GIR_RootConstrainSelectedInstOperands,
22332 // GIR_Coverage, 6421,
22333 GIR_Done,
22334 // Label 1244: @63452
22335 GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(63478), // Rule ID 6422 //
22336 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22337 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
22338 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22339 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22340 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src) => (REV64v2i32:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src)
22341 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
22342 GIR_RootConstrainSelectedInstOperands,
22343 // GIR_Coverage, 6422,
22344 GIR_Done,
22345 // Label 1245: @63478
22346 GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(63504), // Rule ID 6423 //
22347 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22348 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22349 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22350 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22351 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src) => (REV64v4i16:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src)
22352 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
22353 GIR_RootConstrainSelectedInstOperands,
22354 // GIR_Coverage, 6423,
22355 GIR_Done,
22356 // Label 1246: @63504
22357 GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(63530), // Rule ID 6424 //
22358 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22359 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22360 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22361 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22362 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4bf16] }:$src) => (REV64v4i16:{ *:[v1f64] } FPR64:{ *:[v4bf16] }:$src)
22363 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
22364 GIR_RootConstrainSelectedInstOperands,
22365 // GIR_Coverage, 6424,
22366 GIR_Done,
22367 // Label 1247: @63530
22368 GIM_Try, /*On fail goto*//*Label 1248*/ GIMT_Encode4(63559), // Rule ID 6425 //
22369 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22370 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22371 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22372 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v1f64] }:$src
22373 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22374 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22375 GIR_RootToRootCopy, /*OpIdx*/1, // src
22376 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22377 // GIR_Coverage, 6425,
22378 GIR_EraseRootFromParent_Done,
22379 // Label 1248: @63559
22380 GIM_Try, /*On fail goto*//*Label 1249*/ GIMT_Encode4(63588), // Rule ID 6426 //
22381 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22382 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22383 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22384 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v1f64] }:$src
22385 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22386 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22387 GIR_RootToRootCopy, /*OpIdx*/1, // src
22388 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22389 // GIR_Coverage, 6426,
22390 GIR_EraseRootFromParent_Done,
22391 // Label 1249: @63588
22392 GIM_Reject,
22393 // Label 1160: @63589
22394 GIM_Try, /*On fail goto*//*Label 1250*/ GIMT_Encode4(63621), // Rule ID 6442 //
22395 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22396 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
22397 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22398 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22399 // (bitconvert:{ *:[f128] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[f128] }:$src
22400 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22401 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22402 GIR_RootToRootCopy, /*OpIdx*/1, // src
22403 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
22404 // GIR_Coverage, 6442,
22405 GIR_EraseRootFromParent_Done,
22406 // Label 1250: @63621
22407 GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(63653), // Rule ID 6443 //
22408 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22409 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
22410 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22411 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22412 // (bitconvert:{ *:[f128] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[f128] }:$src
22413 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22414 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22415 GIR_RootToRootCopy, /*OpIdx*/1, // src
22416 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
22417 // GIR_Coverage, 6443,
22418 GIR_EraseRootFromParent_Done,
22419 // Label 1251: @63653
22420 GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(63685), // Rule ID 6444 //
22421 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22422 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
22423 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22424 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22425 // (bitconvert:{ *:[f128] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[f128] }:$src
22426 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22427 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22428 GIR_RootToRootCopy, /*OpIdx*/1, // src
22429 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
22430 // GIR_Coverage, 6444,
22431 GIR_EraseRootFromParent_Done,
22432 // Label 1252: @63685
22433 GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(63717), // Rule ID 6445 //
22434 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22435 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
22436 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22437 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22438 // (bitconvert:{ *:[f128] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[f128] }:$src
22439 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22440 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22441 GIR_RootToRootCopy, /*OpIdx*/1, // src
22442 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
22443 // GIR_Coverage, 6445,
22444 GIR_EraseRootFromParent_Done,
22445 // Label 1253: @63717
22446 GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(63749), // Rule ID 6446 //
22447 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22448 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
22449 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22450 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22451 // (bitconvert:{ *:[f128] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[f128] }:$src
22452 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22453 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22454 GIR_RootToRootCopy, /*OpIdx*/1, // src
22455 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
22456 // GIR_Coverage, 6446,
22457 GIR_EraseRootFromParent_Done,
22458 // Label 1254: @63749
22459 GIM_Try, /*On fail goto*//*Label 1255*/ GIMT_Encode4(63781), // Rule ID 6447 //
22460 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22461 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
22462 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22463 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22464 // (bitconvert:{ *:[f128] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[f128] }:$src
22465 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22466 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22467 GIR_RootToRootCopy, /*OpIdx*/1, // src
22468 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
22469 // GIR_Coverage, 6447,
22470 GIR_EraseRootFromParent_Done,
22471 // Label 1255: @63781
22472 GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(63813), // Rule ID 6448 //
22473 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22474 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
22475 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22476 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22477 // (bitconvert:{ *:[f128] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[f128] }:$src
22478 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22479 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22480 GIR_RootToRootCopy, /*OpIdx*/1, // src
22481 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
22482 // GIR_Coverage, 6448,
22483 GIR_EraseRootFromParent_Done,
22484 // Label 1256: @63813
22485 GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(63845), // Rule ID 6449 //
22486 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22487 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
22488 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22489 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22490 // (bitconvert:{ *:[f128] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[f128] }:$src
22491 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22492 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22493 GIR_RootToRootCopy, /*OpIdx*/1, // src
22494 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
22495 // GIR_Coverage, 6449,
22496 GIR_EraseRootFromParent_Done,
22497 // Label 1257: @63845
22498 GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(63878), // Rule ID 6450 //
22499 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22500 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
22501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22502 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22503 // (bitconvert:{ *:[f128] } FPR128:{ *:[v2i64] }:$src) => (EXTv16i8:{ *:[f128] } FPR128:{ *:[v2i64] }:$src, FPR128:{ *:[v2i64] }:$src, 8:{ *:[i32] })
22504 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
22505 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22506 GIR_RootToRootCopy, /*OpIdx*/1, // src
22507 GIR_RootToRootCopy, /*OpIdx*/1, // src
22508 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
22509 GIR_RootConstrainSelectedInstOperands,
22510 // GIR_Coverage, 6450,
22511 GIR_EraseRootFromParent_Done,
22512 // Label 1258: @63878
22513 GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(63949), // Rule ID 6451 //
22514 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22515 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
22516 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22517 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22518 // (bitconvert:{ *:[f128] } FPR128:{ *:[v4i32] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4i32] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4i32] }:$src), 8:{ *:[i32] })
22519 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
22520 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
22521 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
22522 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22523 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
22524 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
22525 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
22526 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22527 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
22528 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22529 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
22530 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22531 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22532 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
22533 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
22534 GIR_RootConstrainSelectedInstOperands,
22535 // GIR_Coverage, 6451,
22536 GIR_EraseRootFromParent_Done,
22537 // Label 1259: @63949
22538 GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(64020), // Rule ID 6452 //
22539 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22540 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
22541 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22542 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22543 // (bitconvert:{ *:[f128] } FPR128:{ *:[v8i16] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8i16] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8i16] }:$src), 8:{ *:[i32] })
22544 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
22545 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
22546 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
22547 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22548 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
22549 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
22550 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
22551 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22552 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
22553 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22554 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
22555 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22556 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22557 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
22558 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
22559 GIR_RootConstrainSelectedInstOperands,
22560 // GIR_Coverage, 6452,
22561 GIR_EraseRootFromParent_Done,
22562 // Label 1260: @64020
22563 GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(64091), // Rule ID 6453 //
22564 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22565 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
22566 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22567 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22568 // (bitconvert:{ *:[f128] } FPR128:{ *:[v8f16] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8f16] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8f16] }:$src), 8:{ *:[i32] })
22569 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
22570 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
22571 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
22572 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22573 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
22574 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
22575 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
22576 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22577 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
22578 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22579 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
22580 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22581 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22582 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
22583 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
22584 GIR_RootConstrainSelectedInstOperands,
22585 // GIR_Coverage, 6453,
22586 GIR_EraseRootFromParent_Done,
22587 // Label 1261: @64091
22588 GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(64162), // Rule ID 6454 //
22589 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22590 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
22591 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22592 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22593 // (bitconvert:{ *:[f128] } FPR128:{ *:[v8bf16] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8bf16] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8bf16] }:$src), 8:{ *:[i32] })
22594 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
22595 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
22596 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
22597 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22598 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
22599 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
22600 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
22601 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22602 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
22603 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22604 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
22605 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22606 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22607 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
22608 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
22609 GIR_RootConstrainSelectedInstOperands,
22610 // GIR_Coverage, 6454,
22611 GIR_EraseRootFromParent_Done,
22612 // Label 1262: @64162
22613 GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(64195), // Rule ID 6455 //
22614 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22615 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
22616 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22617 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22618 // (bitconvert:{ *:[f128] } FPR128:{ *:[v2f64] }:$src) => (EXTv16i8:{ *:[f128] } FPR128:{ *:[v2f64] }:$src, FPR128:{ *:[v2f64] }:$src, 8:{ *:[i32] })
22619 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
22620 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22621 GIR_RootToRootCopy, /*OpIdx*/1, // src
22622 GIR_RootToRootCopy, /*OpIdx*/1, // src
22623 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
22624 GIR_RootConstrainSelectedInstOperands,
22625 // GIR_Coverage, 6455,
22626 GIR_EraseRootFromParent_Done,
22627 // Label 1263: @64195
22628 GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(64266), // Rule ID 6456 //
22629 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22630 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
22631 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22632 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22633 // (bitconvert:{ *:[f128] } FPR128:{ *:[v4f32] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4f32] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4f32] }:$src), 8:{ *:[i32] })
22634 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
22635 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
22636 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
22637 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22638 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
22639 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
22640 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
22641 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22642 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
22643 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22644 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
22645 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22646 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22647 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
22648 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
22649 GIR_RootConstrainSelectedInstOperands,
22650 // GIR_Coverage, 6456,
22651 GIR_EraseRootFromParent_Done,
22652 // Label 1264: @64266
22653 GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(64337), // Rule ID 6457 //
22654 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22655 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
22656 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22657 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
22658 // (bitconvert:{ *:[f128] } FPR128:{ *:[v16i8] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v16i8:{ *:[f128] } FPR128:{ *:[v16i8] }:$src), (REV64v16i8:{ *:[f128] } FPR128:{ *:[v16i8] }:$src), 8:{ *:[i32] })
22659 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
22660 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
22661 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
22662 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22663 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
22664 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
22665 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
22666 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22667 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
22668 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22669 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
22670 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22671 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22672 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
22673 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
22674 GIR_RootConstrainSelectedInstOperands,
22675 // GIR_Coverage, 6457,
22676 GIR_EraseRootFromParent_Done,
22677 // Label 1265: @64337
22678 GIM_Reject,
22679 // Label 1161: @64338
22680 GIM_Try, /*On fail goto*//*Label 1266*/ GIMT_Encode4(64368), // Rule ID 6278 //
22681 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22682 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22683 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22684 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
22685 // (bitconvert:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
22686 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22687 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22688 // GIR_Coverage, 6278,
22689 GIR_Done,
22690 // Label 1266: @64368
22691 GIM_Try, /*On fail goto*//*Label 1267*/ GIMT_Encode4(64398), // Rule ID 6281 //
22692 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22693 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22694 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22695 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
22696 // (bitconvert:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
22697 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22698 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22699 // GIR_Coverage, 6281,
22700 GIR_Done,
22701 // Label 1267: @64398
22702 GIM_Try, /*On fail goto*//*Label 1268*/ GIMT_Encode4(64445), // Rule ID 6291 //
22703 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22704 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22705 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22706 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
22707 // (bitconvert:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn) => (REV64v2i32:{ *:[v2i32] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }))
22708 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
22709 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22710 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22711 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn
22712 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22713 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
22714 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22715 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22716 GIR_RootConstrainSelectedInstOperands,
22717 // GIR_Coverage, 6291,
22718 GIR_EraseRootFromParent_Done,
22719 // Label 1268: @64445
22720 GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(64492), // Rule ID 6294 //
22721 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22722 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22723 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22724 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
22725 // (bitconvert:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn) => (REV64v2i32:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }))
22726 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
22727 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22728 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22729 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn
22730 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22731 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
22732 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22733 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22734 GIR_RootConstrainSelectedInstOperands,
22735 // GIR_Coverage, 6294,
22736 GIR_EraseRootFromParent_Done,
22737 // Label 1269: @64492
22738 GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(64524), // Rule ID 6328 //
22739 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22740 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22741 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22742 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22743 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v2i32] }:$src
22744 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22745 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22746 GIR_RootToRootCopy, /*OpIdx*/1, // src
22747 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22748 // GIR_Coverage, 6328,
22749 GIR_EraseRootFromParent_Done,
22750 // Label 1270: @64524
22751 GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(64556), // Rule ID 6329 //
22752 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22753 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22754 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22755 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22756 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v2i32] }:$src
22757 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22758 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22759 GIR_RootToRootCopy, /*OpIdx*/1, // src
22760 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22761 // GIR_Coverage, 6329,
22762 GIR_EraseRootFromParent_Done,
22763 // Label 1271: @64556
22764 GIM_Try, /*On fail goto*//*Label 1272*/ GIMT_Encode4(64588), // Rule ID 6330 //
22765 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22766 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
22767 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22768 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22769 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v2i32] }:$src
22770 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22771 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22772 GIR_RootToRootCopy, /*OpIdx*/1, // src
22773 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22774 // GIR_Coverage, 6330,
22775 GIR_EraseRootFromParent_Done,
22776 // Label 1272: @64588
22777 GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(64620), // Rule ID 6331 //
22778 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22779 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22780 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22781 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22782 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v2i32] }:$src
22783 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22784 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22785 GIR_RootToRootCopy, /*OpIdx*/1, // src
22786 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22787 // GIR_Coverage, 6331,
22788 GIR_EraseRootFromParent_Done,
22789 // Label 1273: @64620
22790 GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(64652), // Rule ID 6332 //
22791 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22792 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22793 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22794 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22795 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v2i32] }:$src
22796 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22797 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22798 GIR_RootToRootCopy, /*OpIdx*/1, // src
22799 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22800 // GIR_Coverage, 6332,
22801 GIR_EraseRootFromParent_Done,
22802 // Label 1274: @64652
22803 GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(64684), // Rule ID 6333 //
22804 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22805 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22806 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22807 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22808 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v2i32] }:$src
22809 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22810 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22811 GIR_RootToRootCopy, /*OpIdx*/1, // src
22812 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22813 // GIR_Coverage, 6333,
22814 GIR_EraseRootFromParent_Done,
22815 // Label 1275: @64684
22816 GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(64716), // Rule ID 6334 //
22817 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22818 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22819 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22820 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22821 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[v2i32] }:$src
22822 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22823 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22824 GIR_RootToRootCopy, /*OpIdx*/1, // src
22825 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22826 // GIR_Coverage, 6334,
22827 GIR_EraseRootFromParent_Done,
22828 // Label 1276: @64716
22829 GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(64742), // Rule ID 6335 //
22830 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22831 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22832 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22833 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22834 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src) => (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src)
22835 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
22836 GIR_RootConstrainSelectedInstOperands,
22837 // GIR_Coverage, 6335,
22838 GIR_Done,
22839 // Label 1277: @64742
22840 GIM_Try, /*On fail goto*//*Label 1278*/ GIMT_Encode4(64768), // Rule ID 6336 //
22841 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22842 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22843 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22844 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22845 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src) => (REV32v4i16:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src)
22846 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
22847 GIR_RootConstrainSelectedInstOperands,
22848 // GIR_Coverage, 6336,
22849 GIR_Done,
22850 // Label 1278: @64768
22851 GIM_Try, /*On fail goto*//*Label 1279*/ GIMT_Encode4(64794), // Rule ID 6337 //
22852 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22853 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
22854 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22855 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22856 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src) => (REV32v8i8:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src)
22857 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i8),
22858 GIR_RootConstrainSelectedInstOperands,
22859 // GIR_Coverage, 6337,
22860 GIR_Done,
22861 // Label 1279: @64794
22862 GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(64820), // Rule ID 6338 //
22863 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22864 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22865 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22866 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22867 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[f64] }:$src) => (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[f64] }:$src)
22868 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
22869 GIR_RootConstrainSelectedInstOperands,
22870 // GIR_Coverage, 6338,
22871 GIR_Done,
22872 // Label 1280: @64820
22873 GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(64846), // Rule ID 6339 //
22874 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22875 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22876 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22877 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22878 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src) => (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src)
22879 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
22880 GIR_RootConstrainSelectedInstOperands,
22881 // GIR_Coverage, 6339,
22882 GIR_Done,
22883 // Label 1281: @64846
22884 GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(64872), // Rule ID 6340 //
22885 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22886 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22887 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22888 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22889 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src) => (REV32v4i16:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src)
22890 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
22891 GIR_RootConstrainSelectedInstOperands,
22892 // GIR_Coverage, 6340,
22893 GIR_Done,
22894 // Label 1282: @64872
22895 GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(64898), // Rule ID 6341 //
22896 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
22897 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22898 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22899 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22900 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4bf16] }:$src) => (REV32v4i16:{ *:[v2i32] } FPR64:{ *:[v4bf16] }:$src)
22901 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
22902 GIR_RootConstrainSelectedInstOperands,
22903 // GIR_Coverage, 6341,
22904 GIR_Done,
22905 // Label 1283: @64898
22906 GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(64927), // Rule ID 6342 //
22907 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
22908 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22909 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22910 // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v2i32] }:$src
22911 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22912 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22913 GIR_RootToRootCopy, /*OpIdx*/1, // src
22914 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22915 // GIR_Coverage, 6342,
22916 GIR_EraseRootFromParent_Done,
22917 // Label 1284: @64927
22918 GIM_Try, /*On fail goto*//*Label 1285*/ GIMT_Encode4(64959), // Rule ID 6427 //
22919 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22920 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22921 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22922 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22923 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v2f32] }:$src
22924 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22925 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22926 GIR_RootToRootCopy, /*OpIdx*/1, // src
22927 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22928 // GIR_Coverage, 6427,
22929 GIR_EraseRootFromParent_Done,
22930 // Label 1285: @64959
22931 GIM_Try, /*On fail goto*//*Label 1286*/ GIMT_Encode4(64991), // Rule ID 6428 //
22932 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22933 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22934 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22935 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22936 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v2f32] }:$src
22937 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22938 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22939 GIR_RootToRootCopy, /*OpIdx*/1, // src
22940 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22941 // GIR_Coverage, 6428,
22942 GIR_EraseRootFromParent_Done,
22943 // Label 1286: @64991
22944 GIM_Try, /*On fail goto*//*Label 1287*/ GIMT_Encode4(65023), // Rule ID 6429 //
22945 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22946 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
22947 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22948 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22949 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v2f32] }:$src
22950 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22951 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22952 GIR_RootToRootCopy, /*OpIdx*/1, // src
22953 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22954 // GIR_Coverage, 6429,
22955 GIR_EraseRootFromParent_Done,
22956 // Label 1287: @65023
22957 GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(65055), // Rule ID 6430 //
22958 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22959 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22960 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22961 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22962 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v2f32] }:$src
22963 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22964 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22965 GIR_RootToRootCopy, /*OpIdx*/1, // src
22966 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22967 // GIR_Coverage, 6430,
22968 GIR_EraseRootFromParent_Done,
22969 // Label 1288: @65055
22970 GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(65087), // Rule ID 6431 //
22971 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22972 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22973 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22974 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22975 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v2f32] }:$src
22976 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22977 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22978 GIR_RootToRootCopy, /*OpIdx*/1, // src
22979 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22980 // GIR_Coverage, 6431,
22981 GIR_EraseRootFromParent_Done,
22982 // Label 1289: @65087
22983 GIM_Try, /*On fail goto*//*Label 1290*/ GIMT_Encode4(65119), // Rule ID 6432 //
22984 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22985 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22986 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22987 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
22988 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v2f32] }:$src
22989 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
22990 GIR_RootToRootCopy, /*OpIdx*/0, // dst
22991 GIR_RootToRootCopy, /*OpIdx*/1, // src
22992 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
22993 // GIR_Coverage, 6432,
22994 GIR_EraseRootFromParent_Done,
22995 // Label 1290: @65119
22996 GIM_Try, /*On fail goto*//*Label 1291*/ GIMT_Encode4(65151), // Rule ID 6433 //
22997 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
22998 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
22999 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23000 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23001 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[v2f32] }:$src
23002 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23003 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23004 GIR_RootToRootCopy, /*OpIdx*/1, // src
23005 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23006 // GIR_Coverage, 6433,
23007 GIR_EraseRootFromParent_Done,
23008 // Label 1291: @65151
23009 GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(65177), // Rule ID 6434 //
23010 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23011 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23012 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23013 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23014 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src) => (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src)
23015 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
23016 GIR_RootConstrainSelectedInstOperands,
23017 // GIR_Coverage, 6434,
23018 GIR_Done,
23019 // Label 1292: @65177
23020 GIM_Try, /*On fail goto*//*Label 1293*/ GIMT_Encode4(65203), // Rule ID 6435 //
23021 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23022 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
23023 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23024 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23025 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src) => (REV32v4i16:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src)
23026 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
23027 GIR_RootConstrainSelectedInstOperands,
23028 // GIR_Coverage, 6435,
23029 GIR_Done,
23030 // Label 1293: @65203
23031 GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(65229), // Rule ID 6436 //
23032 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23033 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
23034 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23035 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23036 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src) => (REV32v8i8:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src)
23037 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i8),
23038 GIR_RootConstrainSelectedInstOperands,
23039 // GIR_Coverage, 6436,
23040 GIR_Done,
23041 // Label 1294: @65229
23042 GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(65255), // Rule ID 6437 //
23043 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23044 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23045 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23046 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23047 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src) => (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src)
23048 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
23049 GIR_RootConstrainSelectedInstOperands,
23050 // GIR_Coverage, 6437,
23051 GIR_Done,
23052 // Label 1295: @65255
23053 GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(65281), // Rule ID 6438 //
23054 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23055 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23056 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23057 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23058 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[f64] }:$src) => (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[f64] }:$src)
23059 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
23060 GIR_RootConstrainSelectedInstOperands,
23061 // GIR_Coverage, 6438,
23062 GIR_Done,
23063 // Label 1296: @65281
23064 GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(65307), // Rule ID 6439 //
23065 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23066 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
23067 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23068 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23069 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src) => (REV32v4i16:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src)
23070 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
23071 GIR_RootConstrainSelectedInstOperands,
23072 // GIR_Coverage, 6439,
23073 GIR_Done,
23074 // Label 1297: @65307
23075 GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(65333), // Rule ID 6440 //
23076 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23077 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
23078 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23079 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23080 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4bf16] }:$src) => (REV32v4i16:{ *:[v2f32] } FPR64:{ *:[v4bf16] }:$src)
23081 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
23082 GIR_RootConstrainSelectedInstOperands,
23083 // GIR_Coverage, 6440,
23084 GIR_Done,
23085 // Label 1298: @65333
23086 GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(65362), // Rule ID 6441 //
23087 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
23088 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23089 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23090 // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v2f32] }:$src
23091 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23092 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23093 GIR_RootToRootCopy, /*OpIdx*/1, // src
23094 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23095 // GIR_Coverage, 6441,
23096 GIR_EraseRootFromParent_Done,
23097 // Label 1299: @65362
23098 GIM_Reject,
23099 // Label 1162: @65363
23100 GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(65395), // Rule ID 6458 //
23101 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23102 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
23103 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23104 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23105 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v2f64] }:$src
23106 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23107 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23108 GIR_RootToRootCopy, /*OpIdx*/1, // src
23109 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
23110 // GIR_Coverage, 6458,
23111 GIR_EraseRootFromParent_Done,
23112 // Label 1300: @65395
23113 GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(65427), // Rule ID 6459 //
23114 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23115 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23116 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23117 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23118 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v2f64] }:$src
23119 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23120 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23121 GIR_RootToRootCopy, /*OpIdx*/1, // src
23122 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
23123 // GIR_Coverage, 6459,
23124 GIR_EraseRootFromParent_Done,
23125 // Label 1301: @65427
23126 GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(65459), // Rule ID 6460 //
23127 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23128 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
23129 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23130 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23131 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v2f64] }:$src
23132 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23133 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23134 GIR_RootToRootCopy, /*OpIdx*/1, // src
23135 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
23136 // GIR_Coverage, 6460,
23137 GIR_EraseRootFromParent_Done,
23138 // Label 1302: @65459
23139 GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(65491), // Rule ID 6461 //
23140 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23141 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
23142 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23143 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23144 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v2f64] }:$src
23145 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23146 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23147 GIR_RootToRootCopy, /*OpIdx*/1, // src
23148 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
23149 // GIR_Coverage, 6461,
23150 GIR_EraseRootFromParent_Done,
23151 // Label 1303: @65491
23152 GIM_Try, /*On fail goto*//*Label 1304*/ GIMT_Encode4(65523), // Rule ID 6462 //
23153 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23154 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
23155 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23156 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23157 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[v2f64] }:$src
23158 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23159 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23160 GIR_RootToRootCopy, /*OpIdx*/1, // src
23161 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
23162 // GIR_Coverage, 6462,
23163 GIR_EraseRootFromParent_Done,
23164 // Label 1304: @65523
23165 GIM_Try, /*On fail goto*//*Label 1305*/ GIMT_Encode4(65555), // Rule ID 6463 //
23166 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23167 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
23168 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23169 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23170 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v2f64] }:$src
23171 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23172 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23173 GIR_RootToRootCopy, /*OpIdx*/1, // src
23174 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
23175 // GIR_Coverage, 6463,
23176 GIR_EraseRootFromParent_Done,
23177 // Label 1305: @65555
23178 GIM_Try, /*On fail goto*//*Label 1306*/ GIMT_Encode4(65587), // Rule ID 6464 //
23179 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23180 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23181 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23182 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23183 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v2f64] }:$src
23184 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23185 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23186 GIR_RootToRootCopy, /*OpIdx*/1, // src
23187 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
23188 // GIR_Coverage, 6464,
23189 GIR_EraseRootFromParent_Done,
23190 // Label 1306: @65587
23191 GIM_Try, /*On fail goto*//*Label 1307*/ GIMT_Encode4(65620), // Rule ID 6465 //
23192 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23193 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
23194 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23195 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23196 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v2f64] } FPR128:{ *:[f128] }:$src, FPR128:{ *:[f128] }:$src, 8:{ *:[i32] })
23197 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
23198 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23199 GIR_RootToRootCopy, /*OpIdx*/1, // src
23200 GIR_RootToRootCopy, /*OpIdx*/1, // src
23201 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
23202 GIR_RootConstrainSelectedInstOperands,
23203 // GIR_Coverage, 6465,
23204 GIR_EraseRootFromParent_Done,
23205 // Label 1307: @65620
23206 GIM_Try, /*On fail goto*//*Label 1308*/ GIMT_Encode4(65646), // Rule ID 6466 //
23207 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23208 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23209 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23210 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23211 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src) => (REV64v4i32:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src)
23212 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
23213 GIR_RootConstrainSelectedInstOperands,
23214 // GIR_Coverage, 6466,
23215 GIR_Done,
23216 // Label 1308: @65646
23217 GIM_Try, /*On fail goto*//*Label 1309*/ GIMT_Encode4(65672), // Rule ID 6467 //
23218 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23219 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
23220 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23221 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23222 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src) => (REV64v8i16:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src)
23223 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
23224 GIR_RootConstrainSelectedInstOperands,
23225 // GIR_Coverage, 6467,
23226 GIR_Done,
23227 // Label 1309: @65672
23228 GIM_Try, /*On fail goto*//*Label 1310*/ GIMT_Encode4(65698), // Rule ID 6468 //
23229 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23230 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
23231 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23232 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23233 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src) => (REV64v8i16:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src)
23234 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
23235 GIR_RootConstrainSelectedInstOperands,
23236 // GIR_Coverage, 6468,
23237 GIR_Done,
23238 // Label 1310: @65698
23239 GIM_Try, /*On fail goto*//*Label 1311*/ GIMT_Encode4(65724), // Rule ID 6469 //
23240 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23241 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
23242 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23243 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23244 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8bf16] }:$src) => (REV64v8i16:{ *:[v2f64] } FPR128:{ *:[v8bf16] }:$src)
23245 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
23246 GIR_RootConstrainSelectedInstOperands,
23247 // GIR_Coverage, 6469,
23248 GIR_Done,
23249 // Label 1311: @65724
23250 GIM_Try, /*On fail goto*//*Label 1312*/ GIMT_Encode4(65750), // Rule ID 6470 //
23251 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23252 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
23253 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23254 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23255 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src) => (REV64v16i8:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src)
23256 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
23257 GIR_RootConstrainSelectedInstOperands,
23258 // GIR_Coverage, 6470,
23259 GIR_Done,
23260 // Label 1312: @65750
23261 GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(65776), // Rule ID 6471 //
23262 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23263 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23264 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23265 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23266 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src) => (REV64v4i32:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src)
23267 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
23268 GIR_RootConstrainSelectedInstOperands,
23269 // GIR_Coverage, 6471,
23270 GIR_Done,
23271 // Label 1313: @65776
23272 GIM_Try, /*On fail goto*//*Label 1314*/ GIMT_Encode4(65805), // Rule ID 6472 //
23273 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23274 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23275 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23276 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v2f64] }:$src
23277 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23278 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23279 GIR_RootToRootCopy, /*OpIdx*/1, // src
23280 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
23281 // GIR_Coverage, 6472,
23282 GIR_EraseRootFromParent_Done,
23283 // Label 1314: @65805
23284 GIM_Try, /*On fail goto*//*Label 1315*/ GIMT_Encode4(65837), // Rule ID 6488 //
23285 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23286 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
23287 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23288 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23289 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v2i64] }:$src
23290 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23291 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23292 GIR_RootToRootCopy, /*OpIdx*/1, // src
23293 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
23294 // GIR_Coverage, 6488,
23295 GIR_EraseRootFromParent_Done,
23296 // Label 1315: @65837
23297 GIM_Try, /*On fail goto*//*Label 1316*/ GIMT_Encode4(65869), // Rule ID 6489 //
23298 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23299 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23300 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23301 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23302 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v2i64] }:$src
23303 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23304 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23305 GIR_RootToRootCopy, /*OpIdx*/1, // src
23306 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
23307 // GIR_Coverage, 6489,
23308 GIR_EraseRootFromParent_Done,
23309 // Label 1316: @65869
23310 GIM_Try, /*On fail goto*//*Label 1317*/ GIMT_Encode4(65901), // Rule ID 6490 //
23311 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23312 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
23313 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23314 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23315 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v2i64] }:$src
23316 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23317 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23318 GIR_RootToRootCopy, /*OpIdx*/1, // src
23319 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
23320 // GIR_Coverage, 6490,
23321 GIR_EraseRootFromParent_Done,
23322 // Label 1317: @65901
23323 GIM_Try, /*On fail goto*//*Label 1318*/ GIMT_Encode4(65933), // Rule ID 6491 //
23324 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23325 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
23326 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23327 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23328 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v2i64] }:$src
23329 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23330 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23331 GIR_RootToRootCopy, /*OpIdx*/1, // src
23332 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
23333 // GIR_Coverage, 6491,
23334 GIR_EraseRootFromParent_Done,
23335 // Label 1318: @65933
23336 GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(65965), // Rule ID 6492 //
23337 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23338 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23339 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23340 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23341 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v2i64] }:$src
23342 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23343 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23344 GIR_RootToRootCopy, /*OpIdx*/1, // src
23345 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
23346 // GIR_Coverage, 6492,
23347 GIR_EraseRootFromParent_Done,
23348 // Label 1319: @65965
23349 GIM_Try, /*On fail goto*//*Label 1320*/ GIMT_Encode4(65997), // Rule ID 6493 //
23350 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23351 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
23352 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23353 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23354 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v2i64] }:$src
23355 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23356 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23357 GIR_RootToRootCopy, /*OpIdx*/1, // src
23358 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
23359 // GIR_Coverage, 6493,
23360 GIR_EraseRootFromParent_Done,
23361 // Label 1320: @65997
23362 GIM_Try, /*On fail goto*//*Label 1321*/ GIMT_Encode4(66029), // Rule ID 6494 //
23363 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23364 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
23365 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23366 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23367 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[v2i64] }:$src
23368 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23369 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23370 GIR_RootToRootCopy, /*OpIdx*/1, // src
23371 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
23372 // GIR_Coverage, 6494,
23373 GIR_EraseRootFromParent_Done,
23374 // Label 1321: @66029
23375 GIM_Try, /*On fail goto*//*Label 1322*/ GIMT_Encode4(66062), // Rule ID 6495 //
23376 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23377 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
23378 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23379 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23380 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v2i64] } FPR128:{ *:[f128] }:$src, FPR128:{ *:[f128] }:$src, 8:{ *:[i32] })
23381 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
23382 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23383 GIR_RootToRootCopy, /*OpIdx*/1, // src
23384 GIR_RootToRootCopy, /*OpIdx*/1, // src
23385 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
23386 GIR_RootConstrainSelectedInstOperands,
23387 // GIR_Coverage, 6495,
23388 GIR_EraseRootFromParent_Done,
23389 // Label 1322: @66062
23390 GIM_Try, /*On fail goto*//*Label 1323*/ GIMT_Encode4(66088), // Rule ID 6496 //
23391 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23392 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23393 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23394 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23395 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src) => (REV64v4i32:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src)
23396 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
23397 GIR_RootConstrainSelectedInstOperands,
23398 // GIR_Coverage, 6496,
23399 GIR_Done,
23400 // Label 1323: @66088
23401 GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(66114), // Rule ID 6497 //
23402 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23403 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
23404 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23405 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23406 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src) => (REV64v8i16:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src)
23407 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
23408 GIR_RootConstrainSelectedInstOperands,
23409 // GIR_Coverage, 6497,
23410 GIR_Done,
23411 // Label 1324: @66114
23412 GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(66140), // Rule ID 6498 //
23413 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23414 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
23415 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23416 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23417 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src) => (REV64v16i8:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src)
23418 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
23419 GIR_RootConstrainSelectedInstOperands,
23420 // GIR_Coverage, 6498,
23421 GIR_Done,
23422 // Label 1325: @66140
23423 GIM_Try, /*On fail goto*//*Label 1326*/ GIMT_Encode4(66166), // Rule ID 6499 //
23424 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23425 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23426 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23427 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23428 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src) => (REV64v4i32:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src)
23429 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
23430 GIR_RootConstrainSelectedInstOperands,
23431 // GIR_Coverage, 6499,
23432 GIR_Done,
23433 // Label 1326: @66166
23434 GIM_Try, /*On fail goto*//*Label 1327*/ GIMT_Encode4(66192), // Rule ID 6500 //
23435 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23436 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
23437 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23438 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23439 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src) => (REV64v8i16:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src)
23440 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
23441 GIR_RootConstrainSelectedInstOperands,
23442 // GIR_Coverage, 6500,
23443 GIR_Done,
23444 // Label 1327: @66192
23445 GIM_Try, /*On fail goto*//*Label 1328*/ GIMT_Encode4(66218), // Rule ID 6501 //
23446 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23447 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
23448 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23449 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23450 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8bf16] }:$src) => (REV64v8i16:{ *:[v2i64] } FPR128:{ *:[v8bf16] }:$src)
23451 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
23452 GIR_RootConstrainSelectedInstOperands,
23453 // GIR_Coverage, 6501,
23454 GIR_Done,
23455 // Label 1328: @66218
23456 GIM_Try, /*On fail goto*//*Label 1329*/ GIMT_Encode4(66247), // Rule ID 6502 //
23457 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23458 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23459 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
23460 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v2i64] }:$src
23461 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23462 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23463 GIR_RootToRootCopy, /*OpIdx*/1, // src
23464 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
23465 // GIR_Coverage, 6502,
23466 GIR_EraseRootFromParent_Done,
23467 // Label 1329: @66247
23468 GIM_Reject,
23469 // Label 1163: @66248
23470 GIM_Try, /*On fail goto*//*Label 1330*/ GIMT_Encode4(66278), // Rule ID 6277 //
23471 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23472 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23473 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23474 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
23475 // (bitconvert:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
23476 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23477 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23478 // GIR_Coverage, 6277,
23479 GIR_Done,
23480 // Label 1330: @66278
23481 GIM_Try, /*On fail goto*//*Label 1331*/ GIMT_Encode4(66308), // Rule ID 6279 //
23482 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23483 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23484 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23485 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
23486 // (bitconvert:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
23487 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23488 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23489 // GIR_Coverage, 6279,
23490 GIR_Done,
23491 // Label 1331: @66308
23492 GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(66338), // Rule ID 6280 //
23493 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23494 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23495 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23496 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
23497 // (bitconvert:{ *:[v4bf16] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v4bf16] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
23498 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23499 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23500 // GIR_Coverage, 6280,
23501 GIR_Done,
23502 // Label 1332: @66338
23503 GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(66385), // Rule ID 6290 //
23504 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23505 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23506 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23507 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
23508 // (bitconvert:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn) => (REV64v4i16:{ *:[v4i16] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }))
23509 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
23510 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23511 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23512 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn
23513 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23514 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
23515 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23516 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23517 GIR_RootConstrainSelectedInstOperands,
23518 // GIR_Coverage, 6290,
23519 GIR_EraseRootFromParent_Done,
23520 // Label 1333: @66385
23521 GIM_Try, /*On fail goto*//*Label 1334*/ GIMT_Encode4(66432), // Rule ID 6292 //
23522 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23523 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23524 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23525 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
23526 // (bitconvert:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn) => (REV64v4i16:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }))
23527 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
23528 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23529 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23530 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn
23531 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23532 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
23533 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23534 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23535 GIR_RootConstrainSelectedInstOperands,
23536 // GIR_Coverage, 6292,
23537 GIR_EraseRootFromParent_Done,
23538 // Label 1334: @66432
23539 GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(66479), // Rule ID 6293 //
23540 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23541 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23542 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23543 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
23544 // (bitconvert:{ *:[v4bf16] } GPR64:{ *:[i64] }:$Xn) => (REV64v4i16:{ *:[v4bf16] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }))
23545 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
23546 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23547 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
23548 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn
23549 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23550 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
23551 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23552 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23553 GIR_RootConstrainSelectedInstOperands,
23554 // GIR_Coverage, 6293,
23555 GIR_EraseRootFromParent_Done,
23556 // Label 1335: @66479
23557 GIM_Try, /*On fail goto*//*Label 1336*/ GIMT_Encode4(66511), // Rule ID 6343 //
23558 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23559 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23560 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23561 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23562 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v4i16] }:$src
23563 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23564 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23565 GIR_RootToRootCopy, /*OpIdx*/1, // src
23566 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23567 // GIR_Coverage, 6343,
23568 GIR_EraseRootFromParent_Done,
23569 // Label 1336: @66511
23570 GIM_Try, /*On fail goto*//*Label 1337*/ GIMT_Encode4(66543), // Rule ID 6344 //
23571 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23572 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
23573 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23574 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23575 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v4i16] }:$src
23576 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23577 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23578 GIR_RootToRootCopy, /*OpIdx*/1, // src
23579 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23580 // GIR_Coverage, 6344,
23581 GIR_EraseRootFromParent_Done,
23582 // Label 1337: @66543
23583 GIM_Try, /*On fail goto*//*Label 1338*/ GIMT_Encode4(66575), // Rule ID 6345 //
23584 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23585 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
23586 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23587 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23588 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v4i16] }:$src
23589 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23590 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23591 GIR_RootToRootCopy, /*OpIdx*/1, // src
23592 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23593 // GIR_Coverage, 6345,
23594 GIR_EraseRootFromParent_Done,
23595 // Label 1338: @66575
23596 GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(66607), // Rule ID 6346 //
23597 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23598 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23599 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23600 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23601 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v4i16] }:$src
23602 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23603 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23604 GIR_RootToRootCopy, /*OpIdx*/1, // src
23605 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23606 // GIR_Coverage, 6346,
23607 GIR_EraseRootFromParent_Done,
23608 // Label 1339: @66607
23609 GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(66639), // Rule ID 6347 //
23610 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23611 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
23612 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23613 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23614 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v4i16] }:$src
23615 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23616 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23617 GIR_RootToRootCopy, /*OpIdx*/1, // src
23618 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23619 // GIR_Coverage, 6347,
23620 GIR_EraseRootFromParent_Done,
23621 // Label 1340: @66639
23622 GIM_Try, /*On fail goto*//*Label 1341*/ GIMT_Encode4(66671), // Rule ID 6348 //
23623 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23624 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23625 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23626 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23627 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v4i16] }:$src
23628 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23629 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23630 GIR_RootToRootCopy, /*OpIdx*/1, // src
23631 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23632 // GIR_Coverage, 6348,
23633 GIR_EraseRootFromParent_Done,
23634 // Label 1341: @66671
23635 GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(66697), // Rule ID 6349 //
23636 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23637 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23638 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23639 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23640 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src) => (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src)
23641 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
23642 GIR_RootConstrainSelectedInstOperands,
23643 // GIR_Coverage, 6349,
23644 GIR_Done,
23645 // Label 1342: @66697
23646 GIM_Try, /*On fail goto*//*Label 1343*/ GIMT_Encode4(66723), // Rule ID 6350 //
23647 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23648 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
23649 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23650 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23651 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src) => (REV32v4i16:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src)
23652 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
23653 GIR_RootConstrainSelectedInstOperands,
23654 // GIR_Coverage, 6350,
23655 GIR_Done,
23656 // Label 1343: @66723
23657 GIM_Try, /*On fail goto*//*Label 1344*/ GIMT_Encode4(66749), // Rule ID 6351 //
23658 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23659 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
23660 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23661 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23662 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src) => (REV16v8i8:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src)
23663 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
23664 GIR_RootConstrainSelectedInstOperands,
23665 // GIR_Coverage, 6351,
23666 GIR_Done,
23667 // Label 1344: @66749
23668 GIM_Try, /*On fail goto*//*Label 1345*/ GIMT_Encode4(66775), // Rule ID 6352 //
23669 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23670 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23671 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23672 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23673 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[f64] }:$src) => (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[f64] }:$src)
23674 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
23675 GIR_RootConstrainSelectedInstOperands,
23676 // GIR_Coverage, 6352,
23677 GIR_Done,
23678 // Label 1345: @66775
23679 GIM_Try, /*On fail goto*//*Label 1346*/ GIMT_Encode4(66801), // Rule ID 6353 //
23680 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23681 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
23682 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23683 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23684 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src) => (REV32v4i16:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src)
23685 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
23686 GIR_RootConstrainSelectedInstOperands,
23687 // GIR_Coverage, 6353,
23688 GIR_Done,
23689 // Label 1346: @66801
23690 GIM_Try, /*On fail goto*//*Label 1347*/ GIMT_Encode4(66827), // Rule ID 6354 //
23691 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23692 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23693 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23694 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23695 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src) => (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src)
23696 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
23697 GIR_RootConstrainSelectedInstOperands,
23698 // GIR_Coverage, 6354,
23699 GIR_Done,
23700 // Label 1347: @66827
23701 GIM_Try, /*On fail goto*//*Label 1348*/ GIMT_Encode4(66856), // Rule ID 6355 //
23702 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
23703 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23704 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23705 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v4i16] }:$src
23706 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23707 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23708 GIR_RootToRootCopy, /*OpIdx*/1, // src
23709 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23710 // GIR_Coverage, 6355,
23711 GIR_EraseRootFromParent_Done,
23712 // Label 1348: @66856
23713 GIM_Try, /*On fail goto*//*Label 1349*/ GIMT_Encode4(66885), // Rule ID 6356 //
23714 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
23715 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23716 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23717 // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[v4i16] }:$src
23718 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23719 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23720 GIR_RootToRootCopy, /*OpIdx*/1, // src
23721 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23722 // GIR_Coverage, 6356,
23723 GIR_EraseRootFromParent_Done,
23724 // Label 1349: @66885
23725 GIM_Try, /*On fail goto*//*Label 1350*/ GIMT_Encode4(66917), // Rule ID 6357 //
23726 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23727 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23728 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23729 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23730 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v4f16] }:$src
23731 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23732 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23733 GIR_RootToRootCopy, /*OpIdx*/1, // src
23734 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23735 // GIR_Coverage, 6357,
23736 GIR_EraseRootFromParent_Done,
23737 // Label 1350: @66917
23738 GIM_Try, /*On fail goto*//*Label 1351*/ GIMT_Encode4(66949), // Rule ID 6358 //
23739 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23740 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
23741 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23742 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23743 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v4f16] }:$src
23744 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23745 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23746 GIR_RootToRootCopy, /*OpIdx*/1, // src
23747 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23748 // GIR_Coverage, 6358,
23749 GIR_EraseRootFromParent_Done,
23750 // Label 1351: @66949
23751 GIM_Try, /*On fail goto*//*Label 1352*/ GIMT_Encode4(66981), // Rule ID 6359 //
23752 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23753 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
23754 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23755 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23756 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v4f16] }:$src
23757 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23758 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23759 GIR_RootToRootCopy, /*OpIdx*/1, // src
23760 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23761 // GIR_Coverage, 6359,
23762 GIR_EraseRootFromParent_Done,
23763 // Label 1352: @66981
23764 GIM_Try, /*On fail goto*//*Label 1353*/ GIMT_Encode4(67013), // Rule ID 6360 //
23765 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23766 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23767 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23768 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23769 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v4f16] }:$src
23770 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23771 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23772 GIR_RootToRootCopy, /*OpIdx*/1, // src
23773 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23774 // GIR_Coverage, 6360,
23775 GIR_EraseRootFromParent_Done,
23776 // Label 1353: @67013
23777 GIM_Try, /*On fail goto*//*Label 1354*/ GIMT_Encode4(67045), // Rule ID 6361 //
23778 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23779 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
23780 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23781 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23782 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v4f16] }:$src
23783 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23784 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23785 GIR_RootToRootCopy, /*OpIdx*/1, // src
23786 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23787 // GIR_Coverage, 6361,
23788 GIR_EraseRootFromParent_Done,
23789 // Label 1354: @67045
23790 GIM_Try, /*On fail goto*//*Label 1355*/ GIMT_Encode4(67077), // Rule ID 6362 //
23791 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23792 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23793 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23794 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23795 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v4f16] }:$src
23796 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23797 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23798 GIR_RootToRootCopy, /*OpIdx*/1, // src
23799 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23800 // GIR_Coverage, 6362,
23801 GIR_EraseRootFromParent_Done,
23802 // Label 1355: @67077
23803 GIM_Try, /*On fail goto*//*Label 1356*/ GIMT_Encode4(67109), // Rule ID 6363 //
23804 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23805 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23806 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23807 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23808 // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v4bf16] }:$src
23809 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23810 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23811 GIR_RootToRootCopy, /*OpIdx*/1, // src
23812 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23813 // GIR_Coverage, 6363,
23814 GIR_EraseRootFromParent_Done,
23815 // Label 1356: @67109
23816 GIM_Try, /*On fail goto*//*Label 1357*/ GIMT_Encode4(67141), // Rule ID 6364 //
23817 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23818 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
23819 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23820 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23821 // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v4bf16] }:$src
23822 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23823 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23824 GIR_RootToRootCopy, /*OpIdx*/1, // src
23825 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23826 // GIR_Coverage, 6364,
23827 GIR_EraseRootFromParent_Done,
23828 // Label 1357: @67141
23829 GIM_Try, /*On fail goto*//*Label 1358*/ GIMT_Encode4(67173), // Rule ID 6365 //
23830 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23831 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
23832 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23833 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23834 // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v4bf16] }:$src
23835 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23836 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23837 GIR_RootToRootCopy, /*OpIdx*/1, // src
23838 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23839 // GIR_Coverage, 6365,
23840 GIR_EraseRootFromParent_Done,
23841 // Label 1358: @67173
23842 GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(67205), // Rule ID 6366 //
23843 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23844 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23845 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23846 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23847 // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v4bf16] }:$src
23848 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23849 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23850 GIR_RootToRootCopy, /*OpIdx*/1, // src
23851 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23852 // GIR_Coverage, 6366,
23853 GIR_EraseRootFromParent_Done,
23854 // Label 1359: @67205
23855 GIM_Try, /*On fail goto*//*Label 1360*/ GIMT_Encode4(67237), // Rule ID 6367 //
23856 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23857 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
23858 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23859 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23860 // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v4bf16] }:$src
23861 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23862 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23863 GIR_RootToRootCopy, /*OpIdx*/1, // src
23864 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23865 // GIR_Coverage, 6367,
23866 GIR_EraseRootFromParent_Done,
23867 // Label 1360: @67237
23868 GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(67269), // Rule ID 6368 //
23869 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
23870 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23871 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23872 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23873 // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v4bf16] }:$src
23874 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23875 GIR_RootToRootCopy, /*OpIdx*/0, // dst
23876 GIR_RootToRootCopy, /*OpIdx*/1, // src
23877 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
23878 // GIR_Coverage, 6368,
23879 GIR_EraseRootFromParent_Done,
23880 // Label 1361: @67269
23881 GIM_Try, /*On fail goto*//*Label 1362*/ GIMT_Encode4(67295), // Rule ID 6369 //
23882 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23883 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23884 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23885 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23886 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src) => (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src)
23887 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
23888 GIR_RootConstrainSelectedInstOperands,
23889 // GIR_Coverage, 6369,
23890 GIR_Done,
23891 // Label 1362: @67295
23892 GIM_Try, /*On fail goto*//*Label 1363*/ GIMT_Encode4(67321), // Rule ID 6370 //
23893 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23894 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
23895 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23896 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23897 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src) => (REV32v4i16:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src)
23898 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
23899 GIR_RootConstrainSelectedInstOperands,
23900 // GIR_Coverage, 6370,
23901 GIR_Done,
23902 // Label 1363: @67321
23903 GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(67347), // Rule ID 6371 //
23904 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23905 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
23906 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23907 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23908 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src) => (REV16v8i8:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src)
23909 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
23910 GIR_RootConstrainSelectedInstOperands,
23911 // GIR_Coverage, 6371,
23912 GIR_Done,
23913 // Label 1364: @67347
23914 GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(67373), // Rule ID 6372 //
23915 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23916 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23917 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23918 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23919 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[f64] }:$src) => (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[f64] }:$src)
23920 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
23921 GIR_RootConstrainSelectedInstOperands,
23922 // GIR_Coverage, 6372,
23923 GIR_Done,
23924 // Label 1365: @67373
23925 GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(67399), // Rule ID 6373 //
23926 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23927 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
23928 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23929 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23930 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src) => (REV32v4i16:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src)
23931 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
23932 GIR_RootConstrainSelectedInstOperands,
23933 // GIR_Coverage, 6373,
23934 GIR_Done,
23935 // Label 1366: @67399
23936 GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(67425), // Rule ID 6374 //
23937 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23938 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23939 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23940 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23941 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src) => (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src)
23942 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
23943 GIR_RootConstrainSelectedInstOperands,
23944 // GIR_Coverage, 6374,
23945 GIR_Done,
23946 // Label 1367: @67425
23947 GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(67451), // Rule ID 6375 //
23948 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23949 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23950 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23951 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23952 // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v1i64] }:$src) => (REV64v4i16:{ *:[v4bf16] } FPR64:{ *:[v1i64] }:$src)
23953 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
23954 GIR_RootConstrainSelectedInstOperands,
23955 // GIR_Coverage, 6375,
23956 GIR_Done,
23957 // Label 1368: @67451
23958 GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(67477), // Rule ID 6376 //
23959 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23960 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
23961 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23962 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23963 // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v2i32] }:$src) => (REV32v4i16:{ *:[v4bf16] } FPR64:{ *:[v2i32] }:$src)
23964 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
23965 GIR_RootConstrainSelectedInstOperands,
23966 // GIR_Coverage, 6376,
23967 GIR_Done,
23968 // Label 1369: @67477
23969 GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(67503), // Rule ID 6377 //
23970 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23971 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
23972 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23973 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23974 // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v8i8] }:$src) => (REV16v8i8:{ *:[v4bf16] } FPR64:{ *:[v8i8] }:$src)
23975 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
23976 GIR_RootConstrainSelectedInstOperands,
23977 // GIR_Coverage, 6377,
23978 GIR_Done,
23979 // Label 1370: @67503
23980 GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(67529), // Rule ID 6378 //
23981 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23982 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23983 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23984 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23985 // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[f64] }:$src) => (REV64v4i16:{ *:[v4bf16] } FPR64:{ *:[f64] }:$src)
23986 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
23987 GIR_RootConstrainSelectedInstOperands,
23988 // GIR_Coverage, 6378,
23989 GIR_Done,
23990 // Label 1371: @67529
23991 GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(67555), // Rule ID 6379 //
23992 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
23993 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
23994 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23995 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
23996 // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v2f32] }:$src) => (REV32v4i16:{ *:[v4bf16] } FPR64:{ *:[v2f32] }:$src)
23997 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
23998 GIR_RootConstrainSelectedInstOperands,
23999 // GIR_Coverage, 6379,
24000 GIR_Done,
24001 // Label 1372: @67555
24002 GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(67581), // Rule ID 6380 //
24003 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24004 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24005 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24006 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24007 // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v1f64] }:$src) => (REV64v4i16:{ *:[v4bf16] } FPR64:{ *:[v1f64] }:$src)
24008 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
24009 GIR_RootConstrainSelectedInstOperands,
24010 // GIR_Coverage, 6380,
24011 GIR_Done,
24012 // Label 1373: @67581
24013 GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(67610), // Rule ID 6381 //
24014 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
24015 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24016 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24017 // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v4f16] }:$src
24018 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24019 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24020 GIR_RootToRootCopy, /*OpIdx*/1, // src
24021 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
24022 // GIR_Coverage, 6381,
24023 GIR_EraseRootFromParent_Done,
24024 // Label 1374: @67610
24025 GIM_Try, /*On fail goto*//*Label 1375*/ GIMT_Encode4(67639), // Rule ID 6382 //
24026 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
24027 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24028 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24029 // (bitconvert:{ *:[v4bf16] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v4bf16] }:$src
24030 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24031 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24032 GIR_RootToRootCopy, /*OpIdx*/1, // src
24033 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
24034 // GIR_Coverage, 6382,
24035 GIR_EraseRootFromParent_Done,
24036 // Label 1375: @67639
24037 GIM_Reject,
24038 // Label 1164: @67640
24039 GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(67672), // Rule ID 6473 //
24040 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24041 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
24042 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24043 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24044 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v4f32] }:$src
24045 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24046 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24047 GIR_RootToRootCopy, /*OpIdx*/1, // src
24048 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24049 // GIR_Coverage, 6473,
24050 GIR_EraseRootFromParent_Done,
24051 // Label 1376: @67672
24052 GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(67704), // Rule ID 6474 //
24053 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24054 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24055 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24056 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24057 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v4f32] }:$src
24058 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24059 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24060 GIR_RootToRootCopy, /*OpIdx*/1, // src
24061 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24062 // GIR_Coverage, 6474,
24063 GIR_EraseRootFromParent_Done,
24064 // Label 1377: @67704
24065 GIM_Try, /*On fail goto*//*Label 1378*/ GIMT_Encode4(67736), // Rule ID 6475 //
24066 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24067 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24068 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24069 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24070 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v4f32] }:$src
24071 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24072 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24073 GIR_RootToRootCopy, /*OpIdx*/1, // src
24074 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24075 // GIR_Coverage, 6475,
24076 GIR_EraseRootFromParent_Done,
24077 // Label 1378: @67736
24078 GIM_Try, /*On fail goto*//*Label 1379*/ GIMT_Encode4(67768), // Rule ID 6476 //
24079 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24080 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24081 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24082 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24083 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[v4f32] }:$src
24084 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24085 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24086 GIR_RootToRootCopy, /*OpIdx*/1, // src
24087 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24088 // GIR_Coverage, 6476,
24089 GIR_EraseRootFromParent_Done,
24090 // Label 1379: @67768
24091 GIM_Try, /*On fail goto*//*Label 1380*/ GIMT_Encode4(67800), // Rule ID 6477 //
24092 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24093 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24094 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24095 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24096 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v4f32] }:$src
24097 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24098 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24099 GIR_RootToRootCopy, /*OpIdx*/1, // src
24100 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24101 // GIR_Coverage, 6477,
24102 GIR_EraseRootFromParent_Done,
24103 // Label 1380: @67800
24104 GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(67832), // Rule ID 6478 //
24105 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24106 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24107 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24108 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24109 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v4f32] }:$src
24110 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24111 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24112 GIR_RootToRootCopy, /*OpIdx*/1, // src
24113 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24114 // GIR_Coverage, 6478,
24115 GIR_EraseRootFromParent_Done,
24116 // Label 1381: @67832
24117 GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(67864), // Rule ID 6479 //
24118 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24119 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24120 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24121 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24122 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v4f32] }:$src
24123 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24124 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24125 GIR_RootToRootCopy, /*OpIdx*/1, // src
24126 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24127 // GIR_Coverage, 6479,
24128 GIR_EraseRootFromParent_Done,
24129 // Label 1382: @67864
24130 GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(67935), // Rule ID 6480 //
24131 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24132 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
24133 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24134 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24135 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v4f32] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] })
24136 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
24137 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
24138 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
24139 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24140 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
24141 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
24142 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
24143 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24144 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
24145 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24146 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
24147 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
24148 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24149 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
24150 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
24151 GIR_RootConstrainSelectedInstOperands,
24152 // GIR_Coverage, 6480,
24153 GIR_EraseRootFromParent_Done,
24154 // Label 1383: @67935
24155 GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(67961), // Rule ID 6481 //
24156 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24157 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24158 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24159 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24160 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src) => (REV32v8i16:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src)
24161 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
24162 GIR_RootConstrainSelectedInstOperands,
24163 // GIR_Coverage, 6481,
24164 GIR_Done,
24165 // Label 1384: @67961
24166 GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(67987), // Rule ID 6482 //
24167 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24168 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24169 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24170 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24171 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src) => (REV32v8i16:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src)
24172 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
24173 GIR_RootConstrainSelectedInstOperands,
24174 // GIR_Coverage, 6482,
24175 GIR_Done,
24176 // Label 1385: @67987
24177 GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(68013), // Rule ID 6483 //
24178 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24179 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24180 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24181 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24182 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8bf16] }:$src) => (REV32v8i16:{ *:[v4f32] } FPR128:{ *:[v8bf16] }:$src)
24183 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
24184 GIR_RootConstrainSelectedInstOperands,
24185 // GIR_Coverage, 6483,
24186 GIR_Done,
24187 // Label 1386: @68013
24188 GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(68039), // Rule ID 6484 //
24189 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24190 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24191 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24192 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24193 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src) => (REV32v16i8:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src)
24194 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v16i8),
24195 GIR_RootConstrainSelectedInstOperands,
24196 // GIR_Coverage, 6484,
24197 GIR_Done,
24198 // Label 1387: @68039
24199 GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(68065), // Rule ID 6485 //
24200 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24201 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24202 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24203 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24204 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src) => (REV64v4i32:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src)
24205 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
24206 GIR_RootConstrainSelectedInstOperands,
24207 // GIR_Coverage, 6485,
24208 GIR_Done,
24209 // Label 1388: @68065
24210 GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(68091), // Rule ID 6486 //
24211 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24212 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24213 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24214 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24215 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src) => (REV64v4i32:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src)
24216 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
24217 GIR_RootConstrainSelectedInstOperands,
24218 // GIR_Coverage, 6486,
24219 GIR_Done,
24220 // Label 1389: @68091
24221 GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(68120), // Rule ID 6487 //
24222 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24223 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24224 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24225 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v4f32] }:$src
24226 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24227 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24228 GIR_RootToRootCopy, /*OpIdx*/1, // src
24229 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24230 // GIR_Coverage, 6487,
24231 GIR_EraseRootFromParent_Done,
24232 // Label 1390: @68120
24233 GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(68152), // Rule ID 6503 //
24234 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24235 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
24236 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24237 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24238 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v4i32] }:$src
24239 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24240 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24241 GIR_RootToRootCopy, /*OpIdx*/1, // src
24242 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24243 // GIR_Coverage, 6503,
24244 GIR_EraseRootFromParent_Done,
24245 // Label 1391: @68152
24246 GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(68184), // Rule ID 6504 //
24247 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24248 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24249 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24250 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24251 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v4i32] }:$src
24252 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24253 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24254 GIR_RootToRootCopy, /*OpIdx*/1, // src
24255 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24256 // GIR_Coverage, 6504,
24257 GIR_EraseRootFromParent_Done,
24258 // Label 1392: @68184
24259 GIM_Try, /*On fail goto*//*Label 1393*/ GIMT_Encode4(68216), // Rule ID 6505 //
24260 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24261 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24262 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24263 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24264 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v4i32] }:$src
24265 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24266 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24267 GIR_RootToRootCopy, /*OpIdx*/1, // src
24268 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24269 // GIR_Coverage, 6505,
24270 GIR_EraseRootFromParent_Done,
24271 // Label 1393: @68216
24272 GIM_Try, /*On fail goto*//*Label 1394*/ GIMT_Encode4(68248), // Rule ID 6506 //
24273 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24274 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24275 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24276 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24277 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v4i32] }:$src
24278 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24279 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24280 GIR_RootToRootCopy, /*OpIdx*/1, // src
24281 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24282 // GIR_Coverage, 6506,
24283 GIR_EraseRootFromParent_Done,
24284 // Label 1394: @68248
24285 GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(68280), // Rule ID 6507 //
24286 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24287 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24288 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24289 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24290 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v4i32] }:$src
24291 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24292 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24293 GIR_RootToRootCopy, /*OpIdx*/1, // src
24294 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24295 // GIR_Coverage, 6507,
24296 GIR_EraseRootFromParent_Done,
24297 // Label 1395: @68280
24298 GIM_Try, /*On fail goto*//*Label 1396*/ GIMT_Encode4(68312), // Rule ID 6508 //
24299 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24300 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24301 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24302 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24303 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v4i32] }:$src
24304 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24305 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24306 GIR_RootToRootCopy, /*OpIdx*/1, // src
24307 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24308 // GIR_Coverage, 6508,
24309 GIR_EraseRootFromParent_Done,
24310 // Label 1396: @68312
24311 GIM_Try, /*On fail goto*//*Label 1397*/ GIMT_Encode4(68344), // Rule ID 6509 //
24312 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24313 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24314 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24315 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24316 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[v4i32] }:$src
24317 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24318 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24319 GIR_RootToRootCopy, /*OpIdx*/1, // src
24320 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24321 // GIR_Coverage, 6509,
24322 GIR_EraseRootFromParent_Done,
24323 // Label 1397: @68344
24324 GIM_Try, /*On fail goto*//*Label 1398*/ GIMT_Encode4(68415), // Rule ID 6510 //
24325 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24326 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
24327 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24328 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24329 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v4i32] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] })
24330 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
24331 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
24332 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
24333 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24334 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
24335 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
24336 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
24337 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24338 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
24339 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24340 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
24341 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
24342 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24343 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
24344 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
24345 GIR_RootConstrainSelectedInstOperands,
24346 // GIR_Coverage, 6510,
24347 GIR_EraseRootFromParent_Done,
24348 // Label 1398: @68415
24349 GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(68441), // Rule ID 6511 //
24350 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24351 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24352 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24353 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24354 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src) => (REV64v4i32:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src)
24355 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
24356 GIR_RootConstrainSelectedInstOperands,
24357 // GIR_Coverage, 6511,
24358 GIR_Done,
24359 // Label 1399: @68441
24360 GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(68467), // Rule ID 6512 //
24361 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24362 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24363 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24364 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24365 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src) => (REV32v8i16:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src)
24366 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
24367 GIR_RootConstrainSelectedInstOperands,
24368 // GIR_Coverage, 6512,
24369 GIR_Done,
24370 // Label 1400: @68467
24371 GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(68493), // Rule ID 6513 //
24372 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24373 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24374 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24375 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24376 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src) => (REV32v16i8:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src)
24377 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v16i8),
24378 GIR_RootConstrainSelectedInstOperands,
24379 // GIR_Coverage, 6513,
24380 GIR_Done,
24381 // Label 1401: @68493
24382 GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(68519), // Rule ID 6514 //
24383 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24384 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24385 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24386 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24387 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src) => (REV64v4i32:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src)
24388 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
24389 GIR_RootConstrainSelectedInstOperands,
24390 // GIR_Coverage, 6514,
24391 GIR_Done,
24392 // Label 1402: @68519
24393 GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(68545), // Rule ID 6515 //
24394 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24395 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24396 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24397 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24398 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src) => (REV32v8i16:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src)
24399 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
24400 GIR_RootConstrainSelectedInstOperands,
24401 // GIR_Coverage, 6515,
24402 GIR_Done,
24403 // Label 1403: @68545
24404 GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(68571), // Rule ID 6516 //
24405 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24406 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24407 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24408 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24409 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8bf16] }:$src) => (REV32v8i16:{ *:[v4i32] } FPR128:{ *:[v8bf16] }:$src)
24410 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
24411 GIR_RootConstrainSelectedInstOperands,
24412 // GIR_Coverage, 6516,
24413 GIR_Done,
24414 // Label 1404: @68571
24415 GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(68600), // Rule ID 6517 //
24416 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24417 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24418 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24419 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v4i32] }:$src
24420 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24421 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24422 GIR_RootToRootCopy, /*OpIdx*/1, // src
24423 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24424 // GIR_Coverage, 6517,
24425 GIR_EraseRootFromParent_Done,
24426 // Label 1405: @68600
24427 GIM_Reject,
24428 // Label 1165: @68601
24429 GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(68675), // Rule ID 5320 //
24430 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24431 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24432 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24433 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
24434 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24435 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
24436 GIM_CheckIsSafeToFold, /*NumInsns*/1,
24437 // (bitconvert:{ *:[v8i8] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn)) => (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i32] }, (FMOVWSr:{ *:[f32] } GPR32:{ *:[i32] }:$Rn), ssub:{ *:[i32] })
24438 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24439 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVWSr),
24440 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24441 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
24442 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24443 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
24444 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24445 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24446 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24447 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
24448 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
24449 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
24450 // GIR_Coverage, 5320,
24451 GIR_EraseRootFromParent_Done,
24452 // Label 1406: @68675
24453 GIM_Try, /*On fail goto*//*Label 1407*/ GIMT_Encode4(68705), // Rule ID 6276 //
24454 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24455 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24456 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24457 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
24458 // (bitconvert:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
24459 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24460 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
24461 // GIR_Coverage, 6276,
24462 GIR_Done,
24463 // Label 1407: @68705
24464 GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(68752), // Rule ID 6289 //
24465 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24466 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24467 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24468 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
24469 // (bitconvert:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn) => (REV64v8i8:{ *:[v8i8] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }))
24470 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
24471 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24472 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24473 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn
24474 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24475 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
24476 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
24477 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24478 GIR_RootConstrainSelectedInstOperands,
24479 // GIR_Coverage, 6289,
24480 GIR_EraseRootFromParent_Done,
24481 // Label 1408: @68752
24482 GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(68784), // Rule ID 6383 //
24483 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24484 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24485 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24486 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24487 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src) => FPR64:{ *:[v8i8] }:$src
24488 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24489 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24490 GIR_RootToRootCopy, /*OpIdx*/1, // src
24491 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
24492 // GIR_Coverage, 6383,
24493 GIR_EraseRootFromParent_Done,
24494 // Label 1409: @68784
24495 GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(68816), // Rule ID 6384 //
24496 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24497 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
24498 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24499 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24500 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v8i8] }:$src
24501 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24502 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24503 GIR_RootToRootCopy, /*OpIdx*/1, // src
24504 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
24505 // GIR_Coverage, 6384,
24506 GIR_EraseRootFromParent_Done,
24507 // Label 1410: @68816
24508 GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(68848), // Rule ID 6385 //
24509 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24510 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
24511 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24512 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24513 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v8i8] }:$src
24514 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24515 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24516 GIR_RootToRootCopy, /*OpIdx*/1, // src
24517 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
24518 // GIR_Coverage, 6385,
24519 GIR_EraseRootFromParent_Done,
24520 // Label 1411: @68848
24521 GIM_Try, /*On fail goto*//*Label 1412*/ GIMT_Encode4(68880), // Rule ID 6386 //
24522 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24523 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24524 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24525 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24526 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[f64] }:$src) => FPR64:{ *:[v8i8] }:$src
24527 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24528 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24529 GIR_RootToRootCopy, /*OpIdx*/1, // src
24530 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
24531 // GIR_Coverage, 6386,
24532 GIR_EraseRootFromParent_Done,
24533 // Label 1412: @68880
24534 GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(68912), // Rule ID 6387 //
24535 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24536 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
24537 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24538 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24539 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src) => FPR64:{ *:[v8i8] }:$src
24540 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24541 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24542 GIR_RootToRootCopy, /*OpIdx*/1, // src
24543 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
24544 // GIR_Coverage, 6387,
24545 GIR_EraseRootFromParent_Done,
24546 // Label 1413: @68912
24547 GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(68944), // Rule ID 6388 //
24548 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24549 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24550 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24551 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24552 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v8i8] }:$src
24553 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24554 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24555 GIR_RootToRootCopy, /*OpIdx*/1, // src
24556 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
24557 // GIR_Coverage, 6388,
24558 GIR_EraseRootFromParent_Done,
24559 // Label 1414: @68944
24560 GIM_Try, /*On fail goto*//*Label 1415*/ GIMT_Encode4(68976), // Rule ID 6389 //
24561 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24562 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
24563 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24564 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24565 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src) => FPR64:{ *:[v8i8] }:$src
24566 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24567 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24568 GIR_RootToRootCopy, /*OpIdx*/1, // src
24569 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
24570 // GIR_Coverage, 6389,
24571 GIR_EraseRootFromParent_Done,
24572 // Label 1415: @68976
24573 GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(69008), // Rule ID 6390 //
24574 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24575 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
24576 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24577 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24578 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4bf16] }:$src) => FPR64:{ *:[v8i8] }:$src
24579 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24580 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24581 GIR_RootToRootCopy, /*OpIdx*/1, // src
24582 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
24583 // GIR_Coverage, 6390,
24584 GIR_EraseRootFromParent_Done,
24585 // Label 1416: @69008
24586 GIM_Try, /*On fail goto*//*Label 1417*/ GIMT_Encode4(69034), // Rule ID 6391 //
24587 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24588 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24589 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24590 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24591 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src) => (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src)
24592 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
24593 GIR_RootConstrainSelectedInstOperands,
24594 // GIR_Coverage, 6391,
24595 GIR_Done,
24596 // Label 1417: @69034
24597 GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(69060), // Rule ID 6392 //
24598 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24599 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
24600 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24601 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24602 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src) => (REV32v8i8:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src)
24603 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i8),
24604 GIR_RootConstrainSelectedInstOperands,
24605 // GIR_Coverage, 6392,
24606 GIR_Done,
24607 // Label 1418: @69060
24608 GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(69086), // Rule ID 6393 //
24609 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24610 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
24611 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24612 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24613 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src) => (REV16v8i8:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src)
24614 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
24615 GIR_RootConstrainSelectedInstOperands,
24616 // GIR_Coverage, 6393,
24617 GIR_Done,
24618 // Label 1419: @69086
24619 GIM_Try, /*On fail goto*//*Label 1420*/ GIMT_Encode4(69112), // Rule ID 6394 //
24620 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24621 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24622 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24623 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24624 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[f64] }:$src) => (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[f64] }:$src)
24625 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
24626 GIR_RootConstrainSelectedInstOperands,
24627 // GIR_Coverage, 6394,
24628 GIR_Done,
24629 // Label 1420: @69112
24630 GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(69138), // Rule ID 6395 //
24631 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24632 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
24633 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24634 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24635 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src) => (REV32v8i8:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src)
24636 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i8),
24637 GIR_RootConstrainSelectedInstOperands,
24638 // GIR_Coverage, 6395,
24639 GIR_Done,
24640 // Label 1421: @69138
24641 GIM_Try, /*On fail goto*//*Label 1422*/ GIMT_Encode4(69164), // Rule ID 6396 //
24642 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24643 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24644 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24645 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24646 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src) => (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src)
24647 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
24648 GIR_RootConstrainSelectedInstOperands,
24649 // GIR_Coverage, 6396,
24650 GIR_Done,
24651 // Label 1422: @69164
24652 GIM_Try, /*On fail goto*//*Label 1423*/ GIMT_Encode4(69190), // Rule ID 6397 //
24653 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24654 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
24655 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24656 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24657 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src) => (REV16v8i8:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src)
24658 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
24659 GIR_RootConstrainSelectedInstOperands,
24660 // GIR_Coverage, 6397,
24661 GIR_Done,
24662 // Label 1423: @69190
24663 GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(69216), // Rule ID 6398 //
24664 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24665 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
24666 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24667 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
24668 // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4bf16] }:$src) => (REV16v8i8:{ *:[v8i8] } FPR64:{ *:[v4bf16] }:$src)
24669 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
24670 GIR_RootConstrainSelectedInstOperands,
24671 // GIR_Coverage, 6398,
24672 GIR_Done,
24673 // Label 1424: @69216
24674 GIM_Reject,
24675 // Label 1166: @69217
24676 GIM_Try, /*On fail goto*//*Label 1425*/ GIMT_Encode4(69249), // Rule ID 6518 //
24677 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24678 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
24679 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24680 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24681 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v8i16] }:$src
24682 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24683 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24684 GIR_RootToRootCopy, /*OpIdx*/1, // src
24685 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24686 // GIR_Coverage, 6518,
24687 GIR_EraseRootFromParent_Done,
24688 // Label 1425: @69249
24689 GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(69281), // Rule ID 6519 //
24690 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24691 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24692 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24693 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24694 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v8i16] }:$src
24695 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24696 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24697 GIR_RootToRootCopy, /*OpIdx*/1, // src
24698 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24699 // GIR_Coverage, 6519,
24700 GIR_EraseRootFromParent_Done,
24701 // Label 1426: @69281
24702 GIM_Try, /*On fail goto*//*Label 1427*/ GIMT_Encode4(69313), // Rule ID 6520 //
24703 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24704 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24705 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24706 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24707 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v8i16] }:$src
24708 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24709 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24710 GIR_RootToRootCopy, /*OpIdx*/1, // src
24711 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24712 // GIR_Coverage, 6520,
24713 GIR_EraseRootFromParent_Done,
24714 // Label 1427: @69313
24715 GIM_Try, /*On fail goto*//*Label 1428*/ GIMT_Encode4(69345), // Rule ID 6521 //
24716 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24717 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24718 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24719 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24720 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v8i16] }:$src
24721 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24722 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24723 GIR_RootToRootCopy, /*OpIdx*/1, // src
24724 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24725 // GIR_Coverage, 6521,
24726 GIR_EraseRootFromParent_Done,
24727 // Label 1428: @69345
24728 GIM_Try, /*On fail goto*//*Label 1429*/ GIMT_Encode4(69377), // Rule ID 6522 //
24729 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24730 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24731 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24732 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24733 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v8i16] }:$src
24734 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24735 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24736 GIR_RootToRootCopy, /*OpIdx*/1, // src
24737 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24738 // GIR_Coverage, 6522,
24739 GIR_EraseRootFromParent_Done,
24740 // Label 1429: @69377
24741 GIM_Try, /*On fail goto*//*Label 1430*/ GIMT_Encode4(69409), // Rule ID 6523 //
24742 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24743 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24744 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24745 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24746 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v8i16] }:$src
24747 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24748 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24749 GIR_RootToRootCopy, /*OpIdx*/1, // src
24750 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24751 // GIR_Coverage, 6523,
24752 GIR_EraseRootFromParent_Done,
24753 // Label 1430: @69409
24754 GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(69480), // Rule ID 6524 //
24755 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24756 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
24757 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24758 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24759 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v8i16] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] })
24760 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
24761 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
24762 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
24763 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24764 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
24765 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
24766 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
24767 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24768 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
24769 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24770 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
24771 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
24772 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24773 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
24774 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
24775 GIR_RootConstrainSelectedInstOperands,
24776 // GIR_Coverage, 6524,
24777 GIR_EraseRootFromParent_Done,
24778 // Label 1431: @69480
24779 GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(69506), // Rule ID 6525 //
24780 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24781 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24782 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24783 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24784 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src) => (REV64v8i16:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src)
24785 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
24786 GIR_RootConstrainSelectedInstOperands,
24787 // GIR_Coverage, 6525,
24788 GIR_Done,
24789 // Label 1432: @69506
24790 GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(69532), // Rule ID 6526 //
24791 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24792 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24793 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24794 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24795 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src) => (REV32v8i16:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src)
24796 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
24797 GIR_RootConstrainSelectedInstOperands,
24798 // GIR_Coverage, 6526,
24799 GIR_Done,
24800 // Label 1433: @69532
24801 GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(69558), // Rule ID 6527 //
24802 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24803 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24804 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24805 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24806 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src) => (REV16v16i8:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src)
24807 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
24808 GIR_RootConstrainSelectedInstOperands,
24809 // GIR_Coverage, 6527,
24810 GIR_Done,
24811 // Label 1434: @69558
24812 GIM_Try, /*On fail goto*//*Label 1435*/ GIMT_Encode4(69584), // Rule ID 6528 //
24813 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24814 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24815 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24816 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24817 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src) => (REV64v8i16:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src)
24818 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
24819 GIR_RootConstrainSelectedInstOperands,
24820 // GIR_Coverage, 6528,
24821 GIR_Done,
24822 // Label 1435: @69584
24823 GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(69610), // Rule ID 6529 //
24824 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
24825 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24826 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24827 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24828 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src) => (REV32v8i16:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src)
24829 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
24830 GIR_RootConstrainSelectedInstOperands,
24831 // GIR_Coverage, 6529,
24832 GIR_Done,
24833 // Label 1436: @69610
24834 GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(69639), // Rule ID 6530 //
24835 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24836 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24837 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24838 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v8i16] }:$src
24839 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24840 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24841 GIR_RootToRootCopy, /*OpIdx*/1, // src
24842 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24843 // GIR_Coverage, 6530,
24844 GIR_EraseRootFromParent_Done,
24845 // Label 1437: @69639
24846 GIM_Try, /*On fail goto*//*Label 1438*/ GIMT_Encode4(69668), // Rule ID 6531 //
24847 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24848 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24849 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24850 // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[v8i16] }:$src
24851 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24852 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24853 GIR_RootToRootCopy, /*OpIdx*/1, // src
24854 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24855 // GIR_Coverage, 6531,
24856 GIR_EraseRootFromParent_Done,
24857 // Label 1438: @69668
24858 GIM_Try, /*On fail goto*//*Label 1439*/ GIMT_Encode4(69700), // Rule ID 6532 //
24859 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24860 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
24861 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24862 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24863 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v8f16] }:$src
24864 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24865 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24866 GIR_RootToRootCopy, /*OpIdx*/1, // src
24867 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24868 // GIR_Coverage, 6532,
24869 GIR_EraseRootFromParent_Done,
24870 // Label 1439: @69700
24871 GIM_Try, /*On fail goto*//*Label 1440*/ GIMT_Encode4(69732), // Rule ID 6533 //
24872 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24873 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24874 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24875 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24876 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v8f16] }:$src
24877 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24878 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24879 GIR_RootToRootCopy, /*OpIdx*/1, // src
24880 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24881 // GIR_Coverage, 6533,
24882 GIR_EraseRootFromParent_Done,
24883 // Label 1440: @69732
24884 GIM_Try, /*On fail goto*//*Label 1441*/ GIMT_Encode4(69764), // Rule ID 6534 //
24885 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24886 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24887 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24888 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24889 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v8f16] }:$src
24890 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24891 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24892 GIR_RootToRootCopy, /*OpIdx*/1, // src
24893 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24894 // GIR_Coverage, 6534,
24895 GIR_EraseRootFromParent_Done,
24896 // Label 1441: @69764
24897 GIM_Try, /*On fail goto*//*Label 1442*/ GIMT_Encode4(69796), // Rule ID 6535 //
24898 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24899 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24900 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24901 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24902 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v8f16] }:$src
24903 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24904 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24905 GIR_RootToRootCopy, /*OpIdx*/1, // src
24906 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24907 // GIR_Coverage, 6535,
24908 GIR_EraseRootFromParent_Done,
24909 // Label 1442: @69796
24910 GIM_Try, /*On fail goto*//*Label 1443*/ GIMT_Encode4(69828), // Rule ID 6536 //
24911 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24912 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24913 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24914 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24915 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v8f16] }:$src
24916 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24917 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24918 GIR_RootToRootCopy, /*OpIdx*/1, // src
24919 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24920 // GIR_Coverage, 6536,
24921 GIR_EraseRootFromParent_Done,
24922 // Label 1443: @69828
24923 GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(69860), // Rule ID 6537 //
24924 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24925 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24926 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24927 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24928 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v8f16] }:$src
24929 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24930 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24931 GIR_RootToRootCopy, /*OpIdx*/1, // src
24932 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24933 // GIR_Coverage, 6537,
24934 GIR_EraseRootFromParent_Done,
24935 // Label 1444: @69860
24936 GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(69892), // Rule ID 6538 //
24937 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24938 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
24939 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24940 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24941 // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v8bf16] }:$src
24942 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24943 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24944 GIR_RootToRootCopy, /*OpIdx*/1, // src
24945 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24946 // GIR_Coverage, 6538,
24947 GIR_EraseRootFromParent_Done,
24948 // Label 1445: @69892
24949 GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(69924), // Rule ID 6539 //
24950 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24951 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24952 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24953 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24954 // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v8bf16] }:$src
24955 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24956 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24957 GIR_RootToRootCopy, /*OpIdx*/1, // src
24958 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24959 // GIR_Coverage, 6539,
24960 GIR_EraseRootFromParent_Done,
24961 // Label 1446: @69924
24962 GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(69956), // Rule ID 6540 //
24963 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24964 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24965 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24966 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24967 // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v8bf16] }:$src
24968 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24969 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24970 GIR_RootToRootCopy, /*OpIdx*/1, // src
24971 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24972 // GIR_Coverage, 6540,
24973 GIR_EraseRootFromParent_Done,
24974 // Label 1447: @69956
24975 GIM_Try, /*On fail goto*//*Label 1448*/ GIMT_Encode4(69988), // Rule ID 6541 //
24976 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24977 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24978 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24979 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24980 // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v16i8] }:$src) => FPR128:{ *:[v8bf16] }:$src
24981 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24982 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24983 GIR_RootToRootCopy, /*OpIdx*/1, // src
24984 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24985 // GIR_Coverage, 6541,
24986 GIR_EraseRootFromParent_Done,
24987 // Label 1448: @69988
24988 GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(70020), // Rule ID 6542 //
24989 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
24990 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24991 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24992 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
24993 // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v8bf16] }:$src
24994 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24995 GIR_RootToRootCopy, /*OpIdx*/0, // dst
24996 GIR_RootToRootCopy, /*OpIdx*/1, // src
24997 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
24998 // GIR_Coverage, 6542,
24999 GIR_EraseRootFromParent_Done,
25000 // Label 1449: @70020
25001 GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(70052), // Rule ID 6543 //
25002 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25003 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25004 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25005 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25006 // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v8bf16] }:$src
25007 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25008 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25009 GIR_RootToRootCopy, /*OpIdx*/1, // src
25010 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
25011 // GIR_Coverage, 6543,
25012 GIR_EraseRootFromParent_Done,
25013 // Label 1450: @70052
25014 GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(70123), // Rule ID 6544 //
25015 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25016 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
25017 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25018 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25019 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v8f16] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] })
25020 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
25021 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
25022 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
25023 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
25024 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
25025 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
25026 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
25027 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
25028 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
25029 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
25030 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
25031 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
25032 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25033 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
25034 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
25035 GIR_RootConstrainSelectedInstOperands,
25036 // GIR_Coverage, 6544,
25037 GIR_EraseRootFromParent_Done,
25038 // Label 1451: @70123
25039 GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(70149), // Rule ID 6545 //
25040 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25041 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25042 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25043 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25044 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src) => (REV64v8i16:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src)
25045 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
25046 GIR_RootConstrainSelectedInstOperands,
25047 // GIR_Coverage, 6545,
25048 GIR_Done,
25049 // Label 1452: @70149
25050 GIM_Try, /*On fail goto*//*Label 1453*/ GIMT_Encode4(70175), // Rule ID 6546 //
25051 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25052 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25053 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25054 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25055 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src) => (REV32v8i16:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src)
25056 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
25057 GIR_RootConstrainSelectedInstOperands,
25058 // GIR_Coverage, 6546,
25059 GIR_Done,
25060 // Label 1453: @70175
25061 GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(70201), // Rule ID 6547 //
25062 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25063 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
25064 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25065 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25066 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src) => (REV16v16i8:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src)
25067 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
25068 GIR_RootConstrainSelectedInstOperands,
25069 // GIR_Coverage, 6547,
25070 GIR_Done,
25071 // Label 1454: @70201
25072 GIM_Try, /*On fail goto*//*Label 1455*/ GIMT_Encode4(70227), // Rule ID 6548 //
25073 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25074 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25075 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25076 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25077 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src) => (REV64v8i16:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src)
25078 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
25079 GIR_RootConstrainSelectedInstOperands,
25080 // GIR_Coverage, 6548,
25081 GIR_Done,
25082 // Label 1455: @70227
25083 GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(70253), // Rule ID 6549 //
25084 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25085 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25086 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25087 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25088 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src) => (REV32v8i16:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src)
25089 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
25090 GIR_RootConstrainSelectedInstOperands,
25091 // GIR_Coverage, 6549,
25092 GIR_Done,
25093 // Label 1456: @70253
25094 GIM_Try, /*On fail goto*//*Label 1457*/ GIMT_Encode4(70324), // Rule ID 6550 //
25095 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25096 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
25097 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25098 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25099 // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v8bf16] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] })
25100 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
25101 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
25102 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
25103 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
25104 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
25105 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
25106 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
25107 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
25108 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
25109 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
25110 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
25111 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
25112 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25113 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
25114 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
25115 GIR_RootConstrainSelectedInstOperands,
25116 // GIR_Coverage, 6550,
25117 GIR_EraseRootFromParent_Done,
25118 // Label 1457: @70324
25119 GIM_Try, /*On fail goto*//*Label 1458*/ GIMT_Encode4(70350), // Rule ID 6551 //
25120 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25121 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25122 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25123 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25124 // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v2i64] }:$src) => (REV64v8i16:{ *:[v8bf16] } FPR128:{ *:[v2i64] }:$src)
25125 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
25126 GIR_RootConstrainSelectedInstOperands,
25127 // GIR_Coverage, 6551,
25128 GIR_Done,
25129 // Label 1458: @70350
25130 GIM_Try, /*On fail goto*//*Label 1459*/ GIMT_Encode4(70376), // Rule ID 6552 //
25131 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25132 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25133 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25134 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25135 // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v4i32] }:$src) => (REV32v8i16:{ *:[v8bf16] } FPR128:{ *:[v4i32] }:$src)
25136 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
25137 GIR_RootConstrainSelectedInstOperands,
25138 // GIR_Coverage, 6552,
25139 GIR_Done,
25140 // Label 1459: @70376
25141 GIM_Try, /*On fail goto*//*Label 1460*/ GIMT_Encode4(70402), // Rule ID 6553 //
25142 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25143 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
25144 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25145 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25146 // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v16i8] }:$src) => (REV16v16i8:{ *:[v8bf16] } FPR128:{ *:[v16i8] }:$src)
25147 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
25148 GIR_RootConstrainSelectedInstOperands,
25149 // GIR_Coverage, 6553,
25150 GIR_Done,
25151 // Label 1460: @70402
25152 GIM_Try, /*On fail goto*//*Label 1461*/ GIMT_Encode4(70428), // Rule ID 6554 //
25153 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25154 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25155 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25156 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25157 // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v2f64] }:$src) => (REV64v8i16:{ *:[v8bf16] } FPR128:{ *:[v2f64] }:$src)
25158 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
25159 GIR_RootConstrainSelectedInstOperands,
25160 // GIR_Coverage, 6554,
25161 GIR_Done,
25162 // Label 1461: @70428
25163 GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(70454), // Rule ID 6555 //
25164 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25165 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25166 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25167 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25168 // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v4f32] }:$src) => (REV32v8i16:{ *:[v8bf16] } FPR128:{ *:[v4f32] }:$src)
25169 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
25170 GIR_RootConstrainSelectedInstOperands,
25171 // GIR_Coverage, 6555,
25172 GIR_Done,
25173 // Label 1462: @70454
25174 GIM_Try, /*On fail goto*//*Label 1463*/ GIMT_Encode4(70483), // Rule ID 6556 //
25175 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
25176 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25177 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25178 // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v8f16] }:$src
25179 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25180 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25181 GIR_RootToRootCopy, /*OpIdx*/1, // src
25182 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
25183 // GIR_Coverage, 6556,
25184 GIR_EraseRootFromParent_Done,
25185 // Label 1463: @70483
25186 GIM_Try, /*On fail goto*//*Label 1464*/ GIMT_Encode4(70512), // Rule ID 6557 //
25187 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
25188 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25189 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25190 // (bitconvert:{ *:[v8bf16] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v8bf16] }:$src
25191 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25192 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25193 GIR_RootToRootCopy, /*OpIdx*/1, // src
25194 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
25195 // GIR_Coverage, 6557,
25196 GIR_EraseRootFromParent_Done,
25197 // Label 1464: @70512
25198 GIM_Reject,
25199 // Label 1167: @70513
25200 GIM_Try, /*On fail goto*//*Label 1465*/ GIMT_Encode4(70545), // Rule ID 6558 //
25201 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25202 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
25203 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25204 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25205 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[f128] }:$src) => FPR128:{ *:[v16i8] }:$src
25206 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25207 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25208 GIR_RootToRootCopy, /*OpIdx*/1, // src
25209 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
25210 // GIR_Coverage, 6558,
25211 GIR_EraseRootFromParent_Done,
25212 // Label 1465: @70545
25213 GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(70577), // Rule ID 6559 //
25214 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25215 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25216 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25217 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25218 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src) => FPR128:{ *:[v16i8] }:$src
25219 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25220 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25221 GIR_RootToRootCopy, /*OpIdx*/1, // src
25222 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
25223 // GIR_Coverage, 6559,
25224 GIR_EraseRootFromParent_Done,
25225 // Label 1466: @70577
25226 GIM_Try, /*On fail goto*//*Label 1467*/ GIMT_Encode4(70609), // Rule ID 6560 //
25227 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25228 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25229 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25230 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25231 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src) => FPR128:{ *:[v16i8] }:$src
25232 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25233 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25234 GIR_RootToRootCopy, /*OpIdx*/1, // src
25235 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
25236 // GIR_Coverage, 6560,
25237 GIR_EraseRootFromParent_Done,
25238 // Label 1467: @70609
25239 GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(70641), // Rule ID 6561 //
25240 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25241 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
25242 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25243 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25244 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src) => FPR128:{ *:[v16i8] }:$src
25245 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25246 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25247 GIR_RootToRootCopy, /*OpIdx*/1, // src
25248 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
25249 // GIR_Coverage, 6561,
25250 GIR_EraseRootFromParent_Done,
25251 // Label 1468: @70641
25252 GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(70673), // Rule ID 6562 //
25253 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25254 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25255 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25256 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25257 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src) => FPR128:{ *:[v16i8] }:$src
25258 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25259 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25260 GIR_RootToRootCopy, /*OpIdx*/1, // src
25261 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
25262 // GIR_Coverage, 6562,
25263 GIR_EraseRootFromParent_Done,
25264 // Label 1469: @70673
25265 GIM_Try, /*On fail goto*//*Label 1470*/ GIMT_Encode4(70705), // Rule ID 6563 //
25266 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25267 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25268 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25269 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25270 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src) => FPR128:{ *:[v16i8] }:$src
25271 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25272 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25273 GIR_RootToRootCopy, /*OpIdx*/1, // src
25274 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
25275 // GIR_Coverage, 6563,
25276 GIR_EraseRootFromParent_Done,
25277 // Label 1470: @70705
25278 GIM_Try, /*On fail goto*//*Label 1471*/ GIMT_Encode4(70737), // Rule ID 6564 //
25279 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25280 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
25281 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25282 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25283 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v16i8] }:$src
25284 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25285 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25286 GIR_RootToRootCopy, /*OpIdx*/1, // src
25287 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
25288 // GIR_Coverage, 6564,
25289 GIR_EraseRootFromParent_Done,
25290 // Label 1471: @70737
25291 GIM_Try, /*On fail goto*//*Label 1472*/ GIMT_Encode4(70769), // Rule ID 6565 //
25292 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25293 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
25294 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25295 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25296 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8bf16] }:$src) => FPR128:{ *:[v16i8] }:$src
25297 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25298 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25299 GIR_RootToRootCopy, /*OpIdx*/1, // src
25300 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
25301 // GIR_Coverage, 6565,
25302 GIR_EraseRootFromParent_Done,
25303 // Label 1472: @70769
25304 GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(70840), // Rule ID 6566 //
25305 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25306 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
25307 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25308 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25309 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[f128] }:$src) => (EXTv16i8:{ *:[v16i8] } (REV64v16i8:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v16i8:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] })
25310 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
25311 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
25312 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
25313 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
25314 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
25315 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
25316 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
25317 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
25318 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
25319 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
25320 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
25321 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
25322 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25323 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
25324 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
25325 GIR_RootConstrainSelectedInstOperands,
25326 // GIR_Coverage, 6566,
25327 GIR_EraseRootFromParent_Done,
25328 // Label 1473: @70840
25329 GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(70866), // Rule ID 6567 //
25330 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25331 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25332 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25333 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25334 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src) => (REV64v16i8:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src)
25335 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
25336 GIR_RootConstrainSelectedInstOperands,
25337 // GIR_Coverage, 6567,
25338 GIR_Done,
25339 // Label 1474: @70866
25340 GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(70892), // Rule ID 6568 //
25341 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25342 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25343 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25344 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25345 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src) => (REV32v16i8:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src)
25346 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v16i8),
25347 GIR_RootConstrainSelectedInstOperands,
25348 // GIR_Coverage, 6568,
25349 GIR_Done,
25350 // Label 1475: @70892
25351 GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(70918), // Rule ID 6569 //
25352 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25353 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
25354 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25355 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25356 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src) => (REV16v16i8:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src)
25357 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
25358 GIR_RootConstrainSelectedInstOperands,
25359 // GIR_Coverage, 6569,
25360 GIR_Done,
25361 // Label 1476: @70918
25362 GIM_Try, /*On fail goto*//*Label 1477*/ GIMT_Encode4(70944), // Rule ID 6570 //
25363 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25364 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25365 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25366 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25367 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src) => (REV64v16i8:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src)
25368 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
25369 GIR_RootConstrainSelectedInstOperands,
25370 // GIR_Coverage, 6570,
25371 GIR_Done,
25372 // Label 1477: @70944
25373 GIM_Try, /*On fail goto*//*Label 1478*/ GIMT_Encode4(70970), // Rule ID 6571 //
25374 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25375 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25376 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25377 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25378 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src) => (REV32v16i8:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src)
25379 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v16i8),
25380 GIR_RootConstrainSelectedInstOperands,
25381 // GIR_Coverage, 6571,
25382 GIR_Done,
25383 // Label 1478: @70970
25384 GIM_Try, /*On fail goto*//*Label 1479*/ GIMT_Encode4(70996), // Rule ID 6572 //
25385 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25386 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
25387 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25388 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25389 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src) => (REV16v16i8:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src)
25390 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
25391 GIR_RootConstrainSelectedInstOperands,
25392 // GIR_Coverage, 6572,
25393 GIR_Done,
25394 // Label 1479: @70996
25395 GIM_Try, /*On fail goto*//*Label 1480*/ GIMT_Encode4(71022), // Rule ID 6573 //
25396 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
25397 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
25398 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25399 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
25400 // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8bf16] }:$src) => (REV16v16i8:{ *:[v16i8] } FPR128:{ *:[v8bf16] }:$src)
25401 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
25402 GIR_RootConstrainSelectedInstOperands,
25403 // GIR_Coverage, 6573,
25404 GIR_Done,
25405 // Label 1480: @71022
25406 GIM_Reject,
25407 // Label 1168: @71023
25408 GIM_Try, /*On fail goto*//*Label 1481*/ GIMT_Encode4(71051), // Rule ID 10255 //
25409 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25410 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
25411 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25412 // (bitconvert:{ *:[nxv2i64] } nxv16i8:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv2i64] }:$src
25413 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25414 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25415 GIR_RootToRootCopy, /*OpIdx*/1, // src
25416 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25417 // GIR_Coverage, 10255,
25418 GIR_EraseRootFromParent_Done,
25419 // Label 1481: @71051
25420 GIM_Try, /*On fail goto*//*Label 1482*/ GIMT_Encode4(71079), // Rule ID 10256 //
25421 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25422 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
25423 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25424 // (bitconvert:{ *:[nxv2i64] } nxv8i16:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv2i64] }:$src
25425 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25426 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25427 GIR_RootToRootCopy, /*OpIdx*/1, // src
25428 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25429 // GIR_Coverage, 10256,
25430 GIR_EraseRootFromParent_Done,
25431 // Label 1482: @71079
25432 GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(71107), // Rule ID 10257 //
25433 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25434 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
25435 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25436 // (bitconvert:{ *:[nxv2i64] } nxv4i32:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv2i64] }:$src
25437 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25438 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25439 GIR_RootToRootCopy, /*OpIdx*/1, // src
25440 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25441 // GIR_Coverage, 10257,
25442 GIR_EraseRootFromParent_Done,
25443 // Label 1483: @71107
25444 GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(71135), // Rule ID 10258 //
25445 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25446 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
25447 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25448 // (bitconvert:{ *:[nxv2i64] } nxv8f16:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv2i64] }:$src
25449 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25450 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25451 GIR_RootToRootCopy, /*OpIdx*/1, // src
25452 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25453 // GIR_Coverage, 10258,
25454 GIR_EraseRootFromParent_Done,
25455 // Label 1484: @71135
25456 GIM_Try, /*On fail goto*//*Label 1485*/ GIMT_Encode4(71163), // Rule ID 10259 //
25457 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25458 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
25459 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25460 // (bitconvert:{ *:[nxv2i64] } nxv4f32:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv2i64] }:$src
25461 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25462 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25463 GIR_RootToRootCopy, /*OpIdx*/1, // src
25464 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25465 // GIR_Coverage, 10259,
25466 GIR_EraseRootFromParent_Done,
25467 // Label 1485: @71163
25468 GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(71191), // Rule ID 10260 //
25469 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25470 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
25471 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25472 // (bitconvert:{ *:[nxv2i64] } nxv2f64:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv2i64] }:$src
25473 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25474 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25475 GIR_RootToRootCopy, /*OpIdx*/1, // src
25476 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25477 // GIR_Coverage, 10260,
25478 GIR_EraseRootFromParent_Done,
25479 // Label 1486: @71191
25480 GIM_Try, /*On fail goto*//*Label 1487*/ GIMT_Encode4(71219), // Rule ID 10273 //
25481 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25482 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
25483 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25484 // (bitconvert:{ *:[nxv2f64] } nxv16i8:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv2f64] }:$src
25485 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25486 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25487 GIR_RootToRootCopy, /*OpIdx*/1, // src
25488 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25489 // GIR_Coverage, 10273,
25490 GIR_EraseRootFromParent_Done,
25491 // Label 1487: @71219
25492 GIM_Try, /*On fail goto*//*Label 1488*/ GIMT_Encode4(71247), // Rule ID 10274 //
25493 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25494 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
25495 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25496 // (bitconvert:{ *:[nxv2f64] } nxv8i16:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv2f64] }:$src
25497 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25498 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25499 GIR_RootToRootCopy, /*OpIdx*/1, // src
25500 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25501 // GIR_Coverage, 10274,
25502 GIR_EraseRootFromParent_Done,
25503 // Label 1488: @71247
25504 GIM_Try, /*On fail goto*//*Label 1489*/ GIMT_Encode4(71275), // Rule ID 10275 //
25505 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25506 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
25507 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25508 // (bitconvert:{ *:[nxv2f64] } nxv4i32:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv2f64] }:$src
25509 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25510 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25511 GIR_RootToRootCopy, /*OpIdx*/1, // src
25512 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25513 // GIR_Coverage, 10275,
25514 GIR_EraseRootFromParent_Done,
25515 // Label 1489: @71275
25516 GIM_Try, /*On fail goto*//*Label 1490*/ GIMT_Encode4(71303), // Rule ID 10276 //
25517 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25518 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
25519 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25520 // (bitconvert:{ *:[nxv2f64] } nxv2i64:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv2f64] }:$src
25521 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25522 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25523 GIR_RootToRootCopy, /*OpIdx*/1, // src
25524 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25525 // GIR_Coverage, 10276,
25526 GIR_EraseRootFromParent_Done,
25527 // Label 1490: @71303
25528 GIM_Try, /*On fail goto*//*Label 1491*/ GIMT_Encode4(71331), // Rule ID 10277 //
25529 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25530 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
25531 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25532 // (bitconvert:{ *:[nxv2f64] } nxv8f16:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv2f64] }:$src
25533 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25534 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25535 GIR_RootToRootCopy, /*OpIdx*/1, // src
25536 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25537 // GIR_Coverage, 10277,
25538 GIR_EraseRootFromParent_Done,
25539 // Label 1491: @71331
25540 GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(71359), // Rule ID 10278 //
25541 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25542 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
25543 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25544 // (bitconvert:{ *:[nxv2f64] } nxv4f32:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv2f64] }:$src
25545 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25546 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25547 GIR_RootToRootCopy, /*OpIdx*/1, // src
25548 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25549 // GIR_Coverage, 10278,
25550 GIR_EraseRootFromParent_Done,
25551 // Label 1492: @71359
25552 GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(71387), // Rule ID 10289 //
25553 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25554 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
25555 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25556 // (bitconvert:{ *:[nxv2i64] } nxv8bf16:{ *:[nxv8bf16] }:$src) => ZPR:{ *:[nxv2i64] }:$src
25557 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25558 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25559 GIR_RootToRootCopy, /*OpIdx*/1, // src
25560 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25561 // GIR_Coverage, 10289,
25562 GIR_EraseRootFromParent_Done,
25563 // Label 1493: @71387
25564 GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(71415), // Rule ID 10292 //
25565 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25566 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
25567 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25568 // (bitconvert:{ *:[nxv2f64] } nxv8bf16:{ *:[nxv8bf16] }:$src) => ZPR:{ *:[nxv2f64] }:$src
25569 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25570 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25571 GIR_RootToRootCopy, /*OpIdx*/1, // src
25572 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25573 // GIR_Coverage, 10292,
25574 GIR_EraseRootFromParent_Done,
25575 // Label 1494: @71415
25576 GIM_Reject,
25577 // Label 1169: @71416
25578 GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(71444), // Rule ID 10249 //
25579 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25580 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
25581 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25582 // (bitconvert:{ *:[nxv4i32] } nxv16i8:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv4i32] }:$src
25583 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25584 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25585 GIR_RootToRootCopy, /*OpIdx*/1, // src
25586 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25587 // GIR_Coverage, 10249,
25588 GIR_EraseRootFromParent_Done,
25589 // Label 1495: @71444
25590 GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(71472), // Rule ID 10250 //
25591 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25592 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
25593 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25594 // (bitconvert:{ *:[nxv4i32] } nxv8i16:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv4i32] }:$src
25595 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25596 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25597 GIR_RootToRootCopy, /*OpIdx*/1, // src
25598 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25599 // GIR_Coverage, 10250,
25600 GIR_EraseRootFromParent_Done,
25601 // Label 1496: @71472
25602 GIM_Try, /*On fail goto*//*Label 1497*/ GIMT_Encode4(71500), // Rule ID 10251 //
25603 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25604 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
25605 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25606 // (bitconvert:{ *:[nxv4i32] } nxv2i64:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv4i32] }:$src
25607 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25608 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25609 GIR_RootToRootCopy, /*OpIdx*/1, // src
25610 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25611 // GIR_Coverage, 10251,
25612 GIR_EraseRootFromParent_Done,
25613 // Label 1497: @71500
25614 GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(71528), // Rule ID 10252 //
25615 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25616 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
25617 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25618 // (bitconvert:{ *:[nxv4i32] } nxv8f16:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv4i32] }:$src
25619 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25620 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25621 GIR_RootToRootCopy, /*OpIdx*/1, // src
25622 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25623 // GIR_Coverage, 10252,
25624 GIR_EraseRootFromParent_Done,
25625 // Label 1498: @71528
25626 GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(71556), // Rule ID 10253 //
25627 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25628 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
25629 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25630 // (bitconvert:{ *:[nxv4i32] } nxv4f32:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv4i32] }:$src
25631 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25632 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25633 GIR_RootToRootCopy, /*OpIdx*/1, // src
25634 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25635 // GIR_Coverage, 10253,
25636 GIR_EraseRootFromParent_Done,
25637 // Label 1499: @71556
25638 GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(71584), // Rule ID 10254 //
25639 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25640 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
25641 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25642 // (bitconvert:{ *:[nxv4i32] } nxv2f64:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv4i32] }:$src
25643 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25644 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25645 GIR_RootToRootCopy, /*OpIdx*/1, // src
25646 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25647 // GIR_Coverage, 10254,
25648 GIR_EraseRootFromParent_Done,
25649 // Label 1500: @71584
25650 GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(71612), // Rule ID 10267 //
25651 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25652 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
25653 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25654 // (bitconvert:{ *:[nxv4f32] } nxv16i8:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv4f32] }:$src
25655 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25656 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25657 GIR_RootToRootCopy, /*OpIdx*/1, // src
25658 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25659 // GIR_Coverage, 10267,
25660 GIR_EraseRootFromParent_Done,
25661 // Label 1501: @71612
25662 GIM_Try, /*On fail goto*//*Label 1502*/ GIMT_Encode4(71640), // Rule ID 10268 //
25663 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25664 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
25665 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25666 // (bitconvert:{ *:[nxv4f32] } nxv8i16:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv4f32] }:$src
25667 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25668 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25669 GIR_RootToRootCopy, /*OpIdx*/1, // src
25670 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25671 // GIR_Coverage, 10268,
25672 GIR_EraseRootFromParent_Done,
25673 // Label 1502: @71640
25674 GIM_Try, /*On fail goto*//*Label 1503*/ GIMT_Encode4(71668), // Rule ID 10269 //
25675 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25676 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
25677 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25678 // (bitconvert:{ *:[nxv4f32] } nxv4i32:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv4f32] }:$src
25679 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25680 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25681 GIR_RootToRootCopy, /*OpIdx*/1, // src
25682 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25683 // GIR_Coverage, 10269,
25684 GIR_EraseRootFromParent_Done,
25685 // Label 1503: @71668
25686 GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(71696), // Rule ID 10270 //
25687 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25688 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
25689 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25690 // (bitconvert:{ *:[nxv4f32] } nxv2i64:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv4f32] }:$src
25691 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25692 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25693 GIR_RootToRootCopy, /*OpIdx*/1, // src
25694 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25695 // GIR_Coverage, 10270,
25696 GIR_EraseRootFromParent_Done,
25697 // Label 1504: @71696
25698 GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(71724), // Rule ID 10271 //
25699 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25700 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
25701 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25702 // (bitconvert:{ *:[nxv4f32] } nxv8f16:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv4f32] }:$src
25703 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25704 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25705 GIR_RootToRootCopy, /*OpIdx*/1, // src
25706 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25707 // GIR_Coverage, 10271,
25708 GIR_EraseRootFromParent_Done,
25709 // Label 1505: @71724
25710 GIM_Try, /*On fail goto*//*Label 1506*/ GIMT_Encode4(71752), // Rule ID 10272 //
25711 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25712 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
25713 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25714 // (bitconvert:{ *:[nxv4f32] } nxv2f64:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv4f32] }:$src
25715 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25716 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25717 GIR_RootToRootCopy, /*OpIdx*/1, // src
25718 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25719 // GIR_Coverage, 10272,
25720 GIR_EraseRootFromParent_Done,
25721 // Label 1506: @71752
25722 GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(71780), // Rule ID 10288 //
25723 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25724 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
25725 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25726 // (bitconvert:{ *:[nxv4i32] } nxv8bf16:{ *:[nxv8bf16] }:$src) => ZPR:{ *:[nxv4i32] }:$src
25727 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25728 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25729 GIR_RootToRootCopy, /*OpIdx*/1, // src
25730 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25731 // GIR_Coverage, 10288,
25732 GIR_EraseRootFromParent_Done,
25733 // Label 1507: @71780
25734 GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(71808), // Rule ID 10291 //
25735 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25736 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
25737 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25738 // (bitconvert:{ *:[nxv4f32] } nxv8bf16:{ *:[nxv8bf16] }:$src) => ZPR:{ *:[nxv4f32] }:$src
25739 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25740 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25741 GIR_RootToRootCopy, /*OpIdx*/1, // src
25742 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25743 // GIR_Coverage, 10291,
25744 GIR_EraseRootFromParent_Done,
25745 // Label 1508: @71808
25746 GIM_Reject,
25747 // Label 1170: @71809
25748 GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(71837), // Rule ID 10243 //
25749 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25750 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
25751 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25752 // (bitconvert:{ *:[nxv8i16] } nxv16i8:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv8i16] }:$src
25753 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25754 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25755 GIR_RootToRootCopy, /*OpIdx*/1, // src
25756 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25757 // GIR_Coverage, 10243,
25758 GIR_EraseRootFromParent_Done,
25759 // Label 1509: @71837
25760 GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(71865), // Rule ID 10244 //
25761 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25762 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
25763 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25764 // (bitconvert:{ *:[nxv8i16] } nxv4i32:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv8i16] }:$src
25765 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25766 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25767 GIR_RootToRootCopy, /*OpIdx*/1, // src
25768 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25769 // GIR_Coverage, 10244,
25770 GIR_EraseRootFromParent_Done,
25771 // Label 1510: @71865
25772 GIM_Try, /*On fail goto*//*Label 1511*/ GIMT_Encode4(71893), // Rule ID 10245 //
25773 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25774 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
25775 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25776 // (bitconvert:{ *:[nxv8i16] } nxv2i64:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv8i16] }:$src
25777 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25778 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25779 GIR_RootToRootCopy, /*OpIdx*/1, // src
25780 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25781 // GIR_Coverage, 10245,
25782 GIR_EraseRootFromParent_Done,
25783 // Label 1511: @71893
25784 GIM_Try, /*On fail goto*//*Label 1512*/ GIMT_Encode4(71921), // Rule ID 10246 //
25785 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25786 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
25787 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25788 // (bitconvert:{ *:[nxv8i16] } nxv8f16:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv8i16] }:$src
25789 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25790 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25791 GIR_RootToRootCopy, /*OpIdx*/1, // src
25792 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25793 // GIR_Coverage, 10246,
25794 GIR_EraseRootFromParent_Done,
25795 // Label 1512: @71921
25796 GIM_Try, /*On fail goto*//*Label 1513*/ GIMT_Encode4(71949), // Rule ID 10247 //
25797 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25798 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
25799 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25800 // (bitconvert:{ *:[nxv8i16] } nxv4f32:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv8i16] }:$src
25801 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25802 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25803 GIR_RootToRootCopy, /*OpIdx*/1, // src
25804 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25805 // GIR_Coverage, 10247,
25806 GIR_EraseRootFromParent_Done,
25807 // Label 1513: @71949
25808 GIM_Try, /*On fail goto*//*Label 1514*/ GIMT_Encode4(71977), // Rule ID 10248 //
25809 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25810 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
25811 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25812 // (bitconvert:{ *:[nxv8i16] } nxv2f64:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv8i16] }:$src
25813 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25814 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25815 GIR_RootToRootCopy, /*OpIdx*/1, // src
25816 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25817 // GIR_Coverage, 10248,
25818 GIR_EraseRootFromParent_Done,
25819 // Label 1514: @71977
25820 GIM_Try, /*On fail goto*//*Label 1515*/ GIMT_Encode4(72005), // Rule ID 10261 //
25821 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25822 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
25823 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25824 // (bitconvert:{ *:[nxv8f16] } nxv16i8:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv8f16] }:$src
25825 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25826 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25827 GIR_RootToRootCopy, /*OpIdx*/1, // src
25828 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25829 // GIR_Coverage, 10261,
25830 GIR_EraseRootFromParent_Done,
25831 // Label 1515: @72005
25832 GIM_Try, /*On fail goto*//*Label 1516*/ GIMT_Encode4(72033), // Rule ID 10262 //
25833 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25834 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
25835 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25836 // (bitconvert:{ *:[nxv8f16] } nxv8i16:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv8f16] }:$src
25837 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25838 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25839 GIR_RootToRootCopy, /*OpIdx*/1, // src
25840 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25841 // GIR_Coverage, 10262,
25842 GIR_EraseRootFromParent_Done,
25843 // Label 1516: @72033
25844 GIM_Try, /*On fail goto*//*Label 1517*/ GIMT_Encode4(72061), // Rule ID 10263 //
25845 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25846 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
25847 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25848 // (bitconvert:{ *:[nxv8f16] } nxv4i32:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv8f16] }:$src
25849 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25850 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25851 GIR_RootToRootCopy, /*OpIdx*/1, // src
25852 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25853 // GIR_Coverage, 10263,
25854 GIR_EraseRootFromParent_Done,
25855 // Label 1517: @72061
25856 GIM_Try, /*On fail goto*//*Label 1518*/ GIMT_Encode4(72089), // Rule ID 10264 //
25857 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25858 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
25859 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25860 // (bitconvert:{ *:[nxv8f16] } nxv2i64:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv8f16] }:$src
25861 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25862 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25863 GIR_RootToRootCopy, /*OpIdx*/1, // src
25864 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25865 // GIR_Coverage, 10264,
25866 GIR_EraseRootFromParent_Done,
25867 // Label 1518: @72089
25868 GIM_Try, /*On fail goto*//*Label 1519*/ GIMT_Encode4(72117), // Rule ID 10265 //
25869 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25870 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
25871 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25872 // (bitconvert:{ *:[nxv8f16] } nxv4f32:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv8f16] }:$src
25873 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25874 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25875 GIR_RootToRootCopy, /*OpIdx*/1, // src
25876 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25877 // GIR_Coverage, 10265,
25878 GIR_EraseRootFromParent_Done,
25879 // Label 1519: @72117
25880 GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(72145), // Rule ID 10266 //
25881 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25882 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
25883 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25884 // (bitconvert:{ *:[nxv8f16] } nxv2f64:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv8f16] }:$src
25885 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25886 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25887 GIR_RootToRootCopy, /*OpIdx*/1, // src
25888 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25889 // GIR_Coverage, 10266,
25890 GIR_EraseRootFromParent_Done,
25891 // Label 1520: @72145
25892 GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(72173), // Rule ID 10279 //
25893 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25894 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
25895 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25896 // (bitconvert:{ *:[nxv8bf16] } nxv16i8:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv8bf16] }:$src
25897 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25898 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25899 GIR_RootToRootCopy, /*OpIdx*/1, // src
25900 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25901 // GIR_Coverage, 10279,
25902 GIR_EraseRootFromParent_Done,
25903 // Label 1521: @72173
25904 GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(72201), // Rule ID 10280 //
25905 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25906 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
25907 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25908 // (bitconvert:{ *:[nxv8bf16] } nxv8i16:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv8bf16] }:$src
25909 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25910 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25911 GIR_RootToRootCopy, /*OpIdx*/1, // src
25912 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25913 // GIR_Coverage, 10280,
25914 GIR_EraseRootFromParent_Done,
25915 // Label 1522: @72201
25916 GIM_Try, /*On fail goto*//*Label 1523*/ GIMT_Encode4(72229), // Rule ID 10281 //
25917 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25918 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
25919 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25920 // (bitconvert:{ *:[nxv8bf16] } nxv4i32:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv8bf16] }:$src
25921 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25922 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25923 GIR_RootToRootCopy, /*OpIdx*/1, // src
25924 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25925 // GIR_Coverage, 10281,
25926 GIR_EraseRootFromParent_Done,
25927 // Label 1523: @72229
25928 GIM_Try, /*On fail goto*//*Label 1524*/ GIMT_Encode4(72257), // Rule ID 10282 //
25929 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25930 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
25931 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25932 // (bitconvert:{ *:[nxv8bf16] } nxv2i64:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv8bf16] }:$src
25933 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25934 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25935 GIR_RootToRootCopy, /*OpIdx*/1, // src
25936 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25937 // GIR_Coverage, 10282,
25938 GIR_EraseRootFromParent_Done,
25939 // Label 1524: @72257
25940 GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(72285), // Rule ID 10283 //
25941 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25942 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
25943 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25944 // (bitconvert:{ *:[nxv8bf16] } nxv8f16:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv8bf16] }:$src
25945 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25946 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25947 GIR_RootToRootCopy, /*OpIdx*/1, // src
25948 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25949 // GIR_Coverage, 10283,
25950 GIR_EraseRootFromParent_Done,
25951 // Label 1525: @72285
25952 GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(72313), // Rule ID 10284 //
25953 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25954 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
25955 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25956 // (bitconvert:{ *:[nxv8bf16] } nxv4f32:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv8bf16] }:$src
25957 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25958 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25959 GIR_RootToRootCopy, /*OpIdx*/1, // src
25960 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25961 // GIR_Coverage, 10284,
25962 GIR_EraseRootFromParent_Done,
25963 // Label 1526: @72313
25964 GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(72341), // Rule ID 10285 //
25965 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25966 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
25967 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25968 // (bitconvert:{ *:[nxv8bf16] } nxv2f64:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv8bf16] }:$src
25969 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25970 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25971 GIR_RootToRootCopy, /*OpIdx*/1, // src
25972 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25973 // GIR_Coverage, 10285,
25974 GIR_EraseRootFromParent_Done,
25975 // Label 1527: @72341
25976 GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(72369), // Rule ID 10287 //
25977 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25978 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
25979 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25980 // (bitconvert:{ *:[nxv8i16] } nxv8bf16:{ *:[nxv8bf16] }:$src) => ZPR:{ *:[nxv8i16] }:$src
25981 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25982 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25983 GIR_RootToRootCopy, /*OpIdx*/1, // src
25984 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25985 // GIR_Coverage, 10287,
25986 GIR_EraseRootFromParent_Done,
25987 // Label 1528: @72369
25988 GIM_Try, /*On fail goto*//*Label 1529*/ GIMT_Encode4(72397), // Rule ID 10290 //
25989 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
25990 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
25991 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
25992 // (bitconvert:{ *:[nxv8f16] } nxv8bf16:{ *:[nxv8bf16] }:$src) => ZPR:{ *:[nxv8f16] }:$src
25993 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25994 GIR_RootToRootCopy, /*OpIdx*/0, // dst
25995 GIR_RootToRootCopy, /*OpIdx*/1, // src
25996 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
25997 // GIR_Coverage, 10290,
25998 GIR_EraseRootFromParent_Done,
25999 // Label 1529: @72397
26000 GIM_Reject,
26001 // Label 1171: @72398
26002 GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(72426), // Rule ID 10237 //
26003 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
26004 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
26005 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
26006 // (bitconvert:{ *:[nxv16i8] } nxv8i16:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv16i8] }:$src
26007 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26008 GIR_RootToRootCopy, /*OpIdx*/0, // dst
26009 GIR_RootToRootCopy, /*OpIdx*/1, // src
26010 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
26011 // GIR_Coverage, 10237,
26012 GIR_EraseRootFromParent_Done,
26013 // Label 1530: @72426
26014 GIM_Try, /*On fail goto*//*Label 1531*/ GIMT_Encode4(72454), // Rule ID 10238 //
26015 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
26016 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
26017 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
26018 // (bitconvert:{ *:[nxv16i8] } nxv4i32:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv16i8] }:$src
26019 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26020 GIR_RootToRootCopy, /*OpIdx*/0, // dst
26021 GIR_RootToRootCopy, /*OpIdx*/1, // src
26022 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
26023 // GIR_Coverage, 10238,
26024 GIR_EraseRootFromParent_Done,
26025 // Label 1531: @72454
26026 GIM_Try, /*On fail goto*//*Label 1532*/ GIMT_Encode4(72482), // Rule ID 10239 //
26027 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
26028 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
26029 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
26030 // (bitconvert:{ *:[nxv16i8] } nxv2i64:{ *:[nxv2i64] }:$src) => ZPR:{ *:[nxv16i8] }:$src
26031 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26032 GIR_RootToRootCopy, /*OpIdx*/0, // dst
26033 GIR_RootToRootCopy, /*OpIdx*/1, // src
26034 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
26035 // GIR_Coverage, 10239,
26036 GIR_EraseRootFromParent_Done,
26037 // Label 1532: @72482
26038 GIM_Try, /*On fail goto*//*Label 1533*/ GIMT_Encode4(72510), // Rule ID 10240 //
26039 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
26040 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
26041 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
26042 // (bitconvert:{ *:[nxv16i8] } nxv8f16:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv16i8] }:$src
26043 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26044 GIR_RootToRootCopy, /*OpIdx*/0, // dst
26045 GIR_RootToRootCopy, /*OpIdx*/1, // src
26046 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
26047 // GIR_Coverage, 10240,
26048 GIR_EraseRootFromParent_Done,
26049 // Label 1533: @72510
26050 GIM_Try, /*On fail goto*//*Label 1534*/ GIMT_Encode4(72538), // Rule ID 10241 //
26051 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
26052 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
26053 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
26054 // (bitconvert:{ *:[nxv16i8] } nxv4f32:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv16i8] }:$src
26055 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26056 GIR_RootToRootCopy, /*OpIdx*/0, // dst
26057 GIR_RootToRootCopy, /*OpIdx*/1, // src
26058 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
26059 // GIR_Coverage, 10241,
26060 GIR_EraseRootFromParent_Done,
26061 // Label 1534: @72538
26062 GIM_Try, /*On fail goto*//*Label 1535*/ GIMT_Encode4(72566), // Rule ID 10242 //
26063 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
26064 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
26065 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
26066 // (bitconvert:{ *:[nxv16i8] } nxv2f64:{ *:[nxv2f64] }:$src) => ZPR:{ *:[nxv16i8] }:$src
26067 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26068 GIR_RootToRootCopy, /*OpIdx*/0, // dst
26069 GIR_RootToRootCopy, /*OpIdx*/1, // src
26070 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
26071 // GIR_Coverage, 10242,
26072 GIR_EraseRootFromParent_Done,
26073 // Label 1535: @72566
26074 GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(72594), // Rule ID 10286 //
26075 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
26076 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
26077 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
26078 // (bitconvert:{ *:[nxv16i8] } nxv8bf16:{ *:[nxv8bf16] }:$src) => ZPR:{ *:[nxv16i8] }:$src
26079 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26080 GIR_RootToRootCopy, /*OpIdx*/0, // dst
26081 GIR_RootToRootCopy, /*OpIdx*/1, // src
26082 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
26083 // GIR_Coverage, 10286,
26084 GIR_EraseRootFromParent_Done,
26085 // Label 1536: @72594
26086 GIM_Reject,
26087 // Label 1172: @72595
26088 GIM_Reject,
26089 // Label 10: @72596
26090 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 1545*/ GIMT_Encode4(74018),
26091 /*GILLT_s16*//*Label 1537*/ GIMT_Encode4(72647),
26092 /*GILLT_s32*//*Label 1538*/ GIMT_Encode4(72678),
26093 /*GILLT_s64*//*Label 1539*/ GIMT_Encode4(72709), GIMT_Encode4(0),
26094 /*GILLT_v2s32*//*Label 1540*/ GIMT_Encode4(72740),
26095 /*GILLT_v2s64*//*Label 1541*/ GIMT_Encode4(72771),
26096 /*GILLT_v4s16*//*Label 1542*/ GIMT_Encode4(72802),
26097 /*GILLT_v4s32*//*Label 1543*/ GIMT_Encode4(72833), GIMT_Encode4(0),
26098 /*GILLT_v8s16*//*Label 1544*/ GIMT_Encode4(72864),
26099 // Label 1537: @72647
26100 GIM_Try, /*On fail goto*//*Label 1546*/ GIMT_Encode4(72677), // Rule ID 558 //
26101 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
26102 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
26103 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
26104 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
26105 // (ftrunc:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTZHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
26106 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZHr),
26107 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
26108 GIR_RootConstrainSelectedInstOperands,
26109 // GIR_Coverage, 558,
26110 GIR_Done,
26111 // Label 1546: @72677
26112 GIM_Reject,
26113 // Label 1538: @72678
26114 GIM_Try, /*On fail goto*//*Label 1547*/ GIMT_Encode4(72708), // Rule ID 560 //
26115 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
26116 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26117 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
26118 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
26119 // (ftrunc:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTZSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
26120 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZSr),
26121 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
26122 GIR_RootConstrainSelectedInstOperands,
26123 // GIR_Coverage, 560,
26124 GIR_Done,
26125 // Label 1547: @72708
26126 GIM_Reject,
26127 // Label 1539: @72709
26128 GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(72739), // Rule ID 562 //
26129 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
26130 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26131 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
26132 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
26133 // (ftrunc:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTZDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
26134 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZDr),
26135 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
26136 GIR_RootConstrainSelectedInstOperands,
26137 // GIR_Coverage, 562,
26138 GIR_Done,
26139 // Label 1548: @72739
26140 GIM_Reject,
26141 // Label 1540: @72740
26142 GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(72770), // Rule ID 920 //
26143 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
26144 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
26145 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
26146 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
26147 // (ftrunc:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTZv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
26148 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv2f32),
26149 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
26150 GIR_RootConstrainSelectedInstOperands,
26151 // GIR_Coverage, 920,
26152 GIR_Done,
26153 // Label 1549: @72770
26154 GIM_Reject,
26155 // Label 1541: @72771
26156 GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(72801), // Rule ID 924 //
26157 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
26158 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26159 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
26160 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
26161 // (ftrunc:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTZv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
26162 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv2f64),
26163 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
26164 GIR_RootConstrainSelectedInstOperands,
26165 // GIR_Coverage, 924,
26166 GIR_Done,
26167 // Label 1550: @72801
26168 GIM_Reject,
26169 // Label 1542: @72802
26170 GIM_Try, /*On fail goto*//*Label 1551*/ GIMT_Encode4(72832), // Rule ID 916 //
26171 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
26172 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
26173 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
26174 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
26175 // (ftrunc:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTZv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
26176 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f16),
26177 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
26178 GIR_RootConstrainSelectedInstOperands,
26179 // GIR_Coverage, 916,
26180 GIR_Done,
26181 // Label 1551: @72832
26182 GIM_Reject,
26183 // Label 1543: @72833
26184 GIM_Try, /*On fail goto*//*Label 1552*/ GIMT_Encode4(72863), // Rule ID 922 //
26185 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
26186 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26187 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
26188 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
26189 // (ftrunc:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTZv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
26190 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f32),
26191 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
26192 GIR_RootConstrainSelectedInstOperands,
26193 // GIR_Coverage, 922,
26194 GIR_Done,
26195 // Label 1552: @72863
26196 GIM_Reject,
26197 // Label 1544: @72864
26198 GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(74017),
26199 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26200 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
26201 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
26202 GIM_Try, /*On fail goto*//*Label 1554*/ GIMT_Encode4(72899), // Rule ID 918 //
26203 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
26204 // (ftrunc:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTZv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
26205 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv8f16),
26206 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
26207 GIR_RootConstrainSelectedInstOperands,
26208 // GIR_Coverage, 918,
26209 GIR_Done,
26210 // Label 1554: @72899
26211 GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(73084), // Rule ID 6710 //
26212 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
26213 // (ftrunc:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTZv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTZv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
26214 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
26215 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
26216 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
26217 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
26218 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
26219 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
26220 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
26221 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
26222 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
26223 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26224 GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
26225 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
26226 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f32),
26227 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26228 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
26229 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
26230 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26231 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26232 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
26233 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
26234 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
26235 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
26236 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26237 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
26238 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
26239 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f32),
26240 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26241 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
26242 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
26243 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
26244 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26245 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
26246 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
26247 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26248 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26249 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
26250 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
26251 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26252 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
26253 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
26254 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
26255 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
26256 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
26257 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
26258 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
26259 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
26260 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26261 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
26262 GIR_RootConstrainSelectedInstOperands,
26263 // GIR_Coverage, 6710,
26264 GIR_EraseRootFromParent_Done,
26265 // Label 1555: @73084
26266 GIM_Try, /*On fail goto*//*Label 1556*/ GIMT_Encode4(73219), // Rule ID 6712 //
26267 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16),
26268 // (ftrunc:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (BFCVTN2:{ *:[v8bf16] } (BFCVTN:{ *:[v8bf16] } (FRINTZv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })))), (FRINTZv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)))
26269 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
26270 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
26271 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
26272 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
26273 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
26274 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
26275 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
26276 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26277 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, // Rn
26278 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
26279 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f32),
26280 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26281 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
26282 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
26283 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26284 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26285 GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
26286 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
26287 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
26288 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
26289 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26290 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
26291 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
26292 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f32),
26293 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26294 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
26295 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
26296 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN),
26297 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26298 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
26299 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
26300 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN2),
26301 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
26302 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26303 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
26304 GIR_RootConstrainSelectedInstOperands,
26305 // GIR_Coverage, 6712,
26306 GIR_EraseRootFromParent_Done,
26307 // Label 1556: @73219
26308 GIM_Try, /*On fail goto*//*Label 1557*/ GIMT_Encode4(74016), // Rule ID 6714 //
26309 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoBF16),
26310 // (ftrunc:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (UZP2v8i16:{ *:[v8bf16] } (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FRINTZv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), (FRINTZv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FRINTZv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FRINTZv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), 64:{ *:[i32] }, 16:{ *:[i32] })), (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FRINTZv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), (FRINTZv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FRINTZv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FRINTZv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), 64:{ *:[i32] }, 16:{ *:[i32] })))
26311 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
26312 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
26313 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
26314 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
26315 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
26316 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
26317 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
26318 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
26319 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s128,
26320 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s128,
26321 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
26322 GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_v4s32,
26323 GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_v4s16,
26324 GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s128,
26325 GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_s128,
26326 GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_s128,
26327 GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_s128,
26328 GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_s128,
26329 GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_v4s32,
26330 GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_v4s32,
26331 GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_v4s16,
26332 GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s128,
26333 GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s128,
26334 GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_v4s32,
26335 GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_v4s32,
26336 GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_v4s32,
26337 GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_v4s32,
26338 GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_s128,
26339 GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_s128,
26340 GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_v4s32,
26341 GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_v4s32,
26342 GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_s128,
26343 GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_s128,
26344 GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_s128,
26345 GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_s128,
26346 GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_s128,
26347 GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_v4s32,
26348 GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_v4s32,
26349 GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
26350 GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26351 GIR_Copy, /*NewInsnID*/38, /*OldInsnID*/0, /*OpIdx*/1, // Rn
26352 GIR_ConstrainSelectedInstOperands, /*InsnID*/38,
26353 GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f32),
26354 GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26355 GIR_AddSimpleTempRegister, /*InsnID*/37, /*TempRegID*/37,
26356 GIR_ConstrainSelectedInstOperands, /*InsnID*/37,
26357 GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
26358 GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26359 GIR_AddSimpleTempRegister, /*InsnID*/36, /*TempRegID*/36,
26360 GIR_AddImm8, /*InsnID*/36, /*Imm*/64,
26361 GIR_AddImm8, /*InsnID*/36, /*Imm*/16,
26362 GIR_ConstrainSelectedInstOperands, /*InsnID*/36,
26363 GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
26364 GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26365 GIR_AddImm8, /*InsnID*/35, /*Imm*/127,
26366 GIR_AddImm, /*InsnID*/35, /*Imm*/GIMT_Encode8(264),
26367 GIR_ConstrainSelectedInstOperands, /*InsnID*/35,
26368 GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
26369 GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26370 GIR_AddImm8, /*InsnID*/34, /*Imm*/1,
26371 GIR_AddImm8, /*InsnID*/34, /*Imm*/0,
26372 GIR_ConstrainSelectedInstOperands, /*InsnID*/34,
26373 GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
26374 GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26375 GIR_Copy, /*NewInsnID*/33, /*OldInsnID*/0, /*OpIdx*/1, // Rn
26376 GIR_AddImm8, /*InsnID*/33, /*Imm*/16,
26377 GIR_ConstrainSelectedInstOperands, /*InsnID*/33,
26378 GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
26379 GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26380 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/32,
26381 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/33,
26382 GIR_ConstrainSelectedInstOperands, /*InsnID*/32,
26383 GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
26384 GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26385 GIR_Copy, /*NewInsnID*/31, /*OldInsnID*/0, /*OpIdx*/1, // Rn
26386 GIR_ConstrainSelectedInstOperands, /*InsnID*/31,
26387 GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f32),
26388 GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26389 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/30,
26390 GIR_ConstrainSelectedInstOperands, /*InsnID*/30,
26391 GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
26392 GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26393 GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/29,
26394 GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/31,
26395 GIR_ConstrainSelectedInstOperands, /*InsnID*/29,
26396 GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
26397 GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26398 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/28,
26399 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/34,
26400 GIR_ConstrainSelectedInstOperands, /*InsnID*/28,
26401 GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
26402 GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26403 GIR_Copy, /*NewInsnID*/27, /*OldInsnID*/0, /*OpIdx*/1, // Rn
26404 GIR_ConstrainSelectedInstOperands, /*InsnID*/27,
26405 GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f32),
26406 GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26407 GIR_AddSimpleTempRegister, /*InsnID*/26, /*TempRegID*/26,
26408 GIR_ConstrainSelectedInstOperands, /*InsnID*/26,
26409 GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
26410 GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26411 GIR_Copy, /*NewInsnID*/25, /*OldInsnID*/0, /*OpIdx*/1, // Rn
26412 GIR_ConstrainSelectedInstOperands, /*InsnID*/25,
26413 GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f32),
26414 GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26415 GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/24,
26416 GIR_ConstrainSelectedInstOperands, /*InsnID*/24,
26417 GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
26418 GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26419 GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/23,
26420 GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/25,
26421 GIR_ConstrainSelectedInstOperands, /*InsnID*/23,
26422 GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
26423 GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26424 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/22,
26425 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/27,
26426 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/35,
26427 GIR_ConstrainSelectedInstOperands, /*InsnID*/22,
26428 GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26429 GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26430 GIR_CopySubReg, /*NewInsnID*/21, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
26431 GIR_ConstrainOperandRC, /*InsnID*/21, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
26432 GIR_ConstrainOperandRC, /*InsnID*/21, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
26433 GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
26434 GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26435 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/20,
26436 GIR_ConstrainSelectedInstOperands, /*InsnID*/20,
26437 GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f32),
26438 GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26439 GIR_AddSimpleTempRegister, /*InsnID*/19, /*TempRegID*/19,
26440 GIR_ConstrainSelectedInstOperands, /*InsnID*/19,
26441 GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
26442 GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26443 GIR_AddSimpleTempRegister, /*InsnID*/18, /*TempRegID*/18,
26444 GIR_AddImm8, /*InsnID*/18, /*Imm*/64,
26445 GIR_AddImm8, /*InsnID*/18, /*Imm*/16,
26446 GIR_ConstrainSelectedInstOperands, /*InsnID*/18,
26447 GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
26448 GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26449 GIR_AddImm8, /*InsnID*/17, /*Imm*/127,
26450 GIR_AddImm, /*InsnID*/17, /*Imm*/GIMT_Encode8(264),
26451 GIR_ConstrainSelectedInstOperands, /*InsnID*/17,
26452 GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
26453 GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26454 GIR_AddImm8, /*InsnID*/16, /*Imm*/1,
26455 GIR_AddImm8, /*InsnID*/16, /*Imm*/0,
26456 GIR_ConstrainSelectedInstOperands, /*InsnID*/16,
26457 GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
26458 GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26459 GIR_Copy, /*NewInsnID*/15, /*OldInsnID*/0, /*OpIdx*/1, // Rn
26460 GIR_AddImm8, /*InsnID*/15, /*Imm*/16,
26461 GIR_ConstrainSelectedInstOperands, /*InsnID*/15,
26462 GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
26463 GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26464 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14,
26465 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/15,
26466 GIR_ConstrainSelectedInstOperands, /*InsnID*/14,
26467 GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26468 GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26469 GIR_CopySubReg, /*NewInsnID*/13, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
26470 GIR_ConstrainOperandRC, /*InsnID*/13, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
26471 GIR_ConstrainOperandRC, /*InsnID*/13, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
26472 GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
26473 GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26474 GIR_AddSimpleTempRegister, /*InsnID*/12, /*TempRegID*/12,
26475 GIR_ConstrainSelectedInstOperands, /*InsnID*/12,
26476 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f32),
26477 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26478 GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11,
26479 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
26480 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
26481 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26482 GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
26483 GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/13,
26484 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
26485 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
26486 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26487 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
26488 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/16,
26489 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
26490 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26491 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26492 GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
26493 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
26494 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
26495 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
26496 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26497 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
26498 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
26499 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f32),
26500 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26501 GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
26502 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
26503 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26504 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26505 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
26506 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
26507 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
26508 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
26509 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26510 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
26511 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
26512 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f32),
26513 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26514 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
26515 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
26516 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
26517 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26518 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
26519 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
26520 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
26521 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
26522 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26523 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
26524 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/8,
26525 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/17,
26526 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
26527 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
26528 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
26529 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26530 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/21,
26531 GIR_RootConstrainSelectedInstOperands,
26532 // GIR_Coverage, 6714,
26533 GIR_EraseRootFromParent_Done,
26534 // Label 1557: @74016
26535 GIM_Reject,
26536 // Label 1553: @74017
26537 GIM_Reject,
26538 // Label 1545: @74018
26539 GIM_Reject,
26540 // Label 11: @74019
26541 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 1566*/ GIMT_Encode4(75441),
26542 /*GILLT_s16*//*Label 1558*/ GIMT_Encode4(74070),
26543 /*GILLT_s32*//*Label 1559*/ GIMT_Encode4(74101),
26544 /*GILLT_s64*//*Label 1560*/ GIMT_Encode4(74132), GIMT_Encode4(0),
26545 /*GILLT_v2s32*//*Label 1561*/ GIMT_Encode4(74163),
26546 /*GILLT_v2s64*//*Label 1562*/ GIMT_Encode4(74194),
26547 /*GILLT_v4s16*//*Label 1563*/ GIMT_Encode4(74225),
26548 /*GILLT_v4s32*//*Label 1564*/ GIMT_Encode4(74256), GIMT_Encode4(0),
26549 /*GILLT_v8s16*//*Label 1565*/ GIMT_Encode4(74287),
26550 // Label 1558: @74070
26551 GIM_Try, /*On fail goto*//*Label 1567*/ GIMT_Encode4(74100), // Rule ID 522 //
26552 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
26553 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
26554 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
26555 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
26556 // (fround:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTAHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
26557 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTAHr),
26558 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
26559 GIR_RootConstrainSelectedInstOperands,
26560 // GIR_Coverage, 522,
26561 GIR_Done,
26562 // Label 1567: @74100
26563 GIM_Reject,
26564 // Label 1559: @74101
26565 GIM_Try, /*On fail goto*//*Label 1568*/ GIMT_Encode4(74131), // Rule ID 524 //
26566 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
26567 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26568 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
26569 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
26570 // (fround:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTASr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
26571 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTASr),
26572 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
26573 GIR_RootConstrainSelectedInstOperands,
26574 // GIR_Coverage, 524,
26575 GIR_Done,
26576 // Label 1568: @74131
26577 GIM_Reject,
26578 // Label 1560: @74132
26579 GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(74162), // Rule ID 526 //
26580 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
26581 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26582 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
26583 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
26584 // (fround:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTADr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
26585 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTADr),
26586 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
26587 GIR_RootConstrainSelectedInstOperands,
26588 // GIR_Coverage, 526,
26589 GIR_Done,
26590 // Label 1569: @74162
26591 GIM_Reject,
26592 // Label 1561: @74163
26593 GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(74193), // Rule ID 860 //
26594 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
26595 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
26596 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
26597 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
26598 // (fround:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTAv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
26599 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv2f32),
26600 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
26601 GIR_RootConstrainSelectedInstOperands,
26602 // GIR_Coverage, 860,
26603 GIR_Done,
26604 // Label 1570: @74193
26605 GIM_Reject,
26606 // Label 1562: @74194
26607 GIM_Try, /*On fail goto*//*Label 1571*/ GIMT_Encode4(74224), // Rule ID 864 //
26608 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
26609 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26610 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
26611 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
26612 // (fround:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTAv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
26613 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv2f64),
26614 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
26615 GIR_RootConstrainSelectedInstOperands,
26616 // GIR_Coverage, 864,
26617 GIR_Done,
26618 // Label 1571: @74224
26619 GIM_Reject,
26620 // Label 1563: @74225
26621 GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(74255), // Rule ID 856 //
26622 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
26623 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
26624 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
26625 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
26626 // (fround:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTAv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
26627 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f16),
26628 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
26629 GIR_RootConstrainSelectedInstOperands,
26630 // GIR_Coverage, 856,
26631 GIR_Done,
26632 // Label 1572: @74255
26633 GIM_Reject,
26634 // Label 1564: @74256
26635 GIM_Try, /*On fail goto*//*Label 1573*/ GIMT_Encode4(74286), // Rule ID 862 //
26636 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
26637 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26638 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
26639 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
26640 // (fround:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTAv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
26641 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f32),
26642 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
26643 GIR_RootConstrainSelectedInstOperands,
26644 // GIR_Coverage, 862,
26645 GIR_Done,
26646 // Label 1573: @74286
26647 GIM_Reject,
26648 // Label 1565: @74287
26649 GIM_Try, /*On fail goto*//*Label 1574*/ GIMT_Encode4(75440),
26650 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26651 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
26652 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
26653 GIM_Try, /*On fail goto*//*Label 1575*/ GIMT_Encode4(74322), // Rule ID 858 //
26654 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
26655 // (fround:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTAv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
26656 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv8f16),
26657 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
26658 GIR_RootConstrainSelectedInstOperands,
26659 // GIR_Coverage, 858,
26660 GIR_Done,
26661 // Label 1575: @74322
26662 GIM_Try, /*On fail goto*//*Label 1576*/ GIMT_Encode4(74507), // Rule ID 6692 //
26663 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
26664 // (fround:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTAv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTAv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
26665 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
26666 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
26667 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
26668 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
26669 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
26670 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
26671 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
26672 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
26673 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
26674 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26675 GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
26676 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
26677 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f32),
26678 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26679 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
26680 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
26681 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26682 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26683 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
26684 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
26685 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
26686 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
26687 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26688 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
26689 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
26690 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f32),
26691 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26692 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
26693 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
26694 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
26695 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26696 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
26697 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
26698 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26699 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26700 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
26701 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
26702 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26703 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
26704 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
26705 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
26706 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
26707 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
26708 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
26709 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
26710 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
26711 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26712 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
26713 GIR_RootConstrainSelectedInstOperands,
26714 // GIR_Coverage, 6692,
26715 GIR_EraseRootFromParent_Done,
26716 // Label 1576: @74507
26717 GIM_Try, /*On fail goto*//*Label 1577*/ GIMT_Encode4(74642), // Rule ID 6694 //
26718 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16),
26719 // (fround:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (BFCVTN2:{ *:[v8bf16] } (BFCVTN:{ *:[v8bf16] } (FRINTAv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })))), (FRINTAv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)))
26720 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
26721 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
26722 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
26723 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
26724 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
26725 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
26726 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
26727 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26728 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, // Rn
26729 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
26730 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f32),
26731 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26732 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
26733 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
26734 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26735 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26736 GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
26737 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
26738 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
26739 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
26740 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26741 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
26742 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
26743 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f32),
26744 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26745 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
26746 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
26747 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN),
26748 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26749 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
26750 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
26751 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN2),
26752 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
26753 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26754 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
26755 GIR_RootConstrainSelectedInstOperands,
26756 // GIR_Coverage, 6694,
26757 GIR_EraseRootFromParent_Done,
26758 // Label 1577: @74642
26759 GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(75439), // Rule ID 6696 //
26760 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoBF16),
26761 // (fround:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (UZP2v8i16:{ *:[v8bf16] } (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FRINTAv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), (FRINTAv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FRINTAv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FRINTAv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), 64:{ *:[i32] }, 16:{ *:[i32] })), (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FRINTAv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), (FRINTAv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FRINTAv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FRINTAv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), 64:{ *:[i32] }, 16:{ *:[i32] })))
26762 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
26763 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
26764 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
26765 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
26766 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
26767 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
26768 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
26769 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
26770 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s128,
26771 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s128,
26772 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
26773 GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_v4s32,
26774 GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_v4s16,
26775 GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s128,
26776 GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_s128,
26777 GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_s128,
26778 GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_s128,
26779 GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_s128,
26780 GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_v4s32,
26781 GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_v4s32,
26782 GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_v4s16,
26783 GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s128,
26784 GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s128,
26785 GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_v4s32,
26786 GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_v4s32,
26787 GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_v4s32,
26788 GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_v4s32,
26789 GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_s128,
26790 GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_s128,
26791 GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_v4s32,
26792 GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_v4s32,
26793 GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_s128,
26794 GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_s128,
26795 GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_s128,
26796 GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_s128,
26797 GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_s128,
26798 GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_v4s32,
26799 GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_v4s32,
26800 GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
26801 GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26802 GIR_Copy, /*NewInsnID*/38, /*OldInsnID*/0, /*OpIdx*/1, // Rn
26803 GIR_ConstrainSelectedInstOperands, /*InsnID*/38,
26804 GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f32),
26805 GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26806 GIR_AddSimpleTempRegister, /*InsnID*/37, /*TempRegID*/37,
26807 GIR_ConstrainSelectedInstOperands, /*InsnID*/37,
26808 GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
26809 GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26810 GIR_AddSimpleTempRegister, /*InsnID*/36, /*TempRegID*/36,
26811 GIR_AddImm8, /*InsnID*/36, /*Imm*/64,
26812 GIR_AddImm8, /*InsnID*/36, /*Imm*/16,
26813 GIR_ConstrainSelectedInstOperands, /*InsnID*/36,
26814 GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
26815 GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26816 GIR_AddImm8, /*InsnID*/35, /*Imm*/127,
26817 GIR_AddImm, /*InsnID*/35, /*Imm*/GIMT_Encode8(264),
26818 GIR_ConstrainSelectedInstOperands, /*InsnID*/35,
26819 GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
26820 GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26821 GIR_AddImm8, /*InsnID*/34, /*Imm*/1,
26822 GIR_AddImm8, /*InsnID*/34, /*Imm*/0,
26823 GIR_ConstrainSelectedInstOperands, /*InsnID*/34,
26824 GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
26825 GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26826 GIR_Copy, /*NewInsnID*/33, /*OldInsnID*/0, /*OpIdx*/1, // Rn
26827 GIR_AddImm8, /*InsnID*/33, /*Imm*/16,
26828 GIR_ConstrainSelectedInstOperands, /*InsnID*/33,
26829 GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
26830 GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26831 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/32,
26832 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/33,
26833 GIR_ConstrainSelectedInstOperands, /*InsnID*/32,
26834 GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
26835 GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26836 GIR_Copy, /*NewInsnID*/31, /*OldInsnID*/0, /*OpIdx*/1, // Rn
26837 GIR_ConstrainSelectedInstOperands, /*InsnID*/31,
26838 GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f32),
26839 GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26840 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/30,
26841 GIR_ConstrainSelectedInstOperands, /*InsnID*/30,
26842 GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
26843 GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26844 GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/29,
26845 GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/31,
26846 GIR_ConstrainSelectedInstOperands, /*InsnID*/29,
26847 GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
26848 GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26849 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/28,
26850 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/34,
26851 GIR_ConstrainSelectedInstOperands, /*InsnID*/28,
26852 GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
26853 GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26854 GIR_Copy, /*NewInsnID*/27, /*OldInsnID*/0, /*OpIdx*/1, // Rn
26855 GIR_ConstrainSelectedInstOperands, /*InsnID*/27,
26856 GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f32),
26857 GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26858 GIR_AddSimpleTempRegister, /*InsnID*/26, /*TempRegID*/26,
26859 GIR_ConstrainSelectedInstOperands, /*InsnID*/26,
26860 GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
26861 GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26862 GIR_Copy, /*NewInsnID*/25, /*OldInsnID*/0, /*OpIdx*/1, // Rn
26863 GIR_ConstrainSelectedInstOperands, /*InsnID*/25,
26864 GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f32),
26865 GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26866 GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/24,
26867 GIR_ConstrainSelectedInstOperands, /*InsnID*/24,
26868 GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
26869 GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26870 GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/23,
26871 GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/25,
26872 GIR_ConstrainSelectedInstOperands, /*InsnID*/23,
26873 GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
26874 GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26875 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/22,
26876 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/27,
26877 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/35,
26878 GIR_ConstrainSelectedInstOperands, /*InsnID*/22,
26879 GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26880 GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26881 GIR_CopySubReg, /*NewInsnID*/21, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
26882 GIR_ConstrainOperandRC, /*InsnID*/21, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
26883 GIR_ConstrainOperandRC, /*InsnID*/21, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
26884 GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
26885 GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26886 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/20,
26887 GIR_ConstrainSelectedInstOperands, /*InsnID*/20,
26888 GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f32),
26889 GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26890 GIR_AddSimpleTempRegister, /*InsnID*/19, /*TempRegID*/19,
26891 GIR_ConstrainSelectedInstOperands, /*InsnID*/19,
26892 GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
26893 GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26894 GIR_AddSimpleTempRegister, /*InsnID*/18, /*TempRegID*/18,
26895 GIR_AddImm8, /*InsnID*/18, /*Imm*/64,
26896 GIR_AddImm8, /*InsnID*/18, /*Imm*/16,
26897 GIR_ConstrainSelectedInstOperands, /*InsnID*/18,
26898 GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
26899 GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26900 GIR_AddImm8, /*InsnID*/17, /*Imm*/127,
26901 GIR_AddImm, /*InsnID*/17, /*Imm*/GIMT_Encode8(264),
26902 GIR_ConstrainSelectedInstOperands, /*InsnID*/17,
26903 GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
26904 GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26905 GIR_AddImm8, /*InsnID*/16, /*Imm*/1,
26906 GIR_AddImm8, /*InsnID*/16, /*Imm*/0,
26907 GIR_ConstrainSelectedInstOperands, /*InsnID*/16,
26908 GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
26909 GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26910 GIR_Copy, /*NewInsnID*/15, /*OldInsnID*/0, /*OpIdx*/1, // Rn
26911 GIR_AddImm8, /*InsnID*/15, /*Imm*/16,
26912 GIR_ConstrainSelectedInstOperands, /*InsnID*/15,
26913 GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
26914 GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26915 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14,
26916 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/15,
26917 GIR_ConstrainSelectedInstOperands, /*InsnID*/14,
26918 GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26919 GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26920 GIR_CopySubReg, /*NewInsnID*/13, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
26921 GIR_ConstrainOperandRC, /*InsnID*/13, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
26922 GIR_ConstrainOperandRC, /*InsnID*/13, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
26923 GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
26924 GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26925 GIR_AddSimpleTempRegister, /*InsnID*/12, /*TempRegID*/12,
26926 GIR_ConstrainSelectedInstOperands, /*InsnID*/12,
26927 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f32),
26928 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26929 GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11,
26930 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
26931 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
26932 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26933 GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
26934 GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/13,
26935 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
26936 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
26937 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26938 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
26939 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/16,
26940 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
26941 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26942 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26943 GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
26944 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
26945 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
26946 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
26947 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26948 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
26949 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
26950 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f32),
26951 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26952 GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
26953 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
26954 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
26955 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26956 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
26957 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
26958 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
26959 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
26960 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26961 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
26962 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
26963 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f32),
26964 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26965 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
26966 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
26967 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
26968 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26969 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
26970 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
26971 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
26972 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
26973 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
26974 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
26975 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/8,
26976 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/17,
26977 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
26978 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
26979 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
26980 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26981 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/21,
26982 GIR_RootConstrainSelectedInstOperands,
26983 // GIR_Coverage, 6696,
26984 GIR_EraseRootFromParent_Done,
26985 // Label 1578: @75439
26986 GIM_Reject,
26987 // Label 1574: @75440
26988 GIM_Reject,
26989 // Label 1566: @75441
26990 GIM_Reject,
26991 // Label 12: @75442
26992 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 1581*/ GIMT_Encode4(75709),
26993 /*GILLT_s32*//*Label 1579*/ GIMT_Encode4(75461),
26994 /*GILLT_s64*//*Label 1580*/ GIMT_Encode4(75585),
26995 // Label 1579: @75461
26996 GIM_Try, /*On fail goto*//*Label 1582*/ GIMT_Encode4(75504), // Rule ID 4470 //
26997 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
26998 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
26999 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
27000 // (lrint:{ *:[i32] } f16:{ *:[f16] }:$Rn) => (FCVTZSUWHr:{ *:[i32] } (FRINTXHr:{ *:[i16] } f16:{ *:[f16] }:$Rn))
27001 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
27002 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXHr),
27003 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27004 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
27005 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
27006 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWHr),
27007 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27008 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27009 GIR_RootConstrainSelectedInstOperands,
27010 // GIR_Coverage, 4470,
27011 GIR_EraseRootFromParent_Done,
27012 // Label 1582: @75504
27013 GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(75544), // Rule ID 4476 //
27014 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
27015 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
27016 // (lrint:{ *:[i32] } f32:{ *:[f32] }:$Rn) => (FCVTZSUWSr:{ *:[i32] } (FRINTXSr:{ *:[i32] } f32:{ *:[f32] }:$Rn))
27017 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
27018 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXSr),
27019 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27020 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
27021 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
27022 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWSr),
27023 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27024 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27025 GIR_RootConstrainSelectedInstOperands,
27026 // GIR_Coverage, 4476,
27027 GIR_EraseRootFromParent_Done,
27028 // Label 1583: @75544
27029 GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(75584), // Rule ID 4478 //
27030 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
27031 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
27032 // (lrint:{ *:[i32] } f64:{ *:[f64] }:$Rn) => (FCVTZSUWDr:{ *:[i32] } (FRINTXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn))
27033 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
27034 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXDr),
27035 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27036 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
27037 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
27038 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWDr),
27039 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27040 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27041 GIR_RootConstrainSelectedInstOperands,
27042 // GIR_Coverage, 4478,
27043 GIR_EraseRootFromParent_Done,
27044 // Label 1584: @75584
27045 GIM_Reject,
27046 // Label 1580: @75585
27047 GIM_Try, /*On fail goto*//*Label 1585*/ GIMT_Encode4(75628), // Rule ID 4472 //
27048 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
27049 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
27050 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
27051 // (lrint:{ *:[i64] } f16:{ *:[f16] }:$Rn) => (FCVTZSUXHr:{ *:[i64] } (FRINTXHr:{ *:[i16] } f16:{ *:[f16] }:$Rn))
27052 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
27053 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXHr),
27054 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27055 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
27056 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
27057 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXHr),
27058 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27059 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27060 GIR_RootConstrainSelectedInstOperands,
27061 // GIR_Coverage, 4472,
27062 GIR_EraseRootFromParent_Done,
27063 // Label 1585: @75628
27064 GIM_Try, /*On fail goto*//*Label 1586*/ GIMT_Encode4(75668), // Rule ID 4480 //
27065 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
27066 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
27067 // (lrint:{ *:[i64] } f32:{ *:[f32] }:$Rn) => (FCVTZSUXSr:{ *:[i64] } (FRINTXSr:{ *:[i32] } f32:{ *:[f32] }:$Rn))
27068 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
27069 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXSr),
27070 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27071 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
27072 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
27073 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXSr),
27074 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27075 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27076 GIR_RootConstrainSelectedInstOperands,
27077 // GIR_Coverage, 4480,
27078 GIR_EraseRootFromParent_Done,
27079 // Label 1586: @75668
27080 GIM_Try, /*On fail goto*//*Label 1587*/ GIMT_Encode4(75708), // Rule ID 4482 //
27081 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
27082 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
27083 // (lrint:{ *:[i64] } f64:{ *:[f64] }:$Rn) => (FCVTZSUXDr:{ *:[i64] } (FRINTXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn))
27084 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
27085 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXDr),
27086 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27087 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
27088 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
27089 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXDr),
27090 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27091 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27092 GIR_RootConstrainSelectedInstOperands,
27093 // GIR_Coverage, 4482,
27094 GIR_EraseRootFromParent_Done,
27095 // Label 1587: @75708
27096 GIM_Reject,
27097 // Label 1581: @75709
27098 GIM_Reject,
27099 // Label 13: @75710
27100 GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(75859),
27101 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
27102 GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 1592*/ GIMT_Encode4(75858),
27103 /*GILLT_s16*//*Label 1589*/ GIMT_Encode4(75741),
27104 /*GILLT_s32*//*Label 1590*/ GIMT_Encode4(75782),
27105 /*GILLT_s64*//*Label 1591*/ GIMT_Encode4(75820),
27106 // Label 1589: @75741
27107 GIM_Try, /*On fail goto*//*Label 1593*/ GIMT_Encode4(75781), // Rule ID 4474 //
27108 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
27109 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
27110 // (llrint:{ *:[i64] } f16:{ *:[f16] }:$Rn) => (FCVTZSUXHr:{ *:[i64] } (FRINTXHr:{ *:[i16] } f16:{ *:[f16] }:$Rn))
27111 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
27112 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXHr),
27113 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27114 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
27115 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
27116 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXHr),
27117 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27118 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27119 GIR_RootConstrainSelectedInstOperands,
27120 // GIR_Coverage, 4474,
27121 GIR_EraseRootFromParent_Done,
27122 // Label 1593: @75781
27123 GIM_Reject,
27124 // Label 1590: @75782
27125 GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(75819), // Rule ID 4484 //
27126 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
27127 // (llrint:{ *:[i64] } f32:{ *:[f32] }:$Rn) => (FCVTZSUXSr:{ *:[i64] } (FRINTXSr:{ *:[i32] } f32:{ *:[f32] }:$Rn))
27128 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
27129 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXSr),
27130 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27131 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
27132 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
27133 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXSr),
27134 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27135 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27136 GIR_RootConstrainSelectedInstOperands,
27137 // GIR_Coverage, 4484,
27138 GIR_EraseRootFromParent_Done,
27139 // Label 1594: @75819
27140 GIM_Reject,
27141 // Label 1591: @75820
27142 GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(75857), // Rule ID 4486 //
27143 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
27144 // (llrint:{ *:[i64] } f64:{ *:[f64] }:$Rn) => (FCVTZSUXDr:{ *:[i64] } (FRINTXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn))
27145 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
27146 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXDr),
27147 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27148 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
27149 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
27150 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXDr),
27151 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27152 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27153 GIR_RootConstrainSelectedInstOperands,
27154 // GIR_Coverage, 4486,
27155 GIR_EraseRootFromParent_Done,
27156 // Label 1595: @75857
27157 GIM_Reject,
27158 // Label 1592: @75858
27159 GIM_Reject,
27160 // Label 1588: @75859
27161 GIM_Reject,
27162 // Label 14: @75860
27163 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 1604*/ GIMT_Encode4(77282),
27164 /*GILLT_s16*//*Label 1596*/ GIMT_Encode4(75911),
27165 /*GILLT_s32*//*Label 1597*/ GIMT_Encode4(75942),
27166 /*GILLT_s64*//*Label 1598*/ GIMT_Encode4(75973), GIMT_Encode4(0),
27167 /*GILLT_v2s32*//*Label 1599*/ GIMT_Encode4(76004),
27168 /*GILLT_v2s64*//*Label 1600*/ GIMT_Encode4(76035),
27169 /*GILLT_v4s16*//*Label 1601*/ GIMT_Encode4(76066),
27170 /*GILLT_v4s32*//*Label 1602*/ GIMT_Encode4(76097), GIMT_Encode4(0),
27171 /*GILLT_v8s16*//*Label 1603*/ GIMT_Encode4(76128),
27172 // Label 1596: @75911
27173 GIM_Try, /*On fail goto*//*Label 1605*/ GIMT_Encode4(75941), // Rule ID 540 //
27174 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
27175 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
27176 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
27177 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
27178 // (froundeven:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTNHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
27179 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNHr),
27180 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
27181 GIR_RootConstrainSelectedInstOperands,
27182 // GIR_Coverage, 540,
27183 GIR_Done,
27184 // Label 1605: @75941
27185 GIM_Reject,
27186 // Label 1597: @75942
27187 GIM_Try, /*On fail goto*//*Label 1606*/ GIMT_Encode4(75972), // Rule ID 542 //
27188 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
27189 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
27190 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
27191 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
27192 // (froundeven:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTNSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
27193 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNSr),
27194 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
27195 GIR_RootConstrainSelectedInstOperands,
27196 // GIR_Coverage, 542,
27197 GIR_Done,
27198 // Label 1606: @75972
27199 GIM_Reject,
27200 // Label 1598: @75973
27201 GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(76003), // Rule ID 544 //
27202 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
27203 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
27204 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
27205 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
27206 // (froundeven:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTNDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
27207 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNDr),
27208 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
27209 GIR_RootConstrainSelectedInstOperands,
27210 // GIR_Coverage, 544,
27211 GIR_Done,
27212 // Label 1607: @76003
27213 GIM_Reject,
27214 // Label 1599: @76004
27215 GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(76034), // Rule ID 890 //
27216 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
27217 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
27218 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
27219 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
27220 // (froundeven:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTNv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
27221 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv2f32),
27222 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
27223 GIR_RootConstrainSelectedInstOperands,
27224 // GIR_Coverage, 890,
27225 GIR_Done,
27226 // Label 1608: @76034
27227 GIM_Reject,
27228 // Label 1600: @76035
27229 GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(76065), // Rule ID 894 //
27230 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
27231 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
27232 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
27233 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
27234 // (froundeven:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTNv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
27235 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv2f64),
27236 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
27237 GIR_RootConstrainSelectedInstOperands,
27238 // GIR_Coverage, 894,
27239 GIR_Done,
27240 // Label 1609: @76065
27241 GIM_Reject,
27242 // Label 1601: @76066
27243 GIM_Try, /*On fail goto*//*Label 1610*/ GIMT_Encode4(76096), // Rule ID 886 //
27244 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
27245 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
27246 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
27247 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
27248 // (froundeven:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTNv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
27249 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f16),
27250 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
27251 GIR_RootConstrainSelectedInstOperands,
27252 // GIR_Coverage, 886,
27253 GIR_Done,
27254 // Label 1610: @76096
27255 GIM_Reject,
27256 // Label 1602: @76097
27257 GIM_Try, /*On fail goto*//*Label 1611*/ GIMT_Encode4(76127), // Rule ID 892 //
27258 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
27259 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
27260 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
27261 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
27262 // (froundeven:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTNv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
27263 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f32),
27264 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
27265 GIR_RootConstrainSelectedInstOperands,
27266 // GIR_Coverage, 892,
27267 GIR_Done,
27268 // Label 1611: @76127
27269 GIM_Reject,
27270 // Label 1603: @76128
27271 GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(77281),
27272 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
27273 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
27274 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
27275 GIM_Try, /*On fail goto*//*Label 1613*/ GIMT_Encode4(76163), // Rule ID 888 //
27276 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
27277 // (froundeven:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTNv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
27278 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv8f16),
27279 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
27280 GIR_RootConstrainSelectedInstOperands,
27281 // GIR_Coverage, 888,
27282 GIR_Done,
27283 // Label 1613: @76163
27284 GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(76348), // Rule ID 6698 //
27285 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
27286 // (froundeven:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTNv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTNv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
27287 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
27288 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
27289 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
27290 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
27291 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
27292 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
27293 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
27294 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
27295 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
27296 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27297 GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
27298 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
27299 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f32),
27300 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27301 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
27302 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
27303 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27304 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27305 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
27306 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
27307 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
27308 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
27309 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27310 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
27311 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
27312 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f32),
27313 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27314 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
27315 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
27316 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
27317 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27318 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
27319 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
27320 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27321 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27322 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
27323 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
27324 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27325 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
27326 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
27327 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
27328 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
27329 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
27330 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
27331 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
27332 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27333 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27334 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
27335 GIR_RootConstrainSelectedInstOperands,
27336 // GIR_Coverage, 6698,
27337 GIR_EraseRootFromParent_Done,
27338 // Label 1614: @76348
27339 GIM_Try, /*On fail goto*//*Label 1615*/ GIMT_Encode4(76483), // Rule ID 6700 //
27340 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16),
27341 // (froundeven:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (BFCVTN2:{ *:[v8bf16] } (BFCVTN:{ *:[v8bf16] } (FRINTNv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })))), (FRINTNv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)))
27342 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
27343 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
27344 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
27345 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
27346 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
27347 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
27348 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
27349 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27350 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, // Rn
27351 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
27352 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f32),
27353 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27354 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
27355 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
27356 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27357 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27358 GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
27359 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
27360 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
27361 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
27362 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27363 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
27364 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
27365 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f32),
27366 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27367 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
27368 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
27369 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN),
27370 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27371 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
27372 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
27373 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN2),
27374 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27375 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27376 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
27377 GIR_RootConstrainSelectedInstOperands,
27378 // GIR_Coverage, 6700,
27379 GIR_EraseRootFromParent_Done,
27380 // Label 1615: @76483
27381 GIM_Try, /*On fail goto*//*Label 1616*/ GIMT_Encode4(77280), // Rule ID 6702 //
27382 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoBF16),
27383 // (froundeven:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (UZP2v8i16:{ *:[v8bf16] } (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FRINTNv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), (FRINTNv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FRINTNv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FRINTNv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), 64:{ *:[i32] }, 16:{ *:[i32] })), (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FRINTNv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), (FRINTNv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FRINTNv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FRINTNv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), 64:{ *:[i32] }, 16:{ *:[i32] })))
27384 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
27385 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
27386 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
27387 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
27388 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
27389 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
27390 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
27391 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
27392 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s128,
27393 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s128,
27394 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
27395 GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_v4s32,
27396 GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_v4s16,
27397 GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s128,
27398 GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_s128,
27399 GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_s128,
27400 GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_s128,
27401 GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_s128,
27402 GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_v4s32,
27403 GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_v4s32,
27404 GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_v4s16,
27405 GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s128,
27406 GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s128,
27407 GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_v4s32,
27408 GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_v4s32,
27409 GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_v4s32,
27410 GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_v4s32,
27411 GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_s128,
27412 GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_s128,
27413 GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_v4s32,
27414 GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_v4s32,
27415 GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_s128,
27416 GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_s128,
27417 GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_s128,
27418 GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_s128,
27419 GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_s128,
27420 GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_v4s32,
27421 GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_v4s32,
27422 GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
27423 GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27424 GIR_Copy, /*NewInsnID*/38, /*OldInsnID*/0, /*OpIdx*/1, // Rn
27425 GIR_ConstrainSelectedInstOperands, /*InsnID*/38,
27426 GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f32),
27427 GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27428 GIR_AddSimpleTempRegister, /*InsnID*/37, /*TempRegID*/37,
27429 GIR_ConstrainSelectedInstOperands, /*InsnID*/37,
27430 GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
27431 GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27432 GIR_AddSimpleTempRegister, /*InsnID*/36, /*TempRegID*/36,
27433 GIR_AddImm8, /*InsnID*/36, /*Imm*/64,
27434 GIR_AddImm8, /*InsnID*/36, /*Imm*/16,
27435 GIR_ConstrainSelectedInstOperands, /*InsnID*/36,
27436 GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
27437 GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27438 GIR_AddImm8, /*InsnID*/35, /*Imm*/127,
27439 GIR_AddImm, /*InsnID*/35, /*Imm*/GIMT_Encode8(264),
27440 GIR_ConstrainSelectedInstOperands, /*InsnID*/35,
27441 GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
27442 GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27443 GIR_AddImm8, /*InsnID*/34, /*Imm*/1,
27444 GIR_AddImm8, /*InsnID*/34, /*Imm*/0,
27445 GIR_ConstrainSelectedInstOperands, /*InsnID*/34,
27446 GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
27447 GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27448 GIR_Copy, /*NewInsnID*/33, /*OldInsnID*/0, /*OpIdx*/1, // Rn
27449 GIR_AddImm8, /*InsnID*/33, /*Imm*/16,
27450 GIR_ConstrainSelectedInstOperands, /*InsnID*/33,
27451 GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
27452 GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27453 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/32,
27454 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/33,
27455 GIR_ConstrainSelectedInstOperands, /*InsnID*/32,
27456 GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
27457 GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27458 GIR_Copy, /*NewInsnID*/31, /*OldInsnID*/0, /*OpIdx*/1, // Rn
27459 GIR_ConstrainSelectedInstOperands, /*InsnID*/31,
27460 GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f32),
27461 GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27462 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/30,
27463 GIR_ConstrainSelectedInstOperands, /*InsnID*/30,
27464 GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
27465 GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27466 GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/29,
27467 GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/31,
27468 GIR_ConstrainSelectedInstOperands, /*InsnID*/29,
27469 GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
27470 GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27471 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/28,
27472 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/34,
27473 GIR_ConstrainSelectedInstOperands, /*InsnID*/28,
27474 GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
27475 GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27476 GIR_Copy, /*NewInsnID*/27, /*OldInsnID*/0, /*OpIdx*/1, // Rn
27477 GIR_ConstrainSelectedInstOperands, /*InsnID*/27,
27478 GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f32),
27479 GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27480 GIR_AddSimpleTempRegister, /*InsnID*/26, /*TempRegID*/26,
27481 GIR_ConstrainSelectedInstOperands, /*InsnID*/26,
27482 GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
27483 GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27484 GIR_Copy, /*NewInsnID*/25, /*OldInsnID*/0, /*OpIdx*/1, // Rn
27485 GIR_ConstrainSelectedInstOperands, /*InsnID*/25,
27486 GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f32),
27487 GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27488 GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/24,
27489 GIR_ConstrainSelectedInstOperands, /*InsnID*/24,
27490 GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
27491 GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27492 GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/23,
27493 GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/25,
27494 GIR_ConstrainSelectedInstOperands, /*InsnID*/23,
27495 GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
27496 GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27497 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/22,
27498 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/27,
27499 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/35,
27500 GIR_ConstrainSelectedInstOperands, /*InsnID*/22,
27501 GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27502 GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27503 GIR_CopySubReg, /*NewInsnID*/21, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
27504 GIR_ConstrainOperandRC, /*InsnID*/21, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
27505 GIR_ConstrainOperandRC, /*InsnID*/21, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
27506 GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
27507 GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27508 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/20,
27509 GIR_ConstrainSelectedInstOperands, /*InsnID*/20,
27510 GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f32),
27511 GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27512 GIR_AddSimpleTempRegister, /*InsnID*/19, /*TempRegID*/19,
27513 GIR_ConstrainSelectedInstOperands, /*InsnID*/19,
27514 GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
27515 GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27516 GIR_AddSimpleTempRegister, /*InsnID*/18, /*TempRegID*/18,
27517 GIR_AddImm8, /*InsnID*/18, /*Imm*/64,
27518 GIR_AddImm8, /*InsnID*/18, /*Imm*/16,
27519 GIR_ConstrainSelectedInstOperands, /*InsnID*/18,
27520 GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
27521 GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27522 GIR_AddImm8, /*InsnID*/17, /*Imm*/127,
27523 GIR_AddImm, /*InsnID*/17, /*Imm*/GIMT_Encode8(264),
27524 GIR_ConstrainSelectedInstOperands, /*InsnID*/17,
27525 GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
27526 GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27527 GIR_AddImm8, /*InsnID*/16, /*Imm*/1,
27528 GIR_AddImm8, /*InsnID*/16, /*Imm*/0,
27529 GIR_ConstrainSelectedInstOperands, /*InsnID*/16,
27530 GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
27531 GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27532 GIR_Copy, /*NewInsnID*/15, /*OldInsnID*/0, /*OpIdx*/1, // Rn
27533 GIR_AddImm8, /*InsnID*/15, /*Imm*/16,
27534 GIR_ConstrainSelectedInstOperands, /*InsnID*/15,
27535 GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
27536 GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27537 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14,
27538 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/15,
27539 GIR_ConstrainSelectedInstOperands, /*InsnID*/14,
27540 GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27541 GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27542 GIR_CopySubReg, /*NewInsnID*/13, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
27543 GIR_ConstrainOperandRC, /*InsnID*/13, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
27544 GIR_ConstrainOperandRC, /*InsnID*/13, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
27545 GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
27546 GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27547 GIR_AddSimpleTempRegister, /*InsnID*/12, /*TempRegID*/12,
27548 GIR_ConstrainSelectedInstOperands, /*InsnID*/12,
27549 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f32),
27550 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27551 GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11,
27552 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
27553 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
27554 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27555 GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
27556 GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/13,
27557 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
27558 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
27559 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27560 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
27561 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/16,
27562 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
27563 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27564 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27565 GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
27566 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
27567 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
27568 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
27569 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27570 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
27571 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
27572 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f32),
27573 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27574 GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
27575 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
27576 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
27577 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27578 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
27579 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
27580 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
27581 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
27582 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27583 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
27584 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
27585 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f32),
27586 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27587 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
27588 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
27589 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
27590 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27591 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
27592 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
27593 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
27594 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
27595 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
27596 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
27597 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/8,
27598 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/17,
27599 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
27600 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
27601 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27602 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27603 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/21,
27604 GIR_RootConstrainSelectedInstOperands,
27605 // GIR_Coverage, 6702,
27606 GIR_EraseRootFromParent_Done,
27607 // Label 1616: @77280
27608 GIM_Reject,
27609 // Label 1612: @77281
27610 GIM_Reject,
27611 // Label 1604: @77282
27612 GIM_Reject,
27613 // Label 15: @77283
27614 GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(77315), // Rule ID 3773 //
27615 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
27616 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
27617 // (readcyclecounter:{ *:[i64] }) => (MRS:{ *:[i64] }:{ *:[i32] } 57090:{ *:[i32] })
27618 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MRS),
27619 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27620 GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(57090),
27621 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
27622 GIR_RootConstrainSelectedInstOperands,
27623 // GIR_Coverage, 3773,
27624 GIR_EraseRootFromParent_Done,
27625 // Label 1617: @77315
27626 GIM_Reject,
27627 // Label 16: @77316
27628 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(24), /*)*//*default:*//*Label 1638*/ GIMT_Encode4(86381),
27629 /*GILLT_s8*//*Label 1618*/ GIMT_Encode4(77423),
27630 /*GILLT_s16*//*Label 1619*/ GIMT_Encode4(77599),
27631 /*GILLT_s32*//*Label 1620*/ GIMT_Encode4(77841),
27632 /*GILLT_s64*//*Label 1621*/ GIMT_Encode4(80139),
27633 /*GILLT_s128*//*Label 1622*/ GIMT_Encode4(82820),
27634 /*GILLT_v2s32*//*Label 1623*/ GIMT_Encode4(83029),
27635 /*GILLT_v2s64*//*Label 1624*/ GIMT_Encode4(83407),
27636 /*GILLT_v4s16*//*Label 1625*/ GIMT_Encode4(83785),
27637 /*GILLT_v4s32*//*Label 1626*/ GIMT_Encode4(84293),
27638 /*GILLT_v8s8*//*Label 1627*/ GIMT_Encode4(84671),
27639 /*GILLT_v8s16*//*Label 1628*/ GIMT_Encode4(84879),
27640 /*GILLT_v16s8*//*Label 1629*/ GIMT_Encode4(85387), GIMT_Encode4(0), GIMT_Encode4(0),
27641 /*GILLT_nxv2s16*//*Label 1630*/ GIMT_Encode4(85595),
27642 /*GILLT_nxv2s32*//*Label 1631*/ GIMT_Encode4(85709),
27643 /*GILLT_nxv2s64*//*Label 1632*/ GIMT_Encode4(85773), GIMT_Encode4(0),
27644 /*GILLT_nxv4s16*//*Label 1633*/ GIMT_Encode4(85887),
27645 /*GILLT_nxv4s32*//*Label 1634*/ GIMT_Encode4(86001), GIMT_Encode4(0),
27646 /*GILLT_nxv8s16*//*Label 1635*/ GIMT_Encode4(86115),
27647 /*GILLT_nxv16s1*//*Label 1636*/ GIMT_Encode4(86273),
27648 /*GILLT_nxv16s8*//*Label 1637*/ GIMT_Encode4(86317),
27649 // Label 1618: @77423
27650 GIM_Try, /*On fail goto*//*Label 1639*/ GIMT_Encode4(77598),
27651 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
27652 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
27653 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
27654 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
27655 GIM_Try, /*On fail goto*//*Label 1640*/ GIMT_Encode4(77484), // Rule ID 247 //
27656 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
27657 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
27658 // (ld:{ *:[i8] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
27659 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
27660 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27661 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27662 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
27663 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
27664 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27665 GIR_RootConstrainSelectedInstOperands,
27666 // GIR_Coverage, 247,
27667 GIR_EraseRootFromParent_Done,
27668 // Label 1640: @77484
27669 GIM_Try, /*On fail goto*//*Label 1641*/ GIMT_Encode4(77525), // Rule ID 248 //
27670 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
27671 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
27672 // (ld:{ *:[i8] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
27673 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
27674 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27675 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27676 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
27677 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
27678 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27679 GIR_RootConstrainSelectedInstOperands,
27680 // GIR_Coverage, 248,
27681 GIR_EraseRootFromParent_Done,
27682 // Label 1641: @77525
27683 GIM_Try, /*On fail goto*//*Label 1642*/ GIMT_Encode4(77561), // Rule ID 271 //
27684 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
27685 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
27686 // (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
27687 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
27688 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27689 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27690 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
27691 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27692 GIR_RootConstrainSelectedInstOperands,
27693 // GIR_Coverage, 271,
27694 GIR_EraseRootFromParent_Done,
27695 // Label 1642: @77561
27696 GIM_Try, /*On fail goto*//*Label 1643*/ GIMT_Encode4(77597), // Rule ID 292 //
27697 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
27698 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
27699 // (ld:{ *:[i8] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
27700 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
27701 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27702 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27703 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
27704 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27705 GIR_RootConstrainSelectedInstOperands,
27706 // GIR_Coverage, 292,
27707 GIR_EraseRootFromParent_Done,
27708 // Label 1643: @77597
27709 GIM_Reject,
27710 // Label 1639: @77598
27711 GIM_Reject,
27712 // Label 1619: @77599
27713 GIM_Try, /*On fail goto*//*Label 1644*/ GIMT_Encode4(77840),
27714 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
27715 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
27716 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
27717 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
27718 GIM_Try, /*On fail goto*//*Label 1645*/ GIMT_Encode4(77660), // Rule ID 249 //
27719 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
27720 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
27721 // (ld:{ *:[f16] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRHroW:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
27722 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
27723 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27724 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27725 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
27726 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
27727 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27728 GIR_RootConstrainSelectedInstOperands,
27729 // GIR_Coverage, 249,
27730 GIR_EraseRootFromParent_Done,
27731 // Label 1645: @77660
27732 GIM_Try, /*On fail goto*//*Label 1646*/ GIMT_Encode4(77701), // Rule ID 250 //
27733 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
27734 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
27735 // (ld:{ *:[f16] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRHroX:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
27736 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
27737 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27738 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27739 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
27740 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
27741 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27742 GIR_RootConstrainSelectedInstOperands,
27743 // GIR_Coverage, 250,
27744 GIR_EraseRootFromParent_Done,
27745 // Label 1646: @77701
27746 GIM_Try, /*On fail goto*//*Label 1647*/ GIMT_Encode4(77737), // Rule ID 272 //
27747 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
27748 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
27749 // (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRHui:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
27750 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
27751 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27752 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27753 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
27754 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27755 GIR_RootConstrainSelectedInstOperands,
27756 // GIR_Coverage, 272,
27757 GIR_EraseRootFromParent_Done,
27758 // Label 1647: @77737
27759 GIM_Try, /*On fail goto*//*Label 1648*/ GIMT_Encode4(77773), // Rule ID 293 //
27760 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
27761 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
27762 // (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURHi:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
27763 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
27764 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27765 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27766 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
27767 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27768 GIR_RootConstrainSelectedInstOperands,
27769 // GIR_Coverage, 293,
27770 GIR_EraseRootFromParent_Done,
27771 // Label 1648: @77773
27772 GIM_Try, /*On fail goto*//*Label 1649*/ GIMT_Encode4(77806), // Rule ID 4024 //
27773 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
27774 // (ld:{ *:[bf16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRHui:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
27775 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
27776 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27777 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27778 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
27779 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27780 GIR_RootConstrainSelectedInstOperands,
27781 // GIR_Coverage, 4024,
27782 GIR_EraseRootFromParent_Done,
27783 // Label 1649: @77806
27784 GIM_Try, /*On fail goto*//*Label 1650*/ GIMT_Encode4(77839), // Rule ID 4063 //
27785 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
27786 // (ld:{ *:[bf16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURHi:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
27787 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
27788 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27789 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27790 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
27791 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27792 GIR_RootConstrainSelectedInstOperands,
27793 // GIR_Coverage, 4063,
27794 GIR_EraseRootFromParent_Done,
27795 // Label 1650: @77839
27796 GIM_Reject,
27797 // Label 1644: @77840
27798 GIM_Reject,
27799 // Label 1620: @77841
27800 GIM_Try, /*On fail goto*//*Label 1651*/ GIMT_Encode4(77894), // Rule ID 243 //
27801 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
27802 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
27803 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
27804 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
27805 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
27806 // (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
27807 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWroW),
27808 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27809 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27810 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
27811 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
27812 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27813 GIR_RootConstrainSelectedInstOperands,
27814 // GIR_Coverage, 243,
27815 GIR_EraseRootFromParent_Done,
27816 // Label 1651: @77894
27817 GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(77947), // Rule ID 244 //
27818 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
27819 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
27820 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
27821 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
27822 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
27823 // (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
27824 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWroX),
27825 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27826 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27827 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
27828 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
27829 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27830 GIR_RootConstrainSelectedInstOperands,
27831 // GIR_Coverage, 244,
27832 GIR_EraseRootFromParent_Done,
27833 // Label 1652: @77947
27834 GIM_Try, /*On fail goto*//*Label 1653*/ GIMT_Encode4(78003), // Rule ID 251 //
27835 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
27836 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
27837 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
27838 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
27839 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
27840 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
27841 // (ld:{ *:[f32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRSroW:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
27842 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
27843 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27844 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27845 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
27846 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
27847 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27848 GIR_RootConstrainSelectedInstOperands,
27849 // GIR_Coverage, 251,
27850 GIR_EraseRootFromParent_Done,
27851 // Label 1653: @78003
27852 GIM_Try, /*On fail goto*//*Label 1654*/ GIMT_Encode4(78059), // Rule ID 252 //
27853 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
27854 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
27855 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
27856 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
27857 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
27858 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
27859 // (ld:{ *:[f32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRSroX:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
27860 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
27861 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27862 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27863 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
27864 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
27865 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27866 GIR_RootConstrainSelectedInstOperands,
27867 // GIR_Coverage, 252,
27868 GIR_EraseRootFromParent_Done,
27869 // Label 1654: @78059
27870 GIM_Try, /*On fail goto*//*Label 1655*/ GIMT_Encode4(78119), // Rule ID 4016 //
27871 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
27872 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
27873 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
27874 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
27875 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
27876 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
27877 // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
27878 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
27879 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27880 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27881 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
27882 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
27883 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27884 GIR_RootConstrainSelectedInstOperands,
27885 // GIR_Coverage, 4016,
27886 GIR_EraseRootFromParent_Done,
27887 // Label 1655: @78119
27888 GIM_Try, /*On fail goto*//*Label 1656*/ GIMT_Encode4(78179), // Rule ID 4017 //
27889 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
27890 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
27891 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
27892 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
27893 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
27894 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
27895 // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
27896 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
27897 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27898 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27899 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
27900 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
27901 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27902 GIR_RootConstrainSelectedInstOperands,
27903 // GIR_Coverage, 4017,
27904 GIR_EraseRootFromParent_Done,
27905 // Label 1656: @78179
27906 GIM_Try, /*On fail goto*//*Label 1657*/ GIMT_Encode4(78239), // Rule ID 4018 //
27907 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
27908 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
27909 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
27910 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
27911 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
27912 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
27913 // (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
27914 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroW),
27915 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27916 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27917 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
27918 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
27919 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27920 GIR_RootConstrainSelectedInstOperands,
27921 // GIR_Coverage, 4018,
27922 GIR_EraseRootFromParent_Done,
27923 // Label 1657: @78239
27924 GIM_Try, /*On fail goto*//*Label 1658*/ GIMT_Encode4(78299), // Rule ID 4019 //
27925 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
27926 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
27927 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
27928 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
27929 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
27930 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
27931 // (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
27932 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroX),
27933 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27934 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27935 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
27936 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
27937 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27938 GIR_RootConstrainSelectedInstOperands,
27939 // GIR_Coverage, 4019,
27940 GIR_EraseRootFromParent_Done,
27941 // Label 1658: @78299
27942 GIM_Try, /*On fail goto*//*Label 1659*/ GIMT_Encode4(78359), // Rule ID 4020 //
27943 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
27944 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
27945 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
27946 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
27947 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
27948 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
27949 // (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
27950 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWroW),
27951 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27952 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27953 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
27954 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
27955 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27956 GIR_RootConstrainSelectedInstOperands,
27957 // GIR_Coverage, 4020,
27958 GIR_EraseRootFromParent_Done,
27959 // Label 1659: @78359
27960 GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(78419), // Rule ID 4021 //
27961 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
27962 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
27963 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
27964 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
27965 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
27966 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
27967 // (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
27968 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWroX),
27969 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27970 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27971 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
27972 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
27973 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27974 GIR_RootConstrainSelectedInstOperands,
27975 // GIR_Coverage, 4021,
27976 GIR_EraseRootFromParent_Done,
27977 // Label 1660: @78419
27978 GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(78467), // Rule ID 270 //
27979 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
27980 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
27981 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
27982 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
27983 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
27984 // (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
27985 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWui),
27986 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
27987 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
27988 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
27989 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
27990 GIR_RootConstrainSelectedInstOperands,
27991 // GIR_Coverage, 270,
27992 GIR_EraseRootFromParent_Done,
27993 // Label 1661: @78467
27994 GIM_Try, /*On fail goto*//*Label 1662*/ GIMT_Encode4(78518), // Rule ID 273 //
27995 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
27996 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
27997 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
27998 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
27999 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28000 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
28001 // (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRSui:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
28002 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
28003 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28004 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28005 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28006 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28007 GIR_RootConstrainSelectedInstOperands,
28008 // GIR_Coverage, 273,
28009 GIR_EraseRootFromParent_Done,
28010 // Label 1662: @78518
28011 GIM_Try, /*On fail goto*//*Label 1663*/ GIMT_Encode4(78577), // Rule ID 6750 //
28012 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
28013 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28014 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28015 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28016 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28017 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
28018 // (atomic_load:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_anonymous_14575>> => (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset)
28019 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
28020 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28021 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28022 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28023 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
28024 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28025 GIR_RootConstrainSelectedInstOperands,
28026 // GIR_Coverage, 6750,
28027 GIR_EraseRootFromParent_Done,
28028 // Label 1663: @78577
28029 GIM_Try, /*On fail goto*//*Label 1664*/ GIMT_Encode4(78636), // Rule ID 6752 //
28030 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
28031 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28032 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28033 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28034 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28035 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
28036 // (atomic_load:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_anonymous_14575>> => (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset)
28037 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
28038 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28039 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28040 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28041 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
28042 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28043 GIR_RootConstrainSelectedInstOperands,
28044 // GIR_Coverage, 6752,
28045 GIR_EraseRootFromParent_Done,
28046 // Label 1664: @78636
28047 GIM_Try, /*On fail goto*//*Label 1665*/ GIMT_Encode4(78695), // Rule ID 6762 //
28048 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
28049 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28050 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28051 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28052 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28053 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
28054 // (atomic_load:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_16>><<P:Predicate_anonymous_14584>> => (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
28055 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroW),
28056 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28057 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28058 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28059 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28060 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28061 GIR_RootConstrainSelectedInstOperands,
28062 // GIR_Coverage, 6762,
28063 GIR_EraseRootFromParent_Done,
28064 // Label 1665: @78695
28065 GIM_Try, /*On fail goto*//*Label 1666*/ GIMT_Encode4(78754), // Rule ID 6764 //
28066 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
28067 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28068 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28069 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28070 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28071 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
28072 // (atomic_load:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_16>><<P:Predicate_anonymous_14584>> => (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
28073 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroX),
28074 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28075 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28076 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28077 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28078 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28079 GIR_RootConstrainSelectedInstOperands,
28080 // GIR_Coverage, 6764,
28081 GIR_EraseRootFromParent_Done,
28082 // Label 1666: @78754
28083 GIM_Try, /*On fail goto*//*Label 1667*/ GIMT_Encode4(78813), // Rule ID 6772 //
28084 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
28085 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28086 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28087 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28088 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28089 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
28090 // (atomic_load:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_32>><<P:Predicate_anonymous_14592>> => (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
28091 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWroW),
28092 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28093 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28094 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28095 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28096 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28097 GIR_RootConstrainSelectedInstOperands,
28098 // GIR_Coverage, 6772,
28099 GIR_EraseRootFromParent_Done,
28100 // Label 1667: @78813
28101 GIM_Try, /*On fail goto*//*Label 1668*/ GIMT_Encode4(78872), // Rule ID 6773 //
28102 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
28103 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28104 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28105 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28106 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28107 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
28108 // (atomic_load:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_32>><<P:Predicate_anonymous_14592>> => (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
28109 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWroX),
28110 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28111 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28112 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28113 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28114 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28115 GIR_RootConstrainSelectedInstOperands,
28116 // GIR_Coverage, 6773,
28117 GIR_EraseRootFromParent_Done,
28118 // Label 1668: @78872
28119 GIM_Try, /*On fail goto*//*Label 1669*/ GIMT_Encode4(78920), // Rule ID 291 //
28120 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28121 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28122 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28123 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28124 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
28125 // (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
28126 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURWi),
28127 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28128 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28129 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28130 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28131 GIR_RootConstrainSelectedInstOperands,
28132 // GIR_Coverage, 291,
28133 GIR_EraseRootFromParent_Done,
28134 // Label 1669: @78920
28135 GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(78971), // Rule ID 294 //
28136 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
28137 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28138 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28139 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
28140 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28141 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
28142 // (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURSi:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
28143 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
28144 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28145 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28146 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28147 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28148 GIR_RootConstrainSelectedInstOperands,
28149 // GIR_Coverage, 294,
28150 GIR_EraseRootFromParent_Done,
28151 // Label 1670: @78971
28152 GIM_Try, /*On fail goto*//*Label 1671*/ GIMT_Encode4(79025), // Rule ID 6754 //
28153 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
28154 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28155 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28156 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28157 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28158 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
28159 // (atomic_load:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_anonymous_14575>> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
28160 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
28161 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28162 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28163 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28164 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28165 GIR_RootConstrainSelectedInstOperands,
28166 // GIR_Coverage, 6754,
28167 GIR_EraseRootFromParent_Done,
28168 // Label 1671: @79025
28169 GIM_Try, /*On fail goto*//*Label 1672*/ GIMT_Encode4(79079), // Rule ID 6756 //
28170 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
28171 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28172 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28173 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28174 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28175 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
28176 // (atomic_load:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_anonymous_14575>> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
28177 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
28178 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28179 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28180 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28181 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28182 GIR_RootConstrainSelectedInstOperands,
28183 // GIR_Coverage, 6756,
28184 GIR_EraseRootFromParent_Done,
28185 // Label 1672: @79079
28186 GIM_Try, /*On fail goto*//*Label 1673*/ GIMT_Encode4(79133), // Rule ID 6766 //
28187 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
28188 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28189 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28190 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28191 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28192 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
28193 // (atomic_load:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_anonymous_14584>> => (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
28194 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHui),
28195 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28196 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28197 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28198 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28199 GIR_RootConstrainSelectedInstOperands,
28200 // GIR_Coverage, 6766,
28201 GIR_EraseRootFromParent_Done,
28202 // Label 1673: @79133
28203 GIM_Try, /*On fail goto*//*Label 1674*/ GIMT_Encode4(79187), // Rule ID 6768 //
28204 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
28205 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28206 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28207 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28208 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28209 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
28210 // (atomic_load:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_anonymous_14584>> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
28211 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
28212 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28213 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28214 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28215 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28216 GIR_RootConstrainSelectedInstOperands,
28217 // GIR_Coverage, 6768,
28218 GIR_EraseRootFromParent_Done,
28219 // Label 1674: @79187
28220 GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(79241), // Rule ID 6774 //
28221 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
28222 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28223 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28224 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28225 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28226 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
28227 // (atomic_load:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_32>><<P:Predicate_anonymous_14592>> => (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
28228 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWui),
28229 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28230 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28231 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28232 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28233 GIR_RootConstrainSelectedInstOperands,
28234 // GIR_Coverage, 6774,
28235 GIR_EraseRootFromParent_Done,
28236 // Label 1675: @79241
28237 GIM_Try, /*On fail goto*//*Label 1676*/ GIMT_Encode4(79295), // Rule ID 6775 //
28238 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
28239 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28240 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28241 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28242 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28243 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
28244 // (atomic_load:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_32>><<P:Predicate_anonymous_14592>> => (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
28245 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURWi),
28246 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28247 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28248 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28249 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28250 GIR_RootConstrainSelectedInstOperands,
28251 // GIR_Coverage, 6775,
28252 GIR_EraseRootFromParent_Done,
28253 // Label 1676: @79295
28254 GIM_Try, /*On fail goto*//*Label 1677*/ GIMT_Encode4(79352), // Rule ID 7090 //
28255 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO),
28256 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
28257 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28258 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28259 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28260 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28261 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
28262 // (atomic_load:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_anonymous_14573>> => (LDAPURBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
28263 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAPURBi),
28264 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28265 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28266 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28267 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28268 GIR_RootConstrainSelectedInstOperands,
28269 // GIR_Coverage, 7090,
28270 GIR_EraseRootFromParent_Done,
28271 // Label 1677: @79352
28272 GIM_Try, /*On fail goto*//*Label 1678*/ GIMT_Encode4(79409), // Rule ID 7092 //
28273 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO),
28274 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
28275 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28276 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28277 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28278 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28279 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
28280 // (atomic_load:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_anonymous_14582>> => (LDAPURHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
28281 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAPURHi),
28282 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28283 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28284 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28285 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28286 GIR_RootConstrainSelectedInstOperands,
28287 // GIR_Coverage, 7092,
28288 GIR_EraseRootFromParent_Done,
28289 // Label 1678: @79409
28290 GIM_Try, /*On fail goto*//*Label 1679*/ GIMT_Encode4(79466), // Rule ID 7094 //
28291 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO),
28292 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
28293 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28294 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28295 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28296 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28297 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
28298 // (atomic_load:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_32>><<P:Predicate_anonymous_14567>> => (LDAPURi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
28299 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAPURi),
28300 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28301 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28302 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28303 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28304 GIR_RootConstrainSelectedInstOperands,
28305 // GIR_Coverage, 7094,
28306 GIR_EraseRootFromParent_Done,
28307 // Label 1679: @79466
28308 GIM_Try, /*On fail goto*//*Label 1680*/ GIMT_Encode4(79521), // Rule ID 4054 //
28309 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28310 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
28311 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28312 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28313 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28314 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
28315 // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
28316 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHui),
28317 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28318 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28319 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28320 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28321 GIR_RootConstrainSelectedInstOperands,
28322 // GIR_Coverage, 4054,
28323 GIR_EraseRootFromParent_Done,
28324 // Label 1680: @79521
28325 GIM_Try, /*On fail goto*//*Label 1681*/ GIMT_Encode4(79576), // Rule ID 4055 //
28326 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28327 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
28328 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28329 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28330 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28331 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
28332 // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
28333 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
28334 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28335 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28336 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28337 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28338 GIR_RootConstrainSelectedInstOperands,
28339 // GIR_Coverage, 4055,
28340 GIR_EraseRootFromParent_Done,
28341 // Label 1681: @79576
28342 GIM_Try, /*On fail goto*//*Label 1682*/ GIMT_Encode4(79631), // Rule ID 4056 //
28343 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28344 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
28345 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28346 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28347 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28348 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
28349 // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
28350 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
28351 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28352 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28353 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28354 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28355 GIR_RootConstrainSelectedInstOperands,
28356 // GIR_Coverage, 4056,
28357 GIR_EraseRootFromParent_Done,
28358 // Label 1682: @79631
28359 GIM_Try, /*On fail goto*//*Label 1683*/ GIMT_Encode4(79686), // Rule ID 4078 //
28360 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28361 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
28362 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28363 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28364 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28365 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
28366 // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
28367 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
28368 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28369 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28370 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28371 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28372 GIR_RootConstrainSelectedInstOperands,
28373 // GIR_Coverage, 4078,
28374 GIR_EraseRootFromParent_Done,
28375 // Label 1683: @79686
28376 GIM_Try, /*On fail goto*//*Label 1684*/ GIMT_Encode4(79741), // Rule ID 4079 //
28377 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28378 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
28379 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28380 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28381 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28382 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
28383 // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
28384 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
28385 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28386 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28387 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28388 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28389 GIR_RootConstrainSelectedInstOperands,
28390 // GIR_Coverage, 4079,
28391 GIR_EraseRootFromParent_Done,
28392 // Label 1684: @79741
28393 GIM_Try, /*On fail goto*//*Label 1685*/ GIMT_Encode4(79796), // Rule ID 4080 //
28394 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28395 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
28396 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28397 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28398 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28399 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
28400 // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
28401 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
28402 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28403 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28404 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28405 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28406 GIR_RootConstrainSelectedInstOperands,
28407 // GIR_Coverage, 4080,
28408 GIR_EraseRootFromParent_Done,
28409 // Label 1685: @79796
28410 GIM_Try, /*On fail goto*//*Label 1686*/ GIMT_Encode4(79836), // Rule ID 6742 //
28411 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC),
28412 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
28413 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28414 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28415 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28416 // MIs[0] ptr
28417 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
28418 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
28419 // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_8>><<P:Predicate_anonymous_14563>> => (LDAPRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
28420 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDAPRB),
28421 GIR_RootConstrainSelectedInstOperands,
28422 // GIR_Coverage, 6742,
28423 GIR_Done,
28424 // Label 1686: @79836
28425 GIM_Try, /*On fail goto*//*Label 1687*/ GIMT_Encode4(79876), // Rule ID 6743 //
28426 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC),
28427 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
28428 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28429 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28430 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28431 // MIs[0] ptr
28432 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
28433 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
28434 // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_16>><<P:Predicate_anonymous_14565>> => (LDAPRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
28435 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDAPRH),
28436 GIR_RootConstrainSelectedInstOperands,
28437 // GIR_Coverage, 6743,
28438 GIR_Done,
28439 // Label 1687: @79876
28440 GIM_Try, /*On fail goto*//*Label 1688*/ GIMT_Encode4(79916), // Rule ID 6744 //
28441 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC),
28442 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
28443 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28444 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28445 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28446 // MIs[0] ptr
28447 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
28448 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
28449 // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_32>><<P:Predicate_anonymous_14567>> => (LDAPRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
28450 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDAPRW),
28451 GIR_RootConstrainSelectedInstOperands,
28452 // GIR_Coverage, 6744,
28453 GIR_Done,
28454 // Label 1688: @79916
28455 GIM_Try, /*On fail goto*//*Label 1689*/ GIMT_Encode4(79953), // Rule ID 6746 //
28456 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
28457 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
28458 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28459 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28460 // MIs[0] ptr
28461 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
28462 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
28463 // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_8>><<P:Predicate_anonymous_14571>> => (LDARB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
28464 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARB),
28465 GIR_RootConstrainSelectedInstOperands,
28466 // GIR_Coverage, 6746,
28467 GIR_Done,
28468 // Label 1689: @79953
28469 GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(79990), // Rule ID 6748 //
28470 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
28471 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28472 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28473 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28474 // MIs[0] ptr
28475 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
28476 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
28477 // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_8>><<P:Predicate_anonymous_14573>> => (LDARB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
28478 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARB),
28479 GIR_RootConstrainSelectedInstOperands,
28480 // GIR_Coverage, 6748,
28481 GIR_Done,
28482 // Label 1690: @79990
28483 GIM_Try, /*On fail goto*//*Label 1691*/ GIMT_Encode4(80027), // Rule ID 6758 //
28484 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
28485 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
28486 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28487 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28488 // MIs[0] ptr
28489 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
28490 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
28491 // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_16>><<P:Predicate_anonymous_14580>> => (LDARH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
28492 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARH),
28493 GIR_RootConstrainSelectedInstOperands,
28494 // GIR_Coverage, 6758,
28495 GIR_Done,
28496 // Label 1691: @80027
28497 GIM_Try, /*On fail goto*//*Label 1692*/ GIMT_Encode4(80064), // Rule ID 6760 //
28498 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
28499 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28500 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28502 // MIs[0] ptr
28503 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
28504 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
28505 // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_16>><<P:Predicate_anonymous_14582>> => (LDARH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
28506 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARH),
28507 GIR_RootConstrainSelectedInstOperands,
28508 // GIR_Coverage, 6760,
28509 GIR_Done,
28510 // Label 1692: @80064
28511 GIM_Try, /*On fail goto*//*Label 1693*/ GIMT_Encode4(80101), // Rule ID 6770 //
28512 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
28513 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
28514 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28515 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28516 // MIs[0] ptr
28517 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
28518 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
28519 // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_32>><<P:Predicate_anonymous_14589>> => (LDARW:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
28520 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARW),
28521 GIR_RootConstrainSelectedInstOperands,
28522 // GIR_Coverage, 6770,
28523 GIR_Done,
28524 // Label 1693: @80101
28525 GIM_Try, /*On fail goto*//*Label 1694*/ GIMT_Encode4(80138), // Rule ID 6771 //
28526 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
28527 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28528 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28529 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
28530 // MIs[0] ptr
28531 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
28532 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
28533 // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_32>><<P:Predicate_anonymous_14567>> => (LDARW:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
28534 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARW),
28535 GIR_RootConstrainSelectedInstOperands,
28536 // GIR_Coverage, 6771,
28537 GIR_Done,
28538 // Label 1694: @80138
28539 GIM_Reject,
28540 // Label 1621: @80139
28541 GIM_Try, /*On fail goto*//*Label 1695*/ GIMT_Encode4(80192), // Rule ID 245 //
28542 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28543 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28544 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
28545 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28546 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
28547 // (ld:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
28548 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRXroW),
28549 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28550 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28551 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28552 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28553 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28554 GIR_RootConstrainSelectedInstOperands,
28555 // GIR_Coverage, 245,
28556 GIR_EraseRootFromParent_Done,
28557 // Label 1695: @80192
28558 GIM_Try, /*On fail goto*//*Label 1696*/ GIMT_Encode4(80245), // Rule ID 246 //
28559 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28560 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28561 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
28562 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28563 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
28564 // (ld:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
28565 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRXroX),
28566 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28567 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28568 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28569 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28570 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28571 GIR_RootConstrainSelectedInstOperands,
28572 // GIR_Coverage, 246,
28573 GIR_EraseRootFromParent_Done,
28574 // Label 1696: @80245
28575 GIM_Try, /*On fail goto*//*Label 1697*/ GIMT_Encode4(80301), // Rule ID 253 //
28576 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
28577 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28578 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28579 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
28580 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28581 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
28582 // (ld:{ *:[f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroW:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
28583 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
28584 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28585 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28586 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28587 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28588 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28589 GIR_RootConstrainSelectedInstOperands,
28590 // GIR_Coverage, 253,
28591 GIR_EraseRootFromParent_Done,
28592 // Label 1697: @80301
28593 GIM_Try, /*On fail goto*//*Label 1698*/ GIMT_Encode4(80357), // Rule ID 254 //
28594 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
28595 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28596 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28597 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
28598 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28599 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
28600 // (ld:{ *:[f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroX:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
28601 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
28602 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28603 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28604 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28605 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28606 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28607 GIR_RootConstrainSelectedInstOperands,
28608 // GIR_Coverage, 254,
28609 GIR_EraseRootFromParent_Done,
28610 // Label 1698: @80357
28611 GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(80410), // Rule ID 3980 //
28612 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28613 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28614 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
28615 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28616 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
28617 // (ld:{ *:[v1i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroW:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
28618 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
28619 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28620 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28621 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28622 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28623 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28624 GIR_RootConstrainSelectedInstOperands,
28625 // GIR_Coverage, 3980,
28626 GIR_EraseRootFromParent_Done,
28627 // Label 1699: @80410
28628 GIM_Try, /*On fail goto*//*Label 1700*/ GIMT_Encode4(80463), // Rule ID 3981 //
28629 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28630 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28631 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
28632 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28633 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
28634 // (ld:{ *:[v1i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroX:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
28635 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
28636 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28637 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28638 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28639 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28640 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28641 GIR_RootConstrainSelectedInstOperands,
28642 // GIR_Coverage, 3981,
28643 GIR_EraseRootFromParent_Done,
28644 // Label 1700: @80463
28645 GIM_Try, /*On fail goto*//*Label 1701*/ GIMT_Encode4(80516), // Rule ID 3982 //
28646 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28647 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28648 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
28649 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28650 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
28651 // (ld:{ *:[v1f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroW:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
28652 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
28653 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28654 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28655 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28656 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28657 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28658 GIR_RootConstrainSelectedInstOperands,
28659 // GIR_Coverage, 3982,
28660 GIR_EraseRootFromParent_Done,
28661 // Label 1701: @80516
28662 GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(80569), // Rule ID 3983 //
28663 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28664 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28665 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
28666 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28667 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
28668 // (ld:{ *:[v1f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroX:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
28669 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
28670 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28671 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28672 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28673 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28674 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28675 GIR_RootConstrainSelectedInstOperands,
28676 // GIR_Coverage, 3983,
28677 GIR_EraseRootFromParent_Done,
28678 // Label 1702: @80569
28679 GIM_Try, /*On fail goto*//*Label 1703*/ GIMT_Encode4(80661), // Rule ID 4008 //
28680 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28681 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
28682 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28683 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
28684 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28685 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
28686 // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
28687 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
28688 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
28689 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28690 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28691 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28692 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28693 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
28694 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
28695 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
28696 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
28697 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28698 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28699 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
28700 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
28701 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
28702 // GIR_Coverage, 4008,
28703 GIR_EraseRootFromParent_Done,
28704 // Label 1703: @80661
28705 GIM_Try, /*On fail goto*//*Label 1704*/ GIMT_Encode4(80753), // Rule ID 4009 //
28706 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28707 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
28708 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28709 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
28710 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28711 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
28712 // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
28713 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
28714 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
28715 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28716 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28717 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28718 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28719 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
28720 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
28721 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
28722 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
28723 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28724 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28725 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
28726 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
28727 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
28728 // GIR_Coverage, 4009,
28729 GIR_EraseRootFromParent_Done,
28730 // Label 1704: @80753
28731 GIM_Try, /*On fail goto*//*Label 1705*/ GIMT_Encode4(80845), // Rule ID 4010 //
28732 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28733 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
28734 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28735 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
28736 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28737 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
28738 // (ld:{ *:[i64] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
28739 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
28740 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroW),
28741 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28742 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28743 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28744 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28745 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
28746 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
28747 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
28748 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
28749 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28750 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28751 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
28752 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
28753 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
28754 // GIR_Coverage, 4010,
28755 GIR_EraseRootFromParent_Done,
28756 // Label 1705: @80845
28757 GIM_Try, /*On fail goto*//*Label 1706*/ GIMT_Encode4(80937), // Rule ID 4011 //
28758 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28759 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
28760 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28761 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
28762 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28763 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
28764 // (ld:{ *:[i64] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
28765 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
28766 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroX),
28767 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28768 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28769 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28770 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28771 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
28772 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
28773 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
28774 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
28775 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28776 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28777 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
28778 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
28779 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
28780 // GIR_Coverage, 4011,
28781 GIR_EraseRootFromParent_Done,
28782 // Label 1706: @80937
28783 GIM_Try, /*On fail goto*//*Label 1707*/ GIMT_Encode4(81029), // Rule ID 4012 //
28784 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28785 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
28786 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28787 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
28788 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28789 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
28790 // (ld:{ *:[i64] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
28791 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
28792 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRWroW),
28793 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28794 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28795 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28796 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28797 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
28798 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
28799 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
28800 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
28801 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28802 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28803 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
28804 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
28805 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
28806 // GIR_Coverage, 4012,
28807 GIR_EraseRootFromParent_Done,
28808 // Label 1707: @81029
28809 GIM_Try, /*On fail goto*//*Label 1708*/ GIMT_Encode4(81121), // Rule ID 4013 //
28810 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28811 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
28812 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28813 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
28814 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28815 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
28816 // (ld:{ *:[i64] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
28817 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
28818 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRWroX),
28819 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28820 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28821 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28822 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28823 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
28824 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
28825 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
28826 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
28827 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28828 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28829 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
28830 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
28831 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
28832 // GIR_Coverage, 4013,
28833 GIR_EraseRootFromParent_Done,
28834 // Label 1708: @81121
28835 GIM_Try, /*On fail goto*//*Label 1709*/ GIMT_Encode4(81213), // Rule ID 4014 //
28836 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28837 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
28838 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28839 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
28840 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28841 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
28842 // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
28843 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
28844 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
28845 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28846 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28847 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28848 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28849 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
28850 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
28851 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
28852 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
28853 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28854 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28855 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
28856 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
28857 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
28858 // GIR_Coverage, 4014,
28859 GIR_EraseRootFromParent_Done,
28860 // Label 1709: @81213
28861 GIM_Try, /*On fail goto*//*Label 1710*/ GIMT_Encode4(81305), // Rule ID 4015 //
28862 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28863 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
28864 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28865 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
28866 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28867 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
28868 // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
28869 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
28870 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
28871 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
28872 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28873 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28874 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28875 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
28876 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
28877 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
28878 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
28879 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28880 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28881 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
28882 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
28883 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
28884 // GIR_Coverage, 4015,
28885 GIR_EraseRootFromParent_Done,
28886 // Label 1710: @81305
28887 GIM_Try, /*On fail goto*//*Label 1711*/ GIMT_Encode4(81353), // Rule ID 269 //
28888 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28889 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28890 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
28891 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28892 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
28893 // (ld:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
28894 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRXui),
28895 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28896 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28897 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28898 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28899 GIR_RootConstrainSelectedInstOperands,
28900 // GIR_Coverage, 269,
28901 GIR_EraseRootFromParent_Done,
28902 // Label 1711: @81353
28903 GIM_Try, /*On fail goto*//*Label 1712*/ GIMT_Encode4(81404), // Rule ID 274 //
28904 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
28905 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28906 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28907 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
28908 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28909 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
28910 // (ld:{ *:[f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
28911 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
28912 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28913 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28914 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28915 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28916 GIR_RootConstrainSelectedInstOperands,
28917 // GIR_Coverage, 274,
28918 GIR_EraseRootFromParent_Done,
28919 // Label 1712: @81404
28920 GIM_Try, /*On fail goto*//*Label 1713*/ GIMT_Encode4(81463), // Rule ID 6778 //
28921 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
28922 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28923 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28924 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
28925 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28926 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
28927 // (atomic_load:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_64>><<P:Predicate_anonymous_14600>> => (LDRXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
28928 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRXroW),
28929 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28930 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28931 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28932 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28933 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28934 GIR_RootConstrainSelectedInstOperands,
28935 // GIR_Coverage, 6778,
28936 GIR_EraseRootFromParent_Done,
28937 // Label 1713: @81463
28938 GIM_Try, /*On fail goto*//*Label 1714*/ GIMT_Encode4(81522), // Rule ID 6779 //
28939 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
28940 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28941 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28942 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
28943 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28944 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
28945 // (atomic_load:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_64>><<P:Predicate_anonymous_14600>> => (LDRXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
28946 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRXroX),
28947 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28948 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28949 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
28950 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
28951 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28952 GIR_RootConstrainSelectedInstOperands,
28953 // GIR_Coverage, 6779,
28954 GIR_EraseRootFromParent_Done,
28955 // Label 1714: @81522
28956 GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(81570), // Rule ID 290 //
28957 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28958 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28959 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
28960 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28961 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
28962 // (ld:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
28963 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURXi),
28964 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28965 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28966 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28967 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28968 GIR_RootConstrainSelectedInstOperands,
28969 // GIR_Coverage, 290,
28970 GIR_EraseRootFromParent_Done,
28971 // Label 1715: @81570
28972 GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(81621), // Rule ID 295 //
28973 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
28974 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
28975 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
28976 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
28977 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28978 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
28979 // (ld:{ *:[f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
28980 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
28981 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28982 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
28983 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
28984 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
28985 GIR_RootConstrainSelectedInstOperands,
28986 // GIR_Coverage, 295,
28987 GIR_EraseRootFromParent_Done,
28988 // Label 1716: @81621
28989 GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(81675), // Rule ID 6780 //
28990 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
28991 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
28992 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
28993 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
28994 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
28995 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
28996 // (atomic_load:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_64>><<P:Predicate_anonymous_14600>> => (LDRXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
28997 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRXui),
28998 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
28999 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29000 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29001 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29002 GIR_RootConstrainSelectedInstOperands,
29003 // GIR_Coverage, 6780,
29004 GIR_EraseRootFromParent_Done,
29005 // Label 1717: @81675
29006 GIM_Try, /*On fail goto*//*Label 1718*/ GIMT_Encode4(81729), // Rule ID 6781 //
29007 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
29008 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
29009 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
29010 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
29011 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29012 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
29013 // (atomic_load:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_64>><<P:Predicate_anonymous_14600>> => (LDURXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
29014 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURXi),
29015 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29016 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29017 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29018 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29019 GIR_RootConstrainSelectedInstOperands,
29020 // GIR_Coverage, 6781,
29021 GIR_EraseRootFromParent_Done,
29022 // Label 1718: @81729
29023 GIM_Try, /*On fail goto*//*Label 1719*/ GIMT_Encode4(81786), // Rule ID 7095 //
29024 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO),
29025 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
29026 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
29027 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
29028 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
29029 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29030 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
29031 // (atomic_load:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_64>><<P:Predicate_anonymous_14569>> => (LDAPURXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
29032 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAPURXi),
29033 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29034 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29035 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29036 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29037 GIR_RootConstrainSelectedInstOperands,
29038 // GIR_Coverage, 7095,
29039 GIR_EraseRootFromParent_Done,
29040 // Label 1719: @81786
29041 GIM_Try, /*On fail goto*//*Label 1720*/ GIMT_Encode4(81834), // Rule ID 4039 //
29042 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
29043 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
29044 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
29045 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29046 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
29047 // (ld:{ *:[v1f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
29048 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
29049 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29050 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29051 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29052 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29053 GIR_RootConstrainSelectedInstOperands,
29054 // GIR_Coverage, 4039,
29055 GIR_EraseRootFromParent_Done,
29056 // Label 1720: @81834
29057 GIM_Try, /*On fail goto*//*Label 1721*/ GIMT_Encode4(81882), // Rule ID 4040 //
29058 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
29059 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
29060 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
29061 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29062 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
29063 // (ld:{ *:[v1i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
29064 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
29065 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29066 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29067 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29068 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29069 GIR_RootConstrainSelectedInstOperands,
29070 // GIR_Coverage, 4040,
29071 GIR_EraseRootFromParent_Done,
29072 // Label 1721: @81882
29073 GIM_Try, /*On fail goto*//*Label 1722*/ GIMT_Encode4(81930), // Rule ID 4069 //
29074 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
29075 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
29076 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
29077 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29078 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
29079 // (ld:{ *:[v1f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
29080 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
29081 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29082 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29083 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29084 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29085 GIR_RootConstrainSelectedInstOperands,
29086 // GIR_Coverage, 4069,
29087 GIR_EraseRootFromParent_Done,
29088 // Label 1722: @81930
29089 GIM_Try, /*On fail goto*//*Label 1723*/ GIMT_Encode4(81978), // Rule ID 4070 //
29090 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
29091 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
29092 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
29093 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29094 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
29095 // (ld:{ *:[v1i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
29096 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
29097 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29098 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29099 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29100 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29101 GIR_RootConstrainSelectedInstOperands,
29102 // GIR_Coverage, 4070,
29103 GIR_EraseRootFromParent_Done,
29104 // Label 1723: @81978
29105 GIM_Try, /*On fail goto*//*Label 1724*/ GIMT_Encode4(82065), // Rule ID 4057 //
29106 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
29107 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
29108 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
29109 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
29110 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29111 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
29112 // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
29113 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
29114 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRWui),
29115 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29116 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29117 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29118 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
29119 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
29120 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
29121 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
29122 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29123 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29124 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
29125 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
29126 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
29127 // GIR_Coverage, 4057,
29128 GIR_EraseRootFromParent_Done,
29129 // Label 1724: @82065
29130 GIM_Try, /*On fail goto*//*Label 1725*/ GIMT_Encode4(82152), // Rule ID 4058 //
29131 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
29132 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
29133 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
29134 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
29135 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29136 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
29137 // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
29138 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
29139 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHHui),
29140 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29141 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29142 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29143 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
29144 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
29145 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
29146 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
29147 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29148 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29149 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
29150 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
29151 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
29152 // GIR_Coverage, 4058,
29153 GIR_EraseRootFromParent_Done,
29154 // Label 1725: @82152
29155 GIM_Try, /*On fail goto*//*Label 1726*/ GIMT_Encode4(82239), // Rule ID 4059 //
29156 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
29157 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
29158 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
29159 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
29160 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29161 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
29162 // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
29163 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
29164 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
29165 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29166 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29167 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29168 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
29169 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
29170 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
29171 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
29172 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29173 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29174 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
29175 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
29176 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
29177 // GIR_Coverage, 4059,
29178 GIR_EraseRootFromParent_Done,
29179 // Label 1726: @82239
29180 GIM_Try, /*On fail goto*//*Label 1727*/ GIMT_Encode4(82326), // Rule ID 4060 //
29181 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
29182 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
29183 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
29184 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
29185 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29186 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
29187 // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
29188 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
29189 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
29190 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29191 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29192 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29193 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
29194 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
29195 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
29196 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
29197 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29198 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29199 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
29200 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
29201 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
29202 // GIR_Coverage, 4060,
29203 GIR_EraseRootFromParent_Done,
29204 // Label 1727: @82326
29205 GIM_Try, /*On fail goto*//*Label 1728*/ GIMT_Encode4(82413), // Rule ID 4081 //
29206 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
29207 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
29208 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
29209 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
29210 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29211 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
29212 // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
29213 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
29214 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURWi),
29215 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29216 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29217 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29218 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
29219 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
29220 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
29221 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
29222 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29223 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29224 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
29225 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
29226 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
29227 // GIR_Coverage, 4081,
29228 GIR_EraseRootFromParent_Done,
29229 // Label 1728: @82413
29230 GIM_Try, /*On fail goto*//*Label 1729*/ GIMT_Encode4(82500), // Rule ID 4082 //
29231 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
29232 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
29233 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
29234 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
29235 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29236 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
29237 // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
29238 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
29239 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
29240 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29241 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29242 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29243 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
29244 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
29245 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
29246 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
29247 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29248 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29249 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
29250 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
29251 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
29252 // GIR_Coverage, 4082,
29253 GIR_EraseRootFromParent_Done,
29254 // Label 1729: @82500
29255 GIM_Try, /*On fail goto*//*Label 1730*/ GIMT_Encode4(82587), // Rule ID 4083 //
29256 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
29257 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
29258 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
29259 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
29260 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29261 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
29262 // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
29263 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
29264 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
29265 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29266 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29267 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29268 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
29269 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
29270 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
29271 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
29272 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29273 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29274 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
29275 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
29276 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
29277 // GIR_Coverage, 4083,
29278 GIR_EraseRootFromParent_Done,
29279 // Label 1730: @82587
29280 GIM_Try, /*On fail goto*//*Label 1731*/ GIMT_Encode4(82674), // Rule ID 4084 //
29281 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
29282 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
29283 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
29284 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
29285 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29286 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
29287 // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
29288 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
29289 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
29290 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
29291 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29292 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29293 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
29294 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
29295 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
29296 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
29297 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29298 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29299 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
29300 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
29301 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
29302 // GIR_Coverage, 4084,
29303 GIR_EraseRootFromParent_Done,
29304 // Label 1731: @82674
29305 GIM_Try, /*On fail goto*//*Label 1732*/ GIMT_Encode4(82714), // Rule ID 6745 //
29306 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC),
29307 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
29308 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
29309 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
29310 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
29311 // MIs[0] ptr
29312 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
29313 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
29314 // (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_64>><<P:Predicate_anonymous_14569>> => (LDAPRX:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)
29315 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDAPRX),
29316 GIR_RootConstrainSelectedInstOperands,
29317 // GIR_Coverage, 6745,
29318 GIR_Done,
29319 // Label 1732: @82714
29320 GIM_Try, /*On fail goto*//*Label 1733*/ GIMT_Encode4(82751), // Rule ID 6776 //
29321 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
29322 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
29323 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
29324 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
29325 // MIs[0] ptr
29326 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
29327 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
29328 // (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_64>><<P:Predicate_anonymous_14597>> => (LDARX:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)
29329 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARX),
29330 GIR_RootConstrainSelectedInstOperands,
29331 // GIR_Coverage, 6776,
29332 GIR_Done,
29333 // Label 1733: @82751
29334 GIM_Try, /*On fail goto*//*Label 1734*/ GIMT_Encode4(82788), // Rule ID 6777 //
29335 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
29336 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
29337 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
29338 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
29339 // MIs[0] ptr
29340 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
29341 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
29342 // (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_64>><<P:Predicate_anonymous_14569>> => (LDARX:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)
29343 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARX),
29344 GIR_RootConstrainSelectedInstOperands,
29345 // GIR_Coverage, 6777,
29346 GIR_Done,
29347 // Label 1734: @82788
29348 GIM_Try, /*On fail goto*//*Label 1735*/ GIMT_Encode4(82819), // Rule ID 5997 //
29349 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
29350 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
29351 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
29352 // MIs[0] Rn
29353 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
29354 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
29355 // (ld:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev1d:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn)
29356 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev1d),
29357 GIR_RootConstrainSelectedInstOperands,
29358 // GIR_Coverage, 5997,
29359 GIR_Done,
29360 // Label 1735: @82819
29361 GIM_Reject,
29362 // Label 1622: @82820
29363 GIM_Try, /*On fail goto*//*Label 1736*/ GIMT_Encode4(83028),
29364 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
29365 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
29366 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
29367 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29368 GIM_Try, /*On fail goto*//*Label 1737*/ GIMT_Encode4(82881), // Rule ID 255 //
29369 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
29370 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
29371 // (ld:{ *:[f128] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroW:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
29372 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
29373 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29374 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29375 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29376 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29377 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29378 GIR_RootConstrainSelectedInstOperands,
29379 // GIR_Coverage, 255,
29380 GIR_EraseRootFromParent_Done,
29381 // Label 1737: @82881
29382 GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(82922), // Rule ID 256 //
29383 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
29384 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
29385 // (ld:{ *:[f128] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroX:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
29386 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
29387 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29388 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29389 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29390 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29391 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29392 GIR_RootConstrainSelectedInstOperands,
29393 // GIR_Coverage, 256,
29394 GIR_EraseRootFromParent_Done,
29395 // Label 1738: @82922
29396 GIM_Try, /*On fail goto*//*Label 1739*/ GIMT_Encode4(82958), // Rule ID 275 //
29397 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
29398 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
29399 // (ld:{ *:[f128] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
29400 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
29401 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29402 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29403 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29404 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29405 GIR_RootConstrainSelectedInstOperands,
29406 // GIR_Coverage, 275,
29407 GIR_EraseRootFromParent_Done,
29408 // Label 1739: @82958
29409 GIM_Try, /*On fail goto*//*Label 1740*/ GIMT_Encode4(82994), // Rule ID 296 //
29410 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
29411 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
29412 // (ld:{ *:[f128] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
29413 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
29414 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29415 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29416 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29417 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29418 GIR_RootConstrainSelectedInstOperands,
29419 // GIR_Coverage, 296,
29420 GIR_EraseRootFromParent_Done,
29421 // Label 1740: @82994
29422 GIM_Try, /*On fail goto*//*Label 1741*/ GIMT_Encode4(83027), // Rule ID 4049 //
29423 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
29424 // (ld:{ *:[f128] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
29425 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
29426 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29427 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29428 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29429 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29430 GIR_RootConstrainSelectedInstOperands,
29431 // GIR_Coverage, 4049,
29432 GIR_EraseRootFromParent_Done,
29433 // Label 1741: @83027
29434 GIM_Reject,
29435 // Label 1736: @83028
29436 GIM_Reject,
29437 // Label 1623: @83029
29438 GIM_Try, /*On fail goto*//*Label 1742*/ GIMT_Encode4(83406),
29439 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
29440 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
29441 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
29442 GIM_Try, /*On fail goto*//*Label 1743*/ GIMT_Encode4(83090), // Rule ID 3968 //
29443 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29444 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29445 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
29446 // (ld:{ *:[v2i32] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroW:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
29447 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
29448 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29449 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29450 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29451 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29452 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29453 GIR_RootConstrainSelectedInstOperands,
29454 // GIR_Coverage, 3968,
29455 GIR_EraseRootFromParent_Done,
29456 // Label 1743: @83090
29457 GIM_Try, /*On fail goto*//*Label 1744*/ GIMT_Encode4(83135), // Rule ID 3969 //
29458 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29459 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29460 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
29461 // (ld:{ *:[v2i32] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroX:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
29462 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
29463 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29464 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29465 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29466 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29467 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29468 GIR_RootConstrainSelectedInstOperands,
29469 // GIR_Coverage, 3969,
29470 GIR_EraseRootFromParent_Done,
29471 // Label 1744: @83135
29472 GIM_Try, /*On fail goto*//*Label 1745*/ GIMT_Encode4(83180), // Rule ID 3970 //
29473 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29474 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29475 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
29476 // (ld:{ *:[v2f32] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroW:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
29477 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
29478 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29479 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29480 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29481 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29482 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29483 GIR_RootConstrainSelectedInstOperands,
29484 // GIR_Coverage, 3970,
29485 GIR_EraseRootFromParent_Done,
29486 // Label 1745: @83180
29487 GIM_Try, /*On fail goto*//*Label 1746*/ GIMT_Encode4(83225), // Rule ID 3971 //
29488 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29489 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29490 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
29491 // (ld:{ *:[v2f32] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroX:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
29492 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
29493 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29494 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29495 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29496 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29497 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29498 GIR_RootConstrainSelectedInstOperands,
29499 // GIR_Coverage, 3971,
29500 GIR_EraseRootFromParent_Done,
29501 // Label 1746: @83225
29502 GIM_Try, /*On fail goto*//*Label 1747*/ GIMT_Encode4(83265), // Rule ID 4033 //
29503 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29504 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29505 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
29506 // (ld:{ *:[v2f32] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
29507 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
29508 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29509 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29510 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29511 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29512 GIR_RootConstrainSelectedInstOperands,
29513 // GIR_Coverage, 4033,
29514 GIR_EraseRootFromParent_Done,
29515 // Label 1747: @83265
29516 GIM_Try, /*On fail goto*//*Label 1748*/ GIMT_Encode4(83305), // Rule ID 4036 //
29517 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29518 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29519 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
29520 // (ld:{ *:[v2i32] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
29521 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
29522 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29523 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29524 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29525 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29526 GIR_RootConstrainSelectedInstOperands,
29527 // GIR_Coverage, 4036,
29528 GIR_EraseRootFromParent_Done,
29529 // Label 1748: @83305
29530 GIM_Try, /*On fail goto*//*Label 1749*/ GIMT_Encode4(83345), // Rule ID 4064 //
29531 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29532 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29533 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
29534 // (ld:{ *:[v2f32] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
29535 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
29536 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29537 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29538 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29539 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29540 GIR_RootConstrainSelectedInstOperands,
29541 // GIR_Coverage, 4064,
29542 GIR_EraseRootFromParent_Done,
29543 // Label 1749: @83345
29544 GIM_Try, /*On fail goto*//*Label 1750*/ GIMT_Encode4(83385), // Rule ID 4065 //
29545 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29546 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29547 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
29548 // (ld:{ *:[v2i32] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
29549 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
29550 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29551 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29552 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29553 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29554 GIR_RootConstrainSelectedInstOperands,
29555 // GIR_Coverage, 4065,
29556 GIR_EraseRootFromParent_Done,
29557 // Label 1750: @83385
29558 GIM_Try, /*On fail goto*//*Label 1751*/ GIMT_Encode4(83405), // Rule ID 5996 //
29559 // MIs[0] Rn
29560 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
29561 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
29562 // (ld:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev2s:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn)
29563 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev2s),
29564 GIR_RootConstrainSelectedInstOperands,
29565 // GIR_Coverage, 5996,
29566 GIR_Done,
29567 // Label 1751: @83405
29568 GIM_Reject,
29569 // Label 1742: @83406
29570 GIM_Reject,
29571 // Label 1624: @83407
29572 GIM_Try, /*On fail goto*//*Label 1752*/ GIMT_Encode4(83784),
29573 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
29574 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
29575 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
29576 GIM_Try, /*On fail goto*//*Label 1753*/ GIMT_Encode4(83468), // Rule ID 3984 //
29577 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29578 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29579 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
29580 // (ld:{ *:[v2i64] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroW:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
29581 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
29582 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29583 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29584 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29585 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29586 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29587 GIR_RootConstrainSelectedInstOperands,
29588 // GIR_Coverage, 3984,
29589 GIR_EraseRootFromParent_Done,
29590 // Label 1753: @83468
29591 GIM_Try, /*On fail goto*//*Label 1754*/ GIMT_Encode4(83513), // Rule ID 3985 //
29592 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29593 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29594 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
29595 // (ld:{ *:[v2i64] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroX:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
29596 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
29597 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29598 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29599 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29600 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29601 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29602 GIR_RootConstrainSelectedInstOperands,
29603 // GIR_Coverage, 3985,
29604 GIR_EraseRootFromParent_Done,
29605 // Label 1754: @83513
29606 GIM_Try, /*On fail goto*//*Label 1755*/ GIMT_Encode4(83558), // Rule ID 3986 //
29607 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29608 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29609 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
29610 // (ld:{ *:[v2f64] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroW:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
29611 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
29612 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29613 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29614 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29615 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29616 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29617 GIR_RootConstrainSelectedInstOperands,
29618 // GIR_Coverage, 3986,
29619 GIR_EraseRootFromParent_Done,
29620 // Label 1755: @83558
29621 GIM_Try, /*On fail goto*//*Label 1756*/ GIMT_Encode4(83603), // Rule ID 3987 //
29622 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29623 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29624 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
29625 // (ld:{ *:[v2f64] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroX:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
29626 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
29627 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29628 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29629 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29630 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29631 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29632 GIR_RootConstrainSelectedInstOperands,
29633 // GIR_Coverage, 3987,
29634 GIR_EraseRootFromParent_Done,
29635 // Label 1756: @83603
29636 GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(83643), // Rule ID 4042 //
29637 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29638 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29639 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
29640 // (ld:{ *:[v2f64] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
29641 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
29642 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29643 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29644 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29645 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29646 GIR_RootConstrainSelectedInstOperands,
29647 // GIR_Coverage, 4042,
29648 GIR_EraseRootFromParent_Done,
29649 // Label 1757: @83643
29650 GIM_Try, /*On fail goto*//*Label 1758*/ GIMT_Encode4(83683), // Rule ID 4046 //
29651 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29652 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29653 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
29654 // (ld:{ *:[v2i64] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
29655 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
29656 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29657 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29658 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29659 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29660 GIR_RootConstrainSelectedInstOperands,
29661 // GIR_Coverage, 4046,
29662 GIR_EraseRootFromParent_Done,
29663 // Label 1758: @83683
29664 GIM_Try, /*On fail goto*//*Label 1759*/ GIMT_Encode4(83723), // Rule ID 4071 //
29665 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29666 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29667 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
29668 // (ld:{ *:[v2f64] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
29669 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
29670 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29671 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29672 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29673 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29674 GIR_RootConstrainSelectedInstOperands,
29675 // GIR_Coverage, 4071,
29676 GIR_EraseRootFromParent_Done,
29677 // Label 1759: @83723
29678 GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(83763), // Rule ID 4072 //
29679 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29680 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29681 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
29682 // (ld:{ *:[v2i64] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
29683 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
29684 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29685 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29686 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29687 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29688 GIR_RootConstrainSelectedInstOperands,
29689 // GIR_Coverage, 4072,
29690 GIR_EraseRootFromParent_Done,
29691 // Label 1760: @83763
29692 GIM_Try, /*On fail goto*//*Label 1761*/ GIMT_Encode4(83783), // Rule ID 5993 //
29693 // MIs[0] Rn
29694 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
29695 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
29696 // (ld:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev2d:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)
29697 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev2d),
29698 GIR_RootConstrainSelectedInstOperands,
29699 // GIR_Coverage, 5993,
29700 GIR_Done,
29701 // Label 1761: @83783
29702 GIM_Reject,
29703 // Label 1752: @83784
29704 GIM_Reject,
29705 // Label 1625: @83785
29706 GIM_Try, /*On fail goto*//*Label 1762*/ GIMT_Encode4(84292),
29707 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
29708 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
29709 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
29710 GIM_Try, /*On fail goto*//*Label 1763*/ GIMT_Encode4(83846), // Rule ID 3974 //
29711 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29712 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29713 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
29714 // (ld:{ *:[v4i16] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroW:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
29715 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
29716 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29717 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29718 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29719 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29720 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29721 GIR_RootConstrainSelectedInstOperands,
29722 // GIR_Coverage, 3974,
29723 GIR_EraseRootFromParent_Done,
29724 // Label 1763: @83846
29725 GIM_Try, /*On fail goto*//*Label 1764*/ GIMT_Encode4(83891), // Rule ID 3975 //
29726 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29727 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29728 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
29729 // (ld:{ *:[v4i16] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroX:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
29730 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
29731 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29732 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29733 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29734 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29735 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29736 GIR_RootConstrainSelectedInstOperands,
29737 // GIR_Coverage, 3975,
29738 GIR_EraseRootFromParent_Done,
29739 // Label 1764: @83891
29740 GIM_Try, /*On fail goto*//*Label 1765*/ GIMT_Encode4(83936), // Rule ID 3976 //
29741 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29742 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29743 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
29744 // (ld:{ *:[v4f16] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroW:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
29745 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
29746 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29747 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29748 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29749 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29750 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29751 GIR_RootConstrainSelectedInstOperands,
29752 // GIR_Coverage, 3976,
29753 GIR_EraseRootFromParent_Done,
29754 // Label 1765: @83936
29755 GIM_Try, /*On fail goto*//*Label 1766*/ GIMT_Encode4(83981), // Rule ID 3977 //
29756 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29757 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29758 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
29759 // (ld:{ *:[v4f16] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroX:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
29760 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
29761 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29762 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29763 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29764 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29765 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29766 GIR_RootConstrainSelectedInstOperands,
29767 // GIR_Coverage, 3977,
29768 GIR_EraseRootFromParent_Done,
29769 // Label 1766: @83981
29770 GIM_Try, /*On fail goto*//*Label 1767*/ GIMT_Encode4(84026), // Rule ID 3978 //
29771 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29772 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29773 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
29774 // (ld:{ *:[v4bf16] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroW:{ *:[v4bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
29775 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
29776 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29777 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29778 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29779 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29780 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29781 GIR_RootConstrainSelectedInstOperands,
29782 // GIR_Coverage, 3978,
29783 GIR_EraseRootFromParent_Done,
29784 // Label 1767: @84026
29785 GIM_Try, /*On fail goto*//*Label 1768*/ GIMT_Encode4(84071), // Rule ID 3979 //
29786 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29787 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29788 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
29789 // (ld:{ *:[v4bf16] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroX:{ *:[v4bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
29790 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
29791 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29792 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29793 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29794 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29795 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29796 GIR_RootConstrainSelectedInstOperands,
29797 // GIR_Coverage, 3979,
29798 GIR_EraseRootFromParent_Done,
29799 // Label 1768: @84071
29800 GIM_Try, /*On fail goto*//*Label 1769*/ GIMT_Encode4(84111), // Rule ID 4035 //
29801 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29802 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29803 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
29804 // (ld:{ *:[v4i16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
29805 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
29806 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29807 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29808 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29809 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29810 GIR_RootConstrainSelectedInstOperands,
29811 // GIR_Coverage, 4035,
29812 GIR_EraseRootFromParent_Done,
29813 // Label 1769: @84111
29814 GIM_Try, /*On fail goto*//*Label 1770*/ GIMT_Encode4(84151), // Rule ID 4037 //
29815 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29816 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29817 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
29818 // (ld:{ *:[v4f16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
29819 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
29820 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29821 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29822 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29823 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29824 GIR_RootConstrainSelectedInstOperands,
29825 // GIR_Coverage, 4037,
29826 GIR_EraseRootFromParent_Done,
29827 // Label 1770: @84151
29828 GIM_Try, /*On fail goto*//*Label 1771*/ GIMT_Encode4(84191), // Rule ID 4038 //
29829 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29830 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29831 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
29832 // (ld:{ *:[v4bf16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v4bf16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
29833 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
29834 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29835 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29836 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29837 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29838 GIR_RootConstrainSelectedInstOperands,
29839 // GIR_Coverage, 4038,
29840 GIR_EraseRootFromParent_Done,
29841 // Label 1771: @84191
29842 GIM_Try, /*On fail goto*//*Label 1772*/ GIMT_Encode4(84231), // Rule ID 4066 //
29843 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29844 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29845 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
29846 // (ld:{ *:[v4i16] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
29847 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
29848 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29849 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29850 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29851 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29852 GIR_RootConstrainSelectedInstOperands,
29853 // GIR_Coverage, 4066,
29854 GIR_EraseRootFromParent_Done,
29855 // Label 1772: @84231
29856 GIM_Try, /*On fail goto*//*Label 1773*/ GIMT_Encode4(84271), // Rule ID 4068 //
29857 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29858 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29859 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
29860 // (ld:{ *:[v4f16] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
29861 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
29862 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29863 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29864 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29865 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29866 GIR_RootConstrainSelectedInstOperands,
29867 // GIR_Coverage, 4068,
29868 GIR_EraseRootFromParent_Done,
29869 // Label 1773: @84271
29870 GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(84291), // Rule ID 5995 //
29871 // MIs[0] Rn
29872 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
29873 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
29874 // (ld:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev4h:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn)
29875 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev4h),
29876 GIR_RootConstrainSelectedInstOperands,
29877 // GIR_Coverage, 5995,
29878 GIR_Done,
29879 // Label 1774: @84291
29880 GIM_Reject,
29881 // Label 1762: @84292
29882 GIM_Reject,
29883 // Label 1626: @84293
29884 GIM_Try, /*On fail goto*//*Label 1775*/ GIMT_Encode4(84670),
29885 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
29886 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
29887 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
29888 GIM_Try, /*On fail goto*//*Label 1776*/ GIMT_Encode4(84354), // Rule ID 3988 //
29889 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29890 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29891 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
29892 // (ld:{ *:[v4i32] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroW:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
29893 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
29894 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29895 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29896 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29897 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29898 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29899 GIR_RootConstrainSelectedInstOperands,
29900 // GIR_Coverage, 3988,
29901 GIR_EraseRootFromParent_Done,
29902 // Label 1776: @84354
29903 GIM_Try, /*On fail goto*//*Label 1777*/ GIMT_Encode4(84399), // Rule ID 3989 //
29904 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29905 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29906 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
29907 // (ld:{ *:[v4i32] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroX:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
29908 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
29909 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29910 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29911 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29912 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29913 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29914 GIR_RootConstrainSelectedInstOperands,
29915 // GIR_Coverage, 3989,
29916 GIR_EraseRootFromParent_Done,
29917 // Label 1777: @84399
29918 GIM_Try, /*On fail goto*//*Label 1778*/ GIMT_Encode4(84444), // Rule ID 3990 //
29919 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29920 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29921 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
29922 // (ld:{ *:[v4f32] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroW:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
29923 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
29924 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29925 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29926 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29927 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29928 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29929 GIR_RootConstrainSelectedInstOperands,
29930 // GIR_Coverage, 3990,
29931 GIR_EraseRootFromParent_Done,
29932 // Label 1778: @84444
29933 GIM_Try, /*On fail goto*//*Label 1779*/ GIMT_Encode4(84489), // Rule ID 3991 //
29934 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29935 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29936 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
29937 // (ld:{ *:[v4f32] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroX:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
29938 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
29939 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29940 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29941 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
29942 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
29943 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29944 GIR_RootConstrainSelectedInstOperands,
29945 // GIR_Coverage, 3991,
29946 GIR_EraseRootFromParent_Done,
29947 // Label 1779: @84489
29948 GIM_Try, /*On fail goto*//*Label 1780*/ GIMT_Encode4(84529), // Rule ID 4041 //
29949 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29950 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29951 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
29952 // (ld:{ *:[v4f32] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
29953 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
29954 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29955 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29956 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29957 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29958 GIR_RootConstrainSelectedInstOperands,
29959 // GIR_Coverage, 4041,
29960 GIR_EraseRootFromParent_Done,
29961 // Label 1780: @84529
29962 GIM_Try, /*On fail goto*//*Label 1781*/ GIMT_Encode4(84569), // Rule ID 4045 //
29963 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29964 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29965 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
29966 // (ld:{ *:[v4i32] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
29967 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
29968 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29969 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29970 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29971 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29972 GIR_RootConstrainSelectedInstOperands,
29973 // GIR_Coverage, 4045,
29974 GIR_EraseRootFromParent_Done,
29975 // Label 1781: @84569
29976 GIM_Try, /*On fail goto*//*Label 1782*/ GIMT_Encode4(84609), // Rule ID 4073 //
29977 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29978 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29979 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
29980 // (ld:{ *:[v4f32] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
29981 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
29982 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29983 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29984 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29985 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
29986 GIR_RootConstrainSelectedInstOperands,
29987 // GIR_Coverage, 4073,
29988 GIR_EraseRootFromParent_Done,
29989 // Label 1782: @84609
29990 GIM_Try, /*On fail goto*//*Label 1783*/ GIMT_Encode4(84649), // Rule ID 4074 //
29991 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
29992 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
29993 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
29994 // (ld:{ *:[v4i32] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
29995 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
29996 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
29997 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
29998 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
29999 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30000 GIR_RootConstrainSelectedInstOperands,
30001 // GIR_Coverage, 4074,
30002 GIR_EraseRootFromParent_Done,
30003 // Label 1783: @84649
30004 GIM_Try, /*On fail goto*//*Label 1784*/ GIMT_Encode4(84669), // Rule ID 5992 //
30005 // MIs[0] Rn
30006 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
30007 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
30008 // (ld:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev4s:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)
30009 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev4s),
30010 GIR_RootConstrainSelectedInstOperands,
30011 // GIR_Coverage, 5992,
30012 GIR_Done,
30013 // Label 1784: @84669
30014 GIM_Reject,
30015 // Label 1775: @84670
30016 GIM_Reject,
30017 // Label 1627: @84671
30018 GIM_Try, /*On fail goto*//*Label 1785*/ GIMT_Encode4(84878),
30019 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
30020 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30021 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
30022 GIM_Try, /*On fail goto*//*Label 1786*/ GIMT_Encode4(84732), // Rule ID 3972 //
30023 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
30024 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30025 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
30026 // (ld:{ *:[v8i8] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroW:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
30027 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
30028 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30029 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30030 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30031 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30032 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30033 GIR_RootConstrainSelectedInstOperands,
30034 // GIR_Coverage, 3972,
30035 GIR_EraseRootFromParent_Done,
30036 // Label 1786: @84732
30037 GIM_Try, /*On fail goto*//*Label 1787*/ GIMT_Encode4(84777), // Rule ID 3973 //
30038 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
30039 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30040 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
30041 // (ld:{ *:[v8i8] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDroX:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
30042 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
30043 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30044 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30045 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30046 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30047 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30048 GIR_RootConstrainSelectedInstOperands,
30049 // GIR_Coverage, 3973,
30050 GIR_EraseRootFromParent_Done,
30051 // Label 1787: @84777
30052 GIM_Try, /*On fail goto*//*Label 1788*/ GIMT_Encode4(84817), // Rule ID 4034 //
30053 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
30054 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30055 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
30056 // (ld:{ *:[v8i8] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRDui:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
30057 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
30058 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30059 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30060 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
30061 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30062 GIR_RootConstrainSelectedInstOperands,
30063 // GIR_Coverage, 4034,
30064 GIR_EraseRootFromParent_Done,
30065 // Label 1788: @84817
30066 GIM_Try, /*On fail goto*//*Label 1789*/ GIMT_Encode4(84857), // Rule ID 4067 //
30067 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
30068 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30069 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
30070 // (ld:{ *:[v8i8] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURDi:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
30071 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
30072 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30073 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30074 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
30075 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30076 GIR_RootConstrainSelectedInstOperands,
30077 // GIR_Coverage, 4067,
30078 GIR_EraseRootFromParent_Done,
30079 // Label 1789: @84857
30080 GIM_Try, /*On fail goto*//*Label 1790*/ GIMT_Encode4(84877), // Rule ID 5994 //
30081 // MIs[0] Rn
30082 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
30083 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
30084 // (ld:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev8b:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn)
30085 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev8b),
30086 GIR_RootConstrainSelectedInstOperands,
30087 // GIR_Coverage, 5994,
30088 GIR_Done,
30089 // Label 1790: @84877
30090 GIM_Reject,
30091 // Label 1785: @84878
30092 GIM_Reject,
30093 // Label 1628: @84879
30094 GIM_Try, /*On fail goto*//*Label 1791*/ GIMT_Encode4(85386),
30095 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
30096 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30097 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
30098 GIM_Try, /*On fail goto*//*Label 1792*/ GIMT_Encode4(84940), // Rule ID 3992 //
30099 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
30100 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30101 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
30102 // (ld:{ *:[v8i16] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroW:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
30103 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
30104 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30105 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30106 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30107 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30108 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30109 GIR_RootConstrainSelectedInstOperands,
30110 // GIR_Coverage, 3992,
30111 GIR_EraseRootFromParent_Done,
30112 // Label 1792: @84940
30113 GIM_Try, /*On fail goto*//*Label 1793*/ GIMT_Encode4(84985), // Rule ID 3993 //
30114 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
30115 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30116 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
30117 // (ld:{ *:[v8i16] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroX:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
30118 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
30119 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30120 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30121 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30122 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30123 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30124 GIR_RootConstrainSelectedInstOperands,
30125 // GIR_Coverage, 3993,
30126 GIR_EraseRootFromParent_Done,
30127 // Label 1793: @84985
30128 GIM_Try, /*On fail goto*//*Label 1794*/ GIMT_Encode4(85030), // Rule ID 3994 //
30129 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
30130 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30131 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
30132 // (ld:{ *:[v8f16] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroW:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
30133 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
30134 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30135 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30136 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30137 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30138 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30139 GIR_RootConstrainSelectedInstOperands,
30140 // GIR_Coverage, 3994,
30141 GIR_EraseRootFromParent_Done,
30142 // Label 1794: @85030
30143 GIM_Try, /*On fail goto*//*Label 1795*/ GIMT_Encode4(85075), // Rule ID 3995 //
30144 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
30145 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30146 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
30147 // (ld:{ *:[v8f16] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroX:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
30148 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
30149 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30150 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30151 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30152 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30153 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30154 GIR_RootConstrainSelectedInstOperands,
30155 // GIR_Coverage, 3995,
30156 GIR_EraseRootFromParent_Done,
30157 // Label 1795: @85075
30158 GIM_Try, /*On fail goto*//*Label 1796*/ GIMT_Encode4(85120), // Rule ID 3996 //
30159 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
30160 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30161 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
30162 // (ld:{ *:[v8bf16] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroW:{ *:[v8bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
30163 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
30164 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30165 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30166 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30167 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30168 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30169 GIR_RootConstrainSelectedInstOperands,
30170 // GIR_Coverage, 3996,
30171 GIR_EraseRootFromParent_Done,
30172 // Label 1796: @85120
30173 GIM_Try, /*On fail goto*//*Label 1797*/ GIMT_Encode4(85165), // Rule ID 3997 //
30174 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
30175 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30176 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
30177 // (ld:{ *:[v8bf16] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroX:{ *:[v8bf16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
30178 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
30179 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30180 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30181 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30182 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30183 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30184 GIR_RootConstrainSelectedInstOperands,
30185 // GIR_Coverage, 3997,
30186 GIR_EraseRootFromParent_Done,
30187 // Label 1797: @85165
30188 GIM_Try, /*On fail goto*//*Label 1798*/ GIMT_Encode4(85205), // Rule ID 4044 //
30189 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
30190 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30191 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
30192 // (ld:{ *:[v8i16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
30193 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
30194 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30195 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30196 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
30197 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30198 GIR_RootConstrainSelectedInstOperands,
30199 // GIR_Coverage, 4044,
30200 GIR_EraseRootFromParent_Done,
30201 // Label 1798: @85205
30202 GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(85245), // Rule ID 4047 //
30203 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
30204 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30205 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
30206 // (ld:{ *:[v8f16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
30207 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
30208 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30209 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30210 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
30211 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30212 GIR_RootConstrainSelectedInstOperands,
30213 // GIR_Coverage, 4047,
30214 GIR_EraseRootFromParent_Done,
30215 // Label 1799: @85245
30216 GIM_Try, /*On fail goto*//*Label 1800*/ GIMT_Encode4(85285), // Rule ID 4048 //
30217 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
30218 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30219 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
30220 // (ld:{ *:[v8bf16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v8bf16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
30221 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
30222 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30223 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30224 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
30225 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30226 GIR_RootConstrainSelectedInstOperands,
30227 // GIR_Coverage, 4048,
30228 GIR_EraseRootFromParent_Done,
30229 // Label 1800: @85285
30230 GIM_Try, /*On fail goto*//*Label 1801*/ GIMT_Encode4(85325), // Rule ID 4075 //
30231 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
30232 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30233 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
30234 // (ld:{ *:[v8i16] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
30235 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
30236 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30237 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30238 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
30239 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30240 GIR_RootConstrainSelectedInstOperands,
30241 // GIR_Coverage, 4075,
30242 GIR_EraseRootFromParent_Done,
30243 // Label 1801: @85325
30244 GIM_Try, /*On fail goto*//*Label 1802*/ GIMT_Encode4(85365), // Rule ID 4077 //
30245 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
30246 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30247 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
30248 // (ld:{ *:[v8f16] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
30249 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
30250 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30251 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30252 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
30253 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30254 GIR_RootConstrainSelectedInstOperands,
30255 // GIR_Coverage, 4077,
30256 GIR_EraseRootFromParent_Done,
30257 // Label 1802: @85365
30258 GIM_Try, /*On fail goto*//*Label 1803*/ GIMT_Encode4(85385), // Rule ID 5991 //
30259 // MIs[0] Rn
30260 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
30261 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
30262 // (ld:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev8h:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)
30263 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev8h),
30264 GIR_RootConstrainSelectedInstOperands,
30265 // GIR_Coverage, 5991,
30266 GIR_Done,
30267 // Label 1803: @85385
30268 GIM_Reject,
30269 // Label 1791: @85386
30270 GIM_Reject,
30271 // Label 1629: @85387
30272 GIM_Try, /*On fail goto*//*Label 1804*/ GIMT_Encode4(85594),
30273 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
30274 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30275 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
30276 GIM_Try, /*On fail goto*//*Label 1805*/ GIMT_Encode4(85448), // Rule ID 3998 //
30277 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
30278 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30279 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
30280 // (ld:{ *:[v16i8] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroW:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
30281 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
30282 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30283 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30284 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30285 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30286 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30287 GIR_RootConstrainSelectedInstOperands,
30288 // GIR_Coverage, 3998,
30289 GIR_EraseRootFromParent_Done,
30290 // Label 1805: @85448
30291 GIM_Try, /*On fail goto*//*Label 1806*/ GIMT_Encode4(85493), // Rule ID 3999 //
30292 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
30293 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30294 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
30295 // (ld:{ *:[v16i8] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQroX:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
30296 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
30297 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30298 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30299 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30300 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30301 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30302 GIR_RootConstrainSelectedInstOperands,
30303 // GIR_Coverage, 3999,
30304 GIR_EraseRootFromParent_Done,
30305 // Label 1806: @85493
30306 GIM_Try, /*On fail goto*//*Label 1807*/ GIMT_Encode4(85533), // Rule ID 4043 //
30307 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
30308 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30309 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
30310 // (ld:{ *:[v16i8] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDRQui:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
30311 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
30312 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30313 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30314 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
30315 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30316 GIR_RootConstrainSelectedInstOperands,
30317 // GIR_Coverage, 4043,
30318 GIR_EraseRootFromParent_Done,
30319 // Label 1807: @85533
30320 GIM_Try, /*On fail goto*//*Label 1808*/ GIMT_Encode4(85573), // Rule ID 4076 //
30321 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
30322 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30323 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
30324 // (ld:{ *:[v16i8] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDURQi:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
30325 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
30326 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30327 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30328 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
30329 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30330 GIR_RootConstrainSelectedInstOperands,
30331 // GIR_Coverage, 4076,
30332 GIR_EraseRootFromParent_Done,
30333 // Label 1808: @85573
30334 GIM_Try, /*On fail goto*//*Label 1809*/ GIMT_Encode4(85593), // Rule ID 5990 //
30335 // MIs[0] Rn
30336 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
30337 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
30338 // (ld:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1Onev16b:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)
30339 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev16b),
30340 GIR_RootConstrainSelectedInstOperands,
30341 // GIR_Coverage, 5990,
30342 GIR_Done,
30343 // Label 1809: @85593
30344 GIM_Reject,
30345 // Label 1804: @85594
30346 GIM_Reject,
30347 // Label 1630: @85595
30348 GIM_Try, /*On fail goto*//*Label 1810*/ GIMT_Encode4(85708),
30349 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
30350 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30351 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
30352 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
30353 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30354 GIM_Try, /*On fail goto*//*Label 1811*/ GIMT_Encode4(85663), // Rule ID 10624 //
30355 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
30356 // (ld:{ *:[nxv2f16] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1H_D_IMM:{ *:[nxv2f16] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
30357 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
30358 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
30359 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30360 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
30361 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
30362 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1H_D_IMM),
30363 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
30364 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30365 GIR_RootToRootCopy, /*OpIdx*/1, // base
30366 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30367 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30368 GIR_RootConstrainSelectedInstOperands,
30369 // GIR_Coverage, 10624,
30370 GIR_EraseRootFromParent_Done,
30371 // Label 1811: @85663
30372 GIM_Try, /*On fail goto*//*Label 1812*/ GIMT_Encode4(85707), // Rule ID 10627 //
30373 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
30374 // (ld:{ *:[nxv2bf16] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1H_D_IMM:{ *:[nxv2bf16] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
30375 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
30376 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
30377 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30378 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
30379 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
30380 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1H_D_IMM),
30381 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
30382 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30383 GIR_RootToRootCopy, /*OpIdx*/1, // base
30384 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30385 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30386 GIR_RootConstrainSelectedInstOperands,
30387 // GIR_Coverage, 10627,
30388 GIR_EraseRootFromParent_Done,
30389 // Label 1812: @85707
30390 GIM_Reject,
30391 // Label 1810: @85708
30392 GIM_Reject,
30393 // Label 1631: @85709
30394 GIM_Try, /*On fail goto*//*Label 1813*/ GIMT_Encode4(85772), // Rule ID 10633 //
30395 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
30396 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
30397 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30398 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
30399 // MIs[0] base
30400 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
30401 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30402 // (ld:{ *:[nxv2f32] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1W_D_IMM:{ *:[nxv2f32] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
30403 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
30404 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
30405 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30406 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
30407 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
30408 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1W_D_IMM),
30409 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
30410 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30411 GIR_RootToRootCopy, /*OpIdx*/1, // base
30412 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30413 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30414 GIR_RootConstrainSelectedInstOperands,
30415 // GIR_Coverage, 10633,
30416 GIR_EraseRootFromParent_Done,
30417 // Label 1813: @85772
30418 GIM_Reject,
30419 // Label 1632: @85773
30420 GIM_Try, /*On fail goto*//*Label 1814*/ GIMT_Encode4(85886),
30421 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
30422 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30423 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
30424 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
30425 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30426 GIM_Try, /*On fail goto*//*Label 1815*/ GIMT_Encode4(85841), // Rule ID 10609 //
30427 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
30428 // (ld:{ *:[nxv2i64] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1D_IMM:{ *:[nxv2i64] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
30429 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
30430 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
30431 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30432 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
30433 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
30434 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1D_IMM),
30435 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
30436 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30437 GIR_RootToRootCopy, /*OpIdx*/1, // base
30438 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30439 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30440 GIR_RootConstrainSelectedInstOperands,
30441 // GIR_Coverage, 10609,
30442 GIR_EraseRootFromParent_Done,
30443 // Label 1815: @85841
30444 GIM_Try, /*On fail goto*//*Label 1816*/ GIMT_Encode4(85885), // Rule ID 10636 //
30445 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
30446 // (ld:{ *:[nxv2f64] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1D_IMM:{ *:[nxv2f64] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
30447 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
30448 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
30449 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30450 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
30451 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
30452 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1D_IMM),
30453 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
30454 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30455 GIR_RootToRootCopy, /*OpIdx*/1, // base
30456 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30457 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30458 GIR_RootConstrainSelectedInstOperands,
30459 // GIR_Coverage, 10636,
30460 GIR_EraseRootFromParent_Done,
30461 // Label 1816: @85885
30462 GIM_Reject,
30463 // Label 1814: @85886
30464 GIM_Reject,
30465 // Label 1633: @85887
30466 GIM_Try, /*On fail goto*//*Label 1817*/ GIMT_Encode4(86000),
30467 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
30468 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30469 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
30470 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
30471 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30472 GIM_Try, /*On fail goto*//*Label 1818*/ GIMT_Encode4(85955), // Rule ID 10618 //
30473 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
30474 // (ld:{ *:[nxv4f16] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1H_S_IMM:{ *:[nxv4f16] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
30475 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
30476 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
30477 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30478 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
30479 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
30480 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1H_S_IMM),
30481 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
30482 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30483 GIR_RootToRootCopy, /*OpIdx*/1, // base
30484 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30485 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30486 GIR_RootConstrainSelectedInstOperands,
30487 // GIR_Coverage, 10618,
30488 GIR_EraseRootFromParent_Done,
30489 // Label 1818: @85955
30490 GIM_Try, /*On fail goto*//*Label 1819*/ GIMT_Encode4(85999), // Rule ID 10621 //
30491 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
30492 // (ld:{ *:[nxv4bf16] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1H_S_IMM:{ *:[nxv4bf16] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
30493 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
30494 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
30495 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30496 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
30497 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
30498 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1H_S_IMM),
30499 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
30500 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30501 GIR_RootToRootCopy, /*OpIdx*/1, // base
30502 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30503 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30504 GIR_RootConstrainSelectedInstOperands,
30505 // GIR_Coverage, 10621,
30506 GIR_EraseRootFromParent_Done,
30507 // Label 1819: @85999
30508 GIM_Reject,
30509 // Label 1817: @86000
30510 GIM_Reject,
30511 // Label 1634: @86001
30512 GIM_Try, /*On fail goto*//*Label 1820*/ GIMT_Encode4(86114),
30513 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
30514 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30515 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
30516 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
30517 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30518 GIM_Try, /*On fail goto*//*Label 1821*/ GIMT_Encode4(86069), // Rule ID 10597 //
30519 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
30520 // (ld:{ *:[nxv4i32] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1W_IMM:{ *:[nxv4i32] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
30521 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
30522 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
30523 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30524 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
30525 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
30526 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1W_IMM),
30527 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
30528 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30529 GIR_RootToRootCopy, /*OpIdx*/1, // base
30530 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30531 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30532 GIR_RootConstrainSelectedInstOperands,
30533 // GIR_Coverage, 10597,
30534 GIR_EraseRootFromParent_Done,
30535 // Label 1821: @86069
30536 GIM_Try, /*On fail goto*//*Label 1822*/ GIMT_Encode4(86113), // Rule ID 10630 //
30537 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
30538 // (ld:{ *:[nxv4f32] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1W_IMM:{ *:[nxv4f32] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
30539 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
30540 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
30541 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30542 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
30543 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
30544 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1W_IMM),
30545 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
30546 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30547 GIR_RootToRootCopy, /*OpIdx*/1, // base
30548 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30549 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30550 GIR_RootConstrainSelectedInstOperands,
30551 // GIR_Coverage, 10630,
30552 GIR_EraseRootFromParent_Done,
30553 // Label 1822: @86113
30554 GIM_Reject,
30555 // Label 1820: @86114
30556 GIM_Reject,
30557 // Label 1635: @86115
30558 GIM_Try, /*On fail goto*//*Label 1823*/ GIMT_Encode4(86272),
30559 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
30560 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30561 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
30562 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
30563 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30564 GIM_Try, /*On fail goto*//*Label 1824*/ GIMT_Encode4(86183), // Rule ID 10576 //
30565 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
30566 // (ld:{ *:[nxv8i16] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1H_IMM:{ *:[nxv8i16] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
30567 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
30568 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
30569 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30570 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
30571 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
30572 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1H_IMM),
30573 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
30574 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30575 GIR_RootToRootCopy, /*OpIdx*/1, // base
30576 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30577 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30578 GIR_RootConstrainSelectedInstOperands,
30579 // GIR_Coverage, 10576,
30580 GIR_EraseRootFromParent_Done,
30581 // Label 1824: @86183
30582 GIM_Try, /*On fail goto*//*Label 1825*/ GIMT_Encode4(86227), // Rule ID 10612 //
30583 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
30584 // (ld:{ *:[nxv8f16] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1H_IMM:{ *:[nxv8f16] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
30585 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
30586 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
30587 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30588 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
30589 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
30590 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1H_IMM),
30591 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
30592 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30593 GIR_RootToRootCopy, /*OpIdx*/1, // base
30594 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30595 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30596 GIR_RootConstrainSelectedInstOperands,
30597 // GIR_Coverage, 10612,
30598 GIR_EraseRootFromParent_Done,
30599 // Label 1825: @86227
30600 GIM_Try, /*On fail goto*//*Label 1826*/ GIMT_Encode4(86271), // Rule ID 10615 //
30601 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
30602 // (ld:{ *:[nxv8bf16] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1H_IMM:{ *:[nxv8bf16] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
30603 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
30604 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
30605 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30606 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
30607 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
30608 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1H_IMM),
30609 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
30610 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30611 GIR_RootToRootCopy, /*OpIdx*/1, // base
30612 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30613 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30614 GIR_RootConstrainSelectedInstOperands,
30615 // GIR_Coverage, 10615,
30616 GIR_EraseRootFromParent_Done,
30617 // Label 1826: @86271
30618 GIM_Reject,
30619 // Label 1823: @86272
30620 GIM_Reject,
30621 // Label 1636: @86273
30622 GIM_Try, /*On fail goto*//*Label 1827*/ GIMT_Encode4(86316), // Rule ID 2368 //
30623 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
30624 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
30625 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30626 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
30627 // MIs[0] base
30628 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
30629 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30630 // (ld:{ *:[nxv16i1] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LDR_PXI:{ *:[nxv16i1] } GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
30631 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDR_PXI),
30632 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pt]
30633 GIR_RootToRootCopy, /*OpIdx*/1, // base
30634 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30635 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30636 GIR_RootConstrainSelectedInstOperands,
30637 // GIR_Coverage, 2368,
30638 GIR_EraseRootFromParent_Done,
30639 // Label 1827: @86316
30640 GIM_Reject,
30641 // Label 1637: @86317
30642 GIM_Try, /*On fail goto*//*Label 1828*/ GIMT_Encode4(86380), // Rule ID 10544 //
30643 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
30644 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
30645 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30646 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
30647 // MIs[0] base
30648 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
30649 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30650 // (ld:{ *:[nxv16i8] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD1B_IMM:{ *:[nxv16i8] } (PTRUE_B:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
30651 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
30652 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_B),
30653 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
30654 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
30655 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
30656 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1B_IMM),
30657 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
30658 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30659 GIR_RootToRootCopy, /*OpIdx*/1, // base
30660 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30661 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30662 GIR_RootConstrainSelectedInstOperands,
30663 // GIR_Coverage, 10544,
30664 GIR_EraseRootFromParent_Done,
30665 // Label 1828: @86380
30666 GIM_Reject,
30667 // Label 1638: @86381
30668 GIM_Reject,
30669 // Label 17: @86382
30670 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 1831*/ GIMT_Encode4(87473),
30671 /*GILLT_s32*//*Label 1829*/ GIMT_Encode4(86401),
30672 /*GILLT_s64*//*Label 1830*/ GIMT_Encode4(86830),
30673 // Label 1829: @86401
30674 GIM_Try, /*On fail goto*//*Label 1832*/ GIMT_Encode4(86457), // Rule ID 257 //
30675 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
30676 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30677 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
30678 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30679 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
30680 // (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDRSHWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
30681 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSHWroW),
30682 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30683 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30684 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30685 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30686 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30687 GIR_RootConstrainSelectedInstOperands,
30688 // GIR_Coverage, 257,
30689 GIR_EraseRootFromParent_Done,
30690 // Label 1832: @86457
30691 GIM_Try, /*On fail goto*//*Label 1833*/ GIMT_Encode4(86513), // Rule ID 258 //
30692 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
30693 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30694 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
30695 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30696 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
30697 // (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDRSHWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
30698 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSHWroX),
30699 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30700 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30701 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30702 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30703 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30704 GIR_RootConstrainSelectedInstOperands,
30705 // GIR_Coverage, 258,
30706 GIR_EraseRootFromParent_Done,
30707 // Label 1833: @86513
30708 GIM_Try, /*On fail goto*//*Label 1834*/ GIMT_Encode4(86569), // Rule ID 261 //
30709 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
30710 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30711 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
30712 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30713 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
30714 // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDRSBWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
30715 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSBWroW),
30716 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30717 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30718 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30719 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30720 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30721 GIR_RootConstrainSelectedInstOperands,
30722 // GIR_Coverage, 261,
30723 GIR_EraseRootFromParent_Done,
30724 // Label 1834: @86569
30725 GIM_Try, /*On fail goto*//*Label 1835*/ GIMT_Encode4(86625), // Rule ID 262 //
30726 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
30727 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30728 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
30729 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30730 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
30731 // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDRSBWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
30732 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSBWroX),
30733 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30734 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30735 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30736 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30737 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30738 GIR_RootConstrainSelectedInstOperands,
30739 // GIR_Coverage, 262,
30740 GIR_EraseRootFromParent_Done,
30741 // Label 1835: @86625
30742 GIM_Try, /*On fail goto*//*Label 1836*/ GIMT_Encode4(86676), // Rule ID 278 //
30743 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
30744 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30745 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
30746 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30747 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
30748 // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDRSHWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
30749 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSHWui),
30750 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30751 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30752 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
30753 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30754 GIR_RootConstrainSelectedInstOperands,
30755 // GIR_Coverage, 278,
30756 GIR_EraseRootFromParent_Done,
30757 // Label 1836: @86676
30758 GIM_Try, /*On fail goto*//*Label 1837*/ GIMT_Encode4(86727), // Rule ID 280 //
30759 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
30760 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30761 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
30762 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30763 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
30764 // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDRSBWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
30765 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSBWui),
30766 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30767 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30768 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
30769 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30770 GIR_RootConstrainSelectedInstOperands,
30771 // GIR_Coverage, 280,
30772 GIR_EraseRootFromParent_Done,
30773 // Label 1837: @86727
30774 GIM_Try, /*On fail goto*//*Label 1838*/ GIMT_Encode4(86778), // Rule ID 299 //
30775 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
30776 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30777 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
30778 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30779 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
30780 // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDURSHWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
30781 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSHWi),
30782 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30783 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30784 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
30785 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30786 GIR_RootConstrainSelectedInstOperands,
30787 // GIR_Coverage, 299,
30788 GIR_EraseRootFromParent_Done,
30789 // Label 1838: @86778
30790 GIM_Try, /*On fail goto*//*Label 1839*/ GIMT_Encode4(86829), // Rule ID 301 //
30791 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
30792 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30793 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
30794 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30795 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
30796 // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDURSBWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
30797 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSBWi),
30798 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30799 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30800 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
30801 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30802 GIR_RootConstrainSelectedInstOperands,
30803 // GIR_Coverage, 301,
30804 GIR_EraseRootFromParent_Done,
30805 // Label 1839: @86829
30806 GIM_Reject,
30807 // Label 1830: @86830
30808 GIM_Try, /*On fail goto*//*Label 1840*/ GIMT_Encode4(86886), // Rule ID 259 //
30809 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
30810 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30811 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30812 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30813 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
30814 // (ld:{ *:[i64] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDRSHXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
30815 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSHXroW),
30816 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30817 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30818 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30819 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30820 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30821 GIR_RootConstrainSelectedInstOperands,
30822 // GIR_Coverage, 259,
30823 GIR_EraseRootFromParent_Done,
30824 // Label 1840: @86886
30825 GIM_Try, /*On fail goto*//*Label 1841*/ GIMT_Encode4(86942), // Rule ID 260 //
30826 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
30827 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30828 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30829 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30830 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
30831 // (ld:{ *:[i64] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDRSHXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
30832 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSHXroX),
30833 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30834 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30835 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30836 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30837 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30838 GIR_RootConstrainSelectedInstOperands,
30839 // GIR_Coverage, 260,
30840 GIR_EraseRootFromParent_Done,
30841 // Label 1841: @86942
30842 GIM_Try, /*On fail goto*//*Label 1842*/ GIMT_Encode4(86998), // Rule ID 263 //
30843 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
30844 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30845 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30846 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30847 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
30848 // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDRSBXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
30849 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSBXroW),
30850 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30851 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30852 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30853 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30854 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30855 GIR_RootConstrainSelectedInstOperands,
30856 // GIR_Coverage, 263,
30857 GIR_EraseRootFromParent_Done,
30858 // Label 1842: @86998
30859 GIM_Try, /*On fail goto*//*Label 1843*/ GIMT_Encode4(87054), // Rule ID 264 //
30860 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
30861 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30862 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30863 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30864 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
30865 // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDRSBXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
30866 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSBXroX),
30867 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30868 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30869 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30870 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30871 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30872 GIR_RootConstrainSelectedInstOperands,
30873 // GIR_Coverage, 264,
30874 GIR_EraseRootFromParent_Done,
30875 // Label 1843: @87054
30876 GIM_Try, /*On fail goto*//*Label 1844*/ GIMT_Encode4(87110), // Rule ID 265 //
30877 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
30878 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30879 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30880 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30881 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
30882 // (ld:{ *:[i64] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LDRSWroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
30883 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSWroW),
30884 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30885 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30886 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30887 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30888 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30889 GIR_RootConstrainSelectedInstOperands,
30890 // GIR_Coverage, 265,
30891 GIR_EraseRootFromParent_Done,
30892 // Label 1844: @87110
30893 GIM_Try, /*On fail goto*//*Label 1845*/ GIMT_Encode4(87166), // Rule ID 266 //
30894 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
30895 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30896 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30897 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30898 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
30899 // (ld:{ *:[i64] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LDRSWroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
30900 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSWroX),
30901 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30902 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30903 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
30904 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
30905 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30906 GIR_RootConstrainSelectedInstOperands,
30907 // GIR_Coverage, 266,
30908 GIR_EraseRootFromParent_Done,
30909 // Label 1845: @87166
30910 GIM_Try, /*On fail goto*//*Label 1846*/ GIMT_Encode4(87217), // Rule ID 279 //
30911 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
30912 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30913 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30914 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30915 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
30916 // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDRSHXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
30917 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSHXui),
30918 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30919 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30920 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
30921 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30922 GIR_RootConstrainSelectedInstOperands,
30923 // GIR_Coverage, 279,
30924 GIR_EraseRootFromParent_Done,
30925 // Label 1846: @87217
30926 GIM_Try, /*On fail goto*//*Label 1847*/ GIMT_Encode4(87268), // Rule ID 281 //
30927 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
30928 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30929 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30930 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30931 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
30932 // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDRSBXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
30933 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSBXui),
30934 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30935 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30936 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
30937 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30938 GIR_RootConstrainSelectedInstOperands,
30939 // GIR_Coverage, 281,
30940 GIR_EraseRootFromParent_Done,
30941 // Label 1847: @87268
30942 GIM_Try, /*On fail goto*//*Label 1848*/ GIMT_Encode4(87319), // Rule ID 282 //
30943 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
30944 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30945 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30946 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30947 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
30948 // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LDRSWui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
30949 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSWui),
30950 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30951 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30952 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
30953 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30954 GIR_RootConstrainSelectedInstOperands,
30955 // GIR_Coverage, 282,
30956 GIR_EraseRootFromParent_Done,
30957 // Label 1848: @87319
30958 GIM_Try, /*On fail goto*//*Label 1849*/ GIMT_Encode4(87370), // Rule ID 300 //
30959 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
30960 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30961 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30962 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30963 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
30964 // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LDURSHXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
30965 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSHXi),
30966 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30967 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30968 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
30969 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30970 GIR_RootConstrainSelectedInstOperands,
30971 // GIR_Coverage, 300,
30972 GIR_EraseRootFromParent_Done,
30973 // Label 1849: @87370
30974 GIM_Try, /*On fail goto*//*Label 1850*/ GIMT_Encode4(87421), // Rule ID 302 //
30975 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
30976 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30977 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30978 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30979 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
30980 // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LDURSBXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
30981 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSBXi),
30982 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30983 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
30984 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
30985 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
30986 GIR_RootConstrainSelectedInstOperands,
30987 // GIR_Coverage, 302,
30988 GIR_EraseRootFromParent_Done,
30989 // Label 1850: @87421
30990 GIM_Try, /*On fail goto*//*Label 1851*/ GIMT_Encode4(87472), // Rule ID 303 //
30991 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
30992 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
30993 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
30994 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
30995 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
30996 // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LDURSWi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
30997 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSWi),
30998 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
30999 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31000 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31001 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31002 GIR_RootConstrainSelectedInstOperands,
31003 // GIR_Coverage, 303,
31004 GIR_EraseRootFromParent_Done,
31005 // Label 1851: @87472
31006 GIM_Reject,
31007 // Label 1831: @87473
31008 GIM_Reject,
31009 // Label 18: @87474
31010 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 1854*/ GIMT_Encode4(90487),
31011 /*GILLT_s32*//*Label 1852*/ GIMT_Encode4(87493),
31012 /*GILLT_s64*//*Label 1853*/ GIMT_Encode4(88952),
31013 // Label 1852: @87493
31014 GIM_Try, /*On fail goto*//*Label 1855*/ GIMT_Encode4(87549), // Rule ID 239 //
31015 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31016 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31017 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31018 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31019 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
31020 // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
31021 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
31022 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31023 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31024 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
31025 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
31026 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31027 GIR_RootConstrainSelectedInstOperands,
31028 // GIR_Coverage, 239,
31029 GIR_EraseRootFromParent_Done,
31030 // Label 1855: @87549
31031 GIM_Try, /*On fail goto*//*Label 1856*/ GIMT_Encode4(87605), // Rule ID 240 //
31032 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31033 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31034 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31035 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31036 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
31037 // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
31038 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
31039 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31040 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31041 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
31042 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
31043 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31044 GIR_RootConstrainSelectedInstOperands,
31045 // GIR_Coverage, 240,
31046 GIR_EraseRootFromParent_Done,
31047 // Label 1856: @87605
31048 GIM_Try, /*On fail goto*//*Label 1857*/ GIMT_Encode4(87661), // Rule ID 241 //
31049 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
31050 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31051 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31052 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31053 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
31054 // (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
31055 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroW),
31056 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31057 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31058 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
31059 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
31060 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31061 GIR_RootConstrainSelectedInstOperands,
31062 // GIR_Coverage, 241,
31063 GIR_EraseRootFromParent_Done,
31064 // Label 1857: @87661
31065 GIM_Try, /*On fail goto*//*Label 1858*/ GIMT_Encode4(87717), // Rule ID 242 //
31066 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
31067 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31068 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31069 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31070 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
31071 // (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
31072 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroX),
31073 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31074 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31075 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
31076 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
31077 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31078 GIR_RootConstrainSelectedInstOperands,
31079 // GIR_Coverage, 242,
31080 GIR_EraseRootFromParent_Done,
31081 // Label 1858: @87717
31082 GIM_Try, /*On fail goto*//*Label 1859*/ GIMT_Encode4(87773), // Rule ID 4022 //
31083 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31084 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31085 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31086 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31087 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
31088 // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>> => (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
31089 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
31090 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31091 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31092 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
31093 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
31094 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31095 GIR_RootConstrainSelectedInstOperands,
31096 // GIR_Coverage, 4022,
31097 GIR_EraseRootFromParent_Done,
31098 // Label 1859: @87773
31099 GIM_Try, /*On fail goto*//*Label 1860*/ GIMT_Encode4(87829), // Rule ID 4023 //
31100 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31101 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31102 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31103 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31104 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
31105 // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>> => (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
31106 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
31107 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31108 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31109 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
31110 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
31111 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31112 GIR_RootConstrainSelectedInstOperands,
31113 // GIR_Coverage, 4023,
31114 GIR_EraseRootFromParent_Done,
31115 // Label 1860: @87829
31116 GIM_Try, /*On fail goto*//*Label 1861*/ GIMT_Encode4(87880), // Rule ID 276 //
31117 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
31118 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31119 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31120 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31121 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
31122 // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
31123 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHui),
31124 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31125 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31126 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31127 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31128 GIR_RootConstrainSelectedInstOperands,
31129 // GIR_Coverage, 276,
31130 GIR_EraseRootFromParent_Done,
31131 // Label 1861: @87880
31132 GIM_Try, /*On fail goto*//*Label 1862*/ GIMT_Encode4(87931), // Rule ID 277 //
31133 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31134 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31135 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31136 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31137 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
31138 // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
31139 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
31140 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31141 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31142 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31143 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31144 GIR_RootConstrainSelectedInstOperands,
31145 // GIR_Coverage, 277,
31146 GIR_EraseRootFromParent_Done,
31147 // Label 1862: @87931
31148 GIM_Try, /*On fail goto*//*Label 1863*/ GIMT_Encode4(87990), // Rule ID 6751 //
31149 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31150 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
31151 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
31152 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31153 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31154 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
31155 // (atomic_load:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_14575>> => (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset)
31156 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
31157 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31158 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31159 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
31160 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
31161 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31162 GIR_RootConstrainSelectedInstOperands,
31163 // GIR_Coverage, 6751,
31164 GIR_EraseRootFromParent_Done,
31165 // Label 1863: @87990
31166 GIM_Try, /*On fail goto*//*Label 1864*/ GIMT_Encode4(88049), // Rule ID 6753 //
31167 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31168 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
31169 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
31170 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31171 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31172 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
31173 // (atomic_load:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_14575>> => (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset)
31174 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
31175 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31176 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31177 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
31178 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
31179 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31180 GIR_RootConstrainSelectedInstOperands,
31181 // GIR_Coverage, 6753,
31182 GIR_EraseRootFromParent_Done,
31183 // Label 1864: @88049
31184 GIM_Try, /*On fail goto*//*Label 1865*/ GIMT_Encode4(88108), // Rule ID 6763 //
31185 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
31186 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
31187 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
31188 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31189 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31190 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
31191 // (atomic_load:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_14584>> => (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
31192 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroW),
31193 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31194 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31195 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
31196 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
31197 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31198 GIR_RootConstrainSelectedInstOperands,
31199 // GIR_Coverage, 6763,
31200 GIR_EraseRootFromParent_Done,
31201 // Label 1865: @88108
31202 GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(88167), // Rule ID 6765 //
31203 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
31204 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
31205 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
31206 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31207 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31208 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
31209 // (atomic_load:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_14584>> => (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
31210 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroX),
31211 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31212 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31213 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
31214 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
31215 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31216 GIR_RootConstrainSelectedInstOperands,
31217 // GIR_Coverage, 6765,
31218 GIR_EraseRootFromParent_Done,
31219 // Label 1866: @88167
31220 GIM_Try, /*On fail goto*//*Label 1867*/ GIMT_Encode4(88218), // Rule ID 297 //
31221 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
31222 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31223 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31224 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31225 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
31226 // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
31227 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
31228 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31229 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31230 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31231 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31232 GIR_RootConstrainSelectedInstOperands,
31233 // GIR_Coverage, 297,
31234 GIR_EraseRootFromParent_Done,
31235 // Label 1867: @88218
31236 GIM_Try, /*On fail goto*//*Label 1868*/ GIMT_Encode4(88269), // Rule ID 298 //
31237 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31238 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31239 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31240 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31241 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
31242 // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
31243 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
31244 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31245 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31246 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31247 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31248 GIR_RootConstrainSelectedInstOperands,
31249 // GIR_Coverage, 298,
31250 GIR_EraseRootFromParent_Done,
31251 // Label 1868: @88269
31252 GIM_Try, /*On fail goto*//*Label 1869*/ GIMT_Encode4(88320), // Rule ID 4052 //
31253 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31254 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31255 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31256 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31257 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
31258 // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
31259 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
31260 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31261 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31262 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31263 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31264 GIR_RootConstrainSelectedInstOperands,
31265 // GIR_Coverage, 4052,
31266 GIR_EraseRootFromParent_Done,
31267 // Label 1869: @88320
31268 GIM_Try, /*On fail goto*//*Label 1870*/ GIMT_Encode4(88371), // Rule ID 4085 //
31269 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
31270 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31271 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31272 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31273 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
31274 // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
31275 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
31276 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31277 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31278 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31279 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31280 GIR_RootConstrainSelectedInstOperands,
31281 // GIR_Coverage, 4085,
31282 GIR_EraseRootFromParent_Done,
31283 // Label 1870: @88371
31284 GIM_Try, /*On fail goto*//*Label 1871*/ GIMT_Encode4(88422), // Rule ID 4086 //
31285 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31286 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31287 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31288 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31289 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
31290 // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
31291 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
31292 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31293 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31294 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31295 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31296 GIR_RootConstrainSelectedInstOperands,
31297 // GIR_Coverage, 4086,
31298 GIR_EraseRootFromParent_Done,
31299 // Label 1871: @88422
31300 GIM_Try, /*On fail goto*//*Label 1872*/ GIMT_Encode4(88473), // Rule ID 4087 //
31301 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31302 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31303 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31304 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31305 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
31306 // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
31307 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
31308 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31309 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31310 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31311 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31312 GIR_RootConstrainSelectedInstOperands,
31313 // GIR_Coverage, 4087,
31314 GIR_EraseRootFromParent_Done,
31315 // Label 1872: @88473
31316 GIM_Try, /*On fail goto*//*Label 1873*/ GIMT_Encode4(88527), // Rule ID 6755 //
31317 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31318 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
31319 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
31320 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31321 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31322 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
31323 // (atomic_load:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_14575>> => (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
31324 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
31325 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31326 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31327 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31328 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31329 GIR_RootConstrainSelectedInstOperands,
31330 // GIR_Coverage, 6755,
31331 GIR_EraseRootFromParent_Done,
31332 // Label 1873: @88527
31333 GIM_Try, /*On fail goto*//*Label 1874*/ GIMT_Encode4(88581), // Rule ID 6757 //
31334 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31335 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
31336 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
31337 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31338 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31339 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
31340 // (atomic_load:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_14575>> => (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
31341 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
31342 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31343 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31344 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31345 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31346 GIR_RootConstrainSelectedInstOperands,
31347 // GIR_Coverage, 6757,
31348 GIR_EraseRootFromParent_Done,
31349 // Label 1874: @88581
31350 GIM_Try, /*On fail goto*//*Label 1875*/ GIMT_Encode4(88635), // Rule ID 6767 //
31351 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
31352 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
31353 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
31354 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31355 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31356 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
31357 // (atomic_load:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_14584>> => (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
31358 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHui),
31359 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31360 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31361 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31362 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31363 GIR_RootConstrainSelectedInstOperands,
31364 // GIR_Coverage, 6767,
31365 GIR_EraseRootFromParent_Done,
31366 // Label 1875: @88635
31367 GIM_Try, /*On fail goto*//*Label 1876*/ GIMT_Encode4(88689), // Rule ID 6769 //
31368 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
31369 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
31370 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
31371 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31372 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31373 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
31374 // (atomic_load:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_14584>> => (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
31375 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
31376 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31377 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31378 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31379 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31380 GIR_RootConstrainSelectedInstOperands,
31381 // GIR_Coverage, 6769,
31382 GIR_EraseRootFromParent_Done,
31383 // Label 1876: @88689
31384 GIM_Try, /*On fail goto*//*Label 1877*/ GIMT_Encode4(88746), // Rule ID 7091 //
31385 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO),
31386 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31387 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
31388 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
31389 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31390 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31391 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
31392 // (atomic_load:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_14573>> => (LDAPURBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
31393 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAPURBi),
31394 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31395 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31396 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31397 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31398 GIR_RootConstrainSelectedInstOperands,
31399 // GIR_Coverage, 7091,
31400 GIR_EraseRootFromParent_Done,
31401 // Label 1877: @88746
31402 GIM_Try, /*On fail goto*//*Label 1878*/ GIMT_Encode4(88803), // Rule ID 7093 //
31403 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO),
31404 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
31405 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
31406 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
31407 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31408 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31409 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
31410 // (atomic_load:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_14582>> => (LDAPURHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
31411 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAPURHi),
31412 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
31413 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31414 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31415 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
31416 GIR_RootConstrainSelectedInstOperands,
31417 // GIR_Coverage, 7093,
31418 GIR_EraseRootFromParent_Done,
31419 // Label 1878: @88803
31420 GIM_Try, /*On fail goto*//*Label 1879*/ GIMT_Encode4(88840), // Rule ID 6747 //
31421 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31422 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
31423 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
31424 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31425 // MIs[0] ptr
31426 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
31427 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
31428 // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_14571>> => (LDARB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
31429 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARB),
31430 GIR_RootConstrainSelectedInstOperands,
31431 // GIR_Coverage, 6747,
31432 GIR_Done,
31433 // Label 1879: @88840
31434 GIM_Try, /*On fail goto*//*Label 1880*/ GIMT_Encode4(88877), // Rule ID 6749 //
31435 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31436 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
31437 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
31438 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31439 // MIs[0] ptr
31440 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
31441 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
31442 // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_14573>> => (LDARB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
31443 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARB),
31444 GIR_RootConstrainSelectedInstOperands,
31445 // GIR_Coverage, 6749,
31446 GIR_Done,
31447 // Label 1880: @88877
31448 GIM_Try, /*On fail goto*//*Label 1881*/ GIMT_Encode4(88914), // Rule ID 6759 //
31449 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
31450 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
31451 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
31452 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31453 // MIs[0] ptr
31454 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
31455 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
31456 // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_14580>> => (LDARH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
31457 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARH),
31458 GIR_RootConstrainSelectedInstOperands,
31459 // GIR_Coverage, 6759,
31460 GIR_Done,
31461 // Label 1881: @88914
31462 GIM_Try, /*On fail goto*//*Label 1882*/ GIMT_Encode4(88951), // Rule ID 6761 //
31463 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
31464 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
31465 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
31466 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
31467 // MIs[0] ptr
31468 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
31469 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
31470 // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_14582>> => (LDARH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
31471 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARH),
31472 GIR_RootConstrainSelectedInstOperands,
31473 // GIR_Coverage, 6761,
31474 GIR_Done,
31475 // Label 1882: @88951
31476 GIM_Reject,
31477 // Label 1853: @88952
31478 GIM_Try, /*On fail goto*//*Label 1883*/ GIMT_Encode4(89040), // Rule ID 4000 //
31479 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31480 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31481 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
31482 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31483 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
31484 // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
31485 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
31486 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
31487 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31488 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31489 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
31490 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
31491 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
31492 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
31493 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
31494 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31495 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31496 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31497 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
31498 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
31499 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
31500 // GIR_Coverage, 4000,
31501 GIR_EraseRootFromParent_Done,
31502 // Label 1883: @89040
31503 GIM_Try, /*On fail goto*//*Label 1884*/ GIMT_Encode4(89128), // Rule ID 4001 //
31504 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31505 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31506 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
31507 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31508 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
31509 // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
31510 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
31511 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
31512 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31513 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31514 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
31515 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
31516 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
31517 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
31518 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
31519 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31520 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31521 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31522 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
31523 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
31524 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
31525 // GIR_Coverage, 4001,
31526 GIR_EraseRootFromParent_Done,
31527 // Label 1884: @89128
31528 GIM_Try, /*On fail goto*//*Label 1885*/ GIMT_Encode4(89216), // Rule ID 4002 //
31529 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
31530 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31531 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
31532 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31533 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
31534 // (ld:{ *:[i64] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
31535 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
31536 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroW),
31537 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31538 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31539 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
31540 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
31541 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
31542 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
31543 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
31544 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31545 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31546 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31547 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
31548 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
31549 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
31550 // GIR_Coverage, 4002,
31551 GIR_EraseRootFromParent_Done,
31552 // Label 1885: @89216
31553 GIM_Try, /*On fail goto*//*Label 1886*/ GIMT_Encode4(89304), // Rule ID 4003 //
31554 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
31555 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31556 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
31557 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31558 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
31559 // (ld:{ *:[i64] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
31560 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
31561 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroX),
31562 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31563 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31564 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
31565 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
31566 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
31567 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
31568 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
31569 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31570 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31571 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31572 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
31573 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
31574 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
31575 // GIR_Coverage, 4003,
31576 GIR_EraseRootFromParent_Done,
31577 // Label 1886: @89304
31578 GIM_Try, /*On fail goto*//*Label 1887*/ GIMT_Encode4(89392), // Rule ID 4004 //
31579 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
31580 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31581 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
31582 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31583 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
31584 // (ld:{ *:[i64] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
31585 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
31586 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRWroW),
31587 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31588 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31589 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
31590 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
31591 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
31592 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
31593 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
31594 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31595 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31596 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31597 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
31598 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
31599 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
31600 // GIR_Coverage, 4004,
31601 GIR_EraseRootFromParent_Done,
31602 // Label 1887: @89392
31603 GIM_Try, /*On fail goto*//*Label 1888*/ GIMT_Encode4(89480), // Rule ID 4005 //
31604 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
31605 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31606 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
31607 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31608 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
31609 // (ld:{ *:[i64] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
31610 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
31611 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRWroX),
31612 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31613 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31614 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
31615 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
31616 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
31617 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
31618 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
31619 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31620 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31621 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31622 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
31623 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
31624 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
31625 // GIR_Coverage, 4005,
31626 GIR_EraseRootFromParent_Done,
31627 // Label 1888: @89480
31628 GIM_Try, /*On fail goto*//*Label 1889*/ GIMT_Encode4(89568), // Rule ID 4006 //
31629 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31630 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31631 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
31632 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31633 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
31634 // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
31635 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
31636 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
31637 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31638 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31639 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
31640 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
31641 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
31642 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
31643 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
31644 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31645 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31646 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31647 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
31648 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
31649 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
31650 // GIR_Coverage, 4006,
31651 GIR_EraseRootFromParent_Done,
31652 // Label 1889: @89568
31653 GIM_Try, /*On fail goto*//*Label 1890*/ GIMT_Encode4(89656), // Rule ID 4007 //
31654 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31655 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31656 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
31657 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31658 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
31659 // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
31660 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
31661 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
31662 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31663 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31664 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
31665 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
31666 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
31667 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
31668 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
31669 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31670 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31671 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31672 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
31673 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
31674 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
31675 // GIR_Coverage, 4007,
31676 GIR_EraseRootFromParent_Done,
31677 // Label 1890: @89656
31678 GIM_Try, /*On fail goto*//*Label 1891*/ GIMT_Encode4(89739), // Rule ID 4050 //
31679 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31680 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31681 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
31682 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31683 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
31684 // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
31685 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
31686 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
31687 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31688 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31689 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31690 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
31691 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
31692 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
31693 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31694 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31695 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31696 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
31697 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
31698 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
31699 // GIR_Coverage, 4050,
31700 GIR_EraseRootFromParent_Done,
31701 // Label 1891: @89739
31702 GIM_Try, /*On fail goto*//*Label 1892*/ GIMT_Encode4(89822), // Rule ID 4051 //
31703 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
31704 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31705 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
31706 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31707 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
31708 // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
31709 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
31710 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHHui),
31711 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31712 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31713 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31714 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
31715 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
31716 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
31717 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31718 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31719 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31720 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
31721 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
31722 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
31723 // GIR_Coverage, 4051,
31724 GIR_EraseRootFromParent_Done,
31725 // Label 1892: @89822
31726 GIM_Try, /*On fail goto*//*Label 1893*/ GIMT_Encode4(89905), // Rule ID 4053 //
31727 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31728 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31729 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
31730 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31731 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
31732 // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
31733 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
31734 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
31735 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31736 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31737 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31738 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
31739 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
31740 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
31741 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31742 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31743 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31744 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
31745 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
31746 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
31747 // GIR_Coverage, 4053,
31748 GIR_EraseRootFromParent_Done,
31749 // Label 1893: @89905
31750 GIM_Try, /*On fail goto*//*Label 1894*/ GIMT_Encode4(89988), // Rule ID 4061 //
31751 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
31752 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31753 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
31754 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31755 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
31756 // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
31757 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
31758 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRWui),
31759 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31760 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31761 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31762 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
31763 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
31764 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
31765 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31766 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31767 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31768 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
31769 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
31770 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
31771 // GIR_Coverage, 4061,
31772 GIR_EraseRootFromParent_Done,
31773 // Label 1894: @89988
31774 GIM_Try, /*On fail goto*//*Label 1895*/ GIMT_Encode4(90071), // Rule ID 4088 //
31775 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
31776 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31777 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
31778 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31779 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
31780 // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
31781 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
31782 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURWi),
31783 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31784 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31785 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31786 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
31787 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
31788 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
31789 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31790 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31791 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31792 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
31793 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
31794 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
31795 // GIR_Coverage, 4088,
31796 GIR_EraseRootFromParent_Done,
31797 // Label 1895: @90071
31798 GIM_Try, /*On fail goto*//*Label 1896*/ GIMT_Encode4(90154), // Rule ID 4089 //
31799 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
31800 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31801 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
31802 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31803 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
31804 // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
31805 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
31806 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
31807 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31808 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31809 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31810 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
31811 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
31812 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
31813 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31814 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31815 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31816 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
31817 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
31818 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
31819 // GIR_Coverage, 4089,
31820 GIR_EraseRootFromParent_Done,
31821 // Label 1896: @90154
31822 GIM_Try, /*On fail goto*//*Label 1897*/ GIMT_Encode4(90237), // Rule ID 4090 //
31823 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31824 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31825 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
31826 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31827 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
31828 // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
31829 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
31830 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
31831 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31832 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31833 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31834 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
31835 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
31836 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
31837 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31838 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31839 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31840 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
31841 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
31842 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
31843 // GIR_Coverage, 4090,
31844 GIR_EraseRootFromParent_Done,
31845 // Label 1897: @90237
31846 GIM_Try, /*On fail goto*//*Label 1898*/ GIMT_Encode4(90320), // Rule ID 4091 //
31847 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31848 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31849 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
31850 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31851 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
31852 // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
31853 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
31854 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
31855 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31856 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31857 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31858 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
31859 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
31860 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
31861 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31862 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31863 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31864 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
31865 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
31866 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
31867 // GIR_Coverage, 4091,
31868 GIR_EraseRootFromParent_Done,
31869 // Label 1898: @90320
31870 GIM_Try, /*On fail goto*//*Label 1899*/ GIMT_Encode4(90403), // Rule ID 4092 //
31871 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
31872 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31873 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
31874 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31875 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
31876 // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
31877 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
31878 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
31879 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31880 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31881 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31882 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
31883 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
31884 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
31885 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31886 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31887 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31888 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
31889 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
31890 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
31891 // GIR_Coverage, 4092,
31892 GIR_EraseRootFromParent_Done,
31893 // Label 1899: @90403
31894 GIM_Try, /*On fail goto*//*Label 1900*/ GIMT_Encode4(90486), // Rule ID 4093 //
31895 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
31896 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31897 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
31898 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
31899 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
31900 // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
31901 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
31902 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
31903 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31904 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
31905 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
31906 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
31907 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
31908 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
31909 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31910 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31911 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31912 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
31913 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
31914 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
31915 // GIR_Coverage, 4093,
31916 GIR_EraseRootFromParent_Done,
31917 // Label 1900: @90486
31918 GIM_Reject,
31919 // Label 1854: @90487
31920 GIM_Reject,
31921 // Label 19: @90488
31922 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(24), /*)*//*default:*//*Label 1921*/ GIMT_Encode4(104564),
31923 /*GILLT_s8*//*Label 1901*/ GIMT_Encode4(90595),
31924 /*GILLT_s16*//*Label 1902*/ GIMT_Encode4(90962),
31925 /*GILLT_s32*//*Label 1903*/ GIMT_Encode4(92350),
31926 /*GILLT_s64*//*Label 1904*/ GIMT_Encode4(96945),
31927 /*GILLT_s128*//*Label 1905*/ GIMT_Encode4(100714),
31928 /*GILLT_v2s32*//*Label 1906*/ GIMT_Encode4(100920),
31929 /*GILLT_v2s64*//*Label 1907*/ GIMT_Encode4(101326),
31930 /*GILLT_v4s16*//*Label 1908*/ GIMT_Encode4(101776),
31931 /*GILLT_v4s32*//*Label 1909*/ GIMT_Encode4(102368),
31932 /*GILLT_v8s8*//*Label 1910*/ GIMT_Encode4(102774),
31933 /*GILLT_v8s16*//*Label 1911*/ GIMT_Encode4(102994),
31934 /*GILLT_v16s8*//*Label 1912*/ GIMT_Encode4(103586), GIMT_Encode4(0), GIMT_Encode4(0),
31935 /*GILLT_nxv2s16*//*Label 1913*/ GIMT_Encode4(103806),
31936 /*GILLT_nxv2s32*//*Label 1914*/ GIMT_Encode4(103916),
31937 /*GILLT_nxv2s64*//*Label 1915*/ GIMT_Encode4(103976), GIMT_Encode4(0),
31938 /*GILLT_nxv4s16*//*Label 1916*/ GIMT_Encode4(104086),
31939 /*GILLT_nxv4s32*//*Label 1917*/ GIMT_Encode4(104196), GIMT_Encode4(0),
31940 /*GILLT_nxv8s16*//*Label 1918*/ GIMT_Encode4(104306),
31941 /*GILLT_nxv16s1*//*Label 1919*/ GIMT_Encode4(104460),
31942 /*GILLT_nxv16s8*//*Label 1920*/ GIMT_Encode4(104504),
31943 // Label 1901: @90595
31944 GIM_Try, /*On fail goto*//*Label 1922*/ GIMT_Encode4(90961),
31945 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
31946 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
31947 GIM_Try, /*On fail goto*//*Label 1923*/ GIMT_Encode4(90675), // Rule ID 12435 //
31948 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
31949 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
31950 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
31951 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
31952 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
31953 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
31954 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31955 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
31956 // MIs[2] Operand 1
31957 // No operand predicates
31958 // MIs[0] Rn
31959 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
31960 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
31961 GIM_CheckIsSafeToFold, /*NumInsns*/2,
31962 // (st (vector_extract:{ *:[i8] } VecListOne128:{ *:[v16i8] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i8 VecListOne128:{ *:[v16i8] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
31963 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i8),
31964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
31965 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
31966 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
31967 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
31968 GIR_RootConstrainSelectedInstOperands,
31969 // GIR_Coverage, 12435,
31970 GIR_EraseRootFromParent_Done,
31971 // Label 1923: @90675
31972 GIM_Try, /*On fail goto*//*Label 1924*/ GIMT_Encode4(90774), // Rule ID 12436 //
31973 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
31974 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
31975 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
31976 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
31977 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
31978 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
31979 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31980 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
31981 // MIs[2] Operand 1
31982 // No operand predicates
31983 // MIs[0] Rn
31984 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
31985 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
31986 GIM_CheckIsSafeToFold, /*NumInsns*/2,
31987 // (st (vector_extract:{ *:[i8] } VecListOne64:{ *:[v8i8] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i8 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v8i8] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
31988 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
31989 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
31990 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
31991 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
31992 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
31993 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
31994 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
31995 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
31996 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i8),
31997 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31998 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
31999 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
32000 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
32001 GIR_RootConstrainSelectedInstOperands,
32002 // GIR_Coverage, 12436,
32003 GIR_EraseRootFromParent_Done,
32004 // Label 1924: @90774
32005 GIM_Try, /*On fail goto*//*Label 1925*/ GIMT_Encode4(90823), // Rule ID 313 //
32006 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
32007 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
32008 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32009 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
32010 // (st FPR8Op:{ *:[i8] }:$Rt, (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRBroW FPR8Op:{ *:[i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
32011 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBroW),
32012 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
32013 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32014 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
32015 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
32016 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
32017 GIR_RootConstrainSelectedInstOperands,
32018 // GIR_Coverage, 313,
32019 GIR_EraseRootFromParent_Done,
32020 // Label 1925: @90823
32021 GIM_Try, /*On fail goto*//*Label 1926*/ GIMT_Encode4(90872), // Rule ID 314 //
32022 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
32023 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
32024 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32025 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
32026 // (st FPR8Op:{ *:[i8] }:$Rt, (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRBroX FPR8Op:{ *:[i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
32027 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBroX),
32028 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
32029 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32030 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
32031 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
32032 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
32033 GIR_RootConstrainSelectedInstOperands,
32034 // GIR_Coverage, 314,
32035 GIR_EraseRootFromParent_Done,
32036 // Label 1926: @90872
32037 GIM_Try, /*On fail goto*//*Label 1927*/ GIMT_Encode4(90916), // Rule ID 323 //
32038 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
32039 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
32040 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32041 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
32042 // (st FPR8Op:{ *:[i8] }:$Rt, (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRBui FPR8Op:{ *:[i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
32043 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBui),
32044 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
32045 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32046 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
32047 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
32048 GIR_RootConstrainSelectedInstOperands,
32049 // GIR_Coverage, 323,
32050 GIR_EraseRootFromParent_Done,
32051 // Label 1927: @90916
32052 GIM_Try, /*On fail goto*//*Label 1928*/ GIMT_Encode4(90960), // Rule ID 331 //
32053 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
32054 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
32055 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32056 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
32057 // (st FPR8Op:{ *:[i8] }:$Rt, (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURBi FPR8Op:{ *:[i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
32058 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURBi),
32059 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
32060 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32061 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
32062 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
32063 GIR_RootConstrainSelectedInstOperands,
32064 // GIR_Coverage, 331,
32065 GIR_EraseRootFromParent_Done,
32066 // Label 1928: @90960
32067 GIM_Reject,
32068 // Label 1922: @90961
32069 GIM_Reject,
32070 // Label 1902: @90962
32071 GIM_Try, /*On fail goto*//*Label 1929*/ GIMT_Encode4(92349),
32072 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
32073 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
32074 GIM_Try, /*On fail goto*//*Label 1930*/ GIMT_Encode4(91073), // Rule ID 4186 //
32075 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32076 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32077 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
32078 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32079 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32080 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32081 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32082 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32083 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
32084 // (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, 0:{ *:[i64] }), (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRHroW (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
32085 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
32086 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32087 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32088 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Vt
32089 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
32090 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
32091 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroW),
32092 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32093 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32094 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
32095 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
32096 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32097 GIR_RootConstrainSelectedInstOperands,
32098 // GIR_Coverage, 4186,
32099 GIR_EraseRootFromParent_Done,
32100 // Label 1930: @91073
32101 GIM_Try, /*On fail goto*//*Label 1931*/ GIMT_Encode4(91172), // Rule ID 4187 //
32102 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32103 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32104 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
32105 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32106 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32107 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32108 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32109 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32110 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
32111 // (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRHroX (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
32112 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
32113 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32114 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32115 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Vt
32116 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
32117 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
32118 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroX),
32119 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32120 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32121 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
32122 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
32123 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32124 GIR_RootConstrainSelectedInstOperands,
32125 // GIR_Coverage, 4187,
32126 GIR_EraseRootFromParent_Done,
32127 // Label 1931: @91172
32128 GIM_Try, /*On fail goto*//*Label 1932*/ GIMT_Encode4(91271), // Rule ID 12433 //
32129 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32130 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32131 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
32132 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32133 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
32134 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32135 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32136 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32137 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
32138 // (st (vector_extract:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, 0:{ *:[i64] }), (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRHroW (EXTRACT_SUBREG:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
32139 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
32140 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32141 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32142 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Vt
32143 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
32144 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
32145 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroW),
32146 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32147 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32148 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
32149 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
32150 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32151 GIR_RootConstrainSelectedInstOperands,
32152 // GIR_Coverage, 12433,
32153 GIR_EraseRootFromParent_Done,
32154 // Label 1932: @91271
32155 GIM_Try, /*On fail goto*//*Label 1933*/ GIMT_Encode4(91370), // Rule ID 12434 //
32156 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32157 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32158 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
32159 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32160 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
32161 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32162 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32163 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32164 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
32165 // (st (vector_extract:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRHroX (EXTRACT_SUBREG:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
32166 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
32167 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32168 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32169 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Vt
32170 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
32171 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
32172 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroX),
32173 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32174 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32175 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
32176 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
32177 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32178 GIR_RootConstrainSelectedInstOperands,
32179 // GIR_Coverage, 12434,
32180 GIR_EraseRootFromParent_Done,
32181 // Label 1933: @91370
32182 GIM_Try, /*On fail goto*//*Label 1934*/ GIMT_Encode4(91464), // Rule ID 4218 //
32183 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32184 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32185 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
32186 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32187 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32188 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32189 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32190 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32191 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
32192 // (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, 0:{ *:[i64] }), (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRHui (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
32193 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
32194 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32195 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32196 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Vt
32197 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
32198 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
32199 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHui),
32200 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32201 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32202 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
32203 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32204 GIR_RootConstrainSelectedInstOperands,
32205 // GIR_Coverage, 4218,
32206 GIR_EraseRootFromParent_Done,
32207 // Label 1934: @91464
32208 GIM_Try, /*On fail goto*//*Label 1935*/ GIMT_Encode4(91558), // Rule ID 4246 //
32209 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32210 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32211 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
32212 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32213 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32214 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32215 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32216 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32217 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
32218 // (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, 0:{ *:[i64] }), (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURHi (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
32219 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
32220 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32221 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32222 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Vt
32223 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
32224 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
32225 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHi),
32226 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32227 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32228 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
32229 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32230 GIR_RootConstrainSelectedInstOperands,
32231 // GIR_Coverage, 4246,
32232 GIR_EraseRootFromParent_Done,
32233 // Label 1935: @91558
32234 GIM_Try, /*On fail goto*//*Label 1936*/ GIMT_Encode4(91652), // Rule ID 12432 //
32235 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32236 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32237 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
32238 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32239 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
32240 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32241 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32242 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32243 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
32244 // (st (vector_extract:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, 0:{ *:[i64] }), (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRHui (EXTRACT_SUBREG:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
32245 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
32246 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32247 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32248 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Vt
32249 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
32250 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
32251 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHui),
32252 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32253 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32254 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
32255 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32256 GIR_RootConstrainSelectedInstOperands,
32257 // GIR_Coverage, 12432,
32258 GIR_EraseRootFromParent_Done,
32259 // Label 1936: @91652
32260 GIM_Try, /*On fail goto*//*Label 1937*/ GIMT_Encode4(91746), // Rule ID 12438 //
32261 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32262 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32263 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
32264 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32265 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
32266 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32267 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32268 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32269 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
32270 // (st (vector_extract:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, 0:{ *:[i64] }), (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURHi (EXTRACT_SUBREG:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
32271 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
32272 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32273 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32274 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Vt
32275 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
32276 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
32277 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHi),
32278 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32279 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32280 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
32281 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32282 GIR_RootConstrainSelectedInstOperands,
32283 // GIR_Coverage, 12438,
32284 GIR_EraseRootFromParent_Done,
32285 // Label 1937: @91746
32286 GIM_Try, /*On fail goto*//*Label 1938*/ GIMT_Encode4(91814), // Rule ID 6058 //
32287 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32288 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32289 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
32290 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32291 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32292 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
32293 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32294 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
32295 // MIs[2] Operand 1
32296 // No operand predicates
32297 // MIs[0] Rn
32298 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
32299 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
32300 GIM_CheckIsSafeToFold, /*NumInsns*/2,
32301 // (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i16 VecListOne128:{ *:[v8f16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
32302 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i16),
32303 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
32304 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
32305 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
32306 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
32307 GIR_RootConstrainSelectedInstOperands,
32308 // GIR_Coverage, 6058,
32309 GIR_EraseRootFromParent_Done,
32310 // Label 1938: @91814
32311 GIM_Try, /*On fail goto*//*Label 1939*/ GIMT_Encode4(91882), // Rule ID 6059 //
32312 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32313 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32314 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
32315 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32316 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32317 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
32318 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32319 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
32320 // MIs[2] Operand 1
32321 // No operand predicates
32322 // MIs[0] Rn
32323 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
32324 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
32325 GIM_CheckIsSafeToFold, /*NumInsns*/2,
32326 // (st (vector_extract:{ *:[bf16] } VecListOne128:{ *:[v8bf16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i16 VecListOne128:{ *:[v8bf16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
32327 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i16),
32328 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
32329 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
32330 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
32331 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
32332 GIR_RootConstrainSelectedInstOperands,
32333 // GIR_Coverage, 6059,
32334 GIR_EraseRootFromParent_Done,
32335 // Label 1939: @91882
32336 GIM_Try, /*On fail goto*//*Label 1940*/ GIMT_Encode4(91981), // Rule ID 6064 //
32337 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32338 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32339 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
32340 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32341 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
32342 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
32343 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32344 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
32345 // MIs[2] Operand 1
32346 // No operand predicates
32347 // MIs[0] Rn
32348 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
32349 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
32350 GIM_CheckIsSafeToFold, /*NumInsns*/2,
32351 // (st (vector_extract:{ *:[f16] } VecListOne64:{ *:[v4f16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i16 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4f16] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
32352 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
32353 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
32354 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32355 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
32356 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
32357 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
32358 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
32359 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
32360 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i16),
32361 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32362 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
32363 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
32364 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
32365 GIR_RootConstrainSelectedInstOperands,
32366 // GIR_Coverage, 6064,
32367 GIR_EraseRootFromParent_Done,
32368 // Label 1940: @91981
32369 GIM_Try, /*On fail goto*//*Label 1941*/ GIMT_Encode4(92080), // Rule ID 6065 //
32370 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32371 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32372 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
32373 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32374 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
32375 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
32376 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32377 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
32378 // MIs[2] Operand 1
32379 // No operand predicates
32380 // MIs[0] Rn
32381 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
32382 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
32383 GIM_CheckIsSafeToFold, /*NumInsns*/2,
32384 // (st (vector_extract:{ *:[bf16] } VecListOne64:{ *:[v4bf16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i16 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4bf16] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
32385 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
32386 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
32387 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32388 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
32389 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
32390 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
32391 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
32392 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
32393 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i16),
32394 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32395 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
32396 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
32397 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
32398 GIR_RootConstrainSelectedInstOperands,
32399 // GIR_Coverage, 6065,
32400 GIR_EraseRootFromParent_Done,
32401 // Label 1941: @92080
32402 GIM_Try, /*On fail goto*//*Label 1942*/ GIMT_Encode4(92129), // Rule ID 315 //
32403 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
32404 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
32405 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32406 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
32407 // (st FPR16Op:{ *:[f16] }:$Rt, (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRHroW FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
32408 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroW),
32409 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
32410 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32411 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
32412 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
32413 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
32414 GIR_RootConstrainSelectedInstOperands,
32415 // GIR_Coverage, 315,
32416 GIR_EraseRootFromParent_Done,
32417 // Label 1942: @92129
32418 GIM_Try, /*On fail goto*//*Label 1943*/ GIMT_Encode4(92178), // Rule ID 316 //
32419 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
32420 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
32421 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32422 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
32423 // (st FPR16Op:{ *:[f16] }:$Rt, (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRHroX FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
32424 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroX),
32425 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
32426 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32427 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
32428 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
32429 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
32430 GIR_RootConstrainSelectedInstOperands,
32431 // GIR_Coverage, 316,
32432 GIR_EraseRootFromParent_Done,
32433 // Label 1943: @92178
32434 GIM_Try, /*On fail goto*//*Label 1944*/ GIMT_Encode4(92222), // Rule ID 324 //
32435 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
32436 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
32437 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32438 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
32439 // (st FPR16Op:{ *:[f16] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRHui FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
32440 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHui),
32441 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
32442 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32443 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
32444 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
32445 GIR_RootConstrainSelectedInstOperands,
32446 // GIR_Coverage, 324,
32447 GIR_EraseRootFromParent_Done,
32448 // Label 1944: @92222
32449 GIM_Try, /*On fail goto*//*Label 1945*/ GIMT_Encode4(92266), // Rule ID 332 //
32450 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
32451 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
32452 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32453 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
32454 // (st FPR16Op:{ *:[f16] }:$Rt, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURHi FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
32455 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHi),
32456 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
32457 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32458 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
32459 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
32460 GIR_RootConstrainSelectedInstOperands,
32461 // GIR_Coverage, 332,
32462 GIR_EraseRootFromParent_Done,
32463 // Label 1945: @92266
32464 GIM_Try, /*On fail goto*//*Label 1946*/ GIMT_Encode4(92307), // Rule ID 4196 //
32465 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
32466 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32467 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
32468 // (st FPR16Op:{ *:[bf16] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRHui FPR16:{ *:[bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
32469 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHui),
32470 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
32471 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32472 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
32473 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
32474 GIR_RootConstrainSelectedInstOperands,
32475 // GIR_Coverage, 4196,
32476 GIR_EraseRootFromParent_Done,
32477 // Label 1946: @92307
32478 GIM_Try, /*On fail goto*//*Label 1947*/ GIMT_Encode4(92348), // Rule ID 4223 //
32479 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
32480 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32481 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
32482 // (st FPR16Op:{ *:[bf16] }:$Rt, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURHi FPR16:{ *:[bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
32483 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHi),
32484 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
32485 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32486 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
32487 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
32488 GIR_RootConstrainSelectedInstOperands,
32489 // GIR_Coverage, 4223,
32490 GIR_EraseRootFromParent_Done,
32491 // Label 1947: @92348
32492 GIM_Reject,
32493 // Label 1929: @92349
32494 GIM_Reject,
32495 // Label 1903: @92350
32496 GIM_Try, /*On fail goto*//*Label 1948*/ GIMT_Encode4(92456), // Rule ID 4188 //
32497 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
32498 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
32499 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32500 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32501 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
32502 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32503 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32504 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32505 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32506 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32507 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
32508 // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, 0:{ *:[i64] }), (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRSroW (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
32509 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32510 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32511 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32512 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Vt
32513 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
32514 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
32515 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroW),
32516 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32517 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32518 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
32519 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
32520 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32521 GIR_RootConstrainSelectedInstOperands,
32522 // GIR_Coverage, 4188,
32523 GIR_EraseRootFromParent_Done,
32524 // Label 1948: @92456
32525 GIM_Try, /*On fail goto*//*Label 1949*/ GIMT_Encode4(92562), // Rule ID 4189 //
32526 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
32527 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
32528 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32529 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32530 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
32531 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32532 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32533 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32534 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32535 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32536 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
32537 // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRSroX (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
32538 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32539 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32540 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32541 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Vt
32542 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
32543 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
32544 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroX),
32545 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32546 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32547 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
32548 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
32549 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32550 GIR_RootConstrainSelectedInstOperands,
32551 // GIR_Coverage, 4189,
32552 GIR_EraseRootFromParent_Done,
32553 // Label 1949: @92562
32554 GIM_Try, /*On fail goto*//*Label 1950*/ GIMT_Encode4(92668), // Rule ID 4190 //
32555 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
32556 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
32557 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32558 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32559 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
32560 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32561 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32562 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32563 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32564 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32565 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
32566 // (st (vector_extract:{ *:[f32] } VecListOne128:{ *:[v4f32] }:$Vt, 0:{ *:[i64] }), (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRSroW (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4f32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
32567 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32568 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32569 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32570 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Vt
32571 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
32572 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
32573 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroW),
32574 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32575 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32576 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
32577 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
32578 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32579 GIR_RootConstrainSelectedInstOperands,
32580 // GIR_Coverage, 4190,
32581 GIR_EraseRootFromParent_Done,
32582 // Label 1950: @92668
32583 GIM_Try, /*On fail goto*//*Label 1951*/ GIMT_Encode4(92774), // Rule ID 4191 //
32584 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
32585 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
32586 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32587 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32588 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
32589 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32590 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32591 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32592 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32593 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32594 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
32595 // (st (vector_extract:{ *:[f32] } VecListOne128:{ *:[v4f32] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRSroX (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4f32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
32596 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32597 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32598 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32599 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Vt
32600 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
32601 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
32602 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroX),
32603 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32604 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32605 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
32606 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
32607 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32608 GIR_RootConstrainSelectedInstOperands,
32609 // GIR_Coverage, 4191,
32610 GIR_EraseRootFromParent_Done,
32611 // Label 1951: @92774
32612 GIM_Try, /*On fail goto*//*Label 1952*/ GIMT_Encode4(92880), // Rule ID 12440 //
32613 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
32614 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
32615 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32616 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32617 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
32618 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32619 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
32620 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32621 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32622 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32623 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
32624 // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, 0:{ *:[i64] }), (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRSroW (EXTRACT_SUBREG:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
32625 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32626 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32627 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32628 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Vt
32629 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
32630 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
32631 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroW),
32632 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32633 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32634 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
32635 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
32636 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32637 GIR_RootConstrainSelectedInstOperands,
32638 // GIR_Coverage, 12440,
32639 GIR_EraseRootFromParent_Done,
32640 // Label 1952: @92880
32641 GIM_Try, /*On fail goto*//*Label 1953*/ GIMT_Encode4(92986), // Rule ID 12441 //
32642 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
32643 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
32644 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32645 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32646 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
32647 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32648 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
32649 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32650 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32651 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32652 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
32653 // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRSroX (EXTRACT_SUBREG:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
32654 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32655 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32656 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32657 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Vt
32658 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
32659 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
32660 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroX),
32661 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32662 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32663 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
32664 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
32665 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32666 GIR_RootConstrainSelectedInstOperands,
32667 // GIR_Coverage, 12441,
32668 GIR_EraseRootFromParent_Done,
32669 // Label 1953: @92986
32670 GIM_Try, /*On fail goto*//*Label 1954*/ GIMT_Encode4(93099), // Rule ID 4184 //
32671 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
32672 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
32673 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
32674 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32675 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32676 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
32677 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32678 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32679 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32680 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32681 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32682 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
32683 // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, 0:{ *:[i64] }), (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> => (STRHroW (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
32684 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
32685 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32686 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32687 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Vt
32688 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
32689 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
32690 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroW),
32691 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32692 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32693 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
32694 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
32695 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32696 GIR_RootConstrainSelectedInstOperands,
32697 // GIR_Coverage, 4184,
32698 GIR_EraseRootFromParent_Done,
32699 // Label 1954: @93099
32700 GIM_Try, /*On fail goto*//*Label 1955*/ GIMT_Encode4(93212), // Rule ID 4185 //
32701 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
32702 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
32703 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
32704 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32705 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32706 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
32707 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32708 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32709 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32710 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32711 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32712 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
32713 // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> => (STRHroX (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
32714 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
32715 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32716 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32717 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Vt
32718 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
32719 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
32720 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroX),
32721 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32722 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32723 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
32724 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
32725 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32726 GIR_RootConstrainSelectedInstOperands,
32727 // GIR_Coverage, 4185,
32728 GIR_EraseRootFromParent_Done,
32729 // Label 1955: @93212
32730 GIM_Try, /*On fail goto*//*Label 1956*/ GIMT_Encode4(93313), // Rule ID 4219 //
32731 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
32732 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
32733 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32734 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32735 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
32736 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32737 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32738 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32739 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32740 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32741 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
32742 // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, 0:{ *:[i64] }), (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRSui (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
32743 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32744 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32745 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32746 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Vt
32747 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
32748 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
32749 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSui),
32750 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32751 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32752 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
32753 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32754 GIR_RootConstrainSelectedInstOperands,
32755 // GIR_Coverage, 4219,
32756 GIR_EraseRootFromParent_Done,
32757 // Label 1956: @93313
32758 GIM_Try, /*On fail goto*//*Label 1957*/ GIMT_Encode4(93414), // Rule ID 4220 //
32759 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
32760 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
32761 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32762 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32763 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
32764 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32765 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32766 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32767 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32768 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32769 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
32770 // (st (vector_extract:{ *:[f32] } VecListOne128:{ *:[v4f32] }:$Vt, 0:{ *:[i64] }), (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRSui (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4f32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
32771 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32772 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32773 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32774 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Vt
32775 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
32776 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
32777 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSui),
32778 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32779 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32780 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
32781 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32782 GIR_RootConstrainSelectedInstOperands,
32783 // GIR_Coverage, 4220,
32784 GIR_EraseRootFromParent_Done,
32785 // Label 1957: @93414
32786 GIM_Try, /*On fail goto*//*Label 1958*/ GIMT_Encode4(93515), // Rule ID 4247 //
32787 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
32788 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
32789 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32790 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32791 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
32792 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32793 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32794 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32795 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32796 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32797 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
32798 // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, 0:{ *:[i64] }), (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURSi (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
32799 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32800 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32801 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32802 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Vt
32803 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
32804 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
32805 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURSi),
32806 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32807 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32808 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
32809 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32810 GIR_RootConstrainSelectedInstOperands,
32811 // GIR_Coverage, 4247,
32812 GIR_EraseRootFromParent_Done,
32813 // Label 1958: @93515
32814 GIM_Try, /*On fail goto*//*Label 1959*/ GIMT_Encode4(93616), // Rule ID 4248 //
32815 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
32816 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
32817 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32818 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32819 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
32820 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32821 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32822 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32823 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32824 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32825 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
32826 // (st (vector_extract:{ *:[f32] } VecListOne128:{ *:[v4f32] }:$Vt, 0:{ *:[i64] }), (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURSi (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4f32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
32827 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32828 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32829 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32830 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Vt
32831 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
32832 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
32833 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURSi),
32834 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32835 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32836 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
32837 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32838 GIR_RootConstrainSelectedInstOperands,
32839 // GIR_Coverage, 4248,
32840 GIR_EraseRootFromParent_Done,
32841 // Label 1959: @93616
32842 GIM_Try, /*On fail goto*//*Label 1960*/ GIMT_Encode4(93717), // Rule ID 12437 //
32843 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
32844 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
32845 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32846 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32847 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
32848 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32849 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
32850 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32851 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32852 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32853 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
32854 // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, 0:{ *:[i64] }), (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRSui (EXTRACT_SUBREG:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
32855 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32856 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32857 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32858 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Vt
32859 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
32860 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
32861 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSui),
32862 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32863 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32864 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
32865 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32866 GIR_RootConstrainSelectedInstOperands,
32867 // GIR_Coverage, 12437,
32868 GIR_EraseRootFromParent_Done,
32869 // Label 1960: @93717
32870 GIM_Try, /*On fail goto*//*Label 1961*/ GIMT_Encode4(93818), // Rule ID 12439 //
32871 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
32872 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
32873 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32874 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32875 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
32876 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32877 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
32878 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32879 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32880 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32881 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
32882 // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, 0:{ *:[i64] }), (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURSi (EXTRACT_SUBREG:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
32883 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
32884 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32885 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32886 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Vt
32887 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
32888 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
32889 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURSi),
32890 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32891 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32892 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
32893 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32894 GIR_RootConstrainSelectedInstOperands,
32895 // GIR_Coverage, 12439,
32896 GIR_EraseRootFromParent_Done,
32897 // Label 1961: @93818
32898 GIM_Try, /*On fail goto*//*Label 1962*/ GIMT_Encode4(93926), // Rule ID 4217 //
32899 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
32900 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
32901 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
32902 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32903 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32904 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
32905 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32906 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32907 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32908 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32909 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32910 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
32911 // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, 0:{ *:[i64] }), (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> => (STRHui (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
32912 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
32913 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32914 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32915 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Vt
32916 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
32917 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
32918 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHui),
32919 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32920 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32921 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
32922 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32923 GIR_RootConstrainSelectedInstOperands,
32924 // GIR_Coverage, 4217,
32925 GIR_EraseRootFromParent_Done,
32926 // Label 1962: @93926
32927 GIM_Try, /*On fail goto*//*Label 1963*/ GIMT_Encode4(94034), // Rule ID 4245 //
32928 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
32929 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
32930 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
32931 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32932 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32933 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
32934 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32935 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32936 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
32937 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
32938 GIM_CheckIsSafeToFold, /*NumInsns*/1,
32939 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
32940 // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, 0:{ *:[i64] }), (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> => (STURHi (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
32941 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
32942 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
32943 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
32944 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Vt
32945 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
32946 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
32947 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHi),
32948 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32949 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
32950 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
32951 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32952 GIR_RootConstrainSelectedInstOperands,
32953 // GIR_Coverage, 4245,
32954 GIR_EraseRootFromParent_Done,
32955 // Label 1963: @94034
32956 GIM_Try, /*On fail goto*//*Label 1964*/ GIMT_Encode4(94109), // Rule ID 6054 //
32957 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
32958 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
32959 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32960 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32961 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
32962 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32963 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32964 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
32965 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32966 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
32967 // MIs[2] Operand 1
32968 // No operand predicates
32969 // MIs[0] Rn
32970 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
32971 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
32972 GIM_CheckIsSafeToFold, /*NumInsns*/2,
32973 // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i32 VecListOne128:{ *:[v4i32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
32974 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i32),
32975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
32976 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
32977 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
32978 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
32979 GIR_RootConstrainSelectedInstOperands,
32980 // GIR_Coverage, 6054,
32981 GIR_EraseRootFromParent_Done,
32982 // Label 1964: @94109
32983 GIM_Try, /*On fail goto*//*Label 1965*/ GIMT_Encode4(94184), // Rule ID 6055 //
32984 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
32985 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
32986 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
32987 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
32988 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
32989 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
32990 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
32991 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
32992 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32993 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
32994 // MIs[2] Operand 1
32995 // No operand predicates
32996 // MIs[0] Rn
32997 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
32998 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
32999 GIM_CheckIsSafeToFold, /*NumInsns*/2,
33000 // (st (vector_extract:{ *:[f32] } VecListOne128:{ *:[v4f32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i32 VecListOne128:{ *:[v4f32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
33001 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i32),
33002 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
33003 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
33004 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
33005 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
33006 GIR_RootConstrainSelectedInstOperands,
33007 // GIR_Coverage, 6055,
33008 GIR_EraseRootFromParent_Done,
33009 // Label 1965: @94184
33010 GIM_Try, /*On fail goto*//*Label 1966*/ GIMT_Encode4(94290), // Rule ID 6062 //
33011 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33012 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33013 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
33014 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
33015 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
33016 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33017 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
33018 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
33019 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33020 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
33021 // MIs[2] Operand 1
33022 // No operand predicates
33023 // MIs[0] Rn
33024 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
33025 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
33026 GIM_CheckIsSafeToFold, /*NumInsns*/2,
33027 // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i32 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v2i32] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
33028 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
33029 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
33030 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33031 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
33032 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
33033 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
33034 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
33035 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
33036 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i32),
33037 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33038 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
33039 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
33040 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
33041 GIR_RootConstrainSelectedInstOperands,
33042 // GIR_Coverage, 6062,
33043 GIR_EraseRootFromParent_Done,
33044 // Label 1966: @94290
33045 GIM_Try, /*On fail goto*//*Label 1967*/ GIMT_Encode4(94396), // Rule ID 6063 //
33046 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33047 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33048 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
33049 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
33050 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
33051 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33052 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
33053 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
33054 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33055 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
33056 // MIs[2] Operand 1
33057 // No operand predicates
33058 // MIs[0] Rn
33059 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
33060 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
33061 GIM_CheckIsSafeToFold, /*NumInsns*/2,
33062 // (st (vector_extract:{ *:[f32] } VecListOne64:{ *:[v2f32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i32 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v2f32] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
33063 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
33064 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
33065 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33066 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
33067 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
33068 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
33069 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
33070 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
33071 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i32),
33072 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33073 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
33074 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
33075 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
33076 GIR_RootConstrainSelectedInstOperands,
33077 // GIR_Coverage, 6063,
33078 GIR_EraseRootFromParent_Done,
33079 // Label 1967: @94396
33080 GIM_Try, /*On fail goto*//*Label 1968*/ GIMT_Encode4(94478), // Rule ID 6052 //
33081 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33082 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
33083 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33084 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
33085 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
33086 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
33087 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33088 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
33089 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
33090 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33091 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
33092 // MIs[2] Operand 1
33093 // No operand predicates
33094 // MIs[0] Rn
33095 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
33096 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
33097 GIM_CheckIsSafeToFold, /*NumInsns*/2,
33098 // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v16i8] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> => (ST1i8 VecListOne128:{ *:[v16i8] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
33099 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i8),
33100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
33101 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
33102 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
33103 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
33104 GIR_RootConstrainSelectedInstOperands,
33105 // GIR_Coverage, 6052,
33106 GIR_EraseRootFromParent_Done,
33107 // Label 1968: @94478
33108 GIM_Try, /*On fail goto*//*Label 1969*/ GIMT_Encode4(94560), // Rule ID 6053 //
33109 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33110 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
33111 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33112 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
33113 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
33114 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
33115 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33116 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
33117 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
33118 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33119 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
33120 // MIs[2] Operand 1
33121 // No operand predicates
33122 // MIs[0] Rn
33123 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
33124 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
33125 GIM_CheckIsSafeToFold, /*NumInsns*/2,
33126 // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> => (ST1i16 VecListOne128:{ *:[v8i16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
33127 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i16),
33128 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
33129 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
33130 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
33131 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
33132 GIR_RootConstrainSelectedInstOperands,
33133 // GIR_Coverage, 6053,
33134 GIR_EraseRootFromParent_Done,
33135 // Label 1969: @94560
33136 GIM_Try, /*On fail goto*//*Label 1970*/ GIMT_Encode4(94673), // Rule ID 6060 //
33137 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33138 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
33139 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33140 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
33141 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
33142 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
33143 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33144 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
33145 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
33146 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33147 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
33148 // MIs[2] Operand 1
33149 // No operand predicates
33150 // MIs[0] Rn
33151 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
33152 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
33153 GIM_CheckIsSafeToFold, /*NumInsns*/2,
33154 // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v8i8] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> => (ST1i8 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v8i8] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
33155 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
33156 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
33157 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33158 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
33159 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
33160 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
33161 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
33162 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
33163 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i8),
33164 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33165 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
33166 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
33167 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
33168 GIR_RootConstrainSelectedInstOperands,
33169 // GIR_Coverage, 6060,
33170 GIR_EraseRootFromParent_Done,
33171 // Label 1970: @94673
33172 GIM_Try, /*On fail goto*//*Label 1971*/ GIMT_Encode4(94786), // Rule ID 6061 //
33173 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33174 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
33175 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33176 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
33177 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
33178 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
33179 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33180 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
33181 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
33182 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33183 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
33184 // MIs[2] Operand 1
33185 // No operand predicates
33186 // MIs[0] Rn
33187 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
33188 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
33189 GIM_CheckIsSafeToFold, /*NumInsns*/2,
33190 // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v4i16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> => (ST1i16 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4i16] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
33191 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
33192 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
33193 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33194 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
33195 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
33196 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
33197 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
33198 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
33199 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i16),
33200 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33201 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
33202 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
33203 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
33204 GIR_RootConstrainSelectedInstOperands,
33205 // GIR_Coverage, 6061,
33206 GIR_EraseRootFromParent_Done,
33207 // Label 1971: @94786
33208 GIM_Try, /*On fail goto*//*Label 1972*/ GIMT_Encode4(94839), // Rule ID 309 //
33209 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33210 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33211 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33212 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33213 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
33214 // (st GPR32:{ *:[i32] }:$Rt, (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRWroW GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
33215 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWroW),
33216 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
33217 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33218 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33219 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33220 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33221 GIR_RootConstrainSelectedInstOperands,
33222 // GIR_Coverage, 309,
33223 GIR_EraseRootFromParent_Done,
33224 // Label 1972: @94839
33225 GIM_Try, /*On fail goto*//*Label 1973*/ GIMT_Encode4(94892), // Rule ID 310 //
33226 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33227 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33228 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33229 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33230 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
33231 // (st GPR32:{ *:[i32] }:$Rt, (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRWroX GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
33232 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWroX),
33233 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
33234 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33235 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33236 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33237 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33238 GIR_RootConstrainSelectedInstOperands,
33239 // GIR_Coverage, 310,
33240 GIR_EraseRootFromParent_Done,
33241 // Label 1973: @94892
33242 GIM_Try, /*On fail goto*//*Label 1974*/ GIMT_Encode4(94948), // Rule ID 317 //
33243 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
33244 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33245 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33246 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
33247 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33248 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
33249 // (st FPR32Op:{ *:[f32] }:$Rt, (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRSroW FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
33250 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroW),
33251 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
33252 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33253 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33254 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33255 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33256 GIR_RootConstrainSelectedInstOperands,
33257 // GIR_Coverage, 317,
33258 GIR_EraseRootFromParent_Done,
33259 // Label 1974: @94948
33260 GIM_Try, /*On fail goto*//*Label 1975*/ GIMT_Encode4(95004), // Rule ID 318 //
33261 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
33262 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33263 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33264 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
33265 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33266 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
33267 // (st FPR32Op:{ *:[f32] }:$Rt, (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRSroX FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
33268 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroX),
33269 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
33270 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33271 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33272 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33273 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33274 GIR_RootConstrainSelectedInstOperands,
33275 // GIR_Coverage, 318,
33276 GIR_EraseRootFromParent_Done,
33277 // Label 1975: @95004
33278 GIM_Try, /*On fail goto*//*Label 1976*/ GIMT_Encode4(95064), // Rule ID 305 //
33279 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33280 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
33281 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33282 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33283 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33284 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
33285 // (st GPR32:{ *:[i32] }:$Rt, (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> => (STRBBroW GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
33286 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBroW),
33287 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
33288 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33289 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33290 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33291 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33292 GIR_RootConstrainSelectedInstOperands,
33293 // GIR_Coverage, 305,
33294 GIR_EraseRootFromParent_Done,
33295 // Label 1976: @95064
33296 GIM_Try, /*On fail goto*//*Label 1977*/ GIMT_Encode4(95124), // Rule ID 306 //
33297 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33298 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
33299 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33300 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33301 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33302 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
33303 // (st GPR32:{ *:[i32] }:$Rt, (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> => (STRBBroX GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
33304 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBroX),
33305 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
33306 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33307 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33308 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33309 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33310 GIR_RootConstrainSelectedInstOperands,
33311 // GIR_Coverage, 306,
33312 GIR_EraseRootFromParent_Done,
33313 // Label 1977: @95124
33314 GIM_Try, /*On fail goto*//*Label 1978*/ GIMT_Encode4(95184), // Rule ID 307 //
33315 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33316 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
33317 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33318 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33319 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33320 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
33321 // (st GPR32:{ *:[i32] }:$Rt, (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> => (STRHHroW GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
33322 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHroW),
33323 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
33324 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33325 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33326 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33327 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33328 GIR_RootConstrainSelectedInstOperands,
33329 // GIR_Coverage, 307,
33330 GIR_EraseRootFromParent_Done,
33331 // Label 1978: @95184
33332 GIM_Try, /*On fail goto*//*Label 1979*/ GIMT_Encode4(95244), // Rule ID 308 //
33333 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33334 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
33335 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33336 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33337 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33338 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
33339 // (st GPR32:{ *:[i32] }:$Rt, (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> => (STRHHroX GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
33340 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHroX),
33341 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
33342 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33343 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33344 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33345 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33346 GIR_RootConstrainSelectedInstOperands,
33347 // GIR_Coverage, 308,
33348 GIR_EraseRootFromParent_Done,
33349 // Label 1979: @95244
33350 GIM_Try, /*On fail goto*//*Label 1980*/ GIMT_Encode4(95296), // Rule ID 322 //
33351 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33352 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33353 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33354 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33355 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
33356 // (st GPR32z:{ *:[i32] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRWui GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
33357 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWui),
33358 GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::WZR), // Rt
33359 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33360 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
33361 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33362 GIR_RootConstrainSelectedInstOperands,
33363 // GIR_Coverage, 322,
33364 GIR_EraseRootFromParent_Done,
33365 // Label 1980: @95296
33366 GIM_Try, /*On fail goto*//*Label 1981*/ GIMT_Encode4(95347), // Rule ID 325 //
33367 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
33368 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33369 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33370 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
33371 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33372 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
33373 // (st FPR32Op:{ *:[f32] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRSui FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
33374 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSui),
33375 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
33376 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33377 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
33378 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33379 GIR_RootConstrainSelectedInstOperands,
33380 // GIR_Coverage, 325,
33381 GIR_EraseRootFromParent_Done,
33382 // Label 1981: @95347
33383 GIM_Try, /*On fail goto*//*Label 1982*/ GIMT_Encode4(95406), // Rule ID 327 //
33384 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33385 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
33386 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33387 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33388 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33389 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
33390 // (st GPR32z:{ *:[i32] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> => (STRHHui GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
33391 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHui),
33392 GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::WZR), // Rt
33393 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33394 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
33395 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33396 GIR_RootConstrainSelectedInstOperands,
33397 // GIR_Coverage, 327,
33398 GIR_EraseRootFromParent_Done,
33399 // Label 1982: @95406
33400 GIM_Try, /*On fail goto*//*Label 1983*/ GIMT_Encode4(95465), // Rule ID 328 //
33401 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33402 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
33403 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33404 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33405 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33406 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
33407 // (st GPR32z:{ *:[i32] }:$Rt, (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> => (STRBBui GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
33408 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBui),
33409 GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::WZR), // Rt
33410 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33411 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
33412 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33413 GIR_RootConstrainSelectedInstOperands,
33414 // GIR_Coverage, 328,
33415 GIR_EraseRootFromParent_Done,
33416 // Label 1983: @95465
33417 GIM_Try, /*On fail goto*//*Label 1984*/ GIMT_Encode4(95542), // Rule ID 6810 //
33418 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
33419 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33420 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33421 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
33422 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
33423 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
33424 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
33425 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33426 GIM_CheckIsSafeToFold, /*NumInsns*/1,
33427 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
33428 // (atomic_store (bitconvert:{ *:[i32] } FPR32Op:{ *:[f32] }:$val), (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_14629>> => (STRSroW FPR32Op:{ *:[f32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
33429 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroW),
33430 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
33431 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33432 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33433 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33434 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33435 GIR_RootConstrainSelectedInstOperands,
33436 // GIR_Coverage, 6810,
33437 GIR_EraseRootFromParent_Done,
33438 // Label 1984: @95542
33439 GIM_Try, /*On fail goto*//*Label 1985*/ GIMT_Encode4(95619), // Rule ID 6811 //
33440 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
33441 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33442 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33443 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
33444 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
33445 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
33446 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
33447 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33448 GIM_CheckIsSafeToFold, /*NumInsns*/1,
33449 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
33450 // (atomic_store (bitconvert:{ *:[i32] } FPR32Op:{ *:[f32] }:$val), (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_14629>> => (STRSroX FPR32Op:{ *:[f32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
33451 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroX),
33452 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
33453 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33454 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33455 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33456 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33457 GIR_RootConstrainSelectedInstOperands,
33458 // GIR_Coverage, 6811,
33459 GIR_EraseRootFromParent_Done,
33460 // Label 1985: @95619
33461 GIM_Try, /*On fail goto*//*Label 1986*/ GIMT_Encode4(95678), // Rule ID 6791 //
33462 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
33463 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33464 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33465 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33466 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33467 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
33468 // (atomic_store GPR32:{ *:[i32] }:$val, (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_14615>> => (STRBBroW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
33469 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBroW),
33470 GIR_RootToRootCopy, /*OpIdx*/0, // val
33471 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33472 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33473 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33474 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33475 GIR_RootConstrainSelectedInstOperands,
33476 // GIR_Coverage, 6791,
33477 GIR_EraseRootFromParent_Done,
33478 // Label 1986: @95678
33479 GIM_Try, /*On fail goto*//*Label 1987*/ GIMT_Encode4(95737), // Rule ID 6792 //
33480 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
33481 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33482 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33483 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33484 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33485 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
33486 // (atomic_store GPR32:{ *:[i32] }:$val, (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_14615>> => (STRBBroX GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
33487 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBroX),
33488 GIR_RootToRootCopy, /*OpIdx*/0, // val
33489 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33490 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33491 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33492 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33493 GIR_RootConstrainSelectedInstOperands,
33494 // GIR_Coverage, 6792,
33495 GIR_EraseRootFromParent_Done,
33496 // Label 1987: @95737
33497 GIM_Try, /*On fail goto*//*Label 1988*/ GIMT_Encode4(95796), // Rule ID 6796 //
33498 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
33499 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33500 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33502 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33503 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
33504 // (atomic_store GPR32:{ *:[i32] }:$val, (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_14622>> => (STRHHroW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
33505 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHroW),
33506 GIR_RootToRootCopy, /*OpIdx*/0, // val
33507 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33508 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33509 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33510 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33511 GIR_RootConstrainSelectedInstOperands,
33512 // GIR_Coverage, 6796,
33513 GIR_EraseRootFromParent_Done,
33514 // Label 1988: @95796
33515 GIM_Try, /*On fail goto*//*Label 1989*/ GIMT_Encode4(95855), // Rule ID 6797 //
33516 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
33517 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33518 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33519 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33520 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33521 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
33522 // (atomic_store GPR32:{ *:[i32] }:$val, (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_14622>> => (STRHHroX GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
33523 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHroX),
33524 GIR_RootToRootCopy, /*OpIdx*/0, // val
33525 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33526 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33527 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33528 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33529 GIR_RootConstrainSelectedInstOperands,
33530 // GIR_Coverage, 6797,
33531 GIR_EraseRootFromParent_Done,
33532 // Label 1989: @95855
33533 GIM_Try, /*On fail goto*//*Label 1990*/ GIMT_Encode4(95914), // Rule ID 6801 //
33534 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
33535 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33536 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33537 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33538 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33539 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
33540 // (atomic_store GPR32:{ *:[i32] }:$val, (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_14629>> => (STRWroW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
33541 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWroW),
33542 GIR_RootToRootCopy, /*OpIdx*/0, // val
33543 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33544 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33545 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33546 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33547 GIR_RootConstrainSelectedInstOperands,
33548 // GIR_Coverage, 6801,
33549 GIR_EraseRootFromParent_Done,
33550 // Label 1990: @95914
33551 GIM_Try, /*On fail goto*//*Label 1991*/ GIMT_Encode4(95973), // Rule ID 6802 //
33552 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
33553 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33554 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33555 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33556 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33557 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
33558 // (atomic_store GPR32:{ *:[i32] }:$val, (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_14629>> => (STRWroX GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
33559 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWroX),
33560 GIR_RootToRootCopy, /*OpIdx*/0, // val
33561 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33562 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33563 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33564 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33565 GIR_RootConstrainSelectedInstOperands,
33566 // GIR_Coverage, 6802,
33567 GIR_EraseRootFromParent_Done,
33568 // Label 1991: @95973
33569 GIM_Try, /*On fail goto*//*Label 1992*/ GIMT_Encode4(96045), // Rule ID 6812 //
33570 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
33571 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33572 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33573 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
33574 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
33575 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
33576 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
33577 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33578 GIM_CheckIsSafeToFold, /*NumInsns*/1,
33579 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
33580 // (atomic_store (bitconvert:{ *:[i32] } FPR32Op:{ *:[f32] }:$val), (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_14629>> => (STRSui FPR32Op:{ *:[f32] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
33581 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSui),
33582 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
33583 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33584 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
33585 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33586 GIR_RootConstrainSelectedInstOperands,
33587 // GIR_Coverage, 6812,
33588 GIR_EraseRootFromParent_Done,
33589 // Label 1992: @96045
33590 GIM_Try, /*On fail goto*//*Label 1993*/ GIMT_Encode4(96117), // Rule ID 6813 //
33591 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
33592 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33593 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33594 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
33595 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
33596 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
33597 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
33598 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33599 GIM_CheckIsSafeToFold, /*NumInsns*/1,
33600 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
33601 // (atomic_store (bitconvert:{ *:[i32] } FPR32Op:{ *:[f32] }:$val), (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_14629>> => (STURSi FPR32Op:{ *:[f32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
33602 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURSi),
33603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
33604 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33605 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
33606 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33607 GIR_RootConstrainSelectedInstOperands,
33608 // GIR_Coverage, 6813,
33609 GIR_EraseRootFromParent_Done,
33610 // Label 1993: @96117
33611 GIM_Try, /*On fail goto*//*Label 1994*/ GIMT_Encode4(96169), // Rule ID 330 //
33612 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33613 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33614 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33615 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33616 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
33617 // (st GPR32z:{ *:[i32] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURWi GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
33618 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURWi),
33619 GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::WZR), // Rt
33620 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33621 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
33622 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33623 GIR_RootConstrainSelectedInstOperands,
33624 // GIR_Coverage, 330,
33625 GIR_EraseRootFromParent_Done,
33626 // Label 1994: @96169
33627 GIM_Try, /*On fail goto*//*Label 1995*/ GIMT_Encode4(96220), // Rule ID 333 //
33628 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
33629 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33630 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33631 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
33632 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33633 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
33634 // (st FPR32Op:{ *:[f32] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURSi FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
33635 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURSi),
33636 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
33637 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33638 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
33639 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33640 GIR_RootConstrainSelectedInstOperands,
33641 // GIR_Coverage, 333,
33642 GIR_EraseRootFromParent_Done,
33643 // Label 1995: @96220
33644 GIM_Try, /*On fail goto*//*Label 1996*/ GIMT_Encode4(96279), // Rule ID 336 //
33645 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33646 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
33647 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33648 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33649 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33650 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
33651 // (st GPR32z:{ *:[i32] }:$Rt, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> => (STURHHi GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
33652 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHHi),
33653 GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::WZR), // Rt
33654 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33655 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
33656 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33657 GIR_RootConstrainSelectedInstOperands,
33658 // GIR_Coverage, 336,
33659 GIR_EraseRootFromParent_Done,
33660 // Label 1996: @96279
33661 GIM_Try, /*On fail goto*//*Label 1997*/ GIMT_Encode4(96338), // Rule ID 337 //
33662 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33663 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
33664 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33665 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33666 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33667 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
33668 // (st GPR32z:{ *:[i32] }:$Rt, (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> => (STURBBi GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
33669 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURBBi),
33670 GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::WZR), // Rt
33671 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33672 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
33673 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33674 GIR_RootConstrainSelectedInstOperands,
33675 // GIR_Coverage, 337,
33676 GIR_EraseRootFromParent_Done,
33677 // Label 1997: @96338
33678 GIM_Try, /*On fail goto*//*Label 1998*/ GIMT_Encode4(96392), // Rule ID 6793 //
33679 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
33680 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33681 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33682 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33683 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33684 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
33685 // (atomic_store GPR32:{ *:[i32] }:$val, (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_14615>> => (STRBBui GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
33686 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBui),
33687 GIR_RootToRootCopy, /*OpIdx*/0, // val
33688 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33689 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
33690 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33691 GIR_RootConstrainSelectedInstOperands,
33692 // GIR_Coverage, 6793,
33693 GIR_EraseRootFromParent_Done,
33694 // Label 1998: @96392
33695 GIM_Try, /*On fail goto*//*Label 1999*/ GIMT_Encode4(96446), // Rule ID 6794 //
33696 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
33697 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33698 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33699 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33700 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33701 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
33702 // (atomic_store GPR32:{ *:[i32] }:$val, (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_14615>> => (STURBBi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
33703 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURBBi),
33704 GIR_RootToRootCopy, /*OpIdx*/0, // val
33705 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33706 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
33707 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33708 GIR_RootConstrainSelectedInstOperands,
33709 // GIR_Coverage, 6794,
33710 GIR_EraseRootFromParent_Done,
33711 // Label 1999: @96446
33712 GIM_Try, /*On fail goto*//*Label 2000*/ GIMT_Encode4(96500), // Rule ID 6798 //
33713 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
33714 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33715 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33716 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33717 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33718 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
33719 // (atomic_store GPR32:{ *:[i32] }:$val, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_14622>> => (STRHHui GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
33720 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHui),
33721 GIR_RootToRootCopy, /*OpIdx*/0, // val
33722 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33723 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
33724 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33725 GIR_RootConstrainSelectedInstOperands,
33726 // GIR_Coverage, 6798,
33727 GIR_EraseRootFromParent_Done,
33728 // Label 2000: @96500
33729 GIM_Try, /*On fail goto*//*Label 2001*/ GIMT_Encode4(96554), // Rule ID 6799 //
33730 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
33731 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33732 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33733 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33734 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33735 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
33736 // (atomic_store GPR32:{ *:[i32] }:$val, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_14622>> => (STURHHi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
33737 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHHi),
33738 GIR_RootToRootCopy, /*OpIdx*/0, // val
33739 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33740 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
33741 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33742 GIR_RootConstrainSelectedInstOperands,
33743 // GIR_Coverage, 6799,
33744 GIR_EraseRootFromParent_Done,
33745 // Label 2001: @96554
33746 GIM_Try, /*On fail goto*//*Label 2002*/ GIMT_Encode4(96608), // Rule ID 6803 //
33747 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
33748 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33749 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33750 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33751 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33752 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
33753 // (atomic_store GPR32:{ *:[i32] }:$val, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_14629>> => (STRWui GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
33754 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWui),
33755 GIR_RootToRootCopy, /*OpIdx*/0, // val
33756 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33757 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
33758 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33759 GIR_RootConstrainSelectedInstOperands,
33760 // GIR_Coverage, 6803,
33761 GIR_EraseRootFromParent_Done,
33762 // Label 2002: @96608
33763 GIM_Try, /*On fail goto*//*Label 2003*/ GIMT_Encode4(96662), // Rule ID 6804 //
33764 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
33765 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33766 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33767 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33768 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33769 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
33770 // (atomic_store GPR32:{ *:[i32] }:$val, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_14629>> => (STURWi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
33771 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURWi),
33772 GIR_RootToRootCopy, /*OpIdx*/0, // val
33773 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33774 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
33775 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33776 GIR_RootConstrainSelectedInstOperands,
33777 // GIR_Coverage, 6804,
33778 GIR_EraseRootFromParent_Done,
33779 // Label 2003: @96662
33780 GIM_Try, /*On fail goto*//*Label 2004*/ GIMT_Encode4(96719), // Rule ID 7096 //
33781 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO),
33782 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
33783 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33784 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33785 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33786 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33787 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
33788 // (atomic_store GPR32:{ *:[i32] }:$val, (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_14613>> => (STLURBi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
33789 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLURBi),
33790 GIR_RootToRootCopy, /*OpIdx*/0, // val
33791 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33792 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
33793 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33794 GIR_RootConstrainSelectedInstOperands,
33795 // GIR_Coverage, 7096,
33796 GIR_EraseRootFromParent_Done,
33797 // Label 2004: @96719
33798 GIM_Try, /*On fail goto*//*Label 2005*/ GIMT_Encode4(96776), // Rule ID 7097 //
33799 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO),
33800 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
33801 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33802 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33803 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33804 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33805 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
33806 // (atomic_store GPR32:{ *:[i32] }:$val, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_14620>> => (STLURHi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
33807 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLURHi),
33808 GIR_RootToRootCopy, /*OpIdx*/0, // val
33809 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33810 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
33811 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33812 GIR_RootConstrainSelectedInstOperands,
33813 // GIR_Coverage, 7097,
33814 GIR_EraseRootFromParent_Done,
33815 // Label 2005: @96776
33816 GIM_Try, /*On fail goto*//*Label 2006*/ GIMT_Encode4(96833), // Rule ID 7098 //
33817 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO),
33818 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
33819 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33820 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33821 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33822 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33823 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
33824 // (atomic_store GPR32:{ *:[i32] }:$val, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_14627>> => (STLURWi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
33825 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLURWi),
33826 GIR_RootToRootCopy, /*OpIdx*/0, // val
33827 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33828 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
33829 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33830 GIR_RootConstrainSelectedInstOperands,
33831 // GIR_Coverage, 7098,
33832 GIR_EraseRootFromParent_Done,
33833 // Label 2006: @96833
33834 GIM_Try, /*On fail goto*//*Label 2007*/ GIMT_Encode4(96870), // Rule ID 6790 //
33835 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
33836 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33837 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33838 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33839 // MIs[0] ptr
33840 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
33841 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
33842 // (atomic_store GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_14613>> => (STLRB GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr)
33843 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::STLRB),
33844 GIR_RootConstrainSelectedInstOperands,
33845 // GIR_Coverage, 6790,
33846 GIR_Done,
33847 // Label 2007: @96870
33848 GIM_Try, /*On fail goto*//*Label 2008*/ GIMT_Encode4(96907), // Rule ID 6795 //
33849 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
33850 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33851 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33852 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33853 // MIs[0] ptr
33854 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
33855 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
33856 // (atomic_store GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_14620>> => (STLRH GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr)
33857 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::STLRH),
33858 GIR_RootConstrainSelectedInstOperands,
33859 // GIR_Coverage, 6795,
33860 GIR_Done,
33861 // Label 2008: @96907
33862 GIM_Try, /*On fail goto*//*Label 2009*/ GIMT_Encode4(96944), // Rule ID 6800 //
33863 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
33864 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
33865 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
33866 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
33867 // MIs[0] ptr
33868 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
33869 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
33870 // (atomic_store GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_14627>> => (STLRW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr)
33871 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::STLRW),
33872 GIR_RootConstrainSelectedInstOperands,
33873 // GIR_Coverage, 6800,
33874 GIR_Done,
33875 // Label 2009: @96944
33876 GIM_Reject,
33877 // Label 1904: @96945
33878 GIM_Try, /*On fail goto*//*Label 2010*/ GIMT_Encode4(97051), // Rule ID 4192 //
33879 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33880 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33881 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
33882 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
33883 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
33884 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33885 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
33886 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
33887 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33888 GIM_CheckIsSafeToFold, /*NumInsns*/1,
33889 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
33890 // (st (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, 0:{ *:[i64] }), (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
33891 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
33892 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33893 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33894 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Vt
33895 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
33896 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
33897 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
33898 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33899 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33900 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33901 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33902 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33903 GIR_RootConstrainSelectedInstOperands,
33904 // GIR_Coverage, 4192,
33905 GIR_EraseRootFromParent_Done,
33906 // Label 2010: @97051
33907 GIM_Try, /*On fail goto*//*Label 2011*/ GIMT_Encode4(97157), // Rule ID 4193 //
33908 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33909 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33910 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
33911 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
33912 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
33913 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33914 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
33915 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
33916 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33917 GIM_CheckIsSafeToFold, /*NumInsns*/1,
33918 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
33919 // (st (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
33920 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
33921 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33922 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33923 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Vt
33924 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
33925 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
33926 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
33927 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33928 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33929 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33930 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33931 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33932 GIR_RootConstrainSelectedInstOperands,
33933 // GIR_Coverage, 4193,
33934 GIR_EraseRootFromParent_Done,
33935 // Label 2011: @97157
33936 GIM_Try, /*On fail goto*//*Label 2012*/ GIMT_Encode4(97263), // Rule ID 4194 //
33937 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33938 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33939 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
33940 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
33941 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
33942 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33943 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
33944 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
33945 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33946 GIM_CheckIsSafeToFold, /*NumInsns*/1,
33947 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
33948 // (st (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, 0:{ *:[i64] }), (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2f64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
33949 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
33950 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33951 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33952 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Vt
33953 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
33954 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
33955 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
33956 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33957 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33958 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33959 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33960 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33961 GIR_RootConstrainSelectedInstOperands,
33962 // GIR_Coverage, 4194,
33963 GIR_EraseRootFromParent_Done,
33964 // Label 2012: @97263
33965 GIM_Try, /*On fail goto*//*Label 2013*/ GIMT_Encode4(97369), // Rule ID 4195 //
33966 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33967 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33968 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
33969 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
33970 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
33971 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
33972 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
33973 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
33974 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
33975 GIM_CheckIsSafeToFold, /*NumInsns*/1,
33976 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
33977 // (st (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2f64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
33978 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
33979 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
33980 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
33981 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Vt
33982 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
33983 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
33984 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
33985 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33986 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
33987 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
33988 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
33989 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33990 GIR_RootConstrainSelectedInstOperands,
33991 // GIR_Coverage, 4195,
33992 GIR_EraseRootFromParent_Done,
33993 // Label 2013: @97369
33994 GIM_Try, /*On fail goto*//*Label 2014*/ GIMT_Encode4(97470), // Rule ID 4221 //
33995 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
33996 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
33997 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
33998 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
33999 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
34000 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
34001 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
34002 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
34003 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34004 GIM_CheckIsSafeToFold, /*NumInsns*/1,
34005 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
34006 // (st (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, 0:{ *:[i64] }), (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
34007 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
34008 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34009 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34010 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Vt
34011 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
34012 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
34013 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
34014 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34015 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34016 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34017 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
34018 GIR_RootConstrainSelectedInstOperands,
34019 // GIR_Coverage, 4221,
34020 GIR_EraseRootFromParent_Done,
34021 // Label 2014: @97470
34022 GIM_Try, /*On fail goto*//*Label 2015*/ GIMT_Encode4(97571), // Rule ID 4222 //
34023 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34024 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34025 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
34026 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
34027 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
34028 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
34029 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
34030 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
34031 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34032 GIM_CheckIsSafeToFold, /*NumInsns*/1,
34033 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
34034 // (st (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, 0:{ *:[i64] }), (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2f64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
34035 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
34036 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34037 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34038 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Vt
34039 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
34040 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
34041 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
34042 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34043 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34044 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34045 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
34046 GIR_RootConstrainSelectedInstOperands,
34047 // GIR_Coverage, 4222,
34048 GIR_EraseRootFromParent_Done,
34049 // Label 2015: @97571
34050 GIM_Try, /*On fail goto*//*Label 2016*/ GIMT_Encode4(97672), // Rule ID 4249 //
34051 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34052 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34053 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
34054 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
34055 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
34056 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
34057 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
34058 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
34059 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34060 GIM_CheckIsSafeToFold, /*NumInsns*/1,
34061 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
34062 // (st (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, 0:{ *:[i64] }), (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
34063 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
34064 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34065 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34066 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Vt
34067 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
34068 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
34069 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
34070 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34071 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34072 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34073 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
34074 GIR_RootConstrainSelectedInstOperands,
34075 // GIR_Coverage, 4249,
34076 GIR_EraseRootFromParent_Done,
34077 // Label 2016: @97672
34078 GIM_Try, /*On fail goto*//*Label 2017*/ GIMT_Encode4(97773), // Rule ID 4250 //
34079 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34080 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34081 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
34082 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
34083 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
34084 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
34085 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
34086 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
34087 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34088 GIM_CheckIsSafeToFold, /*NumInsns*/1,
34089 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
34090 // (st (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, 0:{ *:[i64] }), (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2f64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
34091 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
34092 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34093 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34094 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Vt
34095 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
34096 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
34097 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
34098 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34099 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34100 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34101 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
34102 GIR_RootConstrainSelectedInstOperands,
34103 // GIR_Coverage, 4250,
34104 GIR_EraseRootFromParent_Done,
34105 // Label 2017: @97773
34106 GIM_Try, /*On fail goto*//*Label 2018*/ GIMT_Encode4(97848), // Rule ID 6056 //
34107 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34108 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34109 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
34110 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
34111 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
34112 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
34113 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
34114 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
34115 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34116 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
34117 // MIs[2] Operand 1
34118 // No operand predicates
34119 // MIs[0] Rn
34120 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
34121 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
34122 GIM_CheckIsSafeToFold, /*NumInsns*/2,
34123 // (st (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i64 VecListOne128:{ *:[v2i64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
34124 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i64),
34125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
34126 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
34127 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
34128 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
34129 GIR_RootConstrainSelectedInstOperands,
34130 // GIR_Coverage, 6056,
34131 GIR_EraseRootFromParent_Done,
34132 // Label 2018: @97848
34133 GIM_Try, /*On fail goto*//*Label 2019*/ GIMT_Encode4(97923), // Rule ID 6057 //
34134 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34135 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34136 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
34137 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
34138 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
34139 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
34140 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
34141 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
34142 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34143 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
34144 // MIs[2] Operand 1
34145 // No operand predicates
34146 // MIs[0] Rn
34147 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
34148 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
34149 GIM_CheckIsSafeToFold, /*NumInsns*/2,
34150 // (st (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1i64 VecListOne128:{ *:[v2f64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
34151 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i64),
34152 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
34153 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
34154 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
34155 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
34156 GIR_RootConstrainSelectedInstOperands,
34157 // GIR_Coverage, 6057,
34158 GIR_EraseRootFromParent_Done,
34159 // Label 2019: @97923
34160 GIM_Try, /*On fail goto*//*Label 2020*/ GIMT_Encode4(97976), // Rule ID 311 //
34161 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34162 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34163 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34164 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34165 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
34166 // (st GPR64:{ *:[i64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRXroW GPR64:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
34167 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRXroW),
34168 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
34169 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34170 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
34171 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
34172 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34173 GIR_RootConstrainSelectedInstOperands,
34174 // GIR_Coverage, 311,
34175 GIR_EraseRootFromParent_Done,
34176 // Label 2020: @97976
34177 GIM_Try, /*On fail goto*//*Label 2021*/ GIMT_Encode4(98029), // Rule ID 312 //
34178 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34179 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34180 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34181 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34182 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
34183 // (st GPR64:{ *:[i64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRXroX GPR64:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
34184 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRXroX),
34185 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
34186 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34187 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
34188 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
34189 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34190 GIR_RootConstrainSelectedInstOperands,
34191 // GIR_Coverage, 312,
34192 GIR_EraseRootFromParent_Done,
34193 // Label 2021: @98029
34194 GIM_Try, /*On fail goto*//*Label 2022*/ GIMT_Encode4(98085), // Rule ID 319 //
34195 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
34196 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34197 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34198 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
34199 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34200 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
34201 // (st FPR64Op:{ *:[f64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
34202 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
34203 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
34204 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34205 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
34206 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
34207 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34208 GIR_RootConstrainSelectedInstOperands,
34209 // GIR_Coverage, 319,
34210 GIR_EraseRootFromParent_Done,
34211 // Label 2022: @98085
34212 GIM_Try, /*On fail goto*//*Label 2023*/ GIMT_Encode4(98141), // Rule ID 320 //
34213 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
34214 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34215 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34216 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
34217 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34218 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
34219 // (st FPR64Op:{ *:[f64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
34220 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
34221 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
34222 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34223 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
34224 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
34225 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34226 GIR_RootConstrainSelectedInstOperands,
34227 // GIR_Coverage, 320,
34228 GIR_EraseRootFromParent_Done,
34229 // Label 2023: @98141
34230 GIM_Try, /*On fail goto*//*Label 2024*/ GIMT_Encode4(98194), // Rule ID 4164 //
34231 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34232 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34233 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
34234 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34235 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
34236 // (st FPR64:{ *:[v1i64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
34237 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
34238 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
34239 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34240 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
34241 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
34242 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34243 GIR_RootConstrainSelectedInstOperands,
34244 // GIR_Coverage, 4164,
34245 GIR_EraseRootFromParent_Done,
34246 // Label 2024: @98194
34247 GIM_Try, /*On fail goto*//*Label 2025*/ GIMT_Encode4(98247), // Rule ID 4165 //
34248 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34249 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34250 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
34251 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34252 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
34253 // (st FPR64:{ *:[v1i64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
34254 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
34255 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
34256 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34257 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
34258 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
34259 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34260 GIR_RootConstrainSelectedInstOperands,
34261 // GIR_Coverage, 4165,
34262 GIR_EraseRootFromParent_Done,
34263 // Label 2025: @98247
34264 GIM_Try, /*On fail goto*//*Label 2026*/ GIMT_Encode4(98300), // Rule ID 4166 //
34265 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34266 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34267 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
34268 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34269 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
34270 // (st FPR64:{ *:[v1f64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
34271 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
34272 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
34273 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34274 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
34275 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
34276 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34277 GIR_RootConstrainSelectedInstOperands,
34278 // GIR_Coverage, 4166,
34279 GIR_EraseRootFromParent_Done,
34280 // Label 2026: @98300
34281 GIM_Try, /*On fail goto*//*Label 2027*/ GIMT_Encode4(98353), // Rule ID 4167 //
34282 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34283 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34284 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
34285 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34286 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
34287 // (st FPR64:{ *:[v1f64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
34288 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
34289 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
34290 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34291 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
34292 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
34293 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34294 GIR_RootConstrainSelectedInstOperands,
34295 // GIR_Coverage, 4167,
34296 GIR_EraseRootFromParent_Done,
34297 // Label 2027: @98353
34298 GIM_Try, /*On fail goto*//*Label 2028*/ GIMT_Encode4(98442), // Rule ID 4146 //
34299 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34300 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
34301 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34302 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34303 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34304 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
34305 // (st GPR64:{ *:[i64] }:$Rt, (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> => (STRBBroW (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
34306 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
34307 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34308 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34309 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(16), // Rt
34310 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
34311 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
34312 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBroW),
34313 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34314 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34315 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
34316 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
34317 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34318 GIR_RootConstrainSelectedInstOperands,
34319 // GIR_Coverage, 4146,
34320 GIR_EraseRootFromParent_Done,
34321 // Label 2028: @98442
34322 GIM_Try, /*On fail goto*//*Label 2029*/ GIMT_Encode4(98531), // Rule ID 4147 //
34323 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34324 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
34325 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34326 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34327 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34328 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
34329 // (st GPR64:{ *:[i64] }:$Rt, (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> => (STRBBroX (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
34330 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
34331 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34332 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34333 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(16), // Rt
34334 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
34335 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
34336 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBroX),
34337 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34338 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34339 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
34340 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
34341 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34342 GIR_RootConstrainSelectedInstOperands,
34343 // GIR_Coverage, 4147,
34344 GIR_EraseRootFromParent_Done,
34345 // Label 2029: @98531
34346 GIM_Try, /*On fail goto*//*Label 2030*/ GIMT_Encode4(98620), // Rule ID 4148 //
34347 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34348 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
34349 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34350 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34351 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34352 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
34353 // (st GPR64:{ *:[i64] }:$Rt, (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> => (STRHHroW (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
34354 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
34355 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34356 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34357 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(16), // Rt
34358 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
34359 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
34360 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHroW),
34361 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34362 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34363 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
34364 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
34365 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34366 GIR_RootConstrainSelectedInstOperands,
34367 // GIR_Coverage, 4148,
34368 GIR_EraseRootFromParent_Done,
34369 // Label 2030: @98620
34370 GIM_Try, /*On fail goto*//*Label 2031*/ GIMT_Encode4(98709), // Rule ID 4149 //
34371 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34372 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
34373 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34374 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34375 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34376 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
34377 // (st GPR64:{ *:[i64] }:$Rt, (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> => (STRHHroX (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
34378 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
34379 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34380 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34381 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(16), // Rt
34382 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
34383 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
34384 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHroX),
34385 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34386 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34387 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
34388 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
34389 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34390 GIR_RootConstrainSelectedInstOperands,
34391 // GIR_Coverage, 4149,
34392 GIR_EraseRootFromParent_Done,
34393 // Label 2031: @98709
34394 GIM_Try, /*On fail goto*//*Label 2032*/ GIMT_Encode4(98798), // Rule ID 4150 //
34395 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34396 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
34397 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34398 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34399 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34400 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
34401 // (st GPR64:{ *:[i64] }:$Rt, (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> => (STRWroW (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
34402 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
34403 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34404 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34405 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(16), // Rt
34406 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
34407 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
34408 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWroW),
34409 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34410 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34411 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
34412 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
34413 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34414 GIR_RootConstrainSelectedInstOperands,
34415 // GIR_Coverage, 4150,
34416 GIR_EraseRootFromParent_Done,
34417 // Label 2032: @98798
34418 GIM_Try, /*On fail goto*//*Label 2033*/ GIMT_Encode4(98887), // Rule ID 4151 //
34419 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34420 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
34421 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34422 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34423 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34424 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
34425 // (st GPR64:{ *:[i64] }:$Rt, (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> => (STRWroX (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
34426 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
34427 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34428 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34429 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(16), // Rt
34430 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
34431 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
34432 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWroX),
34433 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34434 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34435 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
34436 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
34437 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34438 GIR_RootConstrainSelectedInstOperands,
34439 // GIR_Coverage, 4151,
34440 GIR_EraseRootFromParent_Done,
34441 // Label 2033: @98887
34442 GIM_Try, /*On fail goto*//*Label 2034*/ GIMT_Encode4(98939), // Rule ID 321 //
34443 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34444 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34445 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34446 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34447 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
34448 // (st GPR64z:{ *:[i64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRXui GPR64z:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
34449 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRXui),
34450 GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::XZR), // Rt
34451 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34452 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34453 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34454 GIR_RootConstrainSelectedInstOperands,
34455 // GIR_Coverage, 321,
34456 GIR_EraseRootFromParent_Done,
34457 // Label 2034: @98939
34458 GIM_Try, /*On fail goto*//*Label 2035*/ GIMT_Encode4(98990), // Rule ID 326 //
34459 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
34460 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34461 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34462 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
34463 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34464 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
34465 // (st FPR64Op:{ *:[f64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
34466 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
34467 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
34468 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34469 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34470 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34471 GIR_RootConstrainSelectedInstOperands,
34472 // GIR_Coverage, 326,
34473 GIR_EraseRootFromParent_Done,
34474 // Label 2035: @98990
34475 GIM_Try, /*On fail goto*//*Label 2036*/ GIMT_Encode4(99038), // Rule ID 4197 //
34476 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34477 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34478 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
34479 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34480 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
34481 // (st FPR64:{ *:[v1i64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
34482 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
34483 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
34484 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34485 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34486 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34487 GIR_RootConstrainSelectedInstOperands,
34488 // GIR_Coverage, 4197,
34489 GIR_EraseRootFromParent_Done,
34490 // Label 2036: @99038
34491 GIM_Try, /*On fail goto*//*Label 2037*/ GIMT_Encode4(99086), // Rule ID 4198 //
34492 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34493 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34494 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
34495 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34496 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
34497 // (st FPR64:{ *:[v1f64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
34498 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
34499 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
34500 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34501 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34502 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34503 GIR_RootConstrainSelectedInstOperands,
34504 // GIR_Coverage, 4198,
34505 GIR_EraseRootFromParent_Done,
34506 // Label 2037: @99086
34507 GIM_Try, /*On fail goto*//*Label 2038*/ GIMT_Encode4(99170), // Rule ID 4214 //
34508 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34509 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
34510 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34511 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34512 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34513 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
34514 // (st GPR64:{ *:[i64] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> => (STRWui (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
34515 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
34516 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34517 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34518 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(16), // Rt
34519 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
34520 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
34521 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWui),
34522 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34523 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34524 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34525 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34526 GIR_RootConstrainSelectedInstOperands,
34527 // GIR_Coverage, 4214,
34528 GIR_EraseRootFromParent_Done,
34529 // Label 2038: @99170
34530 GIM_Try, /*On fail goto*//*Label 2039*/ GIMT_Encode4(99254), // Rule ID 4215 //
34531 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34532 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
34533 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34534 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34535 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34536 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
34537 // (st GPR64:{ *:[i64] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> => (STRHHui (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
34538 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
34539 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34540 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34541 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(16), // Rt
34542 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
34543 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
34544 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHui),
34545 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34546 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34547 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34548 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34549 GIR_RootConstrainSelectedInstOperands,
34550 // GIR_Coverage, 4215,
34551 GIR_EraseRootFromParent_Done,
34552 // Label 2039: @99254
34553 GIM_Try, /*On fail goto*//*Label 2040*/ GIMT_Encode4(99338), // Rule ID 4216 //
34554 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34555 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
34556 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34557 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34558 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34559 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
34560 // (st GPR64:{ *:[i64] }:$Rt, (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> => (STRBBui (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
34561 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
34562 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34563 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34564 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(16), // Rt
34565 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
34566 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
34567 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBui),
34568 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34569 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34570 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34571 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34572 GIR_RootConstrainSelectedInstOperands,
34573 // GIR_Coverage, 4216,
34574 GIR_EraseRootFromParent_Done,
34575 // Label 2040: @99338
34576 GIM_Try, /*On fail goto*//*Label 2041*/ GIMT_Encode4(99415), // Rule ID 6814 //
34577 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
34578 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
34579 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
34580 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
34581 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
34582 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
34583 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
34584 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34585 GIM_CheckIsSafeToFold, /*NumInsns*/1,
34586 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
34587 // (atomic_store (bitconvert:{ *:[i64] } FPR64Op:{ *:[f64] }:$val), (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_14636>> => (STRDroW FPR64Op:{ *:[f64] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
34588 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
34589 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
34590 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34591 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
34592 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
34593 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
34594 GIR_RootConstrainSelectedInstOperands,
34595 // GIR_Coverage, 6814,
34596 GIR_EraseRootFromParent_Done,
34597 // Label 2041: @99415
34598 GIM_Try, /*On fail goto*//*Label 2042*/ GIMT_Encode4(99492), // Rule ID 6815 //
34599 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
34600 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
34601 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
34602 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
34603 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
34604 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
34605 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
34606 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34607 GIM_CheckIsSafeToFold, /*NumInsns*/1,
34608 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
34609 // (atomic_store (bitconvert:{ *:[i64] } FPR64Op:{ *:[f64] }:$val), (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_14636>> => (STRDroX FPR64Op:{ *:[f64] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
34610 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
34611 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
34612 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34613 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
34614 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
34615 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
34616 GIR_RootConstrainSelectedInstOperands,
34617 // GIR_Coverage, 6815,
34618 GIR_EraseRootFromParent_Done,
34619 // Label 2042: @99492
34620 GIM_Try, /*On fail goto*//*Label 2043*/ GIMT_Encode4(99551), // Rule ID 6806 //
34621 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
34622 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
34623 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
34624 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34625 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34626 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
34627 // (atomic_store GPR64:{ *:[i64] }:$val, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_14636>> => (STRXroW GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
34628 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRXroW),
34629 GIR_RootToRootCopy, /*OpIdx*/0, // val
34630 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34631 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
34632 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
34633 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34634 GIR_RootConstrainSelectedInstOperands,
34635 // GIR_Coverage, 6806,
34636 GIR_EraseRootFromParent_Done,
34637 // Label 2043: @99551
34638 GIM_Try, /*On fail goto*//*Label 2044*/ GIMT_Encode4(99610), // Rule ID 6807 //
34639 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
34640 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
34641 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
34642 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34643 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34644 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
34645 // (atomic_store GPR64:{ *:[i64] }:$val, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_14636>> => (STRXroX GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
34646 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRXroX),
34647 GIR_RootToRootCopy, /*OpIdx*/0, // val
34648 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34649 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
34650 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
34651 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34652 GIR_RootConstrainSelectedInstOperands,
34653 // GIR_Coverage, 6807,
34654 GIR_EraseRootFromParent_Done,
34655 // Label 2044: @99610
34656 GIM_Try, /*On fail goto*//*Label 2045*/ GIMT_Encode4(99682), // Rule ID 6816 //
34657 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
34658 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
34659 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
34660 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
34661 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
34662 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
34663 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
34664 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34665 GIM_CheckIsSafeToFold, /*NumInsns*/1,
34666 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
34667 // (atomic_store (bitconvert:{ *:[i64] } FPR64Op:{ *:[f64] }:$val), (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_14636>> => (STRDui FPR64Op:{ *:[f64] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
34668 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
34669 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
34670 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34671 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34672 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
34673 GIR_RootConstrainSelectedInstOperands,
34674 // GIR_Coverage, 6816,
34675 GIR_EraseRootFromParent_Done,
34676 // Label 2045: @99682
34677 GIM_Try, /*On fail goto*//*Label 2046*/ GIMT_Encode4(99754), // Rule ID 6817 //
34678 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
34679 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
34680 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
34681 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
34682 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
34683 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
34684 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
34685 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34686 GIM_CheckIsSafeToFold, /*NumInsns*/1,
34687 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
34688 // (atomic_store (bitconvert:{ *:[i64] } FPR64Op:{ *:[f64] }:$val), (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_14636>> => (STURDi FPR64Op:{ *:[f64] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
34689 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
34690 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
34691 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34692 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34693 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
34694 GIR_RootConstrainSelectedInstOperands,
34695 // GIR_Coverage, 6817,
34696 GIR_EraseRootFromParent_Done,
34697 // Label 2046: @99754
34698 GIM_Try, /*On fail goto*//*Label 2047*/ GIMT_Encode4(99851), // Rule ID 7088 //
34699 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRCPC3),
34700 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
34701 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
34702 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
34703 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
34704 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
34705 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
34706 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
34707 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
34708 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
34709 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
34710 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
34711 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
34712 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34713 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
34714 // MIs[3] Operand 1
34715 // No operand predicates
34716 // MIs[0] Rn
34717 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
34718 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
34719 GIM_CheckIsSafeToFold, /*NumInsns*/3,
34720 // (atomic_store (bitconvert:{ *:[i64] } (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_14634>> => (STL1 VecListOne128:{ *:[v2f64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
34721 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STL1),
34722 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vt
34723 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
34724 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
34725 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/4, /*MergeInsnID's*/0, 1, 2, 3,
34726 GIR_RootConstrainSelectedInstOperands,
34727 // GIR_Coverage, 7088,
34728 GIR_EraseRootFromParent_Done,
34729 // Label 2047: @99851
34730 GIM_Try, /*On fail goto*//*Label 2048*/ GIMT_Encode4(99903), // Rule ID 329 //
34731 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34732 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34733 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34734 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34735 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
34736 // (st GPR64z:{ *:[i64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURXi GPR64z:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
34737 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURXi),
34738 GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::XZR), // Rt
34739 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34740 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34741 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34742 GIR_RootConstrainSelectedInstOperands,
34743 // GIR_Coverage, 329,
34744 GIR_EraseRootFromParent_Done,
34745 // Label 2048: @99903
34746 GIM_Try, /*On fail goto*//*Label 2049*/ GIMT_Encode4(99954), // Rule ID 334 //
34747 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
34748 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34749 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34750 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
34751 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34752 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
34753 // (st FPR64Op:{ *:[f64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
34754 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
34755 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
34756 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34757 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34758 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34759 GIR_RootConstrainSelectedInstOperands,
34760 // GIR_Coverage, 334,
34761 GIR_EraseRootFromParent_Done,
34762 // Label 2049: @99954
34763 GIM_Try, /*On fail goto*//*Label 2050*/ GIMT_Encode4(100008), // Rule ID 6808 //
34764 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
34765 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
34766 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
34767 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34768 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34769 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
34770 // (atomic_store GPR64:{ *:[i64] }:$val, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_14636>> => (STRXui GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
34771 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRXui),
34772 GIR_RootToRootCopy, /*OpIdx*/0, // val
34773 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34774 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34775 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34776 GIR_RootConstrainSelectedInstOperands,
34777 // GIR_Coverage, 6808,
34778 GIR_EraseRootFromParent_Done,
34779 // Label 2050: @100008
34780 GIM_Try, /*On fail goto*//*Label 2051*/ GIMT_Encode4(100062), // Rule ID 6809 //
34781 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
34782 GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
34783 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
34784 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34785 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34786 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
34787 // (atomic_store GPR64:{ *:[i64] }:$val, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_14636>> => (STURXi GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
34788 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURXi),
34789 GIR_RootToRootCopy, /*OpIdx*/0, // val
34790 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34791 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34792 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34793 GIR_RootConstrainSelectedInstOperands,
34794 // GIR_Coverage, 6809,
34795 GIR_EraseRootFromParent_Done,
34796 // Label 2051: @100062
34797 GIM_Try, /*On fail goto*//*Label 2052*/ GIMT_Encode4(100119), // Rule ID 7099 //
34798 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO),
34799 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
34800 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
34801 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
34802 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34803 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34804 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
34805 // (atomic_store GPR64:{ *:[i64] }:$val, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_14634>> => (STLURXi GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
34806 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLURXi),
34807 GIR_RootToRootCopy, /*OpIdx*/0, // val
34808 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34809 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34810 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34811 GIR_RootConstrainSelectedInstOperands,
34812 // GIR_Coverage, 7099,
34813 GIR_EraseRootFromParent_Done,
34814 // Label 2052: @100119
34815 GIM_Try, /*On fail goto*//*Label 2053*/ GIMT_Encode4(100167), // Rule ID 4224 //
34816 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34817 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34818 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
34819 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34820 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
34821 // (st FPR64:{ *:[v1f64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
34822 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
34823 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
34824 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34825 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34826 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34827 GIR_RootConstrainSelectedInstOperands,
34828 // GIR_Coverage, 4224,
34829 GIR_EraseRootFromParent_Done,
34830 // Label 2053: @100167
34831 GIM_Try, /*On fail goto*//*Label 2054*/ GIMT_Encode4(100215), // Rule ID 4225 //
34832 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34833 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34834 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
34835 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34836 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
34837 // (st FPR64:{ *:[v1i64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
34838 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
34839 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
34840 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34841 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34842 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34843 GIR_RootConstrainSelectedInstOperands,
34844 // GIR_Coverage, 4225,
34845 GIR_EraseRootFromParent_Done,
34846 // Label 2054: @100215
34847 GIM_Try, /*On fail goto*//*Label 2055*/ GIMT_Encode4(100299), // Rule ID 4242 //
34848 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34849 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
34850 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34851 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34852 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34853 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
34854 // (st GPR64:{ *:[i64] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> => (STURWi (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
34855 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
34856 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34857 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34858 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(16), // Rt
34859 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
34860 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
34861 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURWi),
34862 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34863 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34864 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34865 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34866 GIR_RootConstrainSelectedInstOperands,
34867 // GIR_Coverage, 4242,
34868 GIR_EraseRootFromParent_Done,
34869 // Label 2055: @100299
34870 GIM_Try, /*On fail goto*//*Label 2056*/ GIMT_Encode4(100383), // Rule ID 4243 //
34871 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34872 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
34873 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34874 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34875 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34876 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
34877 // (st GPR64:{ *:[i64] }:$Rt, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> => (STURHHi (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
34878 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
34879 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34880 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34881 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(16), // Rt
34882 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
34883 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
34884 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHHi),
34885 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34886 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34887 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34888 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34889 GIR_RootConstrainSelectedInstOperands,
34890 // GIR_Coverage, 4243,
34891 GIR_EraseRootFromParent_Done,
34892 // Label 2056: @100383
34893 GIM_Try, /*On fail goto*//*Label 2057*/ GIMT_Encode4(100467), // Rule ID 4244 //
34894 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34895 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
34896 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34897 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34898 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
34899 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
34900 // (st GPR64:{ *:[i64] }:$Rt, (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> => (STURBBi (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
34901 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
34902 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
34903 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34904 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(16), // Rt
34905 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
34906 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
34907 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURBBi),
34908 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34909 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
34910 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
34911 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34912 GIR_RootConstrainSelectedInstOperands,
34913 // GIR_Coverage, 4244,
34914 GIR_EraseRootFromParent_Done,
34915 // Label 2057: @100467
34916 GIM_Try, /*On fail goto*//*Label 2058*/ GIMT_Encode4(100551), // Rule ID 7087 //
34917 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRCPC3),
34918 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
34919 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
34920 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
34921 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
34922 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
34923 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
34924 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
34925 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
34926 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
34927 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34928 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
34929 // MIs[2] Operand 1
34930 // No operand predicates
34931 // MIs[0] Rn
34932 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
34933 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
34934 GIM_CheckIsSafeToFold, /*NumInsns*/2,
34935 // (atomic_store (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_14634>> => (STL1 VecListOne128:{ *:[v2i64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
34936 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STL1),
34937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
34938 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
34939 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
34940 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
34941 GIR_RootConstrainSelectedInstOperands,
34942 // GIR_Coverage, 7087,
34943 GIR_EraseRootFromParent_Done,
34944 // Label 2058: @100551
34945 GIM_Try, /*On fail goto*//*Label 2059*/ GIMT_Encode4(100649), // Rule ID 7089 //
34946 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRCPC3),
34947 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
34948 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
34949 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
34950 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
34951 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
34952 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
34953 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
34954 // MIs[0] Rn
34955 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
34956 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
34957 GIM_CheckIsSafeToFold, /*NumInsns*/1,
34958 // (atomic_store (bitconvert:{ *:[i64] } VecListOne64:{ *:[v1f64] }:$Vt), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_14634>> => (STL1 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, VecListOne64:{ *:[v1f64] }:$Vt, dsub:{ *:[i32] }), 0:{ *:[i64] }, GPR64sp:{ *:[i64] }:$Rn)
34959 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
34960 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
34961 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
34962 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
34963 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
34964 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
34965 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
34966 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
34967 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STL1),
34968 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
34969 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34970 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
34971 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
34972 GIR_RootConstrainSelectedInstOperands,
34973 // GIR_Coverage, 7089,
34974 GIR_EraseRootFromParent_Done,
34975 // Label 2059: @100649
34976 GIM_Try, /*On fail goto*//*Label 2060*/ GIMT_Encode4(100686), // Rule ID 6805 //
34977 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
34978 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
34979 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
34980 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
34981 // MIs[0] ptr
34982 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
34983 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
34984 // (atomic_store GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_14634>> => (STLRX GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$ptr)
34985 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::STLRX),
34986 GIR_RootConstrainSelectedInstOperands,
34987 // GIR_Coverage, 6805,
34988 GIR_Done,
34989 // Label 2060: @100686
34990 GIM_Try, /*On fail goto*//*Label 2061*/ GIMT_Encode4(100713), // Rule ID 6005 //
34991 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
34992 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
34993 // MIs[0] Rn
34994 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
34995 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
34996 // (st v1i64:{ *:[v1i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev1d v1i64:{ *:[v1i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
34997 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev1d),
34998 GIR_RootConstrainSelectedInstOperands,
34999 // GIR_Coverage, 6005,
35000 GIR_Done,
35001 // Label 2061: @100713
35002 GIM_Reject,
35003 // Label 1905: @100714
35004 GIM_Try, /*On fail goto*//*Label 2062*/ GIMT_Encode4(100919),
35005 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
35006 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
35007 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35008 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35009 GIM_Try, /*On fail goto*//*Label 2063*/ GIMT_Encode4(100775), // Rule ID 4144 //
35010 GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseSTRQro),
35011 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
35012 // (st FPR128:{ *:[f128] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroW FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
35013 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
35014 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35015 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35016 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35017 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35018 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35019 GIR_RootConstrainSelectedInstOperands,
35020 // GIR_Coverage, 4144,
35021 GIR_EraseRootFromParent_Done,
35022 // Label 2063: @100775
35023 GIM_Try, /*On fail goto*//*Label 2064*/ GIMT_Encode4(100816), // Rule ID 4145 //
35024 GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseSTRQro),
35025 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
35026 // (st FPR128:{ *:[f128] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroX FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
35027 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
35028 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35029 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35030 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35031 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35032 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35033 GIR_RootConstrainSelectedInstOperands,
35034 // GIR_Coverage, 4145,
35035 GIR_EraseRootFromParent_Done,
35036 // Label 2064: @100816
35037 GIM_Try, /*On fail goto*//*Label 2065*/ GIMT_Encode4(100849), // Rule ID 4205 //
35038 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
35039 // (st FPR128:{ *:[f128] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
35040 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
35041 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35042 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35043 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35044 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35045 GIR_RootConstrainSelectedInstOperands,
35046 // GIR_Coverage, 4205,
35047 GIR_EraseRootFromParent_Done,
35048 // Label 2065: @100849
35049 GIM_Try, /*On fail goto*//*Label 2066*/ GIMT_Encode4(100882), // Rule ID 4232 //
35050 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
35051 // (st FPR128:{ *:[f128] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
35052 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
35053 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35054 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35055 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35056 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35057 GIR_RootConstrainSelectedInstOperands,
35058 // GIR_Coverage, 4232,
35059 GIR_EraseRootFromParent_Done,
35060 // Label 2066: @100882
35061 GIM_Try, /*On fail goto*//*Label 2067*/ GIMT_Encode4(100918), // Rule ID 335 //
35062 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
35063 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
35064 // (st FPR128Op:{ *:[f128] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128Op:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
35065 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
35066 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35067 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35068 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35069 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35070 GIR_RootConstrainSelectedInstOperands,
35071 // GIR_Coverage, 335,
35072 GIR_EraseRootFromParent_Done,
35073 // Label 2067: @100918
35074 GIM_Reject,
35075 // Label 2062: @100919
35076 GIM_Reject,
35077 // Label 1906: @100920
35078 GIM_Try, /*On fail goto*//*Label 2068*/ GIMT_Encode4(101325),
35079 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
35080 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
35081 GIM_Try, /*On fail goto*//*Label 2069*/ GIMT_Encode4(100981), // Rule ID 4152 //
35082 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35083 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35084 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35085 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
35086 // (st FPR64:{ *:[v2i32] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
35087 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
35088 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35089 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35090 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35091 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35092 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35093 GIR_RootConstrainSelectedInstOperands,
35094 // GIR_Coverage, 4152,
35095 GIR_EraseRootFromParent_Done,
35096 // Label 2069: @100981
35097 GIM_Try, /*On fail goto*//*Label 2070*/ GIMT_Encode4(101030), // Rule ID 4153 //
35098 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35099 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35100 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35101 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
35102 // (st FPR64:{ *:[v2i32] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
35103 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
35104 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35105 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35106 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35107 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35108 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35109 GIR_RootConstrainSelectedInstOperands,
35110 // GIR_Coverage, 4153,
35111 GIR_EraseRootFromParent_Done,
35112 // Label 2070: @101030
35113 GIM_Try, /*On fail goto*//*Label 2071*/ GIMT_Encode4(101079), // Rule ID 4154 //
35114 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35115 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35116 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35117 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
35118 // (st FPR64:{ *:[v2f32] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
35119 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
35120 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35121 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35122 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35123 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35124 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35125 GIR_RootConstrainSelectedInstOperands,
35126 // GIR_Coverage, 4154,
35127 GIR_EraseRootFromParent_Done,
35128 // Label 2071: @101079
35129 GIM_Try, /*On fail goto*//*Label 2072*/ GIMT_Encode4(101128), // Rule ID 4155 //
35130 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35131 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35132 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35133 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
35134 // (st FPR64:{ *:[v2f32] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
35135 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
35136 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35137 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35138 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35139 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35140 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35141 GIR_RootConstrainSelectedInstOperands,
35142 // GIR_Coverage, 4155,
35143 GIR_EraseRootFromParent_Done,
35144 // Label 2072: @101128
35145 GIM_Try, /*On fail goto*//*Label 2073*/ GIMT_Encode4(101172), // Rule ID 4199 //
35146 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35147 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35148 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35149 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
35150 // (st FPR64:{ *:[v2f32] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
35151 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
35152 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35153 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35154 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35155 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35156 GIR_RootConstrainSelectedInstOperands,
35157 // GIR_Coverage, 4199,
35158 GIR_EraseRootFromParent_Done,
35159 // Label 2073: @101172
35160 GIM_Try, /*On fail goto*//*Label 2074*/ GIMT_Encode4(101216), // Rule ID 4202 //
35161 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35162 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35163 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35164 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
35165 // (st FPR64:{ *:[v2i32] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
35166 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
35167 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35168 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35169 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35170 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35171 GIR_RootConstrainSelectedInstOperands,
35172 // GIR_Coverage, 4202,
35173 GIR_EraseRootFromParent_Done,
35174 // Label 2074: @101216
35175 GIM_Try, /*On fail goto*//*Label 2075*/ GIMT_Encode4(101260), // Rule ID 4226 //
35176 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35177 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35178 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35179 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
35180 // (st FPR64:{ *:[v2f32] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
35181 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
35182 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35183 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35184 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35185 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35186 GIR_RootConstrainSelectedInstOperands,
35187 // GIR_Coverage, 4226,
35188 GIR_EraseRootFromParent_Done,
35189 // Label 2075: @101260
35190 GIM_Try, /*On fail goto*//*Label 2076*/ GIMT_Encode4(101304), // Rule ID 4229 //
35191 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35192 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35193 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35194 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
35195 // (st FPR64:{ *:[v2i32] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
35196 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
35197 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35198 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35199 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35200 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35201 GIR_RootConstrainSelectedInstOperands,
35202 // GIR_Coverage, 4229,
35203 GIR_EraseRootFromParent_Done,
35204 // Label 2076: @101304
35205 GIM_Try, /*On fail goto*//*Label 2077*/ GIMT_Encode4(101324), // Rule ID 6004 //
35206 // MIs[0] Rn
35207 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
35208 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
35209 // (st v2i32:{ *:[v2i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev2s v2i32:{ *:[v2i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
35210 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev2s),
35211 GIR_RootConstrainSelectedInstOperands,
35212 // GIR_Coverage, 6004,
35213 GIR_Done,
35214 // Label 2077: @101324
35215 GIM_Reject,
35216 // Label 2068: @101325
35217 GIM_Reject,
35218 // Label 1907: @101326
35219 GIM_Try, /*On fail goto*//*Label 2078*/ GIMT_Encode4(101775),
35220 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
35221 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
35222 GIM_Try, /*On fail goto*//*Label 2079*/ GIMT_Encode4(101387), // Rule ID 4168 //
35223 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
35224 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35225 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35226 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
35227 // (st FPR128:{ *:[v2i64] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroW FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
35228 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
35229 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35230 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35231 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35232 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35233 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35234 GIR_RootConstrainSelectedInstOperands,
35235 // GIR_Coverage, 4168,
35236 GIR_EraseRootFromParent_Done,
35237 // Label 2079: @101387
35238 GIM_Try, /*On fail goto*//*Label 2080*/ GIMT_Encode4(101436), // Rule ID 4169 //
35239 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
35240 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35241 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35242 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
35243 // (st FPR128:{ *:[v2i64] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroX FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
35244 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
35245 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35246 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35247 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35248 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35249 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35250 GIR_RootConstrainSelectedInstOperands,
35251 // GIR_Coverage, 4169,
35252 GIR_EraseRootFromParent_Done,
35253 // Label 2080: @101436
35254 GIM_Try, /*On fail goto*//*Label 2081*/ GIMT_Encode4(101485), // Rule ID 4170 //
35255 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
35256 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35257 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35258 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
35259 // (st FPR128:{ *:[v2f64] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroW FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
35260 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
35261 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35262 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35263 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35264 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35265 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35266 GIR_RootConstrainSelectedInstOperands,
35267 // GIR_Coverage, 4170,
35268 GIR_EraseRootFromParent_Done,
35269 // Label 2081: @101485
35270 GIM_Try, /*On fail goto*//*Label 2082*/ GIMT_Encode4(101534), // Rule ID 4171 //
35271 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
35272 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35273 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35274 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
35275 // (st FPR128:{ *:[v2f64] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroX FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
35276 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
35277 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35278 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35279 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35280 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35281 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35282 GIR_RootConstrainSelectedInstOperands,
35283 // GIR_Coverage, 4171,
35284 GIR_EraseRootFromParent_Done,
35285 // Label 2082: @101534
35286 GIM_Try, /*On fail goto*//*Label 2083*/ GIMT_Encode4(101578), // Rule ID 4207 //
35287 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35288 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35289 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35290 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
35291 // (st FPR128:{ *:[v2f64] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
35292 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
35293 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35294 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35295 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35296 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35297 GIR_RootConstrainSelectedInstOperands,
35298 // GIR_Coverage, 4207,
35299 GIR_EraseRootFromParent_Done,
35300 // Label 2083: @101578
35301 GIM_Try, /*On fail goto*//*Label 2084*/ GIMT_Encode4(101622), // Rule ID 4211 //
35302 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35303 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35304 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35305 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
35306 // (st FPR128:{ *:[v2i64] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
35307 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
35308 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35309 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35310 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35311 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35312 GIR_RootConstrainSelectedInstOperands,
35313 // GIR_Coverage, 4211,
35314 GIR_EraseRootFromParent_Done,
35315 // Label 2084: @101622
35316 GIM_Try, /*On fail goto*//*Label 2085*/ GIMT_Encode4(101666), // Rule ID 4234 //
35317 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35318 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35319 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35320 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
35321 // (st FPR128:{ *:[v2f64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
35322 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
35323 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35324 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35325 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35326 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35327 GIR_RootConstrainSelectedInstOperands,
35328 // GIR_Coverage, 4234,
35329 GIR_EraseRootFromParent_Done,
35330 // Label 2085: @101666
35331 GIM_Try, /*On fail goto*//*Label 2086*/ GIMT_Encode4(101710), // Rule ID 4238 //
35332 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35333 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35334 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35335 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
35336 // (st FPR128:{ *:[v2i64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
35337 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
35338 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35339 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35340 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35341 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35342 GIR_RootConstrainSelectedInstOperands,
35343 // GIR_Coverage, 4238,
35344 GIR_EraseRootFromParent_Done,
35345 // Label 2086: @101710
35346 GIM_Try, /*On fail goto*//*Label 2087*/ GIMT_Encode4(101754), // Rule ID 4239 //
35347 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35348 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35349 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35350 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
35351 // (st FPR128:{ *:[v2f64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
35352 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
35353 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35354 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35355 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35356 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35357 GIR_RootConstrainSelectedInstOperands,
35358 // GIR_Coverage, 4239,
35359 GIR_EraseRootFromParent_Done,
35360 // Label 2087: @101754
35361 GIM_Try, /*On fail goto*//*Label 2088*/ GIMT_Encode4(101774), // Rule ID 6001 //
35362 // MIs[0] Rn
35363 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
35364 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
35365 // (st v2i64:{ *:[v2i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev2d v2i64:{ *:[v2i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
35366 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev2d),
35367 GIR_RootConstrainSelectedInstOperands,
35368 // GIR_Coverage, 6001,
35369 GIR_Done,
35370 // Label 2088: @101774
35371 GIM_Reject,
35372 // Label 2078: @101775
35373 GIM_Reject,
35374 // Label 1908: @101776
35375 GIM_Try, /*On fail goto*//*Label 2089*/ GIMT_Encode4(102367),
35376 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
35377 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
35378 GIM_Try, /*On fail goto*//*Label 2090*/ GIMT_Encode4(101837), // Rule ID 4156 //
35379 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35380 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35381 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35382 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
35383 // (st FPR64:{ *:[v4i16] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
35384 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
35385 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35386 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35387 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35388 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35389 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35390 GIR_RootConstrainSelectedInstOperands,
35391 // GIR_Coverage, 4156,
35392 GIR_EraseRootFromParent_Done,
35393 // Label 2090: @101837
35394 GIM_Try, /*On fail goto*//*Label 2091*/ GIMT_Encode4(101886), // Rule ID 4157 //
35395 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35396 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35397 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35398 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
35399 // (st FPR64:{ *:[v4i16] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
35400 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
35401 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35402 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35403 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35404 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35405 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35406 GIR_RootConstrainSelectedInstOperands,
35407 // GIR_Coverage, 4157,
35408 GIR_EraseRootFromParent_Done,
35409 // Label 2091: @101886
35410 GIM_Try, /*On fail goto*//*Label 2092*/ GIMT_Encode4(101935), // Rule ID 4160 //
35411 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35412 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35413 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35414 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
35415 // (st FPR64:{ *:[v4f16] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
35416 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
35417 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35418 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35419 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35420 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35421 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35422 GIR_RootConstrainSelectedInstOperands,
35423 // GIR_Coverage, 4160,
35424 GIR_EraseRootFromParent_Done,
35425 // Label 2092: @101935
35426 GIM_Try, /*On fail goto*//*Label 2093*/ GIMT_Encode4(101984), // Rule ID 4161 //
35427 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35428 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35429 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35430 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
35431 // (st FPR64:{ *:[v4f16] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
35432 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
35433 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35434 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35435 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35436 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35437 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35438 GIR_RootConstrainSelectedInstOperands,
35439 // GIR_Coverage, 4161,
35440 GIR_EraseRootFromParent_Done,
35441 // Label 2093: @101984
35442 GIM_Try, /*On fail goto*//*Label 2094*/ GIMT_Encode4(102033), // Rule ID 4162 //
35443 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35444 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35445 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35446 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
35447 // (st FPR64:{ *:[v4bf16] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW FPR64:{ *:[v4bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
35448 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
35449 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35450 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35451 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35452 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35453 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35454 GIR_RootConstrainSelectedInstOperands,
35455 // GIR_Coverage, 4162,
35456 GIR_EraseRootFromParent_Done,
35457 // Label 2094: @102033
35458 GIM_Try, /*On fail goto*//*Label 2095*/ GIMT_Encode4(102082), // Rule ID 4163 //
35459 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35460 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35461 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35462 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
35463 // (st FPR64:{ *:[v4bf16] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX FPR64:{ *:[v4bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
35464 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
35465 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35466 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35467 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35468 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35469 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35470 GIR_RootConstrainSelectedInstOperands,
35471 // GIR_Coverage, 4163,
35472 GIR_EraseRootFromParent_Done,
35473 // Label 2095: @102082
35474 GIM_Try, /*On fail goto*//*Label 2096*/ GIMT_Encode4(102126), // Rule ID 4201 //
35475 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35476 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35477 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35478 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
35479 // (st FPR64:{ *:[v4i16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
35480 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
35481 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35482 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35483 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35484 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35485 GIR_RootConstrainSelectedInstOperands,
35486 // GIR_Coverage, 4201,
35487 GIR_EraseRootFromParent_Done,
35488 // Label 2096: @102126
35489 GIM_Try, /*On fail goto*//*Label 2097*/ GIMT_Encode4(102170), // Rule ID 4203 //
35490 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35491 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35492 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35493 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
35494 // (st FPR64:{ *:[v4f16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
35495 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
35496 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35497 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35498 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35499 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35500 GIR_RootConstrainSelectedInstOperands,
35501 // GIR_Coverage, 4203,
35502 GIR_EraseRootFromParent_Done,
35503 // Label 2097: @102170
35504 GIM_Try, /*On fail goto*//*Label 2098*/ GIMT_Encode4(102214), // Rule ID 4204 //
35505 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35506 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35507 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35508 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
35509 // (st FPR64:{ *:[v4bf16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v4bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
35510 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
35511 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35512 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35513 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35514 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35515 GIR_RootConstrainSelectedInstOperands,
35516 // GIR_Coverage, 4204,
35517 GIR_EraseRootFromParent_Done,
35518 // Label 2098: @102214
35519 GIM_Try, /*On fail goto*//*Label 2099*/ GIMT_Encode4(102258), // Rule ID 4228 //
35520 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35521 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35522 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35523 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
35524 // (st FPR64:{ *:[v4i16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
35525 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
35526 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35527 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35528 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35529 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35530 GIR_RootConstrainSelectedInstOperands,
35531 // GIR_Coverage, 4228,
35532 GIR_EraseRootFromParent_Done,
35533 // Label 2099: @102258
35534 GIM_Try, /*On fail goto*//*Label 2100*/ GIMT_Encode4(102302), // Rule ID 4230 //
35535 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35536 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35537 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35538 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
35539 // (st FPR64:{ *:[v4f16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
35540 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
35541 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35542 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35543 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35544 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35545 GIR_RootConstrainSelectedInstOperands,
35546 // GIR_Coverage, 4230,
35547 GIR_EraseRootFromParent_Done,
35548 // Label 2100: @102302
35549 GIM_Try, /*On fail goto*//*Label 2101*/ GIMT_Encode4(102346), // Rule ID 4231 //
35550 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35551 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35552 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35553 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
35554 // (st FPR64:{ *:[v4bf16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v4bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
35555 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
35556 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35557 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35558 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35559 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35560 GIR_RootConstrainSelectedInstOperands,
35561 // GIR_Coverage, 4231,
35562 GIR_EraseRootFromParent_Done,
35563 // Label 2101: @102346
35564 GIM_Try, /*On fail goto*//*Label 2102*/ GIMT_Encode4(102366), // Rule ID 6003 //
35565 // MIs[0] Rn
35566 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
35567 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
35568 // (st v4i16:{ *:[v4i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev4h v4i16:{ *:[v4i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
35569 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev4h),
35570 GIR_RootConstrainSelectedInstOperands,
35571 // GIR_Coverage, 6003,
35572 GIR_Done,
35573 // Label 2102: @102366
35574 GIM_Reject,
35575 // Label 2089: @102367
35576 GIM_Reject,
35577 // Label 1909: @102368
35578 GIM_Try, /*On fail goto*//*Label 2103*/ GIMT_Encode4(102773),
35579 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
35580 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
35581 GIM_Try, /*On fail goto*//*Label 2104*/ GIMT_Encode4(102429), // Rule ID 4172 //
35582 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
35583 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35584 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35585 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
35586 // (st FPR128:{ *:[v4i32] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroW FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
35587 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
35588 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35589 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35590 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35591 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35592 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35593 GIR_RootConstrainSelectedInstOperands,
35594 // GIR_Coverage, 4172,
35595 GIR_EraseRootFromParent_Done,
35596 // Label 2104: @102429
35597 GIM_Try, /*On fail goto*//*Label 2105*/ GIMT_Encode4(102478), // Rule ID 4173 //
35598 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
35599 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35600 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35601 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
35602 // (st FPR128:{ *:[v4i32] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroX FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
35603 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
35604 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35605 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35606 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35607 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35608 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35609 GIR_RootConstrainSelectedInstOperands,
35610 // GIR_Coverage, 4173,
35611 GIR_EraseRootFromParent_Done,
35612 // Label 2105: @102478
35613 GIM_Try, /*On fail goto*//*Label 2106*/ GIMT_Encode4(102527), // Rule ID 4174 //
35614 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
35615 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35616 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35617 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
35618 // (st FPR128:{ *:[v4f32] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroW FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
35619 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
35620 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35621 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35622 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35623 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35624 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35625 GIR_RootConstrainSelectedInstOperands,
35626 // GIR_Coverage, 4174,
35627 GIR_EraseRootFromParent_Done,
35628 // Label 2106: @102527
35629 GIM_Try, /*On fail goto*//*Label 2107*/ GIMT_Encode4(102576), // Rule ID 4175 //
35630 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
35631 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35632 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35633 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
35634 // (st FPR128:{ *:[v4f32] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroX FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
35635 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
35636 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35637 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35638 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35639 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35640 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35641 GIR_RootConstrainSelectedInstOperands,
35642 // GIR_Coverage, 4175,
35643 GIR_EraseRootFromParent_Done,
35644 // Label 2107: @102576
35645 GIM_Try, /*On fail goto*//*Label 2108*/ GIMT_Encode4(102620), // Rule ID 4206 //
35646 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35647 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35648 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35649 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
35650 // (st FPR128:{ *:[v4f32] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
35651 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
35652 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35653 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35654 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35655 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35656 GIR_RootConstrainSelectedInstOperands,
35657 // GIR_Coverage, 4206,
35658 GIR_EraseRootFromParent_Done,
35659 // Label 2108: @102620
35660 GIM_Try, /*On fail goto*//*Label 2109*/ GIMT_Encode4(102664), // Rule ID 4210 //
35661 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35662 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35663 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35664 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
35665 // (st FPR128:{ *:[v4i32] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
35666 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
35667 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35668 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35669 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35670 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35671 GIR_RootConstrainSelectedInstOperands,
35672 // GIR_Coverage, 4210,
35673 GIR_EraseRootFromParent_Done,
35674 // Label 2109: @102664
35675 GIM_Try, /*On fail goto*//*Label 2110*/ GIMT_Encode4(102708), // Rule ID 4233 //
35676 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35677 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35678 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35679 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
35680 // (st FPR128:{ *:[v4f32] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
35681 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
35682 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35683 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35684 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35685 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35686 GIR_RootConstrainSelectedInstOperands,
35687 // GIR_Coverage, 4233,
35688 GIR_EraseRootFromParent_Done,
35689 // Label 2110: @102708
35690 GIM_Try, /*On fail goto*//*Label 2111*/ GIMT_Encode4(102752), // Rule ID 4237 //
35691 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35692 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35693 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35694 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
35695 // (st FPR128:{ *:[v4i32] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
35696 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
35697 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35698 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35699 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35700 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35701 GIR_RootConstrainSelectedInstOperands,
35702 // GIR_Coverage, 4237,
35703 GIR_EraseRootFromParent_Done,
35704 // Label 2111: @102752
35705 GIM_Try, /*On fail goto*//*Label 2112*/ GIMT_Encode4(102772), // Rule ID 6000 //
35706 // MIs[0] Rn
35707 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
35708 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
35709 // (st v4i32:{ *:[v4i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev4s v4i32:{ *:[v4i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
35710 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev4s),
35711 GIR_RootConstrainSelectedInstOperands,
35712 // GIR_Coverage, 6000,
35713 GIR_Done,
35714 // Label 2112: @102772
35715 GIM_Reject,
35716 // Label 2103: @102773
35717 GIM_Reject,
35718 // Label 1910: @102774
35719 GIM_Try, /*On fail goto*//*Label 2113*/ GIMT_Encode4(102993),
35720 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
35721 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
35722 GIM_Try, /*On fail goto*//*Label 2114*/ GIMT_Encode4(102835), // Rule ID 4158 //
35723 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35724 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35725 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35726 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
35727 // (st FPR64:{ *:[v8i8] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroW FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
35728 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
35729 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35730 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35731 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35732 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35733 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35734 GIR_RootConstrainSelectedInstOperands,
35735 // GIR_Coverage, 4158,
35736 GIR_EraseRootFromParent_Done,
35737 // Label 2114: @102835
35738 GIM_Try, /*On fail goto*//*Label 2115*/ GIMT_Encode4(102884), // Rule ID 4159 //
35739 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35740 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35741 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35742 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
35743 // (st FPR64:{ *:[v8i8] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDroX FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
35744 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
35745 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35746 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35747 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35748 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35749 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35750 GIR_RootConstrainSelectedInstOperands,
35751 // GIR_Coverage, 4159,
35752 GIR_EraseRootFromParent_Done,
35753 // Label 2115: @102884
35754 GIM_Try, /*On fail goto*//*Label 2116*/ GIMT_Encode4(102928), // Rule ID 4200 //
35755 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35756 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35757 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35758 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
35759 // (st FPR64:{ *:[v8i8] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRDui FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
35760 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
35761 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35762 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35763 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35764 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35765 GIR_RootConstrainSelectedInstOperands,
35766 // GIR_Coverage, 4200,
35767 GIR_EraseRootFromParent_Done,
35768 // Label 2116: @102928
35769 GIM_Try, /*On fail goto*//*Label 2117*/ GIMT_Encode4(102972), // Rule ID 4227 //
35770 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35771 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
35772 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35773 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
35774 // (st FPR64:{ *:[v8i8] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURDi FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
35775 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
35776 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35777 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35778 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35779 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35780 GIR_RootConstrainSelectedInstOperands,
35781 // GIR_Coverage, 4227,
35782 GIR_EraseRootFromParent_Done,
35783 // Label 2117: @102972
35784 GIM_Try, /*On fail goto*//*Label 2118*/ GIMT_Encode4(102992), // Rule ID 6002 //
35785 // MIs[0] Rn
35786 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
35787 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
35788 // (st v8i8:{ *:[v8i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev8b v8i8:{ *:[v8i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
35789 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev8b),
35790 GIR_RootConstrainSelectedInstOperands,
35791 // GIR_Coverage, 6002,
35792 GIR_Done,
35793 // Label 2118: @102992
35794 GIM_Reject,
35795 // Label 2113: @102993
35796 GIM_Reject,
35797 // Label 1911: @102994
35798 GIM_Try, /*On fail goto*//*Label 2119*/ GIMT_Encode4(103585),
35799 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
35800 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
35801 GIM_Try, /*On fail goto*//*Label 2120*/ GIMT_Encode4(103055), // Rule ID 4176 //
35802 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
35803 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35804 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35805 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
35806 // (st FPR128:{ *:[v8i16] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroW FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
35807 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
35808 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35809 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35810 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35811 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35812 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35813 GIR_RootConstrainSelectedInstOperands,
35814 // GIR_Coverage, 4176,
35815 GIR_EraseRootFromParent_Done,
35816 // Label 2120: @103055
35817 GIM_Try, /*On fail goto*//*Label 2121*/ GIMT_Encode4(103104), // Rule ID 4177 //
35818 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
35819 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35820 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35821 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
35822 // (st FPR128:{ *:[v8i16] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroX FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
35823 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
35824 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35825 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35826 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35827 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35828 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35829 GIR_RootConstrainSelectedInstOperands,
35830 // GIR_Coverage, 4177,
35831 GIR_EraseRootFromParent_Done,
35832 // Label 2121: @103104
35833 GIM_Try, /*On fail goto*//*Label 2122*/ GIMT_Encode4(103153), // Rule ID 4180 //
35834 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
35835 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35836 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35837 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
35838 // (st FPR128:{ *:[v8f16] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroW FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
35839 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
35840 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35841 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35842 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35843 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35844 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35845 GIR_RootConstrainSelectedInstOperands,
35846 // GIR_Coverage, 4180,
35847 GIR_EraseRootFromParent_Done,
35848 // Label 2122: @103153
35849 GIM_Try, /*On fail goto*//*Label 2123*/ GIMT_Encode4(103202), // Rule ID 4181 //
35850 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
35851 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35852 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35853 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
35854 // (st FPR128:{ *:[v8f16] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroX FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
35855 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
35856 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35857 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35858 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35859 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35860 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35861 GIR_RootConstrainSelectedInstOperands,
35862 // GIR_Coverage, 4181,
35863 GIR_EraseRootFromParent_Done,
35864 // Label 2123: @103202
35865 GIM_Try, /*On fail goto*//*Label 2124*/ GIMT_Encode4(103251), // Rule ID 4182 //
35866 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
35867 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35868 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35869 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
35870 // (st FPR128:{ *:[v8bf16] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroW FPR128:{ *:[v8bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
35871 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
35872 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35873 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35874 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35875 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35876 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35877 GIR_RootConstrainSelectedInstOperands,
35878 // GIR_Coverage, 4182,
35879 GIR_EraseRootFromParent_Done,
35880 // Label 2124: @103251
35881 GIM_Try, /*On fail goto*//*Label 2125*/ GIMT_Encode4(103300), // Rule ID 4183 //
35882 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
35883 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35884 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35885 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
35886 // (st FPR128:{ *:[v8bf16] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroX FPR128:{ *:[v8bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
35887 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
35888 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35889 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35890 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
35891 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
35892 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35893 GIR_RootConstrainSelectedInstOperands,
35894 // GIR_Coverage, 4183,
35895 GIR_EraseRootFromParent_Done,
35896 // Label 2125: @103300
35897 GIM_Try, /*On fail goto*//*Label 2126*/ GIMT_Encode4(103344), // Rule ID 4209 //
35898 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35899 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35900 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35901 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
35902 // (st FPR128:{ *:[v8i16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
35903 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
35904 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35905 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35906 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35907 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35908 GIR_RootConstrainSelectedInstOperands,
35909 // GIR_Coverage, 4209,
35910 GIR_EraseRootFromParent_Done,
35911 // Label 2126: @103344
35912 GIM_Try, /*On fail goto*//*Label 2127*/ GIMT_Encode4(103388), // Rule ID 4212 //
35913 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35914 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35915 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35916 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
35917 // (st FPR128:{ *:[v8f16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
35918 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
35919 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35920 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35921 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35922 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35923 GIR_RootConstrainSelectedInstOperands,
35924 // GIR_Coverage, 4212,
35925 GIR_EraseRootFromParent_Done,
35926 // Label 2127: @103388
35927 GIM_Try, /*On fail goto*//*Label 2128*/ GIMT_Encode4(103432), // Rule ID 4213 //
35928 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35929 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35930 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35931 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
35932 // (st FPR128:{ *:[v8bf16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v8bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
35933 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
35934 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35935 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35936 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35937 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35938 GIR_RootConstrainSelectedInstOperands,
35939 // GIR_Coverage, 4213,
35940 GIR_EraseRootFromParent_Done,
35941 // Label 2128: @103432
35942 GIM_Try, /*On fail goto*//*Label 2129*/ GIMT_Encode4(103476), // Rule ID 4236 //
35943 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35944 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35945 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35946 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
35947 // (st FPR128:{ *:[v8i16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
35948 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
35949 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35950 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35951 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35952 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35953 GIR_RootConstrainSelectedInstOperands,
35954 // GIR_Coverage, 4236,
35955 GIR_EraseRootFromParent_Done,
35956 // Label 2129: @103476
35957 GIM_Try, /*On fail goto*//*Label 2130*/ GIMT_Encode4(103520), // Rule ID 4240 //
35958 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35959 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35960 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35961 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
35962 // (st FPR128:{ *:[v8f16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
35963 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
35964 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35965 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35966 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35967 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35968 GIR_RootConstrainSelectedInstOperands,
35969 // GIR_Coverage, 4240,
35970 GIR_EraseRootFromParent_Done,
35971 // Label 2130: @103520
35972 GIM_Try, /*On fail goto*//*Label 2131*/ GIMT_Encode4(103564), // Rule ID 4241 //
35973 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
35974 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
35975 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
35976 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
35977 // (st FPR128:{ *:[v8bf16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v8bf16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
35978 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
35979 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
35980 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
35981 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
35982 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35983 GIR_RootConstrainSelectedInstOperands,
35984 // GIR_Coverage, 4241,
35985 GIR_EraseRootFromParent_Done,
35986 // Label 2131: @103564
35987 GIM_Try, /*On fail goto*//*Label 2132*/ GIMT_Encode4(103584), // Rule ID 5999 //
35988 // MIs[0] Rn
35989 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
35990 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
35991 // (st v8i16:{ *:[v8i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev8h v8i16:{ *:[v8i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
35992 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev8h),
35993 GIR_RootConstrainSelectedInstOperands,
35994 // GIR_Coverage, 5999,
35995 GIR_Done,
35996 // Label 2132: @103584
35997 GIM_Reject,
35998 // Label 2119: @103585
35999 GIM_Reject,
36000 // Label 1912: @103586
36001 GIM_Try, /*On fail goto*//*Label 2133*/ GIMT_Encode4(103805),
36002 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
36003 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
36004 GIM_Try, /*On fail goto*//*Label 2134*/ GIMT_Encode4(103647), // Rule ID 4178 //
36005 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
36006 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
36007 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
36008 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
36009 // (st FPR128:{ *:[v16i8] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroW FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
36010 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
36011 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
36012 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
36013 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
36014 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
36015 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36016 GIR_RootConstrainSelectedInstOperands,
36017 // GIR_Coverage, 4178,
36018 GIR_EraseRootFromParent_Done,
36019 // Label 2134: @103647
36020 GIM_Try, /*On fail goto*//*Label 2135*/ GIMT_Encode4(103696), // Rule ID 4179 //
36021 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
36022 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
36023 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
36024 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
36025 // (st FPR128:{ *:[v16i8] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQroX FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
36026 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
36027 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
36028 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
36029 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
36030 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
36031 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36032 GIR_RootConstrainSelectedInstOperands,
36033 // GIR_Coverage, 4179,
36034 GIR_EraseRootFromParent_Done,
36035 // Label 2135: @103696
36036 GIM_Try, /*On fail goto*//*Label 2136*/ GIMT_Encode4(103740), // Rule ID 4208 //
36037 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
36038 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
36039 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
36040 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
36041 // (st FPR128:{ *:[v16i8] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STRQui FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
36042 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
36043 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
36044 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
36045 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
36046 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36047 GIR_RootConstrainSelectedInstOperands,
36048 // GIR_Coverage, 4208,
36049 GIR_EraseRootFromParent_Done,
36050 // Label 2136: @103740
36051 GIM_Try, /*On fail goto*//*Label 2137*/ GIMT_Encode4(103784), // Rule ID 4235 //
36052 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
36053 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
36054 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
36055 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
36056 // (st FPR128:{ *:[v16i8] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STURQi FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
36057 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
36058 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
36059 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
36060 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
36061 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36062 GIR_RootConstrainSelectedInstOperands,
36063 // GIR_Coverage, 4235,
36064 GIR_EraseRootFromParent_Done,
36065 // Label 2137: @103784
36066 GIM_Try, /*On fail goto*//*Label 2138*/ GIMT_Encode4(103804), // Rule ID 5998 //
36067 // MIs[0] Rn
36068 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36069 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36070 // (st v16i8:{ *:[v16i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1Onev16b v16i8:{ *:[v16i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
36071 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev16b),
36072 GIR_RootConstrainSelectedInstOperands,
36073 // GIR_Coverage, 5998,
36074 GIR_Done,
36075 // Label 2138: @103804
36076 GIM_Reject,
36077 // Label 2133: @103805
36078 GIM_Reject,
36079 // Label 1913: @103806
36080 GIM_Try, /*On fail goto*//*Label 2139*/ GIMT_Encode4(103915),
36081 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
36082 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
36083 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36084 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36085 GIM_Try, /*On fail goto*//*Label 2140*/ GIMT_Encode4(103870), // Rule ID 10531 //
36086 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
36087 // (st nxv2f16:{ *:[nxv2f16] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1H_D_IMM ZPR:{ *:[nxv2f16] }:$val, (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
36088 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
36089 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
36090 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36091 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
36092 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36093 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1H_D_IMM),
36094 GIR_RootToRootCopy, /*OpIdx*/0, // val
36095 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36096 GIR_RootToRootCopy, /*OpIdx*/1, // base
36097 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36098 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36099 GIR_RootConstrainSelectedInstOperands,
36100 // GIR_Coverage, 10531,
36101 GIR_EraseRootFromParent_Done,
36102 // Label 2140: @103870
36103 GIM_Try, /*On fail goto*//*Label 2141*/ GIMT_Encode4(103914), // Rule ID 10534 //
36104 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
36105 // (st nxv2bf16:{ *:[nxv2bf16] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1H_D_IMM ZPR:{ *:[nxv2bf16] }:$val, (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
36106 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
36107 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
36108 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36109 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
36110 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36111 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1H_D_IMM),
36112 GIR_RootToRootCopy, /*OpIdx*/0, // val
36113 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36114 GIR_RootToRootCopy, /*OpIdx*/1, // base
36115 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36116 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36117 GIR_RootConstrainSelectedInstOperands,
36118 // GIR_Coverage, 10534,
36119 GIR_EraseRootFromParent_Done,
36120 // Label 2141: @103914
36121 GIM_Reject,
36122 // Label 2139: @103915
36123 GIM_Reject,
36124 // Label 1914: @103916
36125 GIM_Try, /*On fail goto*//*Label 2142*/ GIMT_Encode4(103975), // Rule ID 10540 //
36126 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
36127 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
36128 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
36129 // MIs[0] base
36130 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36131 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36132 // (st nxv2f32:{ *:[nxv2f32] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1W_D_IMM ZPR:{ *:[nxv2f32] }:$val, (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
36133 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
36134 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
36135 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36136 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
36137 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36138 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1W_D_IMM),
36139 GIR_RootToRootCopy, /*OpIdx*/0, // val
36140 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36141 GIR_RootToRootCopy, /*OpIdx*/1, // base
36142 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36143 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36144 GIR_RootConstrainSelectedInstOperands,
36145 // GIR_Coverage, 10540,
36146 GIR_EraseRootFromParent_Done,
36147 // Label 2142: @103975
36148 GIM_Reject,
36149 // Label 1915: @103976
36150 GIM_Try, /*On fail goto*//*Label 2143*/ GIMT_Encode4(104085),
36151 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
36152 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
36153 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36154 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36155 GIM_Try, /*On fail goto*//*Label 2144*/ GIMT_Encode4(104040), // Rule ID 10516 //
36156 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
36157 // (st nxv2i64:{ *:[nxv2i64] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1D_IMM ZPR:{ *:[nxv2i64] }:$val, (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
36158 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
36159 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
36160 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36161 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
36162 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36163 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1D_IMM),
36164 GIR_RootToRootCopy, /*OpIdx*/0, // val
36165 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36166 GIR_RootToRootCopy, /*OpIdx*/1, // base
36167 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36168 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36169 GIR_RootConstrainSelectedInstOperands,
36170 // GIR_Coverage, 10516,
36171 GIR_EraseRootFromParent_Done,
36172 // Label 2144: @104040
36173 GIM_Try, /*On fail goto*//*Label 2145*/ GIMT_Encode4(104084), // Rule ID 10543 //
36174 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
36175 // (st nxv2f64:{ *:[nxv2f64] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1D_IMM ZPR:{ *:[nxv2f64] }:$val, (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
36176 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
36177 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
36178 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36179 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
36180 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36181 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1D_IMM),
36182 GIR_RootToRootCopy, /*OpIdx*/0, // val
36183 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36184 GIR_RootToRootCopy, /*OpIdx*/1, // base
36185 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36186 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36187 GIR_RootConstrainSelectedInstOperands,
36188 // GIR_Coverage, 10543,
36189 GIR_EraseRootFromParent_Done,
36190 // Label 2145: @104084
36191 GIM_Reject,
36192 // Label 2143: @104085
36193 GIM_Reject,
36194 // Label 1916: @104086
36195 GIM_Try, /*On fail goto*//*Label 2146*/ GIMT_Encode4(104195),
36196 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
36197 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
36198 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36199 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36200 GIM_Try, /*On fail goto*//*Label 2147*/ GIMT_Encode4(104150), // Rule ID 10525 //
36201 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
36202 // (st nxv4f16:{ *:[nxv4f16] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1H_S_IMM ZPR:{ *:[nxv4f16] }:$val, (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
36203 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
36204 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
36205 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36206 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
36207 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36208 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1H_S_IMM),
36209 GIR_RootToRootCopy, /*OpIdx*/0, // val
36210 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36211 GIR_RootToRootCopy, /*OpIdx*/1, // base
36212 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36213 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36214 GIR_RootConstrainSelectedInstOperands,
36215 // GIR_Coverage, 10525,
36216 GIR_EraseRootFromParent_Done,
36217 // Label 2147: @104150
36218 GIM_Try, /*On fail goto*//*Label 2148*/ GIMT_Encode4(104194), // Rule ID 10528 //
36219 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
36220 // (st nxv4bf16:{ *:[nxv4bf16] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1H_S_IMM ZPR:{ *:[nxv4bf16] }:$val, (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
36221 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
36222 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
36223 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36224 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
36225 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36226 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1H_S_IMM),
36227 GIR_RootToRootCopy, /*OpIdx*/0, // val
36228 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36229 GIR_RootToRootCopy, /*OpIdx*/1, // base
36230 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36231 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36232 GIR_RootConstrainSelectedInstOperands,
36233 // GIR_Coverage, 10528,
36234 GIR_EraseRootFromParent_Done,
36235 // Label 2148: @104194
36236 GIM_Reject,
36237 // Label 2146: @104195
36238 GIM_Reject,
36239 // Label 1917: @104196
36240 GIM_Try, /*On fail goto*//*Label 2149*/ GIMT_Encode4(104305),
36241 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
36242 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
36243 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36244 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36245 GIM_Try, /*On fail goto*//*Label 2150*/ GIMT_Encode4(104260), // Rule ID 10510 //
36246 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
36247 // (st nxv4i32:{ *:[nxv4i32] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1W_IMM ZPR:{ *:[nxv4i32] }:$val, (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
36248 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
36249 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
36250 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36251 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
36252 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36253 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1W_IMM),
36254 GIR_RootToRootCopy, /*OpIdx*/0, // val
36255 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36256 GIR_RootToRootCopy, /*OpIdx*/1, // base
36257 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36258 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36259 GIR_RootConstrainSelectedInstOperands,
36260 // GIR_Coverage, 10510,
36261 GIR_EraseRootFromParent_Done,
36262 // Label 2150: @104260
36263 GIM_Try, /*On fail goto*//*Label 2151*/ GIMT_Encode4(104304), // Rule ID 10537 //
36264 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
36265 // (st nxv4f32:{ *:[nxv4f32] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1W_IMM ZPR:{ *:[nxv4f32] }:$val, (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
36266 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
36267 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
36268 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36269 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
36270 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36271 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1W_IMM),
36272 GIR_RootToRootCopy, /*OpIdx*/0, // val
36273 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36274 GIR_RootToRootCopy, /*OpIdx*/1, // base
36275 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36276 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36277 GIR_RootConstrainSelectedInstOperands,
36278 // GIR_Coverage, 10537,
36279 GIR_EraseRootFromParent_Done,
36280 // Label 2151: @104304
36281 GIM_Reject,
36282 // Label 2149: @104305
36283 GIM_Reject,
36284 // Label 1918: @104306
36285 GIM_Try, /*On fail goto*//*Label 2152*/ GIMT_Encode4(104459),
36286 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
36287 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
36288 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36289 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36290 GIM_Try, /*On fail goto*//*Label 2153*/ GIMT_Encode4(104370), // Rule ID 10501 //
36291 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
36292 // (st nxv8i16:{ *:[nxv8i16] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1H_IMM ZPR:{ *:[nxv8i16] }:$val, (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
36293 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
36294 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
36295 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36296 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
36297 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36298 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1H_IMM),
36299 GIR_RootToRootCopy, /*OpIdx*/0, // val
36300 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36301 GIR_RootToRootCopy, /*OpIdx*/1, // base
36302 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36303 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36304 GIR_RootConstrainSelectedInstOperands,
36305 // GIR_Coverage, 10501,
36306 GIR_EraseRootFromParent_Done,
36307 // Label 2153: @104370
36308 GIM_Try, /*On fail goto*//*Label 2154*/ GIMT_Encode4(104414), // Rule ID 10519 //
36309 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
36310 // (st nxv8f16:{ *:[nxv8f16] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1H_IMM ZPR:{ *:[nxv8f16] }:$val, (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
36311 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
36312 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
36313 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36314 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
36315 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36316 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1H_IMM),
36317 GIR_RootToRootCopy, /*OpIdx*/0, // val
36318 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36319 GIR_RootToRootCopy, /*OpIdx*/1, // base
36320 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36321 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36322 GIR_RootConstrainSelectedInstOperands,
36323 // GIR_Coverage, 10519,
36324 GIR_EraseRootFromParent_Done,
36325 // Label 2154: @104414
36326 GIM_Try, /*On fail goto*//*Label 2155*/ GIMT_Encode4(104458), // Rule ID 10522 //
36327 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
36328 // (st nxv8bf16:{ *:[nxv8bf16] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1H_IMM ZPR:{ *:[nxv8bf16] }:$val, (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
36329 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
36330 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
36331 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36332 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
36333 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36334 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1H_IMM),
36335 GIR_RootToRootCopy, /*OpIdx*/0, // val
36336 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36337 GIR_RootToRootCopy, /*OpIdx*/1, // base
36338 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36339 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36340 GIR_RootConstrainSelectedInstOperands,
36341 // GIR_Coverage, 10522,
36342 GIR_EraseRootFromParent_Done,
36343 // Label 2155: @104458
36344 GIM_Reject,
36345 // Label 2152: @104459
36346 GIM_Reject,
36347 // Label 1919: @104460
36348 GIM_Try, /*On fail goto*//*Label 2156*/ GIMT_Encode4(104503), // Rule ID 2370 //
36349 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
36350 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
36351 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
36352 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
36353 // MIs[0] base
36354 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36355 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36356 // (st PPR:{ *:[nxv16i1] }:$Val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (STR_PXI PPR:{ *:[nxv16i1] }:$Val, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
36357 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STR_PXI),
36358 GIR_RootToRootCopy, /*OpIdx*/0, // Val
36359 GIR_RootToRootCopy, /*OpIdx*/1, // base
36360 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36361 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36362 GIR_RootConstrainSelectedInstOperands,
36363 // GIR_Coverage, 2370,
36364 GIR_EraseRootFromParent_Done,
36365 // Label 2156: @104503
36366 GIM_Reject,
36367 // Label 1920: @104504
36368 GIM_Try, /*On fail goto*//*Label 2157*/ GIMT_Encode4(104563), // Rule ID 10487 //
36369 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
36370 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
36371 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
36372 // MIs[0] base
36373 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36374 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36375 // (st nxv16i8:{ *:[nxv16i8] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (ST1B_IMM ZPR:{ *:[nxv16i8] }:$val, (PTRUE_B:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
36376 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
36377 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_B),
36378 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
36379 GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
36380 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
36381 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1B_IMM),
36382 GIR_RootToRootCopy, /*OpIdx*/0, // val
36383 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36384 GIR_RootToRootCopy, /*OpIdx*/1, // base
36385 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36386 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36387 GIR_RootConstrainSelectedInstOperands,
36388 // GIR_Coverage, 10487,
36389 GIR_EraseRootFromParent_Done,
36390 // Label 2157: @104563
36391 GIM_Reject,
36392 // Label 1921: @104564
36393 GIM_Reject,
36394 // Label 20: @104565
36395 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2160*/ GIMT_Encode4(105915),
36396 /*GILLT_s32*//*Label 2158*/ GIMT_Encode4(104584),
36397 /*GILLT_s64*//*Label 2159*/ GIMT_Encode4(105602),
36398 // Label 2158: @104584
36399 GIM_Try, /*On fail goto*//*Label 2161*/ GIMT_Encode4(105601),
36400 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36401 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36402 GIM_Try, /*On fail goto*//*Label 2162*/ GIMT_Encode4(104650), // Rule ID 7028 //
36403 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36404 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
36405 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
36406 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36407 // MIs[0] Rn
36408 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36409 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36410 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36411 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36412 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_monotonic>> => (CASW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36413 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASW),
36414 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36415 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36416 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36417 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36418 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36419 GIR_RootConstrainSelectedInstOperands,
36420 // GIR_Coverage, 7028,
36421 GIR_EraseRootFromParent_Done,
36422 // Label 2162: @104650
36423 GIM_Try, /*On fail goto*//*Label 2163*/ GIMT_Encode4(104705), // Rule ID 7029 //
36424 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36425 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
36426 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
36427 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36428 // MIs[0] Rn
36429 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36430 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36431 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36432 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36433 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_acquire>> => (CASAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36434 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASAW),
36435 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36436 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36437 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36438 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36439 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36440 GIR_RootConstrainSelectedInstOperands,
36441 // GIR_Coverage, 7029,
36442 GIR_EraseRootFromParent_Done,
36443 // Label 2163: @104705
36444 GIM_Try, /*On fail goto*//*Label 2164*/ GIMT_Encode4(104760), // Rule ID 7030 //
36445 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36446 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
36447 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
36448 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36449 // MIs[0] Rn
36450 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36451 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36452 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36453 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36454 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_release>> => (CASLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36455 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASLW),
36456 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36457 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36458 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36459 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36460 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36461 GIR_RootConstrainSelectedInstOperands,
36462 // GIR_Coverage, 7030,
36463 GIR_EraseRootFromParent_Done,
36464 // Label 2164: @104760
36465 GIM_Try, /*On fail goto*//*Label 2165*/ GIMT_Encode4(104815), // Rule ID 7031 //
36466 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36467 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
36468 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
36469 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36470 // MIs[0] Rn
36471 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36472 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36473 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36474 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36475 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_acq_rel>> => (CASALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36476 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALW),
36477 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36478 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36479 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36480 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36481 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36482 GIR_RootConstrainSelectedInstOperands,
36483 // GIR_Coverage, 7031,
36484 GIR_EraseRootFromParent_Done,
36485 // Label 2165: @104815
36486 GIM_Try, /*On fail goto*//*Label 2166*/ GIMT_Encode4(104870), // Rule ID 7032 //
36487 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36488 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
36489 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
36490 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36491 // MIs[0] Rn
36492 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36493 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36494 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36495 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36496 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_seq_cst>> => (CASALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36497 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALW),
36498 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36499 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36500 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36501 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36502 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36503 GIR_RootConstrainSelectedInstOperands,
36504 // GIR_Coverage, 7032,
36505 GIR_EraseRootFromParent_Done,
36506 // Label 2166: @104870
36507 GIM_Try, /*On fail goto*//*Label 2167*/ GIMT_Encode4(104925), // Rule ID 7033 //
36508 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36509 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
36510 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
36511 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36512 // MIs[0] Rn
36513 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36514 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36515 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36516 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36517 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_monotonic>> => (CASH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36518 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASH),
36519 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36520 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36521 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36522 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36523 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36524 GIR_RootConstrainSelectedInstOperands,
36525 // GIR_Coverage, 7033,
36526 GIR_EraseRootFromParent_Done,
36527 // Label 2167: @104925
36528 GIM_Try, /*On fail goto*//*Label 2168*/ GIMT_Encode4(104980), // Rule ID 7034 //
36529 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36530 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
36531 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
36532 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36533 // MIs[0] Rn
36534 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36535 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36536 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36537 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36538 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_acquire>> => (CASAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36539 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASAH),
36540 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36541 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36542 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36543 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36544 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36545 GIR_RootConstrainSelectedInstOperands,
36546 // GIR_Coverage, 7034,
36547 GIR_EraseRootFromParent_Done,
36548 // Label 2168: @104980
36549 GIM_Try, /*On fail goto*//*Label 2169*/ GIMT_Encode4(105035), // Rule ID 7035 //
36550 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36551 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
36552 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
36553 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36554 // MIs[0] Rn
36555 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36556 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36557 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36558 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36559 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_release>> => (CASLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36560 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASLH),
36561 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36562 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36563 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36564 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36565 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36566 GIR_RootConstrainSelectedInstOperands,
36567 // GIR_Coverage, 7035,
36568 GIR_EraseRootFromParent_Done,
36569 // Label 2169: @105035
36570 GIM_Try, /*On fail goto*//*Label 2170*/ GIMT_Encode4(105090), // Rule ID 7036 //
36571 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36572 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
36573 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
36574 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36575 // MIs[0] Rn
36576 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36577 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36578 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36579 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36580 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_acq_rel>> => (CASALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36581 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALH),
36582 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36583 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36584 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36585 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36586 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36587 GIR_RootConstrainSelectedInstOperands,
36588 // GIR_Coverage, 7036,
36589 GIR_EraseRootFromParent_Done,
36590 // Label 2170: @105090
36591 GIM_Try, /*On fail goto*//*Label 2171*/ GIMT_Encode4(105145), // Rule ID 7037 //
36592 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36593 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
36594 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
36595 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36596 // MIs[0] Rn
36597 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36598 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36599 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36600 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36601 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_seq_cst>> => (CASALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36602 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALH),
36603 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36604 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36605 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36606 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36607 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36608 GIR_RootConstrainSelectedInstOperands,
36609 // GIR_Coverage, 7037,
36610 GIR_EraseRootFromParent_Done,
36611 // Label 2171: @105145
36612 GIM_Try, /*On fail goto*//*Label 2172*/ GIMT_Encode4(105200), // Rule ID 7038 //
36613 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36614 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
36615 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
36616 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36617 // MIs[0] Rn
36618 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36619 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36620 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36621 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36622 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_monotonic>> => (CASB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36623 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASB),
36624 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36625 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36626 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36627 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36628 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36629 GIR_RootConstrainSelectedInstOperands,
36630 // GIR_Coverage, 7038,
36631 GIR_EraseRootFromParent_Done,
36632 // Label 2172: @105200
36633 GIM_Try, /*On fail goto*//*Label 2173*/ GIMT_Encode4(105255), // Rule ID 7039 //
36634 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36635 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
36636 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
36637 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36638 // MIs[0] Rn
36639 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36640 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36641 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36642 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36643 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_acquire>> => (CASAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36644 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASAB),
36645 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36646 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36647 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36648 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36649 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36650 GIR_RootConstrainSelectedInstOperands,
36651 // GIR_Coverage, 7039,
36652 GIR_EraseRootFromParent_Done,
36653 // Label 2173: @105255
36654 GIM_Try, /*On fail goto*//*Label 2174*/ GIMT_Encode4(105310), // Rule ID 7040 //
36655 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36656 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
36657 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
36658 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36659 // MIs[0] Rn
36660 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36661 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36662 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36663 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36664 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_release>> => (CASLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36665 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASLB),
36666 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36667 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36668 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36669 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36670 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36671 GIR_RootConstrainSelectedInstOperands,
36672 // GIR_Coverage, 7040,
36673 GIR_EraseRootFromParent_Done,
36674 // Label 2174: @105310
36675 GIM_Try, /*On fail goto*//*Label 2175*/ GIMT_Encode4(105365), // Rule ID 7041 //
36676 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36677 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
36678 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
36679 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36680 // MIs[0] Rn
36681 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36682 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36683 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36684 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36685 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_acq_rel>> => (CASALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36686 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALB),
36687 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36688 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36689 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36690 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36691 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36692 GIR_RootConstrainSelectedInstOperands,
36693 // GIR_Coverage, 7041,
36694 GIR_EraseRootFromParent_Done,
36695 // Label 2175: @105365
36696 GIM_Try, /*On fail goto*//*Label 2176*/ GIMT_Encode4(105420), // Rule ID 7042 //
36697 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36698 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
36699 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
36700 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36701 // MIs[0] Rn
36702 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36703 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36704 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36705 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36706 // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_seq_cst>> => (CASALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36707 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALB),
36708 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36709 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36710 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36711 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36712 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36713 GIR_RootConstrainSelectedInstOperands,
36714 // GIR_Coverage, 7042,
36715 GIR_EraseRootFromParent_Done,
36716 // Label 2176: @105420
36717 GIM_Try, /*On fail goto*//*Label 2177*/ GIMT_Encode4(105480), // Rule ID 12364 //
36718 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoLSE),
36719 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
36720 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36721 // MIs[0] addr
36722 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36723 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36724 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36725 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36726 // (atomic_cmp_swap:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i8>> => (CMP_SWAP_8:{ *:[i32] }:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)
36727 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
36728 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMP_SWAP_8),
36729 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36730 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
36731 GIR_RootToRootCopy, /*OpIdx*/1, // addr
36732 GIR_RootToRootCopy, /*OpIdx*/2, // desired
36733 GIR_RootToRootCopy, /*OpIdx*/3, // new
36734 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36735 GIR_RootConstrainSelectedInstOperands,
36736 // GIR_Coverage, 12364,
36737 GIR_EraseRootFromParent_Done,
36738 // Label 2177: @105480
36739 GIM_Try, /*On fail goto*//*Label 2178*/ GIMT_Encode4(105540), // Rule ID 12365 //
36740 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoLSE),
36741 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
36742 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36743 // MIs[0] addr
36744 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36745 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36746 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36747 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36748 // (atomic_cmp_swap:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i16>> => (CMP_SWAP_16:{ *:[i32] }:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)
36749 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
36750 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMP_SWAP_16),
36751 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36752 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
36753 GIR_RootToRootCopy, /*OpIdx*/1, // addr
36754 GIR_RootToRootCopy, /*OpIdx*/2, // desired
36755 GIR_RootToRootCopy, /*OpIdx*/3, // new
36756 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36757 GIR_RootConstrainSelectedInstOperands,
36758 // GIR_Coverage, 12365,
36759 GIR_EraseRootFromParent_Done,
36760 // Label 2178: @105540
36761 GIM_Try, /*On fail goto*//*Label 2179*/ GIMT_Encode4(105600), // Rule ID 12366 //
36762 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoLSE),
36763 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
36764 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36765 // MIs[0] addr
36766 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36767 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36768 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36769 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36770 // (atomic_cmp_swap:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>> => (CMP_SWAP_32:{ *:[i32] }:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)
36771 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
36772 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMP_SWAP_32),
36773 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36774 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
36775 GIR_RootToRootCopy, /*OpIdx*/1, // addr
36776 GIR_RootToRootCopy, /*OpIdx*/2, // desired
36777 GIR_RootToRootCopy, /*OpIdx*/3, // new
36778 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36779 GIR_RootConstrainSelectedInstOperands,
36780 // GIR_Coverage, 12366,
36781 GIR_EraseRootFromParent_Done,
36782 // Label 2179: @105600
36783 GIM_Reject,
36784 // Label 2161: @105601
36785 GIM_Reject,
36786 // Label 2159: @105602
36787 GIM_Try, /*On fail goto*//*Label 2180*/ GIMT_Encode4(105914),
36788 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
36789 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
36790 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
36791 GIM_Try, /*On fail goto*//*Label 2181*/ GIMT_Encode4(105668), // Rule ID 2494 //
36792 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36793 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
36794 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36795 // MIs[0] Rn
36796 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36797 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36798 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36799 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36800 // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_monotonic>> => (CASX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36801 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASX),
36802 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36803 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36804 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36805 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36806 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36807 GIR_RootConstrainSelectedInstOperands,
36808 // GIR_Coverage, 2494,
36809 GIR_EraseRootFromParent_Done,
36810 // Label 2181: @105668
36811 GIM_Try, /*On fail goto*//*Label 2182*/ GIMT_Encode4(105716), // Rule ID 2495 //
36812 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36813 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
36814 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36815 // MIs[0] Rn
36816 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36817 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36818 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36819 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36820 // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_acquire>> => (CASAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36821 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASAX),
36822 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36823 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36824 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36825 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36826 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36827 GIR_RootConstrainSelectedInstOperands,
36828 // GIR_Coverage, 2495,
36829 GIR_EraseRootFromParent_Done,
36830 // Label 2182: @105716
36831 GIM_Try, /*On fail goto*//*Label 2183*/ GIMT_Encode4(105764), // Rule ID 2496 //
36832 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36833 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
36834 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36835 // MIs[0] Rn
36836 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36837 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36838 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36839 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36840 // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_release>> => (CASLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36841 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASLX),
36842 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36843 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36844 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36845 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36846 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36847 GIR_RootConstrainSelectedInstOperands,
36848 // GIR_Coverage, 2496,
36849 GIR_EraseRootFromParent_Done,
36850 // Label 2183: @105764
36851 GIM_Try, /*On fail goto*//*Label 2184*/ GIMT_Encode4(105812), // Rule ID 2497 //
36852 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36853 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
36854 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36855 // MIs[0] Rn
36856 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36857 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36858 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36859 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36860 // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_acq_rel>> => (CASALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36861 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALX),
36862 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36863 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36864 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36865 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36866 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36867 GIR_RootConstrainSelectedInstOperands,
36868 // GIR_Coverage, 2497,
36869 GIR_EraseRootFromParent_Done,
36870 // Label 2184: @105812
36871 GIM_Try, /*On fail goto*//*Label 2185*/ GIMT_Encode4(105860), // Rule ID 2498 //
36872 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36873 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
36874 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36875 // MIs[0] Rn
36876 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36877 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36878 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36879 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36880 // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_seq_cst>> => (CASALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
36881 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALX),
36882 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
36883 GIR_RootToRootCopy, /*OpIdx*/2, // Rold
36884 GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
36885 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36886 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36887 GIR_RootConstrainSelectedInstOperands,
36888 // GIR_Coverage, 2498,
36889 GIR_EraseRootFromParent_Done,
36890 // Label 2185: @105860
36891 GIM_Try, /*On fail goto*//*Label 2186*/ GIMT_Encode4(105913), // Rule ID 12367 //
36892 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoLSE),
36893 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36894 // MIs[0] addr
36895 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36896 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36897 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36898 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
36899 // (atomic_cmp_swap:{ *:[i64] } GPR64:{ *:[i64] }:$addr, GPR64:{ *:[i64] }:$desired, GPR64:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i64>> => (CMP_SWAP_64:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR64:{ *:[i64] }:$desired, GPR64:{ *:[i64] }:$new)
36900 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
36901 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMP_SWAP_64),
36902 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36903 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
36904 GIR_RootToRootCopy, /*OpIdx*/1, // addr
36905 GIR_RootToRootCopy, /*OpIdx*/2, // desired
36906 GIR_RootToRootCopy, /*OpIdx*/3, // new
36907 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36908 GIR_RootConstrainSelectedInstOperands,
36909 // GIR_Coverage, 12367,
36910 GIR_EraseRootFromParent_Done,
36911 // Label 2186: @105913
36912 GIM_Reject,
36913 // Label 2180: @105914
36914 GIM_Reject,
36915 // Label 2160: @105915
36916 GIM_Reject,
36917 // Label 21: @105916
36918 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2189*/ GIMT_Encode4(106907),
36919 /*GILLT_s32*//*Label 2187*/ GIMT_Encode4(105935),
36920 /*GILLT_s64*//*Label 2188*/ GIMT_Encode4(106680),
36921 // Label 2187: @105935
36922 GIM_Try, /*On fail goto*//*Label 2190*/ GIMT_Encode4(106679),
36923 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36924 GIM_Try, /*On fail goto*//*Label 2191*/ GIMT_Encode4(105992), // Rule ID 7013 //
36925 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36926 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
36927 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
36928 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36929 // MIs[0] Rn
36930 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36931 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36932 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36933 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_monotonic>> => (SWPW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
36934 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPW),
36935 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
36936 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36937 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36938 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36939 GIR_RootConstrainSelectedInstOperands,
36940 // GIR_Coverage, 7013,
36941 GIR_EraseRootFromParent_Done,
36942 // Label 2191: @105992
36943 GIM_Try, /*On fail goto*//*Label 2192*/ GIMT_Encode4(106041), // Rule ID 7014 //
36944 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36945 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
36946 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
36947 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36948 // MIs[0] Rn
36949 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36950 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36951 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36952 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acquire>> => (SWPAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
36953 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPAW),
36954 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
36955 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36956 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36957 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36958 GIR_RootConstrainSelectedInstOperands,
36959 // GIR_Coverage, 7014,
36960 GIR_EraseRootFromParent_Done,
36961 // Label 2192: @106041
36962 GIM_Try, /*On fail goto*//*Label 2193*/ GIMT_Encode4(106090), // Rule ID 7015 //
36963 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36964 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
36965 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
36966 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36967 // MIs[0] Rn
36968 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36969 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36970 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36971 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_release>> => (SWPLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
36972 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPLW),
36973 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
36974 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36975 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36976 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36977 GIR_RootConstrainSelectedInstOperands,
36978 // GIR_Coverage, 7015,
36979 GIR_EraseRootFromParent_Done,
36980 // Label 2193: @106090
36981 GIM_Try, /*On fail goto*//*Label 2194*/ GIMT_Encode4(106139), // Rule ID 7016 //
36982 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
36983 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
36984 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
36985 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36986 // MIs[0] Rn
36987 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
36988 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
36989 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
36990 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acq_rel>> => (SWPALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
36991 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALW),
36992 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
36993 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36994 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36995 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36996 GIR_RootConstrainSelectedInstOperands,
36997 // GIR_Coverage, 7016,
36998 GIR_EraseRootFromParent_Done,
36999 // Label 2194: @106139
37000 GIM_Try, /*On fail goto*//*Label 2195*/ GIMT_Encode4(106188), // Rule ID 7017 //
37001 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37002 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
37003 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
37004 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37005 // MIs[0] Rn
37006 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37007 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37008 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37009 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_seq_cst>> => (SWPALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37010 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALW),
37011 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37012 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37013 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37014 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37015 GIR_RootConstrainSelectedInstOperands,
37016 // GIR_Coverage, 7017,
37017 GIR_EraseRootFromParent_Done,
37018 // Label 2195: @106188
37019 GIM_Try, /*On fail goto*//*Label 2196*/ GIMT_Encode4(106237), // Rule ID 7018 //
37020 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37021 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
37022 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
37023 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37024 // MIs[0] Rn
37025 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37026 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37027 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37028 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_monotonic>> => (SWPH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37029 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPH),
37030 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37031 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37032 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37033 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37034 GIR_RootConstrainSelectedInstOperands,
37035 // GIR_Coverage, 7018,
37036 GIR_EraseRootFromParent_Done,
37037 // Label 2196: @106237
37038 GIM_Try, /*On fail goto*//*Label 2197*/ GIMT_Encode4(106286), // Rule ID 7019 //
37039 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37040 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
37041 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
37042 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37043 // MIs[0] Rn
37044 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37045 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37046 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37047 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_acquire>> => (SWPAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37048 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPAH),
37049 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37050 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37051 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37052 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37053 GIR_RootConstrainSelectedInstOperands,
37054 // GIR_Coverage, 7019,
37055 GIR_EraseRootFromParent_Done,
37056 // Label 2197: @106286
37057 GIM_Try, /*On fail goto*//*Label 2198*/ GIMT_Encode4(106335), // Rule ID 7020 //
37058 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37059 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
37060 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
37061 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37062 // MIs[0] Rn
37063 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37064 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37065 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37066 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_release>> => (SWPLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37067 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPLH),
37068 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37069 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37070 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37071 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37072 GIR_RootConstrainSelectedInstOperands,
37073 // GIR_Coverage, 7020,
37074 GIR_EraseRootFromParent_Done,
37075 // Label 2198: @106335
37076 GIM_Try, /*On fail goto*//*Label 2199*/ GIMT_Encode4(106384), // Rule ID 7021 //
37077 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37078 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
37079 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
37080 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37081 // MIs[0] Rn
37082 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37083 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37084 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37085 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_acq_rel>> => (SWPALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37086 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALH),
37087 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37088 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37089 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37090 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37091 GIR_RootConstrainSelectedInstOperands,
37092 // GIR_Coverage, 7021,
37093 GIR_EraseRootFromParent_Done,
37094 // Label 2199: @106384
37095 GIM_Try, /*On fail goto*//*Label 2200*/ GIMT_Encode4(106433), // Rule ID 7022 //
37096 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37097 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
37098 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
37099 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37100 // MIs[0] Rn
37101 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37102 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37103 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37104 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_seq_cst>> => (SWPALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37105 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALH),
37106 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37107 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37108 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37109 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37110 GIR_RootConstrainSelectedInstOperands,
37111 // GIR_Coverage, 7022,
37112 GIR_EraseRootFromParent_Done,
37113 // Label 2200: @106433
37114 GIM_Try, /*On fail goto*//*Label 2201*/ GIMT_Encode4(106482), // Rule ID 7023 //
37115 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37116 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
37117 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
37118 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37119 // MIs[0] Rn
37120 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37121 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37122 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37123 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_monotonic>> => (SWPB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37124 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPB),
37125 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37126 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37127 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37128 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37129 GIR_RootConstrainSelectedInstOperands,
37130 // GIR_Coverage, 7023,
37131 GIR_EraseRootFromParent_Done,
37132 // Label 2201: @106482
37133 GIM_Try, /*On fail goto*//*Label 2202*/ GIMT_Encode4(106531), // Rule ID 7024 //
37134 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37135 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
37136 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
37137 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37138 // MIs[0] Rn
37139 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37140 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37141 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37142 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_acquire>> => (SWPAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37143 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPAB),
37144 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37145 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37146 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37147 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37148 GIR_RootConstrainSelectedInstOperands,
37149 // GIR_Coverage, 7024,
37150 GIR_EraseRootFromParent_Done,
37151 // Label 2202: @106531
37152 GIM_Try, /*On fail goto*//*Label 2203*/ GIMT_Encode4(106580), // Rule ID 7025 //
37153 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37154 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
37155 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
37156 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37157 // MIs[0] Rn
37158 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37159 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37160 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37161 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_release>> => (SWPLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37162 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPLB),
37163 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37164 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37165 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37166 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37167 GIR_RootConstrainSelectedInstOperands,
37168 // GIR_Coverage, 7025,
37169 GIR_EraseRootFromParent_Done,
37170 // Label 2203: @106580
37171 GIM_Try, /*On fail goto*//*Label 2204*/ GIMT_Encode4(106629), // Rule ID 7026 //
37172 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37173 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
37174 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
37175 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37176 // MIs[0] Rn
37177 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37178 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37179 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37180 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_acq_rel>> => (SWPALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37181 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALB),
37182 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37183 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37184 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37185 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37186 GIR_RootConstrainSelectedInstOperands,
37187 // GIR_Coverage, 7026,
37188 GIR_EraseRootFromParent_Done,
37189 // Label 2204: @106629
37190 GIM_Try, /*On fail goto*//*Label 2205*/ GIMT_Encode4(106678), // Rule ID 7027 //
37191 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37192 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
37193 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
37194 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37195 // MIs[0] Rn
37196 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37197 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37198 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37199 // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_seq_cst>> => (SWPALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37200 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALB),
37201 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37202 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37203 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37204 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37205 GIR_RootConstrainSelectedInstOperands,
37206 // GIR_Coverage, 7027,
37207 GIR_EraseRootFromParent_Done,
37208 // Label 2205: @106678
37209 GIM_Reject,
37210 // Label 2190: @106679
37211 GIM_Reject,
37212 // Label 2188: @106680
37213 GIM_Try, /*On fail goto*//*Label 2206*/ GIMT_Encode4(106906),
37214 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
37215 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
37216 GIM_Try, /*On fail goto*//*Label 2207*/ GIMT_Encode4(106737), // Rule ID 7008 //
37217 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37218 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
37219 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37220 // MIs[0] Rn
37221 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37222 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37223 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37224 // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_monotonic>> => (SWPX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37225 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPX),
37226 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37227 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37228 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37229 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37230 GIR_RootConstrainSelectedInstOperands,
37231 // GIR_Coverage, 7008,
37232 GIR_EraseRootFromParent_Done,
37233 // Label 2207: @106737
37234 GIM_Try, /*On fail goto*//*Label 2208*/ GIMT_Encode4(106779), // Rule ID 7009 //
37235 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37236 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
37237 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37238 // MIs[0] Rn
37239 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37240 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37241 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37242 // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_acquire>> => (SWPAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37243 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPAX),
37244 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37245 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37246 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37247 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37248 GIR_RootConstrainSelectedInstOperands,
37249 // GIR_Coverage, 7009,
37250 GIR_EraseRootFromParent_Done,
37251 // Label 2208: @106779
37252 GIM_Try, /*On fail goto*//*Label 2209*/ GIMT_Encode4(106821), // Rule ID 7010 //
37253 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37254 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
37255 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37256 // MIs[0] Rn
37257 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37258 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37259 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37260 // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_release>> => (SWPLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37261 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPLX),
37262 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37263 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37264 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37265 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37266 GIR_RootConstrainSelectedInstOperands,
37267 // GIR_Coverage, 7010,
37268 GIR_EraseRootFromParent_Done,
37269 // Label 2209: @106821
37270 GIM_Try, /*On fail goto*//*Label 2210*/ GIMT_Encode4(106863), // Rule ID 7011 //
37271 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37272 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
37273 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37274 // MIs[0] Rn
37275 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37276 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37277 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37278 // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_acq_rel>> => (SWPALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37279 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALX),
37280 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37281 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37282 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37283 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37284 GIR_RootConstrainSelectedInstOperands,
37285 // GIR_Coverage, 7011,
37286 GIR_EraseRootFromParent_Done,
37287 // Label 2210: @106863
37288 GIM_Try, /*On fail goto*//*Label 2211*/ GIMT_Encode4(106905), // Rule ID 7012 //
37289 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37290 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
37291 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37292 // MIs[0] Rn
37293 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37294 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37295 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37296 // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_seq_cst>> => (SWPALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37297 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALX),
37298 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37299 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37300 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37301 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37302 GIR_RootConstrainSelectedInstOperands,
37303 // GIR_Coverage, 7012,
37304 GIR_EraseRootFromParent_Done,
37305 // Label 2211: @106905
37306 GIM_Reject,
37307 // Label 2206: @106906
37308 GIM_Reject,
37309 // Label 2189: @106907
37310 GIM_Reject,
37311 // Label 22: @106908
37312 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2214*/ GIMT_Encode4(107899),
37313 /*GILLT_s32*//*Label 2212*/ GIMT_Encode4(106927),
37314 /*GILLT_s64*//*Label 2213*/ GIMT_Encode4(107672),
37315 // Label 2212: @106927
37316 GIM_Try, /*On fail goto*//*Label 2215*/ GIMT_Encode4(107671),
37317 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
37318 GIM_Try, /*On fail goto*//*Label 2216*/ GIMT_Encode4(106984), // Rule ID 6853 //
37319 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37320 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
37321 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
37322 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37323 // MIs[0] Rn
37324 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37325 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37326 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37327 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_monotonic>> => (LDADDW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37328 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDW),
37329 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37330 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37331 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37332 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37333 GIR_RootConstrainSelectedInstOperands,
37334 // GIR_Coverage, 6853,
37335 GIR_EraseRootFromParent_Done,
37336 // Label 2216: @106984
37337 GIM_Try, /*On fail goto*//*Label 2217*/ GIMT_Encode4(107033), // Rule ID 6854 //
37338 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37339 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
37340 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
37341 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37342 // MIs[0] Rn
37343 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37344 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37345 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37346 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acquire>> => (LDADDAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37347 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAW),
37348 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37349 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37350 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37351 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37352 GIR_RootConstrainSelectedInstOperands,
37353 // GIR_Coverage, 6854,
37354 GIR_EraseRootFromParent_Done,
37355 // Label 2217: @107033
37356 GIM_Try, /*On fail goto*//*Label 2218*/ GIMT_Encode4(107082), // Rule ID 6855 //
37357 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37358 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
37359 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
37360 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37361 // MIs[0] Rn
37362 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37363 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37364 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37365 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_release>> => (LDADDLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37366 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLW),
37367 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37368 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37369 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37370 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37371 GIR_RootConstrainSelectedInstOperands,
37372 // GIR_Coverage, 6855,
37373 GIR_EraseRootFromParent_Done,
37374 // Label 2218: @107082
37375 GIM_Try, /*On fail goto*//*Label 2219*/ GIMT_Encode4(107131), // Rule ID 6856 //
37376 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37377 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
37378 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
37379 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37380 // MIs[0] Rn
37381 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37382 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37383 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37384 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acq_rel>> => (LDADDALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37385 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALW),
37386 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37387 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37388 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37389 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37390 GIR_RootConstrainSelectedInstOperands,
37391 // GIR_Coverage, 6856,
37392 GIR_EraseRootFromParent_Done,
37393 // Label 2219: @107131
37394 GIM_Try, /*On fail goto*//*Label 2220*/ GIMT_Encode4(107180), // Rule ID 6857 //
37395 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37396 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
37397 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
37398 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37399 // MIs[0] Rn
37400 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37401 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37402 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37403 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_seq_cst>> => (LDADDALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37404 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALW),
37405 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37406 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37407 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37408 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37409 GIR_RootConstrainSelectedInstOperands,
37410 // GIR_Coverage, 6857,
37411 GIR_EraseRootFromParent_Done,
37412 // Label 2220: @107180
37413 GIM_Try, /*On fail goto*//*Label 2221*/ GIMT_Encode4(107229), // Rule ID 6858 //
37414 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37415 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
37416 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
37417 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37418 // MIs[0] Rn
37419 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37420 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37421 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37422 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_monotonic>> => (LDADDH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37423 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDH),
37424 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37425 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37426 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37427 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37428 GIR_RootConstrainSelectedInstOperands,
37429 // GIR_Coverage, 6858,
37430 GIR_EraseRootFromParent_Done,
37431 // Label 2221: @107229
37432 GIM_Try, /*On fail goto*//*Label 2222*/ GIMT_Encode4(107278), // Rule ID 6859 //
37433 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37434 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
37435 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
37436 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37437 // MIs[0] Rn
37438 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37439 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37440 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37441 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_acquire>> => (LDADDAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37442 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAH),
37443 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37444 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37445 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37446 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37447 GIR_RootConstrainSelectedInstOperands,
37448 // GIR_Coverage, 6859,
37449 GIR_EraseRootFromParent_Done,
37450 // Label 2222: @107278
37451 GIM_Try, /*On fail goto*//*Label 2223*/ GIMT_Encode4(107327), // Rule ID 6860 //
37452 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37453 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
37454 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
37455 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37456 // MIs[0] Rn
37457 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37458 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37459 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37460 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_release>> => (LDADDLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37461 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLH),
37462 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37463 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37464 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37465 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37466 GIR_RootConstrainSelectedInstOperands,
37467 // GIR_Coverage, 6860,
37468 GIR_EraseRootFromParent_Done,
37469 // Label 2223: @107327
37470 GIM_Try, /*On fail goto*//*Label 2224*/ GIMT_Encode4(107376), // Rule ID 6861 //
37471 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37472 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
37473 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
37474 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37475 // MIs[0] Rn
37476 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37477 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37478 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37479 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_acq_rel>> => (LDADDALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37480 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALH),
37481 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37482 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37483 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37484 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37485 GIR_RootConstrainSelectedInstOperands,
37486 // GIR_Coverage, 6861,
37487 GIR_EraseRootFromParent_Done,
37488 // Label 2224: @107376
37489 GIM_Try, /*On fail goto*//*Label 2225*/ GIMT_Encode4(107425), // Rule ID 6862 //
37490 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37491 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
37492 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
37493 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37494 // MIs[0] Rn
37495 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37496 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37497 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37498 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_seq_cst>> => (LDADDALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37499 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALH),
37500 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37501 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37502 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37503 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37504 GIR_RootConstrainSelectedInstOperands,
37505 // GIR_Coverage, 6862,
37506 GIR_EraseRootFromParent_Done,
37507 // Label 2225: @107425
37508 GIM_Try, /*On fail goto*//*Label 2226*/ GIMT_Encode4(107474), // Rule ID 6863 //
37509 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37510 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
37511 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
37512 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37513 // MIs[0] Rn
37514 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37515 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37516 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37517 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_monotonic>> => (LDADDB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37518 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDB),
37519 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37520 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37521 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37522 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37523 GIR_RootConstrainSelectedInstOperands,
37524 // GIR_Coverage, 6863,
37525 GIR_EraseRootFromParent_Done,
37526 // Label 2226: @107474
37527 GIM_Try, /*On fail goto*//*Label 2227*/ GIMT_Encode4(107523), // Rule ID 6864 //
37528 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37529 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
37530 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
37531 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37532 // MIs[0] Rn
37533 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37534 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37535 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37536 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_acquire>> => (LDADDAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37537 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAB),
37538 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37539 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37540 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37541 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37542 GIR_RootConstrainSelectedInstOperands,
37543 // GIR_Coverage, 6864,
37544 GIR_EraseRootFromParent_Done,
37545 // Label 2227: @107523
37546 GIM_Try, /*On fail goto*//*Label 2228*/ GIMT_Encode4(107572), // Rule ID 6865 //
37547 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37548 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
37549 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
37550 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37551 // MIs[0] Rn
37552 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37553 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37554 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37555 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_release>> => (LDADDLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37556 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLB),
37557 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37558 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37559 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37560 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37561 GIR_RootConstrainSelectedInstOperands,
37562 // GIR_Coverage, 6865,
37563 GIR_EraseRootFromParent_Done,
37564 // Label 2228: @107572
37565 GIM_Try, /*On fail goto*//*Label 2229*/ GIMT_Encode4(107621), // Rule ID 6866 //
37566 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37567 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
37568 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
37569 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37570 // MIs[0] Rn
37571 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37572 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37573 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37574 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_acq_rel>> => (LDADDALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37575 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALB),
37576 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37577 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37578 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37579 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37580 GIR_RootConstrainSelectedInstOperands,
37581 // GIR_Coverage, 6866,
37582 GIR_EraseRootFromParent_Done,
37583 // Label 2229: @107621
37584 GIM_Try, /*On fail goto*//*Label 2230*/ GIMT_Encode4(107670), // Rule ID 6867 //
37585 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37586 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
37587 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
37588 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37589 // MIs[0] Rn
37590 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37591 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37592 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37593 // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_seq_cst>> => (LDADDALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37594 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALB),
37595 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37596 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37597 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37598 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37599 GIR_RootConstrainSelectedInstOperands,
37600 // GIR_Coverage, 6867,
37601 GIR_EraseRootFromParent_Done,
37602 // Label 2230: @107670
37603 GIM_Reject,
37604 // Label 2215: @107671
37605 GIM_Reject,
37606 // Label 2213: @107672
37607 GIM_Try, /*On fail goto*//*Label 2231*/ GIMT_Encode4(107898),
37608 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
37609 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
37610 GIM_Try, /*On fail goto*//*Label 2232*/ GIMT_Encode4(107729), // Rule ID 2489 //
37611 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37612 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
37613 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37614 // MIs[0] Rn
37615 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37616 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37617 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37618 // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_monotonic>> => (LDADDX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37619 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDX),
37620 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37621 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37622 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37623 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37624 GIR_RootConstrainSelectedInstOperands,
37625 // GIR_Coverage, 2489,
37626 GIR_EraseRootFromParent_Done,
37627 // Label 2232: @107729
37628 GIM_Try, /*On fail goto*//*Label 2233*/ GIMT_Encode4(107771), // Rule ID 2490 //
37629 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37630 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
37631 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37632 // MIs[0] Rn
37633 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37634 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37635 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37636 // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_acquire>> => (LDADDAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37637 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAX),
37638 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37639 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37640 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37641 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37642 GIR_RootConstrainSelectedInstOperands,
37643 // GIR_Coverage, 2490,
37644 GIR_EraseRootFromParent_Done,
37645 // Label 2233: @107771
37646 GIM_Try, /*On fail goto*//*Label 2234*/ GIMT_Encode4(107813), // Rule ID 2491 //
37647 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37648 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
37649 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37650 // MIs[0] Rn
37651 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37652 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37653 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37654 // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_release>> => (LDADDLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37655 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLX),
37656 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37657 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37658 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37659 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37660 GIR_RootConstrainSelectedInstOperands,
37661 // GIR_Coverage, 2491,
37662 GIR_EraseRootFromParent_Done,
37663 // Label 2234: @107813
37664 GIM_Try, /*On fail goto*//*Label 2235*/ GIMT_Encode4(107855), // Rule ID 2492 //
37665 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37666 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
37667 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37668 // MIs[0] Rn
37669 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37670 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37671 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37672 // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_acq_rel>> => (LDADDALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37673 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALX),
37674 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37675 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37676 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37677 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37678 GIR_RootConstrainSelectedInstOperands,
37679 // GIR_Coverage, 2492,
37680 GIR_EraseRootFromParent_Done,
37681 // Label 2235: @107855
37682 GIM_Try, /*On fail goto*//*Label 2236*/ GIMT_Encode4(107897), // Rule ID 2493 //
37683 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37684 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
37685 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37686 // MIs[0] Rn
37687 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37688 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37689 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
37690 // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_seq_cst>> => (LDADDALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
37691 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALX),
37692 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37693 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
37694 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37695 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37696 GIR_RootConstrainSelectedInstOperands,
37697 // GIR_Coverage, 2493,
37698 GIR_EraseRootFromParent_Done,
37699 // Label 2236: @107897
37700 GIM_Reject,
37701 // Label 2231: @107898
37702 GIM_Reject,
37703 // Label 2214: @107899
37704 GIM_Reject,
37705 // Label 23: @107900
37706 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2239*/ GIMT_Encode4(109391),
37707 /*GILLT_s32*//*Label 2237*/ GIMT_Encode4(107919),
37708 /*GILLT_s64*//*Label 2238*/ GIMT_Encode4(109039),
37709 // Label 2237: @107919
37710 GIM_Try, /*On fail goto*//*Label 2240*/ GIMT_Encode4(109038),
37711 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
37712 GIM_Try, /*On fail goto*//*Label 2241*/ GIMT_Encode4(108001), // Rule ID 7048 //
37713 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37714 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
37715 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
37716 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37717 // MIs[0] Rn
37718 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37719 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37720 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37721 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i32>><<P:Predicate_atomic_load_sub_i32_monotonic>> => (LDADDW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
37722 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
37723 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
37724 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37725 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37726 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
37727 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
37728 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDW),
37729 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37730 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37731 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37732 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37733 GIR_RootConstrainSelectedInstOperands,
37734 // GIR_Coverage, 7048,
37735 GIR_EraseRootFromParent_Done,
37736 // Label 2241: @108001
37737 GIM_Try, /*On fail goto*//*Label 2242*/ GIMT_Encode4(108075), // Rule ID 7049 //
37738 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37739 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
37740 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
37741 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37742 // MIs[0] Rn
37743 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37744 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37745 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37746 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i32>><<P:Predicate_atomic_load_sub_i32_acquire>> => (LDADDAW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
37747 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
37748 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
37749 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37750 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37751 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
37752 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
37753 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAW),
37754 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37755 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37756 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37757 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37758 GIR_RootConstrainSelectedInstOperands,
37759 // GIR_Coverage, 7049,
37760 GIR_EraseRootFromParent_Done,
37761 // Label 2242: @108075
37762 GIM_Try, /*On fail goto*//*Label 2243*/ GIMT_Encode4(108149), // Rule ID 7050 //
37763 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37764 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
37765 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
37766 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37767 // MIs[0] Rn
37768 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37769 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37770 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37771 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i32>><<P:Predicate_atomic_load_sub_i32_release>> => (LDADDLW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
37772 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
37773 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
37774 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37775 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37776 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
37777 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
37778 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLW),
37779 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37780 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37781 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37782 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37783 GIR_RootConstrainSelectedInstOperands,
37784 // GIR_Coverage, 7050,
37785 GIR_EraseRootFromParent_Done,
37786 // Label 2243: @108149
37787 GIM_Try, /*On fail goto*//*Label 2244*/ GIMT_Encode4(108223), // Rule ID 7051 //
37788 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37789 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
37790 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
37791 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37792 // MIs[0] Rn
37793 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37794 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37795 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37796 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i32>><<P:Predicate_atomic_load_sub_i32_acq_rel>> => (LDADDALW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
37797 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
37798 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
37799 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37800 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37801 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
37802 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
37803 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALW),
37804 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37805 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37806 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37807 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37808 GIR_RootConstrainSelectedInstOperands,
37809 // GIR_Coverage, 7051,
37810 GIR_EraseRootFromParent_Done,
37811 // Label 2244: @108223
37812 GIM_Try, /*On fail goto*//*Label 2245*/ GIMT_Encode4(108297), // Rule ID 7052 //
37813 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37814 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
37815 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
37816 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37817 // MIs[0] Rn
37818 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37819 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37820 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37821 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i32>><<P:Predicate_atomic_load_sub_i32_seq_cst>> => (LDADDALW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
37822 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
37823 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
37824 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37825 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37826 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
37827 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
37828 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALW),
37829 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37830 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37831 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37832 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37833 GIR_RootConstrainSelectedInstOperands,
37834 // GIR_Coverage, 7052,
37835 GIR_EraseRootFromParent_Done,
37836 // Label 2245: @108297
37837 GIM_Try, /*On fail goto*//*Label 2246*/ GIMT_Encode4(108371), // Rule ID 7053 //
37838 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37839 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
37840 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
37841 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37842 // MIs[0] Rn
37843 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37844 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37845 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37846 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i16>><<P:Predicate_atomic_load_sub_i16_monotonic>> => (LDADDH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
37847 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
37848 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
37849 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37850 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37851 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
37852 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
37853 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDH),
37854 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37855 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37856 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37857 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37858 GIR_RootConstrainSelectedInstOperands,
37859 // GIR_Coverage, 7053,
37860 GIR_EraseRootFromParent_Done,
37861 // Label 2246: @108371
37862 GIM_Try, /*On fail goto*//*Label 2247*/ GIMT_Encode4(108445), // Rule ID 7054 //
37863 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37864 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
37865 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
37866 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37867 // MIs[0] Rn
37868 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37869 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37870 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37871 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i16>><<P:Predicate_atomic_load_sub_i16_acquire>> => (LDADDAH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
37872 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
37873 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
37874 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37875 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37876 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
37877 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
37878 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAH),
37879 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37880 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37881 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37882 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37883 GIR_RootConstrainSelectedInstOperands,
37884 // GIR_Coverage, 7054,
37885 GIR_EraseRootFromParent_Done,
37886 // Label 2247: @108445
37887 GIM_Try, /*On fail goto*//*Label 2248*/ GIMT_Encode4(108519), // Rule ID 7055 //
37888 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37889 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
37890 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
37891 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37892 // MIs[0] Rn
37893 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37894 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37895 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37896 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i16>><<P:Predicate_atomic_load_sub_i16_release>> => (LDADDLH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
37897 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
37898 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
37899 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37900 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37901 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
37902 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
37903 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLH),
37904 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37905 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37906 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37907 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37908 GIR_RootConstrainSelectedInstOperands,
37909 // GIR_Coverage, 7055,
37910 GIR_EraseRootFromParent_Done,
37911 // Label 2248: @108519
37912 GIM_Try, /*On fail goto*//*Label 2249*/ GIMT_Encode4(108593), // Rule ID 7056 //
37913 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37914 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
37915 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
37916 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37917 // MIs[0] Rn
37918 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37919 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37920 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37921 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i16>><<P:Predicate_atomic_load_sub_i16_acq_rel>> => (LDADDALH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
37922 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
37923 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
37924 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37925 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37926 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
37927 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
37928 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALH),
37929 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37930 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37931 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37932 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37933 GIR_RootConstrainSelectedInstOperands,
37934 // GIR_Coverage, 7056,
37935 GIR_EraseRootFromParent_Done,
37936 // Label 2249: @108593
37937 GIM_Try, /*On fail goto*//*Label 2250*/ GIMT_Encode4(108667), // Rule ID 7057 //
37938 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37939 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
37940 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
37941 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37942 // MIs[0] Rn
37943 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37944 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37945 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37946 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i16>><<P:Predicate_atomic_load_sub_i16_seq_cst>> => (LDADDALH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
37947 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
37948 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
37949 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37950 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37951 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
37952 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
37953 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALH),
37954 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37955 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37956 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37957 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37958 GIR_RootConstrainSelectedInstOperands,
37959 // GIR_Coverage, 7057,
37960 GIR_EraseRootFromParent_Done,
37961 // Label 2250: @108667
37962 GIM_Try, /*On fail goto*//*Label 2251*/ GIMT_Encode4(108741), // Rule ID 7058 //
37963 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37964 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
37965 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
37966 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37967 // MIs[0] Rn
37968 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37969 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37970 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37971 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i8>><<P:Predicate_atomic_load_sub_i8_monotonic>> => (LDADDB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
37972 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
37973 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
37974 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
37975 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37976 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
37977 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
37978 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDB),
37979 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
37980 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37981 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
37982 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37983 GIR_RootConstrainSelectedInstOperands,
37984 // GIR_Coverage, 7058,
37985 GIR_EraseRootFromParent_Done,
37986 // Label 2251: @108741
37987 GIM_Try, /*On fail goto*//*Label 2252*/ GIMT_Encode4(108815), // Rule ID 7059 //
37988 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
37989 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
37990 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
37991 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37992 // MIs[0] Rn
37993 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
37994 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
37995 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
37996 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i8>><<P:Predicate_atomic_load_sub_i8_acquire>> => (LDADDAB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
37997 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
37998 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
37999 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38000 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38001 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38002 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38003 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAB),
38004 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38005 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38006 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38007 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38008 GIR_RootConstrainSelectedInstOperands,
38009 // GIR_Coverage, 7059,
38010 GIR_EraseRootFromParent_Done,
38011 // Label 2252: @108815
38012 GIM_Try, /*On fail goto*//*Label 2253*/ GIMT_Encode4(108889), // Rule ID 7060 //
38013 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38014 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
38015 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
38016 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38017 // MIs[0] Rn
38018 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38019 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38020 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38021 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i8>><<P:Predicate_atomic_load_sub_i8_release>> => (LDADDLB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38022 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38023 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
38024 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38025 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38026 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38027 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38028 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLB),
38029 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38030 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38031 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38032 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38033 GIR_RootConstrainSelectedInstOperands,
38034 // GIR_Coverage, 7060,
38035 GIR_EraseRootFromParent_Done,
38036 // Label 2253: @108889
38037 GIM_Try, /*On fail goto*//*Label 2254*/ GIMT_Encode4(108963), // Rule ID 7061 //
38038 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38039 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
38040 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
38041 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38042 // MIs[0] Rn
38043 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38044 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38045 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38046 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i8>><<P:Predicate_atomic_load_sub_i8_acq_rel>> => (LDADDALB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38047 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38048 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
38049 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38050 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38051 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38052 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38053 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALB),
38054 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38055 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38056 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38057 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38058 GIR_RootConstrainSelectedInstOperands,
38059 // GIR_Coverage, 7061,
38060 GIR_EraseRootFromParent_Done,
38061 // Label 2254: @108963
38062 GIM_Try, /*On fail goto*//*Label 2255*/ GIMT_Encode4(109037), // Rule ID 7062 //
38063 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38064 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
38065 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
38066 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38067 // MIs[0] Rn
38068 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38069 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38070 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38071 // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i8>><<P:Predicate_atomic_load_sub_i8_seq_cst>> => (LDADDALB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38072 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38073 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
38074 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38075 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38076 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38077 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38078 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALB),
38079 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38080 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38081 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38082 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38083 GIR_RootConstrainSelectedInstOperands,
38084 // GIR_Coverage, 7062,
38085 GIR_EraseRootFromParent_Done,
38086 // Label 2255: @109037
38087 GIM_Reject,
38088 // Label 2240: @109038
38089 GIM_Reject,
38090 // Label 2238: @109039
38091 GIM_Try, /*On fail goto*//*Label 2256*/ GIMT_Encode4(109390),
38092 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
38093 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
38094 GIM_Try, /*On fail goto*//*Label 2257*/ GIMT_Encode4(109121), // Rule ID 7043 //
38095 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38096 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
38097 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38098 // MIs[0] Rn
38099 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38100 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38101 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38102 // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_i64>><<P:Predicate_atomic_load_sub_i64_monotonic>> => (LDADDX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38103 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
38104 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBXrr),
38105 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38106 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38107 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38108 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38109 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDX),
38110 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38111 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38112 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38113 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38114 GIR_RootConstrainSelectedInstOperands,
38115 // GIR_Coverage, 7043,
38116 GIR_EraseRootFromParent_Done,
38117 // Label 2257: @109121
38118 GIM_Try, /*On fail goto*//*Label 2258*/ GIMT_Encode4(109188), // Rule ID 7044 //
38119 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38120 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
38121 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38122 // MIs[0] Rn
38123 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38124 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38125 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38126 // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_i64>><<P:Predicate_atomic_load_sub_i64_acquire>> => (LDADDAX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38127 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
38128 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBXrr),
38129 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38130 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38131 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38132 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38133 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAX),
38134 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38135 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38136 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38137 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38138 GIR_RootConstrainSelectedInstOperands,
38139 // GIR_Coverage, 7044,
38140 GIR_EraseRootFromParent_Done,
38141 // Label 2258: @109188
38142 GIM_Try, /*On fail goto*//*Label 2259*/ GIMT_Encode4(109255), // Rule ID 7045 //
38143 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38144 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
38145 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38146 // MIs[0] Rn
38147 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38148 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38149 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38150 // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_i64>><<P:Predicate_atomic_load_sub_i64_release>> => (LDADDLX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38151 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
38152 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBXrr),
38153 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38154 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38155 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38156 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38157 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLX),
38158 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38159 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38160 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38161 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38162 GIR_RootConstrainSelectedInstOperands,
38163 // GIR_Coverage, 7045,
38164 GIR_EraseRootFromParent_Done,
38165 // Label 2259: @109255
38166 GIM_Try, /*On fail goto*//*Label 2260*/ GIMT_Encode4(109322), // Rule ID 7046 //
38167 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38168 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
38169 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38170 // MIs[0] Rn
38171 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38172 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38173 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38174 // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_i64>><<P:Predicate_atomic_load_sub_i64_acq_rel>> => (LDADDALX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38175 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
38176 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBXrr),
38177 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38178 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38179 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38180 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38181 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALX),
38182 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38183 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38184 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38185 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38186 GIR_RootConstrainSelectedInstOperands,
38187 // GIR_Coverage, 7046,
38188 GIR_EraseRootFromParent_Done,
38189 // Label 2260: @109322
38190 GIM_Try, /*On fail goto*//*Label 2261*/ GIMT_Encode4(109389), // Rule ID 7047 //
38191 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38192 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
38193 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38194 // MIs[0] Rn
38195 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38196 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38197 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38198 // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_i64>><<P:Predicate_atomic_load_sub_i64_seq_cst>> => (LDADDALX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38199 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
38200 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBXrr),
38201 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38202 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38203 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38204 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38205 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALX),
38206 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38207 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38208 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38209 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38210 GIR_RootConstrainSelectedInstOperands,
38211 // GIR_Coverage, 7047,
38212 GIR_EraseRootFromParent_Done,
38213 // Label 2261: @109389
38214 GIM_Reject,
38215 // Label 2256: @109390
38216 GIM_Reject,
38217 // Label 2239: @109391
38218 GIM_Reject,
38219 // Label 24: @109392
38220 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2264*/ GIMT_Encode4(110883),
38221 /*GILLT_s32*//*Label 2262*/ GIMT_Encode4(109411),
38222 /*GILLT_s64*//*Label 2263*/ GIMT_Encode4(110531),
38223 // Label 2262: @109411
38224 GIM_Try, /*On fail goto*//*Label 2265*/ GIMT_Encode4(110530),
38225 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
38226 GIM_Try, /*On fail goto*//*Label 2266*/ GIMT_Encode4(109493), // Rule ID 7068 //
38227 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38228 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
38229 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
38230 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38231 // MIs[0] Rn
38232 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38233 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38234 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38235 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_monotonic>> => (LDCLRW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38236 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38237 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
38238 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38239 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38240 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38241 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38242 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRW),
38243 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38244 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38245 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38246 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38247 GIR_RootConstrainSelectedInstOperands,
38248 // GIR_Coverage, 7068,
38249 GIR_EraseRootFromParent_Done,
38250 // Label 2266: @109493
38251 GIM_Try, /*On fail goto*//*Label 2267*/ GIMT_Encode4(109567), // Rule ID 7069 //
38252 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38253 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
38254 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
38255 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38256 // MIs[0] Rn
38257 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38258 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38259 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38260 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acquire>> => (LDCLRAW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38261 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38262 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
38263 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38264 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38265 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38266 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38267 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRAW),
38268 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38269 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38270 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38271 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38272 GIR_RootConstrainSelectedInstOperands,
38273 // GIR_Coverage, 7069,
38274 GIR_EraseRootFromParent_Done,
38275 // Label 2267: @109567
38276 GIM_Try, /*On fail goto*//*Label 2268*/ GIMT_Encode4(109641), // Rule ID 7070 //
38277 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38278 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
38279 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
38280 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38281 // MIs[0] Rn
38282 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38283 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38284 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38285 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_release>> => (LDCLRLW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38286 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38287 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
38288 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38289 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38290 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38291 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38292 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRLW),
38293 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38294 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38295 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38296 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38297 GIR_RootConstrainSelectedInstOperands,
38298 // GIR_Coverage, 7070,
38299 GIR_EraseRootFromParent_Done,
38300 // Label 2268: @109641
38301 GIM_Try, /*On fail goto*//*Label 2269*/ GIMT_Encode4(109715), // Rule ID 7071 //
38302 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38303 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
38304 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
38305 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38306 // MIs[0] Rn
38307 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38308 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38309 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38310 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acq_rel>> => (LDCLRALW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38311 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38312 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
38313 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38314 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38315 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38316 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38317 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALW),
38318 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38319 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38320 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38321 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38322 GIR_RootConstrainSelectedInstOperands,
38323 // GIR_Coverage, 7071,
38324 GIR_EraseRootFromParent_Done,
38325 // Label 2269: @109715
38326 GIM_Try, /*On fail goto*//*Label 2270*/ GIMT_Encode4(109789), // Rule ID 7072 //
38327 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38328 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
38329 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
38330 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38331 // MIs[0] Rn
38332 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38333 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38334 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38335 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_seq_cst>> => (LDCLRALW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38336 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38337 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
38338 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38339 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38340 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38341 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38342 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALW),
38343 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38344 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38345 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38346 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38347 GIR_RootConstrainSelectedInstOperands,
38348 // GIR_Coverage, 7072,
38349 GIR_EraseRootFromParent_Done,
38350 // Label 2270: @109789
38351 GIM_Try, /*On fail goto*//*Label 2271*/ GIMT_Encode4(109863), // Rule ID 7073 //
38352 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38353 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
38354 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
38355 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38356 // MIs[0] Rn
38357 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38358 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38359 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38360 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_monotonic>> => (LDCLRH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38361 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38362 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
38363 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38364 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38365 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38366 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38367 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRH),
38368 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38369 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38370 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38371 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38372 GIR_RootConstrainSelectedInstOperands,
38373 // GIR_Coverage, 7073,
38374 GIR_EraseRootFromParent_Done,
38375 // Label 2271: @109863
38376 GIM_Try, /*On fail goto*//*Label 2272*/ GIMT_Encode4(109937), // Rule ID 7074 //
38377 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38378 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
38379 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
38380 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38381 // MIs[0] Rn
38382 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38383 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38384 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38385 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_acquire>> => (LDCLRAH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38386 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38387 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
38388 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38389 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38390 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38391 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38392 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRAH),
38393 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38394 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38395 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38396 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38397 GIR_RootConstrainSelectedInstOperands,
38398 // GIR_Coverage, 7074,
38399 GIR_EraseRootFromParent_Done,
38400 // Label 2272: @109937
38401 GIM_Try, /*On fail goto*//*Label 2273*/ GIMT_Encode4(110011), // Rule ID 7075 //
38402 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38403 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
38404 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
38405 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38406 // MIs[0] Rn
38407 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38408 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38409 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38410 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_release>> => (LDCLRLH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38411 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38412 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
38413 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38414 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38415 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38416 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38417 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRLH),
38418 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38419 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38420 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38421 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38422 GIR_RootConstrainSelectedInstOperands,
38423 // GIR_Coverage, 7075,
38424 GIR_EraseRootFromParent_Done,
38425 // Label 2273: @110011
38426 GIM_Try, /*On fail goto*//*Label 2274*/ GIMT_Encode4(110085), // Rule ID 7076 //
38427 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38428 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
38429 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
38430 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38431 // MIs[0] Rn
38432 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38433 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38434 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38435 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_acq_rel>> => (LDCLRALH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38436 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38437 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
38438 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38439 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38440 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38441 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38442 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALH),
38443 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38444 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38445 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38446 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38447 GIR_RootConstrainSelectedInstOperands,
38448 // GIR_Coverage, 7076,
38449 GIR_EraseRootFromParent_Done,
38450 // Label 2274: @110085
38451 GIM_Try, /*On fail goto*//*Label 2275*/ GIMT_Encode4(110159), // Rule ID 7077 //
38452 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38453 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
38454 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
38455 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38456 // MIs[0] Rn
38457 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38458 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38459 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38460 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_seq_cst>> => (LDCLRALH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38461 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38462 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
38463 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38464 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38465 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38466 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38467 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALH),
38468 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38469 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38470 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38471 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38472 GIR_RootConstrainSelectedInstOperands,
38473 // GIR_Coverage, 7077,
38474 GIR_EraseRootFromParent_Done,
38475 // Label 2275: @110159
38476 GIM_Try, /*On fail goto*//*Label 2276*/ GIMT_Encode4(110233), // Rule ID 7078 //
38477 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38478 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
38479 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
38480 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38481 // MIs[0] Rn
38482 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38483 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38484 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38485 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_monotonic>> => (LDCLRB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38486 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38487 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
38488 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38489 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38490 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38491 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38492 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRB),
38493 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38494 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38495 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38496 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38497 GIR_RootConstrainSelectedInstOperands,
38498 // GIR_Coverage, 7078,
38499 GIR_EraseRootFromParent_Done,
38500 // Label 2276: @110233
38501 GIM_Try, /*On fail goto*//*Label 2277*/ GIMT_Encode4(110307), // Rule ID 7079 //
38502 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38503 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
38504 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
38505 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38506 // MIs[0] Rn
38507 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38508 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38509 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38510 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_acquire>> => (LDCLRAB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38511 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38512 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
38513 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38514 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38515 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38516 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38517 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRAB),
38518 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38519 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38520 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38521 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38522 GIR_RootConstrainSelectedInstOperands,
38523 // GIR_Coverage, 7079,
38524 GIR_EraseRootFromParent_Done,
38525 // Label 2277: @110307
38526 GIM_Try, /*On fail goto*//*Label 2278*/ GIMT_Encode4(110381), // Rule ID 7080 //
38527 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38528 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
38529 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
38530 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38531 // MIs[0] Rn
38532 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38533 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38534 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38535 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_release>> => (LDCLRLB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38536 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38537 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
38538 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38539 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38540 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38541 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38542 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRLB),
38543 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38544 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38545 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38546 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38547 GIR_RootConstrainSelectedInstOperands,
38548 // GIR_Coverage, 7080,
38549 GIR_EraseRootFromParent_Done,
38550 // Label 2278: @110381
38551 GIM_Try, /*On fail goto*//*Label 2279*/ GIMT_Encode4(110455), // Rule ID 7081 //
38552 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38553 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
38554 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
38555 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38556 // MIs[0] Rn
38557 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38558 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38559 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38560 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_acq_rel>> => (LDCLRALB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38561 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38562 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
38563 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38564 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38565 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38566 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38567 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALB),
38568 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38569 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38570 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38571 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38572 GIR_RootConstrainSelectedInstOperands,
38573 // GIR_Coverage, 7081,
38574 GIR_EraseRootFromParent_Done,
38575 // Label 2279: @110455
38576 GIM_Try, /*On fail goto*//*Label 2280*/ GIMT_Encode4(110529), // Rule ID 7082 //
38577 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38578 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
38579 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
38580 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38581 // MIs[0] Rn
38582 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38583 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38584 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38585 // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_seq_cst>> => (LDCLRALB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38586 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
38587 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
38588 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38589 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38590 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38591 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38592 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALB),
38593 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38594 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38595 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38596 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38597 GIR_RootConstrainSelectedInstOperands,
38598 // GIR_Coverage, 7082,
38599 GIR_EraseRootFromParent_Done,
38600 // Label 2280: @110529
38601 GIM_Reject,
38602 // Label 2265: @110530
38603 GIM_Reject,
38604 // Label 2263: @110531
38605 GIM_Try, /*On fail goto*//*Label 2281*/ GIMT_Encode4(110882),
38606 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
38607 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
38608 GIM_Try, /*On fail goto*//*Label 2282*/ GIMT_Encode4(110613), // Rule ID 7063 //
38609 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38610 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
38611 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38612 // MIs[0] Rn
38613 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38614 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38615 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38616 // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_monotonic>> => (LDCLRX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38617 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
38618 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
38619 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38620 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38621 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38622 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38623 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRX),
38624 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38625 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38626 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38627 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38628 GIR_RootConstrainSelectedInstOperands,
38629 // GIR_Coverage, 7063,
38630 GIR_EraseRootFromParent_Done,
38631 // Label 2282: @110613
38632 GIM_Try, /*On fail goto*//*Label 2283*/ GIMT_Encode4(110680), // Rule ID 7064 //
38633 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38634 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
38635 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38636 // MIs[0] Rn
38637 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38638 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38639 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38640 // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_acquire>> => (LDCLRAX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38641 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
38642 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
38643 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38644 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38645 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38646 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38647 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRAX),
38648 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38649 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38650 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38651 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38652 GIR_RootConstrainSelectedInstOperands,
38653 // GIR_Coverage, 7064,
38654 GIR_EraseRootFromParent_Done,
38655 // Label 2283: @110680
38656 GIM_Try, /*On fail goto*//*Label 2284*/ GIMT_Encode4(110747), // Rule ID 7065 //
38657 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38658 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
38659 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38660 // MIs[0] Rn
38661 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38662 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38663 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38664 // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_release>> => (LDCLRLX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38665 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
38666 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
38667 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38668 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38669 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38670 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38671 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRLX),
38672 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38673 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38674 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38675 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38676 GIR_RootConstrainSelectedInstOperands,
38677 // GIR_Coverage, 7065,
38678 GIR_EraseRootFromParent_Done,
38679 // Label 2284: @110747
38680 GIM_Try, /*On fail goto*//*Label 2285*/ GIMT_Encode4(110814), // Rule ID 7066 //
38681 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38682 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
38683 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38684 // MIs[0] Rn
38685 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38686 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38687 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38688 // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_acq_rel>> => (LDCLRALX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38689 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
38690 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
38691 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38692 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38693 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38694 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38695 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALX),
38696 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38697 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38698 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38699 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38700 GIR_RootConstrainSelectedInstOperands,
38701 // GIR_Coverage, 7066,
38702 GIR_EraseRootFromParent_Done,
38703 // Label 2285: @110814
38704 GIM_Try, /*On fail goto*//*Label 2286*/ GIMT_Encode4(110881), // Rule ID 7067 //
38705 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38706 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
38707 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38708 // MIs[0] Rn
38709 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38710 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38711 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
38712 // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_seq_cst>> => (LDCLRALX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
38713 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
38714 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
38715 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
38716 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38717 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
38718 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38719 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALX),
38720 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38721 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38722 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38723 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38724 GIR_RootConstrainSelectedInstOperands,
38725 // GIR_Coverage, 7067,
38726 GIR_EraseRootFromParent_Done,
38727 // Label 2286: @110881
38728 GIM_Reject,
38729 // Label 2281: @110882
38730 GIM_Reject,
38731 // Label 2264: @110883
38732 GIM_Reject,
38733 // Label 25: @110884
38734 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2289*/ GIMT_Encode4(111875),
38735 /*GILLT_s32*//*Label 2287*/ GIMT_Encode4(110903),
38736 /*GILLT_s64*//*Label 2288*/ GIMT_Encode4(111648),
38737 // Label 2287: @110903
38738 GIM_Try, /*On fail goto*//*Label 2290*/ GIMT_Encode4(111647),
38739 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
38740 GIM_Try, /*On fail goto*//*Label 2291*/ GIMT_Encode4(110960), // Rule ID 6873 //
38741 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38742 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
38743 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
38744 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38745 // MIs[0] Rn
38746 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38747 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38748 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38749 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_monotonic>> => (LDSETW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
38750 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETW),
38751 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38752 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
38753 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38754 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38755 GIR_RootConstrainSelectedInstOperands,
38756 // GIR_Coverage, 6873,
38757 GIR_EraseRootFromParent_Done,
38758 // Label 2291: @110960
38759 GIM_Try, /*On fail goto*//*Label 2292*/ GIMT_Encode4(111009), // Rule ID 6874 //
38760 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38761 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
38762 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
38763 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38764 // MIs[0] Rn
38765 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38766 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38767 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38768 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acquire>> => (LDSETAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
38769 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETAW),
38770 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38771 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
38772 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38773 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38774 GIR_RootConstrainSelectedInstOperands,
38775 // GIR_Coverage, 6874,
38776 GIR_EraseRootFromParent_Done,
38777 // Label 2292: @111009
38778 GIM_Try, /*On fail goto*//*Label 2293*/ GIMT_Encode4(111058), // Rule ID 6875 //
38779 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38780 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
38781 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
38782 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38783 // MIs[0] Rn
38784 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38785 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38786 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38787 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_release>> => (LDSETLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
38788 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETLW),
38789 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38790 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
38791 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38792 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38793 GIR_RootConstrainSelectedInstOperands,
38794 // GIR_Coverage, 6875,
38795 GIR_EraseRootFromParent_Done,
38796 // Label 2293: @111058
38797 GIM_Try, /*On fail goto*//*Label 2294*/ GIMT_Encode4(111107), // Rule ID 6876 //
38798 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38799 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
38800 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
38801 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38802 // MIs[0] Rn
38803 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38804 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38805 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38806 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acq_rel>> => (LDSETALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
38807 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALW),
38808 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38809 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
38810 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38811 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38812 GIR_RootConstrainSelectedInstOperands,
38813 // GIR_Coverage, 6876,
38814 GIR_EraseRootFromParent_Done,
38815 // Label 2294: @111107
38816 GIM_Try, /*On fail goto*//*Label 2295*/ GIMT_Encode4(111156), // Rule ID 6877 //
38817 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38818 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
38819 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
38820 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38821 // MIs[0] Rn
38822 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38823 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38824 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38825 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_seq_cst>> => (LDSETALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
38826 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALW),
38827 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38828 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
38829 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38830 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38831 GIR_RootConstrainSelectedInstOperands,
38832 // GIR_Coverage, 6877,
38833 GIR_EraseRootFromParent_Done,
38834 // Label 2295: @111156
38835 GIM_Try, /*On fail goto*//*Label 2296*/ GIMT_Encode4(111205), // Rule ID 6878 //
38836 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38837 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
38838 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
38839 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38840 // MIs[0] Rn
38841 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38842 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38843 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38844 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_monotonic>> => (LDSETH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
38845 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETH),
38846 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38847 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
38848 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38849 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38850 GIR_RootConstrainSelectedInstOperands,
38851 // GIR_Coverage, 6878,
38852 GIR_EraseRootFromParent_Done,
38853 // Label 2296: @111205
38854 GIM_Try, /*On fail goto*//*Label 2297*/ GIMT_Encode4(111254), // Rule ID 6879 //
38855 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38856 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
38857 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
38858 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38859 // MIs[0] Rn
38860 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38861 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38862 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38863 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_acquire>> => (LDSETAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
38864 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETAH),
38865 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38866 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
38867 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38868 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38869 GIR_RootConstrainSelectedInstOperands,
38870 // GIR_Coverage, 6879,
38871 GIR_EraseRootFromParent_Done,
38872 // Label 2297: @111254
38873 GIM_Try, /*On fail goto*//*Label 2298*/ GIMT_Encode4(111303), // Rule ID 6880 //
38874 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38875 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
38876 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
38877 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38878 // MIs[0] Rn
38879 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38880 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38881 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38882 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_release>> => (LDSETLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
38883 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETLH),
38884 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38885 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
38886 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38887 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38888 GIR_RootConstrainSelectedInstOperands,
38889 // GIR_Coverage, 6880,
38890 GIR_EraseRootFromParent_Done,
38891 // Label 2298: @111303
38892 GIM_Try, /*On fail goto*//*Label 2299*/ GIMT_Encode4(111352), // Rule ID 6881 //
38893 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38894 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
38895 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
38896 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38897 // MIs[0] Rn
38898 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38899 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38900 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38901 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_acq_rel>> => (LDSETALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
38902 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALH),
38903 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38904 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
38905 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38906 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38907 GIR_RootConstrainSelectedInstOperands,
38908 // GIR_Coverage, 6881,
38909 GIR_EraseRootFromParent_Done,
38910 // Label 2299: @111352
38911 GIM_Try, /*On fail goto*//*Label 2300*/ GIMT_Encode4(111401), // Rule ID 6882 //
38912 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38913 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
38914 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
38915 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38916 // MIs[0] Rn
38917 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38918 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38919 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38920 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_seq_cst>> => (LDSETALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
38921 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALH),
38922 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38923 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
38924 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38925 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38926 GIR_RootConstrainSelectedInstOperands,
38927 // GIR_Coverage, 6882,
38928 GIR_EraseRootFromParent_Done,
38929 // Label 2300: @111401
38930 GIM_Try, /*On fail goto*//*Label 2301*/ GIMT_Encode4(111450), // Rule ID 6883 //
38931 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38932 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
38933 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
38934 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38935 // MIs[0] Rn
38936 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38937 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38938 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38939 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_monotonic>> => (LDSETB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
38940 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETB),
38941 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38942 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
38943 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38944 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38945 GIR_RootConstrainSelectedInstOperands,
38946 // GIR_Coverage, 6883,
38947 GIR_EraseRootFromParent_Done,
38948 // Label 2301: @111450
38949 GIM_Try, /*On fail goto*//*Label 2302*/ GIMT_Encode4(111499), // Rule ID 6884 //
38950 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38951 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
38952 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
38953 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38954 // MIs[0] Rn
38955 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38956 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38957 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38958 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_acquire>> => (LDSETAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
38959 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETAB),
38960 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38961 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
38962 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38963 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38964 GIR_RootConstrainSelectedInstOperands,
38965 // GIR_Coverage, 6884,
38966 GIR_EraseRootFromParent_Done,
38967 // Label 2302: @111499
38968 GIM_Try, /*On fail goto*//*Label 2303*/ GIMT_Encode4(111548), // Rule ID 6885 //
38969 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38970 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
38971 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
38972 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38973 // MIs[0] Rn
38974 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38975 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38976 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38977 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_release>> => (LDSETLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
38978 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETLB),
38979 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38980 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
38981 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38982 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38983 GIR_RootConstrainSelectedInstOperands,
38984 // GIR_Coverage, 6885,
38985 GIR_EraseRootFromParent_Done,
38986 // Label 2303: @111548
38987 GIM_Try, /*On fail goto*//*Label 2304*/ GIMT_Encode4(111597), // Rule ID 6886 //
38988 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
38989 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
38990 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
38991 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38992 // MIs[0] Rn
38993 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
38994 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
38995 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
38996 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_acq_rel>> => (LDSETALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
38997 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALB),
38998 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
38999 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39000 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39001 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39002 GIR_RootConstrainSelectedInstOperands,
39003 // GIR_Coverage, 6886,
39004 GIR_EraseRootFromParent_Done,
39005 // Label 2304: @111597
39006 GIM_Try, /*On fail goto*//*Label 2305*/ GIMT_Encode4(111646), // Rule ID 6887 //
39007 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39008 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
39009 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
39010 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39011 // MIs[0] Rn
39012 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39013 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39014 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39015 // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_seq_cst>> => (LDSETALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39016 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALB),
39017 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39018 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39019 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39020 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39021 GIR_RootConstrainSelectedInstOperands,
39022 // GIR_Coverage, 6887,
39023 GIR_EraseRootFromParent_Done,
39024 // Label 2305: @111646
39025 GIM_Reject,
39026 // Label 2290: @111647
39027 GIM_Reject,
39028 // Label 2288: @111648
39029 GIM_Try, /*On fail goto*//*Label 2306*/ GIMT_Encode4(111874),
39030 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
39031 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
39032 GIM_Try, /*On fail goto*//*Label 2307*/ GIMT_Encode4(111705), // Rule ID 6868 //
39033 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39034 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
39035 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39036 // MIs[0] Rn
39037 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39038 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39039 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39040 // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_monotonic>> => (LDSETX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39041 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETX),
39042 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39043 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39044 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39045 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39046 GIR_RootConstrainSelectedInstOperands,
39047 // GIR_Coverage, 6868,
39048 GIR_EraseRootFromParent_Done,
39049 // Label 2307: @111705
39050 GIM_Try, /*On fail goto*//*Label 2308*/ GIMT_Encode4(111747), // Rule ID 6869 //
39051 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39052 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
39053 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39054 // MIs[0] Rn
39055 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39056 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39057 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39058 // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_acquire>> => (LDSETAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39059 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETAX),
39060 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39061 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39062 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39063 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39064 GIR_RootConstrainSelectedInstOperands,
39065 // GIR_Coverage, 6869,
39066 GIR_EraseRootFromParent_Done,
39067 // Label 2308: @111747
39068 GIM_Try, /*On fail goto*//*Label 2309*/ GIMT_Encode4(111789), // Rule ID 6870 //
39069 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39070 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
39071 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39072 // MIs[0] Rn
39073 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39074 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39075 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39076 // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_release>> => (LDSETLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39077 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETLX),
39078 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39079 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39080 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39081 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39082 GIR_RootConstrainSelectedInstOperands,
39083 // GIR_Coverage, 6870,
39084 GIR_EraseRootFromParent_Done,
39085 // Label 2309: @111789
39086 GIM_Try, /*On fail goto*//*Label 2310*/ GIMT_Encode4(111831), // Rule ID 6871 //
39087 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39088 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
39089 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39090 // MIs[0] Rn
39091 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39092 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39093 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39094 // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_acq_rel>> => (LDSETALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39095 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALX),
39096 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39097 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39098 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39099 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39100 GIR_RootConstrainSelectedInstOperands,
39101 // GIR_Coverage, 6871,
39102 GIR_EraseRootFromParent_Done,
39103 // Label 2310: @111831
39104 GIM_Try, /*On fail goto*//*Label 2311*/ GIMT_Encode4(111873), // Rule ID 6872 //
39105 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39106 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
39107 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39108 // MIs[0] Rn
39109 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39110 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39111 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39112 // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_seq_cst>> => (LDSETALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39113 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALX),
39114 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39115 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39116 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39117 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39118 GIR_RootConstrainSelectedInstOperands,
39119 // GIR_Coverage, 6872,
39120 GIR_EraseRootFromParent_Done,
39121 // Label 2311: @111873
39122 GIM_Reject,
39123 // Label 2306: @111874
39124 GIM_Reject,
39125 // Label 2289: @111875
39126 GIM_Reject,
39127 // Label 26: @111876
39128 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2314*/ GIMT_Encode4(112867),
39129 /*GILLT_s32*//*Label 2312*/ GIMT_Encode4(111895),
39130 /*GILLT_s64*//*Label 2313*/ GIMT_Encode4(112640),
39131 // Label 2312: @111895
39132 GIM_Try, /*On fail goto*//*Label 2315*/ GIMT_Encode4(112639),
39133 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
39134 GIM_Try, /*On fail goto*//*Label 2316*/ GIMT_Encode4(111952), // Rule ID 6893 //
39135 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39136 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
39137 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
39138 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39139 // MIs[0] Rn
39140 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39141 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39142 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39143 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_monotonic>> => (LDEORW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39144 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORW),
39145 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39146 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39147 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39148 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39149 GIR_RootConstrainSelectedInstOperands,
39150 // GIR_Coverage, 6893,
39151 GIR_EraseRootFromParent_Done,
39152 // Label 2316: @111952
39153 GIM_Try, /*On fail goto*//*Label 2317*/ GIMT_Encode4(112001), // Rule ID 6894 //
39154 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39155 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
39156 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
39157 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39158 // MIs[0] Rn
39159 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39160 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39161 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39162 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acquire>> => (LDEORAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39163 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORAW),
39164 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39165 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39166 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39167 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39168 GIR_RootConstrainSelectedInstOperands,
39169 // GIR_Coverage, 6894,
39170 GIR_EraseRootFromParent_Done,
39171 // Label 2317: @112001
39172 GIM_Try, /*On fail goto*//*Label 2318*/ GIMT_Encode4(112050), // Rule ID 6895 //
39173 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39174 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
39175 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
39176 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39177 // MIs[0] Rn
39178 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39179 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39180 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39181 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_release>> => (LDEORLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39182 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORLW),
39183 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39184 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39185 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39186 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39187 GIR_RootConstrainSelectedInstOperands,
39188 // GIR_Coverage, 6895,
39189 GIR_EraseRootFromParent_Done,
39190 // Label 2318: @112050
39191 GIM_Try, /*On fail goto*//*Label 2319*/ GIMT_Encode4(112099), // Rule ID 6896 //
39192 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39193 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
39194 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
39195 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39196 // MIs[0] Rn
39197 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39198 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39199 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39200 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acq_rel>> => (LDEORALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39201 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALW),
39202 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39203 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39204 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39205 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39206 GIR_RootConstrainSelectedInstOperands,
39207 // GIR_Coverage, 6896,
39208 GIR_EraseRootFromParent_Done,
39209 // Label 2319: @112099
39210 GIM_Try, /*On fail goto*//*Label 2320*/ GIMT_Encode4(112148), // Rule ID 6897 //
39211 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39212 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
39213 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
39214 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39215 // MIs[0] Rn
39216 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39217 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39218 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39219 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_seq_cst>> => (LDEORALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39220 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALW),
39221 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39222 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39223 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39224 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39225 GIR_RootConstrainSelectedInstOperands,
39226 // GIR_Coverage, 6897,
39227 GIR_EraseRootFromParent_Done,
39228 // Label 2320: @112148
39229 GIM_Try, /*On fail goto*//*Label 2321*/ GIMT_Encode4(112197), // Rule ID 6898 //
39230 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39231 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
39232 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
39233 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39234 // MIs[0] Rn
39235 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39236 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39237 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39238 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_monotonic>> => (LDEORH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39239 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORH),
39240 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39241 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39242 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39243 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39244 GIR_RootConstrainSelectedInstOperands,
39245 // GIR_Coverage, 6898,
39246 GIR_EraseRootFromParent_Done,
39247 // Label 2321: @112197
39248 GIM_Try, /*On fail goto*//*Label 2322*/ GIMT_Encode4(112246), // Rule ID 6899 //
39249 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39250 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
39251 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
39252 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39253 // MIs[0] Rn
39254 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39255 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39256 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39257 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_acquire>> => (LDEORAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39258 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORAH),
39259 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39260 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39261 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39262 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39263 GIR_RootConstrainSelectedInstOperands,
39264 // GIR_Coverage, 6899,
39265 GIR_EraseRootFromParent_Done,
39266 // Label 2322: @112246
39267 GIM_Try, /*On fail goto*//*Label 2323*/ GIMT_Encode4(112295), // Rule ID 6900 //
39268 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39269 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
39270 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
39271 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39272 // MIs[0] Rn
39273 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39274 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39275 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39276 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_release>> => (LDEORLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39277 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORLH),
39278 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39279 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39280 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39281 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39282 GIR_RootConstrainSelectedInstOperands,
39283 // GIR_Coverage, 6900,
39284 GIR_EraseRootFromParent_Done,
39285 // Label 2323: @112295
39286 GIM_Try, /*On fail goto*//*Label 2324*/ GIMT_Encode4(112344), // Rule ID 6901 //
39287 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39288 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
39289 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
39290 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39291 // MIs[0] Rn
39292 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39293 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39294 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39295 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_acq_rel>> => (LDEORALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39296 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALH),
39297 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39298 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39299 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39300 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39301 GIR_RootConstrainSelectedInstOperands,
39302 // GIR_Coverage, 6901,
39303 GIR_EraseRootFromParent_Done,
39304 // Label 2324: @112344
39305 GIM_Try, /*On fail goto*//*Label 2325*/ GIMT_Encode4(112393), // Rule ID 6902 //
39306 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39307 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
39308 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
39309 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39310 // MIs[0] Rn
39311 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39312 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39313 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39314 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_seq_cst>> => (LDEORALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39315 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALH),
39316 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39317 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39318 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39319 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39320 GIR_RootConstrainSelectedInstOperands,
39321 // GIR_Coverage, 6902,
39322 GIR_EraseRootFromParent_Done,
39323 // Label 2325: @112393
39324 GIM_Try, /*On fail goto*//*Label 2326*/ GIMT_Encode4(112442), // Rule ID 6903 //
39325 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39326 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
39327 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
39328 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39329 // MIs[0] Rn
39330 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39331 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39332 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39333 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_monotonic>> => (LDEORB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39334 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORB),
39335 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39336 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39337 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39338 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39339 GIR_RootConstrainSelectedInstOperands,
39340 // GIR_Coverage, 6903,
39341 GIR_EraseRootFromParent_Done,
39342 // Label 2326: @112442
39343 GIM_Try, /*On fail goto*//*Label 2327*/ GIMT_Encode4(112491), // Rule ID 6904 //
39344 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39345 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
39346 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
39347 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39348 // MIs[0] Rn
39349 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39350 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39351 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39352 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_acquire>> => (LDEORAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39353 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORAB),
39354 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39355 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39356 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39357 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39358 GIR_RootConstrainSelectedInstOperands,
39359 // GIR_Coverage, 6904,
39360 GIR_EraseRootFromParent_Done,
39361 // Label 2327: @112491
39362 GIM_Try, /*On fail goto*//*Label 2328*/ GIMT_Encode4(112540), // Rule ID 6905 //
39363 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39364 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
39365 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
39366 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39367 // MIs[0] Rn
39368 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39369 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39370 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39371 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_release>> => (LDEORLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39372 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORLB),
39373 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39374 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39375 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39376 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39377 GIR_RootConstrainSelectedInstOperands,
39378 // GIR_Coverage, 6905,
39379 GIR_EraseRootFromParent_Done,
39380 // Label 2328: @112540
39381 GIM_Try, /*On fail goto*//*Label 2329*/ GIMT_Encode4(112589), // Rule ID 6906 //
39382 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39383 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
39384 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
39385 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39386 // MIs[0] Rn
39387 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39388 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39389 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39390 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_acq_rel>> => (LDEORALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39391 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALB),
39392 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39393 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39394 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39395 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39396 GIR_RootConstrainSelectedInstOperands,
39397 // GIR_Coverage, 6906,
39398 GIR_EraseRootFromParent_Done,
39399 // Label 2329: @112589
39400 GIM_Try, /*On fail goto*//*Label 2330*/ GIMT_Encode4(112638), // Rule ID 6907 //
39401 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39402 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
39403 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
39404 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39405 // MIs[0] Rn
39406 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39407 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39408 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39409 // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_seq_cst>> => (LDEORALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39410 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALB),
39411 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39412 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39413 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39414 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39415 GIR_RootConstrainSelectedInstOperands,
39416 // GIR_Coverage, 6907,
39417 GIR_EraseRootFromParent_Done,
39418 // Label 2330: @112638
39419 GIM_Reject,
39420 // Label 2315: @112639
39421 GIM_Reject,
39422 // Label 2313: @112640
39423 GIM_Try, /*On fail goto*//*Label 2331*/ GIMT_Encode4(112866),
39424 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
39425 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
39426 GIM_Try, /*On fail goto*//*Label 2332*/ GIMT_Encode4(112697), // Rule ID 6888 //
39427 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39428 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
39429 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39430 // MIs[0] Rn
39431 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39432 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39433 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39434 // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_monotonic>> => (LDEORX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39435 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORX),
39436 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39437 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39438 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39439 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39440 GIR_RootConstrainSelectedInstOperands,
39441 // GIR_Coverage, 6888,
39442 GIR_EraseRootFromParent_Done,
39443 // Label 2332: @112697
39444 GIM_Try, /*On fail goto*//*Label 2333*/ GIMT_Encode4(112739), // Rule ID 6889 //
39445 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39446 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
39447 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39448 // MIs[0] Rn
39449 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39450 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39451 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39452 // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_acquire>> => (LDEORAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39453 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORAX),
39454 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39455 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39456 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39457 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39458 GIR_RootConstrainSelectedInstOperands,
39459 // GIR_Coverage, 6889,
39460 GIR_EraseRootFromParent_Done,
39461 // Label 2333: @112739
39462 GIM_Try, /*On fail goto*//*Label 2334*/ GIMT_Encode4(112781), // Rule ID 6890 //
39463 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39464 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
39465 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39466 // MIs[0] Rn
39467 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39468 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39469 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39470 // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_release>> => (LDEORLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39471 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORLX),
39472 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39473 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39474 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39475 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39476 GIR_RootConstrainSelectedInstOperands,
39477 // GIR_Coverage, 6890,
39478 GIR_EraseRootFromParent_Done,
39479 // Label 2334: @112781
39480 GIM_Try, /*On fail goto*//*Label 2335*/ GIMT_Encode4(112823), // Rule ID 6891 //
39481 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39482 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
39483 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39484 // MIs[0] Rn
39485 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39486 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39487 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39488 // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_acq_rel>> => (LDEORALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39489 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALX),
39490 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39491 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39492 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39493 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39494 GIR_RootConstrainSelectedInstOperands,
39495 // GIR_Coverage, 6891,
39496 GIR_EraseRootFromParent_Done,
39497 // Label 2335: @112823
39498 GIM_Try, /*On fail goto*//*Label 2336*/ GIMT_Encode4(112865), // Rule ID 6892 //
39499 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39500 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
39501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39502 // MIs[0] Rn
39503 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39504 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39505 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39506 // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_seq_cst>> => (LDEORALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39507 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALX),
39508 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39509 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39510 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39511 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39512 GIR_RootConstrainSelectedInstOperands,
39513 // GIR_Coverage, 6892,
39514 GIR_EraseRootFromParent_Done,
39515 // Label 2336: @112865
39516 GIM_Reject,
39517 // Label 2331: @112866
39518 GIM_Reject,
39519 // Label 2314: @112867
39520 GIM_Reject,
39521 // Label 27: @112868
39522 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2339*/ GIMT_Encode4(113859),
39523 /*GILLT_s32*//*Label 2337*/ GIMT_Encode4(112887),
39524 /*GILLT_s64*//*Label 2338*/ GIMT_Encode4(113632),
39525 // Label 2337: @112887
39526 GIM_Try, /*On fail goto*//*Label 2340*/ GIMT_Encode4(113631),
39527 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
39528 GIM_Try, /*On fail goto*//*Label 2341*/ GIMT_Encode4(112944), // Rule ID 6933 //
39529 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39530 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
39531 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
39532 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39533 // MIs[0] Rn
39534 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39535 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39536 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39537 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_monotonic>> => (LDSMAXW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39538 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXW),
39539 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39540 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39541 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39542 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39543 GIR_RootConstrainSelectedInstOperands,
39544 // GIR_Coverage, 6933,
39545 GIR_EraseRootFromParent_Done,
39546 // Label 2341: @112944
39547 GIM_Try, /*On fail goto*//*Label 2342*/ GIMT_Encode4(112993), // Rule ID 6934 //
39548 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39549 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
39550 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
39551 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39552 // MIs[0] Rn
39553 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39554 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39555 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39556 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acquire>> => (LDSMAXAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39557 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXAW),
39558 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39559 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39560 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39561 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39562 GIR_RootConstrainSelectedInstOperands,
39563 // GIR_Coverage, 6934,
39564 GIR_EraseRootFromParent_Done,
39565 // Label 2342: @112993
39566 GIM_Try, /*On fail goto*//*Label 2343*/ GIMT_Encode4(113042), // Rule ID 6935 //
39567 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39568 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
39569 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
39570 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39571 // MIs[0] Rn
39572 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39573 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39574 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39575 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_release>> => (LDSMAXLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39576 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXLW),
39577 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39578 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39579 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39580 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39581 GIR_RootConstrainSelectedInstOperands,
39582 // GIR_Coverage, 6935,
39583 GIR_EraseRootFromParent_Done,
39584 // Label 2343: @113042
39585 GIM_Try, /*On fail goto*//*Label 2344*/ GIMT_Encode4(113091), // Rule ID 6936 //
39586 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39587 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
39588 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
39589 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39590 // MIs[0] Rn
39591 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39592 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39593 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39594 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acq_rel>> => (LDSMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39595 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALW),
39596 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39597 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39598 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39599 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39600 GIR_RootConstrainSelectedInstOperands,
39601 // GIR_Coverage, 6936,
39602 GIR_EraseRootFromParent_Done,
39603 // Label 2344: @113091
39604 GIM_Try, /*On fail goto*//*Label 2345*/ GIMT_Encode4(113140), // Rule ID 6937 //
39605 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39606 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
39607 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
39608 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39609 // MIs[0] Rn
39610 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39611 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39612 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39613 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_seq_cst>> => (LDSMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39614 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALW),
39615 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39616 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39617 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39618 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39619 GIR_RootConstrainSelectedInstOperands,
39620 // GIR_Coverage, 6937,
39621 GIR_EraseRootFromParent_Done,
39622 // Label 2345: @113140
39623 GIM_Try, /*On fail goto*//*Label 2346*/ GIMT_Encode4(113189), // Rule ID 6938 //
39624 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39625 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
39626 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
39627 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39628 // MIs[0] Rn
39629 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39630 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39631 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39632 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_monotonic>> => (LDSMAXH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39633 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXH),
39634 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39635 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39636 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39637 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39638 GIR_RootConstrainSelectedInstOperands,
39639 // GIR_Coverage, 6938,
39640 GIR_EraseRootFromParent_Done,
39641 // Label 2346: @113189
39642 GIM_Try, /*On fail goto*//*Label 2347*/ GIMT_Encode4(113238), // Rule ID 6939 //
39643 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39644 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
39645 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
39646 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39647 // MIs[0] Rn
39648 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39649 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39650 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39651 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_acquire>> => (LDSMAXAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39652 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXAH),
39653 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39654 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39655 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39656 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39657 GIR_RootConstrainSelectedInstOperands,
39658 // GIR_Coverage, 6939,
39659 GIR_EraseRootFromParent_Done,
39660 // Label 2347: @113238
39661 GIM_Try, /*On fail goto*//*Label 2348*/ GIMT_Encode4(113287), // Rule ID 6940 //
39662 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39663 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
39664 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
39665 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39666 // MIs[0] Rn
39667 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39668 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39669 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39670 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_release>> => (LDSMAXLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39671 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXLH),
39672 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39673 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39674 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39675 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39676 GIR_RootConstrainSelectedInstOperands,
39677 // GIR_Coverage, 6940,
39678 GIR_EraseRootFromParent_Done,
39679 // Label 2348: @113287
39680 GIM_Try, /*On fail goto*//*Label 2349*/ GIMT_Encode4(113336), // Rule ID 6941 //
39681 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39682 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
39683 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
39684 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39685 // MIs[0] Rn
39686 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39687 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39688 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39689 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_acq_rel>> => (LDSMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39690 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALH),
39691 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39692 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39693 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39694 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39695 GIR_RootConstrainSelectedInstOperands,
39696 // GIR_Coverage, 6941,
39697 GIR_EraseRootFromParent_Done,
39698 // Label 2349: @113336
39699 GIM_Try, /*On fail goto*//*Label 2350*/ GIMT_Encode4(113385), // Rule ID 6942 //
39700 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39701 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
39702 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
39703 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39704 // MIs[0] Rn
39705 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39706 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39707 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39708 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_seq_cst>> => (LDSMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39709 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALH),
39710 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39711 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39712 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39713 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39714 GIR_RootConstrainSelectedInstOperands,
39715 // GIR_Coverage, 6942,
39716 GIR_EraseRootFromParent_Done,
39717 // Label 2350: @113385
39718 GIM_Try, /*On fail goto*//*Label 2351*/ GIMT_Encode4(113434), // Rule ID 6943 //
39719 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39720 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
39721 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
39722 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39723 // MIs[0] Rn
39724 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39725 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39726 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39727 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_monotonic>> => (LDSMAXB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39728 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXB),
39729 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39730 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39731 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39732 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39733 GIR_RootConstrainSelectedInstOperands,
39734 // GIR_Coverage, 6943,
39735 GIR_EraseRootFromParent_Done,
39736 // Label 2351: @113434
39737 GIM_Try, /*On fail goto*//*Label 2352*/ GIMT_Encode4(113483), // Rule ID 6944 //
39738 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39739 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
39740 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
39741 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39742 // MIs[0] Rn
39743 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39744 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39745 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39746 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_acquire>> => (LDSMAXAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39747 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXAB),
39748 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39749 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39750 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39751 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39752 GIR_RootConstrainSelectedInstOperands,
39753 // GIR_Coverage, 6944,
39754 GIR_EraseRootFromParent_Done,
39755 // Label 2352: @113483
39756 GIM_Try, /*On fail goto*//*Label 2353*/ GIMT_Encode4(113532), // Rule ID 6945 //
39757 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39758 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
39759 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
39760 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39761 // MIs[0] Rn
39762 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39763 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39764 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39765 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_release>> => (LDSMAXLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39766 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXLB),
39767 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39768 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39769 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39770 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39771 GIR_RootConstrainSelectedInstOperands,
39772 // GIR_Coverage, 6945,
39773 GIR_EraseRootFromParent_Done,
39774 // Label 2353: @113532
39775 GIM_Try, /*On fail goto*//*Label 2354*/ GIMT_Encode4(113581), // Rule ID 6946 //
39776 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39777 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
39778 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
39779 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39780 // MIs[0] Rn
39781 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39782 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39783 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39784 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_acq_rel>> => (LDSMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39785 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALB),
39786 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39787 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39788 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39789 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39790 GIR_RootConstrainSelectedInstOperands,
39791 // GIR_Coverage, 6946,
39792 GIR_EraseRootFromParent_Done,
39793 // Label 2354: @113581
39794 GIM_Try, /*On fail goto*//*Label 2355*/ GIMT_Encode4(113630), // Rule ID 6947 //
39795 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39796 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
39797 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
39798 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39799 // MIs[0] Rn
39800 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39801 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39802 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39803 // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_seq_cst>> => (LDSMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39804 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALB),
39805 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39806 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39807 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39808 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39809 GIR_RootConstrainSelectedInstOperands,
39810 // GIR_Coverage, 6947,
39811 GIR_EraseRootFromParent_Done,
39812 // Label 2355: @113630
39813 GIM_Reject,
39814 // Label 2340: @113631
39815 GIM_Reject,
39816 // Label 2338: @113632
39817 GIM_Try, /*On fail goto*//*Label 2356*/ GIMT_Encode4(113858),
39818 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
39819 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
39820 GIM_Try, /*On fail goto*//*Label 2357*/ GIMT_Encode4(113689), // Rule ID 6928 //
39821 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39822 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
39823 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39824 // MIs[0] Rn
39825 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39826 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39827 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39828 // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_monotonic>> => (LDSMAXX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39829 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXX),
39830 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39831 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39832 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39833 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39834 GIR_RootConstrainSelectedInstOperands,
39835 // GIR_Coverage, 6928,
39836 GIR_EraseRootFromParent_Done,
39837 // Label 2357: @113689
39838 GIM_Try, /*On fail goto*//*Label 2358*/ GIMT_Encode4(113731), // Rule ID 6929 //
39839 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39840 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
39841 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39842 // MIs[0] Rn
39843 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39844 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39845 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39846 // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_acquire>> => (LDSMAXAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39847 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXAX),
39848 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39849 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39850 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39851 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39852 GIR_RootConstrainSelectedInstOperands,
39853 // GIR_Coverage, 6929,
39854 GIR_EraseRootFromParent_Done,
39855 // Label 2358: @113731
39856 GIM_Try, /*On fail goto*//*Label 2359*/ GIMT_Encode4(113773), // Rule ID 6930 //
39857 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39858 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
39859 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39860 // MIs[0] Rn
39861 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39862 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39863 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39864 // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_release>> => (LDSMAXLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39865 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXLX),
39866 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39867 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39868 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39869 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39870 GIR_RootConstrainSelectedInstOperands,
39871 // GIR_Coverage, 6930,
39872 GIR_EraseRootFromParent_Done,
39873 // Label 2359: @113773
39874 GIM_Try, /*On fail goto*//*Label 2360*/ GIMT_Encode4(113815), // Rule ID 6931 //
39875 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39876 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
39877 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39878 // MIs[0] Rn
39879 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39880 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39881 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39882 // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_acq_rel>> => (LDSMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39883 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALX),
39884 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39885 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39886 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39887 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39888 GIR_RootConstrainSelectedInstOperands,
39889 // GIR_Coverage, 6931,
39890 GIR_EraseRootFromParent_Done,
39891 // Label 2360: @113815
39892 GIM_Try, /*On fail goto*//*Label 2361*/ GIMT_Encode4(113857), // Rule ID 6932 //
39893 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39894 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
39895 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39896 // MIs[0] Rn
39897 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39898 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39899 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
39900 // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_seq_cst>> => (LDSMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39901 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALX),
39902 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39903 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39904 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39905 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39906 GIR_RootConstrainSelectedInstOperands,
39907 // GIR_Coverage, 6932,
39908 GIR_EraseRootFromParent_Done,
39909 // Label 2361: @113857
39910 GIM_Reject,
39911 // Label 2356: @113858
39912 GIM_Reject,
39913 // Label 2339: @113859
39914 GIM_Reject,
39915 // Label 28: @113860
39916 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2364*/ GIMT_Encode4(114851),
39917 /*GILLT_s32*//*Label 2362*/ GIMT_Encode4(113879),
39918 /*GILLT_s64*//*Label 2363*/ GIMT_Encode4(114624),
39919 // Label 2362: @113879
39920 GIM_Try, /*On fail goto*//*Label 2365*/ GIMT_Encode4(114623),
39921 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
39922 GIM_Try, /*On fail goto*//*Label 2366*/ GIMT_Encode4(113936), // Rule ID 6953 //
39923 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39924 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
39925 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
39926 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39927 // MIs[0] Rn
39928 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39929 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39930 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39931 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_monotonic>> => (LDSMINW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39932 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINW),
39933 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39934 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39935 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39936 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39937 GIR_RootConstrainSelectedInstOperands,
39938 // GIR_Coverage, 6953,
39939 GIR_EraseRootFromParent_Done,
39940 // Label 2366: @113936
39941 GIM_Try, /*On fail goto*//*Label 2367*/ GIMT_Encode4(113985), // Rule ID 6954 //
39942 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39943 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
39944 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
39945 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39946 // MIs[0] Rn
39947 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39948 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39949 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39950 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acquire>> => (LDSMINAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39951 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINAW),
39952 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39953 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39954 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39955 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39956 GIR_RootConstrainSelectedInstOperands,
39957 // GIR_Coverage, 6954,
39958 GIR_EraseRootFromParent_Done,
39959 // Label 2367: @113985
39960 GIM_Try, /*On fail goto*//*Label 2368*/ GIMT_Encode4(114034), // Rule ID 6955 //
39961 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39962 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
39963 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
39964 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39965 // MIs[0] Rn
39966 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39967 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39968 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39969 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_release>> => (LDSMINLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39970 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINLW),
39971 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39972 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39973 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39974 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39975 GIR_RootConstrainSelectedInstOperands,
39976 // GIR_Coverage, 6955,
39977 GIR_EraseRootFromParent_Done,
39978 // Label 2368: @114034
39979 GIM_Try, /*On fail goto*//*Label 2369*/ GIMT_Encode4(114083), // Rule ID 6956 //
39980 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
39981 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
39982 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
39983 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39984 // MIs[0] Rn
39985 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
39986 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
39987 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
39988 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acq_rel>> => (LDSMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
39989 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALW),
39990 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
39991 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39992 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39993 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
39994 GIR_RootConstrainSelectedInstOperands,
39995 // GIR_Coverage, 6956,
39996 GIR_EraseRootFromParent_Done,
39997 // Label 2369: @114083
39998 GIM_Try, /*On fail goto*//*Label 2370*/ GIMT_Encode4(114132), // Rule ID 6957 //
39999 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40000 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
40001 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
40002 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40003 // MIs[0] Rn
40004 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40005 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40006 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40007 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_seq_cst>> => (LDSMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40008 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALW),
40009 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40010 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40011 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40012 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40013 GIR_RootConstrainSelectedInstOperands,
40014 // GIR_Coverage, 6957,
40015 GIR_EraseRootFromParent_Done,
40016 // Label 2370: @114132
40017 GIM_Try, /*On fail goto*//*Label 2371*/ GIMT_Encode4(114181), // Rule ID 6958 //
40018 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40019 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
40020 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
40021 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40022 // MIs[0] Rn
40023 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40024 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40025 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40026 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_monotonic>> => (LDSMINH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40027 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINH),
40028 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40029 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40030 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40031 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40032 GIR_RootConstrainSelectedInstOperands,
40033 // GIR_Coverage, 6958,
40034 GIR_EraseRootFromParent_Done,
40035 // Label 2371: @114181
40036 GIM_Try, /*On fail goto*//*Label 2372*/ GIMT_Encode4(114230), // Rule ID 6959 //
40037 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40038 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
40039 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
40040 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40041 // MIs[0] Rn
40042 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40043 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40044 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40045 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_acquire>> => (LDSMINAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40046 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINAH),
40047 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40048 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40049 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40050 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40051 GIR_RootConstrainSelectedInstOperands,
40052 // GIR_Coverage, 6959,
40053 GIR_EraseRootFromParent_Done,
40054 // Label 2372: @114230
40055 GIM_Try, /*On fail goto*//*Label 2373*/ GIMT_Encode4(114279), // Rule ID 6960 //
40056 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40057 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
40058 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
40059 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40060 // MIs[0] Rn
40061 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40062 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40063 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40064 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_release>> => (LDSMINLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40065 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINLH),
40066 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40067 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40068 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40069 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40070 GIR_RootConstrainSelectedInstOperands,
40071 // GIR_Coverage, 6960,
40072 GIR_EraseRootFromParent_Done,
40073 // Label 2373: @114279
40074 GIM_Try, /*On fail goto*//*Label 2374*/ GIMT_Encode4(114328), // Rule ID 6961 //
40075 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40076 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
40077 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
40078 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40079 // MIs[0] Rn
40080 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40081 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40082 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40083 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_acq_rel>> => (LDSMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40084 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALH),
40085 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40086 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40087 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40088 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40089 GIR_RootConstrainSelectedInstOperands,
40090 // GIR_Coverage, 6961,
40091 GIR_EraseRootFromParent_Done,
40092 // Label 2374: @114328
40093 GIM_Try, /*On fail goto*//*Label 2375*/ GIMT_Encode4(114377), // Rule ID 6962 //
40094 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40095 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
40096 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
40097 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40098 // MIs[0] Rn
40099 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40100 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40101 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40102 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_seq_cst>> => (LDSMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40103 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALH),
40104 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40105 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40106 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40107 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40108 GIR_RootConstrainSelectedInstOperands,
40109 // GIR_Coverage, 6962,
40110 GIR_EraseRootFromParent_Done,
40111 // Label 2375: @114377
40112 GIM_Try, /*On fail goto*//*Label 2376*/ GIMT_Encode4(114426), // Rule ID 6963 //
40113 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40114 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
40115 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
40116 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40117 // MIs[0] Rn
40118 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40119 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40120 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40121 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_monotonic>> => (LDSMINB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40122 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINB),
40123 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40124 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40125 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40126 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40127 GIR_RootConstrainSelectedInstOperands,
40128 // GIR_Coverage, 6963,
40129 GIR_EraseRootFromParent_Done,
40130 // Label 2376: @114426
40131 GIM_Try, /*On fail goto*//*Label 2377*/ GIMT_Encode4(114475), // Rule ID 6964 //
40132 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40133 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
40134 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
40135 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40136 // MIs[0] Rn
40137 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40138 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40139 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40140 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_acquire>> => (LDSMINAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40141 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINAB),
40142 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40143 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40144 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40145 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40146 GIR_RootConstrainSelectedInstOperands,
40147 // GIR_Coverage, 6964,
40148 GIR_EraseRootFromParent_Done,
40149 // Label 2377: @114475
40150 GIM_Try, /*On fail goto*//*Label 2378*/ GIMT_Encode4(114524), // Rule ID 6965 //
40151 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40152 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
40153 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
40154 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40155 // MIs[0] Rn
40156 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40157 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40158 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40159 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_release>> => (LDSMINLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40160 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINLB),
40161 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40162 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40163 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40164 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40165 GIR_RootConstrainSelectedInstOperands,
40166 // GIR_Coverage, 6965,
40167 GIR_EraseRootFromParent_Done,
40168 // Label 2378: @114524
40169 GIM_Try, /*On fail goto*//*Label 2379*/ GIMT_Encode4(114573), // Rule ID 6966 //
40170 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40171 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
40172 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
40173 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40174 // MIs[0] Rn
40175 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40176 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40177 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40178 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_acq_rel>> => (LDSMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40179 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALB),
40180 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40181 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40182 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40183 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40184 GIR_RootConstrainSelectedInstOperands,
40185 // GIR_Coverage, 6966,
40186 GIR_EraseRootFromParent_Done,
40187 // Label 2379: @114573
40188 GIM_Try, /*On fail goto*//*Label 2380*/ GIMT_Encode4(114622), // Rule ID 6967 //
40189 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40190 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
40191 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
40192 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40193 // MIs[0] Rn
40194 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40195 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40196 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40197 // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_seq_cst>> => (LDSMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40198 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALB),
40199 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40200 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40201 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40202 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40203 GIR_RootConstrainSelectedInstOperands,
40204 // GIR_Coverage, 6967,
40205 GIR_EraseRootFromParent_Done,
40206 // Label 2380: @114622
40207 GIM_Reject,
40208 // Label 2365: @114623
40209 GIM_Reject,
40210 // Label 2363: @114624
40211 GIM_Try, /*On fail goto*//*Label 2381*/ GIMT_Encode4(114850),
40212 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
40213 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
40214 GIM_Try, /*On fail goto*//*Label 2382*/ GIMT_Encode4(114681), // Rule ID 6948 //
40215 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40216 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
40217 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40218 // MIs[0] Rn
40219 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40220 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40221 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40222 // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_monotonic>> => (LDSMINX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40223 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINX),
40224 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40225 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40226 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40227 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40228 GIR_RootConstrainSelectedInstOperands,
40229 // GIR_Coverage, 6948,
40230 GIR_EraseRootFromParent_Done,
40231 // Label 2382: @114681
40232 GIM_Try, /*On fail goto*//*Label 2383*/ GIMT_Encode4(114723), // Rule ID 6949 //
40233 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40234 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
40235 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40236 // MIs[0] Rn
40237 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40238 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40239 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40240 // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_acquire>> => (LDSMINAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40241 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINAX),
40242 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40243 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40244 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40245 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40246 GIR_RootConstrainSelectedInstOperands,
40247 // GIR_Coverage, 6949,
40248 GIR_EraseRootFromParent_Done,
40249 // Label 2383: @114723
40250 GIM_Try, /*On fail goto*//*Label 2384*/ GIMT_Encode4(114765), // Rule ID 6950 //
40251 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40252 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
40253 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40254 // MIs[0] Rn
40255 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40256 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40257 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40258 // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_release>> => (LDSMINLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40259 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINLX),
40260 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40261 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40262 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40263 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40264 GIR_RootConstrainSelectedInstOperands,
40265 // GIR_Coverage, 6950,
40266 GIR_EraseRootFromParent_Done,
40267 // Label 2384: @114765
40268 GIM_Try, /*On fail goto*//*Label 2385*/ GIMT_Encode4(114807), // Rule ID 6951 //
40269 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40270 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
40271 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40272 // MIs[0] Rn
40273 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40274 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40275 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40276 // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_acq_rel>> => (LDSMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40277 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALX),
40278 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40279 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40280 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40281 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40282 GIR_RootConstrainSelectedInstOperands,
40283 // GIR_Coverage, 6951,
40284 GIR_EraseRootFromParent_Done,
40285 // Label 2385: @114807
40286 GIM_Try, /*On fail goto*//*Label 2386*/ GIMT_Encode4(114849), // Rule ID 6952 //
40287 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40288 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
40289 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40290 // MIs[0] Rn
40291 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40292 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40293 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40294 // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_seq_cst>> => (LDSMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40295 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALX),
40296 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40297 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40298 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40299 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40300 GIR_RootConstrainSelectedInstOperands,
40301 // GIR_Coverage, 6952,
40302 GIR_EraseRootFromParent_Done,
40303 // Label 2386: @114849
40304 GIM_Reject,
40305 // Label 2381: @114850
40306 GIM_Reject,
40307 // Label 2364: @114851
40308 GIM_Reject,
40309 // Label 29: @114852
40310 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2389*/ GIMT_Encode4(115843),
40311 /*GILLT_s32*//*Label 2387*/ GIMT_Encode4(114871),
40312 /*GILLT_s64*//*Label 2388*/ GIMT_Encode4(115616),
40313 // Label 2387: @114871
40314 GIM_Try, /*On fail goto*//*Label 2390*/ GIMT_Encode4(115615),
40315 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
40316 GIM_Try, /*On fail goto*//*Label 2391*/ GIMT_Encode4(114928), // Rule ID 6973 //
40317 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40318 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
40319 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
40320 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40321 // MIs[0] Rn
40322 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40323 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40324 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40325 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_monotonic>> => (LDUMAXW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40326 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXW),
40327 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40328 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40329 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40330 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40331 GIR_RootConstrainSelectedInstOperands,
40332 // GIR_Coverage, 6973,
40333 GIR_EraseRootFromParent_Done,
40334 // Label 2391: @114928
40335 GIM_Try, /*On fail goto*//*Label 2392*/ GIMT_Encode4(114977), // Rule ID 6974 //
40336 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40337 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
40338 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
40339 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40340 // MIs[0] Rn
40341 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40342 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40343 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40344 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acquire>> => (LDUMAXAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40345 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXAW),
40346 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40347 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40348 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40349 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40350 GIR_RootConstrainSelectedInstOperands,
40351 // GIR_Coverage, 6974,
40352 GIR_EraseRootFromParent_Done,
40353 // Label 2392: @114977
40354 GIM_Try, /*On fail goto*//*Label 2393*/ GIMT_Encode4(115026), // Rule ID 6975 //
40355 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40356 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
40357 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
40358 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40359 // MIs[0] Rn
40360 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40361 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40362 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40363 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_release>> => (LDUMAXLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40364 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXLW),
40365 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40366 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40367 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40368 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40369 GIR_RootConstrainSelectedInstOperands,
40370 // GIR_Coverage, 6975,
40371 GIR_EraseRootFromParent_Done,
40372 // Label 2393: @115026
40373 GIM_Try, /*On fail goto*//*Label 2394*/ GIMT_Encode4(115075), // Rule ID 6976 //
40374 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40375 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
40376 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
40377 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40378 // MIs[0] Rn
40379 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40380 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40381 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40382 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acq_rel>> => (LDUMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40383 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALW),
40384 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40385 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40386 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40387 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40388 GIR_RootConstrainSelectedInstOperands,
40389 // GIR_Coverage, 6976,
40390 GIR_EraseRootFromParent_Done,
40391 // Label 2394: @115075
40392 GIM_Try, /*On fail goto*//*Label 2395*/ GIMT_Encode4(115124), // Rule ID 6977 //
40393 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40394 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
40395 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
40396 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40397 // MIs[0] Rn
40398 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40399 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40400 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40401 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_seq_cst>> => (LDUMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40402 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALW),
40403 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40404 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40405 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40406 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40407 GIR_RootConstrainSelectedInstOperands,
40408 // GIR_Coverage, 6977,
40409 GIR_EraseRootFromParent_Done,
40410 // Label 2395: @115124
40411 GIM_Try, /*On fail goto*//*Label 2396*/ GIMT_Encode4(115173), // Rule ID 6978 //
40412 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40413 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
40414 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
40415 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40416 // MIs[0] Rn
40417 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40418 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40419 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40420 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_monotonic>> => (LDUMAXH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40421 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXH),
40422 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40423 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40424 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40425 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40426 GIR_RootConstrainSelectedInstOperands,
40427 // GIR_Coverage, 6978,
40428 GIR_EraseRootFromParent_Done,
40429 // Label 2396: @115173
40430 GIM_Try, /*On fail goto*//*Label 2397*/ GIMT_Encode4(115222), // Rule ID 6979 //
40431 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40432 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
40433 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
40434 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40435 // MIs[0] Rn
40436 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40437 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40438 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40439 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_acquire>> => (LDUMAXAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40440 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXAH),
40441 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40442 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40443 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40444 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40445 GIR_RootConstrainSelectedInstOperands,
40446 // GIR_Coverage, 6979,
40447 GIR_EraseRootFromParent_Done,
40448 // Label 2397: @115222
40449 GIM_Try, /*On fail goto*//*Label 2398*/ GIMT_Encode4(115271), // Rule ID 6980 //
40450 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40451 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
40452 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
40453 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40454 // MIs[0] Rn
40455 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40456 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40457 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40458 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_release>> => (LDUMAXLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40459 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXLH),
40460 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40461 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40462 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40463 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40464 GIR_RootConstrainSelectedInstOperands,
40465 // GIR_Coverage, 6980,
40466 GIR_EraseRootFromParent_Done,
40467 // Label 2398: @115271
40468 GIM_Try, /*On fail goto*//*Label 2399*/ GIMT_Encode4(115320), // Rule ID 6981 //
40469 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40470 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
40471 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
40472 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40473 // MIs[0] Rn
40474 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40475 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40476 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40477 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_acq_rel>> => (LDUMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40478 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALH),
40479 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40480 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40481 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40482 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40483 GIR_RootConstrainSelectedInstOperands,
40484 // GIR_Coverage, 6981,
40485 GIR_EraseRootFromParent_Done,
40486 // Label 2399: @115320
40487 GIM_Try, /*On fail goto*//*Label 2400*/ GIMT_Encode4(115369), // Rule ID 6982 //
40488 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40489 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
40490 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
40491 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40492 // MIs[0] Rn
40493 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40494 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40495 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40496 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_seq_cst>> => (LDUMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40497 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALH),
40498 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40499 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40500 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40501 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40502 GIR_RootConstrainSelectedInstOperands,
40503 // GIR_Coverage, 6982,
40504 GIR_EraseRootFromParent_Done,
40505 // Label 2400: @115369
40506 GIM_Try, /*On fail goto*//*Label 2401*/ GIMT_Encode4(115418), // Rule ID 6983 //
40507 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40508 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
40509 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
40510 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40511 // MIs[0] Rn
40512 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40513 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40514 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40515 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_monotonic>> => (LDUMAXB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40516 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXB),
40517 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40518 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40519 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40520 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40521 GIR_RootConstrainSelectedInstOperands,
40522 // GIR_Coverage, 6983,
40523 GIR_EraseRootFromParent_Done,
40524 // Label 2401: @115418
40525 GIM_Try, /*On fail goto*//*Label 2402*/ GIMT_Encode4(115467), // Rule ID 6984 //
40526 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40527 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
40528 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
40529 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40530 // MIs[0] Rn
40531 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40532 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40533 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40534 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_acquire>> => (LDUMAXAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40535 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXAB),
40536 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40537 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40538 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40539 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40540 GIR_RootConstrainSelectedInstOperands,
40541 // GIR_Coverage, 6984,
40542 GIR_EraseRootFromParent_Done,
40543 // Label 2402: @115467
40544 GIM_Try, /*On fail goto*//*Label 2403*/ GIMT_Encode4(115516), // Rule ID 6985 //
40545 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40546 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
40547 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
40548 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40549 // MIs[0] Rn
40550 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40551 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40552 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40553 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_release>> => (LDUMAXLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40554 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXLB),
40555 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40556 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40557 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40558 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40559 GIR_RootConstrainSelectedInstOperands,
40560 // GIR_Coverage, 6985,
40561 GIR_EraseRootFromParent_Done,
40562 // Label 2403: @115516
40563 GIM_Try, /*On fail goto*//*Label 2404*/ GIMT_Encode4(115565), // Rule ID 6986 //
40564 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40565 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
40566 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
40567 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40568 // MIs[0] Rn
40569 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40570 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40571 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40572 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_acq_rel>> => (LDUMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40573 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALB),
40574 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40575 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40576 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40577 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40578 GIR_RootConstrainSelectedInstOperands,
40579 // GIR_Coverage, 6986,
40580 GIR_EraseRootFromParent_Done,
40581 // Label 2404: @115565
40582 GIM_Try, /*On fail goto*//*Label 2405*/ GIMT_Encode4(115614), // Rule ID 6987 //
40583 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40584 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
40585 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
40586 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40587 // MIs[0] Rn
40588 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40589 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40590 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40591 // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_seq_cst>> => (LDUMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40592 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALB),
40593 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40594 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40595 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40596 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40597 GIR_RootConstrainSelectedInstOperands,
40598 // GIR_Coverage, 6987,
40599 GIR_EraseRootFromParent_Done,
40600 // Label 2405: @115614
40601 GIM_Reject,
40602 // Label 2390: @115615
40603 GIM_Reject,
40604 // Label 2388: @115616
40605 GIM_Try, /*On fail goto*//*Label 2406*/ GIMT_Encode4(115842),
40606 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
40607 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
40608 GIM_Try, /*On fail goto*//*Label 2407*/ GIMT_Encode4(115673), // Rule ID 6968 //
40609 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40610 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
40611 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40612 // MIs[0] Rn
40613 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40614 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40615 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40616 // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_monotonic>> => (LDUMAXX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40617 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXX),
40618 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40619 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40620 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40621 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40622 GIR_RootConstrainSelectedInstOperands,
40623 // GIR_Coverage, 6968,
40624 GIR_EraseRootFromParent_Done,
40625 // Label 2407: @115673
40626 GIM_Try, /*On fail goto*//*Label 2408*/ GIMT_Encode4(115715), // Rule ID 6969 //
40627 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40628 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
40629 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40630 // MIs[0] Rn
40631 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40632 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40633 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40634 // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_acquire>> => (LDUMAXAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40635 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXAX),
40636 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40637 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40638 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40639 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40640 GIR_RootConstrainSelectedInstOperands,
40641 // GIR_Coverage, 6969,
40642 GIR_EraseRootFromParent_Done,
40643 // Label 2408: @115715
40644 GIM_Try, /*On fail goto*//*Label 2409*/ GIMT_Encode4(115757), // Rule ID 6970 //
40645 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40646 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
40647 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40648 // MIs[0] Rn
40649 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40650 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40651 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40652 // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_release>> => (LDUMAXLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40653 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXLX),
40654 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40655 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40656 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40657 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40658 GIR_RootConstrainSelectedInstOperands,
40659 // GIR_Coverage, 6970,
40660 GIR_EraseRootFromParent_Done,
40661 // Label 2409: @115757
40662 GIM_Try, /*On fail goto*//*Label 2410*/ GIMT_Encode4(115799), // Rule ID 6971 //
40663 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40664 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
40665 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40666 // MIs[0] Rn
40667 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40668 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40669 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40670 // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_acq_rel>> => (LDUMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40671 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALX),
40672 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40673 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40674 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40675 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40676 GIR_RootConstrainSelectedInstOperands,
40677 // GIR_Coverage, 6971,
40678 GIR_EraseRootFromParent_Done,
40679 // Label 2410: @115799
40680 GIM_Try, /*On fail goto*//*Label 2411*/ GIMT_Encode4(115841), // Rule ID 6972 //
40681 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40682 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
40683 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40684 // MIs[0] Rn
40685 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40686 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40687 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
40688 // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_seq_cst>> => (LDUMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40689 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALX),
40690 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40691 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40692 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40693 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40694 GIR_RootConstrainSelectedInstOperands,
40695 // GIR_Coverage, 6972,
40696 GIR_EraseRootFromParent_Done,
40697 // Label 2411: @115841
40698 GIM_Reject,
40699 // Label 2406: @115842
40700 GIM_Reject,
40701 // Label 2389: @115843
40702 GIM_Reject,
40703 // Label 30: @115844
40704 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2414*/ GIMT_Encode4(116835),
40705 /*GILLT_s32*//*Label 2412*/ GIMT_Encode4(115863),
40706 /*GILLT_s64*//*Label 2413*/ GIMT_Encode4(116608),
40707 // Label 2412: @115863
40708 GIM_Try, /*On fail goto*//*Label 2415*/ GIMT_Encode4(116607),
40709 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
40710 GIM_Try, /*On fail goto*//*Label 2416*/ GIMT_Encode4(115920), // Rule ID 6993 //
40711 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40712 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
40713 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
40714 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40715 // MIs[0] Rn
40716 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40717 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40718 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40719 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_monotonic>> => (LDUMINW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40720 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINW),
40721 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40722 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40723 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40724 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40725 GIR_RootConstrainSelectedInstOperands,
40726 // GIR_Coverage, 6993,
40727 GIR_EraseRootFromParent_Done,
40728 // Label 2416: @115920
40729 GIM_Try, /*On fail goto*//*Label 2417*/ GIMT_Encode4(115969), // Rule ID 6994 //
40730 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40731 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
40732 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
40733 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40734 // MIs[0] Rn
40735 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40736 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40737 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40738 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acquire>> => (LDUMINAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40739 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINAW),
40740 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40741 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40742 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40743 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40744 GIR_RootConstrainSelectedInstOperands,
40745 // GIR_Coverage, 6994,
40746 GIR_EraseRootFromParent_Done,
40747 // Label 2417: @115969
40748 GIM_Try, /*On fail goto*//*Label 2418*/ GIMT_Encode4(116018), // Rule ID 6995 //
40749 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40750 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
40751 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
40752 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40753 // MIs[0] Rn
40754 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40755 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40756 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40757 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_release>> => (LDUMINLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40758 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINLW),
40759 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40760 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40761 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40762 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40763 GIR_RootConstrainSelectedInstOperands,
40764 // GIR_Coverage, 6995,
40765 GIR_EraseRootFromParent_Done,
40766 // Label 2418: @116018
40767 GIM_Try, /*On fail goto*//*Label 2419*/ GIMT_Encode4(116067), // Rule ID 6996 //
40768 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40769 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
40770 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
40771 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40772 // MIs[0] Rn
40773 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40774 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40775 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40776 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acq_rel>> => (LDUMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40777 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALW),
40778 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40779 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40780 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40781 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40782 GIR_RootConstrainSelectedInstOperands,
40783 // GIR_Coverage, 6996,
40784 GIR_EraseRootFromParent_Done,
40785 // Label 2419: @116067
40786 GIM_Try, /*On fail goto*//*Label 2420*/ GIMT_Encode4(116116), // Rule ID 6997 //
40787 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40788 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
40789 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
40790 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40791 // MIs[0] Rn
40792 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40793 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40794 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40795 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_seq_cst>> => (LDUMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40796 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALW),
40797 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40798 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40799 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40800 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40801 GIR_RootConstrainSelectedInstOperands,
40802 // GIR_Coverage, 6997,
40803 GIR_EraseRootFromParent_Done,
40804 // Label 2420: @116116
40805 GIM_Try, /*On fail goto*//*Label 2421*/ GIMT_Encode4(116165), // Rule ID 6998 //
40806 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40807 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
40808 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
40809 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40810 // MIs[0] Rn
40811 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40812 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40813 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40814 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_monotonic>> => (LDUMINH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40815 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINH),
40816 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40817 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40818 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40819 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40820 GIR_RootConstrainSelectedInstOperands,
40821 // GIR_Coverage, 6998,
40822 GIR_EraseRootFromParent_Done,
40823 // Label 2421: @116165
40824 GIM_Try, /*On fail goto*//*Label 2422*/ GIMT_Encode4(116214), // Rule ID 6999 //
40825 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40826 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
40827 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
40828 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40829 // MIs[0] Rn
40830 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40831 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40832 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40833 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_acquire>> => (LDUMINAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40834 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINAH),
40835 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40836 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40837 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40838 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40839 GIR_RootConstrainSelectedInstOperands,
40840 // GIR_Coverage, 6999,
40841 GIR_EraseRootFromParent_Done,
40842 // Label 2422: @116214
40843 GIM_Try, /*On fail goto*//*Label 2423*/ GIMT_Encode4(116263), // Rule ID 7000 //
40844 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40845 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
40846 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
40847 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40848 // MIs[0] Rn
40849 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40850 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40851 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40852 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_release>> => (LDUMINLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40853 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINLH),
40854 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40855 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40856 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40857 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40858 GIR_RootConstrainSelectedInstOperands,
40859 // GIR_Coverage, 7000,
40860 GIR_EraseRootFromParent_Done,
40861 // Label 2423: @116263
40862 GIM_Try, /*On fail goto*//*Label 2424*/ GIMT_Encode4(116312), // Rule ID 7001 //
40863 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40864 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
40865 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
40866 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40867 // MIs[0] Rn
40868 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40869 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40870 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40871 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_acq_rel>> => (LDUMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40872 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALH),
40873 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40874 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40875 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40876 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40877 GIR_RootConstrainSelectedInstOperands,
40878 // GIR_Coverage, 7001,
40879 GIR_EraseRootFromParent_Done,
40880 // Label 2424: @116312
40881 GIM_Try, /*On fail goto*//*Label 2425*/ GIMT_Encode4(116361), // Rule ID 7002 //
40882 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40883 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
40884 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
40885 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40886 // MIs[0] Rn
40887 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40888 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40889 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40890 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_seq_cst>> => (LDUMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40891 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALH),
40892 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40893 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40894 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40895 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40896 GIR_RootConstrainSelectedInstOperands,
40897 // GIR_Coverage, 7002,
40898 GIR_EraseRootFromParent_Done,
40899 // Label 2425: @116361
40900 GIM_Try, /*On fail goto*//*Label 2426*/ GIMT_Encode4(116410), // Rule ID 7003 //
40901 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40902 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
40903 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
40904 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40905 // MIs[0] Rn
40906 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40907 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40908 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40909 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_monotonic>> => (LDUMINB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40910 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINB),
40911 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40912 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40913 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40914 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40915 GIR_RootConstrainSelectedInstOperands,
40916 // GIR_Coverage, 7003,
40917 GIR_EraseRootFromParent_Done,
40918 // Label 2426: @116410
40919 GIM_Try, /*On fail goto*//*Label 2427*/ GIMT_Encode4(116459), // Rule ID 7004 //
40920 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40921 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
40922 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
40923 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40924 // MIs[0] Rn
40925 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40926 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40927 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40928 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_acquire>> => (LDUMINAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40929 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINAB),
40930 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40931 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40932 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40933 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40934 GIR_RootConstrainSelectedInstOperands,
40935 // GIR_Coverage, 7004,
40936 GIR_EraseRootFromParent_Done,
40937 // Label 2427: @116459
40938 GIM_Try, /*On fail goto*//*Label 2428*/ GIMT_Encode4(116508), // Rule ID 7005 //
40939 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40940 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
40941 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
40942 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40943 // MIs[0] Rn
40944 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40945 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40946 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40947 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_release>> => (LDUMINLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40948 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINLB),
40949 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40950 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40951 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40952 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40953 GIR_RootConstrainSelectedInstOperands,
40954 // GIR_Coverage, 7005,
40955 GIR_EraseRootFromParent_Done,
40956 // Label 2428: @116508
40957 GIM_Try, /*On fail goto*//*Label 2429*/ GIMT_Encode4(116557), // Rule ID 7006 //
40958 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40959 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
40960 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
40961 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40962 // MIs[0] Rn
40963 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40964 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40965 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40966 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_acq_rel>> => (LDUMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40967 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALB),
40968 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40969 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40970 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40971 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40972 GIR_RootConstrainSelectedInstOperands,
40973 // GIR_Coverage, 7006,
40974 GIR_EraseRootFromParent_Done,
40975 // Label 2429: @116557
40976 GIM_Try, /*On fail goto*//*Label 2430*/ GIMT_Encode4(116606), // Rule ID 7007 //
40977 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
40978 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
40979 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
40980 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40981 // MIs[0] Rn
40982 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
40983 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
40984 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
40985 // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_seq_cst>> => (LDUMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
40986 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALB),
40987 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
40988 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
40989 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
40990 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
40991 GIR_RootConstrainSelectedInstOperands,
40992 // GIR_Coverage, 7007,
40993 GIR_EraseRootFromParent_Done,
40994 // Label 2430: @116606
40995 GIM_Reject,
40996 // Label 2415: @116607
40997 GIM_Reject,
40998 // Label 2413: @116608
40999 GIM_Try, /*On fail goto*//*Label 2431*/ GIMT_Encode4(116834),
41000 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41001 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
41002 GIM_Try, /*On fail goto*//*Label 2432*/ GIMT_Encode4(116665), // Rule ID 6988 //
41003 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
41004 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
41005 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41006 // MIs[0] Rn
41007 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
41008 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
41009 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41010 // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_monotonic>> => (LDUMINX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
41011 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINX),
41012 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
41013 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
41014 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
41015 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
41016 GIR_RootConstrainSelectedInstOperands,
41017 // GIR_Coverage, 6988,
41018 GIR_EraseRootFromParent_Done,
41019 // Label 2432: @116665
41020 GIM_Try, /*On fail goto*//*Label 2433*/ GIMT_Encode4(116707), // Rule ID 6989 //
41021 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
41022 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
41023 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41024 // MIs[0] Rn
41025 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
41026 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
41027 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41028 // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_acquire>> => (LDUMINAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
41029 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINAX),
41030 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
41031 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
41032 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
41033 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
41034 GIR_RootConstrainSelectedInstOperands,
41035 // GIR_Coverage, 6989,
41036 GIR_EraseRootFromParent_Done,
41037 // Label 2433: @116707
41038 GIM_Try, /*On fail goto*//*Label 2434*/ GIMT_Encode4(116749), // Rule ID 6990 //
41039 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
41040 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
41041 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41042 // MIs[0] Rn
41043 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
41044 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
41045 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41046 // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_release>> => (LDUMINLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
41047 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINLX),
41048 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
41049 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
41050 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
41051 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
41052 GIR_RootConstrainSelectedInstOperands,
41053 // GIR_Coverage, 6990,
41054 GIR_EraseRootFromParent_Done,
41055 // Label 2434: @116749
41056 GIM_Try, /*On fail goto*//*Label 2435*/ GIMT_Encode4(116791), // Rule ID 6991 //
41057 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
41058 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
41059 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41060 // MIs[0] Rn
41061 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
41062 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
41063 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41064 // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_acq_rel>> => (LDUMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
41065 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALX),
41066 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
41067 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
41068 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
41069 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
41070 GIR_RootConstrainSelectedInstOperands,
41071 // GIR_Coverage, 6991,
41072 GIR_EraseRootFromParent_Done,
41073 // Label 2435: @116791
41074 GIM_Try, /*On fail goto*//*Label 2436*/ GIMT_Encode4(116833), // Rule ID 6992 //
41075 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
41076 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
41077 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41078 // MIs[0] Rn
41079 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
41080 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
41081 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41082 // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_seq_cst>> => (LDUMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
41083 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALX),
41084 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
41085 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
41086 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
41087 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
41088 GIR_RootConstrainSelectedInstOperands,
41089 // GIR_Coverage, 6992,
41090 GIR_EraseRootFromParent_Done,
41091 // Label 2436: @116833
41092 GIM_Reject,
41093 // Label 2431: @116834
41094 GIM_Reject,
41095 // Label 2414: @116835
41096 GIM_Reject,
41097 // Label 31: @116836
41098 GIM_Try, /*On fail goto*//*Label 2437*/ GIMT_Encode4(116863), // Rule ID 6740 //
41099 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41100 GIM_CheckConstantInt8, /*MI*/0, /*Op*/0, 4,
41101 // MIs[0] Operand 1
41102 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
41103 // (atomic_fence 4:{ *:[i64] }, (timm:{ *:[i64] })) => (DMB 9:{ *:[i32] })
41104 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DMB),
41105 GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
41106 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
41107 GIR_RootConstrainSelectedInstOperands,
41108 // GIR_Coverage, 6740,
41109 GIR_EraseRootFromParent_Done,
41110 // Label 2437: @116863
41111 GIM_Try, /*On fail goto*//*Label 2438*/ GIMT_Encode4(116886), // Rule ID 6741 //
41112 // MIs[0] Operand 0
41113 GIM_CheckIsImm, /*MI*/0, /*Op*/0,
41114 // MIs[0] Operand 1
41115 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
41116 // (atomic_fence (timm:{ *:[iPTR] }), (timm:{ *:[iPTR] })) => (DMB 11:{ *:[i32] })
41117 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DMB),
41118 GIR_AddImm8, /*InsnID*/0, /*Imm*/11,
41119 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
41120 GIR_RootConstrainSelectedInstOperands,
41121 // GIR_Coverage, 6741,
41122 GIR_EraseRootFromParent_Done,
41123 // Label 2438: @116886
41124 GIM_Reject,
41125 // Label 32: @116887
41126 GIM_Try, /*On fail goto*//*Label 2439*/ GIMT_Encode4(131109),
41127 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
41128 GIM_Try, /*On fail goto*//*Label 2440*/ GIMT_Encode4(116986), // Rule ID 6098 //
41129 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFuseAES),
41130 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aesmc),
41131 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
41132 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
41133 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
41134 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41135 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
41136 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
41137 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aese),
41138 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
41139 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
41140 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
41141 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
41142 GIM_CheckIsSafeToFold, /*NumInsns*/1,
41143 // (intrinsic_wo_chain:{ *:[v16i8] } 496:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v16i8] } 494:{ *:[iPTR] }, V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2)) => (AESMCrrTied:{ *:[v16i8] } (AESErr:{ *:[v16i8] } V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2))
41144 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
41145 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::AESErr),
41146 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41147 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
41148 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // src2
41149 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41150 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESMCrrTied),
41151 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41152 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41153 GIR_RootConstrainSelectedInstOperands,
41154 // GIR_Coverage, 6098,
41155 GIR_EraseRootFromParent_Done,
41156 // Label 2440: @116986
41157 GIM_Try, /*On fail goto*//*Label 2441*/ GIMT_Encode4(117077), // Rule ID 6099 //
41158 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFuseAES),
41159 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aesimc),
41160 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
41161 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
41162 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
41163 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41164 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
41165 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
41166 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aesd),
41167 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
41168 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
41169 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
41170 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
41171 GIM_CheckIsSafeToFold, /*NumInsns*/1,
41172 // (intrinsic_wo_chain:{ *:[v16i8] } 495:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v16i8] } 493:{ *:[iPTR] }, V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2)) => (AESIMCrrTied:{ *:[v16i8] } (AESDrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2))
41173 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
41174 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::AESDrr),
41175 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
41176 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
41177 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // src2
41178 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41179 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESIMCrrTied),
41180 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41181 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41182 GIR_RootConstrainSelectedInstOperands,
41183 // GIR_Coverage, 6099,
41184 GIR_EraseRootFromParent_Done,
41185 // Label 2441: @117077
41186 GIM_Try, /*On fail goto*//*Label 2442*/ GIMT_Encode4(117117), // Rule ID 2550 //
41187 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
41188 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
41189 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41190 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41191 // MIs[0] pattern
41192 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
41193 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
41194 // (intrinsic_wo_chain:{ *:[i64] } 1148:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern) => (CNTB_XPiI:{ *:[i64] } (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
41195 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTB_XPiI),
41196 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41197 GIR_RootToRootCopy, /*OpIdx*/2, // pattern
41198 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
41199 GIR_RootConstrainSelectedInstOperands,
41200 // GIR_Coverage, 2550,
41201 GIR_EraseRootFromParent_Done,
41202 // Label 2442: @117117
41203 GIM_Try, /*On fail goto*//*Label 2443*/ GIMT_Encode4(117157), // Rule ID 9611 //
41204 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
41205 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
41206 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41207 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41208 // MIs[0] pattern
41209 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
41210 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
41211 // (intrinsic_wo_chain:{ *:[i64] } 1150:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern) => (CNTH_XPiI:{ *:[i64] } (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
41212 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTH_XPiI),
41213 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41214 GIR_RootToRootCopy, /*OpIdx*/2, // pattern
41215 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
41216 GIR_RootConstrainSelectedInstOperands,
41217 // GIR_Coverage, 9611,
41218 GIR_EraseRootFromParent_Done,
41219 // Label 2443: @117157
41220 GIM_Try, /*On fail goto*//*Label 2444*/ GIMT_Encode4(117197), // Rule ID 9614 //
41221 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
41222 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
41223 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41224 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41225 // MIs[0] pattern
41226 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
41227 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
41228 // (intrinsic_wo_chain:{ *:[i64] } 1156:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern) => (CNTW_XPiI:{ *:[i64] } (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
41229 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTW_XPiI),
41230 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41231 GIR_RootToRootCopy, /*OpIdx*/2, // pattern
41232 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
41233 GIR_RootConstrainSelectedInstOperands,
41234 // GIR_Coverage, 9614,
41235 GIR_EraseRootFromParent_Done,
41236 // Label 2444: @117197
41237 GIM_Try, /*On fail goto*//*Label 2445*/ GIMT_Encode4(117237), // Rule ID 9617 //
41238 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
41239 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
41240 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41241 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41242 // MIs[0] pattern
41243 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
41244 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
41245 // (intrinsic_wo_chain:{ *:[i64] } 1149:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern) => (CNTD_XPiI:{ *:[i64] } (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
41246 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTD_XPiI),
41247 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41248 GIR_RootToRootCopy, /*OpIdx*/2, // pattern
41249 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
41250 GIR_RootConstrainSelectedInstOperands,
41251 // GIR_Coverage, 9617,
41252 GIR_EraseRootFromParent_Done,
41253 // Label 2445: @117237
41254 GIM_Try, /*On fail goto*//*Label 2446*/ GIMT_Encode4(117273), // Rule ID 39 //
41255 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON),
41256 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_bfcvtn),
41257 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
41258 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
41259 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
41260 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
41261 // (intrinsic_wo_chain:{ *:[v8bf16] } 554:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (BFCVTN:{ *:[v8bf16] } V128:{ *:[v4f32] }:$Rn)
41262 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN),
41263 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41264 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41265 GIR_RootConstrainSelectedInstOperands,
41266 // GIR_Coverage, 39,
41267 GIR_EraseRootFromParent_Done,
41268 // Label 2446: @117273
41269 GIM_Try, /*On fail goto*//*Label 2447*/ GIMT_Encode4(117309), // Rule ID 41 //
41270 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEONandIsStreamingSafe),
41271 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_bfcvt),
41272 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
41273 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41274 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
41275 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
41276 // (intrinsic_wo_chain:{ *:[bf16] } 553:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (BFCVT:{ *:[bf16] } FPR32:{ *:[f32] }:$Rn)
41277 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVT),
41278 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41279 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41280 GIR_RootConstrainSelectedInstOperands,
41281 // GIR_Coverage, 41,
41282 GIR_EraseRootFromParent_Done,
41283 // Label 2447: @117309
41284 GIM_Try, /*On fail goto*//*Label 2448*/ GIMT_Encode4(117348), // Rule ID 78 //
41285 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasJS),
41286 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_fjcvtzs),
41287 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41288 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41289 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41290 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
41291 // (intrinsic_wo_chain:{ *:[i32] } 528:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FJCVTZS:{ *:[i32] }:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
41292 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FJCVTZS),
41293 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41294 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41295 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
41296 GIR_RootConstrainSelectedInstOperands,
41297 // GIR_Coverage, 78,
41298 GIR_EraseRootFromParent_Done,
41299 // Label 2448: @117348
41300 GIM_Try, /*On fail goto*//*Label 2449*/ GIMT_Encode4(117384), // Rule ID 356 //
41301 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41302 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
41303 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41304 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41305 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41306 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
41307 // (intrinsic_wo_chain:{ *:[i32] } 566:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTASUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
41308 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWHr),
41309 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41310 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41311 GIR_RootConstrainSelectedInstOperands,
41312 // GIR_Coverage, 356,
41313 GIR_EraseRootFromParent_Done,
41314 // Label 2449: @117384
41315 GIM_Try, /*On fail goto*//*Label 2450*/ GIMT_Encode4(117420), // Rule ID 357 //
41316 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41317 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
41318 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41319 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41320 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41321 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
41322 // (intrinsic_wo_chain:{ *:[i64] } 566:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTASUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
41323 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXHr),
41324 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41325 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41326 GIR_RootConstrainSelectedInstOperands,
41327 // GIR_Coverage, 357,
41328 GIR_EraseRootFromParent_Done,
41329 // Label 2450: @117420
41330 GIM_Try, /*On fail goto*//*Label 2451*/ GIMT_Encode4(117456), // Rule ID 358 //
41331 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41332 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
41333 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41334 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41335 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41336 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
41337 // (intrinsic_wo_chain:{ *:[i32] } 566:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTASUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
41338 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWSr),
41339 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41340 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41341 GIR_RootConstrainSelectedInstOperands,
41342 // GIR_Coverage, 358,
41343 GIR_EraseRootFromParent_Done,
41344 // Label 2451: @117456
41345 GIM_Try, /*On fail goto*//*Label 2452*/ GIMT_Encode4(117492), // Rule ID 359 //
41346 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41347 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
41348 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41349 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41350 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41351 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
41352 // (intrinsic_wo_chain:{ *:[i64] } 566:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTASUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
41353 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXSr),
41354 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41355 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41356 GIR_RootConstrainSelectedInstOperands,
41357 // GIR_Coverage, 359,
41358 GIR_EraseRootFromParent_Done,
41359 // Label 2452: @117492
41360 GIM_Try, /*On fail goto*//*Label 2453*/ GIMT_Encode4(117528), // Rule ID 360 //
41361 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41362 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
41363 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41364 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41365 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41366 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
41367 // (intrinsic_wo_chain:{ *:[i32] } 566:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTASUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
41368 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWDr),
41369 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41370 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41371 GIR_RootConstrainSelectedInstOperands,
41372 // GIR_Coverage, 360,
41373 GIR_EraseRootFromParent_Done,
41374 // Label 2453: @117528
41375 GIM_Try, /*On fail goto*//*Label 2454*/ GIMT_Encode4(117564), // Rule ID 361 //
41376 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41377 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
41378 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41379 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41380 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41381 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
41382 // (intrinsic_wo_chain:{ *:[i64] } 566:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTASUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
41383 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXDr),
41384 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41385 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41386 GIR_RootConstrainSelectedInstOperands,
41387 // GIR_Coverage, 361,
41388 GIR_EraseRootFromParent_Done,
41389 // Label 2454: @117564
41390 GIM_Try, /*On fail goto*//*Label 2455*/ GIMT_Encode4(117600), // Rule ID 362 //
41391 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41392 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
41393 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41394 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41395 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41396 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
41397 // (intrinsic_wo_chain:{ *:[i32] } 567:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTAUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
41398 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUWHr),
41399 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41400 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41401 GIR_RootConstrainSelectedInstOperands,
41402 // GIR_Coverage, 362,
41403 GIR_EraseRootFromParent_Done,
41404 // Label 2455: @117600
41405 GIM_Try, /*On fail goto*//*Label 2456*/ GIMT_Encode4(117636), // Rule ID 363 //
41406 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41407 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
41408 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41409 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41410 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41411 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
41412 // (intrinsic_wo_chain:{ *:[i64] } 567:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTAUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
41413 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUXHr),
41414 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41415 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41416 GIR_RootConstrainSelectedInstOperands,
41417 // GIR_Coverage, 363,
41418 GIR_EraseRootFromParent_Done,
41419 // Label 2456: @117636
41420 GIM_Try, /*On fail goto*//*Label 2457*/ GIMT_Encode4(117672), // Rule ID 364 //
41421 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41422 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
41423 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41424 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41425 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41426 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
41427 // (intrinsic_wo_chain:{ *:[i32] } 567:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTAUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
41428 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUWSr),
41429 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41430 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41431 GIR_RootConstrainSelectedInstOperands,
41432 // GIR_Coverage, 364,
41433 GIR_EraseRootFromParent_Done,
41434 // Label 2457: @117672
41435 GIM_Try, /*On fail goto*//*Label 2458*/ GIMT_Encode4(117708), // Rule ID 365 //
41436 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41437 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
41438 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41439 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41440 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41441 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
41442 // (intrinsic_wo_chain:{ *:[i64] } 567:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTAUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
41443 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUXSr),
41444 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41445 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41446 GIR_RootConstrainSelectedInstOperands,
41447 // GIR_Coverage, 365,
41448 GIR_EraseRootFromParent_Done,
41449 // Label 2458: @117708
41450 GIM_Try, /*On fail goto*//*Label 2459*/ GIMT_Encode4(117744), // Rule ID 366 //
41451 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41452 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
41453 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41454 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41455 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41456 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
41457 // (intrinsic_wo_chain:{ *:[i32] } 567:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTAUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
41458 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUWDr),
41459 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41460 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41461 GIR_RootConstrainSelectedInstOperands,
41462 // GIR_Coverage, 366,
41463 GIR_EraseRootFromParent_Done,
41464 // Label 2459: @117744
41465 GIM_Try, /*On fail goto*//*Label 2460*/ GIMT_Encode4(117780), // Rule ID 367 //
41466 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41467 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
41468 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41469 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41470 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41471 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
41472 // (intrinsic_wo_chain:{ *:[i64] } 567:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTAUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
41473 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUXDr),
41474 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41475 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41476 GIR_RootConstrainSelectedInstOperands,
41477 // GIR_Coverage, 367,
41478 GIR_EraseRootFromParent_Done,
41479 // Label 2460: @117780
41480 GIM_Try, /*On fail goto*//*Label 2461*/ GIMT_Encode4(117816), // Rule ID 368 //
41481 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41482 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
41483 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41484 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41485 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41486 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
41487 // (intrinsic_wo_chain:{ *:[i32] } 568:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
41488 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUWHr),
41489 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41490 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41491 GIR_RootConstrainSelectedInstOperands,
41492 // GIR_Coverage, 368,
41493 GIR_EraseRootFromParent_Done,
41494 // Label 2461: @117816
41495 GIM_Try, /*On fail goto*//*Label 2462*/ GIMT_Encode4(117852), // Rule ID 369 //
41496 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41497 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
41498 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41499 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41500 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41501 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
41502 // (intrinsic_wo_chain:{ *:[i64] } 568:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
41503 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUXHr),
41504 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41505 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41506 GIR_RootConstrainSelectedInstOperands,
41507 // GIR_Coverage, 369,
41508 GIR_EraseRootFromParent_Done,
41509 // Label 2462: @117852
41510 GIM_Try, /*On fail goto*//*Label 2463*/ GIMT_Encode4(117888), // Rule ID 370 //
41511 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41512 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
41513 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41514 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41515 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41516 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
41517 // (intrinsic_wo_chain:{ *:[i32] } 568:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
41518 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUWSr),
41519 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41520 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41521 GIR_RootConstrainSelectedInstOperands,
41522 // GIR_Coverage, 370,
41523 GIR_EraseRootFromParent_Done,
41524 // Label 2463: @117888
41525 GIM_Try, /*On fail goto*//*Label 2464*/ GIMT_Encode4(117924), // Rule ID 371 //
41526 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41527 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
41528 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41529 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41530 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41531 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
41532 // (intrinsic_wo_chain:{ *:[i64] } 568:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
41533 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUXSr),
41534 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41535 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41536 GIR_RootConstrainSelectedInstOperands,
41537 // GIR_Coverage, 371,
41538 GIR_EraseRootFromParent_Done,
41539 // Label 2464: @117924
41540 GIM_Try, /*On fail goto*//*Label 2465*/ GIMT_Encode4(117960), // Rule ID 372 //
41541 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41542 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
41543 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41544 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41545 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41546 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
41547 // (intrinsic_wo_chain:{ *:[i32] } 568:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
41548 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUWDr),
41549 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41550 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41551 GIR_RootConstrainSelectedInstOperands,
41552 // GIR_Coverage, 372,
41553 GIR_EraseRootFromParent_Done,
41554 // Label 2465: @117960
41555 GIM_Try, /*On fail goto*//*Label 2466*/ GIMT_Encode4(117996), // Rule ID 373 //
41556 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41557 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
41558 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41559 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41560 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41561 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
41562 // (intrinsic_wo_chain:{ *:[i64] } 568:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
41563 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUXDr),
41564 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41565 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41566 GIR_RootConstrainSelectedInstOperands,
41567 // GIR_Coverage, 373,
41568 GIR_EraseRootFromParent_Done,
41569 // Label 2466: @117996
41570 GIM_Try, /*On fail goto*//*Label 2467*/ GIMT_Encode4(118032), // Rule ID 374 //
41571 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41572 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
41573 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41574 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41575 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41576 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
41577 // (intrinsic_wo_chain:{ *:[i32] } 569:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
41578 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUWHr),
41579 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41580 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41581 GIR_RootConstrainSelectedInstOperands,
41582 // GIR_Coverage, 374,
41583 GIR_EraseRootFromParent_Done,
41584 // Label 2467: @118032
41585 GIM_Try, /*On fail goto*//*Label 2468*/ GIMT_Encode4(118068), // Rule ID 375 //
41586 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41587 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
41588 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41589 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41590 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41591 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
41592 // (intrinsic_wo_chain:{ *:[i64] } 569:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTMUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
41593 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUXHr),
41594 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41595 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41596 GIR_RootConstrainSelectedInstOperands,
41597 // GIR_Coverage, 375,
41598 GIR_EraseRootFromParent_Done,
41599 // Label 2468: @118068
41600 GIM_Try, /*On fail goto*//*Label 2469*/ GIMT_Encode4(118104), // Rule ID 376 //
41601 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41602 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
41603 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41604 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41605 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41606 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
41607 // (intrinsic_wo_chain:{ *:[i32] } 569:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
41608 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUWSr),
41609 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41610 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41611 GIR_RootConstrainSelectedInstOperands,
41612 // GIR_Coverage, 376,
41613 GIR_EraseRootFromParent_Done,
41614 // Label 2469: @118104
41615 GIM_Try, /*On fail goto*//*Label 2470*/ GIMT_Encode4(118140), // Rule ID 377 //
41616 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41617 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
41618 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41619 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41620 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41621 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
41622 // (intrinsic_wo_chain:{ *:[i64] } 569:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTMUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
41623 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUXSr),
41624 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41625 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41626 GIR_RootConstrainSelectedInstOperands,
41627 // GIR_Coverage, 377,
41628 GIR_EraseRootFromParent_Done,
41629 // Label 2470: @118140
41630 GIM_Try, /*On fail goto*//*Label 2471*/ GIMT_Encode4(118176), // Rule ID 378 //
41631 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41632 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
41633 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41634 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41635 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41636 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
41637 // (intrinsic_wo_chain:{ *:[i32] } 569:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
41638 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUWDr),
41639 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41640 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41641 GIR_RootConstrainSelectedInstOperands,
41642 // GIR_Coverage, 378,
41643 GIR_EraseRootFromParent_Done,
41644 // Label 2471: @118176
41645 GIM_Try, /*On fail goto*//*Label 2472*/ GIMT_Encode4(118212), // Rule ID 379 //
41646 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41647 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
41648 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41649 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41650 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41651 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
41652 // (intrinsic_wo_chain:{ *:[i64] } 569:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTMUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
41653 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUXDr),
41654 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41655 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41656 GIR_RootConstrainSelectedInstOperands,
41657 // GIR_Coverage, 379,
41658 GIR_EraseRootFromParent_Done,
41659 // Label 2472: @118212
41660 GIM_Try, /*On fail goto*//*Label 2473*/ GIMT_Encode4(118248), // Rule ID 380 //
41661 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41662 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
41663 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41664 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41665 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41666 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
41667 // (intrinsic_wo_chain:{ *:[i32] } 570:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
41668 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSUWHr),
41669 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41670 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41671 GIR_RootConstrainSelectedInstOperands,
41672 // GIR_Coverage, 380,
41673 GIR_EraseRootFromParent_Done,
41674 // Label 2473: @118248
41675 GIM_Try, /*On fail goto*//*Label 2474*/ GIMT_Encode4(118284), // Rule ID 381 //
41676 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41677 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
41678 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41679 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41680 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41681 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
41682 // (intrinsic_wo_chain:{ *:[i64] } 570:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
41683 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSUXHr),
41684 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41685 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41686 GIR_RootConstrainSelectedInstOperands,
41687 // GIR_Coverage, 381,
41688 GIR_EraseRootFromParent_Done,
41689 // Label 2474: @118284
41690 GIM_Try, /*On fail goto*//*Label 2475*/ GIMT_Encode4(118320), // Rule ID 382 //
41691 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41692 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
41693 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41694 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41695 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41696 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
41697 // (intrinsic_wo_chain:{ *:[i32] } 570:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
41698 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSUWSr),
41699 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41700 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41701 GIR_RootConstrainSelectedInstOperands,
41702 // GIR_Coverage, 382,
41703 GIR_EraseRootFromParent_Done,
41704 // Label 2475: @118320
41705 GIM_Try, /*On fail goto*//*Label 2476*/ GIMT_Encode4(118356), // Rule ID 383 //
41706 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41707 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
41708 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41709 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41710 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41711 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
41712 // (intrinsic_wo_chain:{ *:[i64] } 570:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
41713 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSUXSr),
41714 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41715 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41716 GIR_RootConstrainSelectedInstOperands,
41717 // GIR_Coverage, 383,
41718 GIR_EraseRootFromParent_Done,
41719 // Label 2476: @118356
41720 GIM_Try, /*On fail goto*//*Label 2477*/ GIMT_Encode4(118392), // Rule ID 384 //
41721 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41722 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
41723 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41724 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41725 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41726 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
41727 // (intrinsic_wo_chain:{ *:[i32] } 570:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
41728 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSUWDr),
41729 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41730 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41731 GIR_RootConstrainSelectedInstOperands,
41732 // GIR_Coverage, 384,
41733 GIR_EraseRootFromParent_Done,
41734 // Label 2477: @118392
41735 GIM_Try, /*On fail goto*//*Label 2478*/ GIMT_Encode4(118428), // Rule ID 385 //
41736 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41737 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
41738 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41739 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41740 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41741 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
41742 // (intrinsic_wo_chain:{ *:[i64] } 570:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
41743 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSUXDr),
41744 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41745 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41746 GIR_RootConstrainSelectedInstOperands,
41747 // GIR_Coverage, 385,
41748 GIR_EraseRootFromParent_Done,
41749 // Label 2478: @118428
41750 GIM_Try, /*On fail goto*//*Label 2479*/ GIMT_Encode4(118464), // Rule ID 386 //
41751 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41752 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
41753 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41754 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41755 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41756 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
41757 // (intrinsic_wo_chain:{ *:[i32] } 571:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
41758 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUUWHr),
41759 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41760 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41761 GIR_RootConstrainSelectedInstOperands,
41762 // GIR_Coverage, 386,
41763 GIR_EraseRootFromParent_Done,
41764 // Label 2479: @118464
41765 GIM_Try, /*On fail goto*//*Label 2480*/ GIMT_Encode4(118500), // Rule ID 387 //
41766 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41767 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
41768 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41769 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41770 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41771 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
41772 // (intrinsic_wo_chain:{ *:[i64] } 571:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTNUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
41773 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUUXHr),
41774 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41775 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41776 GIR_RootConstrainSelectedInstOperands,
41777 // GIR_Coverage, 387,
41778 GIR_EraseRootFromParent_Done,
41779 // Label 2480: @118500
41780 GIM_Try, /*On fail goto*//*Label 2481*/ GIMT_Encode4(118536), // Rule ID 388 //
41781 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41782 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
41783 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41784 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41785 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41786 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
41787 // (intrinsic_wo_chain:{ *:[i32] } 571:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
41788 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUUWSr),
41789 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41790 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41791 GIR_RootConstrainSelectedInstOperands,
41792 // GIR_Coverage, 388,
41793 GIR_EraseRootFromParent_Done,
41794 // Label 2481: @118536
41795 GIM_Try, /*On fail goto*//*Label 2482*/ GIMT_Encode4(118572), // Rule ID 389 //
41796 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41797 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
41798 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41799 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41800 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41801 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
41802 // (intrinsic_wo_chain:{ *:[i64] } 571:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTNUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
41803 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUUXSr),
41804 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41805 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41806 GIR_RootConstrainSelectedInstOperands,
41807 // GIR_Coverage, 389,
41808 GIR_EraseRootFromParent_Done,
41809 // Label 2482: @118572
41810 GIM_Try, /*On fail goto*//*Label 2483*/ GIMT_Encode4(118608), // Rule ID 390 //
41811 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41812 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
41813 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41814 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41815 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41816 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
41817 // (intrinsic_wo_chain:{ *:[i32] } 571:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
41818 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUUWDr),
41819 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41820 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41821 GIR_RootConstrainSelectedInstOperands,
41822 // GIR_Coverage, 390,
41823 GIR_EraseRootFromParent_Done,
41824 // Label 2483: @118608
41825 GIM_Try, /*On fail goto*//*Label 2484*/ GIMT_Encode4(118644), // Rule ID 391 //
41826 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41827 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
41828 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41829 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41830 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41831 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
41832 // (intrinsic_wo_chain:{ *:[i64] } 571:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTNUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
41833 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUUXDr),
41834 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41835 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41836 GIR_RootConstrainSelectedInstOperands,
41837 // GIR_Coverage, 391,
41838 GIR_EraseRootFromParent_Done,
41839 // Label 2484: @118644
41840 GIM_Try, /*On fail goto*//*Label 2485*/ GIMT_Encode4(118680), // Rule ID 392 //
41841 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41842 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
41843 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41844 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41845 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41846 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
41847 // (intrinsic_wo_chain:{ *:[i32] } 572:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
41848 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUWHr),
41849 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41850 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41851 GIR_RootConstrainSelectedInstOperands,
41852 // GIR_Coverage, 392,
41853 GIR_EraseRootFromParent_Done,
41854 // Label 2485: @118680
41855 GIM_Try, /*On fail goto*//*Label 2486*/ GIMT_Encode4(118716), // Rule ID 393 //
41856 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41857 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
41858 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41859 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41860 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41861 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
41862 // (intrinsic_wo_chain:{ *:[i64] } 572:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
41863 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUXHr),
41864 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41865 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41866 GIR_RootConstrainSelectedInstOperands,
41867 // GIR_Coverage, 393,
41868 GIR_EraseRootFromParent_Done,
41869 // Label 2486: @118716
41870 GIM_Try, /*On fail goto*//*Label 2487*/ GIMT_Encode4(118752), // Rule ID 394 //
41871 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41872 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
41873 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41874 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41875 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41876 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
41877 // (intrinsic_wo_chain:{ *:[i32] } 572:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
41878 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUWSr),
41879 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41880 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41881 GIR_RootConstrainSelectedInstOperands,
41882 // GIR_Coverage, 394,
41883 GIR_EraseRootFromParent_Done,
41884 // Label 2487: @118752
41885 GIM_Try, /*On fail goto*//*Label 2488*/ GIMT_Encode4(118788), // Rule ID 395 //
41886 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41887 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
41888 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41889 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41890 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41891 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
41892 // (intrinsic_wo_chain:{ *:[i64] } 572:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
41893 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUXSr),
41894 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41895 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41896 GIR_RootConstrainSelectedInstOperands,
41897 // GIR_Coverage, 395,
41898 GIR_EraseRootFromParent_Done,
41899 // Label 2488: @118788
41900 GIM_Try, /*On fail goto*//*Label 2489*/ GIMT_Encode4(118824), // Rule ID 396 //
41901 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41902 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
41903 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41904 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41905 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41906 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
41907 // (intrinsic_wo_chain:{ *:[i32] } 572:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
41908 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUWDr),
41909 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41910 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41911 GIR_RootConstrainSelectedInstOperands,
41912 // GIR_Coverage, 396,
41913 GIR_EraseRootFromParent_Done,
41914 // Label 2489: @118824
41915 GIM_Try, /*On fail goto*//*Label 2490*/ GIMT_Encode4(118860), // Rule ID 397 //
41916 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41917 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
41918 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41919 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41920 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41921 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
41922 // (intrinsic_wo_chain:{ *:[i64] } 572:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
41923 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUXDr),
41924 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41925 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41926 GIR_RootConstrainSelectedInstOperands,
41927 // GIR_Coverage, 397,
41928 GIR_EraseRootFromParent_Done,
41929 // Label 2490: @118860
41930 GIM_Try, /*On fail goto*//*Label 2491*/ GIMT_Encode4(118896), // Rule ID 398 //
41931 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41932 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
41933 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41934 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41935 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41936 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
41937 // (intrinsic_wo_chain:{ *:[i32] } 573:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
41938 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUWHr),
41939 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41940 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41941 GIR_RootConstrainSelectedInstOperands,
41942 // GIR_Coverage, 398,
41943 GIR_EraseRootFromParent_Done,
41944 // Label 2491: @118896
41945 GIM_Try, /*On fail goto*//*Label 2492*/ GIMT_Encode4(118932), // Rule ID 399 //
41946 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41947 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
41948 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41949 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41950 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41951 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
41952 // (intrinsic_wo_chain:{ *:[i64] } 573:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FCVTPUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
41953 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUXHr),
41954 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41955 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41956 GIR_RootConstrainSelectedInstOperands,
41957 // GIR_Coverage, 399,
41958 GIR_EraseRootFromParent_Done,
41959 // Label 2492: @118932
41960 GIM_Try, /*On fail goto*//*Label 2493*/ GIMT_Encode4(118968), // Rule ID 400 //
41961 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41962 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
41963 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41964 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41965 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41966 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
41967 // (intrinsic_wo_chain:{ *:[i32] } 573:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
41968 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUWSr),
41969 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41970 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41971 GIR_RootConstrainSelectedInstOperands,
41972 // GIR_Coverage, 400,
41973 GIR_EraseRootFromParent_Done,
41974 // Label 2493: @118968
41975 GIM_Try, /*On fail goto*//*Label 2494*/ GIMT_Encode4(119004), // Rule ID 401 //
41976 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41977 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
41978 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
41979 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41980 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
41981 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
41982 // (intrinsic_wo_chain:{ *:[i64] } 573:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FCVTPUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
41983 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUXSr),
41984 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
41985 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
41986 GIR_RootConstrainSelectedInstOperands,
41987 // GIR_Coverage, 401,
41988 GIR_EraseRootFromParent_Done,
41989 // Label 2494: @119004
41990 GIM_Try, /*On fail goto*//*Label 2495*/ GIMT_Encode4(119040), // Rule ID 402 //
41991 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
41992 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
41993 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
41994 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41995 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
41996 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
41997 // (intrinsic_wo_chain:{ *:[i32] } 573:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
41998 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUWDr),
41999 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42000 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42001 GIR_RootConstrainSelectedInstOperands,
42002 // GIR_Coverage, 402,
42003 GIR_EraseRootFromParent_Done,
42004 // Label 2495: @119040
42005 GIM_Try, /*On fail goto*//*Label 2496*/ GIMT_Encode4(119076), // Rule ID 403 //
42006 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
42007 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
42008 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
42009 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
42010 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
42011 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42012 // (intrinsic_wo_chain:{ *:[i64] } 573:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTPUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
42013 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUXDr),
42014 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42015 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42016 GIR_RootConstrainSelectedInstOperands,
42017 // GIR_Coverage, 403,
42018 GIR_EraseRootFromParent_Done,
42019 // Label 2496: @119076
42020 GIM_Try, /*On fail goto*//*Label 2497*/ GIMT_Encode4(119112), // Rule ID 569 //
42021 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
42022 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint32z),
42023 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
42024 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
42025 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
42026 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
42027 // (intrinsic_wo_chain:{ *:[f32] } 530:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRINT32ZSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
42028 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32ZSr),
42029 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42030 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42031 GIR_RootConstrainSelectedInstOperands,
42032 // GIR_Coverage, 569,
42033 GIR_EraseRootFromParent_Done,
42034 // Label 2497: @119112
42035 GIM_Try, /*On fail goto*//*Label 2498*/ GIMT_Encode4(119148), // Rule ID 570 //
42036 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
42037 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint32z),
42038 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
42039 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
42040 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42041 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42042 // (intrinsic_wo_chain:{ *:[f64] } 530:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRINT32ZDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
42043 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32ZDr),
42044 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42045 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42046 GIR_RootConstrainSelectedInstOperands,
42047 // GIR_Coverage, 570,
42048 GIR_EraseRootFromParent_Done,
42049 // Label 2498: @119148
42050 GIM_Try, /*On fail goto*//*Label 2499*/ GIMT_Encode4(119184), // Rule ID 571 //
42051 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
42052 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint64z),
42053 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
42054 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
42055 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
42056 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
42057 // (intrinsic_wo_chain:{ *:[f32] } 532:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRINT64ZSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
42058 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64ZSr),
42059 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42060 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42061 GIR_RootConstrainSelectedInstOperands,
42062 // GIR_Coverage, 571,
42063 GIR_EraseRootFromParent_Done,
42064 // Label 2499: @119184
42065 GIM_Try, /*On fail goto*//*Label 2500*/ GIMT_Encode4(119220), // Rule ID 572 //
42066 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
42067 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint64z),
42068 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
42069 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
42070 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42071 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42072 // (intrinsic_wo_chain:{ *:[f64] } 532:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRINT64ZDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
42073 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64ZDr),
42074 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42075 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42076 GIR_RootConstrainSelectedInstOperands,
42077 // GIR_Coverage, 572,
42078 GIR_EraseRootFromParent_Done,
42079 // Label 2500: @119220
42080 GIM_Try, /*On fail goto*//*Label 2501*/ GIMT_Encode4(119256), // Rule ID 573 //
42081 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
42082 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint32x),
42083 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
42084 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
42085 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
42086 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
42087 // (intrinsic_wo_chain:{ *:[f32] } 529:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRINT32XSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
42088 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32XSr),
42089 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42090 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42091 GIR_RootConstrainSelectedInstOperands,
42092 // GIR_Coverage, 573,
42093 GIR_EraseRootFromParent_Done,
42094 // Label 2501: @119256
42095 GIM_Try, /*On fail goto*//*Label 2502*/ GIMT_Encode4(119292), // Rule ID 574 //
42096 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
42097 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint32x),
42098 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
42099 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
42100 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42101 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42102 // (intrinsic_wo_chain:{ *:[f64] } 529:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRINT32XDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
42103 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32XDr),
42104 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42105 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42106 GIR_RootConstrainSelectedInstOperands,
42107 // GIR_Coverage, 574,
42108 GIR_EraseRootFromParent_Done,
42109 // Label 2502: @119292
42110 GIM_Try, /*On fail goto*//*Label 2503*/ GIMT_Encode4(119328), // Rule ID 575 //
42111 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
42112 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint64x),
42113 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
42114 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
42115 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
42116 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
42117 // (intrinsic_wo_chain:{ *:[f32] } 531:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRINT64XSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
42118 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64XSr),
42119 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42120 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42121 GIR_RootConstrainSelectedInstOperands,
42122 // GIR_Coverage, 575,
42123 GIR_EraseRootFromParent_Done,
42124 // Label 2503: @119328
42125 GIM_Try, /*On fail goto*//*Label 2504*/ GIMT_Encode4(119364), // Rule ID 576 //
42126 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
42127 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint64x),
42128 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
42129 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
42130 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42131 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42132 // (intrinsic_wo_chain:{ *:[f64] } 531:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRINT64XDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
42133 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64XDr),
42134 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42135 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42136 GIR_RootConstrainSelectedInstOperands,
42137 // GIR_Coverage, 576,
42138 GIR_EraseRootFromParent_Done,
42139 // Label 2504: @119364
42140 GIM_Try, /*On fail goto*//*Label 2505*/ GIMT_Encode4(119400), // Rule ID 704 //
42141 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42142 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_cls),
42143 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
42144 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
42145 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42146 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42147 // (intrinsic_wo_chain:{ *:[v8i8] } 560:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (CLSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
42148 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSv8i8),
42149 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42150 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42151 GIR_RootConstrainSelectedInstOperands,
42152 // GIR_Coverage, 704,
42153 GIR_EraseRootFromParent_Done,
42154 // Label 2505: @119400
42155 GIM_Try, /*On fail goto*//*Label 2506*/ GIMT_Encode4(119436), // Rule ID 705 //
42156 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42157 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_cls),
42158 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
42159 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
42160 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42161 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42162 // (intrinsic_wo_chain:{ *:[v16i8] } 560:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (CLSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
42163 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSv16i8),
42164 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42165 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42166 GIR_RootConstrainSelectedInstOperands,
42167 // GIR_Coverage, 705,
42168 GIR_EraseRootFromParent_Done,
42169 // Label 2506: @119436
42170 GIM_Try, /*On fail goto*//*Label 2507*/ GIMT_Encode4(119472), // Rule ID 706 //
42171 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42172 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_cls),
42173 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
42174 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
42175 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42176 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42177 // (intrinsic_wo_chain:{ *:[v4i16] } 560:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (CLSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
42178 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSv4i16),
42179 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42180 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42181 GIR_RootConstrainSelectedInstOperands,
42182 // GIR_Coverage, 706,
42183 GIR_EraseRootFromParent_Done,
42184 // Label 2507: @119472
42185 GIM_Try, /*On fail goto*//*Label 2508*/ GIMT_Encode4(119508), // Rule ID 707 //
42186 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42187 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_cls),
42188 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
42189 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
42190 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42191 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42192 // (intrinsic_wo_chain:{ *:[v8i16] } 560:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (CLSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
42193 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSv8i16),
42194 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42195 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42196 GIR_RootConstrainSelectedInstOperands,
42197 // GIR_Coverage, 707,
42198 GIR_EraseRootFromParent_Done,
42199 // Label 2508: @119508
42200 GIM_Try, /*On fail goto*//*Label 2509*/ GIMT_Encode4(119544), // Rule ID 708 //
42201 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42202 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_cls),
42203 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
42204 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
42205 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42206 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42207 // (intrinsic_wo_chain:{ *:[v2i32] } 560:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (CLSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
42208 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSv2i32),
42209 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42210 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42211 GIR_RootConstrainSelectedInstOperands,
42212 // GIR_Coverage, 708,
42213 GIR_EraseRootFromParent_Done,
42214 // Label 2509: @119544
42215 GIM_Try, /*On fail goto*//*Label 2510*/ GIMT_Encode4(119580), // Rule ID 709 //
42216 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42217 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_cls),
42218 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
42219 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
42220 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42221 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42222 // (intrinsic_wo_chain:{ *:[v4i32] } 560:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (CLSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
42223 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSv4i32),
42224 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42225 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42226 GIR_RootConstrainSelectedInstOperands,
42227 // GIR_Coverage, 709,
42228 GIR_EraseRootFromParent_Done,
42229 // Label 2510: @119580
42230 GIM_Try, /*On fail goto*//*Label 2511*/ GIMT_Encode4(119616), // Rule ID 783 //
42231 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42232 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
42233 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
42234 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
42235 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42236 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42237 // (intrinsic_wo_chain:{ *:[v4i16] } 566:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTASv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
42238 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv4f16),
42239 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42240 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42241 GIR_RootConstrainSelectedInstOperands,
42242 // GIR_Coverage, 783,
42243 GIR_EraseRootFromParent_Done,
42244 // Label 2511: @119616
42245 GIM_Try, /*On fail goto*//*Label 2512*/ GIMT_Encode4(119652), // Rule ID 784 //
42246 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42247 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
42248 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
42249 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
42250 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42251 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42252 // (intrinsic_wo_chain:{ *:[v8i16] } 566:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTASv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
42253 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv8f16),
42254 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42255 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42256 GIR_RootConstrainSelectedInstOperands,
42257 // GIR_Coverage, 784,
42258 GIR_EraseRootFromParent_Done,
42259 // Label 2512: @119652
42260 GIM_Try, /*On fail goto*//*Label 2513*/ GIMT_Encode4(119688), // Rule ID 785 //
42261 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42262 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
42263 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
42264 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
42265 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42266 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42267 // (intrinsic_wo_chain:{ *:[v2i32] } 566:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTASv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
42268 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv2f32),
42269 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42270 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42271 GIR_RootConstrainSelectedInstOperands,
42272 // GIR_Coverage, 785,
42273 GIR_EraseRootFromParent_Done,
42274 // Label 2513: @119688
42275 GIM_Try, /*On fail goto*//*Label 2514*/ GIMT_Encode4(119724), // Rule ID 786 //
42276 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42277 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
42278 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
42279 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
42280 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42281 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42282 // (intrinsic_wo_chain:{ *:[v4i32] } 566:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTASv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
42283 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv4f32),
42284 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42285 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42286 GIR_RootConstrainSelectedInstOperands,
42287 // GIR_Coverage, 786,
42288 GIR_EraseRootFromParent_Done,
42289 // Label 2514: @119724
42290 GIM_Try, /*On fail goto*//*Label 2515*/ GIMT_Encode4(119760), // Rule ID 787 //
42291 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42292 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
42293 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
42294 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
42295 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42296 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42297 // (intrinsic_wo_chain:{ *:[v2i64] } 566:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTASv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
42298 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv2f64),
42299 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42300 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42301 GIR_RootConstrainSelectedInstOperands,
42302 // GIR_Coverage, 787,
42303 GIR_EraseRootFromParent_Done,
42304 // Label 2515: @119760
42305 GIM_Try, /*On fail goto*//*Label 2516*/ GIMT_Encode4(119796), // Rule ID 788 //
42306 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42307 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
42308 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
42309 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
42310 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42311 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42312 // (intrinsic_wo_chain:{ *:[v4i16] } 567:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTAUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
42313 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv4f16),
42314 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42315 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42316 GIR_RootConstrainSelectedInstOperands,
42317 // GIR_Coverage, 788,
42318 GIR_EraseRootFromParent_Done,
42319 // Label 2516: @119796
42320 GIM_Try, /*On fail goto*//*Label 2517*/ GIMT_Encode4(119832), // Rule ID 789 //
42321 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42322 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
42323 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
42324 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
42325 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42326 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42327 // (intrinsic_wo_chain:{ *:[v8i16] } 567:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTAUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
42328 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv8f16),
42329 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42330 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42331 GIR_RootConstrainSelectedInstOperands,
42332 // GIR_Coverage, 789,
42333 GIR_EraseRootFromParent_Done,
42334 // Label 2517: @119832
42335 GIM_Try, /*On fail goto*//*Label 2518*/ GIMT_Encode4(119868), // Rule ID 790 //
42336 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42337 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
42338 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
42339 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
42340 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42341 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42342 // (intrinsic_wo_chain:{ *:[v2i32] } 567:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTAUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
42343 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv2f32),
42344 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42345 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42346 GIR_RootConstrainSelectedInstOperands,
42347 // GIR_Coverage, 790,
42348 GIR_EraseRootFromParent_Done,
42349 // Label 2518: @119868
42350 GIM_Try, /*On fail goto*//*Label 2519*/ GIMT_Encode4(119904), // Rule ID 791 //
42351 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42352 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
42353 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
42354 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
42355 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42356 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42357 // (intrinsic_wo_chain:{ *:[v4i32] } 567:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTAUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
42358 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv4f32),
42359 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42360 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42361 GIR_RootConstrainSelectedInstOperands,
42362 // GIR_Coverage, 791,
42363 GIR_EraseRootFromParent_Done,
42364 // Label 2519: @119904
42365 GIM_Try, /*On fail goto*//*Label 2520*/ GIMT_Encode4(119940), // Rule ID 792 //
42366 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42367 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
42368 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
42369 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
42370 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42371 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42372 // (intrinsic_wo_chain:{ *:[v2i64] } 567:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTAUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
42373 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv2f64),
42374 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42375 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42376 GIR_RootConstrainSelectedInstOperands,
42377 // GIR_Coverage, 792,
42378 GIR_EraseRootFromParent_Done,
42379 // Label 2520: @119940
42380 GIM_Try, /*On fail goto*//*Label 2521*/ GIMT_Encode4(119976), // Rule ID 793 //
42381 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42382 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
42383 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
42384 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
42385 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42386 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42387 // (intrinsic_wo_chain:{ *:[v4i16] } 568:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTMSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
42388 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv4f16),
42389 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42390 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42391 GIR_RootConstrainSelectedInstOperands,
42392 // GIR_Coverage, 793,
42393 GIR_EraseRootFromParent_Done,
42394 // Label 2521: @119976
42395 GIM_Try, /*On fail goto*//*Label 2522*/ GIMT_Encode4(120012), // Rule ID 794 //
42396 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42397 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
42398 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
42399 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
42400 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42401 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42402 // (intrinsic_wo_chain:{ *:[v8i16] } 568:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTMSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
42403 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv8f16),
42404 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42405 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42406 GIR_RootConstrainSelectedInstOperands,
42407 // GIR_Coverage, 794,
42408 GIR_EraseRootFromParent_Done,
42409 // Label 2522: @120012
42410 GIM_Try, /*On fail goto*//*Label 2523*/ GIMT_Encode4(120048), // Rule ID 795 //
42411 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42412 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
42413 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
42414 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
42415 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42416 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42417 // (intrinsic_wo_chain:{ *:[v2i32] } 568:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTMSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
42418 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv2f32),
42419 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42420 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42421 GIR_RootConstrainSelectedInstOperands,
42422 // GIR_Coverage, 795,
42423 GIR_EraseRootFromParent_Done,
42424 // Label 2523: @120048
42425 GIM_Try, /*On fail goto*//*Label 2524*/ GIMT_Encode4(120084), // Rule ID 796 //
42426 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42427 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
42428 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
42429 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
42430 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42431 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42432 // (intrinsic_wo_chain:{ *:[v4i32] } 568:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTMSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
42433 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv4f32),
42434 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42435 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42436 GIR_RootConstrainSelectedInstOperands,
42437 // GIR_Coverage, 796,
42438 GIR_EraseRootFromParent_Done,
42439 // Label 2524: @120084
42440 GIM_Try, /*On fail goto*//*Label 2525*/ GIMT_Encode4(120120), // Rule ID 797 //
42441 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42442 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
42443 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
42444 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
42445 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42446 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42447 // (intrinsic_wo_chain:{ *:[v2i64] } 568:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTMSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
42448 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv2f64),
42449 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42450 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42451 GIR_RootConstrainSelectedInstOperands,
42452 // GIR_Coverage, 797,
42453 GIR_EraseRootFromParent_Done,
42454 // Label 2525: @120120
42455 GIM_Try, /*On fail goto*//*Label 2526*/ GIMT_Encode4(120156), // Rule ID 798 //
42456 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42457 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
42458 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
42459 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
42460 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42461 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42462 // (intrinsic_wo_chain:{ *:[v4i16] } 569:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTMUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
42463 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv4f16),
42464 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42465 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42466 GIR_RootConstrainSelectedInstOperands,
42467 // GIR_Coverage, 798,
42468 GIR_EraseRootFromParent_Done,
42469 // Label 2526: @120156
42470 GIM_Try, /*On fail goto*//*Label 2527*/ GIMT_Encode4(120192), // Rule ID 799 //
42471 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42472 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
42473 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
42474 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
42475 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42476 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42477 // (intrinsic_wo_chain:{ *:[v8i16] } 569:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTMUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
42478 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv8f16),
42479 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42480 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42481 GIR_RootConstrainSelectedInstOperands,
42482 // GIR_Coverage, 799,
42483 GIR_EraseRootFromParent_Done,
42484 // Label 2527: @120192
42485 GIM_Try, /*On fail goto*//*Label 2528*/ GIMT_Encode4(120228), // Rule ID 800 //
42486 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42487 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
42488 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
42489 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
42490 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42491 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42492 // (intrinsic_wo_chain:{ *:[v2i32] } 569:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTMUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
42493 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv2f32),
42494 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42495 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42496 GIR_RootConstrainSelectedInstOperands,
42497 // GIR_Coverage, 800,
42498 GIR_EraseRootFromParent_Done,
42499 // Label 2528: @120228
42500 GIM_Try, /*On fail goto*//*Label 2529*/ GIMT_Encode4(120264), // Rule ID 801 //
42501 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42502 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
42503 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
42504 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
42505 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42506 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42507 // (intrinsic_wo_chain:{ *:[v4i32] } 569:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTMUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
42508 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv4f32),
42509 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42510 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42511 GIR_RootConstrainSelectedInstOperands,
42512 // GIR_Coverage, 801,
42513 GIR_EraseRootFromParent_Done,
42514 // Label 2529: @120264
42515 GIM_Try, /*On fail goto*//*Label 2530*/ GIMT_Encode4(120300), // Rule ID 802 //
42516 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42517 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
42518 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
42519 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
42520 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42521 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42522 // (intrinsic_wo_chain:{ *:[v2i64] } 569:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTMUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
42523 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv2f64),
42524 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42525 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42526 GIR_RootConstrainSelectedInstOperands,
42527 // GIR_Coverage, 802,
42528 GIR_EraseRootFromParent_Done,
42529 // Label 2530: @120300
42530 GIM_Try, /*On fail goto*//*Label 2531*/ GIMT_Encode4(120336), // Rule ID 803 //
42531 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42532 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
42533 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
42534 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
42535 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42536 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42537 // (intrinsic_wo_chain:{ *:[v4i16] } 570:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTNSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
42538 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv4f16),
42539 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42540 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42541 GIR_RootConstrainSelectedInstOperands,
42542 // GIR_Coverage, 803,
42543 GIR_EraseRootFromParent_Done,
42544 // Label 2531: @120336
42545 GIM_Try, /*On fail goto*//*Label 2532*/ GIMT_Encode4(120372), // Rule ID 804 //
42546 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42547 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
42548 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
42549 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
42550 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42551 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42552 // (intrinsic_wo_chain:{ *:[v8i16] } 570:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTNSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
42553 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv8f16),
42554 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42555 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42556 GIR_RootConstrainSelectedInstOperands,
42557 // GIR_Coverage, 804,
42558 GIR_EraseRootFromParent_Done,
42559 // Label 2532: @120372
42560 GIM_Try, /*On fail goto*//*Label 2533*/ GIMT_Encode4(120408), // Rule ID 805 //
42561 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42562 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
42563 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
42564 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
42565 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42566 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42567 // (intrinsic_wo_chain:{ *:[v2i32] } 570:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTNSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
42568 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv2f32),
42569 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42570 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42571 GIR_RootConstrainSelectedInstOperands,
42572 // GIR_Coverage, 805,
42573 GIR_EraseRootFromParent_Done,
42574 // Label 2533: @120408
42575 GIM_Try, /*On fail goto*//*Label 2534*/ GIMT_Encode4(120444), // Rule ID 806 //
42576 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42577 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
42578 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
42579 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
42580 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42581 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42582 // (intrinsic_wo_chain:{ *:[v4i32] } 570:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTNSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
42583 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv4f32),
42584 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42585 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42586 GIR_RootConstrainSelectedInstOperands,
42587 // GIR_Coverage, 806,
42588 GIR_EraseRootFromParent_Done,
42589 // Label 2534: @120444
42590 GIM_Try, /*On fail goto*//*Label 2535*/ GIMT_Encode4(120480), // Rule ID 807 //
42591 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42592 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
42593 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
42594 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
42595 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42596 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42597 // (intrinsic_wo_chain:{ *:[v2i64] } 570:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTNSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
42598 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv2f64),
42599 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42600 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42601 GIR_RootConstrainSelectedInstOperands,
42602 // GIR_Coverage, 807,
42603 GIR_EraseRootFromParent_Done,
42604 // Label 2535: @120480
42605 GIM_Try, /*On fail goto*//*Label 2536*/ GIMT_Encode4(120516), // Rule ID 808 //
42606 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42607 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
42608 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
42609 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
42610 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42611 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42612 // (intrinsic_wo_chain:{ *:[v4i16] } 571:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTNUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
42613 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv4f16),
42614 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42615 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42616 GIR_RootConstrainSelectedInstOperands,
42617 // GIR_Coverage, 808,
42618 GIR_EraseRootFromParent_Done,
42619 // Label 2536: @120516
42620 GIM_Try, /*On fail goto*//*Label 2537*/ GIMT_Encode4(120552), // Rule ID 809 //
42621 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42622 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
42623 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
42624 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
42625 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42626 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42627 // (intrinsic_wo_chain:{ *:[v8i16] } 571:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTNUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
42628 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv8f16),
42629 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42630 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42631 GIR_RootConstrainSelectedInstOperands,
42632 // GIR_Coverage, 809,
42633 GIR_EraseRootFromParent_Done,
42634 // Label 2537: @120552
42635 GIM_Try, /*On fail goto*//*Label 2538*/ GIMT_Encode4(120588), // Rule ID 810 //
42636 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42637 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
42638 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
42639 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
42640 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42641 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42642 // (intrinsic_wo_chain:{ *:[v2i32] } 571:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTNUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
42643 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv2f32),
42644 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42645 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42646 GIR_RootConstrainSelectedInstOperands,
42647 // GIR_Coverage, 810,
42648 GIR_EraseRootFromParent_Done,
42649 // Label 2538: @120588
42650 GIM_Try, /*On fail goto*//*Label 2539*/ GIMT_Encode4(120624), // Rule ID 811 //
42651 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42652 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
42653 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
42654 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
42655 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42656 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42657 // (intrinsic_wo_chain:{ *:[v4i32] } 571:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTNUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
42658 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv4f32),
42659 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42660 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42661 GIR_RootConstrainSelectedInstOperands,
42662 // GIR_Coverage, 811,
42663 GIR_EraseRootFromParent_Done,
42664 // Label 2539: @120624
42665 GIM_Try, /*On fail goto*//*Label 2540*/ GIMT_Encode4(120660), // Rule ID 812 //
42666 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42667 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
42668 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
42669 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
42670 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42671 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42672 // (intrinsic_wo_chain:{ *:[v2i64] } 571:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTNUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
42673 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv2f64),
42674 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42675 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42676 GIR_RootConstrainSelectedInstOperands,
42677 // GIR_Coverage, 812,
42678 GIR_EraseRootFromParent_Done,
42679 // Label 2540: @120660
42680 GIM_Try, /*On fail goto*//*Label 2541*/ GIMT_Encode4(120696), // Rule ID 813 //
42681 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42682 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
42683 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
42684 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
42685 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42686 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42687 // (intrinsic_wo_chain:{ *:[v4i16] } 572:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTPSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
42688 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv4f16),
42689 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42690 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42691 GIR_RootConstrainSelectedInstOperands,
42692 // GIR_Coverage, 813,
42693 GIR_EraseRootFromParent_Done,
42694 // Label 2541: @120696
42695 GIM_Try, /*On fail goto*//*Label 2542*/ GIMT_Encode4(120732), // Rule ID 814 //
42696 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42697 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
42698 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
42699 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
42700 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42701 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42702 // (intrinsic_wo_chain:{ *:[v8i16] } 572:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTPSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
42703 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv8f16),
42704 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42705 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42706 GIR_RootConstrainSelectedInstOperands,
42707 // GIR_Coverage, 814,
42708 GIR_EraseRootFromParent_Done,
42709 // Label 2542: @120732
42710 GIM_Try, /*On fail goto*//*Label 2543*/ GIMT_Encode4(120768), // Rule ID 815 //
42711 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42712 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
42713 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
42714 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
42715 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42716 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42717 // (intrinsic_wo_chain:{ *:[v2i32] } 572:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTPSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
42718 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv2f32),
42719 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42720 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42721 GIR_RootConstrainSelectedInstOperands,
42722 // GIR_Coverage, 815,
42723 GIR_EraseRootFromParent_Done,
42724 // Label 2543: @120768
42725 GIM_Try, /*On fail goto*//*Label 2544*/ GIMT_Encode4(120804), // Rule ID 816 //
42726 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42727 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
42728 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
42729 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
42730 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42731 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42732 // (intrinsic_wo_chain:{ *:[v4i32] } 572:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTPSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
42733 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv4f32),
42734 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42735 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42736 GIR_RootConstrainSelectedInstOperands,
42737 // GIR_Coverage, 816,
42738 GIR_EraseRootFromParent_Done,
42739 // Label 2544: @120804
42740 GIM_Try, /*On fail goto*//*Label 2545*/ GIMT_Encode4(120840), // Rule ID 817 //
42741 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42742 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
42743 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
42744 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
42745 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42746 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42747 // (intrinsic_wo_chain:{ *:[v2i64] } 572:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTPSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
42748 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv2f64),
42749 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42750 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42751 GIR_RootConstrainSelectedInstOperands,
42752 // GIR_Coverage, 817,
42753 GIR_EraseRootFromParent_Done,
42754 // Label 2545: @120840
42755 GIM_Try, /*On fail goto*//*Label 2546*/ GIMT_Encode4(120876), // Rule ID 818 //
42756 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42757 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
42758 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
42759 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
42760 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42761 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42762 // (intrinsic_wo_chain:{ *:[v4i16] } 573:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FCVTPUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
42763 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv4f16),
42764 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42765 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42766 GIR_RootConstrainSelectedInstOperands,
42767 // GIR_Coverage, 818,
42768 GIR_EraseRootFromParent_Done,
42769 // Label 2546: @120876
42770 GIM_Try, /*On fail goto*//*Label 2547*/ GIMT_Encode4(120912), // Rule ID 819 //
42771 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42772 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
42773 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
42774 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
42775 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42776 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42777 // (intrinsic_wo_chain:{ *:[v8i16] } 573:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FCVTPUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
42778 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv8f16),
42779 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42780 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42781 GIR_RootConstrainSelectedInstOperands,
42782 // GIR_Coverage, 819,
42783 GIR_EraseRootFromParent_Done,
42784 // Label 2547: @120912
42785 GIM_Try, /*On fail goto*//*Label 2548*/ GIMT_Encode4(120948), // Rule ID 820 //
42786 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42787 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
42788 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
42789 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
42790 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42791 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42792 // (intrinsic_wo_chain:{ *:[v2i32] } 573:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FCVTPUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
42793 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv2f32),
42794 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42795 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42796 GIR_RootConstrainSelectedInstOperands,
42797 // GIR_Coverage, 820,
42798 GIR_EraseRootFromParent_Done,
42799 // Label 2548: @120948
42800 GIM_Try, /*On fail goto*//*Label 2549*/ GIMT_Encode4(120984), // Rule ID 821 //
42801 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42802 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
42803 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
42804 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
42805 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42806 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42807 // (intrinsic_wo_chain:{ *:[v4i32] } 573:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTPUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
42808 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv4f32),
42809 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42810 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42811 GIR_RootConstrainSelectedInstOperands,
42812 // GIR_Coverage, 821,
42813 GIR_EraseRootFromParent_Done,
42814 // Label 2549: @120984
42815 GIM_Try, /*On fail goto*//*Label 2550*/ GIMT_Encode4(121020), // Rule ID 822 //
42816 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42817 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
42818 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
42819 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
42820 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42821 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42822 // (intrinsic_wo_chain:{ *:[v2i64] } 573:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTPUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
42823 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv2f64),
42824 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42825 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42826 GIR_RootConstrainSelectedInstOperands,
42827 // GIR_Coverage, 822,
42828 GIR_EraseRootFromParent_Done,
42829 // Label 2550: @121020
42830 GIM_Try, /*On fail goto*//*Label 2551*/ GIMT_Encode4(121056), // Rule ID 823 //
42831 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42832 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtxn),
42833 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
42834 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
42835 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42836 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42837 // (intrinsic_wo_chain:{ *:[v2f32] } 574:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FCVTXNv2f32:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn)
42838 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTXNv2f32),
42839 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42840 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42841 GIR_RootConstrainSelectedInstOperands,
42842 // GIR_Coverage, 823,
42843 GIR_EraseRootFromParent_Done,
42844 // Label 2551: @121056
42845 GIM_Try, /*On fail goto*//*Label 2552*/ GIMT_Encode4(121092), // Rule ID 850 //
42846 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42847 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
42848 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
42849 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
42850 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42851 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42852 // (intrinsic_wo_chain:{ *:[v4f16] } 594:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FRECPEv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
42853 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv4f16),
42854 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42855 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42856 GIR_RootConstrainSelectedInstOperands,
42857 // GIR_Coverage, 850,
42858 GIR_EraseRootFromParent_Done,
42859 // Label 2552: @121092
42860 GIM_Try, /*On fail goto*//*Label 2553*/ GIMT_Encode4(121128), // Rule ID 851 //
42861 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42862 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
42863 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
42864 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
42865 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42866 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42867 // (intrinsic_wo_chain:{ *:[v8f16] } 594:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FRECPEv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
42868 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv8f16),
42869 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42870 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42871 GIR_RootConstrainSelectedInstOperands,
42872 // GIR_Coverage, 851,
42873 GIR_EraseRootFromParent_Done,
42874 // Label 2553: @121128
42875 GIM_Try, /*On fail goto*//*Label 2554*/ GIMT_Encode4(121164), // Rule ID 852 //
42876 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42877 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
42878 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
42879 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
42880 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42881 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42882 // (intrinsic_wo_chain:{ *:[v2f32] } 594:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRECPEv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
42883 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv2f32),
42884 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42885 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42886 GIR_RootConstrainSelectedInstOperands,
42887 // GIR_Coverage, 852,
42888 GIR_EraseRootFromParent_Done,
42889 // Label 2554: @121164
42890 GIM_Try, /*On fail goto*//*Label 2555*/ GIMT_Encode4(121200), // Rule ID 853 //
42891 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42892 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
42893 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
42894 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
42895 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42896 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42897 // (intrinsic_wo_chain:{ *:[v4f32] } 594:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRECPEv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
42898 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv4f32),
42899 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42900 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42901 GIR_RootConstrainSelectedInstOperands,
42902 // GIR_Coverage, 853,
42903 GIR_EraseRootFromParent_Done,
42904 // Label 2555: @121200
42905 GIM_Try, /*On fail goto*//*Label 2556*/ GIMT_Encode4(121236), // Rule ID 854 //
42906 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42907 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
42908 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
42909 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
42910 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42911 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42912 // (intrinsic_wo_chain:{ *:[v2f64] } 594:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRECPEv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
42913 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv2f64),
42914 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42915 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42916 GIR_RootConstrainSelectedInstOperands,
42917 // GIR_Coverage, 854,
42918 GIR_EraseRootFromParent_Done,
42919 // Label 2556: @121236
42920 GIM_Try, /*On fail goto*//*Label 2557*/ GIMT_Encode4(121272), // Rule ID 925 //
42921 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
42922 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32z),
42923 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
42924 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
42925 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42926 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42927 // (intrinsic_wo_chain:{ *:[v2f32] } 598:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRINT32Zv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
42928 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32Zv2f32),
42929 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42930 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42931 GIR_RootConstrainSelectedInstOperands,
42932 // GIR_Coverage, 925,
42933 GIR_EraseRootFromParent_Done,
42934 // Label 2557: @121272
42935 GIM_Try, /*On fail goto*//*Label 2558*/ GIMT_Encode4(121308), // Rule ID 926 //
42936 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
42937 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32z),
42938 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
42939 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
42940 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42941 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42942 // (intrinsic_wo_chain:{ *:[v4f32] } 598:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRINT32Zv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
42943 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32Zv4f32),
42944 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42945 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42946 GIR_RootConstrainSelectedInstOperands,
42947 // GIR_Coverage, 926,
42948 GIR_EraseRootFromParent_Done,
42949 // Label 2558: @121308
42950 GIM_Try, /*On fail goto*//*Label 2559*/ GIMT_Encode4(121344), // Rule ID 927 //
42951 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
42952 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32z),
42953 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
42954 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
42955 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42956 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42957 // (intrinsic_wo_chain:{ *:[v2f64] } 598:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRINT32Zv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
42958 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32Zv2f64),
42959 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42960 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42961 GIR_RootConstrainSelectedInstOperands,
42962 // GIR_Coverage, 927,
42963 GIR_EraseRootFromParent_Done,
42964 // Label 2559: @121344
42965 GIM_Try, /*On fail goto*//*Label 2560*/ GIMT_Encode4(121380), // Rule ID 928 //
42966 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
42967 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64z),
42968 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
42969 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
42970 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42971 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
42972 // (intrinsic_wo_chain:{ *:[v2f32] } 600:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRINT64Zv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
42973 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64Zv2f32),
42974 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42975 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42976 GIR_RootConstrainSelectedInstOperands,
42977 // GIR_Coverage, 928,
42978 GIR_EraseRootFromParent_Done,
42979 // Label 2560: @121380
42980 GIM_Try, /*On fail goto*//*Label 2561*/ GIMT_Encode4(121416), // Rule ID 929 //
42981 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
42982 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64z),
42983 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
42984 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
42985 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42986 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
42987 // (intrinsic_wo_chain:{ *:[v4f32] } 600:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRINT64Zv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
42988 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64Zv4f32),
42989 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
42990 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
42991 GIR_RootConstrainSelectedInstOperands,
42992 // GIR_Coverage, 929,
42993 GIR_EraseRootFromParent_Done,
42994 // Label 2561: @121416
42995 GIM_Try, /*On fail goto*//*Label 2562*/ GIMT_Encode4(121452), // Rule ID 930 //
42996 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
42997 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64z),
42998 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
42999 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
43000 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43001 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43002 // (intrinsic_wo_chain:{ *:[v2f64] } 600:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRINT64Zv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
43003 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64Zv2f64),
43004 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43005 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43006 GIR_RootConstrainSelectedInstOperands,
43007 // GIR_Coverage, 930,
43008 GIR_EraseRootFromParent_Done,
43009 // Label 2562: @121452
43010 GIM_Try, /*On fail goto*//*Label 2563*/ GIMT_Encode4(121488), // Rule ID 931 //
43011 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
43012 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32x),
43013 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
43014 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
43015 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43016 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43017 // (intrinsic_wo_chain:{ *:[v2f32] } 597:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRINT32Xv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
43018 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32Xv2f32),
43019 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43020 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43021 GIR_RootConstrainSelectedInstOperands,
43022 // GIR_Coverage, 931,
43023 GIR_EraseRootFromParent_Done,
43024 // Label 2563: @121488
43025 GIM_Try, /*On fail goto*//*Label 2564*/ GIMT_Encode4(121524), // Rule ID 932 //
43026 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
43027 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32x),
43028 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
43029 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43030 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43031 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43032 // (intrinsic_wo_chain:{ *:[v4f32] } 597:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRINT32Xv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
43033 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32Xv4f32),
43034 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43035 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43036 GIR_RootConstrainSelectedInstOperands,
43037 // GIR_Coverage, 932,
43038 GIR_EraseRootFromParent_Done,
43039 // Label 2564: @121524
43040 GIM_Try, /*On fail goto*//*Label 2565*/ GIMT_Encode4(121560), // Rule ID 933 //
43041 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
43042 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32x),
43043 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
43044 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
43045 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43046 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43047 // (intrinsic_wo_chain:{ *:[v2f64] } 597:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRINT32Xv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
43048 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32Xv2f64),
43049 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43050 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43051 GIR_RootConstrainSelectedInstOperands,
43052 // GIR_Coverage, 933,
43053 GIR_EraseRootFromParent_Done,
43054 // Label 2565: @121560
43055 GIM_Try, /*On fail goto*//*Label 2566*/ GIMT_Encode4(121596), // Rule ID 934 //
43056 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
43057 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64x),
43058 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
43059 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
43060 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43061 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43062 // (intrinsic_wo_chain:{ *:[v2f32] } 599:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRINT64Xv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
43063 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64Xv2f32),
43064 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43065 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43066 GIR_RootConstrainSelectedInstOperands,
43067 // GIR_Coverage, 934,
43068 GIR_EraseRootFromParent_Done,
43069 // Label 2566: @121596
43070 GIM_Try, /*On fail goto*//*Label 2567*/ GIMT_Encode4(121632), // Rule ID 935 //
43071 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
43072 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64x),
43073 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
43074 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43075 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43076 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43077 // (intrinsic_wo_chain:{ *:[v4f32] } 599:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRINT64Xv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
43078 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64Xv4f32),
43079 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43080 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43081 GIR_RootConstrainSelectedInstOperands,
43082 // GIR_Coverage, 935,
43083 GIR_EraseRootFromParent_Done,
43084 // Label 2567: @121632
43085 GIM_Try, /*On fail goto*//*Label 2568*/ GIMT_Encode4(121668), // Rule ID 936 //
43086 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
43087 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64x),
43088 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
43089 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
43090 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43091 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43092 // (intrinsic_wo_chain:{ *:[v2f64] } 599:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRINT64Xv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
43093 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64Xv2f64),
43094 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43095 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43096 GIR_RootConstrainSelectedInstOperands,
43097 // GIR_Coverage, 936,
43098 GIR_EraseRootFromParent_Done,
43099 // Label 2568: @121668
43100 GIM_Try, /*On fail goto*//*Label 2569*/ GIMT_Encode4(121704), // Rule ID 937 //
43101 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
43102 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
43103 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
43104 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
43105 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43106 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43107 // (intrinsic_wo_chain:{ *:[v4f16] } 601:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FRSQRTEv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
43108 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv4f16),
43109 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43110 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43111 GIR_RootConstrainSelectedInstOperands,
43112 // GIR_Coverage, 937,
43113 GIR_EraseRootFromParent_Done,
43114 // Label 2569: @121704
43115 GIM_Try, /*On fail goto*//*Label 2570*/ GIMT_Encode4(121740), // Rule ID 938 //
43116 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
43117 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
43118 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
43119 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43120 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43121 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43122 // (intrinsic_wo_chain:{ *:[v8f16] } 601:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FRSQRTEv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
43123 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv8f16),
43124 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43125 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43126 GIR_RootConstrainSelectedInstOperands,
43127 // GIR_Coverage, 938,
43128 GIR_EraseRootFromParent_Done,
43129 // Label 2570: @121740
43130 GIM_Try, /*On fail goto*//*Label 2571*/ GIMT_Encode4(121776), // Rule ID 939 //
43131 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43132 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
43133 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
43134 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
43135 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43136 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43137 // (intrinsic_wo_chain:{ *:[v2f32] } 601:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FRSQRTEv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
43138 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv2f32),
43139 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43140 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43141 GIR_RootConstrainSelectedInstOperands,
43142 // GIR_Coverage, 939,
43143 GIR_EraseRootFromParent_Done,
43144 // Label 2571: @121776
43145 GIM_Try, /*On fail goto*//*Label 2572*/ GIMT_Encode4(121812), // Rule ID 940 //
43146 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43147 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
43148 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
43149 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43150 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43151 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43152 // (intrinsic_wo_chain:{ *:[v4f32] } 601:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FRSQRTEv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
43153 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv4f32),
43154 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43155 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43156 GIR_RootConstrainSelectedInstOperands,
43157 // GIR_Coverage, 940,
43158 GIR_EraseRootFromParent_Done,
43159 // Label 2572: @121812
43160 GIM_Try, /*On fail goto*//*Label 2573*/ GIMT_Encode4(121848), // Rule ID 941 //
43161 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43162 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
43163 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
43164 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
43165 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43166 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43167 // (intrinsic_wo_chain:{ *:[v2f64] } 601:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FRSQRTEv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
43168 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv2f64),
43169 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43170 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43171 GIR_RootConstrainSelectedInstOperands,
43172 // GIR_Coverage, 941,
43173 GIR_EraseRootFromParent_Done,
43174 // Label 2573: @121848
43175 GIM_Try, /*On fail goto*//*Label 2574*/ GIMT_Encode4(121884), // Rule ID 988 //
43176 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43177 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
43178 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
43179 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
43180 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43181 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43182 // (intrinsic_wo_chain:{ *:[v4i16] } 622:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)
43183 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv8i8_v4i16),
43184 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43185 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43186 GIR_RootConstrainSelectedInstOperands,
43187 // GIR_Coverage, 988,
43188 GIR_EraseRootFromParent_Done,
43189 // Label 2574: @121884
43190 GIM_Try, /*On fail goto*//*Label 2575*/ GIMT_Encode4(121920), // Rule ID 990 //
43191 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43192 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
43193 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
43194 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
43195 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43196 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43197 // (intrinsic_wo_chain:{ *:[v8i16] } 622:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)
43198 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv16i8_v8i16),
43199 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43200 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43201 GIR_RootConstrainSelectedInstOperands,
43202 // GIR_Coverage, 990,
43203 GIR_EraseRootFromParent_Done,
43204 // Label 2575: @121920
43205 GIM_Try, /*On fail goto*//*Label 2576*/ GIMT_Encode4(121956), // Rule ID 992 //
43206 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43207 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
43208 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
43209 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
43210 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43211 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43212 // (intrinsic_wo_chain:{ *:[v2i32] } 622:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (SADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)
43213 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv4i16_v2i32),
43214 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43215 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43216 GIR_RootConstrainSelectedInstOperands,
43217 // GIR_Coverage, 992,
43218 GIR_EraseRootFromParent_Done,
43219 // Label 2576: @121956
43220 GIM_Try, /*On fail goto*//*Label 2577*/ GIMT_Encode4(121992), // Rule ID 994 //
43221 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43222 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
43223 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
43224 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43225 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43226 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43227 // (intrinsic_wo_chain:{ *:[v4i32] } 622:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)
43228 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv8i16_v4i32),
43229 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43230 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43231 GIR_RootConstrainSelectedInstOperands,
43232 // GIR_Coverage, 994,
43233 GIR_EraseRootFromParent_Done,
43234 // Label 2577: @121992
43235 GIM_Try, /*On fail goto*//*Label 2578*/ GIMT_Encode4(122028), // Rule ID 996 //
43236 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43237 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
43238 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
43239 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
43240 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43241 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43242 // (intrinsic_wo_chain:{ *:[v1i64] } 622:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (SADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn)
43243 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv2i32_v1i64),
43244 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43245 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43246 GIR_RootConstrainSelectedInstOperands,
43247 // GIR_Coverage, 996,
43248 GIR_EraseRootFromParent_Done,
43249 // Label 2578: @122028
43250 GIM_Try, /*On fail goto*//*Label 2579*/ GIMT_Encode4(122064), // Rule ID 998 //
43251 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43252 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
43253 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
43254 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43255 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43256 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43257 // (intrinsic_wo_chain:{ *:[v2i64] } 622:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)
43258 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv4i32_v2i64),
43259 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43260 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43261 GIR_RootConstrainSelectedInstOperands,
43262 // GIR_Coverage, 998,
43263 GIR_EraseRootFromParent_Done,
43264 // Label 2579: @122064
43265 GIM_Try, /*On fail goto*//*Label 2580*/ GIMT_Encode4(122100), // Rule ID 1009 //
43266 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43267 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
43268 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
43269 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
43270 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43271 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43272 // (intrinsic_wo_chain:{ *:[v8i8] } 640:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SQABSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
43273 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv8i8),
43274 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43275 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43276 GIR_RootConstrainSelectedInstOperands,
43277 // GIR_Coverage, 1009,
43278 GIR_EraseRootFromParent_Done,
43279 // Label 2580: @122100
43280 GIM_Try, /*On fail goto*//*Label 2581*/ GIMT_Encode4(122136), // Rule ID 1010 //
43281 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43282 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
43283 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
43284 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
43285 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43286 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43287 // (intrinsic_wo_chain:{ *:[v16i8] } 640:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SQABSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
43288 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv16i8),
43289 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43290 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43291 GIR_RootConstrainSelectedInstOperands,
43292 // GIR_Coverage, 1010,
43293 GIR_EraseRootFromParent_Done,
43294 // Label 2581: @122136
43295 GIM_Try, /*On fail goto*//*Label 2582*/ GIMT_Encode4(122172), // Rule ID 1011 //
43296 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43297 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
43298 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
43299 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
43300 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43301 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43302 // (intrinsic_wo_chain:{ *:[v4i16] } 640:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (SQABSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
43303 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv4i16),
43304 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43305 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43306 GIR_RootConstrainSelectedInstOperands,
43307 // GIR_Coverage, 1011,
43308 GIR_EraseRootFromParent_Done,
43309 // Label 2582: @122172
43310 GIM_Try, /*On fail goto*//*Label 2583*/ GIMT_Encode4(122208), // Rule ID 1012 //
43311 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43312 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
43313 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
43314 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43315 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43316 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43317 // (intrinsic_wo_chain:{ *:[v8i16] } 640:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQABSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
43318 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv8i16),
43319 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43320 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43321 GIR_RootConstrainSelectedInstOperands,
43322 // GIR_Coverage, 1012,
43323 GIR_EraseRootFromParent_Done,
43324 // Label 2583: @122208
43325 GIM_Try, /*On fail goto*//*Label 2584*/ GIMT_Encode4(122244), // Rule ID 1013 //
43326 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43327 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
43328 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
43329 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
43330 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43331 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43332 // (intrinsic_wo_chain:{ *:[v2i32] } 640:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (SQABSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
43333 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv2i32),
43334 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43335 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43336 GIR_RootConstrainSelectedInstOperands,
43337 // GIR_Coverage, 1013,
43338 GIR_EraseRootFromParent_Done,
43339 // Label 2584: @122244
43340 GIM_Try, /*On fail goto*//*Label 2585*/ GIMT_Encode4(122280), // Rule ID 1014 //
43341 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43342 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
43343 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
43344 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43345 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43346 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43347 // (intrinsic_wo_chain:{ *:[v4i32] } 640:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQABSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
43348 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv4i32),
43349 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43350 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43351 GIR_RootConstrainSelectedInstOperands,
43352 // GIR_Coverage, 1014,
43353 GIR_EraseRootFromParent_Done,
43354 // Label 2585: @122280
43355 GIM_Try, /*On fail goto*//*Label 2586*/ GIMT_Encode4(122316), // Rule ID 1015 //
43356 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43357 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
43358 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
43359 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
43360 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43361 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43362 // (intrinsic_wo_chain:{ *:[v2i64] } 640:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQABSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
43363 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv2i64),
43364 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43365 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43366 GIR_RootConstrainSelectedInstOperands,
43367 // GIR_Coverage, 1015,
43368 GIR_EraseRootFromParent_Done,
43369 // Label 2586: @122316
43370 GIM_Try, /*On fail goto*//*Label 2587*/ GIMT_Encode4(122352), // Rule ID 1016 //
43371 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43372 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
43373 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
43374 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
43375 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43376 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43377 // (intrinsic_wo_chain:{ *:[v8i8] } 647:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SQNEGv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
43378 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv8i8),
43379 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43380 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43381 GIR_RootConstrainSelectedInstOperands,
43382 // GIR_Coverage, 1016,
43383 GIR_EraseRootFromParent_Done,
43384 // Label 2587: @122352
43385 GIM_Try, /*On fail goto*//*Label 2588*/ GIMT_Encode4(122388), // Rule ID 1017 //
43386 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43387 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
43388 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
43389 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
43390 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43391 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43392 // (intrinsic_wo_chain:{ *:[v16i8] } 647:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SQNEGv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
43393 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv16i8),
43394 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43395 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43396 GIR_RootConstrainSelectedInstOperands,
43397 // GIR_Coverage, 1017,
43398 GIR_EraseRootFromParent_Done,
43399 // Label 2588: @122388
43400 GIM_Try, /*On fail goto*//*Label 2589*/ GIMT_Encode4(122424), // Rule ID 1018 //
43401 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43402 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
43403 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
43404 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
43405 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43406 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43407 // (intrinsic_wo_chain:{ *:[v4i16] } 647:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (SQNEGv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
43408 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv4i16),
43409 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43410 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43411 GIR_RootConstrainSelectedInstOperands,
43412 // GIR_Coverage, 1018,
43413 GIR_EraseRootFromParent_Done,
43414 // Label 2589: @122424
43415 GIM_Try, /*On fail goto*//*Label 2590*/ GIMT_Encode4(122460), // Rule ID 1019 //
43416 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43417 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
43418 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
43419 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43420 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43421 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43422 // (intrinsic_wo_chain:{ *:[v8i16] } 647:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQNEGv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
43423 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv8i16),
43424 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43425 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43426 GIR_RootConstrainSelectedInstOperands,
43427 // GIR_Coverage, 1019,
43428 GIR_EraseRootFromParent_Done,
43429 // Label 2590: @122460
43430 GIM_Try, /*On fail goto*//*Label 2591*/ GIMT_Encode4(122496), // Rule ID 1020 //
43431 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43432 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
43433 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
43434 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
43435 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43436 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43437 // (intrinsic_wo_chain:{ *:[v2i32] } 647:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (SQNEGv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
43438 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv2i32),
43439 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43440 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43441 GIR_RootConstrainSelectedInstOperands,
43442 // GIR_Coverage, 1020,
43443 GIR_EraseRootFromParent_Done,
43444 // Label 2591: @122496
43445 GIM_Try, /*On fail goto*//*Label 2592*/ GIMT_Encode4(122532), // Rule ID 1021 //
43446 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43447 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
43448 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
43449 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43450 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43451 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43452 // (intrinsic_wo_chain:{ *:[v4i32] } 647:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQNEGv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
43453 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv4i32),
43454 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43455 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43456 GIR_RootConstrainSelectedInstOperands,
43457 // GIR_Coverage, 1021,
43458 GIR_EraseRootFromParent_Done,
43459 // Label 2592: @122532
43460 GIM_Try, /*On fail goto*//*Label 2593*/ GIMT_Encode4(122568), // Rule ID 1022 //
43461 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43462 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
43463 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
43464 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
43465 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43466 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43467 // (intrinsic_wo_chain:{ *:[v2i64] } 647:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQNEGv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
43468 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv2i64),
43469 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43470 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43471 GIR_RootConstrainSelectedInstOperands,
43472 // GIR_Coverage, 1022,
43473 GIR_EraseRootFromParent_Done,
43474 // Label 2593: @122568
43475 GIM_Try, /*On fail goto*//*Label 2594*/ GIMT_Encode4(122604), // Rule ID 1023 //
43476 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43477 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqxtn),
43478 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
43479 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43480 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43481 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43482 // (intrinsic_wo_chain:{ *:[v8i8] } 661:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQXTNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn)
43483 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNv8i8),
43484 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43485 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43486 GIR_RootConstrainSelectedInstOperands,
43487 // GIR_Coverage, 1023,
43488 GIR_EraseRootFromParent_Done,
43489 // Label 2594: @122604
43490 GIM_Try, /*On fail goto*//*Label 2595*/ GIMT_Encode4(122640), // Rule ID 1024 //
43491 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43492 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqxtn),
43493 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
43494 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43495 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43496 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43497 // (intrinsic_wo_chain:{ *:[v4i16] } 661:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQXTNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn)
43498 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNv4i16),
43499 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43500 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43501 GIR_RootConstrainSelectedInstOperands,
43502 // GIR_Coverage, 1024,
43503 GIR_EraseRootFromParent_Done,
43504 // Label 2595: @122640
43505 GIM_Try, /*On fail goto*//*Label 2596*/ GIMT_Encode4(122676), // Rule ID 1025 //
43506 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43507 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqxtn),
43508 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
43509 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
43510 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43511 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43512 // (intrinsic_wo_chain:{ *:[v2i32] } 661:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQXTNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn)
43513 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNv2i32),
43514 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43515 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43516 GIR_RootConstrainSelectedInstOperands,
43517 // GIR_Coverage, 1025,
43518 GIR_EraseRootFromParent_Done,
43519 // Label 2596: @122676
43520 GIM_Try, /*On fail goto*//*Label 2597*/ GIMT_Encode4(122712), // Rule ID 1026 //
43521 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43522 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqxtun),
43523 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
43524 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43525 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43526 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43527 // (intrinsic_wo_chain:{ *:[v8i8] } 662:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SQXTUNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn)
43528 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNv8i8),
43529 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43530 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43531 GIR_RootConstrainSelectedInstOperands,
43532 // GIR_Coverage, 1026,
43533 GIR_EraseRootFromParent_Done,
43534 // Label 2597: @122712
43535 GIM_Try, /*On fail goto*//*Label 2598*/ GIMT_Encode4(122748), // Rule ID 1027 //
43536 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43537 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqxtun),
43538 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
43539 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43540 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43541 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43542 // (intrinsic_wo_chain:{ *:[v4i16] } 662:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (SQXTUNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn)
43543 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNv4i16),
43544 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43545 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43546 GIR_RootConstrainSelectedInstOperands,
43547 // GIR_Coverage, 1027,
43548 GIR_EraseRootFromParent_Done,
43549 // Label 2598: @122748
43550 GIM_Try, /*On fail goto*//*Label 2599*/ GIMT_Encode4(122784), // Rule ID 1028 //
43551 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43552 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqxtun),
43553 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
43554 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
43555 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43556 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43557 // (intrinsic_wo_chain:{ *:[v2i32] } 662:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (SQXTUNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn)
43558 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNv2i32),
43559 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43560 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43561 GIR_RootConstrainSelectedInstOperands,
43562 // GIR_Coverage, 1028,
43563 GIR_EraseRootFromParent_Done,
43564 // Label 2599: @122784
43565 GIM_Try, /*On fail goto*//*Label 2600*/ GIMT_Encode4(122820), // Rule ID 1049 //
43566 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43567 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
43568 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
43569 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
43570 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43571 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43572 // (intrinsic_wo_chain:{ *:[v4i16] } 687:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (UADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)
43573 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv8i8_v4i16),
43574 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43575 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43576 GIR_RootConstrainSelectedInstOperands,
43577 // GIR_Coverage, 1049,
43578 GIR_EraseRootFromParent_Done,
43579 // Label 2600: @122820
43580 GIM_Try, /*On fail goto*//*Label 2601*/ GIMT_Encode4(122856), // Rule ID 1051 //
43581 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43582 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
43583 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
43584 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
43585 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43586 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43587 // (intrinsic_wo_chain:{ *:[v8i16] } 687:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (UADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)
43588 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv16i8_v8i16),
43589 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43590 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43591 GIR_RootConstrainSelectedInstOperands,
43592 // GIR_Coverage, 1051,
43593 GIR_EraseRootFromParent_Done,
43594 // Label 2601: @122856
43595 GIM_Try, /*On fail goto*//*Label 2602*/ GIMT_Encode4(122892), // Rule ID 1053 //
43596 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43597 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
43598 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
43599 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
43600 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43601 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43602 // (intrinsic_wo_chain:{ *:[v2i32] } 687:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (UADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)
43603 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv4i16_v2i32),
43604 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43605 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43606 GIR_RootConstrainSelectedInstOperands,
43607 // GIR_Coverage, 1053,
43608 GIR_EraseRootFromParent_Done,
43609 // Label 2602: @122892
43610 GIM_Try, /*On fail goto*//*Label 2603*/ GIMT_Encode4(122928), // Rule ID 1055 //
43611 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43612 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
43613 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
43614 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43615 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43616 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43617 // (intrinsic_wo_chain:{ *:[v4i32] } 687:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (UADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)
43618 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv8i16_v4i32),
43619 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43620 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43621 GIR_RootConstrainSelectedInstOperands,
43622 // GIR_Coverage, 1055,
43623 GIR_EraseRootFromParent_Done,
43624 // Label 2603: @122928
43625 GIM_Try, /*On fail goto*//*Label 2604*/ GIMT_Encode4(122964), // Rule ID 1057 //
43626 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43627 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
43628 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
43629 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
43630 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43631 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43632 // (intrinsic_wo_chain:{ *:[v1i64] } 687:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (UADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn)
43633 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv2i32_v1i64),
43634 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43635 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43636 GIR_RootConstrainSelectedInstOperands,
43637 // GIR_Coverage, 1057,
43638 GIR_EraseRootFromParent_Done,
43639 // Label 2604: @122964
43640 GIM_Try, /*On fail goto*//*Label 2605*/ GIMT_Encode4(123000), // Rule ID 1059 //
43641 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43642 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
43643 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
43644 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43645 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43646 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43647 // (intrinsic_wo_chain:{ *:[v2i64] } 687:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (UADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)
43648 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv4i32_v2i64),
43649 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43650 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43651 GIR_RootConstrainSelectedInstOperands,
43652 // GIR_Coverage, 1059,
43653 GIR_EraseRootFromParent_Done,
43654 // Label 2605: @123000
43655 GIM_Try, /*On fail goto*//*Label 2606*/ GIMT_Encode4(123036), // Rule ID 1070 //
43656 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43657 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqxtn),
43658 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
43659 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43660 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43661 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43662 // (intrinsic_wo_chain:{ *:[v8i8] } 707:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (UQXTNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn)
43663 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNv8i8),
43664 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43665 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43666 GIR_RootConstrainSelectedInstOperands,
43667 // GIR_Coverage, 1070,
43668 GIR_EraseRootFromParent_Done,
43669 // Label 2606: @123036
43670 GIM_Try, /*On fail goto*//*Label 2607*/ GIMT_Encode4(123072), // Rule ID 1071 //
43671 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43672 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqxtn),
43673 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
43674 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43675 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43676 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43677 // (intrinsic_wo_chain:{ *:[v4i16] } 707:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (UQXTNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn)
43678 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNv4i16),
43679 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43680 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43681 GIR_RootConstrainSelectedInstOperands,
43682 // GIR_Coverage, 1071,
43683 GIR_EraseRootFromParent_Done,
43684 // Label 2607: @123072
43685 GIM_Try, /*On fail goto*//*Label 2608*/ GIMT_Encode4(123108), // Rule ID 1072 //
43686 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43687 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqxtn),
43688 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
43689 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
43690 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43691 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43692 // (intrinsic_wo_chain:{ *:[v2i32] } 707:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (UQXTNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn)
43693 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNv2i32),
43694 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43695 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43696 GIR_RootConstrainSelectedInstOperands,
43697 // GIR_Coverage, 1072,
43698 GIR_EraseRootFromParent_Done,
43699 // Label 2608: @123108
43700 GIM_Try, /*On fail goto*//*Label 2609*/ GIMT_Encode4(123144), // Rule ID 1073 //
43701 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43702 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urecpe),
43703 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
43704 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
43705 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43706 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43707 // (intrinsic_wo_chain:{ *:[v2i32] } 708:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (URECPEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
43708 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URECPEv2i32),
43709 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43710 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43711 GIR_RootConstrainSelectedInstOperands,
43712 // GIR_Coverage, 1073,
43713 GIR_EraseRootFromParent_Done,
43714 // Label 2609: @123144
43715 GIM_Try, /*On fail goto*//*Label 2610*/ GIMT_Encode4(123180), // Rule ID 1074 //
43716 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43717 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urecpe),
43718 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
43719 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43720 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43721 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43722 // (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (URECPEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
43723 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URECPEv4i32),
43724 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43725 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43726 GIR_RootConstrainSelectedInstOperands,
43727 // GIR_Coverage, 1074,
43728 GIR_EraseRootFromParent_Done,
43729 // Label 2610: @123180
43730 GIM_Try, /*On fail goto*//*Label 2611*/ GIMT_Encode4(123216), // Rule ID 1075 //
43731 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43732 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ursqrte),
43733 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
43734 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
43735 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43736 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43737 // (intrinsic_wo_chain:{ *:[v2i32] } 711:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (URSQRTEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
43738 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSQRTEv2i32),
43739 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43740 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43741 GIR_RootConstrainSelectedInstOperands,
43742 // GIR_Coverage, 1075,
43743 GIR_EraseRootFromParent_Done,
43744 // Label 2611: @123216
43745 GIM_Try, /*On fail goto*//*Label 2612*/ GIMT_Encode4(123252), // Rule ID 1076 //
43746 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43747 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ursqrte),
43748 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
43749 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43750 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43751 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43752 // (intrinsic_wo_chain:{ *:[v4i32] } 711:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (URSQRTEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
43753 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSQRTEv4i32),
43754 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43755 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43756 GIR_RootConstrainSelectedInstOperands,
43757 // GIR_Coverage, 1076,
43758 GIR_EraseRootFromParent_Done,
43759 // Label 2612: @123252
43760 GIM_Try, /*On fail goto*//*Label 2613*/ GIMT_Encode4(123288), // Rule ID 1640 //
43761 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43762 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sisd_fcvtxn),
43763 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
43764 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
43765 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
43766 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43767 // (intrinsic_wo_chain:{ *:[f32] } 741:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FCVTXNv1i64:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
43768 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTXNv1i64),
43769 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43770 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43771 GIR_RootConstrainSelectedInstOperands,
43772 // GIR_Coverage, 1640,
43773 GIR_EraseRootFromParent_Done,
43774 // Label 2613: @123288
43775 GIM_Try, /*On fail goto*//*Label 2614*/ GIMT_Encode4(123324), // Rule ID 1646 //
43776 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43777 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
43778 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
43779 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
43780 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43781 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43782 // (intrinsic_wo_chain:{ *:[i64] } 640:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn) => (SQABSv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn)
43783 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv1i64),
43784 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43785 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43786 GIR_RootConstrainSelectedInstOperands,
43787 // GIR_Coverage, 1646,
43788 GIR_EraseRootFromParent_Done,
43789 // Label 2614: @123324
43790 GIM_Try, /*On fail goto*//*Label 2615*/ GIMT_Encode4(123360), // Rule ID 1647 //
43791 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43792 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
43793 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
43794 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
43795 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
43796 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
43797 // (intrinsic_wo_chain:{ *:[i32] } 640:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn) => (SQABSv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn)
43798 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv1i32),
43799 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43800 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43801 GIR_RootConstrainSelectedInstOperands,
43802 // GIR_Coverage, 1647,
43803 GIR_EraseRootFromParent_Done,
43804 // Label 2615: @123360
43805 GIM_Try, /*On fail goto*//*Label 2616*/ GIMT_Encode4(123396), // Rule ID 1648 //
43806 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43807 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
43808 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
43809 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
43810 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43811 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43812 // (intrinsic_wo_chain:{ *:[i64] } 647:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn) => (SQNEGv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn)
43813 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv1i64),
43814 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43815 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43816 GIR_RootConstrainSelectedInstOperands,
43817 // GIR_Coverage, 1648,
43818 GIR_EraseRootFromParent_Done,
43819 // Label 2616: @123396
43820 GIM_Try, /*On fail goto*//*Label 2617*/ GIMT_Encode4(123432), // Rule ID 1649 //
43821 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43822 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
43823 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
43824 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
43825 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
43826 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
43827 // (intrinsic_wo_chain:{ *:[i32] } 647:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn) => (SQNEGv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn)
43828 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv1i32),
43829 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43830 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43831 GIR_RootConstrainSelectedInstOperands,
43832 // GIR_Coverage, 1649,
43833 GIR_EraseRootFromParent_Done,
43834 // Label 2617: @123432
43835 GIM_Try, /*On fail goto*//*Label 2618*/ GIMT_Encode4(123468), // Rule ID 1650 //
43836 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43837 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_scalar_sqxtn),
43838 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
43839 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
43840 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
43841 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43842 // (intrinsic_wo_chain:{ *:[f32] } 625:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (SQXTNv1i32:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
43843 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNv1i32),
43844 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43845 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43846 GIR_RootConstrainSelectedInstOperands,
43847 // GIR_Coverage, 1650,
43848 GIR_EraseRootFromParent_Done,
43849 // Label 2618: @123468
43850 GIM_Try, /*On fail goto*//*Label 2619*/ GIMT_Encode4(123504), // Rule ID 1651 //
43851 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43852 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_scalar_sqxtun),
43853 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
43854 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
43855 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
43856 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43857 // (intrinsic_wo_chain:{ *:[f32] } 626:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (SQXTUNv1i32:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
43858 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNv1i32),
43859 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43860 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43861 GIR_RootConstrainSelectedInstOperands,
43862 // GIR_Coverage, 1651,
43863 GIR_EraseRootFromParent_Done,
43864 // Label 2619: @123504
43865 GIM_Try, /*On fail goto*//*Label 2620*/ GIMT_Encode4(123540), // Rule ID 1657 //
43866 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43867 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_scalar_uqxtn),
43868 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
43869 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
43870 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
43871 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43872 // (intrinsic_wo_chain:{ *:[f32] } 627:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (UQXTNv1i32:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
43873 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNv1i32),
43874 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43875 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43876 GIR_RootConstrainSelectedInstOperands,
43877 // GIR_Coverage, 1657,
43878 GIR_EraseRootFromParent_Done,
43879 // Label 2620: @123540
43880 GIM_Try, /*On fail goto*//*Label 2621*/ GIMT_Encode4(123576), // Rule ID 1930 //
43881 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
43882 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmv),
43883 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
43884 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
43885 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
43886 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43887 // (intrinsic_wo_chain:{ *:[f16] } 580:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMAXNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
43888 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMVv4i16v),
43889 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43890 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43891 GIR_RootConstrainSelectedInstOperands,
43892 // GIR_Coverage, 1930,
43893 GIR_EraseRootFromParent_Done,
43894 // Label 2621: @123576
43895 GIM_Try, /*On fail goto*//*Label 2622*/ GIMT_Encode4(123612), // Rule ID 1932 //
43896 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
43897 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmv),
43898 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
43899 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43900 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
43901 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43902 // (intrinsic_wo_chain:{ *:[f16] } 580:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMAXNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
43903 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMVv8i16v),
43904 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43905 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43906 GIR_RootConstrainSelectedInstOperands,
43907 // GIR_Coverage, 1932,
43908 GIR_EraseRootFromParent_Done,
43909 // Label 2622: @123612
43910 GIM_Try, /*On fail goto*//*Label 2623*/ GIMT_Encode4(123648), // Rule ID 1934 //
43911 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43912 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmv),
43913 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
43914 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43915 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
43916 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43917 // (intrinsic_wo_chain:{ *:[f32] } 580:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMAXNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
43918 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMVv4i32v),
43919 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43920 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43921 GIR_RootConstrainSelectedInstOperands,
43922 // GIR_Coverage, 1934,
43923 GIR_EraseRootFromParent_Done,
43924 // Label 2623: @123648
43925 GIM_Try, /*On fail goto*//*Label 2624*/ GIMT_Encode4(123684), // Rule ID 1936 //
43926 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
43927 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxv),
43928 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
43929 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
43930 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
43931 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43932 // (intrinsic_wo_chain:{ *:[f16] } 582:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMAXVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
43933 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXVv4i16v),
43934 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43935 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43936 GIR_RootConstrainSelectedInstOperands,
43937 // GIR_Coverage, 1936,
43938 GIR_EraseRootFromParent_Done,
43939 // Label 2624: @123684
43940 GIM_Try, /*On fail goto*//*Label 2625*/ GIMT_Encode4(123720), // Rule ID 1938 //
43941 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
43942 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxv),
43943 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
43944 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43945 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
43946 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43947 // (intrinsic_wo_chain:{ *:[f16] } 582:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMAXVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
43948 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXVv8i16v),
43949 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43950 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43951 GIR_RootConstrainSelectedInstOperands,
43952 // GIR_Coverage, 1938,
43953 GIR_EraseRootFromParent_Done,
43954 // Label 2625: @123720
43955 GIM_Try, /*On fail goto*//*Label 2626*/ GIMT_Encode4(123756), // Rule ID 1940 //
43956 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43957 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxv),
43958 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
43959 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43960 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
43961 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43962 // (intrinsic_wo_chain:{ *:[f32] } 582:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMAXVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
43963 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXVv4i32v),
43964 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43965 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43966 GIR_RootConstrainSelectedInstOperands,
43967 // GIR_Coverage, 1940,
43968 GIR_EraseRootFromParent_Done,
43969 // Label 2626: @123756
43970 GIM_Try, /*On fail goto*//*Label 2627*/ GIMT_Encode4(123792), // Rule ID 1942 //
43971 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
43972 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmv),
43973 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
43974 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
43975 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
43976 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
43977 // (intrinsic_wo_chain:{ *:[f16] } 586:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMINNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
43978 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMVv4i16v),
43979 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43980 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43981 GIR_RootConstrainSelectedInstOperands,
43982 // GIR_Coverage, 1942,
43983 GIR_EraseRootFromParent_Done,
43984 // Label 2627: @123792
43985 GIM_Try, /*On fail goto*//*Label 2628*/ GIMT_Encode4(123828), // Rule ID 1944 //
43986 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
43987 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmv),
43988 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
43989 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43990 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
43991 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
43992 // (intrinsic_wo_chain:{ *:[f16] } 586:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMINNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
43993 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMVv8i16v),
43994 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
43995 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
43996 GIR_RootConstrainSelectedInstOperands,
43997 // GIR_Coverage, 1944,
43998 GIR_EraseRootFromParent_Done,
43999 // Label 2628: @123828
44000 GIM_Try, /*On fail goto*//*Label 2629*/ GIMT_Encode4(123864), // Rule ID 1946 //
44001 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
44002 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmv),
44003 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
44004 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
44005 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
44006 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44007 // (intrinsic_wo_chain:{ *:[f32] } 586:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMINNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
44008 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMVv4i32v),
44009 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44010 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44011 GIR_RootConstrainSelectedInstOperands,
44012 // GIR_Coverage, 1946,
44013 GIR_EraseRootFromParent_Done,
44014 // Label 2629: @123864
44015 GIM_Try, /*On fail goto*//*Label 2630*/ GIMT_Encode4(123900), // Rule ID 1948 //
44016 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
44017 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminv),
44018 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
44019 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
44020 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
44021 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44022 // (intrinsic_wo_chain:{ *:[f16] } 588:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn) => (FMINVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
44023 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINVv4i16v),
44024 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44025 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44026 GIR_RootConstrainSelectedInstOperands,
44027 // GIR_Coverage, 1948,
44028 GIR_EraseRootFromParent_Done,
44029 // Label 2630: @123900
44030 GIM_Try, /*On fail goto*//*Label 2631*/ GIMT_Encode4(123936), // Rule ID 1950 //
44031 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
44032 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminv),
44033 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
44034 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
44035 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
44036 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44037 // (intrinsic_wo_chain:{ *:[f16] } 588:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn) => (FMINVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
44038 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINVv8i16v),
44039 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44040 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44041 GIR_RootConstrainSelectedInstOperands,
44042 // GIR_Coverage, 1950,
44043 GIR_EraseRootFromParent_Done,
44044 // Label 2631: @123936
44045 GIM_Try, /*On fail goto*//*Label 2632*/ GIMT_Encode4(123972), // Rule ID 1952 //
44046 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
44047 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminv),
44048 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
44049 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
44050 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
44051 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44052 // (intrinsic_wo_chain:{ *:[f32] } 588:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FMINVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
44053 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINVv4i32v),
44054 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44055 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44056 GIR_RootConstrainSelectedInstOperands,
44057 // GIR_Coverage, 1952,
44058 GIR_EraseRootFromParent_Done,
44059 // Label 2632: @123972
44060 GIM_Try, /*On fail goto*//*Label 2633*/ GIMT_Encode4(124008), // Rule ID 2290 //
44061 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES),
44062 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aesmc),
44063 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
44064 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
44065 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44066 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44067 // (intrinsic_wo_chain:{ *:[v16i8] } 496:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (AESMCrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
44068 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESMCrr),
44069 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44070 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44071 GIR_RootConstrainSelectedInstOperands,
44072 // GIR_Coverage, 2290,
44073 GIR_EraseRootFromParent_Done,
44074 // Label 2633: @124008
44075 GIM_Try, /*On fail goto*//*Label 2634*/ GIMT_Encode4(124044), // Rule ID 2291 //
44076 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES),
44077 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aesimc),
44078 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
44079 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
44080 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44081 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44082 // (intrinsic_wo_chain:{ *:[v16i8] } 495:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (AESIMCrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
44083 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESIMCrr),
44084 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44085 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44086 GIR_RootConstrainSelectedInstOperands,
44087 // GIR_Coverage, 2291,
44088 GIR_EraseRootFromParent_Done,
44089 // Label 2634: @124044
44090 GIM_Try, /*On fail goto*//*Label 2635*/ GIMT_Encode4(124080), // Rule ID 2299 //
44091 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
44092 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha1h),
44093 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
44094 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
44095 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
44096 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
44097 // (intrinsic_wo_chain:{ *:[i32] } 503:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn) => (SHA1Hrr:{ *:[i32] } FPR32:{ *:[i32] }:$Rn)
44098 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA1Hrr),
44099 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44100 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44101 GIR_RootConstrainSelectedInstOperands,
44102 // GIR_Coverage, 2299,
44103 GIR_EraseRootFromParent_Done,
44104 // Label 2635: @124080
44105 GIM_Try, /*On fail goto*//*Label 2636*/ GIMT_Encode4(124116), // Rule ID 2437 //
44106 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
44107 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
44108 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44109 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44110 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44111 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44112 // (intrinsic_wo_chain:{ *:[v1i64] } 640:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn) => (SQABSv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
44113 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv1i64),
44114 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44115 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44116 GIR_RootConstrainSelectedInstOperands,
44117 // GIR_Coverage, 2437,
44118 GIR_EraseRootFromParent_Done,
44119 // Label 2636: @124116
44120 GIM_Try, /*On fail goto*//*Label 2637*/ GIMT_Encode4(124155), // Rule ID 3471 //
44121 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
44122 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane_zero),
44123 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
44124 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
44125 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
44126 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
44127 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1408:{ *:[iPTR] }, ZPRAny:{ *:[nxv16i8] }:$Zn) => (PMOV_PZI_B:{ *:[nxv16i1] } ZPRAny:{ *:[nxv16i8] }:$Zn, 0:{ *:[i32] })
44128 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_B),
44129 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
44130 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
44131 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44132 GIR_RootConstrainSelectedInstOperands,
44133 // GIR_Coverage, 3471,
44134 GIR_EraseRootFromParent_Done,
44135 // Label 2637: @124155
44136 GIM_Try, /*On fail goto*//*Label 2638*/ GIMT_Encode4(124194), // Rule ID 3472 //
44137 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
44138 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane_zero),
44139 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
44140 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
44141 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
44142 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
44143 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1408:{ *:[iPTR] }, ZPRAny:{ *:[nxv8i16] }:$Zn) => (PMOV_PZI_H:{ *:[nxv8i1] } ZPRAny:{ *:[nxv8i16] }:$Zn, 0:{ *:[i32] })
44144 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_H),
44145 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
44146 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
44147 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44148 GIR_RootConstrainSelectedInstOperands,
44149 // GIR_Coverage, 3472,
44150 GIR_EraseRootFromParent_Done,
44151 // Label 2638: @124194
44152 GIM_Try, /*On fail goto*//*Label 2639*/ GIMT_Encode4(124233), // Rule ID 3473 //
44153 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
44154 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane_zero),
44155 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
44156 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
44157 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
44158 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
44159 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1408:{ *:[iPTR] }, ZPRAny:{ *:[nxv4i32] }:$Zn) => (PMOV_PZI_S:{ *:[nxv4i1] } ZPRAny:{ *:[nxv4i32] }:$Zn, 0:{ *:[i32] })
44160 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_S),
44161 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
44162 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
44163 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44164 GIR_RootConstrainSelectedInstOperands,
44165 // GIR_Coverage, 3473,
44166 GIR_EraseRootFromParent_Done,
44167 // Label 2639: @124233
44168 GIM_Try, /*On fail goto*//*Label 2640*/ GIMT_Encode4(124272), // Rule ID 3474 //
44169 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
44170 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane_zero),
44171 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
44172 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
44173 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
44174 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
44175 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1408:{ *:[iPTR] }, ZPRAny:{ *:[nxv2i64] }:$Zn) => (PMOV_PZI_D:{ *:[nxv2i1] } ZPRAny:{ *:[nxv2i64] }:$Zn, 0:{ *:[i32] })
44176 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_D),
44177 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
44178 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
44179 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44180 GIR_RootConstrainSelectedInstOperands,
44181 // GIR_Coverage, 3474,
44182 GIR_EraseRootFromParent_Done,
44183 // Label 2640: @124272
44184 GIM_Try, /*On fail goto*//*Label 2641*/ GIMT_Encode4(124328), // Rule ID 3478 //
44185 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
44186 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_zeroing),
44187 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
44188 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
44189 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
44190 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
44191 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1410:{ *:[iPTR] }, PPR8:{ *:[nxv16i1] }:$Pn) => (PMOV_ZIP_B:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), 0:{ *:[i64] }, PPR8:{ *:[nxv16i1] }:$Pn)
44192 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
44193 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44194 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44195 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44196 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_B),
44197 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
44198 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44199 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44200 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
44201 GIR_RootConstrainSelectedInstOperands,
44202 // GIR_Coverage, 3478,
44203 GIR_EraseRootFromParent_Done,
44204 // Label 2641: @124328
44205 GIM_Try, /*On fail goto*//*Label 2642*/ GIMT_Encode4(124384), // Rule ID 3479 //
44206 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
44207 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_zeroing),
44208 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
44209 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
44210 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
44211 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
44212 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1410:{ *:[iPTR] }, PPR16:{ *:[nxv8i1] }:$Pn) => (PMOV_ZIP_H:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), 0:{ *:[i32] }, PPR16:{ *:[nxv8i1] }:$Pn)
44213 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
44214 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44215 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44216 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44217 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_H),
44218 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
44219 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44220 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44221 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
44222 GIR_RootConstrainSelectedInstOperands,
44223 // GIR_Coverage, 3479,
44224 GIR_EraseRootFromParent_Done,
44225 // Label 2642: @124384
44226 GIM_Try, /*On fail goto*//*Label 2643*/ GIMT_Encode4(124440), // Rule ID 3480 //
44227 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
44228 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_zeroing),
44229 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
44230 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
44231 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
44232 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
44233 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1410:{ *:[iPTR] }, PPR32:{ *:[nxv4i1] }:$Pn) => (PMOV_ZIP_S:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), 0:{ *:[i32] }, PPR32:{ *:[nxv4i1] }:$Pn)
44234 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
44235 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44236 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44237 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44238 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_S),
44239 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
44240 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44241 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44242 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
44243 GIR_RootConstrainSelectedInstOperands,
44244 // GIR_Coverage, 3480,
44245 GIR_EraseRootFromParent_Done,
44246 // Label 2643: @124440
44247 GIM_Try, /*On fail goto*//*Label 2644*/ GIMT_Encode4(124496), // Rule ID 3481 //
44248 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
44249 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_zeroing),
44250 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
44251 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
44252 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
44253 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
44254 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1410:{ *:[iPTR] }, PPR64:{ *:[nxv2i1] }:$Pn) => (PMOV_ZIP_D:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), 0:{ *:[i32] }, PPR64:{ *:[nxv2i1] }:$Pn)
44255 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
44256 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44257 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44258 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44259 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_D),
44260 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
44261 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44262 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44263 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
44264 GIR_RootConstrainSelectedInstOperands,
44265 // GIR_Coverage, 3481,
44266 GIR_EraseRootFromParent_Done,
44267 // Label 2644: @124496
44268 GIM_Try, /*On fail goto*//*Label 2645*/ GIMT_Encode4(124529), // Rule ID 3878 //
44269 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_cls),
44270 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
44271 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
44272 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
44273 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
44274 // (intrinsic_wo_chain:{ *:[i32] } 483:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn) => (CLSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
44275 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSWr),
44276 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44277 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44278 GIR_RootConstrainSelectedInstOperands,
44279 // GIR_Coverage, 3878,
44280 GIR_EraseRootFromParent_Done,
44281 // Label 2645: @124529
44282 GIM_Try, /*On fail goto*//*Label 2646*/ GIMT_Encode4(124594), // Rule ID 3879 //
44283 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_cls64),
44284 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
44285 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44286 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
44287 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
44288 // (intrinsic_wo_chain:{ *:[i32] } 484:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rm) => (EXTRACT_SUBREG:{ *:[i32] } (CLSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rm), sub_32:{ *:[i32] })
44289 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
44290 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CLSXr),
44291 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44292 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
44293 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44294 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44295 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44296 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
44297 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
44298 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
44299 // GIR_Coverage, 3879,
44300 GIR_EraseRootFromParent_Done,
44301 // Label 2646: @124594
44302 GIM_Try, /*On fail goto*//*Label 2647*/ GIMT_Encode4(124627), // Rule ID 4465 //
44303 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32z),
44304 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44305 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44306 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44307 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44308 // (intrinsic_wo_chain:{ *:[v1f64] } 598:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FRINT32ZDr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn)
44309 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32ZDr),
44310 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44311 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44312 GIR_RootConstrainSelectedInstOperands,
44313 // GIR_Coverage, 4465,
44314 GIR_EraseRootFromParent_Done,
44315 // Label 2647: @124627
44316 GIM_Try, /*On fail goto*//*Label 2648*/ GIMT_Encode4(124660), // Rule ID 4466 //
44317 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64z),
44318 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44319 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44320 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44321 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44322 // (intrinsic_wo_chain:{ *:[v1f64] } 600:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FRINT64ZDr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn)
44323 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64ZDr),
44324 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44325 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44326 GIR_RootConstrainSelectedInstOperands,
44327 // GIR_Coverage, 4466,
44328 GIR_EraseRootFromParent_Done,
44329 // Label 2648: @124660
44330 GIM_Try, /*On fail goto*//*Label 2649*/ GIMT_Encode4(124693), // Rule ID 4467 //
44331 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32x),
44332 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44333 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44334 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44335 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44336 // (intrinsic_wo_chain:{ *:[v1f64] } 597:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FRINT32XDr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn)
44337 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32XDr),
44338 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44339 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44340 GIR_RootConstrainSelectedInstOperands,
44341 // GIR_Coverage, 4467,
44342 GIR_EraseRootFromParent_Done,
44343 // Label 2649: @124693
44344 GIM_Try, /*On fail goto*//*Label 2650*/ GIMT_Encode4(124726), // Rule ID 4468 //
44345 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64x),
44346 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44347 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44348 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44349 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44350 // (intrinsic_wo_chain:{ *:[v1f64] } 599:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FRINT64XDr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn)
44351 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64XDr),
44352 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44353 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44354 GIR_RootConstrainSelectedInstOperands,
44355 // GIR_Coverage, 4468,
44356 GIR_EraseRootFromParent_Done,
44357 // Label 2650: @124726
44358 GIM_Try, /*On fail goto*//*Label 2651*/ GIMT_Encode4(124759), // Rule ID 4557 //
44359 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvthf2fp),
44360 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
44361 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
44362 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44363 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44364 // (intrinsic_wo_chain:{ *:[v4f32] } 729:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (FCVTLv4i16:{ *:[v4f32] } V64:{ *:[v4i16] }:$Rn)
44365 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
44366 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44367 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44368 GIR_RootConstrainSelectedInstOperands,
44369 // GIR_Coverage, 4557,
44370 GIR_EraseRootFromParent_Done,
44371 // Label 2651: @124759
44372 GIM_Try, /*On fail goto*//*Label 2652*/ GIMT_Encode4(124792), // Rule ID 4567 //
44373 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2hf),
44374 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
44375 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
44376 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44377 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44378 // (intrinsic_wo_chain:{ *:[v4i16] } 726:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FCVTNv4i16:{ *:[v4i16] } V128:{ *:[v4f32] }:$Rn)
44379 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
44380 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44381 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44382 GIR_RootConstrainSelectedInstOperands,
44383 // GIR_Coverage, 4567,
44384 GIR_EraseRootFromParent_Done,
44385 // Label 2652: @124792
44386 GIM_Try, /*On fail goto*//*Label 2653*/ GIMT_Encode4(124828), // Rule ID 4896 //
44387 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
44388 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
44389 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44390 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44391 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44392 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44393 // (intrinsic_wo_chain:{ *:[v1i64] } 647:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn) => (SQNEGv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
44394 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv1i64),
44395 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44396 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44397 GIR_RootConstrainSelectedInstOperands,
44398 // GIR_Coverage, 4896,
44399 GIR_EraseRootFromParent_Done,
44400 // Label 2653: @124828
44401 GIM_Try, /*On fail goto*//*Label 2654*/ GIMT_Encode4(124861), // Rule ID 4901 //
44402 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
44403 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44404 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44405 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44406 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44407 // (intrinsic_wo_chain:{ *:[v1i64] } 566:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTASv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
44408 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1i64),
44409 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44410 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44411 GIR_RootConstrainSelectedInstOperands,
44412 // GIR_Coverage, 4901,
44413 GIR_EraseRootFromParent_Done,
44414 // Label 2654: @124861
44415 GIM_Try, /*On fail goto*//*Label 2655*/ GIMT_Encode4(124894), // Rule ID 4902 //
44416 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
44417 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44418 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44419 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44420 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44421 // (intrinsic_wo_chain:{ *:[v1i64] } 567:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTAUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
44422 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv1i64),
44423 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44424 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44425 GIR_RootConstrainSelectedInstOperands,
44426 // GIR_Coverage, 4902,
44427 GIR_EraseRootFromParent_Done,
44428 // Label 2655: @124894
44429 GIM_Try, /*On fail goto*//*Label 2656*/ GIMT_Encode4(124927), // Rule ID 4903 //
44430 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
44431 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44432 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44433 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44434 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44435 // (intrinsic_wo_chain:{ *:[v1i64] } 568:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTMSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
44436 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv1i64),
44437 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44438 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44439 GIR_RootConstrainSelectedInstOperands,
44440 // GIR_Coverage, 4903,
44441 GIR_EraseRootFromParent_Done,
44442 // Label 2656: @124927
44443 GIM_Try, /*On fail goto*//*Label 2657*/ GIMT_Encode4(124960), // Rule ID 4904 //
44444 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
44445 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44446 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44447 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44448 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44449 // (intrinsic_wo_chain:{ *:[v1i64] } 569:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTMUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
44450 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv1i64),
44451 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44452 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44453 GIR_RootConstrainSelectedInstOperands,
44454 // GIR_Coverage, 4904,
44455 GIR_EraseRootFromParent_Done,
44456 // Label 2657: @124960
44457 GIM_Try, /*On fail goto*//*Label 2658*/ GIMT_Encode4(124993), // Rule ID 4905 //
44458 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
44459 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44460 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44461 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44462 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44463 // (intrinsic_wo_chain:{ *:[v1i64] } 570:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTNSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
44464 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv1i64),
44465 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44466 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44467 GIR_RootConstrainSelectedInstOperands,
44468 // GIR_Coverage, 4905,
44469 GIR_EraseRootFromParent_Done,
44470 // Label 2658: @124993
44471 GIM_Try, /*On fail goto*//*Label 2659*/ GIMT_Encode4(125026), // Rule ID 4906 //
44472 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
44473 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44474 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44475 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44476 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44477 // (intrinsic_wo_chain:{ *:[v1i64] } 571:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTNUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
44478 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv1i64),
44479 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44480 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44481 GIR_RootConstrainSelectedInstOperands,
44482 // GIR_Coverage, 4906,
44483 GIR_EraseRootFromParent_Done,
44484 // Label 2659: @125026
44485 GIM_Try, /*On fail goto*//*Label 2660*/ GIMT_Encode4(125059), // Rule ID 4907 //
44486 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
44487 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44488 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44489 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44490 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44491 // (intrinsic_wo_chain:{ *:[v1i64] } 572:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTPSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
44492 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv1i64),
44493 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44494 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44495 GIR_RootConstrainSelectedInstOperands,
44496 // GIR_Coverage, 4907,
44497 GIR_EraseRootFromParent_Done,
44498 // Label 2660: @125059
44499 GIM_Try, /*On fail goto*//*Label 2661*/ GIMT_Encode4(125092), // Rule ID 4908 //
44500 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
44501 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44502 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44503 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44504 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44505 // (intrinsic_wo_chain:{ *:[v1i64] } 573:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTPUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
44506 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv1i64),
44507 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44508 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44509 GIR_RootConstrainSelectedInstOperands,
44510 // GIR_Coverage, 4908,
44511 GIR_EraseRootFromParent_Done,
44512 // Label 2661: @125092
44513 GIM_Try, /*On fail goto*//*Label 2662*/ GIMT_Encode4(125125), // Rule ID 4909 //
44514 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
44515 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44516 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44517 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44518 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44519 // (intrinsic_wo_chain:{ *:[v1i64] } 575:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTZSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
44520 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i64),
44521 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44522 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44523 GIR_RootConstrainSelectedInstOperands,
44524 // GIR_Coverage, 4909,
44525 GIR_EraseRootFromParent_Done,
44526 // Label 2662: @125125
44527 GIM_Try, /*On fail goto*//*Label 2663*/ GIMT_Encode4(125158), // Rule ID 4910 //
44528 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
44529 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44530 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44531 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44532 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44533 // (intrinsic_wo_chain:{ *:[v1i64] } 576:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FCVTZUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
44534 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i64),
44535 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44536 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44537 GIR_RootConstrainSelectedInstOperands,
44538 // GIR_Coverage, 4910,
44539 GIR_EraseRootFromParent_Done,
44540 // Label 2663: @125158
44541 GIM_Try, /*On fail goto*//*Label 2664*/ GIMT_Encode4(125191), // Rule ID 4911 //
44542 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
44543 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
44544 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
44545 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
44546 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
44547 // (intrinsic_wo_chain:{ *:[f16] } 594:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FRECPEv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
44548 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv1f16),
44549 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44550 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44551 GIR_RootConstrainSelectedInstOperands,
44552 // GIR_Coverage, 4911,
44553 GIR_EraseRootFromParent_Done,
44554 // Label 2664: @125191
44555 GIM_Try, /*On fail goto*//*Label 2665*/ GIMT_Encode4(125224), // Rule ID 4912 //
44556 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
44557 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
44558 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
44559 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
44560 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
44561 // (intrinsic_wo_chain:{ *:[f32] } 594:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRECPEv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
44562 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv1i32),
44563 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44564 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44565 GIR_RootConstrainSelectedInstOperands,
44566 // GIR_Coverage, 4912,
44567 GIR_EraseRootFromParent_Done,
44568 // Label 2665: @125224
44569 GIM_Try, /*On fail goto*//*Label 2666*/ GIMT_Encode4(125257), // Rule ID 4913 //
44570 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
44571 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44572 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44573 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44574 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44575 // (intrinsic_wo_chain:{ *:[f64] } 594:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRECPEv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
44576 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv1i64),
44577 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44578 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44579 GIR_RootConstrainSelectedInstOperands,
44580 // GIR_Coverage, 4913,
44581 GIR_EraseRootFromParent_Done,
44582 // Label 2666: @125257
44583 GIM_Try, /*On fail goto*//*Label 2667*/ GIMT_Encode4(125290), // Rule ID 4914 //
44584 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
44585 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44586 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44587 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44588 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44589 // (intrinsic_wo_chain:{ *:[v1f64] } 594:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FRECPEv1i64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn)
44590 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv1i64),
44591 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44592 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44593 GIR_RootConstrainSelectedInstOperands,
44594 // GIR_Coverage, 4914,
44595 GIR_EraseRootFromParent_Done,
44596 // Label 2667: @125290
44597 GIM_Try, /*On fail goto*//*Label 2668*/ GIMT_Encode4(125323), // Rule ID 4926 //
44598 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpx),
44599 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
44600 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
44601 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
44602 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
44603 // (intrinsic_wo_chain:{ *:[f16] } 596:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FRECPXv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
44604 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPXv1f16),
44605 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44606 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44607 GIR_RootConstrainSelectedInstOperands,
44608 // GIR_Coverage, 4926,
44609 GIR_EraseRootFromParent_Done,
44610 // Label 2668: @125323
44611 GIM_Try, /*On fail goto*//*Label 2669*/ GIMT_Encode4(125356), // Rule ID 4927 //
44612 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpx),
44613 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
44614 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
44615 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
44616 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
44617 // (intrinsic_wo_chain:{ *:[f32] } 596:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRECPXv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
44618 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPXv1i32),
44619 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44620 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44621 GIR_RootConstrainSelectedInstOperands,
44622 // GIR_Coverage, 4927,
44623 GIR_EraseRootFromParent_Done,
44624 // Label 2669: @125356
44625 GIM_Try, /*On fail goto*//*Label 2670*/ GIMT_Encode4(125389), // Rule ID 4928 //
44626 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpx),
44627 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44628 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44629 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44630 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44631 // (intrinsic_wo_chain:{ *:[f64] } 596:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRECPXv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
44632 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPXv1i64),
44633 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44634 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44635 GIR_RootConstrainSelectedInstOperands,
44636 // GIR_Coverage, 4928,
44637 GIR_EraseRootFromParent_Done,
44638 // Label 2670: @125389
44639 GIM_Try, /*On fail goto*//*Label 2671*/ GIMT_Encode4(125422), // Rule ID 4929 //
44640 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
44641 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
44642 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
44643 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
44644 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
44645 // (intrinsic_wo_chain:{ *:[f16] } 601:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn) => (FRSQRTEv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
44646 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv1f16),
44647 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44648 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44649 GIR_RootConstrainSelectedInstOperands,
44650 // GIR_Coverage, 4929,
44651 GIR_EraseRootFromParent_Done,
44652 // Label 2671: @125422
44653 GIM_Try, /*On fail goto*//*Label 2672*/ GIMT_Encode4(125455), // Rule ID 4930 //
44654 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
44655 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
44656 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
44657 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
44658 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
44659 // (intrinsic_wo_chain:{ *:[f32] } 601:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn) => (FRSQRTEv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
44660 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv1i32),
44661 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44662 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44663 GIR_RootConstrainSelectedInstOperands,
44664 // GIR_Coverage, 4930,
44665 GIR_EraseRootFromParent_Done,
44666 // Label 2672: @125455
44667 GIM_Try, /*On fail goto*//*Label 2673*/ GIMT_Encode4(125488), // Rule ID 4931 //
44668 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
44669 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44670 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44671 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44672 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44673 // (intrinsic_wo_chain:{ *:[f64] } 601:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn) => (FRSQRTEv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
44674 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv1i64),
44675 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44676 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44677 GIR_RootConstrainSelectedInstOperands,
44678 // GIR_Coverage, 4931,
44679 GIR_EraseRootFromParent_Done,
44680 // Label 2673: @125488
44681 GIM_Try, /*On fail goto*//*Label 2674*/ GIMT_Encode4(125521), // Rule ID 4932 //
44682 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
44683 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44684 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
44685 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44686 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44687 // (intrinsic_wo_chain:{ *:[v1f64] } 601:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn) => (FRSQRTEv1i64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn)
44688 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv1i64),
44689 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44690 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44691 GIR_RootConstrainSelectedInstOperands,
44692 // GIR_Coverage, 4932,
44693 GIR_EraseRootFromParent_Done,
44694 // Label 2674: @125521
44695 GIM_Try, /*On fail goto*//*Label 2675*/ GIMT_Encode4(125554), // Rule ID 5247 //
44696 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddv),
44697 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
44698 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
44699 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
44700 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44701 // (intrinsic_wo_chain:{ *:[f32] } 565:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FADDPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
44702 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
44703 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44704 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44705 GIR_RootConstrainSelectedInstOperands,
44706 // GIR_Coverage, 5247,
44707 GIR_EraseRootFromParent_Done,
44708 // Label 2675: @125554
44709 GIM_Try, /*On fail goto*//*Label 2676*/ GIMT_Encode4(125639), // Rule ID 5248 //
44710 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddv),
44711 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
44712 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
44713 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
44714 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44715 // (intrinsic_wo_chain:{ *:[f32] } 565:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn) => (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } (FADDPv4f32:{ *:[f128] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rn), dsub:{ *:[i32] }))
44716 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
44717 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
44718 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f32),
44719 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44720 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
44721 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
44722 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44723 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44724 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44725 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
44726 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
44727 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
44728 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
44729 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44730 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44731 GIR_RootConstrainSelectedInstOperands,
44732 // GIR_Coverage, 5248,
44733 GIR_EraseRootFromParent_Done,
44734 // Label 2676: @125639
44735 GIM_Try, /*On fail goto*//*Label 2677*/ GIMT_Encode4(125672), // Rule ID 5249 //
44736 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddv),
44737 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44738 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
44739 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44740 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44741 // (intrinsic_wo_chain:{ *:[f64] } 565:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FADDPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
44742 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i64p),
44743 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44744 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44745 GIR_RootConstrainSelectedInstOperands,
44746 // GIR_Coverage, 5249,
44747 GIR_EraseRootFromParent_Done,
44748 // Label 2677: @125672
44749 GIM_Try, /*On fail goto*//*Label 2678*/ GIMT_Encode4(125705), // Rule ID 5251 //
44750 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmv),
44751 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
44752 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
44753 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
44754 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44755 // (intrinsic_wo_chain:{ *:[f32] } 580:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMAXNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
44756 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv2i32p),
44757 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44758 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44759 GIR_RootConstrainSelectedInstOperands,
44760 // GIR_Coverage, 5251,
44761 GIR_EraseRootFromParent_Done,
44762 // Label 2678: @125705
44763 GIM_Try, /*On fail goto*//*Label 2679*/ GIMT_Encode4(125738), // Rule ID 5253 //
44764 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmv),
44765 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44766 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
44767 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44768 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44769 // (intrinsic_wo_chain:{ *:[f64] } 580:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMAXNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
44770 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv2i64p),
44771 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44772 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44773 GIR_RootConstrainSelectedInstOperands,
44774 // GIR_Coverage, 5253,
44775 GIR_EraseRootFromParent_Done,
44776 // Label 2679: @125738
44777 GIM_Try, /*On fail goto*//*Label 2680*/ GIMT_Encode4(125771), // Rule ID 5255 //
44778 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxv),
44779 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
44780 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
44781 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
44782 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44783 // (intrinsic_wo_chain:{ *:[f32] } 582:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMAXPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
44784 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv2i32p),
44785 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44786 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44787 GIR_RootConstrainSelectedInstOperands,
44788 // GIR_Coverage, 5255,
44789 GIR_EraseRootFromParent_Done,
44790 // Label 2680: @125771
44791 GIM_Try, /*On fail goto*//*Label 2681*/ GIMT_Encode4(125804), // Rule ID 5257 //
44792 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxv),
44793 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44794 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
44795 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44796 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44797 // (intrinsic_wo_chain:{ *:[f64] } 582:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMAXPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
44798 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv2i64p),
44799 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44800 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44801 GIR_RootConstrainSelectedInstOperands,
44802 // GIR_Coverage, 5257,
44803 GIR_EraseRootFromParent_Done,
44804 // Label 2681: @125804
44805 GIM_Try, /*On fail goto*//*Label 2682*/ GIMT_Encode4(125837), // Rule ID 5259 //
44806 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmv),
44807 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
44808 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
44809 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
44810 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44811 // (intrinsic_wo_chain:{ *:[f32] } 586:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMINNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
44812 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv2i32p),
44813 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44814 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44815 GIR_RootConstrainSelectedInstOperands,
44816 // GIR_Coverage, 5259,
44817 GIR_EraseRootFromParent_Done,
44818 // Label 2682: @125837
44819 GIM_Try, /*On fail goto*//*Label 2683*/ GIMT_Encode4(125870), // Rule ID 5261 //
44820 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmv),
44821 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44822 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
44823 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44824 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44825 // (intrinsic_wo_chain:{ *:[f64] } 586:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMINNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
44826 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv2i64p),
44827 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44828 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44829 GIR_RootConstrainSelectedInstOperands,
44830 // GIR_Coverage, 5261,
44831 GIR_EraseRootFromParent_Done,
44832 // Label 2683: @125870
44833 GIM_Try, /*On fail goto*//*Label 2684*/ GIMT_Encode4(125903), // Rule ID 5263 //
44834 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminv),
44835 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
44836 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
44837 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
44838 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44839 // (intrinsic_wo_chain:{ *:[f32] } 588:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn) => (FMINPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
44840 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv2i32p),
44841 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44842 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44843 GIR_RootConstrainSelectedInstOperands,
44844 // GIR_Coverage, 5263,
44845 GIR_EraseRootFromParent_Done,
44846 // Label 2684: @125903
44847 GIM_Try, /*On fail goto*//*Label 2685*/ GIMT_Encode4(125936), // Rule ID 5265 //
44848 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminv),
44849 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44850 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
44851 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44852 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44853 // (intrinsic_wo_chain:{ *:[f64] } 588:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn) => (FMINPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
44854 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv2i64p),
44855 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44856 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
44857 GIR_RootConstrainSelectedInstOperands,
44858 // GIR_Coverage, 5265,
44859 GIR_EraseRootFromParent_Done,
44860 // Label 2685: @125936
44861 GIM_Try, /*On fail goto*//*Label 2686*/ GIMT_Encode4(126041), // Rule ID 5610 //
44862 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlv),
44863 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
44864 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
44865 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
44866 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44867 // (intrinsic_wo_chain:{ *:[i32] } 623:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
44868 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
44869 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
44870 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
44871 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i8v),
44872 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44873 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
44874 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44875 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44876 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44877 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44878 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
44879 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44880 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44881 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
44882 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
44883 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
44884 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
44885 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
44886 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
44887 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44888 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44889 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44890 GIR_RootConstrainSelectedInstOperands,
44891 // GIR_Coverage, 5610,
44892 GIR_EraseRootFromParent_Done,
44893 // Label 2686: @126041
44894 GIM_Try, /*On fail goto*//*Label 2687*/ GIMT_Encode4(126146), // Rule ID 5611 //
44895 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlv),
44896 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
44897 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
44898 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
44899 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44900 // (intrinsic_wo_chain:{ *:[i32] } 623:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
44901 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
44902 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
44903 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
44904 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv16i8v),
44905 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44906 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
44907 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44908 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44909 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44910 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44911 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
44912 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44913 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44914 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
44915 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
44916 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
44917 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
44918 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
44919 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
44920 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
44921 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44922 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44923 GIR_RootConstrainSelectedInstOperands,
44924 // GIR_Coverage, 5611,
44925 GIR_EraseRootFromParent_Done,
44926 // Label 2687: @126146
44927 GIM_Try, /*On fail goto*//*Label 2688*/ GIMT_Encode4(126261), // Rule ID 5612 //
44928 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlv),
44929 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
44930 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
44931 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44932 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
44933 // (intrinsic_wo_chain:{ *:[i32] } 623:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
44934 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
44935 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
44936 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
44937 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i16v),
44938 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44939 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
44940 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44941 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44942 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44943 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44944 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
44945 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44946 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44947 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
44948 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
44949 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
44950 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
44951 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
44952 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44953 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44954 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
44955 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
44956 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
44957 // GIR_Coverage, 5612,
44958 GIR_EraseRootFromParent_Done,
44959 // Label 2688: @126261
44960 GIM_Try, /*On fail goto*//*Label 2689*/ GIMT_Encode4(126376), // Rule ID 5613 //
44961 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlv),
44962 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
44963 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
44964 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44965 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44966 // (intrinsic_wo_chain:{ *:[i32] } 623:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
44967 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
44968 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
44969 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
44970 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i16v),
44971 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44972 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
44973 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44974 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44975 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44976 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44977 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
44978 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
44979 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44980 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
44981 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
44982 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
44983 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
44984 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
44985 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44986 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44987 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
44988 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
44989 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
44990 // GIR_Coverage, 5613,
44991 GIR_EraseRootFromParent_Done,
44992 // Label 2689: @126376
44993 GIM_Try, /*On fail goto*//*Label 2690*/ GIMT_Encode4(126491), // Rule ID 5614 //
44994 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlv),
44995 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
44996 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
44997 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44998 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
44999 // (intrinsic_wo_chain:{ *:[i64] } 623:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i64] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn), dsub:{ *:[i32] }), dsub:{ *:[i32] })
45000 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
45001 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
45002 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
45003 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i32v),
45004 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45005 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45006 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45007 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45008 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45009 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45010 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45011 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45012 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45013 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45014 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
45015 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45016 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45017 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
45018 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45019 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45020 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
45021 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
45022 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45023 // GIR_Coverage, 5614,
45024 GIR_EraseRootFromParent_Done,
45025 // Label 2690: @126491
45026 GIM_Try, /*On fail goto*//*Label 2691*/ GIMT_Encode4(126606), // Rule ID 5615 //
45027 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlv),
45028 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
45029 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
45030 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45031 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45032 // (intrinsic_wo_chain:{ *:[i32] } 688:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] })
45033 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
45034 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
45035 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
45036 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i8v),
45037 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45038 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45039 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45040 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45041 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45042 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45043 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45044 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45045 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45046 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45047 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
45048 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45049 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45050 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
45051 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45052 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45053 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
45054 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
45055 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45056 // GIR_Coverage, 5615,
45057 GIR_EraseRootFromParent_Done,
45058 // Label 2691: @126606
45059 GIM_Try, /*On fail goto*//*Label 2692*/ GIMT_Encode4(126721), // Rule ID 5616 //
45060 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlv),
45061 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
45062 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
45063 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45064 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45065 // (intrinsic_wo_chain:{ *:[i32] } 688:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] })
45066 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
45067 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
45068 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
45069 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv16i8v),
45070 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45071 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45072 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45073 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45074 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45075 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45076 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45077 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45078 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45079 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45080 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
45081 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45082 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45083 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
45084 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45085 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45086 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
45087 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
45088 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45089 // GIR_Coverage, 5616,
45090 GIR_EraseRootFromParent_Done,
45091 // Label 2692: @126721
45092 GIM_Try, /*On fail goto*//*Label 2693*/ GIMT_Encode4(126836), // Rule ID 5617 //
45093 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlv),
45094 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
45095 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
45096 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45097 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45098 // (intrinsic_wo_chain:{ *:[i32] } 688:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
45099 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
45100 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
45101 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
45102 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i16v),
45103 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45104 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45105 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45106 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45107 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45108 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45109 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45110 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45111 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45112 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45113 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
45114 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45115 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45116 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
45117 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45118 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45119 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
45120 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
45121 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45122 // GIR_Coverage, 5617,
45123 GIR_EraseRootFromParent_Done,
45124 // Label 2693: @126836
45125 GIM_Try, /*On fail goto*//*Label 2694*/ GIMT_Encode4(126951), // Rule ID 5618 //
45126 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlv),
45127 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
45128 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
45129 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45130 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45131 // (intrinsic_wo_chain:{ *:[i32] } 688:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
45132 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
45133 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
45134 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
45135 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i16v),
45136 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45137 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45138 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45139 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45140 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45141 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45142 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45143 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45144 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45145 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45146 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
45147 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45148 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45149 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
45150 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45151 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45152 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
45153 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
45154 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45155 // GIR_Coverage, 5618,
45156 GIR_EraseRootFromParent_Done,
45157 // Label 2694: @126951
45158 GIM_Try, /*On fail goto*//*Label 2695*/ GIMT_Encode4(127066), // Rule ID 5619 //
45159 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlv),
45160 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
45161 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
45162 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45163 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45164 // (intrinsic_wo_chain:{ *:[i64] } 688:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i64] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn), dsub:{ *:[i32] }), dsub:{ *:[i32] })
45165 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
45166 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
45167 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
45168 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i32v),
45169 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45170 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45171 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45172 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45173 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45174 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45175 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45176 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45177 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45178 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45179 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
45180 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45181 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45182 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
45183 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45184 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45185 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
45186 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
45187 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45188 // GIR_Coverage, 5619,
45189 GIR_EraseRootFromParent_Done,
45190 // Label 2695: @127066
45191 GIM_Try, /*On fail goto*//*Label 2696*/ GIMT_Encode4(127181), // Rule ID 5620 //
45192 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlv),
45193 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
45194 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
45195 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45196 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45197 // (intrinsic_wo_chain:{ *:[i64] } 623:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i64] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SADDLPv2i32_v1i64:{ *:[i64] } V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), dsub:{ *:[i32] })
45198 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
45199 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
45200 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
45201 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv2i32_v1i64),
45202 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45203 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45204 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45205 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45206 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45207 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45208 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45209 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45210 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45211 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45212 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
45213 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45214 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45215 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
45216 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45217 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45218 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
45219 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
45220 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45221 // GIR_Coverage, 5620,
45222 GIR_EraseRootFromParent_Done,
45223 // Label 2696: @127181
45224 GIM_Try, /*On fail goto*//*Label 2697*/ GIMT_Encode4(127296), // Rule ID 5621 //
45225 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlv),
45226 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
45227 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
45228 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45229 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45230 // (intrinsic_wo_chain:{ *:[i64] } 688:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i64] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UADDLPv2i32_v1i64:{ *:[i64] } V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), dsub:{ *:[i32] })
45231 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
45232 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
45233 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
45234 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv2i32_v1i64),
45235 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45236 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45237 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45238 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45239 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45240 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45241 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45242 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45243 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45244 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45245 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
45246 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45247 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45248 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
45249 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45250 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45251 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
45252 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
45253 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45254 // GIR_Coverage, 5621,
45255 GIR_EraseRootFromParent_Done,
45256 // Label 2697: @127296
45257 GIM_Try, /*On fail goto*//*Label 2698*/ GIMT_Encode4(127329), // Rule ID 12371 //
45258 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
45259 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
45260 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
45261 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
45262 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45263 // (intrinsic_wo_chain:{ *:[i8] } 624:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (ADDVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
45264 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i8v),
45265 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45266 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45267 GIR_RootConstrainSelectedInstOperands,
45268 // GIR_Coverage, 12371,
45269 GIR_EraseRootFromParent_Done,
45270 // Label 2698: @127329
45271 GIM_Try, /*On fail goto*//*Label 2699*/ GIMT_Encode4(127362), // Rule ID 12373 //
45272 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
45273 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
45274 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
45275 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
45276 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45277 // (intrinsic_wo_chain:{ *:[i8] } 624:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (ADDVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
45278 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv16i8v),
45279 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45280 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45281 GIR_RootConstrainSelectedInstOperands,
45282 // GIR_Coverage, 12373,
45283 GIR_EraseRootFromParent_Done,
45284 // Label 2699: @127362
45285 GIM_Try, /*On fail goto*//*Label 2700*/ GIMT_Encode4(127395), // Rule ID 12375 //
45286 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
45287 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
45288 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
45289 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
45290 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45291 // (intrinsic_wo_chain:{ *:[i16] } 624:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (ADDVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
45292 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i16v),
45293 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45294 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45295 GIR_RootConstrainSelectedInstOperands,
45296 // GIR_Coverage, 12375,
45297 GIR_EraseRootFromParent_Done,
45298 // Label 2700: @127395
45299 GIM_Try, /*On fail goto*//*Label 2701*/ GIMT_Encode4(127428), // Rule ID 12377 //
45300 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
45301 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
45302 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
45303 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
45304 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45305 // (intrinsic_wo_chain:{ *:[i16] } 624:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (ADDVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
45306 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i16v),
45307 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45308 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45309 GIR_RootConstrainSelectedInstOperands,
45310 // GIR_Coverage, 12377,
45311 GIR_EraseRootFromParent_Done,
45312 // Label 2701: @127428
45313 GIM_Try, /*On fail goto*//*Label 2702*/ GIMT_Encode4(127543), // Rule ID 12378 //
45314 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
45315 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
45316 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
45317 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45318 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45319 // (intrinsic_wo_chain:{ *:[i32] } 624:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
45320 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
45321 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
45322 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
45323 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i32v),
45324 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45325 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45326 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45327 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45328 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45329 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45330 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45331 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45332 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45333 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45334 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
45335 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45336 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45337 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
45338 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45339 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45340 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
45341 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
45342 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45343 // GIR_Coverage, 12378,
45344 GIR_EraseRootFromParent_Done,
45345 // Label 2702: @127543
45346 GIM_Try, /*On fail goto*//*Label 2703*/ GIMT_Encode4(127576), // Rule ID 12380 //
45347 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
45348 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
45349 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
45350 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
45351 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45352 // (intrinsic_wo_chain:{ *:[i8] } 689:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (ADDVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
45353 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i8v),
45354 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45355 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45356 GIR_RootConstrainSelectedInstOperands,
45357 // GIR_Coverage, 12380,
45358 GIR_EraseRootFromParent_Done,
45359 // Label 2703: @127576
45360 GIM_Try, /*On fail goto*//*Label 2704*/ GIMT_Encode4(127609), // Rule ID 12382 //
45361 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
45362 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
45363 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
45364 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
45365 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45366 // (intrinsic_wo_chain:{ *:[i8] } 689:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (ADDVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
45367 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv16i8v),
45368 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45369 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45370 GIR_RootConstrainSelectedInstOperands,
45371 // GIR_Coverage, 12382,
45372 GIR_EraseRootFromParent_Done,
45373 // Label 2704: @127609
45374 GIM_Try, /*On fail goto*//*Label 2705*/ GIMT_Encode4(127642), // Rule ID 12384 //
45375 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
45376 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
45377 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
45378 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
45379 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45380 // (intrinsic_wo_chain:{ *:[i16] } 689:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (ADDVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
45381 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i16v),
45382 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45383 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45384 GIR_RootConstrainSelectedInstOperands,
45385 // GIR_Coverage, 12384,
45386 GIR_EraseRootFromParent_Done,
45387 // Label 2705: @127642
45388 GIM_Try, /*On fail goto*//*Label 2706*/ GIMT_Encode4(127675), // Rule ID 12386 //
45389 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
45390 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
45391 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
45392 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
45393 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45394 // (intrinsic_wo_chain:{ *:[i16] } 689:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (ADDVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
45395 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i16v),
45396 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45397 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45398 GIR_RootConstrainSelectedInstOperands,
45399 // GIR_Coverage, 12386,
45400 GIR_EraseRootFromParent_Done,
45401 // Label 2706: @127675
45402 GIM_Try, /*On fail goto*//*Label 2707*/ GIMT_Encode4(127790), // Rule ID 12387 //
45403 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
45404 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
45405 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
45406 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45407 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45408 // (intrinsic_wo_chain:{ *:[i32] } 689:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
45409 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
45410 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
45411 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
45412 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i32v),
45413 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45414 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45415 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45416 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45417 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45418 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45419 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45420 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45421 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45422 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45423 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
45424 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45425 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45426 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
45427 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45428 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45429 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
45430 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
45431 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45432 // GIR_Coverage, 12387,
45433 GIR_EraseRootFromParent_Done,
45434 // Label 2707: @127790
45435 GIM_Try, /*On fail goto*//*Label 2708*/ GIMT_Encode4(127909), // Rule ID 12388 //
45436 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
45437 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
45438 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
45439 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45440 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45441 // (intrinsic_wo_chain:{ *:[i32] } 624:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), ssub:{ *:[i32] })
45442 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
45443 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
45444 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
45445 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i32),
45446 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45447 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45448 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45449 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45450 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45451 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45452 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45453 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45454 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45455 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45456 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45457 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
45458 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45459 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45460 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
45461 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45462 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45463 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
45464 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
45465 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45466 // GIR_Coverage, 12388,
45467 GIR_EraseRootFromParent_Done,
45468 // Label 2708: @127909
45469 GIM_Try, /*On fail goto*//*Label 2709*/ GIMT_Encode4(128024), // Rule ID 12389 //
45470 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
45471 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
45472 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
45473 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45474 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45475 // (intrinsic_wo_chain:{ *:[i64] } 624:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (EXTRACT_SUBREG:{ *:[i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), (ADDPv2i64p:{ *:[i64] } V128:{ *:[v2i64] }:$Rn), dsub:{ *:[i32] }), dsub:{ *:[i32] })
45476 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
45477 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
45478 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
45479 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64p),
45480 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45481 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45482 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45483 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45484 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45485 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45486 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45487 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45488 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45489 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45490 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
45491 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45492 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45493 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
45494 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45495 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45496 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
45497 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
45498 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45499 // GIR_Coverage, 12389,
45500 GIR_EraseRootFromParent_Done,
45501 // Label 2709: @128024
45502 GIM_Try, /*On fail goto*//*Label 2710*/ GIMT_Encode4(128143), // Rule ID 12390 //
45503 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
45504 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
45505 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
45506 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45507 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45508 // (intrinsic_wo_chain:{ *:[i32] } 689:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), ssub:{ *:[i32] })
45509 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
45510 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
45511 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
45512 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i32),
45513 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45514 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45515 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45516 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45517 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45518 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45519 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45520 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45521 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45522 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45523 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45524 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
45525 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45526 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45527 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
45528 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45529 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45530 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
45531 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
45532 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45533 // GIR_Coverage, 12390,
45534 GIR_EraseRootFromParent_Done,
45535 // Label 2710: @128143
45536 GIM_Try, /*On fail goto*//*Label 2711*/ GIMT_Encode4(128258), // Rule ID 12391 //
45537 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
45538 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
45539 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
45540 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45541 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45542 // (intrinsic_wo_chain:{ *:[i64] } 689:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn) => (EXTRACT_SUBREG:{ *:[i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), (ADDPv2i64p:{ *:[i64] } V128:{ *:[v2i64] }:$Rn), dsub:{ *:[i32] }), dsub:{ *:[i32] })
45543 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
45544 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
45545 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
45546 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64p),
45547 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45548 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45549 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45550 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45551 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45552 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45553 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45554 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45555 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45556 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45557 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
45558 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45559 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45560 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
45561 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45562 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45563 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
45564 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
45565 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45566 // GIR_Coverage, 12391,
45567 GIR_EraseRootFromParent_Done,
45568 // Label 2711: @128258
45569 GIM_Try, /*On fail goto*//*Label 2712*/ GIMT_Encode4(128291), // Rule ID 12393 //
45570 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
45571 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
45572 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
45573 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
45574 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45575 // (intrinsic_wo_chain:{ *:[i8] } 634:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SMAXVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
45576 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv8i8v),
45577 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45578 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45579 GIR_RootConstrainSelectedInstOperands,
45580 // GIR_Coverage, 12393,
45581 GIR_EraseRootFromParent_Done,
45582 // Label 2712: @128291
45583 GIM_Try, /*On fail goto*//*Label 2713*/ GIMT_Encode4(128324), // Rule ID 12395 //
45584 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
45585 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
45586 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
45587 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
45588 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45589 // (intrinsic_wo_chain:{ *:[i8] } 634:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SMAXVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
45590 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv16i8v),
45591 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45592 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45593 GIR_RootConstrainSelectedInstOperands,
45594 // GIR_Coverage, 12395,
45595 GIR_EraseRootFromParent_Done,
45596 // Label 2713: @128324
45597 GIM_Try, /*On fail goto*//*Label 2714*/ GIMT_Encode4(128357), // Rule ID 12397 //
45598 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
45599 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
45600 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
45601 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
45602 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45603 // (intrinsic_wo_chain:{ *:[i16] } 634:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (SMAXVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
45604 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv4i16v),
45605 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45606 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45607 GIR_RootConstrainSelectedInstOperands,
45608 // GIR_Coverage, 12397,
45609 GIR_EraseRootFromParent_Done,
45610 // Label 2714: @128357
45611 GIM_Try, /*On fail goto*//*Label 2715*/ GIMT_Encode4(128390), // Rule ID 12399 //
45612 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
45613 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
45614 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
45615 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
45616 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45617 // (intrinsic_wo_chain:{ *:[i16] } 634:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SMAXVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
45618 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv8i16v),
45619 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45620 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45621 GIR_RootConstrainSelectedInstOperands,
45622 // GIR_Coverage, 12399,
45623 GIR_EraseRootFromParent_Done,
45624 // Label 2715: @128390
45625 GIM_Try, /*On fail goto*//*Label 2716*/ GIMT_Encode4(128505), // Rule ID 12400 //
45626 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
45627 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
45628 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
45629 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45630 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45631 // (intrinsic_wo_chain:{ *:[i32] } 634:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMAXVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
45632 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
45633 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
45634 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
45635 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv4i32v),
45636 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45637 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45638 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45639 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45640 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45641 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45642 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45643 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45644 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45645 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45646 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
45647 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45648 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45649 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
45650 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45651 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45652 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
45653 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
45654 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45655 // GIR_Coverage, 12400,
45656 GIR_EraseRootFromParent_Done,
45657 // Label 2716: @128505
45658 GIM_Try, /*On fail goto*//*Label 2717*/ GIMT_Encode4(128624), // Rule ID 12401 //
45659 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
45660 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
45661 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
45662 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45663 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45664 // (intrinsic_wo_chain:{ *:[i32] } 634:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMAXPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), ssub:{ *:[i32] })
45665 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
45666 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
45667 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
45668 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv2i32),
45669 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45670 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45671 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45672 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45673 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45674 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45675 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45676 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45677 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45678 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45679 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45680 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
45681 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45682 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45683 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
45684 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45685 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45686 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
45687 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
45688 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45689 // GIR_Coverage, 12401,
45690 GIR_EraseRootFromParent_Done,
45691 // Label 2717: @128624
45692 GIM_Try, /*On fail goto*//*Label 2718*/ GIMT_Encode4(128657), // Rule ID 12403 //
45693 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
45694 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
45695 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
45696 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
45697 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45698 // (intrinsic_wo_chain:{ *:[i8] } 637:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (SMINVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
45699 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINVv8i8v),
45700 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45701 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45702 GIR_RootConstrainSelectedInstOperands,
45703 // GIR_Coverage, 12403,
45704 GIR_EraseRootFromParent_Done,
45705 // Label 2718: @128657
45706 GIM_Try, /*On fail goto*//*Label 2719*/ GIMT_Encode4(128690), // Rule ID 12405 //
45707 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
45708 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
45709 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
45710 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
45711 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45712 // (intrinsic_wo_chain:{ *:[i8] } 637:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (SMINVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
45713 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINVv16i8v),
45714 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45715 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45716 GIR_RootConstrainSelectedInstOperands,
45717 // GIR_Coverage, 12405,
45718 GIR_EraseRootFromParent_Done,
45719 // Label 2719: @128690
45720 GIM_Try, /*On fail goto*//*Label 2720*/ GIMT_Encode4(128723), // Rule ID 12407 //
45721 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
45722 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
45723 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
45724 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
45725 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45726 // (intrinsic_wo_chain:{ *:[i16] } 637:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (SMINVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
45727 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINVv4i16v),
45728 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45729 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45730 GIR_RootConstrainSelectedInstOperands,
45731 // GIR_Coverage, 12407,
45732 GIR_EraseRootFromParent_Done,
45733 // Label 2720: @128723
45734 GIM_Try, /*On fail goto*//*Label 2721*/ GIMT_Encode4(128756), // Rule ID 12409 //
45735 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
45736 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
45737 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
45738 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
45739 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45740 // (intrinsic_wo_chain:{ *:[i16] } 637:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (SMINVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
45741 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINVv8i16v),
45742 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45743 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45744 GIR_RootConstrainSelectedInstOperands,
45745 // GIR_Coverage, 12409,
45746 GIR_EraseRootFromParent_Done,
45747 // Label 2721: @128756
45748 GIM_Try, /*On fail goto*//*Label 2722*/ GIMT_Encode4(128871), // Rule ID 12410 //
45749 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
45750 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
45751 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
45752 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45753 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45754 // (intrinsic_wo_chain:{ *:[i32] } 637:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMINVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
45755 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
45756 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
45757 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
45758 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMINVv4i32v),
45759 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45760 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45761 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45762 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45763 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45764 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45765 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45766 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45767 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45768 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45769 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
45770 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45771 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45772 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
45773 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45774 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45775 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
45776 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
45777 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45778 // GIR_Coverage, 12410,
45779 GIR_EraseRootFromParent_Done,
45780 // Label 2722: @128871
45781 GIM_Try, /*On fail goto*//*Label 2723*/ GIMT_Encode4(128990), // Rule ID 12411 //
45782 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
45783 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
45784 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
45785 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45786 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45787 // (intrinsic_wo_chain:{ *:[i32] } 637:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMINPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), ssub:{ *:[i32] })
45788 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
45789 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
45790 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
45791 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMINPv2i32),
45792 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45793 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45794 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45795 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45796 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45797 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45798 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45799 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45800 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45801 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45802 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45803 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
45804 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45805 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45806 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
45807 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45808 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45809 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
45810 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
45811 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45812 // GIR_Coverage, 12411,
45813 GIR_EraseRootFromParent_Done,
45814 // Label 2723: @128990
45815 GIM_Try, /*On fail goto*//*Label 2724*/ GIMT_Encode4(129023), // Rule ID 12413 //
45816 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
45817 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
45818 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
45819 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
45820 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45821 // (intrinsic_wo_chain:{ *:[i8] } 695:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (UMAXVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
45822 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv8i8v),
45823 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45824 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45825 GIR_RootConstrainSelectedInstOperands,
45826 // GIR_Coverage, 12413,
45827 GIR_EraseRootFromParent_Done,
45828 // Label 2724: @129023
45829 GIM_Try, /*On fail goto*//*Label 2725*/ GIMT_Encode4(129056), // Rule ID 12415 //
45830 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
45831 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
45832 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
45833 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
45834 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45835 // (intrinsic_wo_chain:{ *:[i8] } 695:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (UMAXVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
45836 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv16i8v),
45837 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45838 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45839 GIR_RootConstrainSelectedInstOperands,
45840 // GIR_Coverage, 12415,
45841 GIR_EraseRootFromParent_Done,
45842 // Label 2725: @129056
45843 GIM_Try, /*On fail goto*//*Label 2726*/ GIMT_Encode4(129089), // Rule ID 12417 //
45844 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
45845 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
45846 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
45847 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
45848 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45849 // (intrinsic_wo_chain:{ *:[i16] } 695:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (UMAXVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
45850 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv4i16v),
45851 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45852 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45853 GIR_RootConstrainSelectedInstOperands,
45854 // GIR_Coverage, 12417,
45855 GIR_EraseRootFromParent_Done,
45856 // Label 2726: @129089
45857 GIM_Try, /*On fail goto*//*Label 2727*/ GIMT_Encode4(129122), // Rule ID 12419 //
45858 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
45859 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
45860 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
45861 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
45862 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45863 // (intrinsic_wo_chain:{ *:[i16] } 695:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (UMAXVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
45864 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv8i16v),
45865 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45866 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45867 GIR_RootConstrainSelectedInstOperands,
45868 // GIR_Coverage, 12419,
45869 GIR_EraseRootFromParent_Done,
45870 // Label 2727: @129122
45871 GIM_Try, /*On fail goto*//*Label 2728*/ GIMT_Encode4(129237), // Rule ID 12420 //
45872 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
45873 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
45874 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
45875 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45876 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45877 // (intrinsic_wo_chain:{ *:[i32] } 695:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMAXVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
45878 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
45879 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
45880 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
45881 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv4i32v),
45882 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45883 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45884 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45885 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45886 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45887 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45888 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45889 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45890 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45891 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45892 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
45893 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45894 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45895 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
45896 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45897 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45898 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
45899 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
45900 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45901 // GIR_Coverage, 12420,
45902 GIR_EraseRootFromParent_Done,
45903 // Label 2728: @129237
45904 GIM_Try, /*On fail goto*//*Label 2729*/ GIMT_Encode4(129356), // Rule ID 12421 //
45905 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
45906 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
45907 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
45908 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45909 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45910 // (intrinsic_wo_chain:{ *:[i32] } 695:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMAXPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), ssub:{ *:[i32] })
45911 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
45912 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
45913 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
45914 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv2i32),
45915 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45916 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45917 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
45918 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45919 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45920 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45921 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45922 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45923 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
45924 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45925 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
45926 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
45927 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
45928 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45929 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
45930 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45931 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45932 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
45933 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
45934 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
45935 // GIR_Coverage, 12421,
45936 GIR_EraseRootFromParent_Done,
45937 // Label 2729: @129356
45938 GIM_Try, /*On fail goto*//*Label 2730*/ GIMT_Encode4(129389), // Rule ID 12423 //
45939 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
45940 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
45941 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
45942 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
45943 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45944 // (intrinsic_wo_chain:{ *:[i8] } 698:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn) => (UMINVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
45945 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINVv8i8v),
45946 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45947 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45948 GIR_RootConstrainSelectedInstOperands,
45949 // GIR_Coverage, 12423,
45950 GIR_EraseRootFromParent_Done,
45951 // Label 2730: @129389
45952 GIM_Try, /*On fail goto*//*Label 2731*/ GIMT_Encode4(129422), // Rule ID 12425 //
45953 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
45954 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
45955 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
45956 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
45957 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45958 // (intrinsic_wo_chain:{ *:[i8] } 698:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn) => (UMINVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
45959 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINVv16i8v),
45960 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45961 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45962 GIR_RootConstrainSelectedInstOperands,
45963 // GIR_Coverage, 12425,
45964 GIR_EraseRootFromParent_Done,
45965 // Label 2731: @129422
45966 GIM_Try, /*On fail goto*//*Label 2732*/ GIMT_Encode4(129455), // Rule ID 12427 //
45967 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
45968 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
45969 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
45970 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
45971 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
45972 // (intrinsic_wo_chain:{ *:[i16] } 698:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn) => (UMINVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
45973 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINVv4i16v),
45974 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45975 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45976 GIR_RootConstrainSelectedInstOperands,
45977 // GIR_Coverage, 12427,
45978 GIR_EraseRootFromParent_Done,
45979 // Label 2732: @129455
45980 GIM_Try, /*On fail goto*//*Label 2733*/ GIMT_Encode4(129488), // Rule ID 12429 //
45981 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
45982 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
45983 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
45984 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
45985 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45986 // (intrinsic_wo_chain:{ *:[i16] } 698:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn) => (UMINVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
45987 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINVv8i16v),
45988 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45989 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
45990 GIR_RootConstrainSelectedInstOperands,
45991 // GIR_Coverage, 12429,
45992 GIR_EraseRootFromParent_Done,
45993 // Label 2733: @129488
45994 GIM_Try, /*On fail goto*//*Label 2734*/ GIMT_Encode4(129603), // Rule ID 12430 //
45995 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
45996 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
45997 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
45998 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
45999 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
46000 // (intrinsic_wo_chain:{ *:[i32] } 698:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMINVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
46001 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
46002 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
46003 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
46004 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::UMINVv4i32v),
46005 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46006 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
46007 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46008 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46009 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46010 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46011 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46012 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46013 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
46014 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
46015 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
46016 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
46017 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
46018 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
46019 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46020 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46021 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
46022 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
46023 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
46024 // GIR_Coverage, 12430,
46025 GIR_EraseRootFromParent_Done,
46026 // Label 2734: @129603
46027 GIM_Try, /*On fail goto*//*Label 2735*/ GIMT_Encode4(129722), // Rule ID 12431 //
46028 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
46029 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
46030 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
46031 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
46032 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
46033 // (intrinsic_wo_chain:{ *:[i32] } 698:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMINPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), ssub:{ *:[i32] })
46034 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
46035 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
46036 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
46037 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::UMINPv2i32),
46038 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46039 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
46040 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
46041 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46042 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46043 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46044 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46045 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46046 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46047 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
46048 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
46049 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
46050 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
46051 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
46052 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
46053 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46054 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46055 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
46056 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
46057 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
46058 // GIR_Coverage, 12431,
46059 GIR_EraseRootFromParent_Done,
46060 // Label 2735: @129722
46061 GIM_Try, /*On fail goto*//*Label 2736*/ GIMT_Encode4(129754), // Rule ID 2333 //
46062 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
46063 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rev_b16),
46064 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
46065 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
46066 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
46067 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1450:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn) => (REV_PP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn)
46068 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV_PP_H),
46069 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
46070 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
46071 GIR_RootConstrainSelectedInstOperands,
46072 // GIR_Coverage, 2333,
46073 GIR_EraseRootFromParent_Done,
46074 // Label 2736: @129754
46075 GIM_Try, /*On fail goto*//*Label 2737*/ GIMT_Encode4(129786), // Rule ID 2334 //
46076 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
46077 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rev_b32),
46078 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
46079 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
46080 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
46081 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1451:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn) => (REV_PP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn)
46082 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV_PP_S),
46083 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
46084 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
46085 GIR_RootConstrainSelectedInstOperands,
46086 // GIR_Coverage, 2334,
46087 GIR_EraseRootFromParent_Done,
46088 // Label 2737: @129786
46089 GIM_Try, /*On fail goto*//*Label 2738*/ GIMT_Encode4(129818), // Rule ID 2335 //
46090 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
46091 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rev_b64),
46092 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
46093 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
46094 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
46095 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1452:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn) => (REV_PP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn)
46096 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV_PP_D),
46097 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
46098 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
46099 GIR_RootConstrainSelectedInstOperands,
46100 // GIR_Coverage, 2335,
46101 GIR_EraseRootFromParent_Done,
46102 // Label 2738: @129818
46103 GIM_Try, /*On fail goto*//*Label 2739*/ GIMT_Encode4(129850), // Rule ID 3018 //
46104 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
46105 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtnb),
46106 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
46107 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
46108 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
46109 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1632:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1) => (SQXTNB_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1)
46110 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNB_ZZ_B),
46111 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
46112 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46113 GIR_RootConstrainSelectedInstOperands,
46114 // GIR_Coverage, 3018,
46115 GIR_EraseRootFromParent_Done,
46116 // Label 2739: @129850
46117 GIM_Try, /*On fail goto*//*Label 2740*/ GIMT_Encode4(129882), // Rule ID 3019 //
46118 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
46119 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtnb),
46120 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
46121 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
46122 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
46123 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1632:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1) => (SQXTNB_ZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1)
46124 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNB_ZZ_H),
46125 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
46126 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46127 GIR_RootConstrainSelectedInstOperands,
46128 // GIR_Coverage, 3019,
46129 GIR_EraseRootFromParent_Done,
46130 // Label 2740: @129882
46131 GIM_Try, /*On fail goto*//*Label 2741*/ GIMT_Encode4(129914), // Rule ID 3020 //
46132 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
46133 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtnb),
46134 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
46135 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
46136 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
46137 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1632:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1) => (SQXTNB_ZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1)
46138 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNB_ZZ_S),
46139 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
46140 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46141 GIR_RootConstrainSelectedInstOperands,
46142 // GIR_Coverage, 3020,
46143 GIR_EraseRootFromParent_Done,
46144 // Label 2741: @129914
46145 GIM_Try, /*On fail goto*//*Label 2742*/ GIMT_Encode4(129946), // Rule ID 3260 //
46146 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
46147 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_punpklo),
46148 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
46149 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
46150 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
46151 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1442:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1) => (PUNPKLO_PP:{ *:[nxv8i1] } ?:{ *:[nxv16i1] }:$Op1)
46152 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
46153 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
46154 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46155 GIR_RootConstrainSelectedInstOperands,
46156 // GIR_Coverage, 3260,
46157 GIR_EraseRootFromParent_Done,
46158 // Label 2742: @129946
46159 GIM_Try, /*On fail goto*//*Label 2743*/ GIMT_Encode4(129978), // Rule ID 3261 //
46160 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
46161 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_punpklo),
46162 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
46163 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
46164 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
46165 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1442:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1) => (PUNPKLO_PP:{ *:[nxv4i1] } ?:{ *:[nxv8i1] }:$Op1)
46166 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
46167 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
46168 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46169 GIR_RootConstrainSelectedInstOperands,
46170 // GIR_Coverage, 3261,
46171 GIR_EraseRootFromParent_Done,
46172 // Label 2743: @129978
46173 GIM_Try, /*On fail goto*//*Label 2744*/ GIMT_Encode4(130010), // Rule ID 3262 //
46174 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
46175 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_punpklo),
46176 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
46177 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
46178 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
46179 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1442:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1) => (PUNPKLO_PP:{ *:[nxv2i1] } ?:{ *:[nxv4i1] }:$Op1)
46180 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
46181 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
46182 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46183 GIR_RootConstrainSelectedInstOperands,
46184 // GIR_Coverage, 3262,
46185 GIR_EraseRootFromParent_Done,
46186 // Label 2744: @130010
46187 GIM_Try, /*On fail goto*//*Label 2745*/ GIMT_Encode4(130042), // Rule ID 3341 //
46188 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
46189 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fexpa_x),
46190 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
46191 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
46192 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
46193 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1234:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1) => (FEXPA_ZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i16] }:$Op1)
46194 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FEXPA_ZZ_H),
46195 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
46196 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46197 GIR_RootConstrainSelectedInstOperands,
46198 // GIR_Coverage, 3341,
46199 GIR_EraseRootFromParent_Done,
46200 // Label 2745: @130042
46201 GIM_Try, /*On fail goto*//*Label 2746*/ GIMT_Encode4(130074), // Rule ID 3342 //
46202 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
46203 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fexpa_x),
46204 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
46205 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
46206 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
46207 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1234:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1) => (FEXPA_ZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i32] }:$Op1)
46208 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FEXPA_ZZ_S),
46209 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
46210 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46211 GIR_RootConstrainSelectedInstOperands,
46212 // GIR_Coverage, 3342,
46213 GIR_EraseRootFromParent_Done,
46214 // Label 2746: @130074
46215 GIM_Try, /*On fail goto*//*Label 2747*/ GIMT_Encode4(130106), // Rule ID 3343 //
46216 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
46217 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fexpa_x),
46218 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
46219 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
46220 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
46221 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1234:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1) => (FEXPA_ZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i64] }:$Op1)
46222 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FEXPA_ZZ_D),
46223 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
46224 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46225 GIR_RootConstrainSelectedInstOperands,
46226 // GIR_Coverage, 3343,
46227 GIR_EraseRootFromParent_Done,
46228 // Label 2747: @130106
46229 GIM_Try, /*On fail goto*//*Label 2748*/ GIMT_Encode4(130138), // Rule ID 3369 //
46230 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2AES),
46231 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_aesmc),
46232 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
46233 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
46234 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
46235 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1077:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1) => (AESMC_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1)
46236 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESMC_ZZ_B),
46237 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
46238 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46239 GIR_RootConstrainSelectedInstOperands,
46240 // GIR_Coverage, 3369,
46241 GIR_EraseRootFromParent_Done,
46242 // Label 2748: @130138
46243 GIM_Try, /*On fail goto*//*Label 2749*/ GIMT_Encode4(130170), // Rule ID 4312 //
46244 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
46245 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
46246 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
46247 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46248 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
46249 // (intrinsic_wo_chain:{ *:[i32] } 575:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn) => (FCVTZSUWHr:{ *:[i32] } ?:{ *:[f16] }:$Rn)
46250 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWHr),
46251 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46252 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46253 GIR_RootConstrainSelectedInstOperands,
46254 // GIR_Coverage, 4312,
46255 GIR_EraseRootFromParent_Done,
46256 // Label 2749: @130170
46257 GIM_Try, /*On fail goto*//*Label 2750*/ GIMT_Encode4(130202), // Rule ID 4313 //
46258 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
46259 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
46260 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
46261 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46262 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
46263 // (intrinsic_wo_chain:{ *:[i64] } 575:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn) => (FCVTZSUXHr:{ *:[i64] } ?:{ *:[f16] }:$Rn)
46264 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXHr),
46265 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46266 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46267 GIR_RootConstrainSelectedInstOperands,
46268 // GIR_Coverage, 4313,
46269 GIR_EraseRootFromParent_Done,
46270 // Label 2750: @130202
46271 GIM_Try, /*On fail goto*//*Label 2751*/ GIMT_Encode4(130231), // Rule ID 4314 //
46272 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
46273 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
46274 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46275 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
46276 // (intrinsic_wo_chain:{ *:[i32] } 575:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn) => (FCVTZSUWSr:{ *:[i32] } ?:{ *:[f32] }:$Rn)
46277 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWSr),
46278 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46279 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46280 GIR_RootConstrainSelectedInstOperands,
46281 // GIR_Coverage, 4314,
46282 GIR_EraseRootFromParent_Done,
46283 // Label 2751: @130231
46284 GIM_Try, /*On fail goto*//*Label 2752*/ GIMT_Encode4(130260), // Rule ID 4315 //
46285 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
46286 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
46287 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46288 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
46289 // (intrinsic_wo_chain:{ *:[i64] } 575:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn) => (FCVTZSUXSr:{ *:[i64] } ?:{ *:[f32] }:$Rn)
46290 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXSr),
46291 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46292 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46293 GIR_RootConstrainSelectedInstOperands,
46294 // GIR_Coverage, 4315,
46295 GIR_EraseRootFromParent_Done,
46296 // Label 2752: @130260
46297 GIM_Try, /*On fail goto*//*Label 2753*/ GIMT_Encode4(130289), // Rule ID 4316 //
46298 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
46299 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
46300 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
46301 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
46302 // (intrinsic_wo_chain:{ *:[i32] } 575:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn) => (FCVTZSUWDr:{ *:[i32] } ?:{ *:[f64] }:$Rn)
46303 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWDr),
46304 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46305 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46306 GIR_RootConstrainSelectedInstOperands,
46307 // GIR_Coverage, 4316,
46308 GIR_EraseRootFromParent_Done,
46309 // Label 2753: @130289
46310 GIM_Try, /*On fail goto*//*Label 2754*/ GIMT_Encode4(130318), // Rule ID 4317 //
46311 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
46312 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
46313 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
46314 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
46315 // (intrinsic_wo_chain:{ *:[i64] } 575:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn) => (FCVTZSUXDr:{ *:[i64] } ?:{ *:[f64] }:$Rn)
46316 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXDr),
46317 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46318 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46319 GIR_RootConstrainSelectedInstOperands,
46320 // GIR_Coverage, 4317,
46321 GIR_EraseRootFromParent_Done,
46322 // Label 2754: @130318
46323 GIM_Try, /*On fail goto*//*Label 2755*/ GIMT_Encode4(130350), // Rule ID 4324 //
46324 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
46325 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
46326 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
46327 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46328 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
46329 // (intrinsic_wo_chain:{ *:[i32] } 576:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn) => (FCVTZUUWHr:{ *:[i32] } ?:{ *:[f16] }:$Rn)
46330 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWHr),
46331 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46332 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46333 GIR_RootConstrainSelectedInstOperands,
46334 // GIR_Coverage, 4324,
46335 GIR_EraseRootFromParent_Done,
46336 // Label 2755: @130350
46337 GIM_Try, /*On fail goto*//*Label 2756*/ GIMT_Encode4(130382), // Rule ID 4325 //
46338 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
46339 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
46340 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
46341 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46342 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
46343 // (intrinsic_wo_chain:{ *:[i64] } 576:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn) => (FCVTZUUXHr:{ *:[i64] } ?:{ *:[f16] }:$Rn)
46344 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXHr),
46345 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46346 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46347 GIR_RootConstrainSelectedInstOperands,
46348 // GIR_Coverage, 4325,
46349 GIR_EraseRootFromParent_Done,
46350 // Label 2756: @130382
46351 GIM_Try, /*On fail goto*//*Label 2757*/ GIMT_Encode4(130411), // Rule ID 4326 //
46352 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
46353 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
46354 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46355 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
46356 // (intrinsic_wo_chain:{ *:[i32] } 576:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn) => (FCVTZUUWSr:{ *:[i32] } ?:{ *:[f32] }:$Rn)
46357 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWSr),
46358 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46359 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46360 GIR_RootConstrainSelectedInstOperands,
46361 // GIR_Coverage, 4326,
46362 GIR_EraseRootFromParent_Done,
46363 // Label 2757: @130411
46364 GIM_Try, /*On fail goto*//*Label 2758*/ GIMT_Encode4(130440), // Rule ID 4327 //
46365 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
46366 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
46367 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46368 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
46369 // (intrinsic_wo_chain:{ *:[i64] } 576:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn) => (FCVTZUUXSr:{ *:[i64] } ?:{ *:[f32] }:$Rn)
46370 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXSr),
46371 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46372 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46373 GIR_RootConstrainSelectedInstOperands,
46374 // GIR_Coverage, 4327,
46375 GIR_EraseRootFromParent_Done,
46376 // Label 2758: @130440
46377 GIM_Try, /*On fail goto*//*Label 2759*/ GIMT_Encode4(130469), // Rule ID 4328 //
46378 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
46379 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
46380 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
46381 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
46382 // (intrinsic_wo_chain:{ *:[i32] } 576:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn) => (FCVTZUUWDr:{ *:[i32] } ?:{ *:[f64] }:$Rn)
46383 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWDr),
46384 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46385 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46386 GIR_RootConstrainSelectedInstOperands,
46387 // GIR_Coverage, 4328,
46388 GIR_EraseRootFromParent_Done,
46389 // Label 2759: @130469
46390 GIM_Try, /*On fail goto*//*Label 2760*/ GIMT_Encode4(130498), // Rule ID 4329 //
46391 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
46392 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
46393 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
46394 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
46395 // (intrinsic_wo_chain:{ *:[i64] } 576:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn) => (FCVTZUUXDr:{ *:[i64] } ?:{ *:[f64] }:$Rn)
46396 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXDr),
46397 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46398 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46399 GIR_RootConstrainSelectedInstOperands,
46400 // GIR_Coverage, 4329,
46401 GIR_EraseRootFromParent_Done,
46402 // Label 2760: @130498
46403 GIM_Try, /*On fail goto*//*Label 2761*/ GIMT_Encode4(130527), // Rule ID 4587 //
46404 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
46405 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
46406 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
46407 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
46408 // (intrinsic_wo_chain:{ *:[v4i16] } 575:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$Rn) => (FCVTZSv4f16:{ *:[v4i16] } ?:{ *:[v4f16] }:$Rn)
46409 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4f16),
46410 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46411 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46412 GIR_RootConstrainSelectedInstOperands,
46413 // GIR_Coverage, 4587,
46414 GIR_EraseRootFromParent_Done,
46415 // Label 2761: @130527
46416 GIM_Try, /*On fail goto*//*Label 2762*/ GIMT_Encode4(130556), // Rule ID 4588 //
46417 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
46418 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
46419 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
46420 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
46421 // (intrinsic_wo_chain:{ *:[v8i16] } 575:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$Rn) => (FCVTZSv8f16:{ *:[v8i16] } ?:{ *:[v8f16] }:$Rn)
46422 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv8f16),
46423 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46424 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46425 GIR_RootConstrainSelectedInstOperands,
46426 // GIR_Coverage, 4588,
46427 GIR_EraseRootFromParent_Done,
46428 // Label 2762: @130556
46429 GIM_Try, /*On fail goto*//*Label 2763*/ GIMT_Encode4(130585), // Rule ID 4589 //
46430 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
46431 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
46432 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
46433 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
46434 // (intrinsic_wo_chain:{ *:[v2i32] } 575:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$Rn) => (FCVTZSv2f32:{ *:[v2i32] } ?:{ *:[v2f32] }:$Rn)
46435 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2f32),
46436 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46437 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46438 GIR_RootConstrainSelectedInstOperands,
46439 // GIR_Coverage, 4589,
46440 GIR_EraseRootFromParent_Done,
46441 // Label 2763: @130585
46442 GIM_Try, /*On fail goto*//*Label 2764*/ GIMT_Encode4(130614), // Rule ID 4590 //
46443 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
46444 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
46445 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
46446 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
46447 // (intrinsic_wo_chain:{ *:[v4i32] } 575:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$Rn) => (FCVTZSv4f32:{ *:[v4i32] } ?:{ *:[v4f32] }:$Rn)
46448 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4f32),
46449 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46450 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46451 GIR_RootConstrainSelectedInstOperands,
46452 // GIR_Coverage, 4590,
46453 GIR_EraseRootFromParent_Done,
46454 // Label 2764: @130614
46455 GIM_Try, /*On fail goto*//*Label 2765*/ GIMT_Encode4(130643), // Rule ID 4591 //
46456 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
46457 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
46458 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
46459 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
46460 // (intrinsic_wo_chain:{ *:[v2i64] } 575:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$Rn) => (FCVTZSv2f64:{ *:[v2i64] } ?:{ *:[v2f64] }:$Rn)
46461 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2f64),
46462 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46463 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46464 GIR_RootConstrainSelectedInstOperands,
46465 // GIR_Coverage, 4591,
46466 GIR_EraseRootFromParent_Done,
46467 // Label 2765: @130643
46468 GIM_Try, /*On fail goto*//*Label 2766*/ GIMT_Encode4(130672), // Rule ID 4592 //
46469 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
46470 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
46471 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
46472 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
46473 // (intrinsic_wo_chain:{ *:[v4i16] } 576:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$Rn) => (FCVTZUv4f16:{ *:[v4i16] } ?:{ *:[v4f16] }:$Rn)
46474 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4f16),
46475 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46476 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46477 GIR_RootConstrainSelectedInstOperands,
46478 // GIR_Coverage, 4592,
46479 GIR_EraseRootFromParent_Done,
46480 // Label 2766: @130672
46481 GIM_Try, /*On fail goto*//*Label 2767*/ GIMT_Encode4(130701), // Rule ID 4593 //
46482 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
46483 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
46484 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
46485 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
46486 // (intrinsic_wo_chain:{ *:[v8i16] } 576:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$Rn) => (FCVTZUv8f16:{ *:[v8i16] } ?:{ *:[v8f16] }:$Rn)
46487 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv8f16),
46488 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46489 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46490 GIR_RootConstrainSelectedInstOperands,
46491 // GIR_Coverage, 4593,
46492 GIR_EraseRootFromParent_Done,
46493 // Label 2767: @130701
46494 GIM_Try, /*On fail goto*//*Label 2768*/ GIMT_Encode4(130730), // Rule ID 4594 //
46495 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
46496 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
46497 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
46498 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
46499 // (intrinsic_wo_chain:{ *:[v2i32] } 576:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$Rn) => (FCVTZUv2f32:{ *:[v2i32] } ?:{ *:[v2f32] }:$Rn)
46500 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2f32),
46501 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46502 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46503 GIR_RootConstrainSelectedInstOperands,
46504 // GIR_Coverage, 4594,
46505 GIR_EraseRootFromParent_Done,
46506 // Label 2768: @130730
46507 GIM_Try, /*On fail goto*//*Label 2769*/ GIMT_Encode4(130759), // Rule ID 4595 //
46508 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
46509 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
46510 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
46511 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
46512 // (intrinsic_wo_chain:{ *:[v4i32] } 576:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$Rn) => (FCVTZUv4f32:{ *:[v4i32] } ?:{ *:[v4f32] }:$Rn)
46513 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4f32),
46514 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46515 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46516 GIR_RootConstrainSelectedInstOperands,
46517 // GIR_Coverage, 4595,
46518 GIR_EraseRootFromParent_Done,
46519 // Label 2769: @130759
46520 GIM_Try, /*On fail goto*//*Label 2770*/ GIMT_Encode4(130788), // Rule ID 4596 //
46521 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
46522 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
46523 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
46524 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
46525 // (intrinsic_wo_chain:{ *:[v2i64] } 576:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$Rn) => (FCVTZUv2f64:{ *:[v2i64] } ?:{ *:[v2f64] }:$Rn)
46526 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2f64),
46527 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
46528 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
46529 GIR_RootConstrainSelectedInstOperands,
46530 // GIR_Coverage, 4596,
46531 GIR_EraseRootFromParent_Done,
46532 // Label 2770: @130788
46533 GIM_Try, /*On fail goto*//*Label 2771*/ GIMT_Encode4(130820), // Rule ID 8052 //
46534 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
46535 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_punpkhi),
46536 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
46537 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
46538 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
46539 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1441:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1) => (PUNPKHI_PP:{ *:[nxv8i1] } ?:{ *:[nxv16i1] }:$Op1)
46540 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
46541 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
46542 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46543 GIR_RootConstrainSelectedInstOperands,
46544 // GIR_Coverage, 8052,
46545 GIR_EraseRootFromParent_Done,
46546 // Label 2771: @130820
46547 GIM_Try, /*On fail goto*//*Label 2772*/ GIMT_Encode4(130852), // Rule ID 8053 //
46548 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
46549 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_punpkhi),
46550 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
46551 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
46552 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
46553 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1441:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1) => (PUNPKHI_PP:{ *:[nxv4i1] } ?:{ *:[nxv8i1] }:$Op1)
46554 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
46555 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
46556 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46557 GIR_RootConstrainSelectedInstOperands,
46558 // GIR_Coverage, 8053,
46559 GIR_EraseRootFromParent_Done,
46560 // Label 2772: @130852
46561 GIM_Try, /*On fail goto*//*Label 2773*/ GIMT_Encode4(130884), // Rule ID 8054 //
46562 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
46563 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_punpkhi),
46564 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
46565 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
46566 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
46567 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1441:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1) => (PUNPKHI_PP:{ *:[nxv2i1] } ?:{ *:[nxv4i1] }:$Op1)
46568 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
46569 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
46570 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46571 GIR_RootConstrainSelectedInstOperands,
46572 // GIR_Coverage, 8054,
46573 GIR_EraseRootFromParent_Done,
46574 // Label 2773: @130884
46575 GIM_Try, /*On fail goto*//*Label 2774*/ GIMT_Encode4(130916), // Rule ID 11472 //
46576 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
46577 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqxtnb),
46578 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
46579 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
46580 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
46581 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1825:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1) => (UQXTNB_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1)
46582 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNB_ZZ_B),
46583 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
46584 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46585 GIR_RootConstrainSelectedInstOperands,
46586 // GIR_Coverage, 11472,
46587 GIR_EraseRootFromParent_Done,
46588 // Label 2774: @130916
46589 GIM_Try, /*On fail goto*//*Label 2775*/ GIMT_Encode4(130948), // Rule ID 11473 //
46590 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
46591 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqxtnb),
46592 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
46593 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
46594 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
46595 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1825:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1) => (UQXTNB_ZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1)
46596 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNB_ZZ_H),
46597 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
46598 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46599 GIR_RootConstrainSelectedInstOperands,
46600 // GIR_Coverage, 11473,
46601 GIR_EraseRootFromParent_Done,
46602 // Label 2775: @130948
46603 GIM_Try, /*On fail goto*//*Label 2776*/ GIMT_Encode4(130980), // Rule ID 11474 //
46604 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
46605 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqxtnb),
46606 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
46607 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
46608 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
46609 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1825:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1) => (UQXTNB_ZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1)
46610 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNB_ZZ_S),
46611 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
46612 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46613 GIR_RootConstrainSelectedInstOperands,
46614 // GIR_Coverage, 11474,
46615 GIR_EraseRootFromParent_Done,
46616 // Label 2776: @130980
46617 GIM_Try, /*On fail goto*//*Label 2777*/ GIMT_Encode4(131012), // Rule ID 11475 //
46618 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
46619 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtunb),
46620 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
46621 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
46622 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
46623 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1634:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1) => (SQXTUNB_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1)
46624 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNB_ZZ_B),
46625 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
46626 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46627 GIR_RootConstrainSelectedInstOperands,
46628 // GIR_Coverage, 11475,
46629 GIR_EraseRootFromParent_Done,
46630 // Label 2777: @131012
46631 GIM_Try, /*On fail goto*//*Label 2778*/ GIMT_Encode4(131044), // Rule ID 11476 //
46632 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
46633 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtunb),
46634 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
46635 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
46636 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
46637 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1634:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1) => (SQXTUNB_ZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1)
46638 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNB_ZZ_H),
46639 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
46640 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46641 GIR_RootConstrainSelectedInstOperands,
46642 // GIR_Coverage, 11476,
46643 GIR_EraseRootFromParent_Done,
46644 // Label 2778: @131044
46645 GIM_Try, /*On fail goto*//*Label 2779*/ GIMT_Encode4(131076), // Rule ID 11477 //
46646 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
46647 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtunb),
46648 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
46649 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
46650 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
46651 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1634:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1) => (SQXTUNB_ZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1)
46652 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNB_ZZ_S),
46653 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
46654 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46655 GIR_RootConstrainSelectedInstOperands,
46656 // GIR_Coverage, 11477,
46657 GIR_EraseRootFromParent_Done,
46658 // Label 2779: @131076
46659 GIM_Try, /*On fail goto*//*Label 2780*/ GIMT_Encode4(131108), // Rule ID 11625 //
46660 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2AES),
46661 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_aesimc),
46662 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
46663 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
46664 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
46665 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1076:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1) => (AESIMC_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1)
46666 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESIMC_ZZ_B),
46667 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
46668 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
46669 GIR_RootConstrainSelectedInstOperands,
46670 // GIR_Coverage, 11625,
46671 GIR_EraseRootFromParent_Done,
46672 // Label 2780: @131108
46673 GIM_Reject,
46674 // Label 2439: @131109
46675 GIM_Try, /*On fail goto*//*Label 2781*/ GIMT_Encode4(175239),
46676 GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
46677 GIM_Try, /*On fail goto*//*Label 2782*/ GIMT_Encode4(131278), // Rule ID 2479 //
46678 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46679 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
46680 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
46681 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46682 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
46683 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
46684 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
46685 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
46686 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
46687 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
46688 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
46689 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
46690 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
46691 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
46692 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
46693 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
46694 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
46695 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
46696 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/3, // MIs[3]
46697 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
46698 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
46699 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
46700 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
46701 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
46702 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
46703 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
46704 // MIs[4] Operand 1
46705 // No operand predicates
46706 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
46707 GIM_CheckIsSafeToFold, /*NumInsns*/4,
46708 // (intrinsic_wo_chain:{ *:[i32] } 641:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 645:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), 0:{ *:[i64] })) => (SQDMLALv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
46709 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
46710 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46711 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46712 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(7), // Rn
46713 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
46714 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
46715 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv1i32_indexed),
46716 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46717 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
46718 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46719 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
46720 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
46721 GIR_RootConstrainSelectedInstOperands,
46722 // GIR_Coverage, 2479,
46723 GIR_EraseRootFromParent_Done,
46724 // Label 2782: @131278
46725 GIM_Try, /*On fail goto*//*Label 2783*/ GIMT_Encode4(131439), // Rule ID 5852 //
46726 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46727 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
46728 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
46729 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46730 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
46731 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
46732 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
46733 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
46734 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
46735 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
46736 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
46737 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
46738 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
46739 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
46740 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
46741 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
46742 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
46743 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
46744 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/3, // MIs[3]
46745 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
46746 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
46747 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
46748 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
46749 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
46750 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
46751 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
46752 // MIs[4] Operand 1
46753 // No operand predicates
46754 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
46755 GIM_CheckIsSafeToFold, /*NumInsns*/4,
46756 // (intrinsic_wo_chain:{ *:[i32] } 660:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 645:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), 0:{ *:[i64] })) => (SQDMLSLv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
46757 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
46758 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46759 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46760 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(7), // Rn
46761 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
46762 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
46763 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv1i32_indexed),
46764 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46765 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
46766 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46767 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
46768 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
46769 GIR_RootConstrainSelectedInstOperands,
46770 // GIR_Coverage, 5852,
46771 GIR_EraseRootFromParent_Done,
46772 // Label 2783: @131439
46773 GIM_Try, /*On fail goto*//*Label 2784*/ GIMT_Encode4(131528), // Rule ID 1730 //
46774 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46775 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
46776 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
46777 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
46778 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
46779 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
46780 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
46781 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
46782 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
46783 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
46784 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
46785 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
46786 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
46787 GIM_CheckIsSafeToFold, /*NumInsns*/1,
46788 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
46789 GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
46790 // (intrinsic_wo_chain:{ *:[v4i32] } 641:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 645:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (SQDMLALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
46791 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv8i16_v4i32),
46792 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46793 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
46794 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
46795 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
46796 GIR_RootConstrainSelectedInstOperands,
46797 // GIR_Coverage, 1730,
46798 GIR_EraseRootFromParent_Done,
46799 // Label 2784: @131528
46800 GIM_Try, /*On fail goto*//*Label 2785*/ GIMT_Encode4(131617), // Rule ID 1732 //
46801 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46802 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
46803 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
46804 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
46805 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
46806 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
46807 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
46808 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
46809 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
46810 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
46811 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
46812 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
46813 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
46814 GIM_CheckIsSafeToFold, /*NumInsns*/1,
46815 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
46816 GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
46817 // (intrinsic_wo_chain:{ *:[v2i64] } 641:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 645:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (SQDMLALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
46818 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i32_v2i64),
46819 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46820 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
46821 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
46822 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
46823 GIR_RootConstrainSelectedInstOperands,
46824 // GIR_Coverage, 1732,
46825 GIR_EraseRootFromParent_Done,
46826 // Label 2785: @131617
46827 GIM_Try, /*On fail goto*//*Label 2786*/ GIMT_Encode4(131706), // Rule ID 1734 //
46828 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46829 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
46830 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
46831 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
46832 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
46833 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
46834 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
46835 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
46836 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
46837 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
46838 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
46839 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
46840 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
46841 GIM_CheckIsSafeToFold, /*NumInsns*/1,
46842 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
46843 GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
46844 // (intrinsic_wo_chain:{ *:[v4i32] } 660:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 645:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (SQDMLSLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
46845 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv8i16_v4i32),
46846 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46847 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
46848 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
46849 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
46850 GIR_RootConstrainSelectedInstOperands,
46851 // GIR_Coverage, 1734,
46852 GIR_EraseRootFromParent_Done,
46853 // Label 2786: @131706
46854 GIM_Try, /*On fail goto*//*Label 2787*/ GIMT_Encode4(131795), // Rule ID 1736 //
46855 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46856 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
46857 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
46858 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
46859 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
46860 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
46861 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
46862 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
46863 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
46864 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
46865 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
46866 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
46867 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
46868 GIM_CheckIsSafeToFold, /*NumInsns*/1,
46869 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
46870 GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
46871 // (intrinsic_wo_chain:{ *:[v2i64] } 660:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 645:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (SQDMLSLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
46872 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv4i32_v2i64),
46873 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46874 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
46875 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
46876 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
46877 GIR_RootConstrainSelectedInstOperands,
46878 // GIR_Coverage, 1736,
46879 GIR_EraseRootFromParent_Done,
46880 // Label 2787: @131795
46881 GIM_Try, /*On fail goto*//*Label 2788*/ GIMT_Encode4(131978), // Rule ID 2477 //
46882 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46883 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
46884 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
46885 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46886 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
46887 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
46888 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
46889 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
46890 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
46891 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
46892 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
46893 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
46894 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
46895 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
46896 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
46897 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
46898 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
46899 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
46900 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
46901 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
46902 GIM_CheckIsSafeToFold, /*NumInsns*/2,
46903 // (intrinsic_wo_chain:{ *:[i32] } 641:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 645:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] })) => (SQDMLALv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v4i16] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
46904 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
46905 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
46906 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
46907 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46908 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46909 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46910 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46911 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46912 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
46913 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/3, // Rm
46914 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
46915 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
46916 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
46917 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
46918 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46919 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46920 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(7), // Rn
46921 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
46922 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
46923 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv1i32_indexed),
46924 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46925 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
46926 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46927 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
46928 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46929 GIR_RootConstrainSelectedInstOperands,
46930 // GIR_Coverage, 2477,
46931 GIR_EraseRootFromParent_Done,
46932 // Label 2788: @131978
46933 GIM_Try, /*On fail goto*//*Label 2789*/ GIMT_Encode4(132161), // Rule ID 5850 //
46934 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46935 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
46936 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
46937 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46938 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
46939 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
46940 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
46941 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
46942 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
46943 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
46944 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
46945 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
46946 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
46947 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
46948 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
46949 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
46950 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
46951 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
46952 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
46953 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
46954 GIM_CheckIsSafeToFold, /*NumInsns*/2,
46955 // (intrinsic_wo_chain:{ *:[i32] } 660:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 645:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] })) => (SQDMLSLv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v4i16] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
46956 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
46957 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
46958 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
46959 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46960 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46961 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
46962 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46963 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46964 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
46965 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/3, // Rm
46966 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
46967 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
46968 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
46969 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
46970 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46971 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
46972 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(7), // Rn
46973 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
46974 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
46975 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv1i32_indexed),
46976 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46977 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
46978 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46979 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
46980 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46981 GIR_RootConstrainSelectedInstOperands,
46982 // GIR_Coverage, 5850,
46983 GIR_EraseRootFromParent_Done,
46984 // Label 2789: @132161
46985 GIM_Try, /*On fail goto*//*Label 2790*/ GIMT_Encode4(132292), // Rule ID 2440 //
46986 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
46987 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
46988 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
46989 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46990 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
46991 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
46992 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46993 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
46994 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
46995 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
46996 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
46997 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
46998 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
46999 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
47000 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
47001 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
47002 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47003 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
47004 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47005 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
47006 // MIs[3] Operand 1
47007 // No operand predicates
47008 GIM_CheckIsSafeToFold, /*NumInsns*/3,
47009 // (intrinsic_wo_chain:{ *:[f16] } 593:{ *:[iPTR] }, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMULXv1i16_indexed:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
47010 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
47011 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47012 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47013 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
47014 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
47015 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
47016 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i16_indexed),
47017 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47018 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
47020 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
47021 GIR_RootConstrainSelectedInstOperands,
47022 // GIR_Coverage, 2440,
47023 GIR_EraseRootFromParent_Done,
47024 // Label 2790: @132292
47025 GIM_Try, /*On fail goto*//*Label 2791*/ GIMT_Encode4(132423), // Rule ID 2441 //
47026 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47027 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
47028 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
47029 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
47030 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
47031 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
47032 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47033 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
47034 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47035 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47036 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47037 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
47038 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
47039 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
47040 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
47041 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
47042 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47043 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
47044 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47045 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
47046 // MIs[3] Operand 1
47047 // No operand predicates
47048 GIM_CheckIsSafeToFold, /*NumInsns*/3,
47049 // (intrinsic_wo_chain:{ *:[f32] } 593:{ *:[iPTR] }, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (FMULXv1i32_indexed:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
47050 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47051 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47052 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47053 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rn
47054 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
47055 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
47056 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i32_indexed),
47057 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47058 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47059 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
47060 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
47061 GIR_RootConstrainSelectedInstOperands,
47062 // GIR_Coverage, 2441,
47063 GIR_EraseRootFromParent_Done,
47064 // Label 2791: @132423
47065 GIM_Try, /*On fail goto*//*Label 2792*/ GIMT_Encode4(132554), // Rule ID 2442 //
47066 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47067 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
47068 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
47069 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
47070 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
47071 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47072 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47073 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
47074 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
47075 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47076 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47077 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
47078 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
47079 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
47080 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
47081 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
47082 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47083 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
47084 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47085 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
47086 // MIs[3] Operand 1
47087 // No operand predicates
47088 GIM_CheckIsSafeToFold, /*NumInsns*/3,
47089 // (intrinsic_wo_chain:{ *:[f64] } 593:{ *:[iPTR] }, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)) => (FMULXv1i64_indexed:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
47090 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
47091 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47092 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47093 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
47094 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
47095 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
47096 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i64_indexed),
47097 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47098 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47099 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
47100 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
47101 GIR_RootConstrainSelectedInstOperands,
47102 // GIR_Coverage, 2442,
47103 GIR_EraseRootFromParent_Done,
47104 // Label 2792: @132554
47105 GIM_Try, /*On fail goto*//*Label 2793*/ GIMT_Encode4(132685), // Rule ID 12868 //
47106 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
47107 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
47108 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
47109 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
47110 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
47111 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
47112 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47113 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
47114 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
47115 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47116 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47117 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
47118 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47119 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
47120 // MIs[2] Operand 1
47121 // No operand predicates
47122 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
47123 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
47124 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
47125 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
47126 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47127 GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
47128 GIM_CheckIsSafeToFold, /*NumInsns*/3,
47129 // (intrinsic_wo_chain:{ *:[f16] } 593:{ *:[iPTR] }, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })) => (FMULXv1i16_indexed:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
47130 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
47131 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47132 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47133 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
47134 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
47135 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
47136 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i16_indexed),
47137 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47138 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
47140 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
47141 GIR_RootConstrainSelectedInstOperands,
47142 // GIR_Coverage, 12868,
47143 GIR_EraseRootFromParent_Done,
47144 // Label 2793: @132685
47145 GIM_Try, /*On fail goto*//*Label 2794*/ GIMT_Encode4(132816), // Rule ID 12869 //
47146 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47147 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
47148 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
47149 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
47150 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
47151 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
47152 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47153 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
47154 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47155 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47156 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47157 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
47158 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47159 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
47160 // MIs[2] Operand 1
47161 // No operand predicates
47162 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
47163 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
47164 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
47165 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
47166 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47167 GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
47168 GIM_CheckIsSafeToFold, /*NumInsns*/3,
47169 // (intrinsic_wo_chain:{ *:[f32] } 593:{ *:[iPTR] }, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })) => (FMULXv1i32_indexed:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
47170 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47171 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47172 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47173 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rn
47174 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
47175 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
47176 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i32_indexed),
47177 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47178 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47179 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
47180 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
47181 GIR_RootConstrainSelectedInstOperands,
47182 // GIR_Coverage, 12869,
47183 GIR_EraseRootFromParent_Done,
47184 // Label 2794: @132816
47185 GIM_Try, /*On fail goto*//*Label 2795*/ GIMT_Encode4(132947), // Rule ID 12870 //
47186 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47187 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
47188 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
47189 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
47190 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
47191 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47192 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47193 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
47194 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
47195 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47196 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47197 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
47198 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47199 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
47200 // MIs[2] Operand 1
47201 // No operand predicates
47202 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
47203 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
47204 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
47205 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
47206 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47207 GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
47208 GIM_CheckIsSafeToFold, /*NumInsns*/3,
47209 // (intrinsic_wo_chain:{ *:[f64] } 593:{ *:[iPTR] }, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })) => (FMULXv1i64_indexed:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
47210 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
47211 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47212 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47213 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
47214 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
47215 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
47216 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i64_indexed),
47217 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47218 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47219 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
47220 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
47221 GIR_RootConstrainSelectedInstOperands,
47222 // GIR_Coverage, 12870,
47223 GIR_EraseRootFromParent_Done,
47224 // Label 2795: @132947
47225 GIM_Try, /*On fail goto*//*Label 2796*/ GIMT_Encode4(133061), // Rule ID 2043 //
47226 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47227 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
47228 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
47229 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
47230 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
47231 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47232 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47233 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
47234 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
47235 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
47236 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
47237 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
47238 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
47239 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47240 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
47241 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
47242 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
47243 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
47244 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
47245 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
47246 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47247 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
47248 // MIs[3] Operand 1
47249 // No operand predicates
47250 GIM_CheckIsSafeToFold, /*NumInsns*/3,
47251 // (intrinsic_wo_chain:{ *:[v4i32] } 641:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 645:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))) => (SQDMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
47252 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i16_indexed),
47253 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47254 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
47255 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
47256 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
47257 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
47258 GIR_RootConstrainSelectedInstOperands,
47259 // GIR_Coverage, 2043,
47260 GIR_EraseRootFromParent_Done,
47261 // Label 2796: @133061
47262 GIM_Try, /*On fail goto*//*Label 2797*/ GIMT_Encode4(133175), // Rule ID 2050 //
47263 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47264 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
47265 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
47266 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
47267 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
47268 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47269 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47270 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
47271 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
47272 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
47273 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
47274 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
47275 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
47276 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47277 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
47278 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
47279 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
47280 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
47281 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
47282 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
47283 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47284 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
47285 // MIs[3] Operand 1
47286 // No operand predicates
47287 GIM_CheckIsSafeToFold, /*NumInsns*/3,
47288 // (intrinsic_wo_chain:{ *:[v4i32] } 660:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 645:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))) => (SQDMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
47289 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv4i16_indexed),
47290 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47291 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
47292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
47293 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
47294 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
47295 GIR_RootConstrainSelectedInstOperands,
47296 // GIR_Coverage, 2050,
47297 GIR_EraseRootFromParent_Done,
47298 // Label 2797: @133175
47299 GIM_Try, /*On fail goto*//*Label 2798*/ GIMT_Encode4(133289), // Rule ID 2046 //
47300 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47301 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
47302 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
47303 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
47304 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
47305 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47306 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47307 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
47308 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
47309 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
47310 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
47311 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
47312 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
47313 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47314 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
47315 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
47316 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
47317 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
47318 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47319 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
47320 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47321 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
47322 // MIs[3] Operand 1
47323 // No operand predicates
47324 GIM_CheckIsSafeToFold, /*NumInsns*/3,
47325 // (intrinsic_wo_chain:{ *:[v2i64] } 641:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 645:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SQDMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
47326 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv2i32_indexed),
47327 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47328 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
47329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
47330 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
47331 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
47332 GIR_RootConstrainSelectedInstOperands,
47333 // GIR_Coverage, 2046,
47334 GIR_EraseRootFromParent_Done,
47335 // Label 2798: @133289
47336 GIM_Try, /*On fail goto*//*Label 2799*/ GIMT_Encode4(133403), // Rule ID 2053 //
47337 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47338 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
47339 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
47340 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
47341 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
47342 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47343 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47344 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
47345 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
47346 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
47347 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
47348 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
47349 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
47350 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47351 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
47352 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
47353 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
47354 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
47355 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47356 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
47357 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47358 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
47359 // MIs[3] Operand 1
47360 // No operand predicates
47361 GIM_CheckIsSafeToFold, /*NumInsns*/3,
47362 // (intrinsic_wo_chain:{ *:[v2i64] } 660:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 645:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SQDMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
47363 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv2i32_indexed),
47364 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47365 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
47366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
47367 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
47368 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
47369 GIR_RootConstrainSelectedInstOperands,
47370 // GIR_Coverage, 2053,
47371 GIR_EraseRootFromParent_Done,
47372 // Label 2799: @133403
47373 GIM_Try, /*On fail goto*//*Label 2800*/ GIMT_Encode4(133517), // Rule ID 2048 //
47374 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47375 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
47376 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
47377 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
47378 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
47379 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47380 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47381 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
47382 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
47383 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
47384 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulls_scalar),
47385 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
47386 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
47387 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
47388 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
47389 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
47390 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
47391 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
47392 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47393 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
47394 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47395 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
47396 // MIs[3] Operand 1
47397 // No operand predicates
47398 GIM_CheckIsSafeToFold, /*NumInsns*/3,
47399 // (intrinsic_wo_chain:{ *:[i64] } 641:{ *:[iPTR] }, FPR64Op:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 646:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SQDMLALv1i64_indexed:{ *:[i64] } FPR64Op:{ *:[i64] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
47400 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv1i64_indexed),
47401 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47402 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
47403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
47404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
47405 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
47406 GIR_RootConstrainSelectedInstOperands,
47407 // GIR_Coverage, 2048,
47408 GIR_EraseRootFromParent_Done,
47409 // Label 2800: @133517
47410 GIM_Try, /*On fail goto*//*Label 2801*/ GIMT_Encode4(133631), // Rule ID 2055 //
47411 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47412 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
47413 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
47414 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
47415 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
47416 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47417 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47418 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
47419 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
47420 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
47421 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulls_scalar),
47422 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
47423 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
47424 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
47425 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
47426 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
47427 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
47428 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
47429 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47430 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
47431 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47432 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
47433 // MIs[3] Operand 1
47434 // No operand predicates
47435 GIM_CheckIsSafeToFold, /*NumInsns*/3,
47436 // (intrinsic_wo_chain:{ *:[i64] } 660:{ *:[iPTR] }, FPR64Op:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 646:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SQDMLSLv1i64_indexed:{ *:[i64] } FPR64Op:{ *:[i64] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
47437 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv1i64_indexed),
47438 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47439 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
47440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
47441 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
47442 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
47443 GIR_RootConstrainSelectedInstOperands,
47444 // GIR_Coverage, 2055,
47445 GIR_EraseRootFromParent_Done,
47446 // Label 2801: @133631
47447 GIM_Try, /*On fail goto*//*Label 2802*/ GIMT_Encode4(133688), // Rule ID 1738 //
47448 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47449 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
47450 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
47451 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
47452 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
47453 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47454 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
47455 GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
47456 // (intrinsic_wo_chain:{ *:[v4i32] } 645:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)) => (SQDMULLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
47457 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv8i16_v4i32),
47458 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47459 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
47460 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
47461 GIR_RootConstrainSelectedInstOperands,
47462 // GIR_Coverage, 1738,
47463 GIR_EraseRootFromParent_Done,
47464 // Label 2802: @133688
47465 GIM_Try, /*On fail goto*//*Label 2803*/ GIMT_Encode4(133745), // Rule ID 1740 //
47466 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47467 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
47468 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
47469 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
47470 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
47471 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47472 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
47473 GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
47474 // (intrinsic_wo_chain:{ *:[v2i64] } 645:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)) => (SQDMULLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
47475 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv4i32_v2i64),
47476 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47477 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
47478 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
47479 GIR_RootConstrainSelectedInstOperands,
47480 // GIR_Coverage, 1740,
47481 GIR_EraseRootFromParent_Done,
47482 // Label 2803: @133745
47483 GIM_Try, /*On fail goto*//*Label 2804*/ GIMT_Encode4(133855), // Rule ID 5869 //
47484 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
47485 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
47486 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
47487 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
47488 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
47489 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47490 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
47491 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
47492 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
47493 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
47494 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
47495 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
47496 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47497 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
47498 // MIs[2] Operand 1
47499 // No operand predicates
47500 GIM_CheckIsSafeToFold, /*NumInsns*/2,
47501 // (intrinsic_wo_chain:{ *:[f16] } 728:{ *:[iPTR] }, (and:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)
47502 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
47503 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47504 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47505 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
47506 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
47507 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
47508 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFh),
47509 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47510 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47511 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
47512 GIR_RootConstrainSelectedInstOperands,
47513 // GIR_Coverage, 5869,
47514 GIR_EraseRootFromParent_Done,
47515 // Label 2804: @133855
47516 GIM_Try, /*On fail goto*//*Label 2805*/ GIMT_Encode4(133952), // Rule ID 13146 //
47517 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
47518 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
47519 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
47520 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
47521 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
47522 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
47523 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47524 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
47525 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
47526 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47527 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47528 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
47529 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
47530 GIM_CheckIsSafeToFold, /*NumInsns*/1,
47531 // (intrinsic_wo_chain:{ *:[f16] } 593:{ *:[iPTR] }, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rn) => (FMULX16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }))
47532 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
47533 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47534 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47535 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rm
47536 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
47537 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
47538 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX16),
47539 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47540 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
47541 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47542 GIR_RootConstrainSelectedInstOperands,
47543 // GIR_Coverage, 13146,
47544 GIR_EraseRootFromParent_Done,
47545 // Label 2805: @133952
47546 GIM_Try, /*On fail goto*//*Label 2806*/ GIMT_Encode4(134049), // Rule ID 13147 //
47547 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
47548 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
47549 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
47550 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
47551 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
47552 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
47553 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47554 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
47555 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47556 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47557 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47558 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
47559 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
47560 GIM_CheckIsSafeToFold, /*NumInsns*/1,
47561 // (intrinsic_wo_chain:{ *:[f32] } 593:{ *:[iPTR] }, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rn) => (FMULX32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }))
47562 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47563 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47564 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47565 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rm
47566 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
47567 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
47568 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX32),
47569 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47570 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
47571 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47572 GIR_RootConstrainSelectedInstOperands,
47573 // GIR_Coverage, 13147,
47574 GIR_EraseRootFromParent_Done,
47575 // Label 2806: @134049
47576 GIM_Try, /*On fail goto*//*Label 2807*/ GIMT_Encode4(134146), // Rule ID 13148 //
47577 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
47578 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
47579 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
47580 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
47581 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
47582 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47583 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47584 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
47585 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
47586 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47587 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47588 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
47589 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47590 GIM_CheckIsSafeToFold, /*NumInsns*/1,
47591 // (intrinsic_wo_chain:{ *:[f64] } 593:{ *:[iPTR] }, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rn) => (FMULX64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }))
47592 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
47593 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47594 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47595 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rm
47596 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
47597 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
47598 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX64),
47599 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47600 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
47601 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47602 GIR_RootConstrainSelectedInstOperands,
47603 // GIR_Coverage, 13148,
47604 GIR_EraseRootFromParent_Done,
47605 // Label 2807: @134146
47606 GIM_Try, /*On fail goto*//*Label 2808*/ GIMT_Encode4(134229), // Rule ID 1729 //
47607 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47608 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
47609 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
47610 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
47611 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
47612 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47613 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47614 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
47615 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
47616 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
47617 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
47618 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
47619 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
47620 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47621 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47622 GIM_CheckIsSafeToFold, /*NumInsns*/1,
47623 // (intrinsic_wo_chain:{ *:[v4i32] } 641:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 645:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SQDMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
47624 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i16_v4i32),
47625 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47626 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
47627 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
47628 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
47629 GIR_RootConstrainSelectedInstOperands,
47630 // GIR_Coverage, 1729,
47631 GIR_EraseRootFromParent_Done,
47632 // Label 2808: @134229
47633 GIM_Try, /*On fail goto*//*Label 2809*/ GIMT_Encode4(134312), // Rule ID 1731 //
47634 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47635 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
47636 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
47637 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
47638 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
47639 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47640 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47641 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
47642 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
47643 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
47644 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
47645 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
47646 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
47647 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47648 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47649 GIM_CheckIsSafeToFold, /*NumInsns*/1,
47650 // (intrinsic_wo_chain:{ *:[v2i64] } 641:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 645:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SQDMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
47651 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv2i32_v2i64),
47652 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47653 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
47654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
47655 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
47656 GIR_RootConstrainSelectedInstOperands,
47657 // GIR_Coverage, 1731,
47658 GIR_EraseRootFromParent_Done,
47659 // Label 2809: @134312
47660 GIM_Try, /*On fail goto*//*Label 2810*/ GIMT_Encode4(134395), // Rule ID 1733 //
47661 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47662 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
47663 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
47664 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
47665 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
47666 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47667 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47668 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
47669 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
47670 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
47671 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
47672 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
47673 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
47674 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47675 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47676 GIM_CheckIsSafeToFold, /*NumInsns*/1,
47677 // (intrinsic_wo_chain:{ *:[v4i32] } 660:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 645:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SQDMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
47678 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv4i16_v4i32),
47679 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47680 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
47681 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
47682 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
47683 GIR_RootConstrainSelectedInstOperands,
47684 // GIR_Coverage, 1733,
47685 GIR_EraseRootFromParent_Done,
47686 // Label 2810: @134395
47687 GIM_Try, /*On fail goto*//*Label 2811*/ GIMT_Encode4(134478), // Rule ID 1735 //
47688 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47689 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
47690 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
47691 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
47692 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
47693 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47694 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47695 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
47696 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
47697 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
47698 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
47699 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
47700 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
47701 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47702 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47703 GIM_CheckIsSafeToFold, /*NumInsns*/1,
47704 // (intrinsic_wo_chain:{ *:[v2i64] } 660:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 645:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SQDMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
47705 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv2i32_v2i64),
47706 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47707 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
47708 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
47709 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
47710 GIR_RootConstrainSelectedInstOperands,
47711 // GIR_Coverage, 1735,
47712 GIR_EraseRootFromParent_Done,
47713 // Label 2811: @134478
47714 GIM_Try, /*On fail goto*//*Label 2812*/ GIMT_Encode4(134558), // Rule ID 4885 //
47715 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
47716 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
47717 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
47718 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
47719 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47720 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47721 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
47722 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
47723 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
47724 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulls_scalar),
47725 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
47726 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
47727 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
47728 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
47729 GIM_CheckIsSafeToFold, /*NumInsns*/1,
47730 // (intrinsic_wo_chain:{ *:[i64] } 641:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 646:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)) => (SQDMLALi32:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
47731 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALi32),
47732 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47733 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
47734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
47735 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
47736 GIR_RootConstrainSelectedInstOperands,
47737 // GIR_Coverage, 4885,
47738 GIR_EraseRootFromParent_Done,
47739 // Label 2812: @134558
47740 GIM_Try, /*On fail goto*//*Label 2813*/ GIMT_Encode4(134638), // Rule ID 4886 //
47741 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
47742 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
47743 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
47744 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
47745 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47746 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47747 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
47748 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
47749 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
47750 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulls_scalar),
47751 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
47752 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
47753 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
47754 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
47755 GIM_CheckIsSafeToFold, /*NumInsns*/1,
47756 // (intrinsic_wo_chain:{ *:[i64] } 660:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, (intrinsic_wo_chain:{ *:[i64] } 646:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)) => (SQDMLSLi32:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
47757 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLi32),
47758 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
47759 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
47760 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
47761 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
47762 GIR_RootConstrainSelectedInstOperands,
47763 // GIR_Coverage, 4886,
47764 GIR_EraseRootFromParent_Done,
47765 // Label 2813: @134638
47766 GIM_Try, /*On fail goto*//*Label 2814*/ GIMT_Encode4(134735), // Rule ID 4882 //
47767 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
47768 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
47769 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
47770 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
47771 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
47772 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
47773 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
47774 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
47775 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
47776 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
47777 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47778 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47779 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
47780 GIM_CheckIsSafeToFold, /*NumInsns*/1,
47781 // (intrinsic_wo_chain:{ *:[f16] } 593:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })) => (FMULX16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }))
47782 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
47783 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47784 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47785 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rm
47786 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
47787 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
47788 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX16),
47789 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47790 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
47791 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47792 GIR_RootConstrainSelectedInstOperands,
47793 // GIR_Coverage, 4882,
47794 GIR_EraseRootFromParent_Done,
47795 // Label 2814: @134735
47796 GIM_Try, /*On fail goto*//*Label 2815*/ GIMT_Encode4(134832), // Rule ID 4883 //
47797 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
47798 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
47799 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
47800 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
47801 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
47802 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
47803 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
47804 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
47805 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
47806 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47807 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47808 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47809 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
47810 GIM_CheckIsSafeToFold, /*NumInsns*/1,
47811 // (intrinsic_wo_chain:{ *:[f32] } 593:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })) => (FMULX32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }))
47812 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47813 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47814 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47815 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rm
47816 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
47817 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
47818 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX32),
47819 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47820 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
47821 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47822 GIR_RootConstrainSelectedInstOperands,
47823 // GIR_Coverage, 4883,
47824 GIR_EraseRootFromParent_Done,
47825 // Label 2815: @134832
47826 GIM_Try, /*On fail goto*//*Label 2816*/ GIMT_Encode4(134929), // Rule ID 4884 //
47827 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
47828 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
47829 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
47830 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
47831 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
47832 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47833 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47834 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
47835 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
47836 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
47837 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47838 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47839 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
47840 GIM_CheckIsSafeToFold, /*NumInsns*/1,
47841 // (intrinsic_wo_chain:{ *:[f64] } 593:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })) => (FMULX64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }))
47842 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
47843 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
47844 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
47845 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rm
47846 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
47847 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
47848 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX64),
47849 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47850 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
47851 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47852 GIR_RootConstrainSelectedInstOperands,
47853 // GIR_Coverage, 4884,
47854 GIR_EraseRootFromParent_Done,
47855 // Label 2816: @134929
47856 GIM_Try, /*On fail goto*//*Label 2817*/ GIMT_Encode4(135010), // Rule ID 12683 //
47857 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
47858 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
47859 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
47860 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
47861 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
47862 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47863 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47864 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
47865 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
47866 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47867 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
47868 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
47869 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47870 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
47871 // MIs[2] Operand 1
47872 // No operand predicates
47873 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47874 GIM_CheckIsSafeToFold, /*NumInsns*/2,
47875 // (intrinsic_wo_chain:{ *:[v4f16] } 593:{ *:[iPTR] }, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rn) => (FMULXv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
47876 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4i16_indexed),
47877 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47878 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
47879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
47880 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
47881 GIR_RootConstrainSelectedInstOperands,
47882 // GIR_Coverage, 12683,
47883 GIR_EraseRootFromParent_Done,
47884 // Label 2817: @135010
47885 GIM_Try, /*On fail goto*//*Label 2818*/ GIMT_Encode4(135091), // Rule ID 12684 //
47886 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
47887 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
47888 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
47889 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
47890 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
47891 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47892 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47893 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
47894 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
47895 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47896 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
47897 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
47898 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47899 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
47900 // MIs[2] Operand 1
47901 // No operand predicates
47902 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47903 GIM_CheckIsSafeToFold, /*NumInsns*/2,
47904 // (intrinsic_wo_chain:{ *:[v8f16] } 593:{ *:[iPTR] }, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rn) => (FMULXv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
47905 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv8i16_indexed),
47906 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47907 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
47908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
47909 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
47910 GIR_RootConstrainSelectedInstOperands,
47911 // GIR_Coverage, 12684,
47912 GIR_EraseRootFromParent_Done,
47913 // Label 2818: @135091
47914 GIM_Try, /*On fail goto*//*Label 2819*/ GIMT_Encode4(135172), // Rule ID 12686 //
47915 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47916 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
47917 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
47918 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
47919 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
47920 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47921 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47922 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
47923 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47924 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47925 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47926 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
47927 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47928 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
47929 // MIs[2] Operand 1
47930 // No operand predicates
47931 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
47932 GIM_CheckIsSafeToFold, /*NumInsns*/2,
47933 // (intrinsic_wo_chain:{ *:[v2f32] } 593:{ *:[iPTR] }, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn) => (FMULXv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
47934 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2i32_indexed),
47935 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47936 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
47937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
47938 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
47939 GIR_RootConstrainSelectedInstOperands,
47940 // GIR_Coverage, 12686,
47941 GIR_EraseRootFromParent_Done,
47942 // Label 2819: @135172
47943 GIM_Try, /*On fail goto*//*Label 2820*/ GIMT_Encode4(135253), // Rule ID 12687 //
47944 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47945 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
47946 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
47947 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
47948 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
47949 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47950 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47951 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
47952 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47953 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47954 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47955 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
47956 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47957 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
47958 // MIs[2] Operand 1
47959 // No operand predicates
47960 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47961 GIM_CheckIsSafeToFold, /*NumInsns*/2,
47962 // (intrinsic_wo_chain:{ *:[v4f32] } 593:{ *:[iPTR] }, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn) => (FMULXv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
47963 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4i32_indexed),
47964 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47965 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
47966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
47967 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
47968 GIR_RootConstrainSelectedInstOperands,
47969 // GIR_Coverage, 12687,
47970 GIR_EraseRootFromParent_Done,
47971 // Label 2820: @135253
47972 GIM_Try, /*On fail goto*//*Label 2821*/ GIMT_Encode4(135334), // Rule ID 12688 //
47973 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47974 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
47975 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
47976 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
47977 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
47978 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47979 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47980 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
47981 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
47982 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
47983 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47984 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
47985 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47986 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
47987 // MIs[2] Operand 1
47988 // No operand predicates
47989 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
47990 GIM_CheckIsSafeToFold, /*NumInsns*/2,
47991 // (intrinsic_wo_chain:{ *:[v2f64] } 593:{ *:[iPTR] }, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn) => (FMULXv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
47992 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2i64_indexed),
47993 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
47994 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
47995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
47996 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
47997 GIR_RootConstrainSelectedInstOperands,
47998 // GIR_Coverage, 12688,
47999 GIR_EraseRootFromParent_Done,
48000 // Label 2821: @135334
48001 GIM_Try, /*On fail goto*//*Label 2822*/ GIMT_Encode4(135415), // Rule ID 12689 //
48002 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
48003 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
48004 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
48005 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
48006 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
48007 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
48008 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
48009 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
48010 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
48011 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48012 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
48013 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48014 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48015 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
48016 // MIs[2] Operand 1
48017 // No operand predicates
48018 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
48019 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48020 // (intrinsic_wo_chain:{ *:[f16] } 593:{ *:[iPTR] }, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16Op:{ *:[f16] }:$Rn) => (FMULXv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
48021 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i16_indexed),
48022 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48023 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
48024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48025 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48026 GIR_RootConstrainSelectedInstOperands,
48027 // GIR_Coverage, 12689,
48028 GIR_EraseRootFromParent_Done,
48029 // Label 2822: @135415
48030 GIM_Try, /*On fail goto*//*Label 2823*/ GIMT_Encode4(135496), // Rule ID 12690 //
48031 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48032 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
48033 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
48034 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
48035 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
48036 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
48037 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
48038 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
48039 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
48040 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48041 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48042 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48043 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48044 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
48045 // MIs[2] Operand 1
48046 // No operand predicates
48047 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
48048 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48049 // (intrinsic_wo_chain:{ *:[f32] } 593:{ *:[iPTR] }, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32Op:{ *:[f32] }:$Rn) => (FMULXv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
48050 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i32_indexed),
48051 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48052 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
48053 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48054 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48055 GIR_RootConstrainSelectedInstOperands,
48056 // GIR_Coverage, 12690,
48057 GIR_EraseRootFromParent_Done,
48058 // Label 2823: @135496
48059 GIM_Try, /*On fail goto*//*Label 2824*/ GIMT_Encode4(135577), // Rule ID 12691 //
48060 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48061 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
48062 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
48063 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
48064 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
48065 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48066 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
48067 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
48068 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
48069 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48070 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48071 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48072 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48073 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
48074 // MIs[2] Operand 1
48075 // No operand predicates
48076 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48077 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48078 // (intrinsic_wo_chain:{ *:[f64] } 593:{ *:[iPTR] }, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64Op:{ *:[f64] }:$Rn) => (FMULXv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
48079 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i64_indexed),
48080 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48081 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
48082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48083 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48084 GIR_RootConstrainSelectedInstOperands,
48085 // GIR_Coverage, 12691,
48086 GIR_EraseRootFromParent_Done,
48087 // Label 2824: @135577
48088 GIM_Try, /*On fail goto*//*Label 2825*/ GIMT_Encode4(135658), // Rule ID 1975 //
48089 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
48090 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
48091 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
48092 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
48093 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
48094 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48095 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48096 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48097 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
48098 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
48099 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48100 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
48101 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48102 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48103 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
48104 // MIs[2] Operand 1
48105 // No operand predicates
48106 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48107 // (intrinsic_wo_chain:{ *:[v4f16] } 593:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMULXv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
48108 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4i16_indexed),
48109 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48110 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48112 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48113 GIR_RootConstrainSelectedInstOperands,
48114 // GIR_Coverage, 1975,
48115 GIR_EraseRootFromParent_Done,
48116 // Label 2825: @135658
48117 GIM_Try, /*On fail goto*//*Label 2826*/ GIMT_Encode4(135739), // Rule ID 1976 //
48118 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
48119 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
48120 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
48121 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
48122 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
48123 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48124 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48125 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48126 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
48127 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
48128 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48129 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
48130 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48131 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48132 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
48133 // MIs[2] Operand 1
48134 // No operand predicates
48135 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48136 // (intrinsic_wo_chain:{ *:[v8f16] } 593:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMULXv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
48137 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv8i16_indexed),
48138 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48139 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48140 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48141 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48142 GIR_RootConstrainSelectedInstOperands,
48143 // GIR_Coverage, 1976,
48144 GIR_EraseRootFromParent_Done,
48145 // Label 2826: @135739
48146 GIM_Try, /*On fail goto*//*Label 2827*/ GIMT_Encode4(135820), // Rule ID 2005 //
48147 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48148 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
48149 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
48150 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
48151 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
48152 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48153 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48154 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48155 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
48156 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
48157 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48158 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
48159 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48160 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48161 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
48162 // MIs[2] Operand 1
48163 // No operand predicates
48164 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48165 // (intrinsic_wo_chain:{ *:[v4i16] } 642:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (SQDMULHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
48166 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv4i16_indexed),
48167 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48168 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48169 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48170 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48171 GIR_RootConstrainSelectedInstOperands,
48172 // GIR_Coverage, 2005,
48173 GIR_EraseRootFromParent_Done,
48174 // Label 2827: @135820
48175 GIM_Try, /*On fail goto*//*Label 2828*/ GIMT_Encode4(135901), // Rule ID 2006 //
48176 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48177 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
48178 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
48179 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
48180 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
48181 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48182 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48183 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48184 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
48185 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
48186 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48187 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
48188 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48189 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48190 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
48191 // MIs[2] Operand 1
48192 // No operand predicates
48193 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48194 // (intrinsic_wo_chain:{ *:[v8i16] } 642:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (SQDMULHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
48195 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv8i16_indexed),
48196 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48197 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48198 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48199 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48200 GIR_RootConstrainSelectedInstOperands,
48201 // GIR_Coverage, 2006,
48202 GIR_EraseRootFromParent_Done,
48203 // Label 2828: @135901
48204 GIM_Try, /*On fail goto*//*Label 2829*/ GIMT_Encode4(135982), // Rule ID 2012 //
48205 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48206 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
48207 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
48208 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
48209 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
48210 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48211 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48212 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48213 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
48214 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
48215 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48216 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
48217 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48218 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48219 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
48220 // MIs[2] Operand 1
48221 // No operand predicates
48222 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48223 // (intrinsic_wo_chain:{ *:[v4i16] } 650:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (SQRDMULHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
48224 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv4i16_indexed),
48225 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48226 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48227 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48228 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48229 GIR_RootConstrainSelectedInstOperands,
48230 // GIR_Coverage, 2012,
48231 GIR_EraseRootFromParent_Done,
48232 // Label 2829: @135982
48233 GIM_Try, /*On fail goto*//*Label 2830*/ GIMT_Encode4(136063), // Rule ID 2013 //
48234 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48235 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
48236 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
48237 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
48238 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
48239 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48240 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48241 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48242 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
48243 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
48244 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48245 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
48246 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48247 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48248 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
48249 // MIs[2] Operand 1
48250 // No operand predicates
48251 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48252 // (intrinsic_wo_chain:{ *:[v8i16] } 650:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (SQRDMULHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
48253 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv8i16_indexed),
48254 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48255 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48256 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48257 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48258 GIR_RootConstrainSelectedInstOperands,
48259 // GIR_Coverage, 2013,
48260 GIR_EraseRootFromParent_Done,
48261 // Label 2830: @136063
48262 GIM_Try, /*On fail goto*//*Label 2831*/ GIMT_Encode4(136144), // Rule ID 2071 //
48263 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48264 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
48265 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
48266 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
48267 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
48268 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48269 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48270 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48271 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
48272 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
48273 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48274 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
48275 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48276 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48277 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
48278 // MIs[2] Operand 1
48279 // No operand predicates
48280 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48281 // (intrinsic_wo_chain:{ *:[v4i32] } 645:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (SQDMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
48282 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv4i16_indexed),
48283 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48284 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48285 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48286 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48287 GIR_RootConstrainSelectedInstOperands,
48288 // GIR_Coverage, 2071,
48289 GIR_EraseRootFromParent_Done,
48290 // Label 2831: @136144
48291 GIM_Try, /*On fail goto*//*Label 2832*/ GIMT_Encode4(136225), // Rule ID 1978 //
48292 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48293 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
48294 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
48295 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
48296 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
48297 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48298 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48299 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48300 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
48301 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
48302 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48303 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48304 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48305 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48306 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
48307 // MIs[2] Operand 1
48308 // No operand predicates
48309 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48310 // (intrinsic_wo_chain:{ *:[v2f32] } 593:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (FMULXv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
48311 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2i32_indexed),
48312 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48313 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48315 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48316 GIR_RootConstrainSelectedInstOperands,
48317 // GIR_Coverage, 1978,
48318 GIR_EraseRootFromParent_Done,
48319 // Label 2832: @136225
48320 GIM_Try, /*On fail goto*//*Label 2833*/ GIMT_Encode4(136306), // Rule ID 1979 //
48321 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48322 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
48323 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
48324 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
48325 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
48326 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48327 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48328 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48329 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
48330 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
48331 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48332 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48333 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48334 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48335 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
48336 // MIs[2] Operand 1
48337 // No operand predicates
48338 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48339 // (intrinsic_wo_chain:{ *:[v4f32] } 593:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (FMULXv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
48340 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4i32_indexed),
48341 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48342 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48343 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48344 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48345 GIR_RootConstrainSelectedInstOperands,
48346 // GIR_Coverage, 1979,
48347 GIR_EraseRootFromParent_Done,
48348 // Label 2833: @136306
48349 GIM_Try, /*On fail goto*//*Label 2834*/ GIMT_Encode4(136387), // Rule ID 2008 //
48350 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48351 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
48352 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
48353 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
48354 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
48355 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48356 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48357 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48358 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
48359 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
48360 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48361 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48362 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48363 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48364 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
48365 // MIs[2] Operand 1
48366 // No operand predicates
48367 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48368 // (intrinsic_wo_chain:{ *:[v2i32] } 642:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQDMULHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
48369 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv2i32_indexed),
48370 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48371 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48372 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48373 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48374 GIR_RootConstrainSelectedInstOperands,
48375 // GIR_Coverage, 2008,
48376 GIR_EraseRootFromParent_Done,
48377 // Label 2834: @136387
48378 GIM_Try, /*On fail goto*//*Label 2835*/ GIMT_Encode4(136468), // Rule ID 2009 //
48379 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48380 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
48381 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
48382 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
48383 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
48384 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48385 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48386 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48387 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
48388 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
48389 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48390 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48391 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48392 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48393 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
48394 // MIs[2] Operand 1
48395 // No operand predicates
48396 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48397 // (intrinsic_wo_chain:{ *:[v4i32] } 642:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQDMULHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
48398 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv4i32_indexed),
48399 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48400 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48402 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48403 GIR_RootConstrainSelectedInstOperands,
48404 // GIR_Coverage, 2009,
48405 GIR_EraseRootFromParent_Done,
48406 // Label 2835: @136468
48407 GIM_Try, /*On fail goto*//*Label 2836*/ GIMT_Encode4(136549), // Rule ID 2015 //
48408 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48409 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
48410 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
48411 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
48412 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
48413 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48414 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48415 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48416 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
48417 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
48418 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48419 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48420 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48421 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48422 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
48423 // MIs[2] Operand 1
48424 // No operand predicates
48425 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48426 // (intrinsic_wo_chain:{ *:[v2i32] } 650:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQRDMULHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
48427 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv2i32_indexed),
48428 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48429 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48430 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48431 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48432 GIR_RootConstrainSelectedInstOperands,
48433 // GIR_Coverage, 2015,
48434 GIR_EraseRootFromParent_Done,
48435 // Label 2836: @136549
48436 GIM_Try, /*On fail goto*//*Label 2837*/ GIMT_Encode4(136630), // Rule ID 2016 //
48437 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48438 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
48439 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
48440 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
48441 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
48442 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48443 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48444 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48445 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
48446 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
48447 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48448 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48449 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48450 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48451 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
48452 // MIs[2] Operand 1
48453 // No operand predicates
48454 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48455 // (intrinsic_wo_chain:{ *:[v4i32] } 650:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQRDMULHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
48456 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv4i32_indexed),
48457 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48458 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48459 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48460 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48461 GIR_RootConstrainSelectedInstOperands,
48462 // GIR_Coverage, 2016,
48463 GIR_EraseRootFromParent_Done,
48464 // Label 2837: @136630
48465 GIM_Try, /*On fail goto*//*Label 2838*/ GIMT_Encode4(136711), // Rule ID 2074 //
48466 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48467 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
48468 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
48469 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
48470 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
48471 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48472 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48473 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48474 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
48475 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
48476 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48477 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48478 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48479 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48480 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
48481 // MIs[2] Operand 1
48482 // No operand predicates
48483 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48484 // (intrinsic_wo_chain:{ *:[v2i64] } 645:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQDMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
48485 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv2i32_indexed),
48486 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48487 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48488 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48489 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48490 GIR_RootConstrainSelectedInstOperands,
48491 // GIR_Coverage, 2074,
48492 GIR_EraseRootFromParent_Done,
48493 // Label 2838: @136711
48494 GIM_Try, /*On fail goto*//*Label 2839*/ GIMT_Encode4(136792), // Rule ID 1980 //
48495 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48496 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
48497 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
48498 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
48499 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
48500 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48501 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48502 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48503 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
48504 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
48505 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48506 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48507 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48508 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48509 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
48510 // MIs[2] Operand 1
48511 // No operand predicates
48512 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48513 // (intrinsic_wo_chain:{ *:[v2f64] } 593:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)) => (FMULXv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
48514 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2i64_indexed),
48515 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48516 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48517 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48518 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48519 GIR_RootConstrainSelectedInstOperands,
48520 // GIR_Coverage, 1980,
48521 GIR_EraseRootFromParent_Done,
48522 // Label 2839: @136792
48523 GIM_Try, /*On fail goto*//*Label 2840*/ GIMT_Encode4(136873), // Rule ID 1981 //
48524 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
48525 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
48526 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
48527 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
48528 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
48529 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
48530 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
48531 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48532 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
48533 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
48534 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48535 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
48536 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48537 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48538 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
48539 // MIs[2] Operand 1
48540 // No operand predicates
48541 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48542 // (intrinsic_wo_chain:{ *:[f16] } 593:{ *:[iPTR] }, FPR16Op:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMULXv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
48543 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i16_indexed),
48544 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48545 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48546 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48547 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48548 GIR_RootConstrainSelectedInstOperands,
48549 // GIR_Coverage, 1981,
48550 GIR_EraseRootFromParent_Done,
48551 // Label 2840: @136873
48552 GIM_Try, /*On fail goto*//*Label 2841*/ GIMT_Encode4(136954), // Rule ID 1982 //
48553 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48554 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
48555 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
48556 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
48557 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
48558 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
48559 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
48560 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48561 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
48562 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
48563 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48564 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48565 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48566 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48567 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
48568 // MIs[2] Operand 1
48569 // No operand predicates
48570 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48571 // (intrinsic_wo_chain:{ *:[f32] } 593:{ *:[iPTR] }, FPR32Op:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (FMULXv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
48572 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i32_indexed),
48573 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48574 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48575 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48576 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48577 GIR_RootConstrainSelectedInstOperands,
48578 // GIR_Coverage, 1982,
48579 GIR_EraseRootFromParent_Done,
48580 // Label 2841: @136954
48581 GIM_Try, /*On fail goto*//*Label 2842*/ GIMT_Encode4(137035), // Rule ID 1983 //
48582 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48583 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
48584 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
48585 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
48586 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
48587 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48588 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48589 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48590 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
48591 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
48592 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48593 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48594 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48595 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48596 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
48597 // MIs[2] Operand 1
48598 // No operand predicates
48599 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48600 // (intrinsic_wo_chain:{ *:[f64] } 593:{ *:[iPTR] }, FPR64Op:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)) => (FMULXv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
48601 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i64_indexed),
48602 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48603 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48605 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48606 GIR_RootConstrainSelectedInstOperands,
48607 // GIR_Coverage, 1983,
48608 GIR_EraseRootFromParent_Done,
48609 // Label 2842: @137035
48610 GIM_Try, /*On fail goto*//*Label 2843*/ GIMT_Encode4(137116), // Rule ID 2010 //
48611 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48612 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
48613 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
48614 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
48615 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
48616 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
48617 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
48618 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48619 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
48620 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
48621 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48622 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48623 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48624 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48625 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
48626 // MIs[2] Operand 1
48627 // No operand predicates
48628 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48629 // (intrinsic_wo_chain:{ *:[i32] } 642:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQDMULHv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
48630 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv1i32_indexed),
48631 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48632 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48633 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48634 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48635 GIR_RootConstrainSelectedInstOperands,
48636 // GIR_Coverage, 2010,
48637 GIR_EraseRootFromParent_Done,
48638 // Label 2843: @137116
48639 GIM_Try, /*On fail goto*//*Label 2844*/ GIMT_Encode4(137197), // Rule ID 2017 //
48640 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48641 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
48642 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
48643 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
48644 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
48645 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
48646 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
48647 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48648 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
48649 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
48650 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48651 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48652 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48653 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48654 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
48655 // MIs[2] Operand 1
48656 // No operand predicates
48657 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48658 // (intrinsic_wo_chain:{ *:[i32] } 650:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQRDMULHv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
48659 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv1i32_indexed),
48660 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48661 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48662 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
48663 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48664 GIR_RootConstrainSelectedInstOperands,
48665 // GIR_Coverage, 2017,
48666 GIR_EraseRootFromParent_Done,
48667 // Label 2844: @137197
48668 GIM_Try, /*On fail goto*//*Label 2845*/ GIMT_Encode4(137275), // Rule ID 5853 //
48669 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulls_scalar),
48670 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
48671 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
48672 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
48673 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48674 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
48675 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48676 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
48677 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
48678 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
48679 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48680 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
48681 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48682 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
48683 // MIs[2] Operand 1
48684 // No operand predicates
48685 GIM_CheckIsSafeToFold, /*NumInsns*/2,
48686 // (intrinsic_wo_chain:{ *:[i64] } 646:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Vm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQDMULLv1i64_indexed:{ *:[i64] } FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Vm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
48687 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv1i64_indexed),
48688 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48689 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48690 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
48691 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
48692 GIR_RootConstrainSelectedInstOperands,
48693 // GIR_Coverage, 5853,
48694 GIR_EraseRootFromParent_Done,
48695 // Label 2845: @137275
48696 GIM_Try, /*On fail goto*//*Label 2846*/ GIMT_Encode4(137335), // Rule ID 5927 //
48697 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
48698 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
48699 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
48700 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
48701 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48702 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48703 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8,
48704 // (intrinsic_wo_chain:{ *:[v8i8] } 619:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vn, 8:{ *:[i32] }) => (RADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Vn, (MOVIv2d_ns:{ *:[v8i16] } 0:{ *:[i32] }))
48705 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
48706 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
48707 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48708 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
48709 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48710 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv8i16_v8i8),
48711 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48712 GIR_RootToRootCopy, /*OpIdx*/2, // Vn
48713 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48714 GIR_RootConstrainSelectedInstOperands,
48715 // GIR_Coverage, 5927,
48716 GIR_EraseRootFromParent_Done,
48717 // Label 2846: @137335
48718 GIM_Try, /*On fail goto*//*Label 2847*/ GIMT_Encode4(137395), // Rule ID 5928 //
48719 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
48720 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
48721 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
48722 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
48723 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48724 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48725 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16,
48726 // (intrinsic_wo_chain:{ *:[v4i16] } 619:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vn, 16:{ *:[i32] }) => (RADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Vn, (MOVIv2d_ns:{ *:[v4i32] } 0:{ *:[i32] }))
48727 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48728 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
48729 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48730 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
48731 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48732 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv4i32_v4i16),
48733 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48734 GIR_RootToRootCopy, /*OpIdx*/2, // Vn
48735 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48736 GIR_RootConstrainSelectedInstOperands,
48737 // GIR_Coverage, 5928,
48738 GIR_EraseRootFromParent_Done,
48739 // Label 2847: @137395
48740 GIM_Try, /*On fail goto*//*Label 2848*/ GIMT_Encode4(137455), // Rule ID 5929 //
48741 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
48742 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
48743 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
48744 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
48745 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48746 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
48747 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 32,
48748 // (intrinsic_wo_chain:{ *:[v2i32] } 619:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vn, 32:{ *:[i32] }) => (RADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Vn, (MOVIv2d_ns:{ *:[v2i64] } 0:{ *:[i32] }))
48749 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
48750 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
48751 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
48752 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
48753 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48754 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv2i64_v2i32),
48755 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48756 GIR_RootToRootCopy, /*OpIdx*/2, // Vn
48757 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48758 GIR_RootConstrainSelectedInstOperands,
48759 // GIR_Coverage, 5929,
48760 GIR_EraseRootFromParent_Done,
48761 // Label 2848: @137455
48762 GIM_Try, /*On fail goto*//*Label 2849*/ GIMT_Encode4(137502), // Rule ID 3766 //
48763 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
48764 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_strip),
48765 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
48766 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
48767 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
48768 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
48769 // MIs[0] Operand 3
48770 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
48771 // (intrinsic_wo_chain:{ *:[i64] } 289:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 0:{ *:[i32] }) => (XPACI:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
48772 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XPACI),
48773 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48774 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
48775 GIR_RootConstrainSelectedInstOperands,
48776 // GIR_Coverage, 3766,
48777 GIR_EraseRootFromParent_Done,
48778 // Label 2849: @137502
48779 GIM_Try, /*On fail goto*//*Label 2850*/ GIMT_Encode4(137549), // Rule ID 3767 //
48780 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
48781 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_strip),
48782 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
48783 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
48784 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
48785 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
48786 // MIs[0] Operand 3
48787 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(1),
48788 // (intrinsic_wo_chain:{ *:[i64] } 289:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 1:{ *:[i32] }) => (XPACI:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
48789 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XPACI),
48790 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48791 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
48792 GIR_RootConstrainSelectedInstOperands,
48793 // GIR_Coverage, 3767,
48794 GIR_EraseRootFromParent_Done,
48795 // Label 2850: @137549
48796 GIM_Try, /*On fail goto*//*Label 2851*/ GIMT_Encode4(137596), // Rule ID 3768 //
48797 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
48798 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_strip),
48799 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
48800 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
48801 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
48802 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
48803 // MIs[0] Operand 3
48804 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(2),
48805 // (intrinsic_wo_chain:{ *:[i64] } 289:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 2:{ *:[i32] }) => (XPACD:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
48806 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XPACD),
48807 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48808 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
48809 GIR_RootConstrainSelectedInstOperands,
48810 // GIR_Coverage, 3768,
48811 GIR_EraseRootFromParent_Done,
48812 // Label 2851: @137596
48813 GIM_Try, /*On fail goto*//*Label 2852*/ GIMT_Encode4(137643), // Rule ID 3769 //
48814 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
48815 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_strip),
48816 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
48817 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
48818 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
48819 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
48820 // MIs[0] Operand 3
48821 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(3),
48822 // (intrinsic_wo_chain:{ *:[i64] } 289:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 3:{ *:[i32] }) => (XPACD:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
48823 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XPACD),
48824 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48825 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
48826 GIR_RootConstrainSelectedInstOperands,
48827 // GIR_Coverage, 3769,
48828 GIR_EraseRootFromParent_Done,
48829 // Label 2852: @137643
48830 GIM_Try, /*On fail goto*//*Label 2853*/ GIMT_Encode4(137689), // Rule ID 3467 //
48831 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
48832 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane),
48833 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
48834 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
48835 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
48836 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
48837 // MIs[0] Idx
48838 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
48839 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_0),
48840 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1407:{ *:[iPTR] }, ZPRAny:{ *:[nxv16i8] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_0>>:$Idx) => (PMOV_PZI_B:{ *:[nxv16i1] } ZPRAny:{ *:[nxv16i8] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_0>>:$Idx)
48841 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_B),
48842 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
48843 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
48844 GIR_RootToRootCopy, /*OpIdx*/3, // Idx
48845 GIR_RootConstrainSelectedInstOperands,
48846 // GIR_Coverage, 3467,
48847 GIR_EraseRootFromParent_Done,
48848 // Label 2853: @137689
48849 GIM_Try, /*On fail goto*//*Label 2854*/ GIMT_Encode4(137735), // Rule ID 3468 //
48850 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
48851 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane),
48852 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
48853 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
48854 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
48855 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
48856 // MIs[0] Idx
48857 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
48858 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
48859 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1407:{ *:[iPTR] }, ZPRAny:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$Idx) => (PMOV_PZI_H:{ *:[nxv8i1] } ZPRAny:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$Idx)
48860 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_H),
48861 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
48862 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
48863 GIR_RootToRootCopy, /*OpIdx*/3, // Idx
48864 GIR_RootConstrainSelectedInstOperands,
48865 // GIR_Coverage, 3468,
48866 GIR_EraseRootFromParent_Done,
48867 // Label 2854: @137735
48868 GIM_Try, /*On fail goto*//*Label 2855*/ GIMT_Encode4(137781), // Rule ID 3469 //
48869 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
48870 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane),
48871 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
48872 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
48873 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
48874 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
48875 // MIs[0] Idx
48876 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
48877 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
48878 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1407:{ *:[iPTR] }, ZPRAny:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$Idx) => (PMOV_PZI_S:{ *:[nxv4i1] } ZPRAny:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$Idx)
48879 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_S),
48880 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
48881 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
48882 GIR_RootToRootCopy, /*OpIdx*/3, // Idx
48883 GIR_RootConstrainSelectedInstOperands,
48884 // GIR_Coverage, 3469,
48885 GIR_EraseRootFromParent_Done,
48886 // Label 2855: @137781
48887 GIM_Try, /*On fail goto*//*Label 2856*/ GIMT_Encode4(137827), // Rule ID 3470 //
48888 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
48889 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane),
48890 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
48891 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
48892 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
48893 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
48894 // MIs[0] Idx
48895 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
48896 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
48897 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1407:{ *:[iPTR] }, ZPRAny:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$Idx) => (PMOV_PZI_D:{ *:[nxv2i1] } ZPRAny:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$Idx)
48898 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_D),
48899 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
48900 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
48901 GIR_RootToRootCopy, /*OpIdx*/3, // Idx
48902 GIR_RootConstrainSelectedInstOperands,
48903 // GIR_Coverage, 3470,
48904 GIR_EraseRootFromParent_Done,
48905 // Label 2856: @137827
48906 GIM_Try, /*On fail goto*//*Label 2857*/ GIMT_Encode4(137883), // Rule ID 2095 //
48907 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48908 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshrn),
48909 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
48910 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
48911 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
48912 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
48913 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48914 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48915 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48916 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
48917 // MIs[1] Operand 1
48918 // No operand predicates
48919 GIM_CheckIsSafeToFold, /*NumInsns*/1,
48920 // (intrinsic_wo_chain:{ *:[i32] } 654:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SQRSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
48921 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNs),
48922 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48923 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48924 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
48925 GIR_RootConstrainSelectedInstOperands,
48926 // GIR_Coverage, 2095,
48927 GIR_EraseRootFromParent_Done,
48928 // Label 2857: @137883
48929 GIM_Try, /*On fail goto*//*Label 2858*/ GIMT_Encode4(137939), // Rule ID 2096 //
48930 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48931 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshrun),
48932 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
48933 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
48934 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
48935 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
48936 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48937 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48938 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48939 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
48940 // MIs[1] Operand 1
48941 // No operand predicates
48942 GIM_CheckIsSafeToFold, /*NumInsns*/1,
48943 // (intrinsic_wo_chain:{ *:[i32] } 655:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SQRSHRUNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
48944 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNs),
48945 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48946 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48947 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
48948 GIR_RootConstrainSelectedInstOperands,
48949 // GIR_Coverage, 2096,
48950 GIR_EraseRootFromParent_Done,
48951 // Label 2858: @137939
48952 GIM_Try, /*On fail goto*//*Label 2859*/ GIMT_Encode4(137995), // Rule ID 2101 //
48953 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48954 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshrn),
48955 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
48956 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
48957 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
48958 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
48959 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48960 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48961 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48962 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
48963 // MIs[1] Operand 1
48964 // No operand predicates
48965 GIM_CheckIsSafeToFold, /*NumInsns*/1,
48966 // (intrinsic_wo_chain:{ *:[i32] } 658:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SQSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
48967 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNs),
48968 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48969 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48970 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
48971 GIR_RootConstrainSelectedInstOperands,
48972 // GIR_Coverage, 2101,
48973 GIR_EraseRootFromParent_Done,
48974 // Label 2859: @137995
48975 GIM_Try, /*On fail goto*//*Label 2860*/ GIMT_Encode4(138051), // Rule ID 2102 //
48976 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48977 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshrun),
48978 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
48979 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
48980 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
48981 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
48982 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
48983 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48984 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48985 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
48986 // MIs[1] Operand 1
48987 // No operand predicates
48988 GIM_CheckIsSafeToFold, /*NumInsns*/1,
48989 // (intrinsic_wo_chain:{ *:[i32] } 659:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SQSHRUNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
48990 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNs),
48991 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48992 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
48993 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
48994 GIR_RootConstrainSelectedInstOperands,
48995 // GIR_Coverage, 2102,
48996 GIR_EraseRootFromParent_Done,
48997 // Label 2860: @138051
48998 GIM_Try, /*On fail goto*//*Label 2861*/ GIMT_Encode4(138107), // Rule ID 2108 //
48999 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49000 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshrn),
49001 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
49002 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49003 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49004 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
49005 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49006 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49007 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49008 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
49009 // MIs[1] Operand 1
49010 // No operand predicates
49011 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49012 // (intrinsic_wo_chain:{ *:[i32] } 703:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (UQRSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
49013 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNs),
49014 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49015 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49016 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49017 GIR_RootConstrainSelectedInstOperands,
49018 // GIR_Coverage, 2108,
49019 GIR_EraseRootFromParent_Done,
49020 // Label 2861: @138107
49021 GIM_Try, /*On fail goto*//*Label 2862*/ GIMT_Encode4(138163), // Rule ID 2111 //
49022 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49023 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshrn),
49024 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
49025 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49026 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49027 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
49028 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49029 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49030 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49031 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
49032 // MIs[1] Operand 1
49033 // No operand predicates
49034 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49035 // (intrinsic_wo_chain:{ *:[i32] } 705:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (UQSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
49036 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNs),
49037 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49038 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49039 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49040 GIR_RootConstrainSelectedInstOperands,
49041 // GIR_Coverage, 2111,
49042 GIR_EraseRootFromParent_Done,
49043 // Label 2862: @138163
49044 GIM_Try, /*On fail goto*//*Label 2863*/ GIMT_Encode4(138219), // Rule ID 2133 //
49045 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49046 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
49047 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
49048 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
49049 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49050 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49051 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49052 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49053 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49054 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
49055 // MIs[1] Operand 1
49056 // No operand predicates
49057 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49058 // (intrinsic_wo_chain:{ *:[v8i8] } 619:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (RSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
49059 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNv8i8_shift),
49060 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49061 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49062 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49063 GIR_RootConstrainSelectedInstOperands,
49064 // GIR_Coverage, 2133,
49065 GIR_EraseRootFromParent_Done,
49066 // Label 2863: @138219
49067 GIM_Try, /*On fail goto*//*Label 2864*/ GIMT_Encode4(138275), // Rule ID 2135 //
49068 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49069 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
49070 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
49071 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
49072 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49073 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49074 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49075 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49076 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49077 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
49078 // MIs[1] Operand 1
49079 // No operand predicates
49080 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49081 // (intrinsic_wo_chain:{ *:[v4i16] } 619:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (RSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
49082 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNv4i16_shift),
49083 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49084 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49085 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49086 GIR_RootConstrainSelectedInstOperands,
49087 // GIR_Coverage, 2135,
49088 GIR_EraseRootFromParent_Done,
49089 // Label 2864: @138275
49090 GIM_Try, /*On fail goto*//*Label 2865*/ GIMT_Encode4(138331), // Rule ID 2137 //
49091 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49092 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
49093 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
49094 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
49095 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49096 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49097 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49098 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49099 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49100 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
49101 // MIs[1] Operand 1
49102 // No operand predicates
49103 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49104 // (intrinsic_wo_chain:{ *:[v2i32] } 619:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (RSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
49105 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNv2i32_shift),
49106 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49107 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49108 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49109 GIR_RootConstrainSelectedInstOperands,
49110 // GIR_Coverage, 2137,
49111 GIR_EraseRootFromParent_Done,
49112 // Label 2865: @138331
49113 GIM_Try, /*On fail goto*//*Label 2866*/ GIMT_Encode4(138387), // Rule ID 2155 //
49114 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49115 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshrn),
49116 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
49117 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
49118 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49119 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49120 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49121 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49122 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49123 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
49124 // MIs[1] Operand 1
49125 // No operand predicates
49126 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49127 // (intrinsic_wo_chain:{ *:[v8i8] } 654:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (SQRSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
49128 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNv8i8_shift),
49129 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49130 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49131 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49132 GIR_RootConstrainSelectedInstOperands,
49133 // GIR_Coverage, 2155,
49134 GIR_EraseRootFromParent_Done,
49135 // Label 2866: @138387
49136 GIM_Try, /*On fail goto*//*Label 2867*/ GIMT_Encode4(138443), // Rule ID 2156 //
49137 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49138 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshrn),
49139 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
49140 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
49141 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49142 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49143 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49144 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49145 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49146 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
49147 // MIs[1] Operand 1
49148 // No operand predicates
49149 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49150 // (intrinsic_wo_chain:{ *:[v4i16] } 654:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (SQRSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
49151 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNv4i16_shift),
49152 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49153 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49154 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49155 GIR_RootConstrainSelectedInstOperands,
49156 // GIR_Coverage, 2156,
49157 GIR_EraseRootFromParent_Done,
49158 // Label 2867: @138443
49159 GIM_Try, /*On fail goto*//*Label 2868*/ GIMT_Encode4(138499), // Rule ID 2157 //
49160 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49161 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshrn),
49162 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
49163 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
49164 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49165 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49166 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49167 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49168 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49169 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
49170 // MIs[1] Operand 1
49171 // No operand predicates
49172 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49173 // (intrinsic_wo_chain:{ *:[v2i32] } 654:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (SQRSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
49174 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNv2i32_shift),
49175 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49176 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49177 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49178 GIR_RootConstrainSelectedInstOperands,
49179 // GIR_Coverage, 2157,
49180 GIR_EraseRootFromParent_Done,
49181 // Label 2868: @138499
49182 GIM_Try, /*On fail goto*//*Label 2869*/ GIMT_Encode4(138555), // Rule ID 2158 //
49183 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49184 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshrun),
49185 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
49186 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
49187 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49188 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49189 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49190 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49191 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49192 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
49193 // MIs[1] Operand 1
49194 // No operand predicates
49195 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49196 // (intrinsic_wo_chain:{ *:[v8i8] } 655:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (SQRSHRUNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
49197 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNv8i8_shift),
49198 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49199 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49200 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49201 GIR_RootConstrainSelectedInstOperands,
49202 // GIR_Coverage, 2158,
49203 GIR_EraseRootFromParent_Done,
49204 // Label 2869: @138555
49205 GIM_Try, /*On fail goto*//*Label 2870*/ GIMT_Encode4(138611), // Rule ID 2159 //
49206 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49207 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshrun),
49208 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
49209 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
49210 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49211 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49212 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49213 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49214 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49215 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
49216 // MIs[1] Operand 1
49217 // No operand predicates
49218 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49219 // (intrinsic_wo_chain:{ *:[v4i16] } 655:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (SQRSHRUNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
49220 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNv4i16_shift),
49221 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49222 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49223 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49224 GIR_RootConstrainSelectedInstOperands,
49225 // GIR_Coverage, 2159,
49226 GIR_EraseRootFromParent_Done,
49227 // Label 2870: @138611
49228 GIM_Try, /*On fail goto*//*Label 2871*/ GIMT_Encode4(138667), // Rule ID 2160 //
49229 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49230 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshrun),
49231 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
49232 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
49233 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49234 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49235 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49236 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49237 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49238 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
49239 // MIs[1] Operand 1
49240 // No operand predicates
49241 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49242 // (intrinsic_wo_chain:{ *:[v2i32] } 655:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (SQRSHRUNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
49243 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNv2i32_shift),
49244 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49245 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49246 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49247 GIR_RootConstrainSelectedInstOperands,
49248 // GIR_Coverage, 2160,
49249 GIR_EraseRootFromParent_Done,
49250 // Label 2871: @138667
49251 GIM_Try, /*On fail goto*//*Label 2872*/ GIMT_Encode4(138723), // Rule ID 2175 //
49252 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49253 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshrn),
49254 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
49255 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
49256 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49257 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49258 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49259 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49260 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49261 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
49262 // MIs[1] Operand 1
49263 // No operand predicates
49264 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49265 // (intrinsic_wo_chain:{ *:[v8i8] } 658:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (SQSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
49266 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNv8i8_shift),
49267 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49268 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49269 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49270 GIR_RootConstrainSelectedInstOperands,
49271 // GIR_Coverage, 2175,
49272 GIR_EraseRootFromParent_Done,
49273 // Label 2872: @138723
49274 GIM_Try, /*On fail goto*//*Label 2873*/ GIMT_Encode4(138779), // Rule ID 2176 //
49275 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49276 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshrn),
49277 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
49278 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
49279 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49280 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49281 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49282 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49283 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49284 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
49285 // MIs[1] Operand 1
49286 // No operand predicates
49287 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49288 // (intrinsic_wo_chain:{ *:[v4i16] } 658:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (SQSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
49289 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNv4i16_shift),
49290 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49291 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49292 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49293 GIR_RootConstrainSelectedInstOperands,
49294 // GIR_Coverage, 2176,
49295 GIR_EraseRootFromParent_Done,
49296 // Label 2873: @138779
49297 GIM_Try, /*On fail goto*//*Label 2874*/ GIMT_Encode4(138835), // Rule ID 2177 //
49298 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49299 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshrn),
49300 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
49301 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
49302 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49303 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49304 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49305 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49306 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49307 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
49308 // MIs[1] Operand 1
49309 // No operand predicates
49310 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49311 // (intrinsic_wo_chain:{ *:[v2i32] } 658:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (SQSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
49312 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNv2i32_shift),
49313 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49314 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49315 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49316 GIR_RootConstrainSelectedInstOperands,
49317 // GIR_Coverage, 2177,
49318 GIR_EraseRootFromParent_Done,
49319 // Label 2874: @138835
49320 GIM_Try, /*On fail goto*//*Label 2875*/ GIMT_Encode4(138891), // Rule ID 2178 //
49321 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49322 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshrun),
49323 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
49324 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
49325 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49326 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49327 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49328 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49329 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49330 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
49331 // MIs[1] Operand 1
49332 // No operand predicates
49333 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49334 // (intrinsic_wo_chain:{ *:[v8i8] } 659:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (SQSHRUNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
49335 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNv8i8_shift),
49336 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49337 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49338 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49339 GIR_RootConstrainSelectedInstOperands,
49340 // GIR_Coverage, 2178,
49341 GIR_EraseRootFromParent_Done,
49342 // Label 2875: @138891
49343 GIM_Try, /*On fail goto*//*Label 2876*/ GIMT_Encode4(138947), // Rule ID 2179 //
49344 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49345 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshrun),
49346 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
49347 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
49348 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49349 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49350 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49351 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49352 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49353 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
49354 // MIs[1] Operand 1
49355 // No operand predicates
49356 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49357 // (intrinsic_wo_chain:{ *:[v4i16] } 659:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (SQSHRUNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
49358 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNv4i16_shift),
49359 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49360 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49361 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49362 GIR_RootConstrainSelectedInstOperands,
49363 // GIR_Coverage, 2179,
49364 GIR_EraseRootFromParent_Done,
49365 // Label 2876: @138947
49366 GIM_Try, /*On fail goto*//*Label 2877*/ GIMT_Encode4(139003), // Rule ID 2180 //
49367 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49368 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshrun),
49369 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
49370 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
49371 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49372 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49373 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49374 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49375 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49376 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
49377 // MIs[1] Operand 1
49378 // No operand predicates
49379 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49380 // (intrinsic_wo_chain:{ *:[v2i32] } 659:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (SQSHRUNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
49381 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNv2i32_shift),
49382 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49383 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49384 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49385 GIR_RootConstrainSelectedInstOperands,
49386 // GIR_Coverage, 2180,
49387 GIR_EraseRootFromParent_Done,
49388 // Label 2877: @139003
49389 GIM_Try, /*On fail goto*//*Label 2878*/ GIMT_Encode4(139059), // Rule ID 2234 //
49390 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49391 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshrn),
49392 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
49393 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
49394 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49395 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49396 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49397 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49398 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49399 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
49400 // MIs[1] Operand 1
49401 // No operand predicates
49402 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49403 // (intrinsic_wo_chain:{ *:[v8i8] } 703:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (UQRSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
49404 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNv8i8_shift),
49405 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49406 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49407 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49408 GIR_RootConstrainSelectedInstOperands,
49409 // GIR_Coverage, 2234,
49410 GIR_EraseRootFromParent_Done,
49411 // Label 2878: @139059
49412 GIM_Try, /*On fail goto*//*Label 2879*/ GIMT_Encode4(139115), // Rule ID 2235 //
49413 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49414 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshrn),
49415 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
49416 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
49417 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49418 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49419 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49420 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49421 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49422 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
49423 // MIs[1] Operand 1
49424 // No operand predicates
49425 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49426 // (intrinsic_wo_chain:{ *:[v4i16] } 703:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (UQRSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
49427 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNv4i16_shift),
49428 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49429 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49430 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49431 GIR_RootConstrainSelectedInstOperands,
49432 // GIR_Coverage, 2235,
49433 GIR_EraseRootFromParent_Done,
49434 // Label 2879: @139115
49435 GIM_Try, /*On fail goto*//*Label 2880*/ GIMT_Encode4(139171), // Rule ID 2236 //
49436 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49437 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshrn),
49438 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
49439 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
49440 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49441 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49442 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49443 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49444 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49445 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
49446 // MIs[1] Operand 1
49447 // No operand predicates
49448 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49449 // (intrinsic_wo_chain:{ *:[v2i32] } 703:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (UQRSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
49450 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNv2i32_shift),
49451 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49452 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49453 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49454 GIR_RootConstrainSelectedInstOperands,
49455 // GIR_Coverage, 2236,
49456 GIR_EraseRootFromParent_Done,
49457 // Label 2880: @139171
49458 GIM_Try, /*On fail goto*//*Label 2881*/ GIMT_Encode4(139227), // Rule ID 2244 //
49459 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49460 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshrn),
49461 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
49462 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
49463 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49464 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49465 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49466 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49467 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49468 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
49469 // MIs[1] Operand 1
49470 // No operand predicates
49471 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49472 // (intrinsic_wo_chain:{ *:[v8i8] } 705:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm) => (UQSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
49473 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNv8i8_shift),
49474 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49475 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49476 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49477 GIR_RootConstrainSelectedInstOperands,
49478 // GIR_Coverage, 2244,
49479 GIR_EraseRootFromParent_Done,
49480 // Label 2881: @139227
49481 GIM_Try, /*On fail goto*//*Label 2882*/ GIMT_Encode4(139283), // Rule ID 2245 //
49482 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49483 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshrn),
49484 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
49485 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
49486 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49487 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49488 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49489 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49490 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49491 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
49492 // MIs[1] Operand 1
49493 // No operand predicates
49494 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49495 // (intrinsic_wo_chain:{ *:[v4i16] } 705:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm) => (UQSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
49496 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNv4i16_shift),
49497 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49498 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49499 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49500 GIR_RootConstrainSelectedInstOperands,
49501 // GIR_Coverage, 2245,
49502 GIR_EraseRootFromParent_Done,
49503 // Label 2882: @139283
49504 GIM_Try, /*On fail goto*//*Label 2883*/ GIMT_Encode4(139339), // Rule ID 2246 //
49505 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
49506 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshrn),
49507 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
49508 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
49509 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49510 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49511 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
49512 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49513 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49514 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
49515 // MIs[1] Operand 1
49516 // No operand predicates
49517 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49518 // (intrinsic_wo_chain:{ *:[v2i32] } 705:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm) => (UQSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
49519 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNv2i32_shift),
49520 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49521 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49522 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49523 GIR_RootConstrainSelectedInstOperands,
49524 // GIR_Coverage, 2246,
49525 GIR_EraseRootFromParent_Done,
49526 // Label 2883: @139339
49527 GIM_Try, /*On fail goto*//*Label 2884*/ GIMT_Encode4(139392), // Rule ID 5854 //
49528 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
49529 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
49530 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
49531 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49532 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
49533 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
49534 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49535 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49536 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
49537 // MIs[1] Operand 1
49538 // No operand predicates
49539 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49540 // (intrinsic_wo_chain:{ *:[i32] } 724:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (FCVTZSs:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
49541 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSs),
49542 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49543 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49544 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49545 GIR_RootConstrainSelectedInstOperands,
49546 // GIR_Coverage, 5854,
49547 GIR_EraseRootFromParent_Done,
49548 // Label 2884: @139392
49549 GIM_Try, /*On fail goto*//*Label 2885*/ GIMT_Encode4(139445), // Rule ID 5855 //
49550 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
49551 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
49552 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
49553 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49554 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
49555 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
49556 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49557 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49558 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
49559 // MIs[1] Operand 1
49560 // No operand predicates
49561 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49562 // (intrinsic_wo_chain:{ *:[i32] } 725:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (FCVTZUs:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
49563 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUs),
49564 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49565 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49566 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49567 GIR_RootConstrainSelectedInstOperands,
49568 // GIR_Coverage, 5855,
49569 GIR_EraseRootFromParent_Done,
49570 // Label 2885: @139445
49571 GIM_Try, /*On fail goto*//*Label 2886*/ GIMT_Encode4(139498), // Rule ID 5856 //
49572 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
49573 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
49574 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49575 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49576 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49577 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49578 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49579 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49580 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
49581 // MIs[1] Operand 1
49582 // No operand predicates
49583 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49584 // (intrinsic_wo_chain:{ *:[i64] } 724:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (FCVTZSd:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
49585 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSd),
49586 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49587 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49588 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49589 GIR_RootConstrainSelectedInstOperands,
49590 // GIR_Coverage, 5856,
49591 GIR_EraseRootFromParent_Done,
49592 // Label 2886: @139498
49593 GIM_Try, /*On fail goto*//*Label 2887*/ GIMT_Encode4(139551), // Rule ID 5857 //
49594 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
49595 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
49596 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49597 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49598 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49599 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49600 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49601 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49602 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
49603 // MIs[1] Operand 1
49604 // No operand predicates
49605 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49606 // (intrinsic_wo_chain:{ *:[i64] } 725:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (FCVTZUd:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
49607 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUd),
49608 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49609 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49610 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49611 GIR_RootConstrainSelectedInstOperands,
49612 // GIR_Coverage, 5857,
49613 GIR_EraseRootFromParent_Done,
49614 // Label 2887: @139551
49615 GIM_Try, /*On fail goto*//*Label 2888*/ GIMT_Encode4(139604), // Rule ID 5858 //
49616 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
49617 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
49618 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49619 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49620 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49621 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49622 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49623 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49624 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
49625 // MIs[1] Operand 1
49626 // No operand predicates
49627 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49628 // (intrinsic_wo_chain:{ *:[v1i64] } 724:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (FCVTZSd:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
49629 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSd),
49630 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49631 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49632 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49633 GIR_RootConstrainSelectedInstOperands,
49634 // GIR_Coverage, 5858,
49635 GIR_EraseRootFromParent_Done,
49636 // Label 2888: @139604
49637 GIM_Try, /*On fail goto*//*Label 2889*/ GIMT_Encode4(139657), // Rule ID 5859 //
49638 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
49639 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
49640 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49641 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49642 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49643 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49644 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49645 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49646 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
49647 // MIs[1] Operand 1
49648 // No operand predicates
49649 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49650 // (intrinsic_wo_chain:{ *:[v1i64] } 725:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (FCVTZUd:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
49651 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUd),
49652 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49653 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49654 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49655 GIR_RootConstrainSelectedInstOperands,
49656 // GIR_Coverage, 5859,
49657 GIR_EraseRootFromParent_Done,
49658 // Label 2889: @139657
49659 GIM_Try, /*On fail goto*//*Label 2890*/ GIMT_Encode4(139710), // Rule ID 5860 //
49660 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
49661 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
49662 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
49663 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49664 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
49665 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
49666 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49667 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49668 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
49669 // MIs[1] Operand 1
49670 // No operand predicates
49671 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49672 // (intrinsic_wo_chain:{ *:[f32] } 728:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (UCVTFs:{ *:[f32] } FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
49673 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFs),
49674 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49675 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49676 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49677 GIR_RootConstrainSelectedInstOperands,
49678 // GIR_Coverage, 5860,
49679 GIR_EraseRootFromParent_Done,
49680 // Label 2890: @139710
49681 GIM_Try, /*On fail goto*//*Label 2891*/ GIMT_Encode4(139763), // Rule ID 5861 //
49682 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
49683 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
49684 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49685 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49686 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49687 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49688 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49689 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49690 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
49691 // MIs[1] Operand 1
49692 // No operand predicates
49693 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49694 // (intrinsic_wo_chain:{ *:[f64] } 728:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (UCVTFd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
49695 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFd),
49696 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49697 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49698 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49699 GIR_RootConstrainSelectedInstOperands,
49700 // GIR_Coverage, 5861,
49701 GIR_EraseRootFromParent_Done,
49702 // Label 2891: @139763
49703 GIM_Try, /*On fail goto*//*Label 2892*/ GIMT_Encode4(139816), // Rule ID 5862 //
49704 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
49705 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
49706 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49707 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49708 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49709 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49710 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49711 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49712 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
49713 // MIs[1] Operand 1
49714 // No operand predicates
49715 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49716 // (intrinsic_wo_chain:{ *:[v1f64] } 727:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (SCVTFd:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
49717 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFd),
49718 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49719 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49720 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49721 GIR_RootConstrainSelectedInstOperands,
49722 // GIR_Coverage, 5862,
49723 GIR_EraseRootFromParent_Done,
49724 // Label 2892: @139816
49725 GIM_Try, /*On fail goto*//*Label 2893*/ GIMT_Encode4(139869), // Rule ID 5863 //
49726 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
49727 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
49728 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49729 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49730 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49731 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49732 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49733 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49734 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
49735 // MIs[1] Operand 1
49736 // No operand predicates
49737 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49738 // (intrinsic_wo_chain:{ *:[f64] } 727:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (SCVTFd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
49739 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFd),
49740 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49741 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49742 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49743 GIR_RootConstrainSelectedInstOperands,
49744 // GIR_Coverage, 5863,
49745 GIR_EraseRootFromParent_Done,
49746 // Label 2893: @139869
49747 GIM_Try, /*On fail goto*//*Label 2894*/ GIMT_Encode4(139922), // Rule ID 5864 //
49748 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
49749 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
49750 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49751 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49752 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49753 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49754 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49755 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49756 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
49757 // MIs[1] Operand 1
49758 // No operand predicates
49759 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49760 // (intrinsic_wo_chain:{ *:[v1f64] } 728:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (UCVTFd:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
49761 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFd),
49762 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49763 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49764 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49765 GIR_RootConstrainSelectedInstOperands,
49766 // GIR_Coverage, 5864,
49767 GIR_EraseRootFromParent_Done,
49768 // Label 2894: @139922
49769 GIM_Try, /*On fail goto*//*Label 2895*/ GIMT_Encode4(139975), // Rule ID 5865 //
49770 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
49771 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
49772 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
49773 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49774 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
49775 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
49776 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49777 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49778 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
49779 // MIs[1] Operand 1
49780 // No operand predicates
49781 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49782 // (intrinsic_wo_chain:{ *:[f32] } 727:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SCVTFs:{ *:[f32] } FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
49783 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFs),
49784 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49785 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
49786 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49787 GIR_RootConstrainSelectedInstOperands,
49788 // GIR_Coverage, 5865,
49789 GIR_EraseRootFromParent_Done,
49790 // Label 2895: @139975
49791 GIM_Try, /*On fail goto*//*Label 2896*/ GIMT_Encode4(140057), // Rule ID 5867 //
49792 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
49793 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
49794 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
49795 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49796 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
49797 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
49798 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49799 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49800 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
49801 // MIs[1] Operand 1
49802 // No operand predicates
49803 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49804 // (intrinsic_wo_chain:{ *:[f16] } 727:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (SCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)
49805 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
49806 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49807 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49808 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(7), // Rn
49809 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
49810 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
49811 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFh),
49812 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49813 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49814 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49815 GIR_RootConstrainSelectedInstOperands,
49816 // GIR_Coverage, 5867,
49817 GIR_EraseRootFromParent_Done,
49818 // Label 2896: @140057
49819 GIM_Try, /*On fail goto*//*Label 2897*/ GIMT_Encode4(140139), // Rule ID 5868 //
49820 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
49821 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
49822 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49823 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49824 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
49825 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49826 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49827 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49828 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
49829 // MIs[1] Operand 1
49830 // No operand predicates
49831 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49832 // (intrinsic_wo_chain:{ *:[f16] } 727:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (SCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)
49833 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
49834 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49835 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49836 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(7), // Rn
49837 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
49838 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
49839 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFh),
49840 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49841 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49842 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49843 GIR_RootConstrainSelectedInstOperands,
49844 // GIR_Coverage, 5868,
49845 GIR_EraseRootFromParent_Done,
49846 // Label 2897: @140139
49847 GIM_Try, /*On fail goto*//*Label 2898*/ GIMT_Encode4(140221), // Rule ID 5870 //
49848 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
49849 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
49850 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
49851 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49852 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
49853 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
49854 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49855 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49856 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
49857 // MIs[1] Operand 1
49858 // No operand predicates
49859 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49860 // (intrinsic_wo_chain:{ *:[f16] } 728:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)
49861 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
49862 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49863 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49864 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(7), // Rn
49865 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
49866 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
49867 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFh),
49868 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49869 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49870 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49871 GIR_RootConstrainSelectedInstOperands,
49872 // GIR_Coverage, 5870,
49873 GIR_EraseRootFromParent_Done,
49874 // Label 2898: @140221
49875 GIM_Try, /*On fail goto*//*Label 2899*/ GIMT_Encode4(140303), // Rule ID 5871 //
49876 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
49877 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
49878 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49879 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49880 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
49881 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49882 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49883 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49884 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
49885 // MIs[1] Operand 1
49886 // No operand predicates
49887 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49888 // (intrinsic_wo_chain:{ *:[f16] } 728:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, hsub:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)
49889 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
49890 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
49891 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49892 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(7), // Rn
49893 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
49894 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
49895 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFh),
49896 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
49897 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49898 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
49899 GIR_RootConstrainSelectedInstOperands,
49900 // GIR_Coverage, 5871,
49901 GIR_EraseRootFromParent_Done,
49902 // Label 2899: @140303
49903 GIM_Try, /*On fail goto*//*Label 2900*/ GIMT_Encode4(140409), // Rule ID 5872 //
49904 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
49905 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
49906 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
49907 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49908 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
49909 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
49910 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49911 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49912 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
49913 // MIs[1] Operand 1
49914 // No operand predicates
49915 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49916 // (intrinsic_wo_chain:{ *:[i32] } 724:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FCVTZSh:{ *:[i16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), hsub:{ *:[i32] })
49917 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
49918 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
49919 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSh),
49920 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49921 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
49922 GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
49923 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49924 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
49925 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49926 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
49927 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
49928 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49929 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49930 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
49931 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
49932 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
49933 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
49934 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
49935 // GIR_Coverage, 5872,
49936 GIR_EraseRootFromParent_Done,
49937 // Label 2900: @140409
49938 GIM_Try, /*On fail goto*//*Label 2901*/ GIMT_Encode4(140515), // Rule ID 5873 //
49939 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
49940 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
49941 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
49942 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49943 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
49944 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
49945 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49946 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49947 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
49948 // MIs[1] Operand 1
49949 // No operand predicates
49950 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49951 // (intrinsic_wo_chain:{ *:[i64] } 724:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (FCVTZSh:{ *:[i16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), hsub:{ *:[i32] })
49952 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
49953 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
49954 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSh),
49955 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49956 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
49957 GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
49958 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49959 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
49960 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49961 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
49962 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
49963 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49964 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49965 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
49966 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
49967 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
49968 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
49969 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
49970 // GIR_Coverage, 5873,
49971 GIR_EraseRootFromParent_Done,
49972 // Label 2901: @140515
49973 GIM_Try, /*On fail goto*//*Label 2902*/ GIMT_Encode4(140621), // Rule ID 5874 //
49974 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
49975 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
49976 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
49977 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49978 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
49979 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
49980 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49981 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
49982 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
49983 // MIs[1] Operand 1
49984 // No operand predicates
49985 GIM_CheckIsSafeToFold, /*NumInsns*/1,
49986 // (intrinsic_wo_chain:{ *:[i32] } 725:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FCVTZUh:{ *:[i16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), hsub:{ *:[i32] })
49987 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
49988 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
49989 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUh),
49990 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49991 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
49992 GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
49993 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
49994 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
49995 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
49996 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
49997 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
49998 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
49999 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50000 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
50001 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
50002 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
50003 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
50004 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
50005 // GIR_Coverage, 5874,
50006 GIR_EraseRootFromParent_Done,
50007 // Label 2902: @140621
50008 GIM_Try, /*On fail goto*//*Label 2903*/ GIMT_Encode4(140727), // Rule ID 5875 //
50009 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
50010 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
50011 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
50012 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
50013 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
50014 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
50015 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
50016 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
50017 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
50018 // MIs[1] Operand 1
50019 // No operand predicates
50020 GIM_CheckIsSafeToFold, /*NumInsns*/1,
50021 // (intrinsic_wo_chain:{ *:[i64] } 725:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (FCVTZUh:{ *:[i16] } FPR16:{ *:[f16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), hsub:{ *:[i32] })
50022 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
50023 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
50024 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUh),
50025 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50026 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
50027 GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm
50028 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
50029 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
50030 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
50031 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50032 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
50033 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
50034 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50035 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
50036 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
50037 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
50038 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
50039 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
50040 // GIR_Coverage, 5875,
50041 GIR_EraseRootFromParent_Done,
50042 // Label 2903: @140727
50043 GIM_Try, /*On fail goto*//*Label 2904*/ GIMT_Encode4(140782), // Rule ID 6668 //
50044 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_blend),
50045 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
50046 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
50047 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
50048 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
50049 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
50050 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
50051 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
50052 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64_0_65535),
50053 // MIs[1] Operand 1
50054 // No operand predicates
50055 GIM_CheckIsSafeToFold, /*NumInsns*/1,
50056 // (intrinsic_wo_chain:{ *:[i64] } 285:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_imm64_0_65535>>:$imm) => (PAUTH_BLEND:{ *:[i64] } GPR64:{ *:[i64] }:$Rd, (trunc_imm:{ *:[i32] } (imm:{ *:[i64] })<<P:Predicate_imm64_0_65535>>:$imm))
50057 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PAUTH_BLEND),
50058 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[disc]
50059 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
50060 GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // imm
50061 GIR_RootConstrainSelectedInstOperands,
50062 // GIR_Coverage, 6668,
50063 GIR_EraseRootFromParent_Done,
50064 // Label 2904: @140782
50065 GIM_Try, /*On fail goto*//*Label 2905*/ GIMT_Encode4(140824), // Rule ID 2970 //
50066 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50067 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sshllb),
50068 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
50069 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
50070 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50071 // MIs[0] Op2
50072 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50073 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL8),
50074 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1645:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op2) => (SSHLLB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op2)
50075 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLB_ZZI_H),
50076 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50077 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50078 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50079 GIR_RootConstrainSelectedInstOperands,
50080 // GIR_Coverage, 2970,
50081 GIR_EraseRootFromParent_Done,
50082 // Label 2905: @140824
50083 GIM_Try, /*On fail goto*//*Label 2906*/ GIMT_Encode4(140866), // Rule ID 2971 //
50084 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50085 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sshllb),
50086 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
50087 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
50088 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50089 // MIs[0] Op2
50090 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50091 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL16),
50092 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1645:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op2) => (SSHLLB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op2)
50093 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLB_ZZI_S),
50094 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50095 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50096 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50097 GIR_RootConstrainSelectedInstOperands,
50098 // GIR_Coverage, 2971,
50099 GIR_EraseRootFromParent_Done,
50100 // Label 2906: @140866
50101 GIM_Try, /*On fail goto*//*Label 2907*/ GIMT_Encode4(140908), // Rule ID 2972 //
50102 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50103 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sshllb),
50104 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
50105 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
50106 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50107 // MIs[0] Op2
50108 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50109 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL32),
50110 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1645:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op2) => (SSHLLB_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op2)
50111 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLB_ZZI_D),
50112 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50113 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50114 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50115 GIR_RootConstrainSelectedInstOperands,
50116 // GIR_Coverage, 2972,
50117 GIR_EraseRootFromParent_Done,
50118 // Label 2907: @140908
50119 GIM_Try, /*On fail goto*//*Label 2908*/ GIMT_Encode4(140950), // Rule ID 3006 //
50120 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50121 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrunb),
50122 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
50123 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
50124 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50125 // MIs[0] Op2
50126 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50127 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
50128 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1626:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2) => (SQSHRUNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)
50129 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNB_ZZI_B),
50130 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50131 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50132 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50133 GIR_RootConstrainSelectedInstOperands,
50134 // GIR_Coverage, 3006,
50135 GIR_EraseRootFromParent_Done,
50136 // Label 2908: @140950
50137 GIM_Try, /*On fail goto*//*Label 2909*/ GIMT_Encode4(140992), // Rule ID 3007 //
50138 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50139 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrunb),
50140 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
50141 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
50142 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50143 // MIs[0] Op2
50144 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50145 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
50146 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1626:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2) => (SQSHRUNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)
50147 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNB_ZZI_H),
50148 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50149 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50150 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50151 GIR_RootConstrainSelectedInstOperands,
50152 // GIR_Coverage, 3007,
50153 GIR_EraseRootFromParent_Done,
50154 // Label 2909: @140992
50155 GIM_Try, /*On fail goto*//*Label 2910*/ GIMT_Encode4(141034), // Rule ID 3008 //
50156 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50157 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrunb),
50158 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
50159 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
50160 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50161 // MIs[0] Op2
50162 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50163 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
50164 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1626:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2) => (SQSHRUNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)
50165 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNB_ZZI_S),
50166 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50167 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50168 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50169 GIR_RootConstrainSelectedInstOperands,
50170 // GIR_Coverage, 3008,
50171 GIR_EraseRootFromParent_Done,
50172 // Label 2910: @141034
50173 GIM_Try, /*On fail goto*//*Label 2911*/ GIMT_Encode4(141076), // Rule ID 3451 //
50174 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
50175 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
50176 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
50177 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
50178 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50179 // MIs[0] Op2
50180 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50181 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB32b_timm),
50182 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1161:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexB32b_timm>>:$Op2) => (DUPQ_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexB32b_timm>>:$Op2)
50183 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_B),
50184 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50185 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50186 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50187 GIR_RootConstrainSelectedInstOperands,
50188 // GIR_Coverage, 3451,
50189 GIR_EraseRootFromParent_Done,
50190 // Label 2911: @141076
50191 GIM_Try, /*On fail goto*//*Label 2912*/ GIMT_Encode4(141118), // Rule ID 3452 //
50192 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
50193 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
50194 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
50195 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
50196 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50197 // MIs[0] Op2
50198 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50199 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
50200 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1161:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op2) => (DUPQ_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op2)
50201 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_H),
50202 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50203 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50204 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50205 GIR_RootConstrainSelectedInstOperands,
50206 // GIR_Coverage, 3452,
50207 GIR_EraseRootFromParent_Done,
50208 // Label 2912: @141118
50209 GIM_Try, /*On fail goto*//*Label 2913*/ GIMT_Encode4(141160), // Rule ID 3453 //
50210 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
50211 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
50212 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
50213 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
50214 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50215 // MIs[0] Op2
50216 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50217 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
50218 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1161:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op2) => (DUPQ_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op2)
50219 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_S),
50220 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50221 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50222 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50223 GIR_RootConstrainSelectedInstOperands,
50224 // GIR_Coverage, 3453,
50225 GIR_EraseRootFromParent_Done,
50226 // Label 2913: @141160
50227 GIM_Try, /*On fail goto*//*Label 2914*/ GIMT_Encode4(141202), // Rule ID 3454 //
50228 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
50229 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
50230 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
50231 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
50232 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50233 // MIs[0] Op2
50234 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50235 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
50236 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1161:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op2) => (DUPQ_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op2)
50237 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_D),
50238 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50239 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50240 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50241 GIR_RootConstrainSelectedInstOperands,
50242 // GIR_Coverage, 3454,
50243 GIR_EraseRootFromParent_Done,
50244 // Label 2914: @141202
50245 GIM_Try, /*On fail goto*//*Label 2915*/ GIMT_Encode4(141244), // Rule ID 3455 //
50246 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
50247 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
50248 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
50249 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
50250 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50251 // MIs[0] Op2
50252 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50253 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
50254 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1161:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op2) => (DUPQ_ZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op2)
50255 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_H),
50256 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50257 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50258 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50259 GIR_RootConstrainSelectedInstOperands,
50260 // GIR_Coverage, 3455,
50261 GIR_EraseRootFromParent_Done,
50262 // Label 2915: @141244
50263 GIM_Try, /*On fail goto*//*Label 2916*/ GIMT_Encode4(141286), // Rule ID 3456 //
50264 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
50265 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
50266 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
50267 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
50268 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50269 // MIs[0] Op2
50270 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50271 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
50272 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1161:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op2) => (DUPQ_ZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op2)
50273 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_S),
50274 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50275 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50276 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50277 GIR_RootConstrainSelectedInstOperands,
50278 // GIR_Coverage, 3456,
50279 GIR_EraseRootFromParent_Done,
50280 // Label 2916: @141286
50281 GIM_Try, /*On fail goto*//*Label 2917*/ GIMT_Encode4(141328), // Rule ID 3457 //
50282 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
50283 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
50284 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
50285 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
50286 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50287 // MIs[0] Op2
50288 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50289 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
50290 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1161:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op2) => (DUPQ_ZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op2)
50291 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_D),
50292 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50293 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50294 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50295 GIR_RootConstrainSelectedInstOperands,
50296 // GIR_Coverage, 3457,
50297 GIR_EraseRootFromParent_Done,
50298 // Label 2917: @141328
50299 GIM_Try, /*On fail goto*//*Label 2918*/ GIMT_Encode4(141370), // Rule ID 3458 //
50300 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
50301 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
50302 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
50303 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
50304 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50305 // MIs[0] Op2
50306 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50307 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
50308 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1161:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op2) => (DUPQ_ZZI_H:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op2)
50309 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_H),
50310 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50311 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50312 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50313 GIR_RootConstrainSelectedInstOperands,
50314 // GIR_Coverage, 3458,
50315 GIR_EraseRootFromParent_Done,
50316 // Label 2918: @141370
50317 GIM_Try, /*On fail goto*//*Label 2919*/ GIMT_Encode4(141412), // Rule ID 11409 //
50318 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50319 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrunb),
50320 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
50321 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
50322 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50323 // MIs[0] Op2
50324 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50325 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
50326 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1620:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2) => (SQRSHRUNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)
50327 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNB_ZZI_B),
50328 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50329 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50330 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50331 GIR_RootConstrainSelectedInstOperands,
50332 // GIR_Coverage, 11409,
50333 GIR_EraseRootFromParent_Done,
50334 // Label 2919: @141412
50335 GIM_Try, /*On fail goto*//*Label 2920*/ GIMT_Encode4(141454), // Rule ID 11410 //
50336 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50337 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrunb),
50338 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
50339 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
50340 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50341 // MIs[0] Op2
50342 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50343 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
50344 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1620:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2) => (SQRSHRUNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)
50345 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNB_ZZI_H),
50346 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50347 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50348 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50349 GIR_RootConstrainSelectedInstOperands,
50350 // GIR_Coverage, 11410,
50351 GIR_EraseRootFromParent_Done,
50352 // Label 2920: @141454
50353 GIM_Try, /*On fail goto*//*Label 2921*/ GIMT_Encode4(141496), // Rule ID 11411 //
50354 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50355 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrunb),
50356 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
50357 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
50358 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50359 // MIs[0] Op2
50360 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50361 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
50362 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1620:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2) => (SQRSHRUNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)
50363 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNB_ZZI_S),
50364 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50365 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50366 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50367 GIR_RootConstrainSelectedInstOperands,
50368 // GIR_Coverage, 11411,
50369 GIR_EraseRootFromParent_Done,
50370 // Label 2921: @141496
50371 GIM_Try, /*On fail goto*//*Label 2922*/ GIMT_Encode4(141538), // Rule ID 11412 //
50372 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50373 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shrnb),
50374 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
50375 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
50376 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50377 // MIs[0] Op2
50378 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50379 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
50380 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1499:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2) => (SHRNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)
50381 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNB_ZZI_B),
50382 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50383 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50384 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50385 GIR_RootConstrainSelectedInstOperands,
50386 // GIR_Coverage, 11412,
50387 GIR_EraseRootFromParent_Done,
50388 // Label 2922: @141538
50389 GIM_Try, /*On fail goto*//*Label 2923*/ GIMT_Encode4(141580), // Rule ID 11413 //
50390 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50391 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shrnb),
50392 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
50393 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
50394 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50395 // MIs[0] Op2
50396 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50397 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
50398 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1499:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2) => (SHRNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)
50399 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNB_ZZI_H),
50400 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50401 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50402 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50403 GIR_RootConstrainSelectedInstOperands,
50404 // GIR_Coverage, 11413,
50405 GIR_EraseRootFromParent_Done,
50406 // Label 2923: @141580
50407 GIM_Try, /*On fail goto*//*Label 2924*/ GIMT_Encode4(141622), // Rule ID 11414 //
50408 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50409 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shrnb),
50410 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
50411 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
50412 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50413 // MIs[0] Op2
50414 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50415 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
50416 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1499:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2) => (SHRNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)
50417 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNB_ZZI_S),
50418 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50419 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50420 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50421 GIR_RootConstrainSelectedInstOperands,
50422 // GIR_Coverage, 11414,
50423 GIR_EraseRootFromParent_Done,
50424 // Label 2924: @141622
50425 GIM_Try, /*On fail goto*//*Label 2925*/ GIMT_Encode4(141664), // Rule ID 11416 //
50426 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50427 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rshrnb),
50428 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
50429 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
50430 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50431 // MIs[0] Op2
50432 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50433 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
50434 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1457:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2) => (RSHRNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)
50435 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNB_ZZI_B),
50436 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50437 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50438 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50439 GIR_RootConstrainSelectedInstOperands,
50440 // GIR_Coverage, 11416,
50441 GIR_EraseRootFromParent_Done,
50442 // Label 2925: @141664
50443 GIM_Try, /*On fail goto*//*Label 2926*/ GIMT_Encode4(141706), // Rule ID 11418 //
50444 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50445 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rshrnb),
50446 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
50447 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
50448 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50449 // MIs[0] Op2
50450 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50451 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
50452 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1457:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2) => (RSHRNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)
50453 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNB_ZZI_H),
50454 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50455 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50456 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50457 GIR_RootConstrainSelectedInstOperands,
50458 // GIR_Coverage, 11418,
50459 GIR_EraseRootFromParent_Done,
50460 // Label 2926: @141706
50461 GIM_Try, /*On fail goto*//*Label 2927*/ GIMT_Encode4(141748), // Rule ID 11420 //
50462 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50463 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rshrnb),
50464 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
50465 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
50466 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50467 // MIs[0] Op2
50468 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50469 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
50470 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1457:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2) => (RSHRNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)
50471 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNB_ZZI_S),
50472 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50473 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50474 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50475 GIR_RootConstrainSelectedInstOperands,
50476 // GIR_Coverage, 11420,
50477 GIR_EraseRootFromParent_Done,
50478 // Label 2927: @141748
50479 GIM_Try, /*On fail goto*//*Label 2928*/ GIMT_Encode4(141790), // Rule ID 11421 //
50480 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50481 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrnb),
50482 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
50483 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
50484 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50485 // MIs[0] Op2
50486 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50487 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
50488 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1624:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2) => (SQSHRNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)
50489 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNB_ZZI_B),
50490 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50491 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50492 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50493 GIR_RootConstrainSelectedInstOperands,
50494 // GIR_Coverage, 11421,
50495 GIR_EraseRootFromParent_Done,
50496 // Label 2928: @141790
50497 GIM_Try, /*On fail goto*//*Label 2929*/ GIMT_Encode4(141832), // Rule ID 11422 //
50498 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50499 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrnb),
50500 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
50501 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
50502 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50503 // MIs[0] Op2
50504 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50505 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
50506 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1624:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2) => (SQSHRNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)
50507 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNB_ZZI_H),
50508 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50509 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50510 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50511 GIR_RootConstrainSelectedInstOperands,
50512 // GIR_Coverage, 11422,
50513 GIR_EraseRootFromParent_Done,
50514 // Label 2929: @141832
50515 GIM_Try, /*On fail goto*//*Label 2930*/ GIMT_Encode4(141874), // Rule ID 11423 //
50516 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50517 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrnb),
50518 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
50519 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
50520 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50521 // MIs[0] Op2
50522 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50523 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
50524 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1624:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2) => (SQSHRNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)
50525 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNB_ZZI_S),
50526 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50527 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50528 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50529 GIR_RootConstrainSelectedInstOperands,
50530 // GIR_Coverage, 11423,
50531 GIR_EraseRootFromParent_Done,
50532 // Label 2930: @141874
50533 GIM_Try, /*On fail goto*//*Label 2931*/ GIMT_Encode4(141916), // Rule ID 11424 //
50534 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50535 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrnb),
50536 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
50537 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
50538 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50539 // MIs[0] Op2
50540 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50541 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
50542 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1614:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2) => (SQRSHRNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)
50543 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNB_ZZI_B),
50544 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50545 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50546 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50547 GIR_RootConstrainSelectedInstOperands,
50548 // GIR_Coverage, 11424,
50549 GIR_EraseRootFromParent_Done,
50550 // Label 2931: @141916
50551 GIM_Try, /*On fail goto*//*Label 2932*/ GIMT_Encode4(141958), // Rule ID 11425 //
50552 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50553 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrnb),
50554 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
50555 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
50556 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50557 // MIs[0] Op2
50558 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50559 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
50560 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1614:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2) => (SQRSHRNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)
50561 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNB_ZZI_H),
50562 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50563 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50564 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50565 GIR_RootConstrainSelectedInstOperands,
50566 // GIR_Coverage, 11425,
50567 GIR_EraseRootFromParent_Done,
50568 // Label 2932: @141958
50569 GIM_Try, /*On fail goto*//*Label 2933*/ GIMT_Encode4(142000), // Rule ID 11426 //
50570 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50571 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrnb),
50572 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
50573 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
50574 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50575 // MIs[0] Op2
50576 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50577 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
50578 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1614:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2) => (SQRSHRNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)
50579 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNB_ZZI_S),
50580 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50581 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50582 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50583 GIR_RootConstrainSelectedInstOperands,
50584 // GIR_Coverage, 11426,
50585 GIR_EraseRootFromParent_Done,
50586 // Label 2933: @142000
50587 GIM_Try, /*On fail goto*//*Label 2934*/ GIMT_Encode4(142042), // Rule ID 11427 //
50588 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50589 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshrnb),
50590 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
50591 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
50592 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50593 // MIs[0] Op2
50594 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50595 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
50596 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1819:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2) => (UQSHRNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)
50597 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNB_ZZI_B),
50598 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50599 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50600 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50601 GIR_RootConstrainSelectedInstOperands,
50602 // GIR_Coverage, 11427,
50603 GIR_EraseRootFromParent_Done,
50604 // Label 2934: @142042
50605 GIM_Try, /*On fail goto*//*Label 2935*/ GIMT_Encode4(142084), // Rule ID 11428 //
50606 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50607 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshrnb),
50608 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
50609 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
50610 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50611 // MIs[0] Op2
50612 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50613 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
50614 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1819:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2) => (UQSHRNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)
50615 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNB_ZZI_H),
50616 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50617 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50618 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50619 GIR_RootConstrainSelectedInstOperands,
50620 // GIR_Coverage, 11428,
50621 GIR_EraseRootFromParent_Done,
50622 // Label 2935: @142084
50623 GIM_Try, /*On fail goto*//*Label 2936*/ GIMT_Encode4(142126), // Rule ID 11429 //
50624 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50625 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshrnb),
50626 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
50627 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
50628 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50629 // MIs[0] Op2
50630 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50631 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
50632 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1819:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2) => (UQSHRNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)
50633 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNB_ZZI_S),
50634 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50635 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50636 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50637 GIR_RootConstrainSelectedInstOperands,
50638 // GIR_Coverage, 11429,
50639 GIR_EraseRootFromParent_Done,
50640 // Label 2936: @142126
50641 GIM_Try, /*On fail goto*//*Label 2937*/ GIMT_Encode4(142168), // Rule ID 11430 //
50642 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50643 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshrnb),
50644 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
50645 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
50646 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50647 // MIs[0] Op2
50648 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50649 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
50650 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1816:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2) => (UQRSHRNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op2)
50651 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNB_ZZI_B),
50652 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50653 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50654 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50655 GIR_RootConstrainSelectedInstOperands,
50656 // GIR_Coverage, 11430,
50657 GIR_EraseRootFromParent_Done,
50658 // Label 2937: @142168
50659 GIM_Try, /*On fail goto*//*Label 2938*/ GIMT_Encode4(142210), // Rule ID 11431 //
50660 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50661 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshrnb),
50662 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
50663 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
50664 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50665 // MIs[0] Op2
50666 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50667 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
50668 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1816:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2) => (UQRSHRNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op2)
50669 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNB_ZZI_H),
50670 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50671 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50672 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50673 GIR_RootConstrainSelectedInstOperands,
50674 // GIR_Coverage, 11431,
50675 GIR_EraseRootFromParent_Done,
50676 // Label 2938: @142210
50677 GIM_Try, /*On fail goto*//*Label 2939*/ GIMT_Encode4(142252), // Rule ID 11432 //
50678 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50679 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshrnb),
50680 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
50681 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
50682 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50683 // MIs[0] Op2
50684 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50685 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
50686 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1816:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2) => (UQRSHRNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op2)
50687 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNB_ZZI_S),
50688 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50689 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50690 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50691 GIR_RootConstrainSelectedInstOperands,
50692 // GIR_Coverage, 11432,
50693 GIR_EraseRootFromParent_Done,
50694 // Label 2939: @142252
50695 GIM_Try, /*On fail goto*//*Label 2940*/ GIMT_Encode4(142294), // Rule ID 11490 //
50696 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50697 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sshllt),
50698 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
50699 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
50700 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50701 // MIs[0] Op2
50702 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50703 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL8),
50704 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1646:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op2) => (SSHLLT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op2)
50705 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLT_ZZI_H),
50706 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50707 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50708 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50709 GIR_RootConstrainSelectedInstOperands,
50710 // GIR_Coverage, 11490,
50711 GIR_EraseRootFromParent_Done,
50712 // Label 2940: @142294
50713 GIM_Try, /*On fail goto*//*Label 2941*/ GIMT_Encode4(142336), // Rule ID 11491 //
50714 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50715 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sshllt),
50716 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
50717 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
50718 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50719 // MIs[0] Op2
50720 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50721 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL16),
50722 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1646:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op2) => (SSHLLT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op2)
50723 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLT_ZZI_S),
50724 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50725 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50726 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50727 GIR_RootConstrainSelectedInstOperands,
50728 // GIR_Coverage, 11491,
50729 GIR_EraseRootFromParent_Done,
50730 // Label 2941: @142336
50731 GIM_Try, /*On fail goto*//*Label 2942*/ GIMT_Encode4(142378), // Rule ID 11492 //
50732 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50733 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sshllt),
50734 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
50735 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
50736 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50737 // MIs[0] Op2
50738 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50739 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL32),
50740 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1646:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op2) => (SSHLLT_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op2)
50741 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLT_ZZI_D),
50742 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50743 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50744 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50745 GIR_RootConstrainSelectedInstOperands,
50746 // GIR_Coverage, 11492,
50747 GIR_EraseRootFromParent_Done,
50748 // Label 2942: @142378
50749 GIM_Try, /*On fail goto*//*Label 2943*/ GIMT_Encode4(142420), // Rule ID 11493 //
50750 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50751 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ushllb),
50752 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
50753 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
50754 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50755 // MIs[0] Op2
50756 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50757 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL8),
50758 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1839:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op2) => (USHLLB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op2)
50759 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLB_ZZI_H),
50760 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50761 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50762 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50763 GIR_RootConstrainSelectedInstOperands,
50764 // GIR_Coverage, 11493,
50765 GIR_EraseRootFromParent_Done,
50766 // Label 2943: @142420
50767 GIM_Try, /*On fail goto*//*Label 2944*/ GIMT_Encode4(142462), // Rule ID 11494 //
50768 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50769 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ushllb),
50770 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
50771 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
50772 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50773 // MIs[0] Op2
50774 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50775 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL16),
50776 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1839:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op2) => (USHLLB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op2)
50777 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLB_ZZI_S),
50778 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50779 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50780 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50781 GIR_RootConstrainSelectedInstOperands,
50782 // GIR_Coverage, 11494,
50783 GIR_EraseRootFromParent_Done,
50784 // Label 2944: @142462
50785 GIM_Try, /*On fail goto*//*Label 2945*/ GIMT_Encode4(142504), // Rule ID 11495 //
50786 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50787 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ushllb),
50788 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
50789 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
50790 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50791 // MIs[0] Op2
50792 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50793 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL32),
50794 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1839:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op2) => (USHLLB_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op2)
50795 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLB_ZZI_D),
50796 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50797 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50798 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50799 GIR_RootConstrainSelectedInstOperands,
50800 // GIR_Coverage, 11495,
50801 GIR_EraseRootFromParent_Done,
50802 // Label 2945: @142504
50803 GIM_Try, /*On fail goto*//*Label 2946*/ GIMT_Encode4(142546), // Rule ID 11496 //
50804 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50805 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ushllt),
50806 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
50807 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
50808 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50809 // MIs[0] Op2
50810 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50811 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL8),
50812 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1840:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op2) => (USHLLT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op2)
50813 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLT_ZZI_H),
50814 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50815 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50816 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50817 GIR_RootConstrainSelectedInstOperands,
50818 // GIR_Coverage, 11496,
50819 GIR_EraseRootFromParent_Done,
50820 // Label 2946: @142546
50821 GIM_Try, /*On fail goto*//*Label 2947*/ GIMT_Encode4(142588), // Rule ID 11497 //
50822 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50823 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ushllt),
50824 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
50825 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
50826 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50827 // MIs[0] Op2
50828 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50829 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL16),
50830 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1840:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op2) => (USHLLT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op2)
50831 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLT_ZZI_S),
50832 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50833 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50834 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50835 GIR_RootConstrainSelectedInstOperands,
50836 // GIR_Coverage, 11497,
50837 GIR_EraseRootFromParent_Done,
50838 // Label 2947: @142588
50839 GIM_Try, /*On fail goto*//*Label 2948*/ GIMT_Encode4(142630), // Rule ID 11498 //
50840 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
50841 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ushllt),
50842 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
50843 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
50844 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
50845 // MIs[0] Op2
50846 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
50847 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL32),
50848 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1840:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op2) => (USHLLT_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op2)
50849 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLT_ZZI_D),
50850 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
50851 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
50852 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
50853 GIR_RootConstrainSelectedInstOperands,
50854 // GIR_Coverage, 11498,
50855 GIR_EraseRootFromParent_Done,
50856 // Label 2948: @142630
50857 GIM_Try, /*On fail goto*//*Label 2949*/ GIMT_Encode4(142682), // Rule ID 2117 //
50858 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
50859 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
50860 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
50861 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
50862 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
50863 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
50864 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
50865 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
50866 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
50867 // MIs[1] Operand 1
50868 // No operand predicates
50869 GIM_CheckIsSafeToFold, /*NumInsns*/1,
50870 // (intrinsic_wo_chain:{ *:[v4i16] } 724:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv4i16_shift:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm)
50871 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4i16_shift),
50872 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
50873 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
50874 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
50875 GIR_RootConstrainSelectedInstOperands,
50876 // GIR_Coverage, 2117,
50877 GIR_EraseRootFromParent_Done,
50878 // Label 2949: @142682
50879 GIM_Try, /*On fail goto*//*Label 2950*/ GIMT_Encode4(142734), // Rule ID 2118 //
50880 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
50881 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
50882 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
50883 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
50884 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
50885 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
50886 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
50887 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
50888 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
50889 // MIs[1] Operand 1
50890 // No operand predicates
50891 GIM_CheckIsSafeToFold, /*NumInsns*/1,
50892 // (intrinsic_wo_chain:{ *:[v8i16] } 724:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv8i16_shift:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm)
50893 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv8i16_shift),
50894 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
50895 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
50896 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
50897 GIR_RootConstrainSelectedInstOperands,
50898 // GIR_Coverage, 2118,
50899 GIR_EraseRootFromParent_Done,
50900 // Label 2950: @142734
50901 GIM_Try, /*On fail goto*//*Label 2951*/ GIMT_Encode4(142786), // Rule ID 2119 //
50902 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
50903 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
50904 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
50905 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
50906 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
50907 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
50908 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
50909 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
50910 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
50911 // MIs[1] Operand 1
50912 // No operand predicates
50913 GIM_CheckIsSafeToFold, /*NumInsns*/1,
50914 // (intrinsic_wo_chain:{ *:[v2i32] } 724:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv2i32_shift:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm)
50915 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2i32_shift),
50916 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
50917 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
50918 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
50919 GIR_RootConstrainSelectedInstOperands,
50920 // GIR_Coverage, 2119,
50921 GIR_EraseRootFromParent_Done,
50922 // Label 2951: @142786
50923 GIM_Try, /*On fail goto*//*Label 2952*/ GIMT_Encode4(142838), // Rule ID 2120 //
50924 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
50925 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
50926 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
50927 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
50928 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
50929 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
50930 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
50931 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
50932 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
50933 // MIs[1] Operand 1
50934 // No operand predicates
50935 GIM_CheckIsSafeToFold, /*NumInsns*/1,
50936 // (intrinsic_wo_chain:{ *:[v4i32] } 724:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv4i32_shift:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm)
50937 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4i32_shift),
50938 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
50939 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
50940 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
50941 GIR_RootConstrainSelectedInstOperands,
50942 // GIR_Coverage, 2120,
50943 GIR_EraseRootFromParent_Done,
50944 // Label 2952: @142838
50945 GIM_Try, /*On fail goto*//*Label 2953*/ GIMT_Encode4(142890), // Rule ID 2121 //
50946 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
50947 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
50948 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
50949 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
50950 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
50951 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
50952 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
50953 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
50954 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
50955 // MIs[1] Operand 1
50956 // No operand predicates
50957 GIM_CheckIsSafeToFold, /*NumInsns*/1,
50958 // (intrinsic_wo_chain:{ *:[v2i64] } 724:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZSv2i64_shift:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm)
50959 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2i64_shift),
50960 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
50961 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
50962 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
50963 GIR_RootConstrainSelectedInstOperands,
50964 // GIR_Coverage, 2121,
50965 GIR_EraseRootFromParent_Done,
50966 // Label 2953: @142890
50967 GIM_Try, /*On fail goto*//*Label 2954*/ GIMT_Encode4(142942), // Rule ID 2122 //
50968 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
50969 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
50970 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
50971 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
50972 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
50973 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
50974 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
50975 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
50976 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
50977 // MIs[1] Operand 1
50978 // No operand predicates
50979 GIM_CheckIsSafeToFold, /*NumInsns*/1,
50980 // (intrinsic_wo_chain:{ *:[v4i16] } 725:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv4i16_shift:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i32] }):$imm)
50981 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4i16_shift),
50982 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
50983 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
50984 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
50985 GIR_RootConstrainSelectedInstOperands,
50986 // GIR_Coverage, 2122,
50987 GIR_EraseRootFromParent_Done,
50988 // Label 2954: @142942
50989 GIM_Try, /*On fail goto*//*Label 2955*/ GIMT_Encode4(142994), // Rule ID 2123 //
50990 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
50991 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
50992 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
50993 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
50994 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
50995 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
50996 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
50997 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
50998 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
50999 // MIs[1] Operand 1
51000 // No operand predicates
51001 GIM_CheckIsSafeToFold, /*NumInsns*/1,
51002 // (intrinsic_wo_chain:{ *:[v8i16] } 725:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv8i16_shift:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm)
51003 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv8i16_shift),
51004 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51005 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51006 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
51007 GIR_RootConstrainSelectedInstOperands,
51008 // GIR_Coverage, 2123,
51009 GIR_EraseRootFromParent_Done,
51010 // Label 2955: @142994
51011 GIM_Try, /*On fail goto*//*Label 2956*/ GIMT_Encode4(143046), // Rule ID 2124 //
51012 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51013 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
51014 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
51015 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
51016 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51017 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51018 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51019 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51020 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51021 // MIs[1] Operand 1
51022 // No operand predicates
51023 GIM_CheckIsSafeToFold, /*NumInsns*/1,
51024 // (intrinsic_wo_chain:{ *:[v2i32] } 725:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv2i32_shift:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i32] }):$imm)
51025 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2i32_shift),
51026 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51027 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51028 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
51029 GIR_RootConstrainSelectedInstOperands,
51030 // GIR_Coverage, 2124,
51031 GIR_EraseRootFromParent_Done,
51032 // Label 2956: @143046
51033 GIM_Try, /*On fail goto*//*Label 2957*/ GIMT_Encode4(143098), // Rule ID 2125 //
51034 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51035 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
51036 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
51037 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
51038 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51039 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51040 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51041 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51042 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51043 // MIs[1] Operand 1
51044 // No operand predicates
51045 GIM_CheckIsSafeToFold, /*NumInsns*/1,
51046 // (intrinsic_wo_chain:{ *:[v4i32] } 725:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv4i32_shift:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm)
51047 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4i32_shift),
51048 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51049 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51050 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
51051 GIR_RootConstrainSelectedInstOperands,
51052 // GIR_Coverage, 2125,
51053 GIR_EraseRootFromParent_Done,
51054 // Label 2957: @143098
51055 GIM_Try, /*On fail goto*//*Label 2958*/ GIMT_Encode4(143150), // Rule ID 2126 //
51056 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51057 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
51058 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
51059 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
51060 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51061 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51062 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51063 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51064 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51065 // MIs[1] Operand 1
51066 // No operand predicates
51067 GIM_CheckIsSafeToFold, /*NumInsns*/1,
51068 // (intrinsic_wo_chain:{ *:[v2i64] } 725:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm) => (FCVTZUv2i64_shift:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm)
51069 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2i64_shift),
51070 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51071 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51072 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
51073 GIR_RootConstrainSelectedInstOperands,
51074 // GIR_Coverage, 2126,
51075 GIR_EraseRootFromParent_Done,
51076 // Label 2958: @143150
51077 GIM_Try, /*On fail goto*//*Label 2959*/ GIMT_Encode4(143202), // Rule ID 2127 //
51078 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
51079 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
51080 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
51081 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
51082 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51083 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51084 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51085 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51086 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51087 // MIs[1] Operand 1
51088 // No operand predicates
51089 GIM_CheckIsSafeToFold, /*NumInsns*/1,
51090 // (intrinsic_wo_chain:{ *:[v4f16] } 727:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv4i16_shift:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
51091 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv4i16_shift),
51092 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51093 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51094 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
51095 GIR_RootConstrainSelectedInstOperands,
51096 // GIR_Coverage, 2127,
51097 GIR_EraseRootFromParent_Done,
51098 // Label 2959: @143202
51099 GIM_Try, /*On fail goto*//*Label 2960*/ GIMT_Encode4(143254), // Rule ID 2128 //
51100 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
51101 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
51102 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
51103 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
51104 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51105 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51106 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51107 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51108 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51109 // MIs[1] Operand 1
51110 // No operand predicates
51111 GIM_CheckIsSafeToFold, /*NumInsns*/1,
51112 // (intrinsic_wo_chain:{ *:[v8f16] } 727:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv8i16_shift:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
51113 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv8i16_shift),
51114 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51115 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51116 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
51117 GIR_RootConstrainSelectedInstOperands,
51118 // GIR_Coverage, 2128,
51119 GIR_EraseRootFromParent_Done,
51120 // Label 2960: @143254
51121 GIM_Try, /*On fail goto*//*Label 2961*/ GIMT_Encode4(143306), // Rule ID 2129 //
51122 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51123 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
51124 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
51125 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
51126 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51127 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51128 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51129 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51130 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51131 // MIs[1] Operand 1
51132 // No operand predicates
51133 GIM_CheckIsSafeToFold, /*NumInsns*/1,
51134 // (intrinsic_wo_chain:{ *:[v2f32] } 727:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv2i32_shift:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
51135 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv2i32_shift),
51136 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51137 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51138 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
51139 GIR_RootConstrainSelectedInstOperands,
51140 // GIR_Coverage, 2129,
51141 GIR_EraseRootFromParent_Done,
51142 // Label 2961: @143306
51143 GIM_Try, /*On fail goto*//*Label 2962*/ GIMT_Encode4(143358), // Rule ID 2130 //
51144 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51145 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
51146 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
51147 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
51148 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51149 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51150 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51151 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51152 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51153 // MIs[1] Operand 1
51154 // No operand predicates
51155 GIM_CheckIsSafeToFold, /*NumInsns*/1,
51156 // (intrinsic_wo_chain:{ *:[v4f32] } 727:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv4i32_shift:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
51157 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv4i32_shift),
51158 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51159 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51160 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
51161 GIR_RootConstrainSelectedInstOperands,
51162 // GIR_Coverage, 2130,
51163 GIR_EraseRootFromParent_Done,
51164 // Label 2962: @143358
51165 GIM_Try, /*On fail goto*//*Label 2963*/ GIMT_Encode4(143410), // Rule ID 2131 //
51166 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51167 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
51168 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
51169 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
51170 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51171 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51172 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51173 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51174 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51175 // MIs[1] Operand 1
51176 // No operand predicates
51177 GIM_CheckIsSafeToFold, /*NumInsns*/1,
51178 // (intrinsic_wo_chain:{ *:[v2f64] } 727:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) => (SCVTFv2i64_shift:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
51179 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv2i64_shift),
51180 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51181 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51182 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
51183 GIR_RootConstrainSelectedInstOperands,
51184 // GIR_Coverage, 2131,
51185 GIR_EraseRootFromParent_Done,
51186 // Label 2963: @143410
51187 GIM_Try, /*On fail goto*//*Label 2964*/ GIMT_Encode4(143462), // Rule ID 2229 //
51188 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
51189 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
51190 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
51191 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
51192 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51193 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51194 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51195 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51196 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51197 // MIs[1] Operand 1
51198 // No operand predicates
51199 GIM_CheckIsSafeToFold, /*NumInsns*/1,
51200 // (intrinsic_wo_chain:{ *:[v4f16] } 728:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv4i16_shift:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
51201 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv4i16_shift),
51202 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51203 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51204 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
51205 GIR_RootConstrainSelectedInstOperands,
51206 // GIR_Coverage, 2229,
51207 GIR_EraseRootFromParent_Done,
51208 // Label 2964: @143462
51209 GIM_Try, /*On fail goto*//*Label 2965*/ GIMT_Encode4(143514), // Rule ID 2230 //
51210 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
51211 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
51212 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
51213 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
51214 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51215 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51216 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51217 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51218 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51219 // MIs[1] Operand 1
51220 // No operand predicates
51221 GIM_CheckIsSafeToFold, /*NumInsns*/1,
51222 // (intrinsic_wo_chain:{ *:[v8f16] } 728:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv8i16_shift:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
51223 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv8i16_shift),
51224 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51225 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51226 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
51227 GIR_RootConstrainSelectedInstOperands,
51228 // GIR_Coverage, 2230,
51229 GIR_EraseRootFromParent_Done,
51230 // Label 2965: @143514
51231 GIM_Try, /*On fail goto*//*Label 2966*/ GIMT_Encode4(143566), // Rule ID 2231 //
51232 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51233 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
51234 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
51235 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
51236 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51237 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51238 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51239 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51240 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51241 // MIs[1] Operand 1
51242 // No operand predicates
51243 GIM_CheckIsSafeToFold, /*NumInsns*/1,
51244 // (intrinsic_wo_chain:{ *:[v2f32] } 728:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv2i32_shift:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
51245 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv2i32_shift),
51246 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51247 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51248 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
51249 GIR_RootConstrainSelectedInstOperands,
51250 // GIR_Coverage, 2231,
51251 GIR_EraseRootFromParent_Done,
51252 // Label 2966: @143566
51253 GIM_Try, /*On fail goto*//*Label 2967*/ GIMT_Encode4(143618), // Rule ID 2232 //
51254 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51255 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
51256 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
51257 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
51258 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51259 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51260 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51261 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51262 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51263 // MIs[1] Operand 1
51264 // No operand predicates
51265 GIM_CheckIsSafeToFold, /*NumInsns*/1,
51266 // (intrinsic_wo_chain:{ *:[v4f32] } 728:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv4i32_shift:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
51267 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv4i32_shift),
51268 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51269 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51270 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
51271 GIR_RootConstrainSelectedInstOperands,
51272 // GIR_Coverage, 2232,
51273 GIR_EraseRootFromParent_Done,
51274 // Label 2967: @143618
51275 GIM_Try, /*On fail goto*//*Label 2968*/ GIMT_Encode4(143670), // Rule ID 2233 //
51276 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51277 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
51278 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
51279 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
51280 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51281 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51282 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51283 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
51284 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
51285 // MIs[1] Operand 1
51286 // No operand predicates
51287 GIM_CheckIsSafeToFold, /*NumInsns*/1,
51288 // (intrinsic_wo_chain:{ *:[v2f64] } 728:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm) => (UCVTFv2i64_shift:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
51289 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv2i64_shift),
51290 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51291 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51292 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
51293 GIR_RootConstrainSelectedInstOperands,
51294 // GIR_Coverage, 2233,
51295 GIR_EraseRootFromParent_Done,
51296 // Label 2968: @143670
51297 GIM_Try, /*On fail goto*//*Label 2969*/ GIMT_Encode4(143715), // Rule ID 40 //
51298 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON),
51299 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_bfcvtn2),
51300 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
51301 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
51302 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
51303 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51304 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51305 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51306 // (intrinsic_wo_chain:{ *:[v8bf16] } 555:{ *:[iPTR] }, V128:{ *:[v8bf16] }:$Rd, V128:{ *:[v4f32] }:$Rn) => (BFCVTN2:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rd, V128:{ *:[v4f32] }:$Rn)
51307 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN2),
51308 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51309 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
51310 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
51311 GIR_RootConstrainSelectedInstOperands,
51312 // GIR_Coverage, 40,
51313 GIR_EraseRootFromParent_Done,
51314 // Label 2969: @143715
51315 GIM_Try, /*On fail goto*//*Label 2970*/ GIMT_Encode4(143760), // Rule ID 75 //
51316 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
51317 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign_generic),
51318 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
51319 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
51320 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
51321 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
51322 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
51323 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
51324 // (intrinsic_wo_chain:{ *:[i64] } 288:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm) => (PACGA:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm)
51325 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PACGA),
51326 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51327 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51328 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51329 GIR_RootConstrainSelectedInstOperands,
51330 // GIR_Coverage, 75,
51331 GIR_EraseRootFromParent_Done,
51332 // Label 2970: @143760
51333 GIM_Try, /*On fail goto*//*Label 2971*/ GIMT_Encode4(143805), // Rule ID 140 //
51334 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
51335 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32b),
51336 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
51337 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
51338 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51339 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51340 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51341 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51342 // (intrinsic_wo_chain:{ *:[i32] } 485:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32Brr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
51343 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32Brr),
51344 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51345 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51346 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51347 GIR_RootConstrainSelectedInstOperands,
51348 // GIR_Coverage, 140,
51349 GIR_EraseRootFromParent_Done,
51350 // Label 2971: @143805
51351 GIM_Try, /*On fail goto*//*Label 2972*/ GIMT_Encode4(143850), // Rule ID 141 //
51352 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
51353 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32h),
51354 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
51355 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
51356 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51357 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51358 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51359 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51360 // (intrinsic_wo_chain:{ *:[i32] } 490:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32Hrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
51361 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32Hrr),
51362 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51363 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51364 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51365 GIR_RootConstrainSelectedInstOperands,
51366 // GIR_Coverage, 141,
51367 GIR_EraseRootFromParent_Done,
51368 // Label 2972: @143850
51369 GIM_Try, /*On fail goto*//*Label 2973*/ GIMT_Encode4(143895), // Rule ID 142 //
51370 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
51371 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32w),
51372 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
51373 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
51374 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51375 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51376 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51377 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51378 // (intrinsic_wo_chain:{ *:[i32] } 491:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32Wrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
51379 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32Wrr),
51380 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51381 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51382 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51383 GIR_RootConstrainSelectedInstOperands,
51384 // GIR_Coverage, 142,
51385 GIR_EraseRootFromParent_Done,
51386 // Label 2973: @143895
51387 GIM_Try, /*On fail goto*//*Label 2974*/ GIMT_Encode4(143940), // Rule ID 143 //
51388 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
51389 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32x),
51390 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
51391 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
51392 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
51393 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51394 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51395 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
51396 // (intrinsic_wo_chain:{ *:[i32] } 492:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (CRC32Xrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm)
51397 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32Xrr),
51398 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51399 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51400 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51401 GIR_RootConstrainSelectedInstOperands,
51402 // GIR_Coverage, 143,
51403 GIR_EraseRootFromParent_Done,
51404 // Label 2974: @143940
51405 GIM_Try, /*On fail goto*//*Label 2975*/ GIMT_Encode4(143985), // Rule ID 144 //
51406 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
51407 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32cb),
51408 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
51409 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
51410 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51411 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51412 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51413 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51414 // (intrinsic_wo_chain:{ *:[i32] } 486:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32CBrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
51415 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32CBrr),
51416 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51417 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51418 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51419 GIR_RootConstrainSelectedInstOperands,
51420 // GIR_Coverage, 144,
51421 GIR_EraseRootFromParent_Done,
51422 // Label 2975: @143985
51423 GIM_Try, /*On fail goto*//*Label 2976*/ GIMT_Encode4(144030), // Rule ID 145 //
51424 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
51425 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32ch),
51426 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
51427 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
51428 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51429 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51430 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51431 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51432 // (intrinsic_wo_chain:{ *:[i32] } 487:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32CHrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
51433 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32CHrr),
51434 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51435 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51436 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51437 GIR_RootConstrainSelectedInstOperands,
51438 // GIR_Coverage, 145,
51439 GIR_EraseRootFromParent_Done,
51440 // Label 2976: @144030
51441 GIM_Try, /*On fail goto*//*Label 2977*/ GIMT_Encode4(144075), // Rule ID 146 //
51442 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
51443 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32cw),
51444 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
51445 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
51446 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
51447 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51448 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51449 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51450 // (intrinsic_wo_chain:{ *:[i32] } 488:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (CRC32CWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
51451 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32CWrr),
51452 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51453 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51454 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51455 GIR_RootConstrainSelectedInstOperands,
51456 // GIR_Coverage, 146,
51457 GIR_EraseRootFromParent_Done,
51458 // Label 2977: @144075
51459 GIM_Try, /*On fail goto*//*Label 2978*/ GIMT_Encode4(144120), // Rule ID 147 //
51460 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
51461 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32cx),
51462 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
51463 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
51464 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
51465 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51466 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
51467 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
51468 // (intrinsic_wo_chain:{ *:[i32] } 489:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (CRC32CXrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm)
51469 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32CXrr),
51470 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51471 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51472 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51473 GIR_RootConstrainSelectedInstOperands,
51474 // GIR_Coverage, 147,
51475 GIR_EraseRootFromParent_Done,
51476 // Label 2978: @144120
51477 GIM_Try, /*On fail goto*//*Label 2979*/ GIMT_Encode4(144165), // Rule ID 1029 //
51478 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51479 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
51480 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
51481 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
51482 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
51483 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51484 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51485 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51486 // (intrinsic_wo_chain:{ *:[v8i8] } 677:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) => (SUQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)
51487 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv8i8),
51488 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51489 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
51490 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
51491 GIR_RootConstrainSelectedInstOperands,
51492 // GIR_Coverage, 1029,
51493 GIR_EraseRootFromParent_Done,
51494 // Label 2979: @144165
51495 GIM_Try, /*On fail goto*//*Label 2980*/ GIMT_Encode4(144210), // Rule ID 1030 //
51496 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51497 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
51498 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
51499 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
51500 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
51501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51502 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51503 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51504 // (intrinsic_wo_chain:{ *:[v16i8] } 677:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (SUQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)
51505 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv16i8),
51506 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51507 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
51508 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
51509 GIR_RootConstrainSelectedInstOperands,
51510 // GIR_Coverage, 1030,
51511 GIR_EraseRootFromParent_Done,
51512 // Label 2980: @144210
51513 GIM_Try, /*On fail goto*//*Label 2981*/ GIMT_Encode4(144255), // Rule ID 1031 //
51514 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51515 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
51516 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
51517 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
51518 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
51519 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51520 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51521 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51522 // (intrinsic_wo_chain:{ *:[v4i16] } 677:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) => (SUQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn)
51523 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv4i16),
51524 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51525 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
51526 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
51527 GIR_RootConstrainSelectedInstOperands,
51528 // GIR_Coverage, 1031,
51529 GIR_EraseRootFromParent_Done,
51530 // Label 2981: @144255
51531 GIM_Try, /*On fail goto*//*Label 2982*/ GIMT_Encode4(144300), // Rule ID 1032 //
51532 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51533 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
51534 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
51535 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
51536 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
51537 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51538 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51539 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51540 // (intrinsic_wo_chain:{ *:[v8i16] } 677:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn) => (SUQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn)
51541 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv8i16),
51542 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51543 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
51544 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
51545 GIR_RootConstrainSelectedInstOperands,
51546 // GIR_Coverage, 1032,
51547 GIR_EraseRootFromParent_Done,
51548 // Label 2982: @144300
51549 GIM_Try, /*On fail goto*//*Label 2983*/ GIMT_Encode4(144345), // Rule ID 1033 //
51550 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51551 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
51552 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
51553 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
51554 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
51555 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51556 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51557 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51558 // (intrinsic_wo_chain:{ *:[v2i32] } 677:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) => (SUQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn)
51559 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv2i32),
51560 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51561 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
51562 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
51563 GIR_RootConstrainSelectedInstOperands,
51564 // GIR_Coverage, 1033,
51565 GIR_EraseRootFromParent_Done,
51566 // Label 2983: @144345
51567 GIM_Try, /*On fail goto*//*Label 2984*/ GIMT_Encode4(144390), // Rule ID 1034 //
51568 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51569 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
51570 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
51571 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
51572 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
51573 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51574 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51575 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51576 // (intrinsic_wo_chain:{ *:[v4i32] } 677:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (SUQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)
51577 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv4i32),
51578 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51579 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
51580 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
51581 GIR_RootConstrainSelectedInstOperands,
51582 // GIR_Coverage, 1034,
51583 GIR_EraseRootFromParent_Done,
51584 // Label 2984: @144390
51585 GIM_Try, /*On fail goto*//*Label 2985*/ GIMT_Encode4(144435), // Rule ID 1035 //
51586 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51587 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
51588 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
51589 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
51590 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
51591 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51592 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51593 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51594 // (intrinsic_wo_chain:{ *:[v2i64] } 677:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn) => (SUQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn)
51595 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv2i64),
51596 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51597 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
51598 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
51599 GIR_RootConstrainSelectedInstOperands,
51600 // GIR_Coverage, 1035,
51601 GIR_EraseRootFromParent_Done,
51602 // Label 2985: @144435
51603 GIM_Try, /*On fail goto*//*Label 2986*/ GIMT_Encode4(144480), // Rule ID 1077 //
51604 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51605 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
51606 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
51607 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
51608 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
51609 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51610 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51611 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51612 // (intrinsic_wo_chain:{ *:[v8i8] } 716:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn) => (USQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)
51613 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv8i8),
51614 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51615 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
51616 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
51617 GIR_RootConstrainSelectedInstOperands,
51618 // GIR_Coverage, 1077,
51619 GIR_EraseRootFromParent_Done,
51620 // Label 2986: @144480
51621 GIM_Try, /*On fail goto*//*Label 2987*/ GIMT_Encode4(144525), // Rule ID 1078 //
51622 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51623 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
51624 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
51625 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
51626 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
51627 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51628 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51629 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51630 // (intrinsic_wo_chain:{ *:[v16i8] } 716:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (USQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)
51631 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv16i8),
51632 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51633 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
51634 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
51635 GIR_RootConstrainSelectedInstOperands,
51636 // GIR_Coverage, 1078,
51637 GIR_EraseRootFromParent_Done,
51638 // Label 2987: @144525
51639 GIM_Try, /*On fail goto*//*Label 2988*/ GIMT_Encode4(144570), // Rule ID 1079 //
51640 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51641 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
51642 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
51643 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
51644 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
51645 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51646 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51647 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51648 // (intrinsic_wo_chain:{ *:[v4i16] } 716:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn) => (USQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn)
51649 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv4i16),
51650 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51651 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
51652 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
51653 GIR_RootConstrainSelectedInstOperands,
51654 // GIR_Coverage, 1079,
51655 GIR_EraseRootFromParent_Done,
51656 // Label 2988: @144570
51657 GIM_Try, /*On fail goto*//*Label 2989*/ GIMT_Encode4(144615), // Rule ID 1080 //
51658 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51659 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
51660 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
51661 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
51662 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
51663 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51664 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51665 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51666 // (intrinsic_wo_chain:{ *:[v8i16] } 716:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn) => (USQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn)
51667 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv8i16),
51668 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51669 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
51670 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
51671 GIR_RootConstrainSelectedInstOperands,
51672 // GIR_Coverage, 1080,
51673 GIR_EraseRootFromParent_Done,
51674 // Label 2989: @144615
51675 GIM_Try, /*On fail goto*//*Label 2990*/ GIMT_Encode4(144660), // Rule ID 1081 //
51676 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51677 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
51678 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
51679 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
51680 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
51681 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51682 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51683 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51684 // (intrinsic_wo_chain:{ *:[v2i32] } 716:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn) => (USQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn)
51685 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv2i32),
51686 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51687 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
51688 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
51689 GIR_RootConstrainSelectedInstOperands,
51690 // GIR_Coverage, 1081,
51691 GIR_EraseRootFromParent_Done,
51692 // Label 2990: @144660
51693 GIM_Try, /*On fail goto*//*Label 2991*/ GIMT_Encode4(144705), // Rule ID 1082 //
51694 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51695 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
51696 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
51697 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
51698 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
51699 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51700 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51701 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51702 // (intrinsic_wo_chain:{ *:[v4i32] } 716:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (USQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)
51703 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv4i32),
51704 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51705 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
51706 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
51707 GIR_RootConstrainSelectedInstOperands,
51708 // GIR_Coverage, 1082,
51709 GIR_EraseRootFromParent_Done,
51710 // Label 2991: @144705
51711 GIM_Try, /*On fail goto*//*Label 2992*/ GIMT_Encode4(144750), // Rule ID 1083 //
51712 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51713 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
51714 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
51715 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
51716 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
51717 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51718 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51719 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51720 // (intrinsic_wo_chain:{ *:[v2i64] } 716:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn) => (USQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn)
51721 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv2i64),
51722 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
51723 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
51724 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
51725 GIR_RootConstrainSelectedInstOperands,
51726 // GIR_Coverage, 1083,
51727 GIR_EraseRootFromParent_Done,
51728 // Label 2992: @144750
51729 GIM_Try, /*On fail goto*//*Label 2993*/ GIMT_Encode4(144795), // Rule ID 1095 //
51730 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51731 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
51732 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
51733 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
51734 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
51735 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51736 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51737 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51738 // (intrinsic_wo_chain:{ *:[v8i8] } 552:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ADDPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
51739 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv8i8),
51740 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51741 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51742 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51743 GIR_RootConstrainSelectedInstOperands,
51744 // GIR_Coverage, 1095,
51745 GIR_EraseRootFromParent_Done,
51746 // Label 2993: @144795
51747 GIM_Try, /*On fail goto*//*Label 2994*/ GIMT_Encode4(144840), // Rule ID 1097 //
51748 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51749 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
51750 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
51751 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
51752 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
51753 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51754 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51755 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51756 // (intrinsic_wo_chain:{ *:[v16i8] } 552:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ADDPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
51757 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv16i8),
51758 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51759 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51760 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51761 GIR_RootConstrainSelectedInstOperands,
51762 // GIR_Coverage, 1097,
51763 GIR_EraseRootFromParent_Done,
51764 // Label 2994: @144840
51765 GIM_Try, /*On fail goto*//*Label 2995*/ GIMT_Encode4(144885), // Rule ID 1099 //
51766 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51767 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
51768 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
51769 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
51770 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
51771 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51772 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51773 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51774 // (intrinsic_wo_chain:{ *:[v4i16] } 552:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (ADDPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
51775 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv4i16),
51776 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51777 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51778 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51779 GIR_RootConstrainSelectedInstOperands,
51780 // GIR_Coverage, 1099,
51781 GIR_EraseRootFromParent_Done,
51782 // Label 2995: @144885
51783 GIM_Try, /*On fail goto*//*Label 2996*/ GIMT_Encode4(144930), // Rule ID 1101 //
51784 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51785 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
51786 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
51787 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
51788 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
51789 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51790 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51791 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51792 // (intrinsic_wo_chain:{ *:[v8i16] } 552:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ADDPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
51793 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv8i16),
51794 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51795 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51796 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51797 GIR_RootConstrainSelectedInstOperands,
51798 // GIR_Coverage, 1101,
51799 GIR_EraseRootFromParent_Done,
51800 // Label 2996: @144930
51801 GIM_Try, /*On fail goto*//*Label 2997*/ GIMT_Encode4(144975), // Rule ID 1103 //
51802 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51803 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
51804 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
51805 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
51806 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
51807 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51808 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51809 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51810 // (intrinsic_wo_chain:{ *:[v2i32] } 552:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (ADDPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
51811 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i32),
51812 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51813 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51814 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51815 GIR_RootConstrainSelectedInstOperands,
51816 // GIR_Coverage, 1103,
51817 GIR_EraseRootFromParent_Done,
51818 // Label 2997: @144975
51819 GIM_Try, /*On fail goto*//*Label 2998*/ GIMT_Encode4(145020), // Rule ID 1105 //
51820 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51821 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
51822 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
51823 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
51824 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
51825 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51826 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51827 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51828 // (intrinsic_wo_chain:{ *:[v4i32] } 552:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ADDPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
51829 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv4i32),
51830 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51831 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51832 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51833 GIR_RootConstrainSelectedInstOperands,
51834 // GIR_Coverage, 1105,
51835 GIR_EraseRootFromParent_Done,
51836 // Label 2998: @145020
51837 GIM_Try, /*On fail goto*//*Label 2999*/ GIMT_Encode4(145065), // Rule ID 1107 //
51838 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51839 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
51840 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
51841 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
51842 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
51843 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51844 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51845 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51846 // (intrinsic_wo_chain:{ *:[v2i64] } 552:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ADDPv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
51847 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64),
51848 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51849 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51850 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51851 GIR_RootConstrainSelectedInstOperands,
51852 // GIR_Coverage, 1107,
51853 GIR_EraseRootFromParent_Done,
51854 // Label 2999: @145065
51855 GIM_Try, /*On fail goto*//*Label 3000*/ GIMT_Encode4(145110), // Rule ID 1150 //
51856 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
51857 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fabd),
51858 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
51859 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
51860 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
51861 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51862 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51863 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51864 // (intrinsic_wo_chain:{ *:[v4f16] } 561:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FABDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
51865 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv4f16),
51866 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51867 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51868 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51869 GIR_RootConstrainSelectedInstOperands,
51870 // GIR_Coverage, 1150,
51871 GIR_EraseRootFromParent_Done,
51872 // Label 3000: @145110
51873 GIM_Try, /*On fail goto*//*Label 3001*/ GIMT_Encode4(145155), // Rule ID 1151 //
51874 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
51875 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fabd),
51876 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
51877 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
51878 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
51879 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51880 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51881 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51882 // (intrinsic_wo_chain:{ *:[v8f16] } 561:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FABDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
51883 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv8f16),
51884 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51885 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51886 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51887 GIR_RootConstrainSelectedInstOperands,
51888 // GIR_Coverage, 1151,
51889 GIR_EraseRootFromParent_Done,
51890 // Label 3001: @145155
51891 GIM_Try, /*On fail goto*//*Label 3002*/ GIMT_Encode4(145200), // Rule ID 1152 //
51892 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51893 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fabd),
51894 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
51895 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
51896 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
51897 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51898 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51899 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51900 // (intrinsic_wo_chain:{ *:[v2f32] } 561:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FABDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
51901 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv2f32),
51902 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51903 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51904 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51905 GIR_RootConstrainSelectedInstOperands,
51906 // GIR_Coverage, 1152,
51907 GIR_EraseRootFromParent_Done,
51908 // Label 3002: @145200
51909 GIM_Try, /*On fail goto*//*Label 3003*/ GIMT_Encode4(145245), // Rule ID 1153 //
51910 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51911 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fabd),
51912 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
51913 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
51914 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
51915 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51916 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51917 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51918 // (intrinsic_wo_chain:{ *:[v4f32] } 561:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FABDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
51919 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv4f32),
51920 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51921 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51922 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51923 GIR_RootConstrainSelectedInstOperands,
51924 // GIR_Coverage, 1153,
51925 GIR_EraseRootFromParent_Done,
51926 // Label 3003: @145245
51927 GIM_Try, /*On fail goto*//*Label 3004*/ GIMT_Encode4(145290), // Rule ID 1154 //
51928 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51929 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fabd),
51930 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
51931 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
51932 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
51933 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51934 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51935 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51936 // (intrinsic_wo_chain:{ *:[v2f64] } 561:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FABDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
51937 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv2f64),
51938 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51939 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51940 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51941 GIR_RootConstrainSelectedInstOperands,
51942 // GIR_Coverage, 1154,
51943 GIR_EraseRootFromParent_Done,
51944 // Label 3004: @145290
51945 GIM_Try, /*On fail goto*//*Label 3005*/ GIMT_Encode4(145335), // Rule ID 1156 //
51946 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
51947 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
51948 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
51949 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
51950 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
51951 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51952 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51953 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51954 // (intrinsic_wo_chain:{ *:[v4i16] } 562:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FACGEv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
51955 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv4f16),
51956 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51957 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51958 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51959 GIR_RootConstrainSelectedInstOperands,
51960 // GIR_Coverage, 1156,
51961 GIR_EraseRootFromParent_Done,
51962 // Label 3005: @145335
51963 GIM_Try, /*On fail goto*//*Label 3006*/ GIMT_Encode4(145380), // Rule ID 1158 //
51964 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
51965 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
51966 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
51967 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
51968 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
51969 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51970 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51971 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
51972 // (intrinsic_wo_chain:{ *:[v8i16] } 562:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FACGEv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
51973 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv8f16),
51974 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51975 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51976 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51977 GIR_RootConstrainSelectedInstOperands,
51978 // GIR_Coverage, 1158,
51979 GIR_EraseRootFromParent_Done,
51980 // Label 3006: @145380
51981 GIM_Try, /*On fail goto*//*Label 3007*/ GIMT_Encode4(145425), // Rule ID 1160 //
51982 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
51983 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
51984 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
51985 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
51986 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
51987 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51988 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51989 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
51990 // (intrinsic_wo_chain:{ *:[v2i32] } 562:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FACGEv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
51991 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv2f32),
51992 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
51993 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
51994 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
51995 GIR_RootConstrainSelectedInstOperands,
51996 // GIR_Coverage, 1160,
51997 GIR_EraseRootFromParent_Done,
51998 // Label 3007: @145425
51999 GIM_Try, /*On fail goto*//*Label 3008*/ GIMT_Encode4(145470), // Rule ID 1162 //
52000 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52001 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
52002 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
52003 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
52004 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
52005 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52006 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52007 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52008 // (intrinsic_wo_chain:{ *:[v4i32] } 562:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FACGEv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
52009 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv4f32),
52010 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52011 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52012 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52013 GIR_RootConstrainSelectedInstOperands,
52014 // GIR_Coverage, 1162,
52015 GIR_EraseRootFromParent_Done,
52016 // Label 3008: @145470
52017 GIM_Try, /*On fail goto*//*Label 3009*/ GIMT_Encode4(145515), // Rule ID 1164 //
52018 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52019 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
52020 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
52021 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
52022 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
52023 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52024 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52025 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52026 // (intrinsic_wo_chain:{ *:[v2i64] } 562:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FACGEv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
52027 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv2f64),
52028 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52029 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52030 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52031 GIR_RootConstrainSelectedInstOperands,
52032 // GIR_Coverage, 1164,
52033 GIR_EraseRootFromParent_Done,
52034 // Label 3009: @145515
52035 GIM_Try, /*On fail goto*//*Label 3010*/ GIMT_Encode4(145560), // Rule ID 1166 //
52036 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
52037 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
52038 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
52039 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
52040 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
52041 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52042 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52043 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52044 // (intrinsic_wo_chain:{ *:[v4i16] } 563:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FACGTv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
52045 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv4f16),
52046 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52047 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52048 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52049 GIR_RootConstrainSelectedInstOperands,
52050 // GIR_Coverage, 1166,
52051 GIR_EraseRootFromParent_Done,
52052 // Label 3010: @145560
52053 GIM_Try, /*On fail goto*//*Label 3011*/ GIMT_Encode4(145605), // Rule ID 1168 //
52054 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
52055 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
52056 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
52057 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
52058 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
52059 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52060 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52061 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52062 // (intrinsic_wo_chain:{ *:[v8i16] } 563:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FACGTv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
52063 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv8f16),
52064 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52065 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52066 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52067 GIR_RootConstrainSelectedInstOperands,
52068 // GIR_Coverage, 1168,
52069 GIR_EraseRootFromParent_Done,
52070 // Label 3011: @145605
52071 GIM_Try, /*On fail goto*//*Label 3012*/ GIMT_Encode4(145650), // Rule ID 1170 //
52072 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52073 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
52074 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
52075 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
52076 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
52077 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52078 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52079 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52080 // (intrinsic_wo_chain:{ *:[v2i32] } 563:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FACGTv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
52081 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv2f32),
52082 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52083 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52084 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52085 GIR_RootConstrainSelectedInstOperands,
52086 // GIR_Coverage, 1170,
52087 GIR_EraseRootFromParent_Done,
52088 // Label 3012: @145650
52089 GIM_Try, /*On fail goto*//*Label 3013*/ GIMT_Encode4(145695), // Rule ID 1172 //
52090 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52091 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
52092 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
52093 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
52094 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
52095 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52096 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52097 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52098 // (intrinsic_wo_chain:{ *:[v4i32] } 563:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FACGTv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
52099 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv4f32),
52100 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52101 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52102 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52103 GIR_RootConstrainSelectedInstOperands,
52104 // GIR_Coverage, 1172,
52105 GIR_EraseRootFromParent_Done,
52106 // Label 3013: @145695
52107 GIM_Try, /*On fail goto*//*Label 3014*/ GIMT_Encode4(145740), // Rule ID 1174 //
52108 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52109 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
52110 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
52111 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
52112 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
52113 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52114 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52115 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52116 // (intrinsic_wo_chain:{ *:[v2i64] } 563:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FACGTv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
52117 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv2f64),
52118 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52119 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52120 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52121 GIR_RootConstrainSelectedInstOperands,
52122 // GIR_Coverage, 1174,
52123 GIR_EraseRootFromParent_Done,
52124 // Label 3014: @145740
52125 GIM_Try, /*On fail goto*//*Label 3015*/ GIMT_Encode4(145785), // Rule ID 1176 //
52126 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
52127 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddp),
52128 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
52129 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
52130 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
52131 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52132 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52133 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52134 // (intrinsic_wo_chain:{ *:[v4f16] } 564:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FADDPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
52135 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f16),
52136 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52137 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52138 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52139 GIR_RootConstrainSelectedInstOperands,
52140 // GIR_Coverage, 1176,
52141 GIR_EraseRootFromParent_Done,
52142 // Label 3015: @145785
52143 GIM_Try, /*On fail goto*//*Label 3016*/ GIMT_Encode4(145830), // Rule ID 1178 //
52144 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
52145 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddp),
52146 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
52147 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
52148 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
52149 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52150 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52151 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52152 // (intrinsic_wo_chain:{ *:[v8f16] } 564:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FADDPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
52153 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv8f16),
52154 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52155 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52156 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52157 GIR_RootConstrainSelectedInstOperands,
52158 // GIR_Coverage, 1178,
52159 GIR_EraseRootFromParent_Done,
52160 // Label 3016: @145830
52161 GIM_Try, /*On fail goto*//*Label 3017*/ GIMT_Encode4(145875), // Rule ID 1180 //
52162 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52163 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddp),
52164 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
52165 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
52166 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
52167 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52168 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52169 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52170 // (intrinsic_wo_chain:{ *:[v2f32] } 564:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FADDPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
52171 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2f32),
52172 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52173 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52174 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52175 GIR_RootConstrainSelectedInstOperands,
52176 // GIR_Coverage, 1180,
52177 GIR_EraseRootFromParent_Done,
52178 // Label 3017: @145875
52179 GIM_Try, /*On fail goto*//*Label 3018*/ GIMT_Encode4(145920), // Rule ID 1182 //
52180 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52181 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddp),
52182 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
52183 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
52184 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
52185 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52186 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52187 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52188 // (intrinsic_wo_chain:{ *:[v4f32] } 564:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FADDPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
52189 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f32),
52190 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52191 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52192 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52193 GIR_RootConstrainSelectedInstOperands,
52194 // GIR_Coverage, 1182,
52195 GIR_EraseRootFromParent_Done,
52196 // Label 3018: @145920
52197 GIM_Try, /*On fail goto*//*Label 3019*/ GIMT_Encode4(145965), // Rule ID 1184 //
52198 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52199 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddp),
52200 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
52201 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
52202 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
52203 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52204 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52205 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52206 // (intrinsic_wo_chain:{ *:[v2f64] } 564:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FADDPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
52207 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2f64),
52208 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52209 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52210 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52211 GIR_RootConstrainSelectedInstOperands,
52212 // GIR_Coverage, 1184,
52213 GIR_EraseRootFromParent_Done,
52214 // Label 3019: @145965
52215 GIM_Try, /*On fail goto*//*Label 3020*/ GIMT_Encode4(146010), // Rule ID 1220 //
52216 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
52217 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmp),
52218 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
52219 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
52220 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
52221 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52222 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52223 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52224 // (intrinsic_wo_chain:{ *:[v4f16] } 579:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMAXNMPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
52225 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv4f16),
52226 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52227 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52228 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52229 GIR_RootConstrainSelectedInstOperands,
52230 // GIR_Coverage, 1220,
52231 GIR_EraseRootFromParent_Done,
52232 // Label 3020: @146010
52233 GIM_Try, /*On fail goto*//*Label 3021*/ GIMT_Encode4(146055), // Rule ID 1221 //
52234 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
52235 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmp),
52236 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
52237 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
52238 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
52239 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52240 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52241 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52242 // (intrinsic_wo_chain:{ *:[v8f16] } 579:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMAXNMPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
52243 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv8f16),
52244 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52245 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52246 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52247 GIR_RootConstrainSelectedInstOperands,
52248 // GIR_Coverage, 1221,
52249 GIR_EraseRootFromParent_Done,
52250 // Label 3021: @146055
52251 GIM_Try, /*On fail goto*//*Label 3022*/ GIMT_Encode4(146100), // Rule ID 1222 //
52252 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52253 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmp),
52254 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
52255 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
52256 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
52257 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52258 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52259 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52260 // (intrinsic_wo_chain:{ *:[v2f32] } 579:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMAXNMPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
52261 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv2f32),
52262 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52263 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52264 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52265 GIR_RootConstrainSelectedInstOperands,
52266 // GIR_Coverage, 1222,
52267 GIR_EraseRootFromParent_Done,
52268 // Label 3022: @146100
52269 GIM_Try, /*On fail goto*//*Label 3023*/ GIMT_Encode4(146145), // Rule ID 1223 //
52270 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52271 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmp),
52272 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
52273 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
52274 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
52275 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52276 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52277 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52278 // (intrinsic_wo_chain:{ *:[v4f32] } 579:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMAXNMPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
52279 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv4f32),
52280 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52281 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52282 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52283 GIR_RootConstrainSelectedInstOperands,
52284 // GIR_Coverage, 1223,
52285 GIR_EraseRootFromParent_Done,
52286 // Label 3023: @146145
52287 GIM_Try, /*On fail goto*//*Label 3024*/ GIMT_Encode4(146190), // Rule ID 1224 //
52288 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52289 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmp),
52290 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
52291 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
52292 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
52293 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52294 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52295 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52296 // (intrinsic_wo_chain:{ *:[v2f64] } 579:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMAXNMPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
52297 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv2f64),
52298 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52299 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52300 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52301 GIR_RootConstrainSelectedInstOperands,
52302 // GIR_Coverage, 1224,
52303 GIR_EraseRootFromParent_Done,
52304 // Label 3024: @146190
52305 GIM_Try, /*On fail goto*//*Label 3025*/ GIMT_Encode4(146235), // Rule ID 1235 //
52306 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
52307 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxp),
52308 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
52309 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
52310 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
52311 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52312 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52313 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52314 // (intrinsic_wo_chain:{ *:[v4f16] } 581:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMAXPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
52315 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv4f16),
52316 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52317 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52318 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52319 GIR_RootConstrainSelectedInstOperands,
52320 // GIR_Coverage, 1235,
52321 GIR_EraseRootFromParent_Done,
52322 // Label 3025: @146235
52323 GIM_Try, /*On fail goto*//*Label 3026*/ GIMT_Encode4(146280), // Rule ID 1236 //
52324 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
52325 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxp),
52326 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
52327 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
52328 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
52329 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52330 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52331 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52332 // (intrinsic_wo_chain:{ *:[v8f16] } 581:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMAXPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
52333 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv8f16),
52334 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52335 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52336 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52337 GIR_RootConstrainSelectedInstOperands,
52338 // GIR_Coverage, 1236,
52339 GIR_EraseRootFromParent_Done,
52340 // Label 3026: @146280
52341 GIM_Try, /*On fail goto*//*Label 3027*/ GIMT_Encode4(146325), // Rule ID 1237 //
52342 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52343 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxp),
52344 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
52345 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
52346 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
52347 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52348 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52349 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52350 // (intrinsic_wo_chain:{ *:[v2f32] } 581:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMAXPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
52351 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv2f32),
52352 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52353 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52354 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52355 GIR_RootConstrainSelectedInstOperands,
52356 // GIR_Coverage, 1237,
52357 GIR_EraseRootFromParent_Done,
52358 // Label 3027: @146325
52359 GIM_Try, /*On fail goto*//*Label 3028*/ GIMT_Encode4(146370), // Rule ID 1238 //
52360 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52361 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxp),
52362 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
52363 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
52364 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
52365 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52366 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52367 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52368 // (intrinsic_wo_chain:{ *:[v4f32] } 581:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMAXPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
52369 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv4f32),
52370 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52371 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52372 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52373 GIR_RootConstrainSelectedInstOperands,
52374 // GIR_Coverage, 1238,
52375 GIR_EraseRootFromParent_Done,
52376 // Label 3028: @146370
52377 GIM_Try, /*On fail goto*//*Label 3029*/ GIMT_Encode4(146415), // Rule ID 1239 //
52378 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52379 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxp),
52380 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
52381 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
52382 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
52383 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52384 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52385 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52386 // (intrinsic_wo_chain:{ *:[v2f64] } 581:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMAXPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
52387 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv2f64),
52388 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52389 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52390 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52391 GIR_RootConstrainSelectedInstOperands,
52392 // GIR_Coverage, 1239,
52393 GIR_EraseRootFromParent_Done,
52394 // Label 3029: @146415
52395 GIM_Try, /*On fail goto*//*Label 3030*/ GIMT_Encode4(146460), // Rule ID 1250 //
52396 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
52397 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmp),
52398 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
52399 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
52400 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
52401 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52402 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52403 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52404 // (intrinsic_wo_chain:{ *:[v4f16] } 585:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMINNMPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
52405 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv4f16),
52406 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52407 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52408 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52409 GIR_RootConstrainSelectedInstOperands,
52410 // GIR_Coverage, 1250,
52411 GIR_EraseRootFromParent_Done,
52412 // Label 3030: @146460
52413 GIM_Try, /*On fail goto*//*Label 3031*/ GIMT_Encode4(146505), // Rule ID 1251 //
52414 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
52415 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmp),
52416 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
52417 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
52418 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
52419 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52420 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52421 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52422 // (intrinsic_wo_chain:{ *:[v8f16] } 585:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMINNMPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
52423 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv8f16),
52424 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52425 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52426 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52427 GIR_RootConstrainSelectedInstOperands,
52428 // GIR_Coverage, 1251,
52429 GIR_EraseRootFromParent_Done,
52430 // Label 3031: @146505
52431 GIM_Try, /*On fail goto*//*Label 3032*/ GIMT_Encode4(146550), // Rule ID 1252 //
52432 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52433 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmp),
52434 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
52435 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
52436 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
52437 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52438 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52439 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52440 // (intrinsic_wo_chain:{ *:[v2f32] } 585:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMINNMPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
52441 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv2f32),
52442 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52443 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52444 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52445 GIR_RootConstrainSelectedInstOperands,
52446 // GIR_Coverage, 1252,
52447 GIR_EraseRootFromParent_Done,
52448 // Label 3032: @146550
52449 GIM_Try, /*On fail goto*//*Label 3033*/ GIMT_Encode4(146595), // Rule ID 1253 //
52450 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52451 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmp),
52452 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
52453 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
52454 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
52455 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52456 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52457 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52458 // (intrinsic_wo_chain:{ *:[v4f32] } 585:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMINNMPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
52459 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv4f32),
52460 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52461 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52462 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52463 GIR_RootConstrainSelectedInstOperands,
52464 // GIR_Coverage, 1253,
52465 GIR_EraseRootFromParent_Done,
52466 // Label 3033: @146595
52467 GIM_Try, /*On fail goto*//*Label 3034*/ GIMT_Encode4(146640), // Rule ID 1254 //
52468 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52469 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmp),
52470 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
52471 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
52472 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
52473 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52474 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52475 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52476 // (intrinsic_wo_chain:{ *:[v2f64] } 585:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMINNMPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
52477 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv2f64),
52478 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52479 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52480 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52481 GIR_RootConstrainSelectedInstOperands,
52482 // GIR_Coverage, 1254,
52483 GIR_EraseRootFromParent_Done,
52484 // Label 3034: @146640
52485 GIM_Try, /*On fail goto*//*Label 3035*/ GIMT_Encode4(146685), // Rule ID 1265 //
52486 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
52487 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminp),
52488 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
52489 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
52490 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
52491 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52492 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52493 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52494 // (intrinsic_wo_chain:{ *:[v4f16] } 587:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMINPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
52495 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv4f16),
52496 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52497 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52498 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52499 GIR_RootConstrainSelectedInstOperands,
52500 // GIR_Coverage, 1265,
52501 GIR_EraseRootFromParent_Done,
52502 // Label 3035: @146685
52503 GIM_Try, /*On fail goto*//*Label 3036*/ GIMT_Encode4(146730), // Rule ID 1266 //
52504 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
52505 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminp),
52506 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
52507 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
52508 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
52509 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52510 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52511 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52512 // (intrinsic_wo_chain:{ *:[v8f16] } 587:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMINPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
52513 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv8f16),
52514 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52515 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52516 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52517 GIR_RootConstrainSelectedInstOperands,
52518 // GIR_Coverage, 1266,
52519 GIR_EraseRootFromParent_Done,
52520 // Label 3036: @146730
52521 GIM_Try, /*On fail goto*//*Label 3037*/ GIMT_Encode4(146775), // Rule ID 1267 //
52522 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52523 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminp),
52524 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
52525 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
52526 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
52527 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52528 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52529 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52530 // (intrinsic_wo_chain:{ *:[v2f32] } 587:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMINPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
52531 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv2f32),
52532 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52533 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52534 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52535 GIR_RootConstrainSelectedInstOperands,
52536 // GIR_Coverage, 1267,
52537 GIR_EraseRootFromParent_Done,
52538 // Label 3037: @146775
52539 GIM_Try, /*On fail goto*//*Label 3038*/ GIMT_Encode4(146820), // Rule ID 1268 //
52540 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52541 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminp),
52542 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
52543 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
52544 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
52545 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52546 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52547 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52548 // (intrinsic_wo_chain:{ *:[v4f32] } 587:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMINPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
52549 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv4f32),
52550 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52551 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52552 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52553 GIR_RootConstrainSelectedInstOperands,
52554 // GIR_Coverage, 1268,
52555 GIR_EraseRootFromParent_Done,
52556 // Label 3038: @146820
52557 GIM_Try, /*On fail goto*//*Label 3039*/ GIMT_Encode4(146865), // Rule ID 1269 //
52558 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52559 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminp),
52560 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
52561 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
52562 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
52563 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52564 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52565 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52566 // (intrinsic_wo_chain:{ *:[v2f64] } 587:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMINPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
52567 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv2f64),
52568 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52569 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52570 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52571 GIR_RootConstrainSelectedInstOperands,
52572 // GIR_Coverage, 1269,
52573 GIR_EraseRootFromParent_Done,
52574 // Label 3039: @146865
52575 GIM_Try, /*On fail goto*//*Label 3040*/ GIMT_Encode4(146910), // Rule ID 1300 //
52576 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
52577 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
52578 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
52579 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
52580 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
52581 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52582 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52583 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52584 // (intrinsic_wo_chain:{ *:[v4f16] } 593:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMULXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
52585 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4f16),
52586 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52587 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52588 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52589 GIR_RootConstrainSelectedInstOperands,
52590 // GIR_Coverage, 1300,
52591 GIR_EraseRootFromParent_Done,
52592 // Label 3040: @146910
52593 GIM_Try, /*On fail goto*//*Label 3041*/ GIMT_Encode4(146955), // Rule ID 1301 //
52594 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
52595 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
52596 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
52597 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
52598 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
52599 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52600 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52601 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52602 // (intrinsic_wo_chain:{ *:[v8f16] } 593:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMULXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
52603 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv8f16),
52604 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52605 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52606 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52607 GIR_RootConstrainSelectedInstOperands,
52608 // GIR_Coverage, 1301,
52609 GIR_EraseRootFromParent_Done,
52610 // Label 3041: @146955
52611 GIM_Try, /*On fail goto*//*Label 3042*/ GIMT_Encode4(147000), // Rule ID 1302 //
52612 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52613 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
52614 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
52615 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
52616 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
52617 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52618 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52619 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52620 // (intrinsic_wo_chain:{ *:[v2f32] } 593:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMULXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
52621 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2f32),
52622 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52623 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52624 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52625 GIR_RootConstrainSelectedInstOperands,
52626 // GIR_Coverage, 1302,
52627 GIR_EraseRootFromParent_Done,
52628 // Label 3042: @147000
52629 GIM_Try, /*On fail goto*//*Label 3043*/ GIMT_Encode4(147045), // Rule ID 1303 //
52630 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52631 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
52632 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
52633 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
52634 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
52635 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52636 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52637 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52638 // (intrinsic_wo_chain:{ *:[v4f32] } 593:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMULXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
52639 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4f32),
52640 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52641 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52642 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52643 GIR_RootConstrainSelectedInstOperands,
52644 // GIR_Coverage, 1303,
52645 GIR_EraseRootFromParent_Done,
52646 // Label 3043: @147045
52647 GIM_Try, /*On fail goto*//*Label 3044*/ GIMT_Encode4(147090), // Rule ID 1304 //
52648 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52649 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
52650 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
52651 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
52652 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
52653 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52654 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52655 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52656 // (intrinsic_wo_chain:{ *:[v2f64] } 593:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMULXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
52657 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2f64),
52658 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52659 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52660 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52661 GIR_RootConstrainSelectedInstOperands,
52662 // GIR_Coverage, 1304,
52663 GIR_EraseRootFromParent_Done,
52664 // Label 3044: @147090
52665 GIM_Try, /*On fail goto*//*Label 3045*/ GIMT_Encode4(147135), // Rule ID 1315 //
52666 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
52667 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
52668 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
52669 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
52670 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
52671 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52672 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52673 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52674 // (intrinsic_wo_chain:{ *:[v4f16] } 595:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FRECPSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
52675 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPSv4f16),
52676 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52677 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52678 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52679 GIR_RootConstrainSelectedInstOperands,
52680 // GIR_Coverage, 1315,
52681 GIR_EraseRootFromParent_Done,
52682 // Label 3045: @147135
52683 GIM_Try, /*On fail goto*//*Label 3046*/ GIMT_Encode4(147180), // Rule ID 1316 //
52684 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
52685 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
52686 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
52687 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
52688 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
52689 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52690 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52691 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52692 // (intrinsic_wo_chain:{ *:[v8f16] } 595:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FRECPSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
52693 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPSv8f16),
52694 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52695 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52696 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52697 GIR_RootConstrainSelectedInstOperands,
52698 // GIR_Coverage, 1316,
52699 GIR_EraseRootFromParent_Done,
52700 // Label 3046: @147180
52701 GIM_Try, /*On fail goto*//*Label 3047*/ GIMT_Encode4(147225), // Rule ID 1317 //
52702 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52703 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
52704 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
52705 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
52706 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
52707 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52708 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52709 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52710 // (intrinsic_wo_chain:{ *:[v2f32] } 595:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FRECPSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
52711 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPSv2f32),
52712 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52713 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52714 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52715 GIR_RootConstrainSelectedInstOperands,
52716 // GIR_Coverage, 1317,
52717 GIR_EraseRootFromParent_Done,
52718 // Label 3047: @147225
52719 GIM_Try, /*On fail goto*//*Label 3048*/ GIMT_Encode4(147270), // Rule ID 1318 //
52720 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52721 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
52722 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
52723 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
52724 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
52725 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52726 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52727 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52728 // (intrinsic_wo_chain:{ *:[v4f32] } 595:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FRECPSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
52729 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPSv4f32),
52730 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52731 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52732 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52733 GIR_RootConstrainSelectedInstOperands,
52734 // GIR_Coverage, 1318,
52735 GIR_EraseRootFromParent_Done,
52736 // Label 3048: @147270
52737 GIM_Try, /*On fail goto*//*Label 3049*/ GIMT_Encode4(147315), // Rule ID 1319 //
52738 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52739 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
52740 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
52741 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
52742 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
52743 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52744 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52745 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52746 // (intrinsic_wo_chain:{ *:[v2f64] } 595:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FRECPSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
52747 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPSv2f64),
52748 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52749 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52750 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52751 GIR_RootConstrainSelectedInstOperands,
52752 // GIR_Coverage, 1319,
52753 GIR_EraseRootFromParent_Done,
52754 // Label 3049: @147315
52755 GIM_Try, /*On fail goto*//*Label 3050*/ GIMT_Encode4(147360), // Rule ID 1320 //
52756 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
52757 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
52758 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
52759 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
52760 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
52761 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52762 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52763 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52764 // (intrinsic_wo_chain:{ *:[v4f16] } 602:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FRSQRTSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
52765 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTSv4f16),
52766 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52767 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52768 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52769 GIR_RootConstrainSelectedInstOperands,
52770 // GIR_Coverage, 1320,
52771 GIR_EraseRootFromParent_Done,
52772 // Label 3050: @147360
52773 GIM_Try, /*On fail goto*//*Label 3051*/ GIMT_Encode4(147405), // Rule ID 1321 //
52774 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
52775 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
52776 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
52777 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
52778 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
52779 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52780 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52781 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52782 // (intrinsic_wo_chain:{ *:[v8f16] } 602:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FRSQRTSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
52783 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTSv8f16),
52784 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52785 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52786 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52787 GIR_RootConstrainSelectedInstOperands,
52788 // GIR_Coverage, 1321,
52789 GIR_EraseRootFromParent_Done,
52790 // Label 3051: @147405
52791 GIM_Try, /*On fail goto*//*Label 3052*/ GIMT_Encode4(147450), // Rule ID 1322 //
52792 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52793 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
52794 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
52795 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
52796 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
52797 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52798 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52799 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52800 // (intrinsic_wo_chain:{ *:[v2f32] } 602:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FRSQRTSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
52801 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTSv2f32),
52802 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52803 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52804 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52805 GIR_RootConstrainSelectedInstOperands,
52806 // GIR_Coverage, 1322,
52807 GIR_EraseRootFromParent_Done,
52808 // Label 3052: @147450
52809 GIM_Try, /*On fail goto*//*Label 3053*/ GIMT_Encode4(147495), // Rule ID 1323 //
52810 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52811 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
52812 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
52813 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
52814 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
52815 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52816 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52817 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52818 // (intrinsic_wo_chain:{ *:[v4f32] } 602:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FRSQRTSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
52819 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTSv4f32),
52820 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52821 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52822 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52823 GIR_RootConstrainSelectedInstOperands,
52824 // GIR_Coverage, 1323,
52825 GIR_EraseRootFromParent_Done,
52826 // Label 3053: @147495
52827 GIM_Try, /*On fail goto*//*Label 3054*/ GIMT_Encode4(147540), // Rule ID 1324 //
52828 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52829 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
52830 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
52831 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
52832 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
52833 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52834 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52835 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52836 // (intrinsic_wo_chain:{ *:[v2f64] } 602:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FRSQRTSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
52837 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTSv2f64),
52838 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52839 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52840 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52841 GIR_RootConstrainSelectedInstOperands,
52842 // GIR_Coverage, 1324,
52843 GIR_EraseRootFromParent_Done,
52844 // Label 3054: @147540
52845 GIM_Try, /*On fail goto*//*Label 3055*/ GIMT_Encode4(147585), // Rule ID 1341 //
52846 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52847 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_pmul),
52848 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
52849 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
52850 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
52851 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52852 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52853 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52854 // (intrinsic_wo_chain:{ *:[v8i8] } 615:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (PMULv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
52855 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULv8i8),
52856 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52857 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52858 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52859 GIR_RootConstrainSelectedInstOperands,
52860 // GIR_Coverage, 1341,
52861 GIR_EraseRootFromParent_Done,
52862 // Label 3055: @147585
52863 GIM_Try, /*On fail goto*//*Label 3056*/ GIMT_Encode4(147630), // Rule ID 1342 //
52864 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52865 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_pmul),
52866 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
52867 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
52868 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
52869 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52870 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52871 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52872 // (intrinsic_wo_chain:{ *:[v16i8] } 615:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (PMULv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
52873 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULv16i8),
52874 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52875 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52876 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52877 GIR_RootConstrainSelectedInstOperands,
52878 // GIR_Coverage, 1342,
52879 GIR_EraseRootFromParent_Done,
52880 // Label 3056: @147630
52881 GIM_Try, /*On fail goto*//*Label 3057*/ GIMT_Encode4(147675), // Rule ID 1356 //
52882 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52883 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
52884 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
52885 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
52886 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
52887 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52888 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52889 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52890 // (intrinsic_wo_chain:{ *:[v8i8] } 621:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SABDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
52891 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDv8i8),
52892 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52893 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52894 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52895 GIR_RootConstrainSelectedInstOperands,
52896 // GIR_Coverage, 1356,
52897 GIR_EraseRootFromParent_Done,
52898 // Label 3057: @147675
52899 GIM_Try, /*On fail goto*//*Label 3058*/ GIMT_Encode4(147720), // Rule ID 1358 //
52900 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52901 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
52902 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
52903 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
52904 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
52905 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52906 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52907 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52908 // (intrinsic_wo_chain:{ *:[v16i8] } 621:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SABDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
52909 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDv16i8),
52910 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52911 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52912 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52913 GIR_RootConstrainSelectedInstOperands,
52914 // GIR_Coverage, 1358,
52915 GIR_EraseRootFromParent_Done,
52916 // Label 3058: @147720
52917 GIM_Try, /*On fail goto*//*Label 3059*/ GIMT_Encode4(147765), // Rule ID 1360 //
52918 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52919 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
52920 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
52921 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
52922 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
52923 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52924 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52925 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52926 // (intrinsic_wo_chain:{ *:[v4i16] } 621:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SABDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
52927 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDv4i16),
52928 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52929 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52930 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52931 GIR_RootConstrainSelectedInstOperands,
52932 // GIR_Coverage, 1360,
52933 GIR_EraseRootFromParent_Done,
52934 // Label 3059: @147765
52935 GIM_Try, /*On fail goto*//*Label 3060*/ GIMT_Encode4(147810), // Rule ID 1362 //
52936 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52937 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
52938 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
52939 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
52940 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
52941 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52942 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52943 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52944 // (intrinsic_wo_chain:{ *:[v8i16] } 621:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SABDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
52945 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDv8i16),
52946 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52947 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52948 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52949 GIR_RootConstrainSelectedInstOperands,
52950 // GIR_Coverage, 1362,
52951 GIR_EraseRootFromParent_Done,
52952 // Label 3060: @147810
52953 GIM_Try, /*On fail goto*//*Label 3061*/ GIMT_Encode4(147855), // Rule ID 1364 //
52954 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52955 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
52956 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
52957 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
52958 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
52959 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52960 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52961 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52962 // (intrinsic_wo_chain:{ *:[v2i32] } 621:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SABDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
52963 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDv2i32),
52964 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52965 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52966 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52967 GIR_RootConstrainSelectedInstOperands,
52968 // GIR_Coverage, 1364,
52969 GIR_EraseRootFromParent_Done,
52970 // Label 3061: @147855
52971 GIM_Try, /*On fail goto*//*Label 3062*/ GIMT_Encode4(147900), // Rule ID 1366 //
52972 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52973 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
52974 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
52975 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
52976 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
52977 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52978 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52979 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
52980 // (intrinsic_wo_chain:{ *:[v4i32] } 621:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SABDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
52981 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDv4i32),
52982 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
52983 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
52984 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
52985 GIR_RootConstrainSelectedInstOperands,
52986 // GIR_Coverage, 1366,
52987 GIR_EraseRootFromParent_Done,
52988 // Label 3062: @147900
52989 GIM_Try, /*On fail goto*//*Label 3063*/ GIMT_Encode4(147945), // Rule ID 1373 //
52990 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
52991 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_shsub),
52992 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
52993 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
52994 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
52995 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52996 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52997 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
52998 // (intrinsic_wo_chain:{ *:[v8i8] } 631:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SHSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
52999 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBv8i8),
53000 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53001 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53002 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53003 GIR_RootConstrainSelectedInstOperands,
53004 // GIR_Coverage, 1373,
53005 GIR_EraseRootFromParent_Done,
53006 // Label 3063: @147945
53007 GIM_Try, /*On fail goto*//*Label 3064*/ GIMT_Encode4(147990), // Rule ID 1374 //
53008 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53009 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_shsub),
53010 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
53011 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
53012 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
53013 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53014 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53015 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53016 // (intrinsic_wo_chain:{ *:[v16i8] } 631:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SHSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
53017 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBv16i8),
53018 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53019 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53020 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53021 GIR_RootConstrainSelectedInstOperands,
53022 // GIR_Coverage, 1374,
53023 GIR_EraseRootFromParent_Done,
53024 // Label 3064: @147990
53025 GIM_Try, /*On fail goto*//*Label 3065*/ GIMT_Encode4(148035), // Rule ID 1375 //
53026 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53027 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_shsub),
53028 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
53029 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
53030 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
53031 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53032 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53033 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53034 // (intrinsic_wo_chain:{ *:[v4i16] } 631:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SHSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
53035 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBv4i16),
53036 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53037 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53038 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53039 GIR_RootConstrainSelectedInstOperands,
53040 // GIR_Coverage, 1375,
53041 GIR_EraseRootFromParent_Done,
53042 // Label 3065: @148035
53043 GIM_Try, /*On fail goto*//*Label 3066*/ GIMT_Encode4(148080), // Rule ID 1376 //
53044 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53045 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_shsub),
53046 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
53047 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
53048 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
53049 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53050 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53051 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53052 // (intrinsic_wo_chain:{ *:[v8i16] } 631:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SHSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
53053 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBv8i16),
53054 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53055 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53056 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53057 GIR_RootConstrainSelectedInstOperands,
53058 // GIR_Coverage, 1376,
53059 GIR_EraseRootFromParent_Done,
53060 // Label 3066: @148080
53061 GIM_Try, /*On fail goto*//*Label 3067*/ GIMT_Encode4(148125), // Rule ID 1377 //
53062 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53063 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_shsub),
53064 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
53065 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
53066 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
53067 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53068 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53069 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53070 // (intrinsic_wo_chain:{ *:[v2i32] } 631:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SHSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
53071 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBv2i32),
53072 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53073 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53074 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53075 GIR_RootConstrainSelectedInstOperands,
53076 // GIR_Coverage, 1377,
53077 GIR_EraseRootFromParent_Done,
53078 // Label 3067: @148125
53079 GIM_Try, /*On fail goto*//*Label 3068*/ GIMT_Encode4(148170), // Rule ID 1378 //
53080 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53081 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_shsub),
53082 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
53083 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
53084 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
53085 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53086 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53087 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53088 // (intrinsic_wo_chain:{ *:[v4i32] } 631:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
53089 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBv4i32),
53090 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53091 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53092 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53093 GIR_RootConstrainSelectedInstOperands,
53094 // GIR_Coverage, 1378,
53095 GIR_EraseRootFromParent_Done,
53096 // Label 3068: @148170
53097 GIM_Try, /*On fail goto*//*Label 3069*/ GIMT_Encode4(148215), // Rule ID 1379 //
53098 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53099 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxp),
53100 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
53101 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
53102 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
53103 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53104 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53105 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53106 // (intrinsic_wo_chain:{ *:[v8i8] } 633:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMAXPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
53107 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv8i8),
53108 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53109 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53110 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53111 GIR_RootConstrainSelectedInstOperands,
53112 // GIR_Coverage, 1379,
53113 GIR_EraseRootFromParent_Done,
53114 // Label 3069: @148215
53115 GIM_Try, /*On fail goto*//*Label 3070*/ GIMT_Encode4(148260), // Rule ID 1380 //
53116 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53117 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxp),
53118 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
53119 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
53120 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
53121 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53122 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53123 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53124 // (intrinsic_wo_chain:{ *:[v16i8] } 633:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMAXPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
53125 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv16i8),
53126 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53127 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53128 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53129 GIR_RootConstrainSelectedInstOperands,
53130 // GIR_Coverage, 1380,
53131 GIR_EraseRootFromParent_Done,
53132 // Label 3070: @148260
53133 GIM_Try, /*On fail goto*//*Label 3071*/ GIMT_Encode4(148305), // Rule ID 1381 //
53134 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53135 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxp),
53136 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
53137 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
53138 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
53139 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53140 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53141 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53142 // (intrinsic_wo_chain:{ *:[v4i16] } 633:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMAXPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
53143 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv4i16),
53144 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53145 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53146 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53147 GIR_RootConstrainSelectedInstOperands,
53148 // GIR_Coverage, 1381,
53149 GIR_EraseRootFromParent_Done,
53150 // Label 3071: @148305
53151 GIM_Try, /*On fail goto*//*Label 3072*/ GIMT_Encode4(148350), // Rule ID 1382 //
53152 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53153 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxp),
53154 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
53155 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
53156 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
53157 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53158 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53159 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53160 // (intrinsic_wo_chain:{ *:[v8i16] } 633:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SMAXPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
53161 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv8i16),
53162 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53163 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53164 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53165 GIR_RootConstrainSelectedInstOperands,
53166 // GIR_Coverage, 1382,
53167 GIR_EraseRootFromParent_Done,
53168 // Label 3072: @148350
53169 GIM_Try, /*On fail goto*//*Label 3073*/ GIMT_Encode4(148395), // Rule ID 1383 //
53170 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53171 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxp),
53172 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
53173 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
53174 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
53175 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53176 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53177 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53178 // (intrinsic_wo_chain:{ *:[v2i32] } 633:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMAXPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
53179 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv2i32),
53180 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53181 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53182 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53183 GIR_RootConstrainSelectedInstOperands,
53184 // GIR_Coverage, 1383,
53185 GIR_EraseRootFromParent_Done,
53186 // Label 3073: @148395
53187 GIM_Try, /*On fail goto*//*Label 3074*/ GIMT_Encode4(148440), // Rule ID 1384 //
53188 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53189 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxp),
53190 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
53191 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
53192 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
53193 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53194 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53195 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53196 // (intrinsic_wo_chain:{ *:[v4i32] } 633:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SMAXPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
53197 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv4i32),
53198 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53199 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53200 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53201 GIR_RootConstrainSelectedInstOperands,
53202 // GIR_Coverage, 1384,
53203 GIR_EraseRootFromParent_Done,
53204 // Label 3074: @148440
53205 GIM_Try, /*On fail goto*//*Label 3075*/ GIMT_Encode4(148485), // Rule ID 1391 //
53206 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53207 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminp),
53208 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
53209 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
53210 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
53211 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53212 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53213 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53214 // (intrinsic_wo_chain:{ *:[v8i8] } 636:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMINPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
53215 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINPv8i8),
53216 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53217 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53218 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53219 GIR_RootConstrainSelectedInstOperands,
53220 // GIR_Coverage, 1391,
53221 GIR_EraseRootFromParent_Done,
53222 // Label 3075: @148485
53223 GIM_Try, /*On fail goto*//*Label 3076*/ GIMT_Encode4(148530), // Rule ID 1392 //
53224 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53225 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminp),
53226 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
53227 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
53228 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
53229 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53230 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53231 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53232 // (intrinsic_wo_chain:{ *:[v16i8] } 636:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMINPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
53233 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINPv16i8),
53234 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53235 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53236 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53237 GIR_RootConstrainSelectedInstOperands,
53238 // GIR_Coverage, 1392,
53239 GIR_EraseRootFromParent_Done,
53240 // Label 3076: @148530
53241 GIM_Try, /*On fail goto*//*Label 3077*/ GIMT_Encode4(148575), // Rule ID 1393 //
53242 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53243 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminp),
53244 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
53245 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
53246 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
53247 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53248 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53249 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53250 // (intrinsic_wo_chain:{ *:[v4i16] } 636:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMINPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
53251 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINPv4i16),
53252 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53253 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53254 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53255 GIR_RootConstrainSelectedInstOperands,
53256 // GIR_Coverage, 1393,
53257 GIR_EraseRootFromParent_Done,
53258 // Label 3077: @148575
53259 GIM_Try, /*On fail goto*//*Label 3078*/ GIMT_Encode4(148620), // Rule ID 1394 //
53260 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53261 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminp),
53262 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
53263 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
53264 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
53265 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53266 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53267 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53268 // (intrinsic_wo_chain:{ *:[v8i16] } 636:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SMINPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
53269 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINPv8i16),
53270 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53271 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53272 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53273 GIR_RootConstrainSelectedInstOperands,
53274 // GIR_Coverage, 1394,
53275 GIR_EraseRootFromParent_Done,
53276 // Label 3078: @148620
53277 GIM_Try, /*On fail goto*//*Label 3079*/ GIMT_Encode4(148665), // Rule ID 1395 //
53278 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53279 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminp),
53280 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
53281 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
53282 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
53283 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53284 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53285 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53286 // (intrinsic_wo_chain:{ *:[v2i32] } 636:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMINPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
53287 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINPv2i32),
53288 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53289 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53290 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53291 GIR_RootConstrainSelectedInstOperands,
53292 // GIR_Coverage, 1395,
53293 GIR_EraseRootFromParent_Done,
53294 // Label 3079: @148665
53295 GIM_Try, /*On fail goto*//*Label 3080*/ GIMT_Encode4(148710), // Rule ID 1396 //
53296 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53297 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminp),
53298 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
53299 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
53300 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
53301 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53302 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53303 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53304 // (intrinsic_wo_chain:{ *:[v4i32] } 636:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SMINPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
53305 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINPv4i32),
53306 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53307 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53308 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53309 GIR_RootConstrainSelectedInstOperands,
53310 // GIR_Coverage, 1396,
53311 GIR_EraseRootFromParent_Done,
53312 // Label 3080: @148710
53313 GIM_Try, /*On fail goto*//*Label 3081*/ GIMT_Encode4(148755), // Rule ID 1403 //
53314 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53315 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
53316 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
53317 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
53318 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
53319 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53320 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53321 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53322 // (intrinsic_wo_chain:{ *:[v8i8] } 641:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
53323 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADDv8i8),
53324 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53325 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53326 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53327 GIR_RootConstrainSelectedInstOperands,
53328 // GIR_Coverage, 1403,
53329 GIR_EraseRootFromParent_Done,
53330 // Label 3081: @148755
53331 GIM_Try, /*On fail goto*//*Label 3082*/ GIMT_Encode4(148800), // Rule ID 1404 //
53332 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53333 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
53334 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
53335 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
53336 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
53337 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53338 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53339 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53340 // (intrinsic_wo_chain:{ *:[v16i8] } 641:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
53341 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADDv16i8),
53342 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53343 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53344 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53345 GIR_RootConstrainSelectedInstOperands,
53346 // GIR_Coverage, 1404,
53347 GIR_EraseRootFromParent_Done,
53348 // Label 3082: @148800
53349 GIM_Try, /*On fail goto*//*Label 3083*/ GIMT_Encode4(148845), // Rule ID 1405 //
53350 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53351 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
53352 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
53353 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
53354 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
53355 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53356 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53357 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53358 // (intrinsic_wo_chain:{ *:[v4i16] } 641:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
53359 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADDv4i16),
53360 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53361 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53362 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53363 GIR_RootConstrainSelectedInstOperands,
53364 // GIR_Coverage, 1405,
53365 GIR_EraseRootFromParent_Done,
53366 // Label 3083: @148845
53367 GIM_Try, /*On fail goto*//*Label 3084*/ GIMT_Encode4(148890), // Rule ID 1406 //
53368 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53369 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
53370 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
53371 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
53372 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
53373 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53374 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53375 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53376 // (intrinsic_wo_chain:{ *:[v8i16] } 641:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
53377 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADDv8i16),
53378 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53379 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53380 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53381 GIR_RootConstrainSelectedInstOperands,
53382 // GIR_Coverage, 1406,
53383 GIR_EraseRootFromParent_Done,
53384 // Label 3084: @148890
53385 GIM_Try, /*On fail goto*//*Label 3085*/ GIMT_Encode4(148935), // Rule ID 1407 //
53386 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53387 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
53388 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
53389 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
53390 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
53391 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53392 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53393 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53394 // (intrinsic_wo_chain:{ *:[v2i32] } 641:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
53395 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADDv2i32),
53396 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53397 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53398 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53399 GIR_RootConstrainSelectedInstOperands,
53400 // GIR_Coverage, 1407,
53401 GIR_EraseRootFromParent_Done,
53402 // Label 3085: @148935
53403 GIM_Try, /*On fail goto*//*Label 3086*/ GIMT_Encode4(148980), // Rule ID 1408 //
53404 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53405 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
53406 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
53407 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
53408 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
53409 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53410 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53411 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53412 // (intrinsic_wo_chain:{ *:[v4i32] } 641:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
53413 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADDv4i32),
53414 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53415 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53416 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53417 GIR_RootConstrainSelectedInstOperands,
53418 // GIR_Coverage, 1408,
53419 GIR_EraseRootFromParent_Done,
53420 // Label 3086: @148980
53421 GIM_Try, /*On fail goto*//*Label 3087*/ GIMT_Encode4(149025), // Rule ID 1409 //
53422 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53423 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
53424 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
53425 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
53426 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
53427 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53428 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53429 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53430 // (intrinsic_wo_chain:{ *:[v2i64] } 641:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
53431 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADDv2i64),
53432 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53433 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53434 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53435 GIR_RootConstrainSelectedInstOperands,
53436 // GIR_Coverage, 1409,
53437 GIR_EraseRootFromParent_Done,
53438 // Label 3087: @149025
53439 GIM_Try, /*On fail goto*//*Label 3088*/ GIMT_Encode4(149070), // Rule ID 1410 //
53440 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53441 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
53442 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
53443 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
53444 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
53445 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53446 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53447 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53448 // (intrinsic_wo_chain:{ *:[v4i16] } 642:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQDMULHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
53449 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv4i16),
53450 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53451 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53452 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53453 GIR_RootConstrainSelectedInstOperands,
53454 // GIR_Coverage, 1410,
53455 GIR_EraseRootFromParent_Done,
53456 // Label 3088: @149070
53457 GIM_Try, /*On fail goto*//*Label 3089*/ GIMT_Encode4(149115), // Rule ID 1411 //
53458 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53459 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
53460 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
53461 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
53462 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
53463 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53464 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53465 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53466 // (intrinsic_wo_chain:{ *:[v8i16] } 642:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQDMULHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
53467 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv8i16),
53468 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53469 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53470 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53471 GIR_RootConstrainSelectedInstOperands,
53472 // GIR_Coverage, 1411,
53473 GIR_EraseRootFromParent_Done,
53474 // Label 3089: @149115
53475 GIM_Try, /*On fail goto*//*Label 3090*/ GIMT_Encode4(149160), // Rule ID 1412 //
53476 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53477 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
53478 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
53479 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
53480 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
53481 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53482 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53483 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53484 // (intrinsic_wo_chain:{ *:[v2i32] } 642:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQDMULHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
53485 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv2i32),
53486 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53487 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53488 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53489 GIR_RootConstrainSelectedInstOperands,
53490 // GIR_Coverage, 1412,
53491 GIR_EraseRootFromParent_Done,
53492 // Label 3090: @149160
53493 GIM_Try, /*On fail goto*//*Label 3091*/ GIMT_Encode4(149205), // Rule ID 1413 //
53494 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53495 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
53496 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
53497 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
53498 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
53499 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53500 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53501 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53502 // (intrinsic_wo_chain:{ *:[v4i32] } 642:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQDMULHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
53503 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv4i32),
53504 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53505 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53506 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53507 GIR_RootConstrainSelectedInstOperands,
53508 // GIR_Coverage, 1413,
53509 GIR_EraseRootFromParent_Done,
53510 // Label 3091: @149205
53511 GIM_Try, /*On fail goto*//*Label 3092*/ GIMT_Encode4(149250), // Rule ID 1414 //
53512 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53513 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
53514 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
53515 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
53516 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
53517 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53518 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53519 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53520 // (intrinsic_wo_chain:{ *:[v4i16] } 650:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQRDMULHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
53521 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv4i16),
53522 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53523 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53524 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53525 GIR_RootConstrainSelectedInstOperands,
53526 // GIR_Coverage, 1414,
53527 GIR_EraseRootFromParent_Done,
53528 // Label 3092: @149250
53529 GIM_Try, /*On fail goto*//*Label 3093*/ GIMT_Encode4(149295), // Rule ID 1415 //
53530 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53531 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
53532 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
53533 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
53534 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
53535 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53536 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53537 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53538 // (intrinsic_wo_chain:{ *:[v8i16] } 650:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQRDMULHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
53539 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv8i16),
53540 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53541 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53542 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53543 GIR_RootConstrainSelectedInstOperands,
53544 // GIR_Coverage, 1415,
53545 GIR_EraseRootFromParent_Done,
53546 // Label 3093: @149295
53547 GIM_Try, /*On fail goto*//*Label 3094*/ GIMT_Encode4(149340), // Rule ID 1416 //
53548 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53549 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
53550 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
53551 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
53552 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
53553 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53554 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53555 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53556 // (intrinsic_wo_chain:{ *:[v2i32] } 650:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQRDMULHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
53557 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv2i32),
53558 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53559 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53560 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53561 GIR_RootConstrainSelectedInstOperands,
53562 // GIR_Coverage, 1416,
53563 GIR_EraseRootFromParent_Done,
53564 // Label 3094: @149340
53565 GIM_Try, /*On fail goto*//*Label 3095*/ GIMT_Encode4(149385), // Rule ID 1417 //
53566 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53567 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
53568 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
53569 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
53570 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
53571 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53572 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53573 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53574 // (intrinsic_wo_chain:{ *:[v4i32] } 650:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQRDMULHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
53575 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv4i32),
53576 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53577 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53578 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53579 GIR_RootConstrainSelectedInstOperands,
53580 // GIR_Coverage, 1417,
53581 GIR_EraseRootFromParent_Done,
53582 // Label 3095: @149385
53583 GIM_Try, /*On fail goto*//*Label 3096*/ GIMT_Encode4(149430), // Rule ID 1418 //
53584 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53585 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
53586 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
53587 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
53588 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
53589 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53590 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53591 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53592 // (intrinsic_wo_chain:{ *:[v8i8] } 653:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
53593 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv8i8),
53594 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53595 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53596 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53597 GIR_RootConstrainSelectedInstOperands,
53598 // GIR_Coverage, 1418,
53599 GIR_EraseRootFromParent_Done,
53600 // Label 3096: @149430
53601 GIM_Try, /*On fail goto*//*Label 3097*/ GIMT_Encode4(149475), // Rule ID 1419 //
53602 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53603 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
53604 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
53605 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
53606 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
53607 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53608 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53609 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53610 // (intrinsic_wo_chain:{ *:[v16i8] } 653:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
53611 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv16i8),
53612 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53613 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53614 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53615 GIR_RootConstrainSelectedInstOperands,
53616 // GIR_Coverage, 1419,
53617 GIR_EraseRootFromParent_Done,
53618 // Label 3097: @149475
53619 GIM_Try, /*On fail goto*//*Label 3098*/ GIMT_Encode4(149520), // Rule ID 1420 //
53620 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53621 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
53622 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
53623 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
53624 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
53625 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53626 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53627 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53628 // (intrinsic_wo_chain:{ *:[v4i16] } 653:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
53629 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv4i16),
53630 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53631 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53632 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53633 GIR_RootConstrainSelectedInstOperands,
53634 // GIR_Coverage, 1420,
53635 GIR_EraseRootFromParent_Done,
53636 // Label 3098: @149520
53637 GIM_Try, /*On fail goto*//*Label 3099*/ GIMT_Encode4(149565), // Rule ID 1421 //
53638 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53639 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
53640 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
53641 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
53642 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
53643 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53644 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53645 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53646 // (intrinsic_wo_chain:{ *:[v8i16] } 653:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
53647 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv8i16),
53648 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53649 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53650 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53651 GIR_RootConstrainSelectedInstOperands,
53652 // GIR_Coverage, 1421,
53653 GIR_EraseRootFromParent_Done,
53654 // Label 3099: @149565
53655 GIM_Try, /*On fail goto*//*Label 3100*/ GIMT_Encode4(149610), // Rule ID 1422 //
53656 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53657 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
53658 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
53659 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
53660 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
53661 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53662 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53663 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53664 // (intrinsic_wo_chain:{ *:[v2i32] } 653:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
53665 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv2i32),
53666 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53667 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53668 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53669 GIR_RootConstrainSelectedInstOperands,
53670 // GIR_Coverage, 1422,
53671 GIR_EraseRootFromParent_Done,
53672 // Label 3100: @149610
53673 GIM_Try, /*On fail goto*//*Label 3101*/ GIMT_Encode4(149655), // Rule ID 1423 //
53674 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53675 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
53676 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
53677 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
53678 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
53679 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53680 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53681 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53682 // (intrinsic_wo_chain:{ *:[v4i32] } 653:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
53683 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv4i32),
53684 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53685 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53686 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53687 GIR_RootConstrainSelectedInstOperands,
53688 // GIR_Coverage, 1423,
53689 GIR_EraseRootFromParent_Done,
53690 // Label 3101: @149655
53691 GIM_Try, /*On fail goto*//*Label 3102*/ GIMT_Encode4(149700), // Rule ID 1424 //
53692 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53693 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
53694 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
53695 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
53696 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
53697 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53698 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53699 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53700 // (intrinsic_wo_chain:{ *:[v2i64] } 653:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
53701 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv2i64),
53702 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53703 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53704 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53705 GIR_RootConstrainSelectedInstOperands,
53706 // GIR_Coverage, 1424,
53707 GIR_EraseRootFromParent_Done,
53708 // Label 3102: @149700
53709 GIM_Try, /*On fail goto*//*Label 3103*/ GIMT_Encode4(149745), // Rule ID 1425 //
53710 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53711 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
53712 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
53713 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
53714 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
53715 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53716 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53717 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53718 // (intrinsic_wo_chain:{ *:[v8i8] } 656:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
53719 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv8i8),
53720 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53721 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53722 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53723 GIR_RootConstrainSelectedInstOperands,
53724 // GIR_Coverage, 1425,
53725 GIR_EraseRootFromParent_Done,
53726 // Label 3103: @149745
53727 GIM_Try, /*On fail goto*//*Label 3104*/ GIMT_Encode4(149790), // Rule ID 1426 //
53728 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53729 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
53730 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
53731 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
53732 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
53733 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53734 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53735 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53736 // (intrinsic_wo_chain:{ *:[v16i8] } 656:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
53737 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv16i8),
53738 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53739 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53740 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53741 GIR_RootConstrainSelectedInstOperands,
53742 // GIR_Coverage, 1426,
53743 GIR_EraseRootFromParent_Done,
53744 // Label 3104: @149790
53745 GIM_Try, /*On fail goto*//*Label 3105*/ GIMT_Encode4(149835), // Rule ID 1427 //
53746 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53747 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
53748 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
53749 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
53750 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
53751 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53752 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53753 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53754 // (intrinsic_wo_chain:{ *:[v4i16] } 656:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
53755 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv4i16),
53756 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53757 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53758 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53759 GIR_RootConstrainSelectedInstOperands,
53760 // GIR_Coverage, 1427,
53761 GIR_EraseRootFromParent_Done,
53762 // Label 3105: @149835
53763 GIM_Try, /*On fail goto*//*Label 3106*/ GIMT_Encode4(149880), // Rule ID 1428 //
53764 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53765 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
53766 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
53767 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
53768 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
53769 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53770 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53771 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53772 // (intrinsic_wo_chain:{ *:[v8i16] } 656:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
53773 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv8i16),
53774 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53775 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53776 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53777 GIR_RootConstrainSelectedInstOperands,
53778 // GIR_Coverage, 1428,
53779 GIR_EraseRootFromParent_Done,
53780 // Label 3106: @149880
53781 GIM_Try, /*On fail goto*//*Label 3107*/ GIMT_Encode4(149925), // Rule ID 1429 //
53782 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53783 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
53784 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
53785 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
53786 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
53787 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53788 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53789 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53790 // (intrinsic_wo_chain:{ *:[v2i32] } 656:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
53791 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv2i32),
53792 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53793 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53794 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53795 GIR_RootConstrainSelectedInstOperands,
53796 // GIR_Coverage, 1429,
53797 GIR_EraseRootFromParent_Done,
53798 // Label 3107: @149925
53799 GIM_Try, /*On fail goto*//*Label 3108*/ GIMT_Encode4(149970), // Rule ID 1430 //
53800 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53801 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
53802 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
53803 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
53804 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
53805 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53806 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53807 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53808 // (intrinsic_wo_chain:{ *:[v4i32] } 656:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
53809 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv4i32),
53810 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53811 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53812 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53813 GIR_RootConstrainSelectedInstOperands,
53814 // GIR_Coverage, 1430,
53815 GIR_EraseRootFromParent_Done,
53816 // Label 3108: @149970
53817 GIM_Try, /*On fail goto*//*Label 3109*/ GIMT_Encode4(150015), // Rule ID 1431 //
53818 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53819 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
53820 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
53821 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
53822 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
53823 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53824 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53825 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53826 // (intrinsic_wo_chain:{ *:[v2i64] } 656:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
53827 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv2i64),
53828 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53829 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53830 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53831 GIR_RootConstrainSelectedInstOperands,
53832 // GIR_Coverage, 1431,
53833 GIR_EraseRootFromParent_Done,
53834 // Label 3109: @150015
53835 GIM_Try, /*On fail goto*//*Label 3110*/ GIMT_Encode4(150060), // Rule ID 1432 //
53836 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53837 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
53838 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
53839 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
53840 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
53841 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53842 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53843 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53844 // (intrinsic_wo_chain:{ *:[v8i8] } 660:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
53845 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv8i8),
53846 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53847 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53848 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53849 GIR_RootConstrainSelectedInstOperands,
53850 // GIR_Coverage, 1432,
53851 GIR_EraseRootFromParent_Done,
53852 // Label 3110: @150060
53853 GIM_Try, /*On fail goto*//*Label 3111*/ GIMT_Encode4(150105), // Rule ID 1433 //
53854 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53855 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
53856 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
53857 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
53858 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
53859 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53860 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53861 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53862 // (intrinsic_wo_chain:{ *:[v16i8] } 660:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
53863 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv16i8),
53864 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53865 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53866 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53867 GIR_RootConstrainSelectedInstOperands,
53868 // GIR_Coverage, 1433,
53869 GIR_EraseRootFromParent_Done,
53870 // Label 3111: @150105
53871 GIM_Try, /*On fail goto*//*Label 3112*/ GIMT_Encode4(150150), // Rule ID 1434 //
53872 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53873 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
53874 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
53875 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
53876 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
53877 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53878 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53879 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53880 // (intrinsic_wo_chain:{ *:[v4i16] } 660:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
53881 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv4i16),
53882 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53883 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53884 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53885 GIR_RootConstrainSelectedInstOperands,
53886 // GIR_Coverage, 1434,
53887 GIR_EraseRootFromParent_Done,
53888 // Label 3112: @150150
53889 GIM_Try, /*On fail goto*//*Label 3113*/ GIMT_Encode4(150195), // Rule ID 1435 //
53890 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53891 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
53892 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
53893 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
53894 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
53895 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53896 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53897 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53898 // (intrinsic_wo_chain:{ *:[v8i16] } 660:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
53899 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv8i16),
53900 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53901 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53902 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53903 GIR_RootConstrainSelectedInstOperands,
53904 // GIR_Coverage, 1435,
53905 GIR_EraseRootFromParent_Done,
53906 // Label 3113: @150195
53907 GIM_Try, /*On fail goto*//*Label 3114*/ GIMT_Encode4(150240), // Rule ID 1436 //
53908 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53909 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
53910 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
53911 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
53912 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
53913 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53914 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53915 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53916 // (intrinsic_wo_chain:{ *:[v2i32] } 660:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
53917 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv2i32),
53918 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53919 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53920 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53921 GIR_RootConstrainSelectedInstOperands,
53922 // GIR_Coverage, 1436,
53923 GIR_EraseRootFromParent_Done,
53924 // Label 3114: @150240
53925 GIM_Try, /*On fail goto*//*Label 3115*/ GIMT_Encode4(150285), // Rule ID 1437 //
53926 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53927 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
53928 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
53929 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
53930 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
53931 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53932 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53933 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53934 // (intrinsic_wo_chain:{ *:[v4i32] } 660:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
53935 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv4i32),
53936 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53937 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53938 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53939 GIR_RootConstrainSelectedInstOperands,
53940 // GIR_Coverage, 1437,
53941 GIR_EraseRootFromParent_Done,
53942 // Label 3115: @150285
53943 GIM_Try, /*On fail goto*//*Label 3116*/ GIMT_Encode4(150330), // Rule ID 1438 //
53944 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53945 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
53946 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
53947 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
53948 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
53949 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53950 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53951 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53952 // (intrinsic_wo_chain:{ *:[v2i64] } 660:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
53953 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv2i64),
53954 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53955 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53956 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53957 GIR_RootConstrainSelectedInstOperands,
53958 // GIR_Coverage, 1438,
53959 GIR_EraseRootFromParent_Done,
53960 // Label 3116: @150330
53961 GIM_Try, /*On fail goto*//*Label 3117*/ GIMT_Encode4(150375), // Rule ID 1445 //
53962 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53963 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
53964 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
53965 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
53966 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
53967 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53968 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53969 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
53970 // (intrinsic_wo_chain:{ *:[v8i8] } 664:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
53971 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv8i8),
53972 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53973 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53974 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53975 GIR_RootConstrainSelectedInstOperands,
53976 // GIR_Coverage, 1445,
53977 GIR_EraseRootFromParent_Done,
53978 // Label 3117: @150375
53979 GIM_Try, /*On fail goto*//*Label 3118*/ GIMT_Encode4(150420), // Rule ID 1446 //
53980 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53981 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
53982 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
53983 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
53984 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
53985 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53986 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53987 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
53988 // (intrinsic_wo_chain:{ *:[v16i8] } 664:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
53989 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv16i8),
53990 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
53991 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
53992 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
53993 GIR_RootConstrainSelectedInstOperands,
53994 // GIR_Coverage, 1446,
53995 GIR_EraseRootFromParent_Done,
53996 // Label 3118: @150420
53997 GIM_Try, /*On fail goto*//*Label 3119*/ GIMT_Encode4(150465), // Rule ID 1447 //
53998 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
53999 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
54000 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
54001 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
54002 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
54003 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54004 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54005 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54006 // (intrinsic_wo_chain:{ *:[v4i16] } 664:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
54007 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv4i16),
54008 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54009 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54010 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54011 GIR_RootConstrainSelectedInstOperands,
54012 // GIR_Coverage, 1447,
54013 GIR_EraseRootFromParent_Done,
54014 // Label 3119: @150465
54015 GIM_Try, /*On fail goto*//*Label 3120*/ GIMT_Encode4(150510), // Rule ID 1448 //
54016 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54017 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
54018 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
54019 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
54020 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
54021 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54022 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54023 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54024 // (intrinsic_wo_chain:{ *:[v8i16] } 664:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
54025 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv8i16),
54026 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54027 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54028 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54029 GIR_RootConstrainSelectedInstOperands,
54030 // GIR_Coverage, 1448,
54031 GIR_EraseRootFromParent_Done,
54032 // Label 3120: @150510
54033 GIM_Try, /*On fail goto*//*Label 3121*/ GIMT_Encode4(150555), // Rule ID 1449 //
54034 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54035 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
54036 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
54037 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
54038 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
54039 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54040 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54041 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54042 // (intrinsic_wo_chain:{ *:[v2i32] } 664:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
54043 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv2i32),
54044 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54045 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54046 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54047 GIR_RootConstrainSelectedInstOperands,
54048 // GIR_Coverage, 1449,
54049 GIR_EraseRootFromParent_Done,
54050 // Label 3121: @150555
54051 GIM_Try, /*On fail goto*//*Label 3122*/ GIMT_Encode4(150600), // Rule ID 1450 //
54052 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54053 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
54054 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
54055 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54056 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
54057 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54058 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54059 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54060 // (intrinsic_wo_chain:{ *:[v4i32] } 664:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
54061 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv4i32),
54062 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54063 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54064 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54065 GIR_RootConstrainSelectedInstOperands,
54066 // GIR_Coverage, 1450,
54067 GIR_EraseRootFromParent_Done,
54068 // Label 3122: @150600
54069 GIM_Try, /*On fail goto*//*Label 3123*/ GIMT_Encode4(150645), // Rule ID 1451 //
54070 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54071 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
54072 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
54073 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
54074 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
54075 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54076 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54077 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54078 // (intrinsic_wo_chain:{ *:[v2i64] } 664:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
54079 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv2i64),
54080 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54081 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54082 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54083 GIR_RootConstrainSelectedInstOperands,
54084 // GIR_Coverage, 1451,
54085 GIR_EraseRootFromParent_Done,
54086 // Label 3123: @150645
54087 GIM_Try, /*On fail goto*//*Label 3124*/ GIMT_Encode4(150690), // Rule ID 1452 //
54088 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54089 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
54090 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
54091 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
54092 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
54093 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54094 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54095 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54096 // (intrinsic_wo_chain:{ *:[v8i8] } 665:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
54097 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv8i8),
54098 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54099 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54100 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54101 GIR_RootConstrainSelectedInstOperands,
54102 // GIR_Coverage, 1452,
54103 GIR_EraseRootFromParent_Done,
54104 // Label 3124: @150690
54105 GIM_Try, /*On fail goto*//*Label 3125*/ GIMT_Encode4(150735), // Rule ID 1453 //
54106 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54107 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
54108 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
54109 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
54110 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
54111 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54112 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54113 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54114 // (intrinsic_wo_chain:{ *:[v16i8] } 665:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
54115 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv16i8),
54116 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54117 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54118 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54119 GIR_RootConstrainSelectedInstOperands,
54120 // GIR_Coverage, 1453,
54121 GIR_EraseRootFromParent_Done,
54122 // Label 3125: @150735
54123 GIM_Try, /*On fail goto*//*Label 3126*/ GIMT_Encode4(150780), // Rule ID 1454 //
54124 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54125 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
54126 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
54127 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
54128 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
54129 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54130 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54131 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54132 // (intrinsic_wo_chain:{ *:[v4i16] } 665:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
54133 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv4i16),
54134 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54135 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54136 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54137 GIR_RootConstrainSelectedInstOperands,
54138 // GIR_Coverage, 1454,
54139 GIR_EraseRootFromParent_Done,
54140 // Label 3126: @150780
54141 GIM_Try, /*On fail goto*//*Label 3127*/ GIMT_Encode4(150825), // Rule ID 1455 //
54142 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54143 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
54144 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
54145 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
54146 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
54147 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54148 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54149 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54150 // (intrinsic_wo_chain:{ *:[v8i16] } 665:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
54151 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv8i16),
54152 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54153 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54154 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54155 GIR_RootConstrainSelectedInstOperands,
54156 // GIR_Coverage, 1455,
54157 GIR_EraseRootFromParent_Done,
54158 // Label 3127: @150825
54159 GIM_Try, /*On fail goto*//*Label 3128*/ GIMT_Encode4(150870), // Rule ID 1456 //
54160 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54161 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
54162 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
54163 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
54164 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
54165 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54166 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54167 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54168 // (intrinsic_wo_chain:{ *:[v2i32] } 665:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
54169 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv2i32),
54170 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54171 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54172 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54173 GIR_RootConstrainSelectedInstOperands,
54174 // GIR_Coverage, 1456,
54175 GIR_EraseRootFromParent_Done,
54176 // Label 3128: @150870
54177 GIM_Try, /*On fail goto*//*Label 3129*/ GIMT_Encode4(150915), // Rule ID 1457 //
54178 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54179 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
54180 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
54181 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54182 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
54183 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54184 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54185 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54186 // (intrinsic_wo_chain:{ *:[v4i32] } 665:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
54187 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv4i32),
54188 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54189 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54190 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54191 GIR_RootConstrainSelectedInstOperands,
54192 // GIR_Coverage, 1457,
54193 GIR_EraseRootFromParent_Done,
54194 // Label 3129: @150915
54195 GIM_Try, /*On fail goto*//*Label 3130*/ GIMT_Encode4(150960), // Rule ID 1458 //
54196 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54197 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
54198 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
54199 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
54200 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
54201 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54202 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54203 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54204 // (intrinsic_wo_chain:{ *:[v2i64] } 665:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
54205 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv2i64),
54206 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54207 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54208 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54209 GIR_RootConstrainSelectedInstOperands,
54210 // GIR_Coverage, 1458,
54211 GIR_EraseRootFromParent_Done,
54212 // Label 3130: @150960
54213 GIM_Try, /*On fail goto*//*Label 3131*/ GIMT_Encode4(151005), // Rule ID 1479 //
54214 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54215 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
54216 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
54217 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
54218 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
54219 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54220 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54221 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54222 // (intrinsic_wo_chain:{ *:[v8i8] } 686:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UABDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
54223 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDv8i8),
54224 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54225 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54226 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54227 GIR_RootConstrainSelectedInstOperands,
54228 // GIR_Coverage, 1479,
54229 GIR_EraseRootFromParent_Done,
54230 // Label 3131: @151005
54231 GIM_Try, /*On fail goto*//*Label 3132*/ GIMT_Encode4(151050), // Rule ID 1481 //
54232 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54233 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
54234 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
54235 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
54236 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
54237 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54238 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54239 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54240 // (intrinsic_wo_chain:{ *:[v16i8] } 686:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UABDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
54241 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDv16i8),
54242 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54243 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54244 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54245 GIR_RootConstrainSelectedInstOperands,
54246 // GIR_Coverage, 1481,
54247 GIR_EraseRootFromParent_Done,
54248 // Label 3132: @151050
54249 GIM_Try, /*On fail goto*//*Label 3133*/ GIMT_Encode4(151095), // Rule ID 1483 //
54250 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54251 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
54252 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
54253 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
54254 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
54255 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54256 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54257 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54258 // (intrinsic_wo_chain:{ *:[v4i16] } 686:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UABDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
54259 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDv4i16),
54260 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54261 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54262 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54263 GIR_RootConstrainSelectedInstOperands,
54264 // GIR_Coverage, 1483,
54265 GIR_EraseRootFromParent_Done,
54266 // Label 3133: @151095
54267 GIM_Try, /*On fail goto*//*Label 3134*/ GIMT_Encode4(151140), // Rule ID 1485 //
54268 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54269 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
54270 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
54271 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
54272 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
54273 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54274 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54275 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54276 // (intrinsic_wo_chain:{ *:[v8i16] } 686:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UABDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
54277 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDv8i16),
54278 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54279 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54280 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54281 GIR_RootConstrainSelectedInstOperands,
54282 // GIR_Coverage, 1485,
54283 GIR_EraseRootFromParent_Done,
54284 // Label 3134: @151140
54285 GIM_Try, /*On fail goto*//*Label 3135*/ GIMT_Encode4(151185), // Rule ID 1487 //
54286 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54287 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
54288 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
54289 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
54290 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
54291 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54292 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54293 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54294 // (intrinsic_wo_chain:{ *:[v2i32] } 686:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UABDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
54295 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDv2i32),
54296 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54297 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54298 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54299 GIR_RootConstrainSelectedInstOperands,
54300 // GIR_Coverage, 1487,
54301 GIR_EraseRootFromParent_Done,
54302 // Label 3135: @151185
54303 GIM_Try, /*On fail goto*//*Label 3136*/ GIMT_Encode4(151230), // Rule ID 1489 //
54304 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54305 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
54306 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
54307 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54308 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
54309 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54310 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54311 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54312 // (intrinsic_wo_chain:{ *:[v4i32] } 686:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UABDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
54313 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDv4i32),
54314 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54315 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54316 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54317 GIR_RootConstrainSelectedInstOperands,
54318 // GIR_Coverage, 1489,
54319 GIR_EraseRootFromParent_Done,
54320 // Label 3136: @151230
54321 GIM_Try, /*On fail goto*//*Label 3137*/ GIMT_Encode4(151275), // Rule ID 1496 //
54322 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54323 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uhsub),
54324 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
54325 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
54326 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
54327 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54328 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54329 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54330 // (intrinsic_wo_chain:{ *:[v8i8] } 692:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UHSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
54331 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBv8i8),
54332 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54333 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54334 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54335 GIR_RootConstrainSelectedInstOperands,
54336 // GIR_Coverage, 1496,
54337 GIR_EraseRootFromParent_Done,
54338 // Label 3137: @151275
54339 GIM_Try, /*On fail goto*//*Label 3138*/ GIMT_Encode4(151320), // Rule ID 1497 //
54340 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54341 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uhsub),
54342 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
54343 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
54344 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
54345 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54346 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54347 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54348 // (intrinsic_wo_chain:{ *:[v16i8] } 692:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UHSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
54349 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBv16i8),
54350 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54351 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54352 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54353 GIR_RootConstrainSelectedInstOperands,
54354 // GIR_Coverage, 1497,
54355 GIR_EraseRootFromParent_Done,
54356 // Label 3138: @151320
54357 GIM_Try, /*On fail goto*//*Label 3139*/ GIMT_Encode4(151365), // Rule ID 1498 //
54358 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54359 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uhsub),
54360 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
54361 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
54362 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
54363 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54364 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54365 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54366 // (intrinsic_wo_chain:{ *:[v4i16] } 692:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UHSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
54367 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBv4i16),
54368 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54369 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54370 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54371 GIR_RootConstrainSelectedInstOperands,
54372 // GIR_Coverage, 1498,
54373 GIR_EraseRootFromParent_Done,
54374 // Label 3139: @151365
54375 GIM_Try, /*On fail goto*//*Label 3140*/ GIMT_Encode4(151410), // Rule ID 1499 //
54376 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54377 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uhsub),
54378 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
54379 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
54380 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
54381 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54382 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54383 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54384 // (intrinsic_wo_chain:{ *:[v8i16] } 692:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UHSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
54385 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBv8i16),
54386 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54387 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54388 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54389 GIR_RootConstrainSelectedInstOperands,
54390 // GIR_Coverage, 1499,
54391 GIR_EraseRootFromParent_Done,
54392 // Label 3140: @151410
54393 GIM_Try, /*On fail goto*//*Label 3141*/ GIMT_Encode4(151455), // Rule ID 1500 //
54394 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54395 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uhsub),
54396 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
54397 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
54398 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
54399 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54400 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54401 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54402 // (intrinsic_wo_chain:{ *:[v2i32] } 692:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UHSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
54403 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBv2i32),
54404 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54405 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54406 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54407 GIR_RootConstrainSelectedInstOperands,
54408 // GIR_Coverage, 1500,
54409 GIR_EraseRootFromParent_Done,
54410 // Label 3141: @151455
54411 GIM_Try, /*On fail goto*//*Label 3142*/ GIMT_Encode4(151500), // Rule ID 1501 //
54412 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54413 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uhsub),
54414 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
54415 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54416 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
54417 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54418 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54419 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54420 // (intrinsic_wo_chain:{ *:[v4i32] } 692:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UHSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
54421 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBv4i32),
54422 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54423 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54424 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54425 GIR_RootConstrainSelectedInstOperands,
54426 // GIR_Coverage, 1501,
54427 GIR_EraseRootFromParent_Done,
54428 // Label 3142: @151500
54429 GIM_Try, /*On fail goto*//*Label 3143*/ GIMT_Encode4(151545), // Rule ID 1502 //
54430 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54431 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxp),
54432 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
54433 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
54434 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
54435 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54436 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54437 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54438 // (intrinsic_wo_chain:{ *:[v8i8] } 694:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMAXPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
54439 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv8i8),
54440 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54441 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54442 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54443 GIR_RootConstrainSelectedInstOperands,
54444 // GIR_Coverage, 1502,
54445 GIR_EraseRootFromParent_Done,
54446 // Label 3143: @151545
54447 GIM_Try, /*On fail goto*//*Label 3144*/ GIMT_Encode4(151590), // Rule ID 1503 //
54448 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54449 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxp),
54450 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
54451 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
54452 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
54453 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54454 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54455 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54456 // (intrinsic_wo_chain:{ *:[v16i8] } 694:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMAXPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
54457 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv16i8),
54458 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54459 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54460 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54461 GIR_RootConstrainSelectedInstOperands,
54462 // GIR_Coverage, 1503,
54463 GIR_EraseRootFromParent_Done,
54464 // Label 3144: @151590
54465 GIM_Try, /*On fail goto*//*Label 3145*/ GIMT_Encode4(151635), // Rule ID 1504 //
54466 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54467 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxp),
54468 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
54469 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
54470 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
54471 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54472 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54473 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54474 // (intrinsic_wo_chain:{ *:[v4i16] } 694:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMAXPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
54475 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv4i16),
54476 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54477 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54478 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54479 GIR_RootConstrainSelectedInstOperands,
54480 // GIR_Coverage, 1504,
54481 GIR_EraseRootFromParent_Done,
54482 // Label 3145: @151635
54483 GIM_Try, /*On fail goto*//*Label 3146*/ GIMT_Encode4(151680), // Rule ID 1505 //
54484 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54485 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxp),
54486 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
54487 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
54488 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
54489 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54490 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54491 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54492 // (intrinsic_wo_chain:{ *:[v8i16] } 694:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UMAXPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
54493 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv8i16),
54494 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54495 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54496 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54497 GIR_RootConstrainSelectedInstOperands,
54498 // GIR_Coverage, 1505,
54499 GIR_EraseRootFromParent_Done,
54500 // Label 3146: @151680
54501 GIM_Try, /*On fail goto*//*Label 3147*/ GIMT_Encode4(151725), // Rule ID 1506 //
54502 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54503 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxp),
54504 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
54505 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
54506 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
54507 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54508 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54509 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54510 // (intrinsic_wo_chain:{ *:[v2i32] } 694:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMAXPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
54511 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv2i32),
54512 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54513 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54514 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54515 GIR_RootConstrainSelectedInstOperands,
54516 // GIR_Coverage, 1506,
54517 GIR_EraseRootFromParent_Done,
54518 // Label 3147: @151725
54519 GIM_Try, /*On fail goto*//*Label 3148*/ GIMT_Encode4(151770), // Rule ID 1507 //
54520 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54521 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxp),
54522 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
54523 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54524 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
54525 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54526 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54527 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54528 // (intrinsic_wo_chain:{ *:[v4i32] } 694:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UMAXPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
54529 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv4i32),
54530 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54531 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54532 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54533 GIR_RootConstrainSelectedInstOperands,
54534 // GIR_Coverage, 1507,
54535 GIR_EraseRootFromParent_Done,
54536 // Label 3148: @151770
54537 GIM_Try, /*On fail goto*//*Label 3149*/ GIMT_Encode4(151815), // Rule ID 1514 //
54538 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54539 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminp),
54540 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
54541 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
54542 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
54543 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54544 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54545 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54546 // (intrinsic_wo_chain:{ *:[v8i8] } 697:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMINPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
54547 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINPv8i8),
54548 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54549 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54550 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54551 GIR_RootConstrainSelectedInstOperands,
54552 // GIR_Coverage, 1514,
54553 GIR_EraseRootFromParent_Done,
54554 // Label 3149: @151815
54555 GIM_Try, /*On fail goto*//*Label 3150*/ GIMT_Encode4(151860), // Rule ID 1515 //
54556 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54557 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminp),
54558 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
54559 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
54560 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
54561 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54562 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54563 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54564 // (intrinsic_wo_chain:{ *:[v16i8] } 697:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMINPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
54565 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINPv16i8),
54566 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54567 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54568 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54569 GIR_RootConstrainSelectedInstOperands,
54570 // GIR_Coverage, 1515,
54571 GIR_EraseRootFromParent_Done,
54572 // Label 3150: @151860
54573 GIM_Try, /*On fail goto*//*Label 3151*/ GIMT_Encode4(151905), // Rule ID 1516 //
54574 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54575 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminp),
54576 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
54577 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
54578 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
54579 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54580 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54581 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54582 // (intrinsic_wo_chain:{ *:[v4i16] } 697:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMINPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
54583 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINPv4i16),
54584 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54585 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54586 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54587 GIR_RootConstrainSelectedInstOperands,
54588 // GIR_Coverage, 1516,
54589 GIR_EraseRootFromParent_Done,
54590 // Label 3151: @151905
54591 GIM_Try, /*On fail goto*//*Label 3152*/ GIMT_Encode4(151950), // Rule ID 1517 //
54592 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54593 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminp),
54594 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
54595 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
54596 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
54597 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54598 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54599 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54600 // (intrinsic_wo_chain:{ *:[v8i16] } 697:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UMINPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
54601 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINPv8i16),
54602 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54603 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54604 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54605 GIR_RootConstrainSelectedInstOperands,
54606 // GIR_Coverage, 1517,
54607 GIR_EraseRootFromParent_Done,
54608 // Label 3152: @151950
54609 GIM_Try, /*On fail goto*//*Label 3153*/ GIMT_Encode4(151995), // Rule ID 1518 //
54610 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54611 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminp),
54612 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
54613 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
54614 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
54615 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54616 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54617 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54618 // (intrinsic_wo_chain:{ *:[v2i32] } 697:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMINPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
54619 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINPv2i32),
54620 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54621 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54622 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54623 GIR_RootConstrainSelectedInstOperands,
54624 // GIR_Coverage, 1518,
54625 GIR_EraseRootFromParent_Done,
54626 // Label 3153: @151995
54627 GIM_Try, /*On fail goto*//*Label 3154*/ GIMT_Encode4(152040), // Rule ID 1519 //
54628 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54629 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminp),
54630 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
54631 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54632 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
54633 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54634 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54635 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54636 // (intrinsic_wo_chain:{ *:[v4i32] } 697:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UMINPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
54637 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINPv4i32),
54638 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54639 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54640 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54641 GIR_RootConstrainSelectedInstOperands,
54642 // GIR_Coverage, 1519,
54643 GIR_EraseRootFromParent_Done,
54644 // Label 3154: @152040
54645 GIM_Try, /*On fail goto*//*Label 3155*/ GIMT_Encode4(152085), // Rule ID 1526 //
54646 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54647 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqadd),
54648 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
54649 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
54650 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
54651 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54652 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54653 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54654 // (intrinsic_wo_chain:{ *:[v8i8] } 701:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
54655 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADDv8i8),
54656 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54657 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54658 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54659 GIR_RootConstrainSelectedInstOperands,
54660 // GIR_Coverage, 1526,
54661 GIR_EraseRootFromParent_Done,
54662 // Label 3155: @152085
54663 GIM_Try, /*On fail goto*//*Label 3156*/ GIMT_Encode4(152130), // Rule ID 1527 //
54664 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54665 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqadd),
54666 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
54667 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
54668 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
54669 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54670 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54671 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54672 // (intrinsic_wo_chain:{ *:[v16i8] } 701:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
54673 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADDv16i8),
54674 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54675 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54676 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54677 GIR_RootConstrainSelectedInstOperands,
54678 // GIR_Coverage, 1527,
54679 GIR_EraseRootFromParent_Done,
54680 // Label 3156: @152130
54681 GIM_Try, /*On fail goto*//*Label 3157*/ GIMT_Encode4(152175), // Rule ID 1528 //
54682 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54683 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqadd),
54684 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
54685 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
54686 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
54687 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54688 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54689 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54690 // (intrinsic_wo_chain:{ *:[v4i16] } 701:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
54691 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADDv4i16),
54692 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54693 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54694 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54695 GIR_RootConstrainSelectedInstOperands,
54696 // GIR_Coverage, 1528,
54697 GIR_EraseRootFromParent_Done,
54698 // Label 3157: @152175
54699 GIM_Try, /*On fail goto*//*Label 3158*/ GIMT_Encode4(152220), // Rule ID 1529 //
54700 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54701 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqadd),
54702 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
54703 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
54704 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
54705 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54706 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54707 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54708 // (intrinsic_wo_chain:{ *:[v8i16] } 701:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
54709 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADDv8i16),
54710 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54711 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54712 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54713 GIR_RootConstrainSelectedInstOperands,
54714 // GIR_Coverage, 1529,
54715 GIR_EraseRootFromParent_Done,
54716 // Label 3158: @152220
54717 GIM_Try, /*On fail goto*//*Label 3159*/ GIMT_Encode4(152265), // Rule ID 1530 //
54718 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54719 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqadd),
54720 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
54721 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
54722 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
54723 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54724 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54725 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54726 // (intrinsic_wo_chain:{ *:[v2i32] } 701:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
54727 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADDv2i32),
54728 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54729 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54730 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54731 GIR_RootConstrainSelectedInstOperands,
54732 // GIR_Coverage, 1530,
54733 GIR_EraseRootFromParent_Done,
54734 // Label 3159: @152265
54735 GIM_Try, /*On fail goto*//*Label 3160*/ GIMT_Encode4(152310), // Rule ID 1531 //
54736 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54737 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqadd),
54738 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
54739 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54740 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
54741 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54742 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54743 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54744 // (intrinsic_wo_chain:{ *:[v4i32] } 701:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
54745 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADDv4i32),
54746 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54747 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54748 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54749 GIR_RootConstrainSelectedInstOperands,
54750 // GIR_Coverage, 1531,
54751 GIR_EraseRootFromParent_Done,
54752 // Label 3160: @152310
54753 GIM_Try, /*On fail goto*//*Label 3161*/ GIMT_Encode4(152355), // Rule ID 1532 //
54754 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54755 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqadd),
54756 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
54757 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
54758 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
54759 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54760 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54761 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54762 // (intrinsic_wo_chain:{ *:[v2i64] } 701:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
54763 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADDv2i64),
54764 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54765 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54766 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54767 GIR_RootConstrainSelectedInstOperands,
54768 // GIR_Coverage, 1532,
54769 GIR_EraseRootFromParent_Done,
54770 // Label 3161: @152355
54771 GIM_Try, /*On fail goto*//*Label 3162*/ GIMT_Encode4(152400), // Rule ID 1533 //
54772 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54773 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
54774 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
54775 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
54776 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
54777 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54778 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54779 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54780 // (intrinsic_wo_chain:{ *:[v8i8] } 702:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
54781 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv8i8),
54782 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54783 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54784 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54785 GIR_RootConstrainSelectedInstOperands,
54786 // GIR_Coverage, 1533,
54787 GIR_EraseRootFromParent_Done,
54788 // Label 3162: @152400
54789 GIM_Try, /*On fail goto*//*Label 3163*/ GIMT_Encode4(152445), // Rule ID 1534 //
54790 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54791 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
54792 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
54793 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
54794 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
54795 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54796 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54797 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54798 // (intrinsic_wo_chain:{ *:[v16i8] } 702:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
54799 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv16i8),
54800 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54801 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54802 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54803 GIR_RootConstrainSelectedInstOperands,
54804 // GIR_Coverage, 1534,
54805 GIR_EraseRootFromParent_Done,
54806 // Label 3163: @152445
54807 GIM_Try, /*On fail goto*//*Label 3164*/ GIMT_Encode4(152490), // Rule ID 1535 //
54808 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54809 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
54810 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
54811 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
54812 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
54813 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54814 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54815 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54816 // (intrinsic_wo_chain:{ *:[v4i16] } 702:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
54817 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv4i16),
54818 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54819 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54820 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54821 GIR_RootConstrainSelectedInstOperands,
54822 // GIR_Coverage, 1535,
54823 GIR_EraseRootFromParent_Done,
54824 // Label 3164: @152490
54825 GIM_Try, /*On fail goto*//*Label 3165*/ GIMT_Encode4(152535), // Rule ID 1536 //
54826 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54827 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
54828 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
54829 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
54830 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
54831 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54832 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54833 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54834 // (intrinsic_wo_chain:{ *:[v8i16] } 702:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
54835 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv8i16),
54836 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54837 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54838 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54839 GIR_RootConstrainSelectedInstOperands,
54840 // GIR_Coverage, 1536,
54841 GIR_EraseRootFromParent_Done,
54842 // Label 3165: @152535
54843 GIM_Try, /*On fail goto*//*Label 3166*/ GIMT_Encode4(152580), // Rule ID 1537 //
54844 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54845 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
54846 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
54847 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
54848 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
54849 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54850 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54851 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54852 // (intrinsic_wo_chain:{ *:[v2i32] } 702:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
54853 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv2i32),
54854 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54855 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54856 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54857 GIR_RootConstrainSelectedInstOperands,
54858 // GIR_Coverage, 1537,
54859 GIR_EraseRootFromParent_Done,
54860 // Label 3166: @152580
54861 GIM_Try, /*On fail goto*//*Label 3167*/ GIMT_Encode4(152625), // Rule ID 1538 //
54862 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54863 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
54864 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
54865 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54866 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
54867 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54868 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54869 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54870 // (intrinsic_wo_chain:{ *:[v4i32] } 702:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
54871 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv4i32),
54872 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54873 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54874 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54875 GIR_RootConstrainSelectedInstOperands,
54876 // GIR_Coverage, 1538,
54877 GIR_EraseRootFromParent_Done,
54878 // Label 3167: @152625
54879 GIM_Try, /*On fail goto*//*Label 3168*/ GIMT_Encode4(152670), // Rule ID 1539 //
54880 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54881 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
54882 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
54883 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
54884 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
54885 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54886 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54887 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54888 // (intrinsic_wo_chain:{ *:[v2i64] } 702:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
54889 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv2i64),
54890 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54891 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54892 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54893 GIR_RootConstrainSelectedInstOperands,
54894 // GIR_Coverage, 1539,
54895 GIR_EraseRootFromParent_Done,
54896 // Label 3168: @152670
54897 GIM_Try, /*On fail goto*//*Label 3169*/ GIMT_Encode4(152715), // Rule ID 1540 //
54898 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54899 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
54900 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
54901 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
54902 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
54903 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54904 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54905 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54906 // (intrinsic_wo_chain:{ *:[v8i8] } 704:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
54907 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv8i8),
54908 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54909 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54910 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54911 GIR_RootConstrainSelectedInstOperands,
54912 // GIR_Coverage, 1540,
54913 GIR_EraseRootFromParent_Done,
54914 // Label 3169: @152715
54915 GIM_Try, /*On fail goto*//*Label 3170*/ GIMT_Encode4(152760), // Rule ID 1541 //
54916 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54917 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
54918 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
54919 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
54920 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
54921 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54922 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54923 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54924 // (intrinsic_wo_chain:{ *:[v16i8] } 704:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
54925 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv16i8),
54926 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54927 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54928 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54929 GIR_RootConstrainSelectedInstOperands,
54930 // GIR_Coverage, 1541,
54931 GIR_EraseRootFromParent_Done,
54932 // Label 3170: @152760
54933 GIM_Try, /*On fail goto*//*Label 3171*/ GIMT_Encode4(152805), // Rule ID 1542 //
54934 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54935 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
54936 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
54937 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
54938 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
54939 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54940 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54941 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54942 // (intrinsic_wo_chain:{ *:[v4i16] } 704:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
54943 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv4i16),
54944 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54945 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54946 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54947 GIR_RootConstrainSelectedInstOperands,
54948 // GIR_Coverage, 1542,
54949 GIR_EraseRootFromParent_Done,
54950 // Label 3171: @152805
54951 GIM_Try, /*On fail goto*//*Label 3172*/ GIMT_Encode4(152850), // Rule ID 1543 //
54952 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54953 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
54954 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
54955 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
54956 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
54957 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54958 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54959 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54960 // (intrinsic_wo_chain:{ *:[v8i16] } 704:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
54961 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv8i16),
54962 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54963 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54964 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54965 GIR_RootConstrainSelectedInstOperands,
54966 // GIR_Coverage, 1543,
54967 GIR_EraseRootFromParent_Done,
54968 // Label 3172: @152850
54969 GIM_Try, /*On fail goto*//*Label 3173*/ GIMT_Encode4(152895), // Rule ID 1544 //
54970 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54971 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
54972 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
54973 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
54974 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
54975 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54976 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54977 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
54978 // (intrinsic_wo_chain:{ *:[v2i32] } 704:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
54979 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv2i32),
54980 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54981 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
54982 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
54983 GIR_RootConstrainSelectedInstOperands,
54984 // GIR_Coverage, 1544,
54985 GIR_EraseRootFromParent_Done,
54986 // Label 3173: @152895
54987 GIM_Try, /*On fail goto*//*Label 3174*/ GIMT_Encode4(152940), // Rule ID 1545 //
54988 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
54989 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
54990 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
54991 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
54992 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
54993 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54994 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54995 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
54996 // (intrinsic_wo_chain:{ *:[v4i32] } 704:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
54997 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv4i32),
54998 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
54999 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55000 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55001 GIR_RootConstrainSelectedInstOperands,
55002 // GIR_Coverage, 1545,
55003 GIR_EraseRootFromParent_Done,
55004 // Label 3174: @152940
55005 GIM_Try, /*On fail goto*//*Label 3175*/ GIMT_Encode4(152985), // Rule ID 1546 //
55006 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55007 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
55008 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
55009 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
55010 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
55011 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55012 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55013 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55014 // (intrinsic_wo_chain:{ *:[v2i64] } 704:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
55015 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv2i64),
55016 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55017 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55018 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55019 GIR_RootConstrainSelectedInstOperands,
55020 // GIR_Coverage, 1546,
55021 GIR_EraseRootFromParent_Done,
55022 // Label 3175: @152985
55023 GIM_Try, /*On fail goto*//*Label 3176*/ GIMT_Encode4(153030), // Rule ID 1547 //
55024 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55025 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqsub),
55026 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
55027 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
55028 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
55029 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55030 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55031 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55032 // (intrinsic_wo_chain:{ *:[v8i8] } 706:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
55033 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv8i8),
55034 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55035 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55036 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55037 GIR_RootConstrainSelectedInstOperands,
55038 // GIR_Coverage, 1547,
55039 GIR_EraseRootFromParent_Done,
55040 // Label 3176: @153030
55041 GIM_Try, /*On fail goto*//*Label 3177*/ GIMT_Encode4(153075), // Rule ID 1548 //
55042 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55043 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqsub),
55044 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
55045 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
55046 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
55047 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55048 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55049 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55050 // (intrinsic_wo_chain:{ *:[v16i8] } 706:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
55051 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv16i8),
55052 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55053 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55054 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55055 GIR_RootConstrainSelectedInstOperands,
55056 // GIR_Coverage, 1548,
55057 GIR_EraseRootFromParent_Done,
55058 // Label 3177: @153075
55059 GIM_Try, /*On fail goto*//*Label 3178*/ GIMT_Encode4(153120), // Rule ID 1549 //
55060 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55061 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqsub),
55062 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
55063 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
55064 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
55065 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55066 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55067 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55068 // (intrinsic_wo_chain:{ *:[v4i16] } 706:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
55069 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv4i16),
55070 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55071 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55072 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55073 GIR_RootConstrainSelectedInstOperands,
55074 // GIR_Coverage, 1549,
55075 GIR_EraseRootFromParent_Done,
55076 // Label 3178: @153120
55077 GIM_Try, /*On fail goto*//*Label 3179*/ GIMT_Encode4(153165), // Rule ID 1550 //
55078 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55079 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqsub),
55080 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
55081 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
55082 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
55083 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55084 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55085 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55086 // (intrinsic_wo_chain:{ *:[v8i16] } 706:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
55087 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv8i16),
55088 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55089 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55090 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55091 GIR_RootConstrainSelectedInstOperands,
55092 // GIR_Coverage, 1550,
55093 GIR_EraseRootFromParent_Done,
55094 // Label 3179: @153165
55095 GIM_Try, /*On fail goto*//*Label 3180*/ GIMT_Encode4(153210), // Rule ID 1551 //
55096 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55097 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqsub),
55098 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
55099 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
55100 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
55101 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55102 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55103 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55104 // (intrinsic_wo_chain:{ *:[v2i32] } 706:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
55105 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv2i32),
55106 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55107 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55108 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55109 GIR_RootConstrainSelectedInstOperands,
55110 // GIR_Coverage, 1551,
55111 GIR_EraseRootFromParent_Done,
55112 // Label 3180: @153210
55113 GIM_Try, /*On fail goto*//*Label 3181*/ GIMT_Encode4(153255), // Rule ID 1552 //
55114 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55115 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqsub),
55116 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
55117 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
55118 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
55119 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55120 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55121 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55122 // (intrinsic_wo_chain:{ *:[v4i32] } 706:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
55123 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv4i32),
55124 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55125 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55126 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55127 GIR_RootConstrainSelectedInstOperands,
55128 // GIR_Coverage, 1552,
55129 GIR_EraseRootFromParent_Done,
55130 // Label 3181: @153255
55131 GIM_Try, /*On fail goto*//*Label 3182*/ GIMT_Encode4(153300), // Rule ID 1553 //
55132 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55133 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqsub),
55134 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
55135 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
55136 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
55137 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55138 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55139 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55140 // (intrinsic_wo_chain:{ *:[v2i64] } 706:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
55141 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv2i64),
55142 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55143 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55144 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55145 GIR_RootConstrainSelectedInstOperands,
55146 // GIR_Coverage, 1553,
55147 GIR_EraseRootFromParent_Done,
55148 // Label 3182: @153300
55149 GIM_Try, /*On fail goto*//*Label 3183*/ GIMT_Encode4(153345), // Rule ID 1560 //
55150 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55151 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
55152 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
55153 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
55154 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
55155 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55156 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55157 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55158 // (intrinsic_wo_chain:{ *:[v8i8] } 710:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (URSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
55159 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv8i8),
55160 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55161 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55162 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55163 GIR_RootConstrainSelectedInstOperands,
55164 // GIR_Coverage, 1560,
55165 GIR_EraseRootFromParent_Done,
55166 // Label 3183: @153345
55167 GIM_Try, /*On fail goto*//*Label 3184*/ GIMT_Encode4(153390), // Rule ID 1561 //
55168 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55169 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
55170 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
55171 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
55172 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
55173 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55174 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55175 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55176 // (intrinsic_wo_chain:{ *:[v16i8] } 710:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (URSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
55177 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv16i8),
55178 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55179 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55180 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55181 GIR_RootConstrainSelectedInstOperands,
55182 // GIR_Coverage, 1561,
55183 GIR_EraseRootFromParent_Done,
55184 // Label 3184: @153390
55185 GIM_Try, /*On fail goto*//*Label 3185*/ GIMT_Encode4(153435), // Rule ID 1562 //
55186 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55187 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
55188 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
55189 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
55190 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
55191 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55192 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55193 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55194 // (intrinsic_wo_chain:{ *:[v4i16] } 710:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (URSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
55195 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv4i16),
55196 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55197 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55198 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55199 GIR_RootConstrainSelectedInstOperands,
55200 // GIR_Coverage, 1562,
55201 GIR_EraseRootFromParent_Done,
55202 // Label 3185: @153435
55203 GIM_Try, /*On fail goto*//*Label 3186*/ GIMT_Encode4(153480), // Rule ID 1563 //
55204 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55205 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
55206 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
55207 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
55208 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
55209 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55210 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55211 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55212 // (intrinsic_wo_chain:{ *:[v8i16] } 710:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (URSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
55213 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv8i16),
55214 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55215 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55216 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55217 GIR_RootConstrainSelectedInstOperands,
55218 // GIR_Coverage, 1563,
55219 GIR_EraseRootFromParent_Done,
55220 // Label 3186: @153480
55221 GIM_Try, /*On fail goto*//*Label 3187*/ GIMT_Encode4(153525), // Rule ID 1564 //
55222 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55223 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
55224 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
55225 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
55226 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
55227 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55228 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55229 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55230 // (intrinsic_wo_chain:{ *:[v2i32] } 710:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (URSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
55231 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv2i32),
55232 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55233 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55234 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55235 GIR_RootConstrainSelectedInstOperands,
55236 // GIR_Coverage, 1564,
55237 GIR_EraseRootFromParent_Done,
55238 // Label 3187: @153525
55239 GIM_Try, /*On fail goto*//*Label 3188*/ GIMT_Encode4(153570), // Rule ID 1565 //
55240 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55241 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
55242 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
55243 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
55244 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
55245 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55246 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55247 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55248 // (intrinsic_wo_chain:{ *:[v4i32] } 710:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (URSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
55249 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv4i32),
55250 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55251 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55252 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55253 GIR_RootConstrainSelectedInstOperands,
55254 // GIR_Coverage, 1565,
55255 GIR_EraseRootFromParent_Done,
55256 // Label 3188: @153570
55257 GIM_Try, /*On fail goto*//*Label 3189*/ GIMT_Encode4(153615), // Rule ID 1566 //
55258 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55259 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
55260 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
55261 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
55262 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
55263 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55264 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55265 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55266 // (intrinsic_wo_chain:{ *:[v2i64] } 710:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (URSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
55267 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv2i64),
55268 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55269 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55270 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55271 GIR_RootConstrainSelectedInstOperands,
55272 // GIR_Coverage, 1566,
55273 GIR_EraseRootFromParent_Done,
55274 // Label 3189: @153615
55275 GIM_Try, /*On fail goto*//*Label 3190*/ GIMT_Encode4(153660), // Rule ID 1567 //
55276 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55277 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
55278 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
55279 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
55280 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
55281 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55282 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55283 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55284 // (intrinsic_wo_chain:{ *:[v8i8] } 713:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (USHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
55285 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv8i8),
55286 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55287 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55288 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55289 GIR_RootConstrainSelectedInstOperands,
55290 // GIR_Coverage, 1567,
55291 GIR_EraseRootFromParent_Done,
55292 // Label 3190: @153660
55293 GIM_Try, /*On fail goto*//*Label 3191*/ GIMT_Encode4(153705), // Rule ID 1568 //
55294 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55295 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
55296 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
55297 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
55298 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
55299 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55300 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55301 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55302 // (intrinsic_wo_chain:{ *:[v16i8] } 713:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (USHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
55303 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv16i8),
55304 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55305 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55306 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55307 GIR_RootConstrainSelectedInstOperands,
55308 // GIR_Coverage, 1568,
55309 GIR_EraseRootFromParent_Done,
55310 // Label 3191: @153705
55311 GIM_Try, /*On fail goto*//*Label 3192*/ GIMT_Encode4(153750), // Rule ID 1569 //
55312 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55313 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
55314 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
55315 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
55316 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
55317 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55318 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55319 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55320 // (intrinsic_wo_chain:{ *:[v4i16] } 713:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (USHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
55321 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv4i16),
55322 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55323 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55324 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55325 GIR_RootConstrainSelectedInstOperands,
55326 // GIR_Coverage, 1569,
55327 GIR_EraseRootFromParent_Done,
55328 // Label 3192: @153750
55329 GIM_Try, /*On fail goto*//*Label 3193*/ GIMT_Encode4(153795), // Rule ID 1570 //
55330 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55331 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
55332 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
55333 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
55334 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
55335 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55336 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55337 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55338 // (intrinsic_wo_chain:{ *:[v8i16] } 713:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (USHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
55339 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv8i16),
55340 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55341 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55342 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55343 GIR_RootConstrainSelectedInstOperands,
55344 // GIR_Coverage, 1570,
55345 GIR_EraseRootFromParent_Done,
55346 // Label 3193: @153795
55347 GIM_Try, /*On fail goto*//*Label 3194*/ GIMT_Encode4(153840), // Rule ID 1571 //
55348 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55349 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
55350 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
55351 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
55352 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
55353 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55354 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55355 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55356 // (intrinsic_wo_chain:{ *:[v2i32] } 713:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (USHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
55357 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv2i32),
55358 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55359 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55360 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55361 GIR_RootConstrainSelectedInstOperands,
55362 // GIR_Coverage, 1571,
55363 GIR_EraseRootFromParent_Done,
55364 // Label 3194: @153840
55365 GIM_Try, /*On fail goto*//*Label 3195*/ GIMT_Encode4(153885), // Rule ID 1572 //
55366 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55367 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
55368 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
55369 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
55370 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
55371 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55372 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55373 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55374 // (intrinsic_wo_chain:{ *:[v4i32] } 713:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (USHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
55375 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv4i32),
55376 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55377 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55378 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55379 GIR_RootConstrainSelectedInstOperands,
55380 // GIR_Coverage, 1572,
55381 GIR_EraseRootFromParent_Done,
55382 // Label 3195: @153885
55383 GIM_Try, /*On fail goto*//*Label 3196*/ GIMT_Encode4(153930), // Rule ID 1573 //
55384 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55385 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
55386 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
55387 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
55388 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
55389 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55390 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55391 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
55392 // (intrinsic_wo_chain:{ *:[v2i64] } 713:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (USHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
55393 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv2i64),
55394 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55395 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55396 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55397 GIR_RootConstrainSelectedInstOperands,
55398 // GIR_Coverage, 1573,
55399 GIR_EraseRootFromParent_Done,
55400 // Label 3196: @153930
55401 GIM_Try, /*On fail goto*//*Label 3197*/ GIMT_Encode4(153975), // Rule ID 1601 //
55402 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55403 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sisd_fabd),
55404 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55405 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55406 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55407 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55408 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55409 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55410 // (intrinsic_wo_chain:{ *:[f64] } 740:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FABD64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
55411 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD64),
55412 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55413 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55414 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55415 GIR_RootConstrainSelectedInstOperands,
55416 // GIR_Coverage, 1601,
55417 GIR_EraseRootFromParent_Done,
55418 // Label 3197: @153975
55419 GIM_Try, /*On fail goto*//*Label 3198*/ GIMT_Encode4(154020), // Rule ID 1602 //
55420 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55421 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sisd_fabd),
55422 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
55423 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
55424 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
55425 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55426 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55427 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55428 // (intrinsic_wo_chain:{ *:[f32] } 740:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FABD32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
55429 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD32),
55430 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55431 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55432 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55433 GIR_RootConstrainSelectedInstOperands,
55434 // GIR_Coverage, 1602,
55435 GIR_EraseRootFromParent_Done,
55436 // Label 3198: @154020
55437 GIM_Try, /*On fail goto*//*Label 3199*/ GIMT_Encode4(154065), // Rule ID 1603 //
55438 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
55439 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sisd_fabd),
55440 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
55441 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
55442 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
55443 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
55444 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
55445 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
55446 // (intrinsic_wo_chain:{ *:[f16] } 740:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FABD16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
55447 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD16),
55448 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55449 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55450 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55451 GIR_RootConstrainSelectedInstOperands,
55452 // GIR_Coverage, 1603,
55453 GIR_EraseRootFromParent_Done,
55454 // Label 3199: @154065
55455 GIM_Try, /*On fail goto*//*Label 3200*/ GIMT_Encode4(154110), // Rule ID 1604 //
55456 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55457 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
55458 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55459 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55460 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55461 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55462 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55463 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55464 // (intrinsic_wo_chain:{ *:[i64] } 562:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FACGE64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
55465 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGE64),
55466 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55467 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55468 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55469 GIR_RootConstrainSelectedInstOperands,
55470 // GIR_Coverage, 1604,
55471 GIR_EraseRootFromParent_Done,
55472 // Label 3200: @154110
55473 GIM_Try, /*On fail goto*//*Label 3201*/ GIMT_Encode4(154155), // Rule ID 1605 //
55474 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55475 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
55476 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
55477 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
55478 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
55479 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55480 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55481 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55482 // (intrinsic_wo_chain:{ *:[i32] } 562:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FACGE32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
55483 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGE32),
55484 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55485 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55486 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55487 GIR_RootConstrainSelectedInstOperands,
55488 // GIR_Coverage, 1605,
55489 GIR_EraseRootFromParent_Done,
55490 // Label 3201: @154155
55491 GIM_Try, /*On fail goto*//*Label 3202*/ GIMT_Encode4(154200), // Rule ID 1606 //
55492 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55493 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
55494 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55495 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55496 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55497 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55498 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55499 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55500 // (intrinsic_wo_chain:{ *:[i64] } 563:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FACGT64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
55501 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGT64),
55502 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55503 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55504 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55505 GIR_RootConstrainSelectedInstOperands,
55506 // GIR_Coverage, 1606,
55507 GIR_EraseRootFromParent_Done,
55508 // Label 3202: @154200
55509 GIM_Try, /*On fail goto*//*Label 3203*/ GIMT_Encode4(154245), // Rule ID 1607 //
55510 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55511 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
55512 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
55513 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
55514 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
55515 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55516 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55517 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55518 // (intrinsic_wo_chain:{ *:[i32] } 563:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FACGT32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
55519 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGT32),
55520 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55521 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55522 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55523 GIR_RootConstrainSelectedInstOperands,
55524 // GIR_Coverage, 1607,
55525 GIR_EraseRootFromParent_Done,
55526 // Label 3203: @154245
55527 GIM_Try, /*On fail goto*//*Label 3204*/ GIMT_Encode4(154290), // Rule ID 1614 //
55528 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
55529 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
55530 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55531 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55532 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55533 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55534 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55535 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55536 // (intrinsic_wo_chain:{ *:[f64] } 593:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMULX64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
55537 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX64),
55538 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55539 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55540 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55541 GIR_RootConstrainSelectedInstOperands,
55542 // GIR_Coverage, 1614,
55543 GIR_EraseRootFromParent_Done,
55544 // Label 3204: @154290
55545 GIM_Try, /*On fail goto*//*Label 3205*/ GIMT_Encode4(154335), // Rule ID 1615 //
55546 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
55547 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
55548 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
55549 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
55550 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
55551 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55552 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55553 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55554 // (intrinsic_wo_chain:{ *:[f32] } 593:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMULX32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
55555 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX32),
55556 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55557 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55558 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55559 GIR_RootConstrainSelectedInstOperands,
55560 // GIR_Coverage, 1615,
55561 GIR_EraseRootFromParent_Done,
55562 // Label 3205: @154335
55563 GIM_Try, /*On fail goto*//*Label 3206*/ GIMT_Encode4(154380), // Rule ID 1616 //
55564 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
55565 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
55566 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
55567 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
55568 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
55569 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
55570 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
55571 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
55572 // (intrinsic_wo_chain:{ *:[f16] } 593:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMULX16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
55573 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX16),
55574 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55575 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55576 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55577 GIR_RootConstrainSelectedInstOperands,
55578 // GIR_Coverage, 1616,
55579 GIR_EraseRootFromParent_Done,
55580 // Label 3206: @154380
55581 GIM_Try, /*On fail goto*//*Label 3207*/ GIMT_Encode4(154425), // Rule ID 1617 //
55582 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
55583 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
55584 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55585 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55586 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55587 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55588 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55589 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55590 // (intrinsic_wo_chain:{ *:[f64] } 595:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FRECPS64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
55591 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPS64),
55592 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55593 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55594 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55595 GIR_RootConstrainSelectedInstOperands,
55596 // GIR_Coverage, 1617,
55597 GIR_EraseRootFromParent_Done,
55598 // Label 3207: @154425
55599 GIM_Try, /*On fail goto*//*Label 3208*/ GIMT_Encode4(154470), // Rule ID 1618 //
55600 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
55601 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
55602 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
55603 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
55604 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
55605 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55606 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55607 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55608 // (intrinsic_wo_chain:{ *:[f32] } 595:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FRECPS32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
55609 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPS32),
55610 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55611 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55612 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55613 GIR_RootConstrainSelectedInstOperands,
55614 // GIR_Coverage, 1618,
55615 GIR_EraseRootFromParent_Done,
55616 // Label 3208: @154470
55617 GIM_Try, /*On fail goto*//*Label 3209*/ GIMT_Encode4(154515), // Rule ID 1619 //
55618 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
55619 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
55620 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
55621 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
55622 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
55623 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
55624 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
55625 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
55626 // (intrinsic_wo_chain:{ *:[f16] } 595:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FRECPS16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
55627 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPS16),
55628 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55629 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55630 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55631 GIR_RootConstrainSelectedInstOperands,
55632 // GIR_Coverage, 1619,
55633 GIR_EraseRootFromParent_Done,
55634 // Label 3209: @154515
55635 GIM_Try, /*On fail goto*//*Label 3210*/ GIMT_Encode4(154560), // Rule ID 1620 //
55636 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
55637 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
55638 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55639 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55640 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55641 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55642 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55643 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55644 // (intrinsic_wo_chain:{ *:[f64] } 602:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FRSQRTS64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
55645 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTS64),
55646 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55647 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55648 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55649 GIR_RootConstrainSelectedInstOperands,
55650 // GIR_Coverage, 1620,
55651 GIR_EraseRootFromParent_Done,
55652 // Label 3210: @154560
55653 GIM_Try, /*On fail goto*//*Label 3211*/ GIMT_Encode4(154605), // Rule ID 1621 //
55654 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
55655 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
55656 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
55657 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
55658 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
55659 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55660 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55661 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55662 // (intrinsic_wo_chain:{ *:[f32] } 602:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FRSQRTS32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
55663 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTS32),
55664 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55665 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55666 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55667 GIR_RootConstrainSelectedInstOperands,
55668 // GIR_Coverage, 1621,
55669 GIR_EraseRootFromParent_Done,
55670 // Label 3211: @154605
55671 GIM_Try, /*On fail goto*//*Label 3212*/ GIMT_Encode4(154650), // Rule ID 1622 //
55672 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
55673 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
55674 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
55675 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
55676 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
55677 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
55678 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
55679 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
55680 // (intrinsic_wo_chain:{ *:[f16] } 602:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FRSQRTS16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
55681 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTS16),
55682 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55683 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55684 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55685 GIR_RootConstrainSelectedInstOperands,
55686 // GIR_Coverage, 1622,
55687 GIR_EraseRootFromParent_Done,
55688 // Label 3212: @154650
55689 GIM_Try, /*On fail goto*//*Label 3213*/ GIMT_Encode4(154695), // Rule ID 1623 //
55690 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55691 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
55692 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55693 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55694 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55695 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55696 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55697 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55698 // (intrinsic_wo_chain:{ *:[v1i64] } 641:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
55699 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADDv1i64),
55700 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55701 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55702 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55703 GIR_RootConstrainSelectedInstOperands,
55704 // GIR_Coverage, 1623,
55705 GIR_EraseRootFromParent_Done,
55706 // Label 3213: @154695
55707 GIM_Try, /*On fail goto*//*Label 3214*/ GIMT_Encode4(154740), // Rule ID 1624 //
55708 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55709 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
55710 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
55711 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
55712 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
55713 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55714 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55715 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55716 // (intrinsic_wo_chain:{ *:[i32] } 642:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQDMULHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
55717 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv1i32),
55718 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55719 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55720 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55721 GIR_RootConstrainSelectedInstOperands,
55722 // GIR_Coverage, 1624,
55723 GIR_EraseRootFromParent_Done,
55724 // Label 3214: @154740
55725 GIM_Try, /*On fail goto*//*Label 3215*/ GIMT_Encode4(154785), // Rule ID 1625 //
55726 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55727 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
55728 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
55729 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
55730 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
55731 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55732 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55733 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55734 // (intrinsic_wo_chain:{ *:[i32] } 650:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQRDMULHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
55735 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv1i32),
55736 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55737 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55738 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55739 GIR_RootConstrainSelectedInstOperands,
55740 // GIR_Coverage, 1625,
55741 GIR_EraseRootFromParent_Done,
55742 // Label 3215: @154785
55743 GIM_Try, /*On fail goto*//*Label 3216*/ GIMT_Encode4(154830), // Rule ID 1626 //
55744 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55745 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
55746 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55747 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55748 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55749 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55750 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55751 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55752 // (intrinsic_wo_chain:{ *:[v1i64] } 653:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
55753 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv1i64),
55754 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55755 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55756 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55757 GIR_RootConstrainSelectedInstOperands,
55758 // GIR_Coverage, 1626,
55759 GIR_EraseRootFromParent_Done,
55760 // Label 3216: @154830
55761 GIM_Try, /*On fail goto*//*Label 3217*/ GIMT_Encode4(154875), // Rule ID 1627 //
55762 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55763 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
55764 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55765 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55766 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55767 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55768 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55769 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55770 // (intrinsic_wo_chain:{ *:[v1i64] } 656:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
55771 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv1i64),
55772 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55773 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55774 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55775 GIR_RootConstrainSelectedInstOperands,
55776 // GIR_Coverage, 1627,
55777 GIR_EraseRootFromParent_Done,
55778 // Label 3217: @154875
55779 GIM_Try, /*On fail goto*//*Label 3218*/ GIMT_Encode4(154920), // Rule ID 1628 //
55780 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55781 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
55782 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55783 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55784 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55785 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55786 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55787 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55788 // (intrinsic_wo_chain:{ *:[v1i64] } 660:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SQSUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
55789 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv1i64),
55790 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55791 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55792 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55793 GIR_RootConstrainSelectedInstOperands,
55794 // GIR_Coverage, 1628,
55795 GIR_EraseRootFromParent_Done,
55796 // Label 3218: @154920
55797 GIM_Try, /*On fail goto*//*Label 3219*/ GIMT_Encode4(154965), // Rule ID 1629 //
55798 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55799 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
55800 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55801 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55802 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55803 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55804 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55805 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55806 // (intrinsic_wo_chain:{ *:[v1i64] } 664:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
55807 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv1i64),
55808 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55809 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55810 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55811 GIR_RootConstrainSelectedInstOperands,
55812 // GIR_Coverage, 1629,
55813 GIR_EraseRootFromParent_Done,
55814 // Label 3219: @154965
55815 GIM_Try, /*On fail goto*//*Label 3220*/ GIMT_Encode4(155010), // Rule ID 1630 //
55816 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55817 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
55818 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55819 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55820 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55821 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55822 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55823 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55824 // (intrinsic_wo_chain:{ *:[v1i64] } 665:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (SSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
55825 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv1i64),
55826 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55827 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55828 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55829 GIR_RootConstrainSelectedInstOperands,
55830 // GIR_Coverage, 1630,
55831 GIR_EraseRootFromParent_Done,
55832 // Label 3220: @155010
55833 GIM_Try, /*On fail goto*//*Label 3221*/ GIMT_Encode4(155055), // Rule ID 1632 //
55834 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55835 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqadd),
55836 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55837 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55838 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55839 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55840 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55841 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55842 // (intrinsic_wo_chain:{ *:[v1i64] } 701:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
55843 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADDv1i64),
55844 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55845 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55846 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55847 GIR_RootConstrainSelectedInstOperands,
55848 // GIR_Coverage, 1632,
55849 GIR_EraseRootFromParent_Done,
55850 // Label 3221: @155055
55851 GIM_Try, /*On fail goto*//*Label 3222*/ GIMT_Encode4(155100), // Rule ID 1633 //
55852 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55853 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
55854 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55855 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55856 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55857 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55858 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55859 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55860 // (intrinsic_wo_chain:{ *:[v1i64] } 702:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
55861 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv1i64),
55862 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55863 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55864 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55865 GIR_RootConstrainSelectedInstOperands,
55866 // GIR_Coverage, 1633,
55867 GIR_EraseRootFromParent_Done,
55868 // Label 3222: @155100
55869 GIM_Try, /*On fail goto*//*Label 3223*/ GIMT_Encode4(155145), // Rule ID 1634 //
55870 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55871 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
55872 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55873 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55874 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55875 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55876 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55877 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55878 // (intrinsic_wo_chain:{ *:[v1i64] } 704:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
55879 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv1i64),
55880 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55881 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55882 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55883 GIR_RootConstrainSelectedInstOperands,
55884 // GIR_Coverage, 1634,
55885 GIR_EraseRootFromParent_Done,
55886 // Label 3223: @155145
55887 GIM_Try, /*On fail goto*//*Label 3224*/ GIMT_Encode4(155190), // Rule ID 1635 //
55888 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55889 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqsub),
55890 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55891 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55892 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55893 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55894 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55895 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55896 // (intrinsic_wo_chain:{ *:[v1i64] } 706:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (UQSUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
55897 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv1i64),
55898 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55899 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55900 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55901 GIR_RootConstrainSelectedInstOperands,
55902 // GIR_Coverage, 1635,
55903 GIR_EraseRootFromParent_Done,
55904 // Label 3224: @155190
55905 GIM_Try, /*On fail goto*//*Label 3225*/ GIMT_Encode4(155235), // Rule ID 1636 //
55906 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55907 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
55908 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55909 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55910 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55911 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55912 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55913 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55914 // (intrinsic_wo_chain:{ *:[v1i64] } 710:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (URSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
55915 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv1i64),
55916 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55917 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55918 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55919 GIR_RootConstrainSelectedInstOperands,
55920 // GIR_Coverage, 1636,
55921 GIR_EraseRootFromParent_Done,
55922 // Label 3225: @155235
55923 GIM_Try, /*On fail goto*//*Label 3226*/ GIMT_Encode4(155280), // Rule ID 1637 //
55924 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55925 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
55926 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55927 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55928 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55929 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55930 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55931 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55932 // (intrinsic_wo_chain:{ *:[v1i64] } 713:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm) => (USHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
55933 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv1i64),
55934 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55935 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55936 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55937 GIR_RootConstrainSelectedInstOperands,
55938 // GIR_Coverage, 1637,
55939 GIR_EraseRootFromParent_Done,
55940 // Label 3226: @155280
55941 GIM_Try, /*On fail goto*//*Label 3227*/ GIMT_Encode4(155325), // Rule ID 1638 //
55942 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55943 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulls_scalar),
55944 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55945 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
55946 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
55947 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55948 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55949 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55950 // (intrinsic_wo_chain:{ *:[i64] } 646:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQDMULLi32:{ *:[i64] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
55951 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLi32),
55952 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
55953 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
55954 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
55955 GIR_RootConstrainSelectedInstOperands,
55956 // GIR_Coverage, 1638,
55957 GIR_EraseRootFromParent_Done,
55958 // Label 3227: @155325
55959 GIM_Try, /*On fail goto*//*Label 3228*/ GIMT_Encode4(155370), // Rule ID 1652 //
55960 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55961 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
55962 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55963 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
55964 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
55965 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55966 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55967 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
55968 // (intrinsic_wo_chain:{ *:[i64] } 677:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn) => (SUQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn)
55969 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv1i64),
55970 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
55971 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
55972 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
55973 GIR_RootConstrainSelectedInstOperands,
55974 // GIR_Coverage, 1652,
55975 GIR_EraseRootFromParent_Done,
55976 // Label 3228: @155370
55977 GIM_Try, /*On fail goto*//*Label 3229*/ GIMT_Encode4(155415), // Rule ID 1653 //
55978 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55979 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
55980 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
55981 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
55982 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
55983 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55984 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55985 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
55986 // (intrinsic_wo_chain:{ *:[i32] } 677:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn) => (SUQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn)
55987 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv1i32),
55988 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
55989 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
55990 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
55991 GIR_RootConstrainSelectedInstOperands,
55992 // GIR_Coverage, 1653,
55993 GIR_EraseRootFromParent_Done,
55994 // Label 3229: @155415
55995 GIM_Try, /*On fail goto*//*Label 3230*/ GIMT_Encode4(155460), // Rule ID 1658 //
55996 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
55997 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
55998 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
55999 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
56000 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
56001 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56002 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56003 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56004 // (intrinsic_wo_chain:{ *:[i64] } 716:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn) => (USQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn)
56005 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv1i64),
56006 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
56007 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
56008 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
56009 GIR_RootConstrainSelectedInstOperands,
56010 // GIR_Coverage, 1658,
56011 GIR_EraseRootFromParent_Done,
56012 // Label 3230: @155460
56013 GIM_Try, /*On fail goto*//*Label 3231*/ GIMT_Encode4(155505), // Rule ID 1659 //
56014 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56015 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
56016 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
56017 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
56018 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
56019 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
56020 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
56021 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
56022 // (intrinsic_wo_chain:{ *:[i32] } 716:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn) => (USQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn)
56023 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv1i32),
56024 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
56025 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
56026 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
56027 GIR_RootConstrainSelectedInstOperands,
56028 // GIR_Coverage, 1659,
56029 GIR_EraseRootFromParent_Done,
56030 // Label 3231: @155505
56031 GIM_Try, /*On fail goto*//*Label 3232*/ GIMT_Encode4(155550), // Rule ID 1660 //
56032 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56033 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addhn),
56034 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
56035 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
56036 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
56037 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56038 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56039 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56040 // (intrinsic_wo_chain:{ *:[v8i8] } 551:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
56041 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv8i16_v8i8),
56042 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56043 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56044 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56045 GIR_RootConstrainSelectedInstOperands,
56046 // GIR_Coverage, 1660,
56047 GIR_EraseRootFromParent_Done,
56048 // Label 3232: @155550
56049 GIM_Try, /*On fail goto*//*Label 3233*/ GIMT_Encode4(155595), // Rule ID 1661 //
56050 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56051 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addhn),
56052 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
56053 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
56054 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
56055 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56056 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56057 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56058 // (intrinsic_wo_chain:{ *:[v4i16] } 551:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
56059 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv4i32_v4i16),
56060 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56061 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56062 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56063 GIR_RootConstrainSelectedInstOperands,
56064 // GIR_Coverage, 1661,
56065 GIR_EraseRootFromParent_Done,
56066 // Label 3233: @155595
56067 GIM_Try, /*On fail goto*//*Label 3234*/ GIMT_Encode4(155640), // Rule ID 1662 //
56068 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56069 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addhn),
56070 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
56071 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
56072 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
56073 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56074 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56075 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56076 // (intrinsic_wo_chain:{ *:[v2i32] } 551:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
56077 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv2i64_v2i32),
56078 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56079 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56080 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56081 GIR_RootConstrainSelectedInstOperands,
56082 // GIR_Coverage, 1662,
56083 GIR_EraseRootFromParent_Done,
56084 // Label 3234: @155640
56085 GIM_Try, /*On fail goto*//*Label 3235*/ GIMT_Encode4(155685), // Rule ID 1663 //
56086 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56087 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_subhn),
56088 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
56089 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
56090 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
56091 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56092 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56093 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56094 // (intrinsic_wo_chain:{ *:[v8i8] } 676:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
56095 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv8i16_v8i8),
56096 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56097 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56098 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56099 GIR_RootConstrainSelectedInstOperands,
56100 // GIR_Coverage, 1663,
56101 GIR_EraseRootFromParent_Done,
56102 // Label 3235: @155685
56103 GIM_Try, /*On fail goto*//*Label 3236*/ GIMT_Encode4(155730), // Rule ID 1664 //
56104 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56105 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_subhn),
56106 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
56107 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
56108 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
56109 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56110 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56111 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56112 // (intrinsic_wo_chain:{ *:[v4i16] } 676:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
56113 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv4i32_v4i16),
56114 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56115 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56116 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56117 GIR_RootConstrainSelectedInstOperands,
56118 // GIR_Coverage, 1664,
56119 GIR_EraseRootFromParent_Done,
56120 // Label 3236: @155730
56121 GIM_Try, /*On fail goto*//*Label 3237*/ GIMT_Encode4(155775), // Rule ID 1665 //
56122 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56123 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_subhn),
56124 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
56125 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
56126 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
56127 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56128 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56129 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56130 // (intrinsic_wo_chain:{ *:[v2i32] } 676:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (SUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
56131 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv2i64_v2i32),
56132 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56133 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56134 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56135 GIR_RootConstrainSelectedInstOperands,
56136 // GIR_Coverage, 1665,
56137 GIR_EraseRootFromParent_Done,
56138 // Label 3237: @155775
56139 GIM_Try, /*On fail goto*//*Label 3238*/ GIMT_Encode4(155820), // Rule ID 1666 //
56140 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56141 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_raddhn),
56142 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
56143 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
56144 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
56145 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56146 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56147 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56148 // (intrinsic_wo_chain:{ *:[v8i8] } 618:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (RADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
56149 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv8i16_v8i8),
56150 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56151 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56152 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56153 GIR_RootConstrainSelectedInstOperands,
56154 // GIR_Coverage, 1666,
56155 GIR_EraseRootFromParent_Done,
56156 // Label 3238: @155820
56157 GIM_Try, /*On fail goto*//*Label 3239*/ GIMT_Encode4(155865), // Rule ID 1667 //
56158 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56159 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_raddhn),
56160 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
56161 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
56162 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
56163 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56164 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56165 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56166 // (intrinsic_wo_chain:{ *:[v4i16] } 618:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (RADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
56167 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv4i32_v4i16),
56168 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56169 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56170 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56171 GIR_RootConstrainSelectedInstOperands,
56172 // GIR_Coverage, 1667,
56173 GIR_EraseRootFromParent_Done,
56174 // Label 3239: @155865
56175 GIM_Try, /*On fail goto*//*Label 3240*/ GIMT_Encode4(155910), // Rule ID 1668 //
56176 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56177 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_raddhn),
56178 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
56179 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
56180 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
56181 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56182 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56183 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56184 // (intrinsic_wo_chain:{ *:[v2i32] } 618:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (RADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
56185 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv2i64_v2i32),
56186 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56187 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56188 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56189 GIR_RootConstrainSelectedInstOperands,
56190 // GIR_Coverage, 1668,
56191 GIR_EraseRootFromParent_Done,
56192 // Label 3240: @155910
56193 GIM_Try, /*On fail goto*//*Label 3241*/ GIMT_Encode4(155955), // Rule ID 1669 //
56194 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56195 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rsubhn),
56196 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
56197 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
56198 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
56199 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56200 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56201 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56202 // (intrinsic_wo_chain:{ *:[v8i8] } 620:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (RSUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
56203 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNv8i16_v8i8),
56204 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56205 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56206 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56207 GIR_RootConstrainSelectedInstOperands,
56208 // GIR_Coverage, 1669,
56209 GIR_EraseRootFromParent_Done,
56210 // Label 3241: @155955
56211 GIM_Try, /*On fail goto*//*Label 3242*/ GIMT_Encode4(156000), // Rule ID 1670 //
56212 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56213 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rsubhn),
56214 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
56215 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
56216 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
56217 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56218 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56219 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56220 // (intrinsic_wo_chain:{ *:[v4i16] } 620:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (RSUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
56221 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNv4i32_v4i16),
56222 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56223 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56224 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56225 GIR_RootConstrainSelectedInstOperands,
56226 // GIR_Coverage, 1670,
56227 GIR_EraseRootFromParent_Done,
56228 // Label 3242: @156000
56229 GIM_Try, /*On fail goto*//*Label 3243*/ GIMT_Encode4(156045), // Rule ID 1671 //
56230 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56231 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rsubhn),
56232 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
56233 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
56234 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
56235 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56236 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56237 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56238 // (intrinsic_wo_chain:{ *:[v2i32] } 620:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (RSUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
56239 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNv2i64_v2i32),
56240 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56241 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56242 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56243 GIR_RootConstrainSelectedInstOperands,
56244 // GIR_Coverage, 1671,
56245 GIR_EraseRootFromParent_Done,
56246 // Label 3243: @156045
56247 GIM_Try, /*On fail goto*//*Label 3244*/ GIMT_Encode4(156090), // Rule ID 1737 //
56248 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56249 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
56250 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
56251 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
56252 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
56253 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56254 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56255 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56256 // (intrinsic_wo_chain:{ *:[v4i32] } 645:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQDMULLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
56257 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv4i16_v4i32),
56258 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56259 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56260 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56261 GIR_RootConstrainSelectedInstOperands,
56262 // GIR_Coverage, 1737,
56263 GIR_EraseRootFromParent_Done,
56264 // Label 3244: @156090
56265 GIM_Try, /*On fail goto*//*Label 3245*/ GIMT_Encode4(156135), // Rule ID 1739 //
56266 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56267 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
56268 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
56269 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
56270 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
56271 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56272 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56273 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56274 // (intrinsic_wo_chain:{ *:[v2i64] } 645:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQDMULLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
56275 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv2i32_v2i64),
56276 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56277 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56278 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56279 GIR_RootConstrainSelectedInstOperands,
56280 // GIR_Coverage, 1739,
56281 GIR_EraseRootFromParent_Done,
56282 // Label 3245: @156135
56283 GIM_Try, /*On fail goto*//*Label 3246*/ GIMT_Encode4(156180), // Rule ID 2288 //
56284 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES),
56285 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aese),
56286 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
56287 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
56288 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
56289 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56290 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56291 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56292 // (intrinsic_wo_chain:{ *:[v16i8] } 494:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (AESErr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)
56293 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESErr),
56294 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
56295 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
56296 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
56297 GIR_RootConstrainSelectedInstOperands,
56298 // GIR_Coverage, 2288,
56299 GIR_EraseRootFromParent_Done,
56300 // Label 3246: @156180
56301 GIM_Try, /*On fail goto*//*Label 3247*/ GIMT_Encode4(156225), // Rule ID 2289 //
56302 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES),
56303 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aesd),
56304 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
56305 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
56306 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
56307 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56308 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56309 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56310 // (intrinsic_wo_chain:{ *:[v16i8] } 493:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn) => (AESDrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)
56311 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESDrr),
56312 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
56313 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
56314 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
56315 GIR_RootConstrainSelectedInstOperands,
56316 // GIR_Coverage, 2289,
56317 GIR_EraseRootFromParent_Done,
56318 // Label 3247: @156225
56319 GIM_Try, /*On fail goto*//*Label 3248*/ GIMT_Encode4(156270), // Rule ID 2300 //
56320 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
56321 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha1su1),
56322 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
56323 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
56324 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
56325 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56326 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56327 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56328 // (intrinsic_wo_chain:{ *:[v4i32] } 507:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (SHA1SU1rr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)
56329 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA1SU1rr),
56330 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
56331 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
56332 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
56333 GIR_RootConstrainSelectedInstOperands,
56334 // GIR_Coverage, 2300,
56335 GIR_EraseRootFromParent_Done,
56336 // Label 3248: @156270
56337 GIM_Try, /*On fail goto*//*Label 3249*/ GIMT_Encode4(156315), // Rule ID 2301 //
56338 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
56339 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha256su0),
56340 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
56341 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
56342 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
56343 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56344 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56345 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56346 // (intrinsic_wo_chain:{ *:[v4i32] } 510:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn) => (SHA256SU0rr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)
56347 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA256SU0rr),
56348 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
56349 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
56350 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
56351 GIR_RootConstrainSelectedInstOperands,
56352 // GIR_Coverage, 2301,
56353 GIR_EraseRootFromParent_Done,
56354 // Label 3249: @156315
56355 GIM_Try, /*On fail goto*//*Label 3250*/ GIMT_Encode4(156360), // Rule ID 2430 //
56356 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56357 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
56358 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
56359 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
56360 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
56361 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56362 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56363 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56364 // (intrinsic_wo_chain:{ *:[i64] } 641:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
56365 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADDv1i64),
56366 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56367 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56368 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56369 GIR_RootConstrainSelectedInstOperands,
56370 // GIR_Coverage, 2430,
56371 GIR_EraseRootFromParent_Done,
56372 // Label 3250: @156360
56373 GIM_Try, /*On fail goto*//*Label 3251*/ GIMT_Encode4(156405), // Rule ID 2431 //
56374 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56375 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
56376 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
56377 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
56378 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
56379 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
56380 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
56381 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
56382 // (intrinsic_wo_chain:{ *:[i32] } 641:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
56383 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADDv1i32),
56384 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56385 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56386 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56387 GIR_RootConstrainSelectedInstOperands,
56388 // GIR_Coverage, 2431,
56389 GIR_EraseRootFromParent_Done,
56390 // Label 3251: @156405
56391 GIM_Try, /*On fail goto*//*Label 3252*/ GIMT_Encode4(156450), // Rule ID 2432 //
56392 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56393 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sisd_fabd),
56394 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
56395 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
56396 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
56397 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56398 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56399 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56400 // (intrinsic_wo_chain:{ *:[v1f64] } 740:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FABD64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
56401 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD64),
56402 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56403 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56404 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56405 GIR_RootConstrainSelectedInstOperands,
56406 // GIR_Coverage, 2432,
56407 GIR_EraseRootFromParent_Done,
56408 // Label 3252: @156450
56409 GIM_Try, /*On fail goto*//*Label 3253*/ GIMT_Encode4(156495), // Rule ID 2433 //
56410 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56411 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
56412 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
56413 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
56414 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
56415 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56416 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56417 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56418 // (intrinsic_wo_chain:{ *:[v1i64] } 562:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FACGE64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
56419 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGE64),
56420 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56421 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56422 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56423 GIR_RootConstrainSelectedInstOperands,
56424 // GIR_Coverage, 2433,
56425 GIR_EraseRootFromParent_Done,
56426 // Label 3253: @156495
56427 GIM_Try, /*On fail goto*//*Label 3254*/ GIMT_Encode4(156540), // Rule ID 2438 //
56428 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56429 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
56430 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
56431 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
56432 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
56433 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56434 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56435 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56436 // (intrinsic_wo_chain:{ *:[v1i64] } 677:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn) => (SUQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn)
56437 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv1i64),
56438 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
56439 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
56440 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
56441 GIR_RootConstrainSelectedInstOperands,
56442 // GIR_Coverage, 2438,
56443 GIR_EraseRootFromParent_Done,
56444 // Label 3254: @156540
56445 GIM_Try, /*On fail goto*//*Label 3255*/ GIMT_Encode4(156585), // Rule ID 2533 //
56446 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
56447 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n32),
56448 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
56449 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
56450 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
56451 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
56452 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
56453 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
56454 // (intrinsic_wo_chain:{ *:[i32] } 1806:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv16i1] }:$Pg) => (UQINCP_WP_B:{ *:[i32] } PPRAny:{ *:[nxv16i1] }:$Pg, ?:{ *:[i32] }:$Rn)
56455 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_WP_B),
56456 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
56457 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
56458 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56459 GIR_RootConstrainSelectedInstOperands,
56460 // GIR_Coverage, 2533,
56461 GIR_EraseRootFromParent_Done,
56462 // Label 3255: @156585
56463 GIM_Try, /*On fail goto*//*Label 3256*/ GIMT_Encode4(156630), // Rule ID 2534 //
56464 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
56465 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n32),
56466 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
56467 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
56468 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
56469 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
56470 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
56471 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
56472 // (intrinsic_wo_chain:{ *:[i32] } 1806:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv8i1] }:$Pg) => (UQINCP_WP_H:{ *:[i32] } PPRAny:{ *:[nxv8i1] }:$Pg, ?:{ *:[i32] }:$Rn)
56473 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_WP_H),
56474 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
56475 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
56476 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56477 GIR_RootConstrainSelectedInstOperands,
56478 // GIR_Coverage, 2534,
56479 GIR_EraseRootFromParent_Done,
56480 // Label 3256: @156630
56481 GIM_Try, /*On fail goto*//*Label 3257*/ GIMT_Encode4(156675), // Rule ID 2535 //
56482 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
56483 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n32),
56484 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
56485 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
56486 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
56487 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
56488 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
56489 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
56490 // (intrinsic_wo_chain:{ *:[i32] } 1806:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv4i1] }:$Pg) => (UQINCP_WP_S:{ *:[i32] } PPRAny:{ *:[nxv4i1] }:$Pg, ?:{ *:[i32] }:$Rn)
56491 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_WP_S),
56492 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
56493 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
56494 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56495 GIR_RootConstrainSelectedInstOperands,
56496 // GIR_Coverage, 2535,
56497 GIR_EraseRootFromParent_Done,
56498 // Label 3257: @156675
56499 GIM_Try, /*On fail goto*//*Label 3258*/ GIMT_Encode4(156720), // Rule ID 2536 //
56500 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
56501 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n32),
56502 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
56503 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
56504 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
56505 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
56506 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
56507 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
56508 // (intrinsic_wo_chain:{ *:[i32] } 1806:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv2i1] }:$Pg) => (UQINCP_WP_D:{ *:[i32] } PPRAny:{ *:[nxv2i1] }:$Pg, ?:{ *:[i32] }:$Rn)
56509 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_WP_D),
56510 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
56511 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
56512 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56513 GIR_RootConstrainSelectedInstOperands,
56514 // GIR_Coverage, 2536,
56515 GIR_EraseRootFromParent_Done,
56516 // Label 3258: @156720
56517 GIM_Try, /*On fail goto*//*Label 3259*/ GIMT_Encode4(156765), // Rule ID 2537 //
56518 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
56519 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp_n64),
56520 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
56521 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
56522 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
56523 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
56524 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
56525 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
56526 // (intrinsic_wo_chain:{ *:[i64] } 1596:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv16i1] }:$Pg) => (SQINCP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$Pg, ?:{ *:[i64] }:$Rn)
56527 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_XP_B),
56528 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
56529 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
56530 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56531 GIR_RootConstrainSelectedInstOperands,
56532 // GIR_Coverage, 2537,
56533 GIR_EraseRootFromParent_Done,
56534 // Label 3259: @156765
56535 GIM_Try, /*On fail goto*//*Label 3260*/ GIMT_Encode4(156810), // Rule ID 2538 //
56536 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
56537 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp_n64),
56538 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
56539 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
56540 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
56541 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
56542 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
56543 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
56544 // (intrinsic_wo_chain:{ *:[i64] } 1596:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv8i1] }:$Pg) => (SQINCP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$Pg, ?:{ *:[i64] }:$Rn)
56545 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_XP_H),
56546 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
56547 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
56548 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56549 GIR_RootConstrainSelectedInstOperands,
56550 // GIR_Coverage, 2538,
56551 GIR_EraseRootFromParent_Done,
56552 // Label 3260: @156810
56553 GIM_Try, /*On fail goto*//*Label 3261*/ GIMT_Encode4(156855), // Rule ID 2539 //
56554 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
56555 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp_n64),
56556 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
56557 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
56558 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
56559 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
56560 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
56561 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
56562 // (intrinsic_wo_chain:{ *:[i64] } 1596:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv4i1] }:$Pg) => (SQINCP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$Pg, ?:{ *:[i64] }:$Rn)
56563 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_XP_S),
56564 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
56565 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
56566 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56567 GIR_RootConstrainSelectedInstOperands,
56568 // GIR_Coverage, 2539,
56569 GIR_EraseRootFromParent_Done,
56570 // Label 3261: @156855
56571 GIM_Try, /*On fail goto*//*Label 3262*/ GIMT_Encode4(156900), // Rule ID 2540 //
56572 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
56573 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp_n64),
56574 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
56575 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
56576 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
56577 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
56578 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
56579 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
56580 // (intrinsic_wo_chain:{ *:[i64] } 1596:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv2i1] }:$Pg) => (SQINCP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$Pg, ?:{ *:[i64] }:$Rn)
56581 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_XP_D),
56582 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
56583 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
56584 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56585 GIR_RootConstrainSelectedInstOperands,
56586 // GIR_Coverage, 2540,
56587 GIR_EraseRootFromParent_Done,
56588 // Label 3262: @156900
56589 GIM_Try, /*On fail goto*//*Label 3263*/ GIMT_Encode4(156945), // Rule ID 3684 //
56590 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
56591 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha512su0),
56592 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
56593 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
56594 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
56595 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56596 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56597 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56598 // (intrinsic_wo_chain:{ *:[v2i64] } 514:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) => (SHA512SU0:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
56599 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA512SU0),
56600 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
56601 GIR_RootToRootCopy, /*OpIdx*/2, // Vn
56602 GIR_RootToRootCopy, /*OpIdx*/3, // Vm
56603 GIR_RootConstrainSelectedInstOperands,
56604 // GIR_Coverage, 3684,
56605 GIR_EraseRootFromParent_Done,
56606 // Label 3263: @156945
56607 GIM_Try, /*On fail goto*//*Label 3264*/ GIMT_Encode4(156990), // Rule ID 3712 //
56608 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
56609 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_rax1),
56610 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
56611 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
56612 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
56613 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56614 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56615 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56616 // (intrinsic_wo_chain:{ *:[v2i64] } 501:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) => (RAX1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
56617 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RAX1),
56618 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
56619 GIR_RootToRootCopy, /*OpIdx*/2, // Vn
56620 GIR_RootToRootCopy, /*OpIdx*/3, // Vm
56621 GIR_RootConstrainSelectedInstOperands,
56622 // GIR_Coverage, 3712,
56623 GIR_EraseRootFromParent_Done,
56624 // Label 3264: @156990
56625 GIM_Try, /*On fail goto*//*Label 3265*/ GIMT_Encode4(157035), // Rule ID 3722 //
56626 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
56627 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm4ekey),
56628 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
56629 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
56630 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
56631 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56632 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56633 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56634 // (intrinsic_wo_chain:{ *:[v4i32] } 524:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) => (SM4ENCKEY:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
56635 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM4ENCKEY),
56636 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
56637 GIR_RootToRootCopy, /*OpIdx*/2, // Vn
56638 GIR_RootToRootCopy, /*OpIdx*/3, // Vm
56639 GIR_RootConstrainSelectedInstOperands,
56640 // GIR_Coverage, 3722,
56641 GIR_EraseRootFromParent_Done,
56642 // Label 3265: @157035
56643 GIM_Try, /*On fail goto*//*Label 3266*/ GIMT_Encode4(157080), // Rule ID 3723 //
56644 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
56645 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm4e),
56646 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
56647 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
56648 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
56649 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56650 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56651 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56652 // (intrinsic_wo_chain:{ *:[v4i32] } 523:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) => (SM4E:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
56653 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM4E),
56654 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
56655 GIR_RootToRootCopy, /*OpIdx*/2, // Vn
56656 GIR_RootToRootCopy, /*OpIdx*/3, // Vm
56657 GIR_RootConstrainSelectedInstOperands,
56658 // GIR_Coverage, 3723,
56659 GIR_EraseRootFromParent_Done,
56660 // Label 3266: @157080
56661 GIM_Try, /*On fail goto*//*Label 3267*/ GIMT_Encode4(157128), // Rule ID 3724 //
56662 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
56663 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot90),
56664 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
56665 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
56666 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
56667 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56668 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56669 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56670 // (intrinsic_wo_chain:{ *:[v4f16] } 718:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FCADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, 0:{ *:[i32] })
56671 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv4f16),
56672 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56673 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56674 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56675 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
56676 GIR_RootConstrainSelectedInstOperands,
56677 // GIR_Coverage, 3724,
56678 GIR_EraseRootFromParent_Done,
56679 // Label 3267: @157128
56680 GIM_Try, /*On fail goto*//*Label 3268*/ GIMT_Encode4(157176), // Rule ID 3725 //
56681 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
56682 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot270),
56683 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
56684 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
56685 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
56686 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56687 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56688 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56689 // (intrinsic_wo_chain:{ *:[v4f16] } 717:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FCADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, 1:{ *:[i32] })
56690 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv4f16),
56691 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56692 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56693 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56694 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
56695 GIR_RootConstrainSelectedInstOperands,
56696 // GIR_Coverage, 3725,
56697 GIR_EraseRootFromParent_Done,
56698 // Label 3268: @157176
56699 GIM_Try, /*On fail goto*//*Label 3269*/ GIMT_Encode4(157224), // Rule ID 3726 //
56700 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
56701 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot90),
56702 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
56703 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
56704 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
56705 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56706 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56707 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56708 // (intrinsic_wo_chain:{ *:[v8f16] } 718:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, 0:{ *:[i32] })
56709 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv8f16),
56710 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56711 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56712 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56713 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
56714 GIR_RootConstrainSelectedInstOperands,
56715 // GIR_Coverage, 3726,
56716 GIR_EraseRootFromParent_Done,
56717 // Label 3269: @157224
56718 GIM_Try, /*On fail goto*//*Label 3270*/ GIMT_Encode4(157272), // Rule ID 3727 //
56719 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
56720 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot270),
56721 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
56722 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
56723 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
56724 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56725 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56726 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56727 // (intrinsic_wo_chain:{ *:[v8f16] } 717:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, 1:{ *:[i32] })
56728 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv8f16),
56729 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56730 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56731 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56732 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
56733 GIR_RootConstrainSelectedInstOperands,
56734 // GIR_Coverage, 3727,
56735 GIR_EraseRootFromParent_Done,
56736 // Label 3270: @157272
56737 GIM_Try, /*On fail goto*//*Label 3271*/ GIMT_Encode4(157320), // Rule ID 3728 //
56738 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
56739 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot90),
56740 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
56741 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
56742 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
56743 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56744 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56745 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56746 // (intrinsic_wo_chain:{ *:[v2f32] } 718:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FCADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, 0:{ *:[i32] })
56747 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv2f32),
56748 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56749 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56750 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56751 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
56752 GIR_RootConstrainSelectedInstOperands,
56753 // GIR_Coverage, 3728,
56754 GIR_EraseRootFromParent_Done,
56755 // Label 3271: @157320
56756 GIM_Try, /*On fail goto*//*Label 3272*/ GIMT_Encode4(157368), // Rule ID 3729 //
56757 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
56758 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot270),
56759 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
56760 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
56761 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
56762 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56763 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56764 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56765 // (intrinsic_wo_chain:{ *:[v2f32] } 717:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FCADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, 1:{ *:[i32] })
56766 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv2f32),
56767 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56768 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56769 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56770 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
56771 GIR_RootConstrainSelectedInstOperands,
56772 // GIR_Coverage, 3729,
56773 GIR_EraseRootFromParent_Done,
56774 // Label 3272: @157368
56775 GIM_Try, /*On fail goto*//*Label 3273*/ GIMT_Encode4(157416), // Rule ID 3730 //
56776 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
56777 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot90),
56778 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
56779 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
56780 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
56781 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56782 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56783 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56784 // (intrinsic_wo_chain:{ *:[v4f32] } 718:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FCADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, 0:{ *:[i32] })
56785 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv4f32),
56786 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56787 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56788 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56789 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
56790 GIR_RootConstrainSelectedInstOperands,
56791 // GIR_Coverage, 3730,
56792 GIR_EraseRootFromParent_Done,
56793 // Label 3273: @157416
56794 GIM_Try, /*On fail goto*//*Label 3274*/ GIMT_Encode4(157464), // Rule ID 3731 //
56795 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
56796 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot270),
56797 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
56798 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
56799 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
56800 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56801 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56802 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56803 // (intrinsic_wo_chain:{ *:[v4f32] } 717:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FCADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, 1:{ *:[i32] })
56804 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv4f32),
56805 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56806 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56807 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56808 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
56809 GIR_RootConstrainSelectedInstOperands,
56810 // GIR_Coverage, 3731,
56811 GIR_EraseRootFromParent_Done,
56812 // Label 3274: @157464
56813 GIM_Try, /*On fail goto*//*Label 3275*/ GIMT_Encode4(157512), // Rule ID 3732 //
56814 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
56815 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot90),
56816 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
56817 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
56818 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
56819 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56820 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56821 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56822 // (intrinsic_wo_chain:{ *:[v2f64] } 718:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FCADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, 0:{ *:[i32] })
56823 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv2f64),
56824 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56825 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56826 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56827 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
56828 GIR_RootConstrainSelectedInstOperands,
56829 // GIR_Coverage, 3732,
56830 GIR_EraseRootFromParent_Done,
56831 // Label 3275: @157512
56832 GIM_Try, /*On fail goto*//*Label 3276*/ GIMT_Encode4(157560), // Rule ID 3733 //
56833 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
56834 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot270),
56835 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
56836 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
56837 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
56838 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56839 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56840 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
56841 // (intrinsic_wo_chain:{ *:[v2f64] } 717:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FCADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, 1:{ *:[i32] })
56842 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv2f64),
56843 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56844 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56845 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56846 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
56847 GIR_RootConstrainSelectedInstOperands,
56848 // GIR_Coverage, 3733,
56849 GIR_EraseRootFromParent_Done,
56850 // Label 3276: @157560
56851 GIM_Try, /*On fail goto*//*Label 3277*/ GIMT_Encode4(157602), // Rule ID 3798 //
56852 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_udiv),
56853 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
56854 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
56855 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
56856 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
56857 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
56858 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
56859 // (intrinsic_wo_chain:{ *:[i32] } 1950:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (UDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
56860 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDIVWr),
56861 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56862 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56863 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56864 GIR_RootConstrainSelectedInstOperands,
56865 // GIR_Coverage, 3798,
56866 GIR_EraseRootFromParent_Done,
56867 // Label 3277: @157602
56868 GIM_Try, /*On fail goto*//*Label 3278*/ GIMT_Encode4(157644), // Rule ID 3799 //
56869 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_udiv),
56870 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
56871 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
56872 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
56873 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
56874 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
56875 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
56876 // (intrinsic_wo_chain:{ *:[i64] } 1950:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (UDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
56877 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDIVXr),
56878 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56879 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56880 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56881 GIR_RootConstrainSelectedInstOperands,
56882 // GIR_Coverage, 3799,
56883 GIR_EraseRootFromParent_Done,
56884 // Label 3278: @157644
56885 GIM_Try, /*On fail goto*//*Label 3279*/ GIMT_Encode4(157686), // Rule ID 3800 //
56886 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sdiv),
56887 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
56888 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
56889 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
56890 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
56891 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
56892 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
56893 // (intrinsic_wo_chain:{ *:[i32] } 735:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (SDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
56894 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDIVWr),
56895 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56896 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56897 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56898 GIR_RootConstrainSelectedInstOperands,
56899 // GIR_Coverage, 3800,
56900 GIR_EraseRootFromParent_Done,
56901 // Label 3279: @157686
56902 GIM_Try, /*On fail goto*//*Label 3280*/ GIMT_Encode4(157728), // Rule ID 3801 //
56903 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sdiv),
56904 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
56905 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
56906 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
56907 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
56908 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
56909 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
56910 // (intrinsic_wo_chain:{ *:[i64] } 735:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
56911 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDIVXr),
56912 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56913 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56914 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56915 GIR_RootConstrainSelectedInstOperands,
56916 // GIR_Coverage, 3801,
56917 GIR_EraseRootFromParent_Done,
56918 // Label 3280: @157728
56919 GIM_Try, /*On fail goto*//*Label 3281*/ GIMT_Encode4(157770), // Rule ID 4855 //
56920 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fabd),
56921 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
56922 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
56923 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
56924 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56925 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56926 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56927 // (intrinsic_wo_chain:{ *:[v1f64] } 561:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FABD64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
56928 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD64),
56929 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56930 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56931 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56932 GIR_RootConstrainSelectedInstOperands,
56933 // GIR_Coverage, 4855,
56934 GIR_EraseRootFromParent_Done,
56935 // Label 3281: @157770
56936 GIM_Try, /*On fail goto*//*Label 3282*/ GIMT_Encode4(157815), // Rule ID 4859 //
56937 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56938 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
56939 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
56940 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
56941 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
56942 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56943 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56944 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56945 // (intrinsic_wo_chain:{ *:[v1i64] } 563:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FACGT64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
56946 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGT64),
56947 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56948 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56949 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56950 GIR_RootConstrainSelectedInstOperands,
56951 // GIR_Coverage, 4859,
56952 GIR_EraseRootFromParent_Done,
56953 // Label 3282: @157815
56954 GIM_Try, /*On fail goto*//*Label 3283*/ GIMT_Encode4(157860), // Rule ID 4863 //
56955 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56956 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
56957 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
56958 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
56959 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
56960 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56961 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56962 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56963 // (intrinsic_wo_chain:{ *:[v1f64] } 593:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FMULX64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
56964 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX64),
56965 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56966 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56967 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56968 GIR_RootConstrainSelectedInstOperands,
56969 // GIR_Coverage, 4863,
56970 GIR_EraseRootFromParent_Done,
56971 // Label 3283: @157860
56972 GIM_Try, /*On fail goto*//*Label 3284*/ GIMT_Encode4(157905), // Rule ID 4864 //
56973 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56974 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
56975 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
56976 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
56977 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
56978 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56979 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56980 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56981 // (intrinsic_wo_chain:{ *:[v1f64] } 595:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FRECPS64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
56982 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPS64),
56983 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
56984 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
56985 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
56986 GIR_RootConstrainSelectedInstOperands,
56987 // GIR_Coverage, 4864,
56988 GIR_EraseRootFromParent_Done,
56989 // Label 3284: @157905
56990 GIM_Try, /*On fail goto*//*Label 3285*/ GIMT_Encode4(157950), // Rule ID 4865 //
56991 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
56992 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
56993 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
56994 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
56995 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
56996 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56997 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56998 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
56999 // (intrinsic_wo_chain:{ *:[v1f64] } 602:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FRSQRTS64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
57000 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTS64),
57001 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57002 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57003 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57004 GIR_RootConstrainSelectedInstOperands,
57005 // GIR_Coverage, 4865,
57006 GIR_EraseRootFromParent_Done,
57007 // Label 3285: @157950
57008 GIM_Try, /*On fail goto*//*Label 3286*/ GIMT_Encode4(157995), // Rule ID 4866 //
57009 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
57010 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
57011 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57012 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57013 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
57014 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57015 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57016 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57017 // (intrinsic_wo_chain:{ *:[i64] } 653:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
57018 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv1i64),
57019 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57020 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57021 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57022 GIR_RootConstrainSelectedInstOperands,
57023 // GIR_Coverage, 4866,
57024 GIR_EraseRootFromParent_Done,
57025 // Label 3286: @157995
57026 GIM_Try, /*On fail goto*//*Label 3287*/ GIMT_Encode4(158040), // Rule ID 4867 //
57027 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
57028 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
57029 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
57030 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
57031 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
57032 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57033 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57034 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57035 // (intrinsic_wo_chain:{ *:[i32] } 653:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQRSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
57036 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv1i32),
57037 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57038 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57039 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57040 GIR_RootConstrainSelectedInstOperands,
57041 // GIR_Coverage, 4867,
57042 GIR_EraseRootFromParent_Done,
57043 // Label 3287: @158040
57044 GIM_Try, /*On fail goto*//*Label 3288*/ GIMT_Encode4(158085), // Rule ID 4868 //
57045 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
57046 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
57047 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57048 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57049 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
57050 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57051 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57052 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57053 // (intrinsic_wo_chain:{ *:[i64] } 656:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
57054 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv1i64),
57055 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57056 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57057 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57058 GIR_RootConstrainSelectedInstOperands,
57059 // GIR_Coverage, 4868,
57060 GIR_EraseRootFromParent_Done,
57061 // Label 3288: @158085
57062 GIM_Try, /*On fail goto*//*Label 3289*/ GIMT_Encode4(158130), // Rule ID 4869 //
57063 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
57064 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
57065 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
57066 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
57067 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
57068 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57069 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57070 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57071 // (intrinsic_wo_chain:{ *:[i32] } 656:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
57072 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv1i32),
57073 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57074 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57075 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57076 GIR_RootConstrainSelectedInstOperands,
57077 // GIR_Coverage, 4869,
57078 GIR_EraseRootFromParent_Done,
57079 // Label 3289: @158130
57080 GIM_Try, /*On fail goto*//*Label 3290*/ GIMT_Encode4(158175), // Rule ID 4870 //
57081 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
57082 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
57083 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57084 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57085 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
57086 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57087 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57088 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57089 // (intrinsic_wo_chain:{ *:[i64] } 660:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SQSUBv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
57090 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv1i64),
57091 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57092 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57093 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57094 GIR_RootConstrainSelectedInstOperands,
57095 // GIR_Coverage, 4870,
57096 GIR_EraseRootFromParent_Done,
57097 // Label 3290: @158175
57098 GIM_Try, /*On fail goto*//*Label 3291*/ GIMT_Encode4(158220), // Rule ID 4871 //
57099 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
57100 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
57101 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
57102 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
57103 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
57104 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57105 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57106 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57107 // (intrinsic_wo_chain:{ *:[i32] } 660:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQSUBv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
57108 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv1i32),
57109 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57110 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57111 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57112 GIR_RootConstrainSelectedInstOperands,
57113 // GIR_Coverage, 4871,
57114 GIR_EraseRootFromParent_Done,
57115 // Label 3291: @158220
57116 GIM_Try, /*On fail goto*//*Label 3292*/ GIMT_Encode4(158265), // Rule ID 4872 //
57117 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
57118 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqadd),
57119 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57120 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57121 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
57122 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57123 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57124 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57125 // (intrinsic_wo_chain:{ *:[i64] } 701:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
57126 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADDv1i64),
57127 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57128 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57129 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57130 GIR_RootConstrainSelectedInstOperands,
57131 // GIR_Coverage, 4872,
57132 GIR_EraseRootFromParent_Done,
57133 // Label 3292: @158265
57134 GIM_Try, /*On fail goto*//*Label 3293*/ GIMT_Encode4(158310), // Rule ID 4873 //
57135 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
57136 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqadd),
57137 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
57138 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
57139 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
57140 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57141 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57142 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57143 // (intrinsic_wo_chain:{ *:[i32] } 701:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
57144 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADDv1i32),
57145 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57146 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57147 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57148 GIR_RootConstrainSelectedInstOperands,
57149 // GIR_Coverage, 4873,
57150 GIR_EraseRootFromParent_Done,
57151 // Label 3293: @158310
57152 GIM_Try, /*On fail goto*//*Label 3294*/ GIMT_Encode4(158355), // Rule ID 4874 //
57153 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
57154 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
57155 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57156 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57157 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
57158 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57159 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57160 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57161 // (intrinsic_wo_chain:{ *:[i64] } 702:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
57162 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv1i64),
57163 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57164 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57165 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57166 GIR_RootConstrainSelectedInstOperands,
57167 // GIR_Coverage, 4874,
57168 GIR_EraseRootFromParent_Done,
57169 // Label 3294: @158355
57170 GIM_Try, /*On fail goto*//*Label 3295*/ GIMT_Encode4(158400), // Rule ID 4875 //
57171 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
57172 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
57173 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
57174 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
57175 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
57176 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57177 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57178 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57179 // (intrinsic_wo_chain:{ *:[i32] } 702:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQRSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
57180 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv1i32),
57181 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57182 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57183 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57184 GIR_RootConstrainSelectedInstOperands,
57185 // GIR_Coverage, 4875,
57186 GIR_EraseRootFromParent_Done,
57187 // Label 3295: @158400
57188 GIM_Try, /*On fail goto*//*Label 3296*/ GIMT_Encode4(158445), // Rule ID 4876 //
57189 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
57190 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
57191 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57192 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57193 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
57194 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57195 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57196 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57197 // (intrinsic_wo_chain:{ *:[i64] } 704:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
57198 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv1i64),
57199 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57200 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57201 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57202 GIR_RootConstrainSelectedInstOperands,
57203 // GIR_Coverage, 4876,
57204 GIR_EraseRootFromParent_Done,
57205 // Label 3296: @158445
57206 GIM_Try, /*On fail goto*//*Label 3297*/ GIMT_Encode4(158490), // Rule ID 4877 //
57207 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
57208 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
57209 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
57210 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
57211 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
57212 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57213 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57214 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57215 // (intrinsic_wo_chain:{ *:[i32] } 704:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
57216 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv1i32),
57217 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57218 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57219 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57220 GIR_RootConstrainSelectedInstOperands,
57221 // GIR_Coverage, 4877,
57222 GIR_EraseRootFromParent_Done,
57223 // Label 3297: @158490
57224 GIM_Try, /*On fail goto*//*Label 3298*/ GIMT_Encode4(158535), // Rule ID 4878 //
57225 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
57226 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqsub),
57227 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57228 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57229 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
57230 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57231 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57232 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57233 // (intrinsic_wo_chain:{ *:[i64] } 706:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (UQSUBv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
57234 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv1i64),
57235 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57236 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57237 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57238 GIR_RootConstrainSelectedInstOperands,
57239 // GIR_Coverage, 4878,
57240 GIR_EraseRootFromParent_Done,
57241 // Label 3298: @158535
57242 GIM_Try, /*On fail goto*//*Label 3299*/ GIMT_Encode4(158580), // Rule ID 4879 //
57243 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
57244 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqsub),
57245 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
57246 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
57247 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
57248 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57249 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57250 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57251 // (intrinsic_wo_chain:{ *:[i32] } 706:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (UQSUBv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
57252 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv1i32),
57253 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57254 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57255 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57256 GIR_RootConstrainSelectedInstOperands,
57257 // GIR_Coverage, 4879,
57258 GIR_EraseRootFromParent_Done,
57259 // Label 3299: @158580
57260 GIM_Try, /*On fail goto*//*Label 3300*/ GIMT_Encode4(158625), // Rule ID 4897 //
57261 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
57262 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
57263 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57264 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57265 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
57266 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57267 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57268 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57269 // (intrinsic_wo_chain:{ *:[v1i64] } 716:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn) => (USQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn)
57270 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv1i64),
57271 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
57272 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
57273 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
57274 GIR_RootConstrainSelectedInstOperands,
57275 // GIR_Coverage, 4897,
57276 GIR_EraseRootFromParent_Done,
57277 // Label 3300: @158625
57278 GIM_Try, /*On fail goto*//*Label 3301*/ GIMT_Encode4(158667), // Rule ID 5236 //
57279 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_tbl1),
57280 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
57281 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
57282 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
57283 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57284 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
57285 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57286 // (intrinsic_wo_chain:{ *:[v8i8] } 678:{ *:[iPTR] }, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri) => (TBLv8i8One:{ *:[v8i8] } VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri)
57287 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLv8i8One),
57288 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
57289 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57290 GIR_RootToRootCopy, /*OpIdx*/3, // Ri
57291 GIR_RootConstrainSelectedInstOperands,
57292 // GIR_Coverage, 5236,
57293 GIR_EraseRootFromParent_Done,
57294 // Label 3301: @158667
57295 GIM_Try, /*On fail goto*//*Label 3302*/ GIMT_Encode4(158709), // Rule ID 5237 //
57296 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_tbl1),
57297 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
57298 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
57299 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
57300 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
57301 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
57302 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
57303 // (intrinsic_wo_chain:{ *:[v16i8] } 678:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn) => (TBLv16i8One:{ *:[v16i8] } V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn)
57304 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLv16i8One),
57305 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
57306 GIR_RootToRootCopy, /*OpIdx*/2, // Ri
57307 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
57308 GIR_RootConstrainSelectedInstOperands,
57309 // GIR_Coverage, 5237,
57310 GIR_EraseRootFromParent_Done,
57311 // Label 3302: @158709
57312 GIM_Try, /*On fail goto*//*Label 3303*/ GIMT_Encode4(158806), // Rule ID 5876 //
57313 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
57314 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
57315 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
57316 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
57317 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57318 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
57319 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
57320 // (intrinsic_wo_chain:{ *:[i32] } 562:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FACGE16:{ *:[i16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm), hsub:{ *:[i32] })
57321 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
57322 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
57323 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FACGE16),
57324 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57325 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
57326 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // Rm
57327 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
57328 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
57329 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57330 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
57331 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
57332 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
57333 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
57334 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
57335 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
57336 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
57337 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
57338 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
57339 // GIR_Coverage, 5876,
57340 GIR_EraseRootFromParent_Done,
57341 // Label 3303: @158806
57342 GIM_Try, /*On fail goto*//*Label 3304*/ GIMT_Encode4(158903), // Rule ID 5877 //
57343 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
57344 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
57345 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
57346 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
57347 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
57348 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
57349 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
57350 // (intrinsic_wo_chain:{ *:[i32] } 563:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FACGT16:{ *:[i16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm), hsub:{ *:[i32] })
57351 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
57352 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
57353 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FACGT16),
57354 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57355 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
57356 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // Rm
57357 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
57358 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
57359 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
57360 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
57361 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
57362 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
57363 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
57364 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
57365 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
57366 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
57367 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
57368 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
57369 // GIR_Coverage, 5877,
57370 GIR_EraseRootFromParent_Done,
57371 // Label 3304: @158903
57372 GIM_Try, /*On fail goto*//*Label 3305*/ GIMT_Encode4(158945), // Rule ID 6626 //
57373 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
57374 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57375 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57376 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
57377 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57378 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57379 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57380 // (intrinsic_wo_chain:{ *:[i64] } 665:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
57381 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv1i64),
57382 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57383 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57384 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57385 GIR_RootConstrainSelectedInstOperands,
57386 // GIR_Coverage, 6626,
57387 GIR_EraseRootFromParent_Done,
57388 // Label 3305: @158945
57389 GIM_Try, /*On fail goto*//*Label 3306*/ GIMT_Encode4(158987), // Rule ID 6627 //
57390 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
57391 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57392 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57393 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
57394 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57395 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57396 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57397 // (intrinsic_wo_chain:{ *:[i64] } 713:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (USHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
57398 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv1i64),
57399 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57400 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57401 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57402 GIR_RootConstrainSelectedInstOperands,
57403 // GIR_Coverage, 6627,
57404 GIR_EraseRootFromParent_Done,
57405 // Label 3306: @158987
57406 GIM_Try, /*On fail goto*//*Label 3307*/ GIMT_Encode4(159029), // Rule ID 6628 //
57407 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
57408 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57409 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57410 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
57411 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57412 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57413 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57414 // (intrinsic_wo_chain:{ *:[i64] } 664:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (SRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
57415 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv1i64),
57416 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57417 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57418 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57419 GIR_RootConstrainSelectedInstOperands,
57420 // GIR_Coverage, 6628,
57421 GIR_EraseRootFromParent_Done,
57422 // Label 3307: @159029
57423 GIM_Try, /*On fail goto*//*Label 3308*/ GIMT_Encode4(159071), // Rule ID 6629 //
57424 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
57425 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57426 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57427 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
57428 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57429 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57430 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
57431 // (intrinsic_wo_chain:{ *:[i64] } 710:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm) => (URSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
57432 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv1i64),
57433 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57434 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57435 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57436 GIR_RootConstrainSelectedInstOperands,
57437 // GIR_Coverage, 6629,
57438 GIR_EraseRootFromParent_Done,
57439 // Label 3308: @159071
57440 GIM_Try, /*On fail goto*//*Label 3309*/ GIMT_Encode4(159119), // Rule ID 6669 //
57441 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_blend),
57442 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57443 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57444 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
57445 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57446 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57447 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57448 // (intrinsic_wo_chain:{ *:[i64] } 285:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, GPR64:{ *:[i64] }:$Rn) => (BFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rd, GPR64:{ *:[i64] }:$Rn, 16:{ *:[i64] }, 15:{ *:[i64] })
57449 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMXri),
57450 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57451 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
57452 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
57453 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
57454 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
57455 GIR_RootConstrainSelectedInstOperands,
57456 // GIR_Coverage, 6669,
57457 GIR_EraseRootFromParent_Done,
57458 // Label 3309: @159119
57459 GIM_Try, /*On fail goto*//*Label 3310*/ GIMT_Encode4(159164), // Rule ID 9711 //
57460 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57461 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n64),
57462 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57463 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57464 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
57465 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57466 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57467 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57468 // (intrinsic_wo_chain:{ *:[i64] } 1807:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv16i1] }:$Pg) => (UQINCP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$Pg, ?:{ *:[i64] }:$Rn)
57469 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_XP_B),
57470 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
57471 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
57472 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57473 GIR_RootConstrainSelectedInstOperands,
57474 // GIR_Coverage, 9711,
57475 GIR_EraseRootFromParent_Done,
57476 // Label 3310: @159164
57477 GIM_Try, /*On fail goto*//*Label 3311*/ GIMT_Encode4(159209), // Rule ID 9712 //
57478 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57479 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n64),
57480 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57481 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57482 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
57483 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57484 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57485 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57486 // (intrinsic_wo_chain:{ *:[i64] } 1807:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv8i1] }:$Pg) => (UQINCP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$Pg, ?:{ *:[i64] }:$Rn)
57487 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_XP_H),
57488 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
57489 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
57490 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57491 GIR_RootConstrainSelectedInstOperands,
57492 // GIR_Coverage, 9712,
57493 GIR_EraseRootFromParent_Done,
57494 // Label 3311: @159209
57495 GIM_Try, /*On fail goto*//*Label 3312*/ GIMT_Encode4(159254), // Rule ID 9713 //
57496 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57497 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n64),
57498 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57499 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57500 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
57501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57502 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57503 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57504 // (intrinsic_wo_chain:{ *:[i64] } 1807:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv4i1] }:$Pg) => (UQINCP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$Pg, ?:{ *:[i64] }:$Rn)
57505 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_XP_S),
57506 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
57507 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
57508 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57509 GIR_RootConstrainSelectedInstOperands,
57510 // GIR_Coverage, 9713,
57511 GIR_EraseRootFromParent_Done,
57512 // Label 3312: @159254
57513 GIM_Try, /*On fail goto*//*Label 3313*/ GIMT_Encode4(159299), // Rule ID 9714 //
57514 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57515 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n64),
57516 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57517 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57518 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
57519 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57520 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57521 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57522 // (intrinsic_wo_chain:{ *:[i64] } 1807:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv2i1] }:$Pg) => (UQINCP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$Pg, ?:{ *:[i64] }:$Rn)
57523 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_XP_D),
57524 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
57525 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
57526 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57527 GIR_RootConstrainSelectedInstOperands,
57528 // GIR_Coverage, 9714,
57529 GIR_EraseRootFromParent_Done,
57530 // Label 3313: @159299
57531 GIM_Try, /*On fail goto*//*Label 3314*/ GIMT_Encode4(159344), // Rule ID 9723 //
57532 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57533 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp_n64),
57534 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57535 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57536 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
57537 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57538 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57539 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57540 // (intrinsic_wo_chain:{ *:[i64] } 1562:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv16i1] }:$Pg) => (SQDECP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$Pg, ?:{ *:[i64] }:$Rn)
57541 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_XP_B),
57542 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
57543 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
57544 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57545 GIR_RootConstrainSelectedInstOperands,
57546 // GIR_Coverage, 9723,
57547 GIR_EraseRootFromParent_Done,
57548 // Label 3314: @159344
57549 GIM_Try, /*On fail goto*//*Label 3315*/ GIMT_Encode4(159389), // Rule ID 9724 //
57550 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57551 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp_n64),
57552 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57553 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57554 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
57555 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57556 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57557 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57558 // (intrinsic_wo_chain:{ *:[i64] } 1562:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv8i1] }:$Pg) => (SQDECP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$Pg, ?:{ *:[i64] }:$Rn)
57559 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_XP_H),
57560 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
57561 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
57562 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57563 GIR_RootConstrainSelectedInstOperands,
57564 // GIR_Coverage, 9724,
57565 GIR_EraseRootFromParent_Done,
57566 // Label 3315: @159389
57567 GIM_Try, /*On fail goto*//*Label 3316*/ GIMT_Encode4(159434), // Rule ID 9725 //
57568 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57569 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp_n64),
57570 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57571 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57572 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
57573 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57574 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57575 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57576 // (intrinsic_wo_chain:{ *:[i64] } 1562:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv4i1] }:$Pg) => (SQDECP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$Pg, ?:{ *:[i64] }:$Rn)
57577 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_XP_S),
57578 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
57579 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
57580 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57581 GIR_RootConstrainSelectedInstOperands,
57582 // GIR_Coverage, 9725,
57583 GIR_EraseRootFromParent_Done,
57584 // Label 3316: @159434
57585 GIM_Try, /*On fail goto*//*Label 3317*/ GIMT_Encode4(159479), // Rule ID 9726 //
57586 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57587 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp_n64),
57588 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57589 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57590 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
57591 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57592 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57593 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57594 // (intrinsic_wo_chain:{ *:[i64] } 1562:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv2i1] }:$Pg) => (SQDECP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$Pg, ?:{ *:[i64] }:$Rn)
57595 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_XP_D),
57596 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
57597 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
57598 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57599 GIR_RootConstrainSelectedInstOperands,
57600 // GIR_Coverage, 9726,
57601 GIR_EraseRootFromParent_Done,
57602 // Label 3317: @159479
57603 GIM_Try, /*On fail goto*//*Label 3318*/ GIMT_Encode4(159524), // Rule ID 9727 //
57604 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57605 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n32),
57606 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
57607 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
57608 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
57609 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
57610 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
57611 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57612 // (intrinsic_wo_chain:{ *:[i32] } 1792:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv16i1] }:$Pg) => (UQDECP_WP_B:{ *:[i32] } PPRAny:{ *:[nxv16i1] }:$Pg, ?:{ *:[i32] }:$Rn)
57613 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_WP_B),
57614 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
57615 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
57616 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57617 GIR_RootConstrainSelectedInstOperands,
57618 // GIR_Coverage, 9727,
57619 GIR_EraseRootFromParent_Done,
57620 // Label 3318: @159524
57621 GIM_Try, /*On fail goto*//*Label 3319*/ GIMT_Encode4(159569), // Rule ID 9728 //
57622 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57623 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n32),
57624 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
57625 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
57626 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
57627 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
57628 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
57629 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57630 // (intrinsic_wo_chain:{ *:[i32] } 1792:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv8i1] }:$Pg) => (UQDECP_WP_H:{ *:[i32] } PPRAny:{ *:[nxv8i1] }:$Pg, ?:{ *:[i32] }:$Rn)
57631 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_WP_H),
57632 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
57633 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
57634 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57635 GIR_RootConstrainSelectedInstOperands,
57636 // GIR_Coverage, 9728,
57637 GIR_EraseRootFromParent_Done,
57638 // Label 3319: @159569
57639 GIM_Try, /*On fail goto*//*Label 3320*/ GIMT_Encode4(159614), // Rule ID 9729 //
57640 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57641 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n32),
57642 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
57643 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
57644 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
57645 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
57646 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
57647 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57648 // (intrinsic_wo_chain:{ *:[i32] } 1792:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv4i1] }:$Pg) => (UQDECP_WP_S:{ *:[i32] } PPRAny:{ *:[nxv4i1] }:$Pg, ?:{ *:[i32] }:$Rn)
57649 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_WP_S),
57650 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
57651 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
57652 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57653 GIR_RootConstrainSelectedInstOperands,
57654 // GIR_Coverage, 9729,
57655 GIR_EraseRootFromParent_Done,
57656 // Label 3320: @159614
57657 GIM_Try, /*On fail goto*//*Label 3321*/ GIMT_Encode4(159659), // Rule ID 9730 //
57658 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57659 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n32),
57660 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
57661 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
57662 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
57663 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
57664 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
57665 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57666 // (intrinsic_wo_chain:{ *:[i32] } 1792:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv2i1] }:$Pg) => (UQDECP_WP_D:{ *:[i32] } PPRAny:{ *:[nxv2i1] }:$Pg, ?:{ *:[i32] }:$Rn)
57667 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_WP_D),
57668 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
57669 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
57670 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57671 GIR_RootConstrainSelectedInstOperands,
57672 // GIR_Coverage, 9730,
57673 GIR_EraseRootFromParent_Done,
57674 // Label 3321: @159659
57675 GIM_Try, /*On fail goto*//*Label 3322*/ GIMT_Encode4(159704), // Rule ID 9731 //
57676 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57677 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n64),
57678 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57679 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57680 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
57681 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57682 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57683 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57684 // (intrinsic_wo_chain:{ *:[i64] } 1793:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv16i1] }:$Pg) => (UQDECP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$Pg, ?:{ *:[i64] }:$Rn)
57685 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_XP_B),
57686 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
57687 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
57688 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57689 GIR_RootConstrainSelectedInstOperands,
57690 // GIR_Coverage, 9731,
57691 GIR_EraseRootFromParent_Done,
57692 // Label 3322: @159704
57693 GIM_Try, /*On fail goto*//*Label 3323*/ GIMT_Encode4(159749), // Rule ID 9732 //
57694 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57695 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n64),
57696 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57697 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57698 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
57699 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57700 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57701 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57702 // (intrinsic_wo_chain:{ *:[i64] } 1793:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv8i1] }:$Pg) => (UQDECP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$Pg, ?:{ *:[i64] }:$Rn)
57703 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_XP_H),
57704 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
57705 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
57706 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57707 GIR_RootConstrainSelectedInstOperands,
57708 // GIR_Coverage, 9732,
57709 GIR_EraseRootFromParent_Done,
57710 // Label 3323: @159749
57711 GIM_Try, /*On fail goto*//*Label 3324*/ GIMT_Encode4(159794), // Rule ID 9733 //
57712 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57713 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n64),
57714 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57715 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57716 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
57717 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57718 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57719 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57720 // (intrinsic_wo_chain:{ *:[i64] } 1793:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv4i1] }:$Pg) => (UQDECP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$Pg, ?:{ *:[i64] }:$Rn)
57721 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_XP_S),
57722 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
57723 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
57724 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57725 GIR_RootConstrainSelectedInstOperands,
57726 // GIR_Coverage, 9733,
57727 GIR_EraseRootFromParent_Done,
57728 // Label 3324: @159794
57729 GIM_Try, /*On fail goto*//*Label 3325*/ GIMT_Encode4(159839), // Rule ID 9734 //
57730 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57731 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n64),
57732 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57733 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
57734 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
57735 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57736 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57737 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57738 // (intrinsic_wo_chain:{ *:[i64] } 1793:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv2i1] }:$Pg) => (UQDECP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$Pg, ?:{ *:[i64] }:$Rn)
57739 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_XP_D),
57740 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
57741 GIR_RootToRootCopy, /*OpIdx*/3, // Pg
57742 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57743 GIR_RootConstrainSelectedInstOperands,
57744 // GIR_Coverage, 9734,
57745 GIR_EraseRootFromParent_Done,
57746 // Label 3325: @159839
57747 GIM_Try, /*On fail goto*//*Label 3326*/ GIMT_Encode4(159885), // Rule ID 149 //
57748 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMTE),
57749 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_gmi),
57750 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57751 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
57752 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57753 // MIs[0] Rn
57754 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
57755 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
57756 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57757 // (intrinsic_wo_chain:{ *:[i64] } 537:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (GMI:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
57758 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::GMI),
57759 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57760 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57761 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57762 GIR_RootConstrainSelectedInstOperands,
57763 // GIR_Coverage, 149,
57764 GIR_EraseRootFromParent_Done,
57765 // Label 3326: @159885
57766 GIM_Try, /*On fail goto*//*Label 3327*/ GIMT_Encode4(159932), // Rule ID 150 //
57767 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMTE),
57768 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_subp),
57769 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
57770 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
57771 // MIs[0] Rn
57772 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
57773 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
57774 // MIs[0] Rm
57775 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
57776 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
57777 // (intrinsic_wo_chain:{ *:[i64] } 1058:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm) => (SUBP:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm)
57778 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBP),
57779 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
57780 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
57781 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
57782 GIR_RootConstrainSelectedInstOperands,
57783 // GIR_Coverage, 150,
57784 GIR_EraseRootFromParent_Done,
57785 // Label 3327: @159932
57786 GIM_Try, /*On fail goto*//*Label 3328*/ GIMT_Encode4(159969), // Rule ID 2339 //
57787 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57788 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1_b16),
57789 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
57790 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
57791 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
57792 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57793 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1932:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (ZIP1_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
57794 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_H),
57795 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
57796 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
57797 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
57798 GIR_RootConstrainSelectedInstOperands,
57799 // GIR_Coverage, 2339,
57800 GIR_EraseRootFromParent_Done,
57801 // Label 3328: @159969
57802 GIM_Try, /*On fail goto*//*Label 3329*/ GIMT_Encode4(160006), // Rule ID 2340 //
57803 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57804 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1_b32),
57805 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
57806 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
57807 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
57808 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57809 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1933:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (ZIP1_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
57810 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_S),
57811 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
57812 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
57813 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
57814 GIR_RootConstrainSelectedInstOperands,
57815 // GIR_Coverage, 2340,
57816 GIR_EraseRootFromParent_Done,
57817 // Label 3329: @160006
57818 GIM_Try, /*On fail goto*//*Label 3330*/ GIMT_Encode4(160043), // Rule ID 2341 //
57819 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57820 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1_b64),
57821 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
57822 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
57823 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
57824 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57825 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1934:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (ZIP1_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
57826 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_D),
57827 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
57828 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
57829 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
57830 GIR_RootConstrainSelectedInstOperands,
57831 // GIR_Coverage, 2341,
57832 GIR_EraseRootFromParent_Done,
57833 // Label 3330: @160043
57834 GIM_Try, /*On fail goto*//*Label 3331*/ GIMT_Encode4(160080), // Rule ID 2343 //
57835 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57836 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2_b16),
57837 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
57838 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
57839 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
57840 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57841 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1937:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (ZIP2_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
57842 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_H),
57843 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
57844 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
57845 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
57846 GIR_RootConstrainSelectedInstOperands,
57847 // GIR_Coverage, 2343,
57848 GIR_EraseRootFromParent_Done,
57849 // Label 3331: @160080
57850 GIM_Try, /*On fail goto*//*Label 3332*/ GIMT_Encode4(160117), // Rule ID 2344 //
57851 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57852 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2_b32),
57853 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
57854 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
57855 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
57856 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57857 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1938:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (ZIP2_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
57858 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_S),
57859 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
57860 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
57861 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
57862 GIR_RootConstrainSelectedInstOperands,
57863 // GIR_Coverage, 2344,
57864 GIR_EraseRootFromParent_Done,
57865 // Label 3332: @160117
57866 GIM_Try, /*On fail goto*//*Label 3333*/ GIMT_Encode4(160154), // Rule ID 2345 //
57867 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57868 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2_b64),
57869 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
57870 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
57871 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
57872 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57873 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1939:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (ZIP2_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
57874 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_D),
57875 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
57876 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
57877 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
57878 GIR_RootConstrainSelectedInstOperands,
57879 // GIR_Coverage, 2345,
57880 GIR_EraseRootFromParent_Done,
57881 // Label 3333: @160154
57882 GIM_Try, /*On fail goto*//*Label 3334*/ GIMT_Encode4(160191), // Rule ID 2347 //
57883 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57884 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1_b16),
57885 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
57886 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
57887 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
57888 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57889 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1858:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (UZP1_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
57890 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_H),
57891 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
57892 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
57893 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
57894 GIR_RootConstrainSelectedInstOperands,
57895 // GIR_Coverage, 2347,
57896 GIR_EraseRootFromParent_Done,
57897 // Label 3334: @160191
57898 GIM_Try, /*On fail goto*//*Label 3335*/ GIMT_Encode4(160228), // Rule ID 2348 //
57899 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57900 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1_b32),
57901 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
57902 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
57903 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
57904 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57905 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1859:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (UZP1_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
57906 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_S),
57907 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
57908 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
57909 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
57910 GIR_RootConstrainSelectedInstOperands,
57911 // GIR_Coverage, 2348,
57912 GIR_EraseRootFromParent_Done,
57913 // Label 3335: @160228
57914 GIM_Try, /*On fail goto*//*Label 3336*/ GIMT_Encode4(160265), // Rule ID 2349 //
57915 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57916 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1_b64),
57917 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
57918 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
57919 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
57920 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57921 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1860:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (UZP1_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
57922 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_D),
57923 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
57924 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
57925 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
57926 GIR_RootConstrainSelectedInstOperands,
57927 // GIR_Coverage, 2349,
57928 GIR_EraseRootFromParent_Done,
57929 // Label 3336: @160265
57930 GIM_Try, /*On fail goto*//*Label 3337*/ GIMT_Encode4(160302), // Rule ID 2351 //
57931 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57932 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2_b16),
57933 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
57934 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
57935 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
57936 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57937 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1863:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (UZP2_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
57938 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_H),
57939 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
57940 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
57941 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
57942 GIR_RootConstrainSelectedInstOperands,
57943 // GIR_Coverage, 2351,
57944 GIR_EraseRootFromParent_Done,
57945 // Label 3337: @160302
57946 GIM_Try, /*On fail goto*//*Label 3338*/ GIMT_Encode4(160339), // Rule ID 2352 //
57947 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57948 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2_b32),
57949 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
57950 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
57951 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
57952 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57953 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1864:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (UZP2_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
57954 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_S),
57955 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
57956 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
57957 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
57958 GIR_RootConstrainSelectedInstOperands,
57959 // GIR_Coverage, 2352,
57960 GIR_EraseRootFromParent_Done,
57961 // Label 3338: @160339
57962 GIM_Try, /*On fail goto*//*Label 3339*/ GIMT_Encode4(160376), // Rule ID 2353 //
57963 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57964 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2_b64),
57965 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
57966 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
57967 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
57968 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57969 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1865:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (UZP2_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
57970 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_D),
57971 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
57972 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
57973 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
57974 GIR_RootConstrainSelectedInstOperands,
57975 // GIR_Coverage, 2353,
57976 GIR_EraseRootFromParent_Done,
57977 // Label 3339: @160376
57978 GIM_Try, /*On fail goto*//*Label 3340*/ GIMT_Encode4(160413), // Rule ID 2355 //
57979 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57980 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1_b16),
57981 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
57982 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
57983 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
57984 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
57985 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1702:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (TRN1_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
57986 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_H),
57987 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
57988 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
57989 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
57990 GIR_RootConstrainSelectedInstOperands,
57991 // GIR_Coverage, 2355,
57992 GIR_EraseRootFromParent_Done,
57993 // Label 3340: @160413
57994 GIM_Try, /*On fail goto*//*Label 3341*/ GIMT_Encode4(160450), // Rule ID 2356 //
57995 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
57996 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1_b32),
57997 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
57998 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
57999 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
58000 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
58001 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1703:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (TRN1_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
58002 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_S),
58003 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
58004 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
58005 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
58006 GIR_RootConstrainSelectedInstOperands,
58007 // GIR_Coverage, 2356,
58008 GIR_EraseRootFromParent_Done,
58009 // Label 3341: @160450
58010 GIM_Try, /*On fail goto*//*Label 3342*/ GIMT_Encode4(160487), // Rule ID 2357 //
58011 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58012 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1_b64),
58013 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
58014 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
58015 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
58016 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
58017 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1704:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (TRN1_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
58018 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_D),
58019 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
58020 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
58021 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
58022 GIR_RootConstrainSelectedInstOperands,
58023 // GIR_Coverage, 2357,
58024 GIR_EraseRootFromParent_Done,
58025 // Label 3342: @160487
58026 GIM_Try, /*On fail goto*//*Label 3343*/ GIMT_Encode4(160524), // Rule ID 2359 //
58027 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58028 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2_b16),
58029 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
58030 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
58031 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
58032 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
58033 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1707:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (TRN2_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
58034 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_H),
58035 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
58036 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
58037 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
58038 GIR_RootConstrainSelectedInstOperands,
58039 // GIR_Coverage, 2359,
58040 GIR_EraseRootFromParent_Done,
58041 // Label 3343: @160524
58042 GIM_Try, /*On fail goto*//*Label 3344*/ GIMT_Encode4(160561), // Rule ID 2360 //
58043 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58044 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2_b32),
58045 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
58046 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
58047 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
58048 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
58049 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1708:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (TRN2_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
58050 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_S),
58051 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
58052 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
58053 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
58054 GIR_RootConstrainSelectedInstOperands,
58055 // GIR_Coverage, 2360,
58056 GIR_EraseRootFromParent_Done,
58057 // Label 3344: @160561
58058 GIM_Try, /*On fail goto*//*Label 3345*/ GIMT_Encode4(160598), // Rule ID 2361 //
58059 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58060 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2_b64),
58061 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
58062 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
58063 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
58064 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
58065 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1709:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (TRN2_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
58066 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_D),
58067 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
58068 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
58069 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
58070 GIR_RootConstrainSelectedInstOperands,
58071 // GIR_Coverage, 2361,
58072 GIR_EraseRootFromParent_Done,
58073 // Label 3345: @160598
58074 GIM_Try, /*On fail goto*//*Label 3346*/ GIMT_Encode4(160635), // Rule ID 2362 //
58075 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
58076 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_histseg),
58077 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
58078 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
58079 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
58080 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58081 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1330:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm) => (HISTSEG_ZZZ:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)
58082 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HISTSEG_ZZZ),
58083 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58084 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
58085 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
58086 GIR_RootConstrainSelectedInstOperands,
58087 // GIR_Coverage, 2362,
58088 GIR_EraseRootFromParent_Done,
58089 // Label 3346: @160635
58090 GIM_Try, /*On fail goto*//*Label 3347*/ GIMT_Encode4(160675), // Rule ID 2520 //
58091 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58092 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pfirst),
58093 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
58094 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
58095 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
58096 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
58097 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1406:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2) => (PFIRST_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
58098 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PFIRST_B),
58099 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pdn]
58100 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58101 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58102 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
58103 GIR_RootConstrainSelectedInstOperands,
58104 // GIR_Coverage, 2520,
58105 GIR_EraseRootFromParent_Done,
58106 // Label 3347: @160675
58107 GIM_Try, /*On fail goto*//*Label 3348*/ GIMT_Encode4(160715), // Rule ID 2521 //
58108 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58109 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pnext),
58110 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
58111 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
58112 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
58113 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
58114 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1414:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2) => (PNEXT_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
58115 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PNEXT_B),
58116 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pdn]
58117 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58118 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58119 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
58120 GIR_RootConstrainSelectedInstOperands,
58121 // GIR_Coverage, 2521,
58122 GIR_EraseRootFromParent_Done,
58123 // Label 3348: @160715
58124 GIM_Try, /*On fail goto*//*Label 3349*/ GIMT_Encode4(160755), // Rule ID 2522 //
58125 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58126 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pnext),
58127 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
58128 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
58129 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
58130 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
58131 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1414:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2) => (PNEXT_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
58132 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PNEXT_H),
58133 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pdn]
58134 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58135 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58136 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
58137 GIR_RootConstrainSelectedInstOperands,
58138 // GIR_Coverage, 2522,
58139 GIR_EraseRootFromParent_Done,
58140 // Label 3349: @160755
58141 GIM_Try, /*On fail goto*//*Label 3350*/ GIMT_Encode4(160795), // Rule ID 2523 //
58142 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58143 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pnext),
58144 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
58145 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
58146 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
58147 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
58148 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1414:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2) => (PNEXT_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
58149 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PNEXT_S),
58150 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pdn]
58151 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58152 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58153 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
58154 GIR_RootConstrainSelectedInstOperands,
58155 // GIR_Coverage, 2523,
58156 GIR_EraseRootFromParent_Done,
58157 // Label 3350: @160795
58158 GIM_Try, /*On fail goto*//*Label 3351*/ GIMT_Encode4(160835), // Rule ID 2524 //
58159 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58160 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pnext),
58161 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
58162 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
58163 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
58164 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
58165 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1414:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2) => (PNEXT_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
58166 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PNEXT_D),
58167 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pdn]
58168 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58169 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58170 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
58171 GIR_RootConstrainSelectedInstOperands,
58172 // GIR_Coverage, 2524,
58173 GIR_EraseRootFromParent_Done,
58174 // Label 3351: @160835
58175 GIM_Try, /*On fail goto*//*Label 3352*/ GIMT_Encode4(160872), // Rule ID 2541 //
58176 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58177 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp),
58178 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
58179 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
58180 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
58181 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58182 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1594:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2) => (SQINCP_ZP_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
58183 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_ZP_H),
58184 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
58185 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58186 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58187 GIR_RootConstrainSelectedInstOperands,
58188 // GIR_Coverage, 2541,
58189 GIR_EraseRootFromParent_Done,
58190 // Label 3352: @160872
58191 GIM_Try, /*On fail goto*//*Label 3353*/ GIMT_Encode4(160909), // Rule ID 2542 //
58192 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58193 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp),
58194 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
58195 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
58196 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
58197 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58198 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1594:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2) => (SQINCP_ZP_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
58199 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_ZP_S),
58200 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
58201 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58202 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58203 GIR_RootConstrainSelectedInstOperands,
58204 // GIR_Coverage, 2542,
58205 GIR_EraseRootFromParent_Done,
58206 // Label 3353: @160909
58207 GIM_Try, /*On fail goto*//*Label 3354*/ GIMT_Encode4(160946), // Rule ID 2543 //
58208 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58209 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp),
58210 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
58211 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
58212 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
58213 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58214 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1594:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2) => (SQINCP_ZP_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
58215 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_ZP_D),
58216 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
58217 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58218 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58219 GIR_RootConstrainSelectedInstOperands,
58220 // GIR_Coverage, 2543,
58221 GIR_EraseRootFromParent_Done,
58222 // Label 3354: @160946
58223 GIM_Try, /*On fail goto*//*Label 3355*/ GIMT_Encode4(160983), // Rule ID 2544 //
58224 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58225 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
58226 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
58227 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
58228 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
58229 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
58230 // (intrinsic_wo_chain:{ *:[i64] } 1151:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2) => (CNTP_XPP_B:{ *:[i64] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
58231 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTP_XPP_B),
58232 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
58233 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58234 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58235 GIR_RootConstrainSelectedInstOperands,
58236 // GIR_Coverage, 2544,
58237 GIR_EraseRootFromParent_Done,
58238 // Label 3355: @160983
58239 GIM_Try, /*On fail goto*//*Label 3356*/ GIMT_Encode4(161020), // Rule ID 2545 //
58240 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58241 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
58242 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
58243 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
58244 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
58245 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
58246 // (intrinsic_wo_chain:{ *:[i64] } 1151:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2) => (CNTP_XPP_H:{ *:[i64] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
58247 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTP_XPP_H),
58248 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
58249 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58250 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58251 GIR_RootConstrainSelectedInstOperands,
58252 // GIR_Coverage, 2545,
58253 GIR_EraseRootFromParent_Done,
58254 // Label 3356: @161020
58255 GIM_Try, /*On fail goto*//*Label 3357*/ GIMT_Encode4(161057), // Rule ID 2546 //
58256 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58257 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
58258 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
58259 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
58260 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
58261 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
58262 // (intrinsic_wo_chain:{ *:[i64] } 1151:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2) => (CNTP_XPP_S:{ *:[i64] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
58263 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTP_XPP_S),
58264 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
58265 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58266 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58267 GIR_RootConstrainSelectedInstOperands,
58268 // GIR_Coverage, 2546,
58269 GIR_EraseRootFromParent_Done,
58270 // Label 3357: @161057
58271 GIM_Try, /*On fail goto*//*Label 3358*/ GIMT_Encode4(161094), // Rule ID 2547 //
58272 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58273 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
58274 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
58275 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
58276 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
58277 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
58278 // (intrinsic_wo_chain:{ *:[i64] } 1151:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2) => (CNTP_XPP_D:{ *:[i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
58279 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTP_XPP_D),
58280 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
58281 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58282 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58283 GIR_RootConstrainSelectedInstOperands,
58284 // GIR_Coverage, 2547,
58285 GIR_EraseRootFromParent_Done,
58286 // Label 3358: @161094
58287 GIM_Try, /*On fail goto*//*Label 3359*/ GIMT_Encode4(161131), // Rule ID 2744 //
58288 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
58289 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftsmul_x),
58290 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
58291 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
58292 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
58293 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58294 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1327:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (FTSMUL_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
58295 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTSMUL_ZZZ_H),
58296 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58297 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58298 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58299 GIR_RootConstrainSelectedInstOperands,
58300 // GIR_Coverage, 2744,
58301 GIR_EraseRootFromParent_Done,
58302 // Label 3359: @161131
58303 GIM_Try, /*On fail goto*//*Label 3360*/ GIMT_Encode4(161168), // Rule ID 2745 //
58304 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
58305 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftsmul_x),
58306 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
58307 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
58308 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
58309 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58310 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1327:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (FTSMUL_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
58311 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTSMUL_ZZZ_S),
58312 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58313 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58314 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58315 GIR_RootConstrainSelectedInstOperands,
58316 // GIR_Coverage, 2745,
58317 GIR_EraseRootFromParent_Done,
58318 // Label 3360: @161168
58319 GIM_Try, /*On fail goto*//*Label 3361*/ GIMT_Encode4(161205), // Rule ID 2746 //
58320 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
58321 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftsmul_x),
58322 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
58323 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
58324 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
58325 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58326 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1327:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (FTSMUL_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
58327 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTSMUL_ZZZ_D),
58328 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58329 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58330 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58331 GIR_RootConstrainSelectedInstOperands,
58332 // GIR_Coverage, 2746,
58333 GIR_EraseRootFromParent_Done,
58334 // Label 3361: @161205
58335 GIM_Try, /*On fail goto*//*Label 3362*/ GIMT_Encode4(161242), // Rule ID 2924 //
58336 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58337 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh),
58338 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
58339 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
58340 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
58341 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58342 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1576:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SQDMULH_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
58343 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZ_B),
58344 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58345 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58346 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58347 GIR_RootConstrainSelectedInstOperands,
58348 // GIR_Coverage, 2924,
58349 GIR_EraseRootFromParent_Done,
58350 // Label 3362: @161242
58351 GIM_Try, /*On fail goto*//*Label 3363*/ GIMT_Encode4(161279), // Rule ID 2925 //
58352 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58353 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh),
58354 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
58355 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
58356 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
58357 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58358 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1576:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SQDMULH_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
58359 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZ_H),
58360 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58361 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58362 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58363 GIR_RootConstrainSelectedInstOperands,
58364 // GIR_Coverage, 2925,
58365 GIR_EraseRootFromParent_Done,
58366 // Label 3363: @161279
58367 GIM_Try, /*On fail goto*//*Label 3364*/ GIMT_Encode4(161316), // Rule ID 2926 //
58368 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58369 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh),
58370 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
58371 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
58372 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
58373 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58374 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1576:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SQDMULH_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
58375 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZ_S),
58376 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58377 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58378 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58379 GIR_RootConstrainSelectedInstOperands,
58380 // GIR_Coverage, 2926,
58381 GIR_EraseRootFromParent_Done,
58382 // Label 3364: @161316
58383 GIM_Try, /*On fail goto*//*Label 3365*/ GIMT_Encode4(161353), // Rule ID 2927 //
58384 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58385 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh),
58386 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
58387 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
58388 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
58389 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58390 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1576:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (SQDMULH_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
58391 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZ_D),
58392 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58393 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58394 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58395 GIR_RootConstrainSelectedInstOperands,
58396 // GIR_Coverage, 2927,
58397 GIR_EraseRootFromParent_Done,
58398 // Label 3365: @161353
58399 GIM_Try, /*On fail goto*//*Label 3366*/ GIMT_Encode4(161390), // Rule ID 2928 //
58400 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58401 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmul),
58402 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
58403 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
58404 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
58405 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58406 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1411:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (PMUL_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
58407 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMUL_ZZZ_B),
58408 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58409 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58410 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58411 GIR_RootConstrainSelectedInstOperands,
58412 // GIR_Coverage, 2928,
58413 GIR_EraseRootFromParent_Done,
58414 // Label 3366: @161390
58415 GIM_Try, /*On fail goto*//*Label 3367*/ GIMT_Encode4(161427), // Rule ID 2950 //
58416 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58417 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlb),
58418 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
58419 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
58420 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
58421 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58422 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1469:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SADDLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
58423 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLB_ZZZ_H),
58424 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58425 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58426 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58427 GIR_RootConstrainSelectedInstOperands,
58428 // GIR_Coverage, 2950,
58429 GIR_EraseRootFromParent_Done,
58430 // Label 3367: @161427
58431 GIM_Try, /*On fail goto*//*Label 3368*/ GIMT_Encode4(161464), // Rule ID 2951 //
58432 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58433 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlb),
58434 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
58435 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
58436 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
58437 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58438 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1469:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SADDLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
58439 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLB_ZZZ_S),
58440 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58441 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58442 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58443 GIR_RootConstrainSelectedInstOperands,
58444 // GIR_Coverage, 2951,
58445 GIR_EraseRootFromParent_Done,
58446 // Label 3368: @161464
58447 GIM_Try, /*On fail goto*//*Label 3369*/ GIMT_Encode4(161501), // Rule ID 2952 //
58448 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58449 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlb),
58450 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
58451 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
58452 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
58453 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58454 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1469:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SADDLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
58455 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLB_ZZZ_D),
58456 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58457 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58458 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58459 GIR_RootConstrainSelectedInstOperands,
58460 // GIR_Coverage, 2952,
58461 GIR_EraseRootFromParent_Done,
58462 // Label 3369: @161501
58463 GIM_Try, /*On fail goto*//*Label 3370*/ GIMT_Encode4(161538), // Rule ID 2953 //
58464 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58465 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddwb),
58466 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
58467 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
58468 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
58469 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58470 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1473:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SADDWB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
58471 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWB_ZZZ_H),
58472 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58473 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58474 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58475 GIR_RootConstrainSelectedInstOperands,
58476 // GIR_Coverage, 2953,
58477 GIR_EraseRootFromParent_Done,
58478 // Label 3370: @161538
58479 GIM_Try, /*On fail goto*//*Label 3371*/ GIMT_Encode4(161575), // Rule ID 2954 //
58480 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58481 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddwb),
58482 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
58483 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
58484 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
58485 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58486 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1473:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SADDWB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
58487 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWB_ZZZ_S),
58488 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58489 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58490 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58491 GIR_RootConstrainSelectedInstOperands,
58492 // GIR_Coverage, 2954,
58493 GIR_EraseRootFromParent_Done,
58494 // Label 3371: @161575
58495 GIM_Try, /*On fail goto*//*Label 3372*/ GIMT_Encode4(161612), // Rule ID 2955 //
58496 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58497 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddwb),
58498 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
58499 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
58500 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
58501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58502 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1473:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SADDWB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
58503 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWB_ZZZ_D),
58504 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58505 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58506 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58507 GIR_RootConstrainSelectedInstOperands,
58508 // GIR_Coverage, 2955,
58509 GIR_EraseRootFromParent_Done,
58510 // Label 3372: @161612
58511 GIM_Try, /*On fail goto*//*Label 3373*/ GIMT_Encode4(161649), // Rule ID 2956 //
58512 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2AES),
58513 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmullb_pair),
58514 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
58515 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
58516 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
58517 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58518 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1412:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (PMULLB_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
58519 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULLB_ZZZ_Q),
58520 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58521 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58522 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58523 GIR_RootConstrainSelectedInstOperands,
58524 // GIR_Coverage, 2956,
58525 GIR_EraseRootFromParent_Done,
58526 // Label 3373: @161649
58527 GIM_Try, /*On fail goto*//*Label 3374*/ GIMT_Encode4(161686), // Rule ID 2957 //
58528 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58529 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmullb_pair),
58530 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
58531 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
58532 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
58533 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58534 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1412:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (PMULLB_ZZZ_H:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
58535 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULLB_ZZZ_H),
58536 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58537 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58538 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58539 GIR_RootConstrainSelectedInstOperands,
58540 // GIR_Coverage, 2957,
58541 GIR_EraseRootFromParent_Done,
58542 // Label 3374: @161686
58543 GIM_Try, /*On fail goto*//*Label 3375*/ GIMT_Encode4(161723), // Rule ID 2958 //
58544 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58545 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmullb_pair),
58546 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
58547 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
58548 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
58549 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58550 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1412:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (PMULLB_ZZZ_D:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
58551 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULLB_ZZZ_D),
58552 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58553 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58554 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58555 GIR_RootConstrainSelectedInstOperands,
58556 // GIR_Coverage, 2958,
58557 GIR_EraseRootFromParent_Done,
58558 // Label 3375: @161723
58559 GIM_Try, /*On fail goto*//*Label 3376*/ GIMT_Encode4(161760), // Rule ID 2959 //
58560 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2BitPerm),
58561 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bext_x),
58562 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
58563 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
58564 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
58565 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58566 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1089:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (BEXT_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
58567 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BEXT_ZZZ_B),
58568 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58569 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58570 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58571 GIR_RootConstrainSelectedInstOperands,
58572 // GIR_Coverage, 2959,
58573 GIR_EraseRootFromParent_Done,
58574 // Label 3376: @161760
58575 GIM_Try, /*On fail goto*//*Label 3377*/ GIMT_Encode4(161797), // Rule ID 2960 //
58576 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2BitPerm),
58577 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bext_x),
58578 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
58579 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
58580 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
58581 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58582 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1089:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (BEXT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
58583 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BEXT_ZZZ_H),
58584 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58585 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58586 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58587 GIR_RootConstrainSelectedInstOperands,
58588 // GIR_Coverage, 2960,
58589 GIR_EraseRootFromParent_Done,
58590 // Label 3377: @161797
58591 GIM_Try, /*On fail goto*//*Label 3378*/ GIMT_Encode4(161834), // Rule ID 2961 //
58592 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2BitPerm),
58593 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bext_x),
58594 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
58595 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
58596 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
58597 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58598 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1089:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (BEXT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
58599 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BEXT_ZZZ_S),
58600 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58601 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58602 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58603 GIR_RootConstrainSelectedInstOperands,
58604 // GIR_Coverage, 2961,
58605 GIR_EraseRootFromParent_Done,
58606 // Label 3378: @161834
58607 GIM_Try, /*On fail goto*//*Label 3379*/ GIMT_Encode4(161871), // Rule ID 2962 //
58608 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2BitPerm),
58609 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bext_x),
58610 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
58611 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
58612 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
58613 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58614 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1089:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (BEXT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
58615 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BEXT_ZZZ_D),
58616 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58617 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58618 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58619 GIR_RootConstrainSelectedInstOperands,
58620 // GIR_Coverage, 2962,
58621 GIR_EraseRootFromParent_Done,
58622 // Label 3379: @161871
58623 GIM_Try, /*On fail goto*//*Label 3380*/ GIMT_Encode4(161908), // Rule ID 2963 //
58624 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58625 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlbt),
58626 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
58627 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
58628 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
58629 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58630 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1470:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SADDLBT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
58631 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLBT_ZZZ_H),
58632 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58633 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58634 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58635 GIR_RootConstrainSelectedInstOperands,
58636 // GIR_Coverage, 2963,
58637 GIR_EraseRootFromParent_Done,
58638 // Label 3380: @161908
58639 GIM_Try, /*On fail goto*//*Label 3381*/ GIMT_Encode4(161945), // Rule ID 2964 //
58640 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58641 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlbt),
58642 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
58643 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
58644 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
58645 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58646 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1470:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SADDLBT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
58647 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLBT_ZZZ_S),
58648 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58649 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58650 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58651 GIR_RootConstrainSelectedInstOperands,
58652 // GIR_Coverage, 2964,
58653 GIR_EraseRootFromParent_Done,
58654 // Label 3381: @161945
58655 GIM_Try, /*On fail goto*//*Label 3382*/ GIMT_Encode4(161982), // Rule ID 2965 //
58656 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58657 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlbt),
58658 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
58659 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
58660 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
58661 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58662 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1470:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SADDLBT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
58663 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLBT_ZZZ_D),
58664 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58665 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58666 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58667 GIR_RootConstrainSelectedInstOperands,
58668 // GIR_Coverage, 2965,
58669 GIR_EraseRootFromParent_Done,
58670 // Label 3382: @161982
58671 GIM_Try, /*On fail goto*//*Label 3383*/ GIMT_Encode4(162019), // Rule ID 3012 //
58672 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58673 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addhnb),
58674 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
58675 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
58676 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
58677 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58678 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1066:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (ADDHNB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
58679 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNB_ZZZ_B),
58680 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58681 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58682 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58683 GIR_RootConstrainSelectedInstOperands,
58684 // GIR_Coverage, 3012,
58685 GIR_EraseRootFromParent_Done,
58686 // Label 3383: @162019
58687 GIM_Try, /*On fail goto*//*Label 3384*/ GIMT_Encode4(162056), // Rule ID 3013 //
58688 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58689 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addhnb),
58690 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
58691 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
58692 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
58693 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58694 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1066:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (ADDHNB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
58695 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNB_ZZZ_H),
58696 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58697 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58698 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58699 GIR_RootConstrainSelectedInstOperands,
58700 // GIR_Coverage, 3013,
58701 GIR_EraseRootFromParent_Done,
58702 // Label 3384: @162056
58703 GIM_Try, /*On fail goto*//*Label 3385*/ GIMT_Encode4(162093), // Rule ID 3014 //
58704 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58705 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addhnb),
58706 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
58707 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
58708 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
58709 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58710 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1066:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (ADDHNB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
58711 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNB_ZZZ_S),
58712 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58713 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58714 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58715 GIR_RootConstrainSelectedInstOperands,
58716 // GIR_Coverage, 3014,
58717 GIR_EraseRootFromParent_Done,
58718 // Label 3385: @162093
58719 GIM_Try, /*On fail goto*//*Label 3386*/ GIMT_Encode4(162130), // Rule ID 3021 //
58720 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58721 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtnt),
58722 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
58723 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
58724 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
58725 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58726 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1633:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SQXTNT_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
58727 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNT_ZZ_B),
58728 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58729 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58730 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58731 GIR_RootConstrainSelectedInstOperands,
58732 // GIR_Coverage, 3021,
58733 GIR_EraseRootFromParent_Done,
58734 // Label 3386: @162130
58735 GIM_Try, /*On fail goto*//*Label 3387*/ GIMT_Encode4(162167), // Rule ID 3022 //
58736 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58737 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtnt),
58738 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
58739 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
58740 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
58741 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58742 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1633:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SQXTNT_ZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
58743 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNT_ZZ_H),
58744 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58745 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58746 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58747 GIR_RootConstrainSelectedInstOperands,
58748 // GIR_Coverage, 3022,
58749 GIR_EraseRootFromParent_Done,
58750 // Label 3387: @162167
58751 GIM_Try, /*On fail goto*//*Label 3388*/ GIMT_Encode4(162204), // Rule ID 3023 //
58752 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
58753 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtnt),
58754 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
58755 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
58756 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
58757 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58758 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1633:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (SQXTNT_ZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
58759 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNT_ZZ_S),
58760 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58761 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58762 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58763 GIR_RootConstrainSelectedInstOperands,
58764 // GIR_Coverage, 3023,
58765 GIR_EraseRootFromParent_Done,
58766 // Label 3388: @162204
58767 GIM_Try, /*On fail goto*//*Label 3389*/ GIMT_Encode4(162244), // Rule ID 3113 //
58768 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58769 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
58770 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
58771 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
58772 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
58773 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
58774 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1913:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILELT_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
58775 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PWW_B),
58776 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
58777 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58778 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58779 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
58780 GIR_RootConstrainSelectedInstOperands,
58781 // GIR_Coverage, 3113,
58782 GIR_EraseRootFromParent_Done,
58783 // Label 3389: @162244
58784 GIM_Try, /*On fail goto*//*Label 3390*/ GIMT_Encode4(162284), // Rule ID 3114 //
58785 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58786 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
58787 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
58788 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
58789 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
58790 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
58791 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1913:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILELT_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
58792 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PWW_H),
58793 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
58794 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58795 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58796 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
58797 GIR_RootConstrainSelectedInstOperands,
58798 // GIR_Coverage, 3114,
58799 GIR_EraseRootFromParent_Done,
58800 // Label 3390: @162284
58801 GIM_Try, /*On fail goto*//*Label 3391*/ GIMT_Encode4(162324), // Rule ID 3115 //
58802 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58803 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
58804 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
58805 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
58806 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
58807 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
58808 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1913:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILELT_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
58809 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PWW_S),
58810 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
58811 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58812 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58813 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
58814 GIR_RootConstrainSelectedInstOperands,
58815 // GIR_Coverage, 3115,
58816 GIR_EraseRootFromParent_Done,
58817 // Label 3391: @162324
58818 GIM_Try, /*On fail goto*//*Label 3392*/ GIMT_Encode4(162364), // Rule ID 3116 //
58819 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58820 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
58821 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
58822 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
58823 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
58824 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
58825 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1913:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILELT_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
58826 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PWW_D),
58827 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
58828 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58829 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58830 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
58831 GIR_RootConstrainSelectedInstOperands,
58832 // GIR_Coverage, 3116,
58833 GIR_EraseRootFromParent_Done,
58834 // Label 3392: @162364
58835 GIM_Try, /*On fail goto*//*Label 3393*/ GIMT_Encode4(162404), // Rule ID 3121 //
58836 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58837 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
58838 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
58839 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
58840 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
58841 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
58842 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1913:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILELT_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
58843 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PXX_B),
58844 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
58845 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58846 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58847 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
58848 GIR_RootConstrainSelectedInstOperands,
58849 // GIR_Coverage, 3121,
58850 GIR_EraseRootFromParent_Done,
58851 // Label 3393: @162404
58852 GIM_Try, /*On fail goto*//*Label 3394*/ GIMT_Encode4(162444), // Rule ID 3122 //
58853 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58854 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
58855 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
58856 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
58857 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
58858 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
58859 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1913:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILELT_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
58860 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PXX_H),
58861 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
58862 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58863 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58864 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
58865 GIR_RootConstrainSelectedInstOperands,
58866 // GIR_Coverage, 3122,
58867 GIR_EraseRootFromParent_Done,
58868 // Label 3394: @162444
58869 GIM_Try, /*On fail goto*//*Label 3395*/ GIMT_Encode4(162484), // Rule ID 3123 //
58870 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58871 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
58872 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
58873 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
58874 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
58875 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
58876 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1913:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILELT_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
58877 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PXX_S),
58878 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
58879 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58880 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58881 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
58882 GIR_RootConstrainSelectedInstOperands,
58883 // GIR_Coverage, 3123,
58884 GIR_EraseRootFromParent_Done,
58885 // Label 3395: @162484
58886 GIM_Try, /*On fail goto*//*Label 3396*/ GIMT_Encode4(162524), // Rule ID 3124 //
58887 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
58888 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
58889 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
58890 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
58891 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
58892 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
58893 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1913:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILELT_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
58894 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PXX_D),
58895 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
58896 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58897 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58898 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
58899 GIR_RootConstrainSelectedInstOperands,
58900 // GIR_Coverage, 3124,
58901 GIR_EraseRootFromParent_Done,
58902 // Label 3396: @162524
58903 GIM_Try, /*On fail goto*//*Label 3397*/ GIMT_Encode4(162561), // Rule ID 3313 //
58904 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
58905 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_compact),
58906 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
58907 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
58908 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
58909 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58910 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1157:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (COMPACT_ZPZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
58911 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::COMPACT_ZPZ_S),
58912 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58913 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58914 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58915 GIR_RootConstrainSelectedInstOperands,
58916 // GIR_Coverage, 3313,
58917 GIR_EraseRootFromParent_Done,
58918 // Label 3397: @162561
58919 GIM_Try, /*On fail goto*//*Label 3398*/ GIMT_Encode4(162598), // Rule ID 3314 //
58920 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
58921 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_compact),
58922 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
58923 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
58924 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
58925 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58926 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1157:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (COMPACT_ZPZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
58927 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::COMPACT_ZPZ_S),
58928 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58929 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58930 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58931 GIR_RootConstrainSelectedInstOperands,
58932 // GIR_Coverage, 3314,
58933 GIR_EraseRootFromParent_Done,
58934 // Label 3398: @162598
58935 GIM_Try, /*On fail goto*//*Label 3399*/ GIMT_Encode4(162635), // Rule ID 3315 //
58936 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
58937 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_compact),
58938 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
58939 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
58940 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
58941 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58942 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1157:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (COMPACT_ZPZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
58943 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::COMPACT_ZPZ_D),
58944 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58945 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58946 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58947 GIR_RootConstrainSelectedInstOperands,
58948 // GIR_Coverage, 3315,
58949 GIR_EraseRootFromParent_Done,
58950 // Label 3399: @162635
58951 GIM_Try, /*On fail goto*//*Label 3400*/ GIMT_Encode4(162672), // Rule ID 3316 //
58952 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
58953 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_compact),
58954 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
58955 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
58956 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
58957 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58958 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1157:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (COMPACT_ZPZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
58959 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::COMPACT_ZPZ_D),
58960 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58961 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58962 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58963 GIR_RootConstrainSelectedInstOperands,
58964 // GIR_Coverage, 3316,
58965 GIR_EraseRootFromParent_Done,
58966 // Label 3400: @162672
58967 GIM_Try, /*On fail goto*//*Label 3401*/ GIMT_Encode4(162709), // Rule ID 3338 //
58968 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
58969 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftssel_x),
58970 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
58971 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
58972 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
58973 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58974 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1328:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (FTSSEL_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
58975 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTSSEL_ZZZ_H),
58976 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58977 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58978 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58979 GIR_RootConstrainSelectedInstOperands,
58980 // GIR_Coverage, 3338,
58981 GIR_EraseRootFromParent_Done,
58982 // Label 3401: @162709
58983 GIM_Try, /*On fail goto*//*Label 3402*/ GIMT_Encode4(162746), // Rule ID 3339 //
58984 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
58985 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftssel_x),
58986 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
58987 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
58988 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
58989 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
58990 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1328:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (FTSSEL_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
58991 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTSSEL_ZZZ_S),
58992 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
58993 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
58994 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
58995 GIR_RootConstrainSelectedInstOperands,
58996 // GIR_Coverage, 3339,
58997 GIR_EraseRootFromParent_Done,
58998 // Label 3402: @162746
58999 GIM_Try, /*On fail goto*//*Label 3403*/ GIMT_Encode4(162783), // Rule ID 3340 //
59000 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
59001 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftssel_x),
59002 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
59003 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
59004 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
59005 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59006 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1328:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (FTSSEL_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
59007 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTSSEL_ZZZ_D),
59008 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59009 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59010 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59011 GIR_RootConstrainSelectedInstOperands,
59012 // GIR_Coverage, 3340,
59013 GIR_EraseRootFromParent_Done,
59014 // Label 3403: @162783
59015 GIM_Try, /*On fail goto*//*Label 3404*/ GIMT_Encode4(162820), // Rule ID 3362 //
59016 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59017 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brka_z),
59018 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
59019 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
59020 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
59021 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59022 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1110:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2) => (BRKA_PPzP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
59023 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKA_PPzP),
59024 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
59025 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59026 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59027 GIR_RootConstrainSelectedInstOperands,
59028 // GIR_Coverage, 3362,
59029 GIR_EraseRootFromParent_Done,
59030 // Label 3404: @162820
59031 GIM_Try, /*On fail goto*//*Label 3405*/ GIMT_Encode4(162857), // Rule ID 3367 //
59032 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2SM4),
59033 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sm4ekey),
59034 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
59035 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
59036 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
59037 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59038 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1505:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SM4EKEY_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
59039 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM4EKEY_ZZZ_S),
59040 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59041 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59042 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59043 GIR_RootConstrainSelectedInstOperands,
59044 // GIR_Coverage, 3367,
59045 GIR_EraseRootFromParent_Done,
59046 // Label 3405: @162857
59047 GIM_Try, /*On fail goto*//*Label 3406*/ GIMT_Encode4(162894), // Rule ID 3368 //
59048 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2AES),
59049 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_aese),
59050 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
59051 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
59052 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
59053 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59054 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1075:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (AESE_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
59055 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESE_ZZZ_B),
59056 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
59057 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59058 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59059 GIR_RootConstrainSelectedInstOperands,
59060 // GIR_Coverage, 3368,
59061 GIR_EraseRootFromParent_Done,
59062 // Label 3406: @162894
59063 GIM_Try, /*On fail goto*//*Label 3407*/ GIMT_Encode4(162931), // Rule ID 3381 //
59064 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
59065 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
59066 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
59067 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
59068 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
59069 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59070 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1935:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (ZIP1_ZZZ_Q:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
59071 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
59072 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59073 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59074 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59075 GIR_RootConstrainSelectedInstOperands,
59076 // GIR_Coverage, 3381,
59077 GIR_EraseRootFromParent_Done,
59078 // Label 3407: @162931
59079 GIM_Try, /*On fail goto*//*Label 3408*/ GIMT_Encode4(162968), // Rule ID 3382 //
59080 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
59081 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
59082 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
59083 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
59084 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
59085 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59086 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1935:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (ZIP1_ZZZ_Q:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
59087 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
59088 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59089 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59090 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59091 GIR_RootConstrainSelectedInstOperands,
59092 // GIR_Coverage, 3382,
59093 GIR_EraseRootFromParent_Done,
59094 // Label 3408: @162968
59095 GIM_Try, /*On fail goto*//*Label 3409*/ GIMT_Encode4(163005), // Rule ID 3383 //
59096 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
59097 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
59098 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
59099 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
59100 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
59101 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59102 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1935:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (ZIP1_ZZZ_Q:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
59103 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
59104 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59105 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59106 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59107 GIR_RootConstrainSelectedInstOperands,
59108 // GIR_Coverage, 3383,
59109 GIR_EraseRootFromParent_Done,
59110 // Label 3409: @163005
59111 GIM_Try, /*On fail goto*//*Label 3410*/ GIMT_Encode4(163042), // Rule ID 3384 //
59112 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
59113 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
59114 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
59115 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
59116 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
59117 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59118 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1935:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (ZIP1_ZZZ_Q:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
59119 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
59120 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59121 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59122 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59123 GIR_RootConstrainSelectedInstOperands,
59124 // GIR_Coverage, 3384,
59125 GIR_EraseRootFromParent_Done,
59126 // Label 3410: @163042
59127 GIM_Try, /*On fail goto*//*Label 3411*/ GIMT_Encode4(163079), // Rule ID 3385 //
59128 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
59129 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
59130 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
59131 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
59132 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
59133 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59134 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1935:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (ZIP1_ZZZ_Q:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
59135 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
59136 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59137 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59138 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59139 GIR_RootConstrainSelectedInstOperands,
59140 // GIR_Coverage, 3385,
59141 GIR_EraseRootFromParent_Done,
59142 // Label 3411: @163079
59143 GIM_Try, /*On fail goto*//*Label 3412*/ GIMT_Encode4(163116), // Rule ID 3386 //
59144 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
59145 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
59146 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
59147 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
59148 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
59149 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59150 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1935:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (ZIP1_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
59151 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
59152 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59153 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59154 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59155 GIR_RootConstrainSelectedInstOperands,
59156 // GIR_Coverage, 3386,
59157 GIR_EraseRootFromParent_Done,
59158 // Label 3412: @163116
59159 GIM_Try, /*On fail goto*//*Label 3413*/ GIMT_Encode4(163153), // Rule ID 3387 //
59160 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
59161 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
59162 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
59163 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
59164 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
59165 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59166 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1935:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (ZIP1_ZZZ_Q:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
59167 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
59168 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59169 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59170 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59171 GIR_RootConstrainSelectedInstOperands,
59172 // GIR_Coverage, 3387,
59173 GIR_EraseRootFromParent_Done,
59174 // Label 3413: @163153
59175 GIM_Try, /*On fail goto*//*Label 3414*/ GIMT_Encode4(163190), // Rule ID 3388 //
59176 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
59177 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
59178 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
59179 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
59180 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
59181 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59182 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1935:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2) => (ZIP1_ZZZ_Q:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2)
59183 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
59184 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59185 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59186 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59187 GIR_RootConstrainSelectedInstOperands,
59188 // GIR_Coverage, 3388,
59189 GIR_EraseRootFromParent_Done,
59190 // Label 3414: @163190
59191 GIM_Try, /*On fail goto*//*Label 3415*/ GIMT_Encode4(163227), // Rule ID 3448 //
59192 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59193 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_faddqv),
59194 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
59195 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
59196 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
59197 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
59198 // (intrinsic_wo_chain:{ *:[v8f16] } 1183:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (FADDQV_H:{ *:[v8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
59199 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDQV_H),
59200 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
59201 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59202 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59203 GIR_RootConstrainSelectedInstOperands,
59204 // GIR_Coverage, 3448,
59205 GIR_EraseRootFromParent_Done,
59206 // Label 3415: @163227
59207 GIM_Try, /*On fail goto*//*Label 3416*/ GIMT_Encode4(163264), // Rule ID 3449 //
59208 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59209 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_faddqv),
59210 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
59211 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
59212 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
59213 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
59214 // (intrinsic_wo_chain:{ *:[v4f32] } 1183:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (FADDQV_S:{ *:[v4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
59215 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDQV_S),
59216 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
59217 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59218 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59219 GIR_RootConstrainSelectedInstOperands,
59220 // GIR_Coverage, 3449,
59221 GIR_EraseRootFromParent_Done,
59222 // Label 3416: @163264
59223 GIM_Try, /*On fail goto*//*Label 3417*/ GIMT_Encode4(163301), // Rule ID 3450 //
59224 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59225 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_faddqv),
59226 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
59227 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
59228 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
59229 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
59230 // (intrinsic_wo_chain:{ *:[v2f64] } 1183:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (FADDQV_D:{ *:[v2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
59231 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDQV_D),
59232 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
59233 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59234 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59235 GIR_RootConstrainSelectedInstOperands,
59236 // GIR_Coverage, 3450,
59237 GIR_EraseRootFromParent_Done,
59238 // Label 3417: @163301
59239 GIM_Try, /*On fail goto*//*Label 3418*/ GIMT_Encode4(163338), // Rule ID 3482 //
59240 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59241 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orqv),
59242 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
59243 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
59244 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
59245 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
59246 // (intrinsic_wo_chain:{ *:[v16i8] } 1399:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (ORQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
59247 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORQV_VPZ_B),
59248 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
59249 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59250 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59251 GIR_RootConstrainSelectedInstOperands,
59252 // GIR_Coverage, 3482,
59253 GIR_EraseRootFromParent_Done,
59254 // Label 3418: @163338
59255 GIM_Try, /*On fail goto*//*Label 3419*/ GIMT_Encode4(163375), // Rule ID 3483 //
59256 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59257 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orqv),
59258 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
59259 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
59260 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
59261 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
59262 // (intrinsic_wo_chain:{ *:[v8i16] } 1399:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (ORQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
59263 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORQV_VPZ_H),
59264 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
59265 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59266 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59267 GIR_RootConstrainSelectedInstOperands,
59268 // GIR_Coverage, 3483,
59269 GIR_EraseRootFromParent_Done,
59270 // Label 3419: @163375
59271 GIM_Try, /*On fail goto*//*Label 3420*/ GIMT_Encode4(163412), // Rule ID 3484 //
59272 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59273 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orqv),
59274 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
59275 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
59276 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
59277 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
59278 // (intrinsic_wo_chain:{ *:[v4i32] } 1399:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (ORQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
59279 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORQV_VPZ_S),
59280 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
59281 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59282 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59283 GIR_RootConstrainSelectedInstOperands,
59284 // GIR_Coverage, 3484,
59285 GIR_EraseRootFromParent_Done,
59286 // Label 3420: @163412
59287 GIM_Try, /*On fail goto*//*Label 3421*/ GIMT_Encode4(163449), // Rule ID 3485 //
59288 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59289 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orqv),
59290 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
59291 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
59292 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
59293 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
59294 // (intrinsic_wo_chain:{ *:[v2i64] } 1399:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (ORQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
59295 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORQV_VPZ_D),
59296 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
59297 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59298 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59299 GIR_RootConstrainSelectedInstOperands,
59300 // GIR_Coverage, 3485,
59301 GIR_EraseRootFromParent_Done,
59302 // Label 3421: @163449
59303 GIM_Try, /*On fail goto*//*Label 3422*/ GIMT_Encode4(163486), // Rule ID 3486 //
59304 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59305 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
59306 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
59307 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
59308 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
59309 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59310 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1943:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (ZIPQ1_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
59311 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_B),
59312 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59313 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59314 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59315 GIR_RootConstrainSelectedInstOperands,
59316 // GIR_Coverage, 3486,
59317 GIR_EraseRootFromParent_Done,
59318 // Label 3422: @163486
59319 GIM_Try, /*On fail goto*//*Label 3423*/ GIMT_Encode4(163523), // Rule ID 3487 //
59320 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59321 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
59322 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
59323 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
59324 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
59325 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59326 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1943:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (ZIPQ1_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
59327 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_H),
59328 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59329 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59330 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59331 GIR_RootConstrainSelectedInstOperands,
59332 // GIR_Coverage, 3487,
59333 GIR_EraseRootFromParent_Done,
59334 // Label 3423: @163523
59335 GIM_Try, /*On fail goto*//*Label 3424*/ GIMT_Encode4(163560), // Rule ID 3488 //
59336 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59337 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
59338 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
59339 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
59340 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
59341 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59342 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1943:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (ZIPQ1_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
59343 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_S),
59344 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59345 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59346 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59347 GIR_RootConstrainSelectedInstOperands,
59348 // GIR_Coverage, 3488,
59349 GIR_EraseRootFromParent_Done,
59350 // Label 3424: @163560
59351 GIM_Try, /*On fail goto*//*Label 3425*/ GIMT_Encode4(163597), // Rule ID 3489 //
59352 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59353 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
59354 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
59355 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
59356 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
59357 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59358 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1943:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (ZIPQ1_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
59359 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_D),
59360 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59361 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59362 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59363 GIR_RootConstrainSelectedInstOperands,
59364 // GIR_Coverage, 3489,
59365 GIR_EraseRootFromParent_Done,
59366 // Label 3425: @163597
59367 GIM_Try, /*On fail goto*//*Label 3426*/ GIMT_Encode4(163634), // Rule ID 3490 //
59368 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59369 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
59370 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
59371 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
59372 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
59373 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59374 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1943:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (ZIPQ1_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
59375 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_H),
59376 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59377 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59378 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59379 GIR_RootConstrainSelectedInstOperands,
59380 // GIR_Coverage, 3490,
59381 GIR_EraseRootFromParent_Done,
59382 // Label 3426: @163634
59383 GIM_Try, /*On fail goto*//*Label 3427*/ GIMT_Encode4(163671), // Rule ID 3491 //
59384 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59385 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
59386 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
59387 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
59388 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
59389 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59390 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1943:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (ZIPQ1_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
59391 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_S),
59392 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59393 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59394 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59395 GIR_RootConstrainSelectedInstOperands,
59396 // GIR_Coverage, 3491,
59397 GIR_EraseRootFromParent_Done,
59398 // Label 3427: @163671
59399 GIM_Try, /*On fail goto*//*Label 3428*/ GIMT_Encode4(163708), // Rule ID 3492 //
59400 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59401 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
59402 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
59403 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
59404 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
59405 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59406 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1943:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (ZIPQ1_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
59407 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_D),
59408 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59409 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59410 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59411 GIR_RootConstrainSelectedInstOperands,
59412 // GIR_Coverage, 3492,
59413 GIR_EraseRootFromParent_Done,
59414 // Label 3428: @163708
59415 GIM_Try, /*On fail goto*//*Label 3429*/ GIMT_Encode4(163745), // Rule ID 3493 //
59416 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59417 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
59418 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
59419 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
59420 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
59421 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59422 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1943:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2) => (ZIPQ1_ZZZ_H:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2)
59423 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_H),
59424 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59425 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59426 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59427 GIR_RootConstrainSelectedInstOperands,
59428 // GIR_Coverage, 3493,
59429 GIR_EraseRootFromParent_Done,
59430 // Label 3429: @163745
59431 GIM_Try, /*On fail goto*//*Label 3430*/ GIMT_Encode4(163782), // Rule ID 3494 //
59432 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59433 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
59434 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
59435 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
59436 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
59437 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59438 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1698:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (TBLQ_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
59439 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_B),
59440 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59441 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59442 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59443 GIR_RootConstrainSelectedInstOperands,
59444 // GIR_Coverage, 3494,
59445 GIR_EraseRootFromParent_Done,
59446 // Label 3430: @163782
59447 GIM_Try, /*On fail goto*//*Label 3431*/ GIMT_Encode4(163819), // Rule ID 3495 //
59448 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59449 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
59450 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
59451 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
59452 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
59453 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59454 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1698:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (TBLQ_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
59455 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_H),
59456 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59457 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59458 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59459 GIR_RootConstrainSelectedInstOperands,
59460 // GIR_Coverage, 3495,
59461 GIR_EraseRootFromParent_Done,
59462 // Label 3431: @163819
59463 GIM_Try, /*On fail goto*//*Label 3432*/ GIMT_Encode4(163856), // Rule ID 3496 //
59464 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59465 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
59466 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
59467 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
59468 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
59469 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59470 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1698:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (TBLQ_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
59471 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_S),
59472 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59473 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59474 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59475 GIR_RootConstrainSelectedInstOperands,
59476 // GIR_Coverage, 3496,
59477 GIR_EraseRootFromParent_Done,
59478 // Label 3432: @163856
59479 GIM_Try, /*On fail goto*//*Label 3433*/ GIMT_Encode4(163893), // Rule ID 3497 //
59480 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59481 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
59482 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
59483 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
59484 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
59485 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59486 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1698:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (TBLQ_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
59487 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_D),
59488 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59489 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59490 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59491 GIR_RootConstrainSelectedInstOperands,
59492 // GIR_Coverage, 3497,
59493 GIR_EraseRootFromParent_Done,
59494 // Label 3433: @163893
59495 GIM_Try, /*On fail goto*//*Label 3434*/ GIMT_Encode4(163930), // Rule ID 3498 //
59496 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59497 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
59498 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
59499 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
59500 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
59501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59502 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1698:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (TBLQ_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
59503 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_H),
59504 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59505 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59506 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59507 GIR_RootConstrainSelectedInstOperands,
59508 // GIR_Coverage, 3498,
59509 GIR_EraseRootFromParent_Done,
59510 // Label 3434: @163930
59511 GIM_Try, /*On fail goto*//*Label 3435*/ GIMT_Encode4(163967), // Rule ID 3499 //
59512 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59513 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
59514 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
59515 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
59516 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
59517 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59518 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1698:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (TBLQ_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
59519 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_S),
59520 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59521 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59522 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59523 GIR_RootConstrainSelectedInstOperands,
59524 // GIR_Coverage, 3499,
59525 GIR_EraseRootFromParent_Done,
59526 // Label 3435: @163967
59527 GIM_Try, /*On fail goto*//*Label 3436*/ GIMT_Encode4(164004), // Rule ID 3500 //
59528 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59529 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
59530 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
59531 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
59532 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
59533 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59534 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1698:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (TBLQ_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
59535 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_D),
59536 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59537 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59538 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59539 GIR_RootConstrainSelectedInstOperands,
59540 // GIR_Coverage, 3500,
59541 GIR_EraseRootFromParent_Done,
59542 // Label 3436: @164004
59543 GIM_Try, /*On fail goto*//*Label 3437*/ GIMT_Encode4(164041), // Rule ID 3501 //
59544 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
59545 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
59546 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
59547 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
59548 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
59549 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59550 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1698:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (TBLQ_ZZZ_H:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
59551 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_H),
59552 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59553 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59554 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59555 GIR_RootConstrainSelectedInstOperands,
59556 // GIR_Coverage, 3501,
59557 GIR_EraseRootFromParent_Done,
59558 // Label 3437: @164041
59559 GIM_Try, /*On fail goto*//*Label 3438*/ GIMT_Encode4(164078), // Rule ID 8057 //
59560 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59561 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brkb_z),
59562 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
59563 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
59564 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
59565 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59566 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1112:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2) => (BRKB_PPzP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
59567 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKB_PPzP),
59568 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
59569 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59570 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59571 GIR_RootConstrainSelectedInstOperands,
59572 // GIR_Coverage, 8057,
59573 GIR_EraseRootFromParent_Done,
59574 // Label 3438: @164078
59575 GIM_Try, /*On fail goto*//*Label 3439*/ GIMT_Encode4(164115), // Rule ID 8558 //
59576 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
59577 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrb),
59578 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
59579 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
59580 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
59581 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59582 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1070:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (ADR_LSL_ZZZ_S_0:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
59583 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_S_0),
59584 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59585 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59586 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59587 GIR_RootConstrainSelectedInstOperands,
59588 // GIR_Coverage, 8558,
59589 GIR_EraseRootFromParent_Done,
59590 // Label 3439: @164115
59591 GIM_Try, /*On fail goto*//*Label 3440*/ GIMT_Encode4(164152), // Rule ID 8559 //
59592 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
59593 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrh),
59594 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
59595 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
59596 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
59597 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59598 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1072:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (ADR_LSL_ZZZ_S_1:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
59599 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_S_1),
59600 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59601 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59602 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59603 GIR_RootConstrainSelectedInstOperands,
59604 // GIR_Coverage, 8559,
59605 GIR_EraseRootFromParent_Done,
59606 // Label 3440: @164152
59607 GIM_Try, /*On fail goto*//*Label 3441*/ GIMT_Encode4(164189), // Rule ID 8560 //
59608 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
59609 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrw),
59610 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
59611 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
59612 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
59613 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59614 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1073:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (ADR_LSL_ZZZ_S_2:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
59615 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_S_2),
59616 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59617 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59618 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59619 GIR_RootConstrainSelectedInstOperands,
59620 // GIR_Coverage, 8560,
59621 GIR_EraseRootFromParent_Done,
59622 // Label 3441: @164189
59623 GIM_Try, /*On fail goto*//*Label 3442*/ GIMT_Encode4(164226), // Rule ID 8561 //
59624 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
59625 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrd),
59626 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
59627 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
59628 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
59629 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59630 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1071:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (ADR_LSL_ZZZ_S_3:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
59631 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_S_3),
59632 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59633 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59634 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59635 GIR_RootConstrainSelectedInstOperands,
59636 // GIR_Coverage, 8561,
59637 GIR_EraseRootFromParent_Done,
59638 // Label 3442: @164226
59639 GIM_Try, /*On fail goto*//*Label 3443*/ GIMT_Encode4(164263), // Rule ID 8562 //
59640 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
59641 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrb),
59642 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
59643 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
59644 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
59645 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59646 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1070:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (ADR_LSL_ZZZ_D_0:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
59647 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_D_0),
59648 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59649 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59650 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59651 GIR_RootConstrainSelectedInstOperands,
59652 // GIR_Coverage, 8562,
59653 GIR_EraseRootFromParent_Done,
59654 // Label 3443: @164263
59655 GIM_Try, /*On fail goto*//*Label 3444*/ GIMT_Encode4(164300), // Rule ID 8563 //
59656 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
59657 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrh),
59658 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
59659 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
59660 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
59661 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59662 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1072:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (ADR_LSL_ZZZ_D_1:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
59663 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_D_1),
59664 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59665 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59666 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59667 GIR_RootConstrainSelectedInstOperands,
59668 // GIR_Coverage, 8563,
59669 GIR_EraseRootFromParent_Done,
59670 // Label 3444: @164300
59671 GIM_Try, /*On fail goto*//*Label 3445*/ GIMT_Encode4(164337), // Rule ID 8564 //
59672 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
59673 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrw),
59674 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
59675 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
59676 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
59677 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59678 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1073:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (ADR_LSL_ZZZ_D_2:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
59679 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_D_2),
59680 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59681 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59682 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59683 GIR_RootConstrainSelectedInstOperands,
59684 // GIR_Coverage, 8564,
59685 GIR_EraseRootFromParent_Done,
59686 // Label 3445: @164337
59687 GIM_Try, /*On fail goto*//*Label 3446*/ GIMT_Encode4(164374), // Rule ID 8565 //
59688 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
59689 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrd),
59690 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
59691 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
59692 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
59693 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
59694 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1071:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (ADR_LSL_ZZZ_D_3:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
59695 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_D_3),
59696 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
59697 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59698 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59699 GIR_RootConstrainSelectedInstOperands,
59700 // GIR_Coverage, 8565,
59701 GIR_EraseRootFromParent_Done,
59702 // Label 3446: @164374
59703 GIM_Try, /*On fail goto*//*Label 3447*/ GIMT_Encode4(164414), // Rule ID 9577 //
59704 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59705 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
59706 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
59707 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
59708 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
59709 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59710 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1895:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILELE_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
59711 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PWW_B),
59712 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
59713 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59714 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59715 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
59716 GIR_RootConstrainSelectedInstOperands,
59717 // GIR_Coverage, 9577,
59718 GIR_EraseRootFromParent_Done,
59719 // Label 3447: @164414
59720 GIM_Try, /*On fail goto*//*Label 3448*/ GIMT_Encode4(164454), // Rule ID 9578 //
59721 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59722 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
59723 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
59724 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
59725 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
59726 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59727 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1895:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILELE_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
59728 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PWW_H),
59729 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
59730 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59731 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59732 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
59733 GIR_RootConstrainSelectedInstOperands,
59734 // GIR_Coverage, 9578,
59735 GIR_EraseRootFromParent_Done,
59736 // Label 3448: @164454
59737 GIM_Try, /*On fail goto*//*Label 3449*/ GIMT_Encode4(164494), // Rule ID 9579 //
59738 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59739 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
59740 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
59741 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
59742 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
59743 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59744 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1895:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILELE_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
59745 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PWW_S),
59746 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
59747 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59748 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59749 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
59750 GIR_RootConstrainSelectedInstOperands,
59751 // GIR_Coverage, 9579,
59752 GIR_EraseRootFromParent_Done,
59753 // Label 3449: @164494
59754 GIM_Try, /*On fail goto*//*Label 3450*/ GIMT_Encode4(164534), // Rule ID 9580 //
59755 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59756 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
59757 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
59758 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
59759 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
59760 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59761 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1895:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILELE_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
59762 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PWW_D),
59763 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
59764 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59765 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59766 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
59767 GIR_RootConstrainSelectedInstOperands,
59768 // GIR_Coverage, 9580,
59769 GIR_EraseRootFromParent_Done,
59770 // Label 3450: @164534
59771 GIM_Try, /*On fail goto*//*Label 3451*/ GIMT_Encode4(164574), // Rule ID 9581 //
59772 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59773 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelo),
59774 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
59775 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
59776 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
59777 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59778 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1901:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILELO_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
59779 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELO_PWW_B),
59780 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
59781 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59782 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59783 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
59784 GIR_RootConstrainSelectedInstOperands,
59785 // GIR_Coverage, 9581,
59786 GIR_EraseRootFromParent_Done,
59787 // Label 3451: @164574
59788 GIM_Try, /*On fail goto*//*Label 3452*/ GIMT_Encode4(164614), // Rule ID 9582 //
59789 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59790 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelo),
59791 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
59792 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
59793 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
59794 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59795 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1901:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILELO_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
59796 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELO_PWW_H),
59797 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
59798 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59799 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59800 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
59801 GIR_RootConstrainSelectedInstOperands,
59802 // GIR_Coverage, 9582,
59803 GIR_EraseRootFromParent_Done,
59804 // Label 3452: @164614
59805 GIM_Try, /*On fail goto*//*Label 3453*/ GIMT_Encode4(164654), // Rule ID 9583 //
59806 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59807 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelo),
59808 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
59809 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
59810 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
59811 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59812 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1901:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILELO_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
59813 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELO_PWW_S),
59814 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
59815 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59816 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59817 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
59818 GIR_RootConstrainSelectedInstOperands,
59819 // GIR_Coverage, 9583,
59820 GIR_EraseRootFromParent_Done,
59821 // Label 3453: @164654
59822 GIM_Try, /*On fail goto*//*Label 3454*/ GIMT_Encode4(164694), // Rule ID 9584 //
59823 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59824 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelo),
59825 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
59826 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
59827 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
59828 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59829 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1901:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILELO_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
59830 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELO_PWW_D),
59831 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
59832 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59833 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59834 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
59835 GIR_RootConstrainSelectedInstOperands,
59836 // GIR_Coverage, 9584,
59837 GIR_EraseRootFromParent_Done,
59838 // Label 3454: @164694
59839 GIM_Try, /*On fail goto*//*Label 3455*/ GIMT_Encode4(164734), // Rule ID 9589 //
59840 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59841 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
59842 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
59843 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
59844 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
59845 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59846 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1907:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILELS_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
59847 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PWW_B),
59848 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
59849 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59850 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59851 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
59852 GIR_RootConstrainSelectedInstOperands,
59853 // GIR_Coverage, 9589,
59854 GIR_EraseRootFromParent_Done,
59855 // Label 3455: @164734
59856 GIM_Try, /*On fail goto*//*Label 3456*/ GIMT_Encode4(164774), // Rule ID 9590 //
59857 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59858 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
59859 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
59860 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
59861 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
59862 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59863 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1907:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILELS_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
59864 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PWW_H),
59865 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
59866 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59867 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59868 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
59869 GIR_RootConstrainSelectedInstOperands,
59870 // GIR_Coverage, 9590,
59871 GIR_EraseRootFromParent_Done,
59872 // Label 3456: @164774
59873 GIM_Try, /*On fail goto*//*Label 3457*/ GIMT_Encode4(164814), // Rule ID 9591 //
59874 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59875 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
59876 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
59877 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
59878 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
59879 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59880 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1907:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILELS_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
59881 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PWW_S),
59882 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
59883 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59884 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59885 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
59886 GIR_RootConstrainSelectedInstOperands,
59887 // GIR_Coverage, 9591,
59888 GIR_EraseRootFromParent_Done,
59889 // Label 3457: @164814
59890 GIM_Try, /*On fail goto*//*Label 3458*/ GIMT_Encode4(164854), // Rule ID 9592 //
59891 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59892 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
59893 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
59894 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
59895 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
59896 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59897 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1907:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILELS_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
59898 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PWW_D),
59899 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
59900 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59901 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59902 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
59903 GIR_RootConstrainSelectedInstOperands,
59904 // GIR_Coverage, 9592,
59905 GIR_EraseRootFromParent_Done,
59906 // Label 3458: @164854
59907 GIM_Try, /*On fail goto*//*Label 3459*/ GIMT_Encode4(164894), // Rule ID 9593 //
59908 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59909 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
59910 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
59911 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
59912 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
59913 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59914 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1895:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILELE_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
59915 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PXX_B),
59916 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
59917 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59918 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59919 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
59920 GIR_RootConstrainSelectedInstOperands,
59921 // GIR_Coverage, 9593,
59922 GIR_EraseRootFromParent_Done,
59923 // Label 3459: @164894
59924 GIM_Try, /*On fail goto*//*Label 3460*/ GIMT_Encode4(164934), // Rule ID 9594 //
59925 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59926 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
59927 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
59928 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
59929 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
59930 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59931 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1895:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILELE_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
59932 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PXX_H),
59933 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
59934 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59935 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59936 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
59937 GIR_RootConstrainSelectedInstOperands,
59938 // GIR_Coverage, 9594,
59939 GIR_EraseRootFromParent_Done,
59940 // Label 3460: @164934
59941 GIM_Try, /*On fail goto*//*Label 3461*/ GIMT_Encode4(164974), // Rule ID 9595 //
59942 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59943 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
59944 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
59945 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
59946 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
59947 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59948 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1895:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILELE_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
59949 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PXX_S),
59950 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
59951 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59952 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59953 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
59954 GIR_RootConstrainSelectedInstOperands,
59955 // GIR_Coverage, 9595,
59956 GIR_EraseRootFromParent_Done,
59957 // Label 3461: @164974
59958 GIM_Try, /*On fail goto*//*Label 3462*/ GIMT_Encode4(165014), // Rule ID 9596 //
59959 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59960 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
59961 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
59962 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
59963 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
59964 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59965 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1895:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILELE_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
59966 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PXX_D),
59967 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
59968 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59969 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59970 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
59971 GIR_RootConstrainSelectedInstOperands,
59972 // GIR_Coverage, 9596,
59973 GIR_EraseRootFromParent_Done,
59974 // Label 3462: @165014
59975 GIM_Try, /*On fail goto*//*Label 3463*/ GIMT_Encode4(165054), // Rule ID 9597 //
59976 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59977 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelo),
59978 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
59979 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
59980 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
59981 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59982 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1901:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILELO_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
59983 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELO_PXX_B),
59984 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
59985 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
59986 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
59987 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
59988 GIR_RootConstrainSelectedInstOperands,
59989 // GIR_Coverage, 9597,
59990 GIR_EraseRootFromParent_Done,
59991 // Label 3463: @165054
59992 GIM_Try, /*On fail goto*//*Label 3464*/ GIMT_Encode4(165094), // Rule ID 9598 //
59993 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
59994 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelo),
59995 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
59996 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
59997 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
59998 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
59999 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1901:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILELO_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
60000 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELO_PXX_H),
60001 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
60002 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60003 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60004 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
60005 GIR_RootConstrainSelectedInstOperands,
60006 // GIR_Coverage, 9598,
60007 GIR_EraseRootFromParent_Done,
60008 // Label 3464: @165094
60009 GIM_Try, /*On fail goto*//*Label 3465*/ GIMT_Encode4(165134), // Rule ID 9599 //
60010 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
60011 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelo),
60012 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
60013 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
60014 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
60015 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
60016 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1901:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILELO_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
60017 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELO_PXX_S),
60018 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
60019 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60020 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60021 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
60022 GIR_RootConstrainSelectedInstOperands,
60023 // GIR_Coverage, 9599,
60024 GIR_EraseRootFromParent_Done,
60025 // Label 3465: @165134
60026 GIM_Try, /*On fail goto*//*Label 3466*/ GIMT_Encode4(165174), // Rule ID 9600 //
60027 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
60028 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelo),
60029 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
60030 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
60031 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
60032 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
60033 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1901:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILELO_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
60034 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELO_PXX_D),
60035 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
60036 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60037 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60038 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
60039 GIR_RootConstrainSelectedInstOperands,
60040 // GIR_Coverage, 9600,
60041 GIR_EraseRootFromParent_Done,
60042 // Label 3466: @165174
60043 GIM_Try, /*On fail goto*//*Label 3467*/ GIMT_Encode4(165214), // Rule ID 9605 //
60044 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
60045 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
60046 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
60047 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
60048 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
60049 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
60050 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1907:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILELS_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
60051 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_B),
60052 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
60053 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60054 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60055 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
60056 GIR_RootConstrainSelectedInstOperands,
60057 // GIR_Coverage, 9605,
60058 GIR_EraseRootFromParent_Done,
60059 // Label 3467: @165214
60060 GIM_Try, /*On fail goto*//*Label 3468*/ GIMT_Encode4(165254), // Rule ID 9606 //
60061 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
60062 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
60063 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
60064 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
60065 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
60066 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
60067 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1907:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILELS_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
60068 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_H),
60069 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
60070 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60071 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60072 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
60073 GIR_RootConstrainSelectedInstOperands,
60074 // GIR_Coverage, 9606,
60075 GIR_EraseRootFromParent_Done,
60076 // Label 3468: @165254
60077 GIM_Try, /*On fail goto*//*Label 3469*/ GIMT_Encode4(165294), // Rule ID 9607 //
60078 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
60079 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
60080 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
60081 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
60082 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
60083 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
60084 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1907:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILELS_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
60085 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_S),
60086 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
60087 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60088 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60089 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
60090 GIR_RootConstrainSelectedInstOperands,
60091 // GIR_Coverage, 9607,
60092 GIR_EraseRootFromParent_Done,
60093 // Label 3469: @165294
60094 GIM_Try, /*On fail goto*//*Label 3470*/ GIMT_Encode4(165334), // Rule ID 9608 //
60095 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
60096 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
60097 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
60098 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
60099 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
60100 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
60101 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1907:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILELS_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
60102 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_D),
60103 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
60104 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60105 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60106 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
60107 GIR_RootConstrainSelectedInstOperands,
60108 // GIR_Coverage, 9608,
60109 GIR_EraseRootFromParent_Done,
60110 // Label 3470: @165334
60111 GIM_Try, /*On fail goto*//*Label 3471*/ GIMT_Encode4(165371), // Rule ID 9767 //
60112 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
60113 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp),
60114 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60115 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60116 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
60117 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60118 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1805:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2) => (UQINCP_ZP_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
60119 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_ZP_H),
60120 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
60121 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60122 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60123 GIR_RootConstrainSelectedInstOperands,
60124 // GIR_Coverage, 9767,
60125 GIR_EraseRootFromParent_Done,
60126 // Label 3471: @165371
60127 GIM_Try, /*On fail goto*//*Label 3472*/ GIMT_Encode4(165408), // Rule ID 9768 //
60128 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
60129 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp),
60130 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
60131 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
60132 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
60133 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60134 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1805:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2) => (UQINCP_ZP_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
60135 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_ZP_S),
60136 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
60137 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60138 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60139 GIR_RootConstrainSelectedInstOperands,
60140 // GIR_Coverage, 9768,
60141 GIR_EraseRootFromParent_Done,
60142 // Label 3472: @165408
60143 GIM_Try, /*On fail goto*//*Label 3473*/ GIMT_Encode4(165445), // Rule ID 9769 //
60144 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
60145 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp),
60146 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
60147 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
60148 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
60149 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60150 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1805:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2) => (UQINCP_ZP_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
60151 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_ZP_D),
60152 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
60153 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60154 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60155 GIR_RootConstrainSelectedInstOperands,
60156 // GIR_Coverage, 9769,
60157 GIR_EraseRootFromParent_Done,
60158 // Label 3473: @165445
60159 GIM_Try, /*On fail goto*//*Label 3474*/ GIMT_Encode4(165482), // Rule ID 9770 //
60160 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
60161 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp),
60162 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60163 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60164 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
60165 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60166 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1560:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2) => (SQDECP_ZP_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
60167 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_ZP_H),
60168 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
60169 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60170 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60171 GIR_RootConstrainSelectedInstOperands,
60172 // GIR_Coverage, 9770,
60173 GIR_EraseRootFromParent_Done,
60174 // Label 3474: @165482
60175 GIM_Try, /*On fail goto*//*Label 3475*/ GIMT_Encode4(165519), // Rule ID 9771 //
60176 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
60177 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp),
60178 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
60179 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
60180 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
60181 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60182 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1560:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2) => (SQDECP_ZP_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
60183 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_ZP_S),
60184 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
60185 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60186 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60187 GIR_RootConstrainSelectedInstOperands,
60188 // GIR_Coverage, 9771,
60189 GIR_EraseRootFromParent_Done,
60190 // Label 3475: @165519
60191 GIM_Try, /*On fail goto*//*Label 3476*/ GIMT_Encode4(165556), // Rule ID 9772 //
60192 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
60193 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp),
60194 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
60195 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
60196 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
60197 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60198 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1560:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2) => (SQDECP_ZP_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
60199 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_ZP_D),
60200 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
60201 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60202 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60203 GIR_RootConstrainSelectedInstOperands,
60204 // GIR_Coverage, 9772,
60205 GIR_EraseRootFromParent_Done,
60206 // Label 3476: @165556
60207 GIM_Try, /*On fail goto*//*Label 3477*/ GIMT_Encode4(165593), // Rule ID 9773 //
60208 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
60209 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp),
60210 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60211 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60212 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
60213 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60214 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1791:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2) => (UQDECP_ZP_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
60215 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_ZP_H),
60216 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
60217 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60218 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60219 GIR_RootConstrainSelectedInstOperands,
60220 // GIR_Coverage, 9773,
60221 GIR_EraseRootFromParent_Done,
60222 // Label 3477: @165593
60223 GIM_Try, /*On fail goto*//*Label 3478*/ GIMT_Encode4(165630), // Rule ID 9774 //
60224 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
60225 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp),
60226 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
60227 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
60228 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
60229 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60230 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1791:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2) => (UQDECP_ZP_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
60231 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_ZP_S),
60232 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
60233 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60234 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60235 GIR_RootConstrainSelectedInstOperands,
60236 // GIR_Coverage, 9774,
60237 GIR_EraseRootFromParent_Done,
60238 // Label 3478: @165630
60239 GIM_Try, /*On fail goto*//*Label 3479*/ GIMT_Encode4(165667), // Rule ID 9775 //
60240 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
60241 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp),
60242 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
60243 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
60244 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
60245 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60246 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1791:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2) => (UQDECP_ZP_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
60247 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_ZP_D),
60248 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
60249 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60250 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60251 GIR_RootConstrainSelectedInstOperands,
60252 // GIR_Coverage, 9775,
60253 GIR_EraseRootFromParent_Done,
60254 // Label 3479: @165667
60255 GIM_Try, /*On fail goto*//*Label 3480*/ GIMT_Encode4(165704), // Rule ID 10930 //
60256 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60257 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
60258 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
60259 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
60260 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
60261 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60262 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1940:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (ZIP2_ZZZ_Q:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
60263 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
60264 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60265 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60266 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60267 GIR_RootConstrainSelectedInstOperands,
60268 // GIR_Coverage, 10930,
60269 GIR_EraseRootFromParent_Done,
60270 // Label 3480: @165704
60271 GIM_Try, /*On fail goto*//*Label 3481*/ GIMT_Encode4(165741), // Rule ID 10931 //
60272 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60273 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
60274 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60275 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60276 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
60277 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60278 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1940:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (ZIP2_ZZZ_Q:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
60279 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
60280 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60281 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60282 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60283 GIR_RootConstrainSelectedInstOperands,
60284 // GIR_Coverage, 10931,
60285 GIR_EraseRootFromParent_Done,
60286 // Label 3481: @165741
60287 GIM_Try, /*On fail goto*//*Label 3482*/ GIMT_Encode4(165778), // Rule ID 10932 //
60288 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60289 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
60290 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60291 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60292 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
60293 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60294 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1940:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (ZIP2_ZZZ_Q:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
60295 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
60296 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60297 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60298 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60299 GIR_RootConstrainSelectedInstOperands,
60300 // GIR_Coverage, 10932,
60301 GIR_EraseRootFromParent_Done,
60302 // Label 3482: @165778
60303 GIM_Try, /*On fail goto*//*Label 3483*/ GIMT_Encode4(165815), // Rule ID 10933 //
60304 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60305 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
60306 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
60307 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
60308 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
60309 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60310 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1940:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (ZIP2_ZZZ_Q:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
60311 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
60312 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60313 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60314 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60315 GIR_RootConstrainSelectedInstOperands,
60316 // GIR_Coverage, 10933,
60317 GIR_EraseRootFromParent_Done,
60318 // Label 3483: @165815
60319 GIM_Try, /*On fail goto*//*Label 3484*/ GIMT_Encode4(165852), // Rule ID 10934 //
60320 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60321 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
60322 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
60323 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
60324 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
60325 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60326 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1940:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (ZIP2_ZZZ_Q:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
60327 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
60328 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60329 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60330 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60331 GIR_RootConstrainSelectedInstOperands,
60332 // GIR_Coverage, 10934,
60333 GIR_EraseRootFromParent_Done,
60334 // Label 3484: @165852
60335 GIM_Try, /*On fail goto*//*Label 3485*/ GIMT_Encode4(165889), // Rule ID 10935 //
60336 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60337 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
60338 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
60339 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
60340 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
60341 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60342 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1940:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (ZIP2_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
60343 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
60344 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60345 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60346 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60347 GIR_RootConstrainSelectedInstOperands,
60348 // GIR_Coverage, 10935,
60349 GIR_EraseRootFromParent_Done,
60350 // Label 3485: @165889
60351 GIM_Try, /*On fail goto*//*Label 3486*/ GIMT_Encode4(165926), // Rule ID 10936 //
60352 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60353 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
60354 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
60355 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
60356 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
60357 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60358 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1940:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (ZIP2_ZZZ_Q:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
60359 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
60360 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60361 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60362 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60363 GIR_RootConstrainSelectedInstOperands,
60364 // GIR_Coverage, 10936,
60365 GIR_EraseRootFromParent_Done,
60366 // Label 3486: @165926
60367 GIM_Try, /*On fail goto*//*Label 3487*/ GIMT_Encode4(165963), // Rule ID 10937 //
60368 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60369 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
60370 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60371 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60372 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
60373 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60374 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1940:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2) => (ZIP2_ZZZ_Q:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2)
60375 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
60376 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60377 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60378 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60379 GIR_RootConstrainSelectedInstOperands,
60380 // GIR_Coverage, 10937,
60381 GIR_EraseRootFromParent_Done,
60382 // Label 3487: @165963
60383 GIM_Try, /*On fail goto*//*Label 3488*/ GIMT_Encode4(166000), // Rule ID 10938 //
60384 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60385 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
60386 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
60387 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
60388 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
60389 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60390 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1861:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (UZP1_ZZZ_Q:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
60391 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
60392 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60393 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60394 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60395 GIR_RootConstrainSelectedInstOperands,
60396 // GIR_Coverage, 10938,
60397 GIR_EraseRootFromParent_Done,
60398 // Label 3488: @166000
60399 GIM_Try, /*On fail goto*//*Label 3489*/ GIMT_Encode4(166037), // Rule ID 10939 //
60400 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60401 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
60402 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60403 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60404 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
60405 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60406 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1861:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (UZP1_ZZZ_Q:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
60407 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
60408 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60409 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60410 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60411 GIR_RootConstrainSelectedInstOperands,
60412 // GIR_Coverage, 10939,
60413 GIR_EraseRootFromParent_Done,
60414 // Label 3489: @166037
60415 GIM_Try, /*On fail goto*//*Label 3490*/ GIMT_Encode4(166074), // Rule ID 10940 //
60416 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60417 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
60418 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60419 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60420 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
60421 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60422 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1861:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (UZP1_ZZZ_Q:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
60423 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
60424 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60425 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60426 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60427 GIR_RootConstrainSelectedInstOperands,
60428 // GIR_Coverage, 10940,
60429 GIR_EraseRootFromParent_Done,
60430 // Label 3490: @166074
60431 GIM_Try, /*On fail goto*//*Label 3491*/ GIMT_Encode4(166111), // Rule ID 10941 //
60432 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60433 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
60434 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
60435 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
60436 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
60437 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60438 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1861:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (UZP1_ZZZ_Q:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
60439 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
60440 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60441 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60442 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60443 GIR_RootConstrainSelectedInstOperands,
60444 // GIR_Coverage, 10941,
60445 GIR_EraseRootFromParent_Done,
60446 // Label 3491: @166111
60447 GIM_Try, /*On fail goto*//*Label 3492*/ GIMT_Encode4(166148), // Rule ID 10942 //
60448 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60449 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
60450 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
60451 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
60452 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
60453 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60454 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1861:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (UZP1_ZZZ_Q:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
60455 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
60456 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60457 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60458 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60459 GIR_RootConstrainSelectedInstOperands,
60460 // GIR_Coverage, 10942,
60461 GIR_EraseRootFromParent_Done,
60462 // Label 3492: @166148
60463 GIM_Try, /*On fail goto*//*Label 3493*/ GIMT_Encode4(166185), // Rule ID 10943 //
60464 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60465 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
60466 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
60467 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
60468 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
60469 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60470 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1861:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (UZP1_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
60471 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
60472 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60473 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60474 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60475 GIR_RootConstrainSelectedInstOperands,
60476 // GIR_Coverage, 10943,
60477 GIR_EraseRootFromParent_Done,
60478 // Label 3493: @166185
60479 GIM_Try, /*On fail goto*//*Label 3494*/ GIMT_Encode4(166222), // Rule ID 10944 //
60480 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60481 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
60482 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
60483 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
60484 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
60485 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60486 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1861:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (UZP1_ZZZ_Q:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
60487 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
60488 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60489 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60490 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60491 GIR_RootConstrainSelectedInstOperands,
60492 // GIR_Coverage, 10944,
60493 GIR_EraseRootFromParent_Done,
60494 // Label 3494: @166222
60495 GIM_Try, /*On fail goto*//*Label 3495*/ GIMT_Encode4(166259), // Rule ID 10945 //
60496 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60497 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
60498 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60499 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60500 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
60501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60502 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1861:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2) => (UZP1_ZZZ_Q:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2)
60503 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
60504 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60505 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60506 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60507 GIR_RootConstrainSelectedInstOperands,
60508 // GIR_Coverage, 10945,
60509 GIR_EraseRootFromParent_Done,
60510 // Label 3495: @166259
60511 GIM_Try, /*On fail goto*//*Label 3496*/ GIMT_Encode4(166296), // Rule ID 10946 //
60512 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60513 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
60514 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
60515 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
60516 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
60517 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60518 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1866:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (UZP2_ZZZ_Q:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
60519 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
60520 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60521 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60522 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60523 GIR_RootConstrainSelectedInstOperands,
60524 // GIR_Coverage, 10946,
60525 GIR_EraseRootFromParent_Done,
60526 // Label 3496: @166296
60527 GIM_Try, /*On fail goto*//*Label 3497*/ GIMT_Encode4(166333), // Rule ID 10947 //
60528 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60529 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
60530 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60531 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60532 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
60533 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60534 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1866:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (UZP2_ZZZ_Q:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
60535 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
60536 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60537 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60538 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60539 GIR_RootConstrainSelectedInstOperands,
60540 // GIR_Coverage, 10947,
60541 GIR_EraseRootFromParent_Done,
60542 // Label 3497: @166333
60543 GIM_Try, /*On fail goto*//*Label 3498*/ GIMT_Encode4(166370), // Rule ID 10948 //
60544 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60545 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
60546 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60547 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60548 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
60549 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60550 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1866:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (UZP2_ZZZ_Q:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
60551 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
60552 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60553 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60554 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60555 GIR_RootConstrainSelectedInstOperands,
60556 // GIR_Coverage, 10948,
60557 GIR_EraseRootFromParent_Done,
60558 // Label 3498: @166370
60559 GIM_Try, /*On fail goto*//*Label 3499*/ GIMT_Encode4(166407), // Rule ID 10949 //
60560 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60561 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
60562 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
60563 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
60564 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
60565 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60566 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1866:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (UZP2_ZZZ_Q:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
60567 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
60568 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60569 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60570 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60571 GIR_RootConstrainSelectedInstOperands,
60572 // GIR_Coverage, 10949,
60573 GIR_EraseRootFromParent_Done,
60574 // Label 3499: @166407
60575 GIM_Try, /*On fail goto*//*Label 3500*/ GIMT_Encode4(166444), // Rule ID 10950 //
60576 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60577 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
60578 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
60579 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
60580 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
60581 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60582 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1866:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (UZP2_ZZZ_Q:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
60583 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
60584 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60585 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60586 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60587 GIR_RootConstrainSelectedInstOperands,
60588 // GIR_Coverage, 10950,
60589 GIR_EraseRootFromParent_Done,
60590 // Label 3500: @166444
60591 GIM_Try, /*On fail goto*//*Label 3501*/ GIMT_Encode4(166481), // Rule ID 10951 //
60592 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60593 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
60594 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
60595 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
60596 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
60597 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60598 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1866:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (UZP2_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
60599 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
60600 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60601 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60602 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60603 GIR_RootConstrainSelectedInstOperands,
60604 // GIR_Coverage, 10951,
60605 GIR_EraseRootFromParent_Done,
60606 // Label 3501: @166481
60607 GIM_Try, /*On fail goto*//*Label 3502*/ GIMT_Encode4(166518), // Rule ID 10952 //
60608 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60609 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
60610 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
60611 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
60612 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
60613 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60614 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1866:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (UZP2_ZZZ_Q:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
60615 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
60616 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60617 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60618 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60619 GIR_RootConstrainSelectedInstOperands,
60620 // GIR_Coverage, 10952,
60621 GIR_EraseRootFromParent_Done,
60622 // Label 3502: @166518
60623 GIM_Try, /*On fail goto*//*Label 3503*/ GIMT_Encode4(166555), // Rule ID 10953 //
60624 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60625 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
60626 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60627 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60628 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
60629 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60630 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1866:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2) => (UZP2_ZZZ_Q:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2)
60631 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
60632 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60633 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60634 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60635 GIR_RootConstrainSelectedInstOperands,
60636 // GIR_Coverage, 10953,
60637 GIR_EraseRootFromParent_Done,
60638 // Label 3503: @166555
60639 GIM_Try, /*On fail goto*//*Label 3504*/ GIMT_Encode4(166592), // Rule ID 10954 //
60640 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60641 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
60642 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
60643 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
60644 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
60645 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60646 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1705:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (TRN1_ZZZ_Q:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
60647 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
60648 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60649 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60650 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60651 GIR_RootConstrainSelectedInstOperands,
60652 // GIR_Coverage, 10954,
60653 GIR_EraseRootFromParent_Done,
60654 // Label 3504: @166592
60655 GIM_Try, /*On fail goto*//*Label 3505*/ GIMT_Encode4(166629), // Rule ID 10955 //
60656 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60657 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
60658 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60659 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60660 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
60661 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60662 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1705:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (TRN1_ZZZ_Q:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
60663 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
60664 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60665 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60666 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60667 GIR_RootConstrainSelectedInstOperands,
60668 // GIR_Coverage, 10955,
60669 GIR_EraseRootFromParent_Done,
60670 // Label 3505: @166629
60671 GIM_Try, /*On fail goto*//*Label 3506*/ GIMT_Encode4(166666), // Rule ID 10956 //
60672 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60673 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
60674 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60675 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60676 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
60677 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60678 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1705:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (TRN1_ZZZ_Q:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
60679 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
60680 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60681 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60682 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60683 GIR_RootConstrainSelectedInstOperands,
60684 // GIR_Coverage, 10956,
60685 GIR_EraseRootFromParent_Done,
60686 // Label 3506: @166666
60687 GIM_Try, /*On fail goto*//*Label 3507*/ GIMT_Encode4(166703), // Rule ID 10957 //
60688 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60689 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
60690 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
60691 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
60692 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
60693 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60694 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1705:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (TRN1_ZZZ_Q:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
60695 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
60696 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60697 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60698 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60699 GIR_RootConstrainSelectedInstOperands,
60700 // GIR_Coverage, 10957,
60701 GIR_EraseRootFromParent_Done,
60702 // Label 3507: @166703
60703 GIM_Try, /*On fail goto*//*Label 3508*/ GIMT_Encode4(166740), // Rule ID 10958 //
60704 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60705 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
60706 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
60707 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
60708 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
60709 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60710 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1705:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (TRN1_ZZZ_Q:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
60711 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
60712 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60713 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60714 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60715 GIR_RootConstrainSelectedInstOperands,
60716 // GIR_Coverage, 10958,
60717 GIR_EraseRootFromParent_Done,
60718 // Label 3508: @166740
60719 GIM_Try, /*On fail goto*//*Label 3509*/ GIMT_Encode4(166777), // Rule ID 10959 //
60720 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60721 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
60722 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
60723 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
60724 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
60725 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60726 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1705:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (TRN1_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
60727 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
60728 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60729 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60730 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60731 GIR_RootConstrainSelectedInstOperands,
60732 // GIR_Coverage, 10959,
60733 GIR_EraseRootFromParent_Done,
60734 // Label 3509: @166777
60735 GIM_Try, /*On fail goto*//*Label 3510*/ GIMT_Encode4(166814), // Rule ID 10960 //
60736 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60737 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
60738 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
60739 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
60740 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
60741 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60742 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1705:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (TRN1_ZZZ_Q:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
60743 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
60744 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60745 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60746 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60747 GIR_RootConstrainSelectedInstOperands,
60748 // GIR_Coverage, 10960,
60749 GIR_EraseRootFromParent_Done,
60750 // Label 3510: @166814
60751 GIM_Try, /*On fail goto*//*Label 3511*/ GIMT_Encode4(166851), // Rule ID 10961 //
60752 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60753 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
60754 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60755 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60756 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
60757 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60758 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1705:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2) => (TRN1_ZZZ_Q:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2)
60759 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
60760 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60761 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60762 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60763 GIR_RootConstrainSelectedInstOperands,
60764 // GIR_Coverage, 10961,
60765 GIR_EraseRootFromParent_Done,
60766 // Label 3511: @166851
60767 GIM_Try, /*On fail goto*//*Label 3512*/ GIMT_Encode4(166888), // Rule ID 10962 //
60768 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60769 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
60770 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
60771 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
60772 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
60773 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60774 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1710:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (TRN2_ZZZ_Q:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
60775 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
60776 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60777 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60778 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60779 GIR_RootConstrainSelectedInstOperands,
60780 // GIR_Coverage, 10962,
60781 GIR_EraseRootFromParent_Done,
60782 // Label 3512: @166888
60783 GIM_Try, /*On fail goto*//*Label 3513*/ GIMT_Encode4(166925), // Rule ID 10963 //
60784 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60785 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
60786 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60787 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60788 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
60789 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60790 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1710:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (TRN2_ZZZ_Q:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
60791 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
60792 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60793 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60794 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60795 GIR_RootConstrainSelectedInstOperands,
60796 // GIR_Coverage, 10963,
60797 GIR_EraseRootFromParent_Done,
60798 // Label 3513: @166925
60799 GIM_Try, /*On fail goto*//*Label 3514*/ GIMT_Encode4(166962), // Rule ID 10964 //
60800 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60801 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
60802 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60803 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60804 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
60805 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60806 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1710:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (TRN2_ZZZ_Q:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
60807 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
60808 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60809 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60810 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60811 GIR_RootConstrainSelectedInstOperands,
60812 // GIR_Coverage, 10964,
60813 GIR_EraseRootFromParent_Done,
60814 // Label 3514: @166962
60815 GIM_Try, /*On fail goto*//*Label 3515*/ GIMT_Encode4(166999), // Rule ID 10965 //
60816 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60817 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
60818 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
60819 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
60820 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
60821 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60822 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1710:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (TRN2_ZZZ_Q:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
60823 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
60824 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60825 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60826 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60827 GIR_RootConstrainSelectedInstOperands,
60828 // GIR_Coverage, 10965,
60829 GIR_EraseRootFromParent_Done,
60830 // Label 3515: @166999
60831 GIM_Try, /*On fail goto*//*Label 3516*/ GIMT_Encode4(167036), // Rule ID 10966 //
60832 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60833 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
60834 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
60835 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
60836 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
60837 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60838 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1710:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (TRN2_ZZZ_Q:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
60839 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
60840 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60841 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60842 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60843 GIR_RootConstrainSelectedInstOperands,
60844 // GIR_Coverage, 10966,
60845 GIR_EraseRootFromParent_Done,
60846 // Label 3516: @167036
60847 GIM_Try, /*On fail goto*//*Label 3517*/ GIMT_Encode4(167073), // Rule ID 10967 //
60848 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60849 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
60850 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
60851 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
60852 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
60853 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60854 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1710:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (TRN2_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
60855 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
60856 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60857 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60858 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60859 GIR_RootConstrainSelectedInstOperands,
60860 // GIR_Coverage, 10967,
60861 GIR_EraseRootFromParent_Done,
60862 // Label 3517: @167073
60863 GIM_Try, /*On fail goto*//*Label 3518*/ GIMT_Encode4(167110), // Rule ID 10968 //
60864 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60865 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
60866 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
60867 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
60868 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
60869 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60870 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1710:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (TRN2_ZZZ_Q:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
60871 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
60872 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60873 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60874 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60875 GIR_RootConstrainSelectedInstOperands,
60876 // GIR_Coverage, 10968,
60877 GIR_EraseRootFromParent_Done,
60878 // Label 3518: @167110
60879 GIM_Try, /*On fail goto*//*Label 3519*/ GIMT_Encode4(167147), // Rule ID 10969 //
60880 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVEorSME),
60881 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
60882 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60883 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60884 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
60885 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60886 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1710:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2) => (TRN2_ZZZ_Q:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2)
60887 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
60888 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60889 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60890 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60891 GIR_RootConstrainSelectedInstOperands,
60892 // GIR_Coverage, 10969,
60893 GIR_EraseRootFromParent_Done,
60894 // Label 3519: @167147
60895 GIM_Try, /*On fail goto*//*Label 3520*/ GIMT_Encode4(167184), // Rule ID 10989 //
60896 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
60897 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh),
60898 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
60899 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
60900 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
60901 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60902 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1607:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SQRDMULH_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
60903 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZ_B),
60904 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60905 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60906 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60907 GIR_RootConstrainSelectedInstOperands,
60908 // GIR_Coverage, 10989,
60909 GIR_EraseRootFromParent_Done,
60910 // Label 3520: @167184
60911 GIM_Try, /*On fail goto*//*Label 3521*/ GIMT_Encode4(167221), // Rule ID 10990 //
60912 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
60913 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh),
60914 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60915 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60916 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
60917 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60918 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1607:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SQRDMULH_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
60919 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZ_H),
60920 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60921 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60922 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60923 GIR_RootConstrainSelectedInstOperands,
60924 // GIR_Coverage, 10990,
60925 GIR_EraseRootFromParent_Done,
60926 // Label 3521: @167221
60927 GIM_Try, /*On fail goto*//*Label 3522*/ GIMT_Encode4(167258), // Rule ID 10991 //
60928 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
60929 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh),
60930 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
60931 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
60932 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
60933 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60934 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1607:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SQRDMULH_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
60935 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZ_S),
60936 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60937 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60938 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60939 GIR_RootConstrainSelectedInstOperands,
60940 // GIR_Coverage, 10991,
60941 GIR_EraseRootFromParent_Done,
60942 // Label 3522: @167258
60943 GIM_Try, /*On fail goto*//*Label 3523*/ GIMT_Encode4(167295), // Rule ID 10992 //
60944 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
60945 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh),
60946 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
60947 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
60948 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
60949 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60950 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1607:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (SQRDMULH_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
60951 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZ_D),
60952 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60953 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60954 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60955 GIR_RootConstrainSelectedInstOperands,
60956 // GIR_Coverage, 10992,
60957 GIR_EraseRootFromParent_Done,
60958 // Label 3523: @167295
60959 GIM_Try, /*On fail goto*//*Label 3524*/ GIMT_Encode4(167332), // Rule ID 11280 //
60960 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
60961 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlt),
60962 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
60963 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
60964 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
60965 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60966 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1471:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SADDLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
60967 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLT_ZZZ_H),
60968 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60969 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60970 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60971 GIR_RootConstrainSelectedInstOperands,
60972 // GIR_Coverage, 11280,
60973 GIR_EraseRootFromParent_Done,
60974 // Label 3524: @167332
60975 GIM_Try, /*On fail goto*//*Label 3525*/ GIMT_Encode4(167369), // Rule ID 11281 //
60976 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
60977 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlt),
60978 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
60979 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
60980 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
60981 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60982 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1471:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SADDLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
60983 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLT_ZZZ_S),
60984 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
60985 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
60986 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
60987 GIR_RootConstrainSelectedInstOperands,
60988 // GIR_Coverage, 11281,
60989 GIR_EraseRootFromParent_Done,
60990 // Label 3525: @167369
60991 GIM_Try, /*On fail goto*//*Label 3526*/ GIMT_Encode4(167406), // Rule ID 11282 //
60992 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
60993 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlt),
60994 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
60995 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
60996 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
60997 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
60998 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1471:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SADDLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
60999 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLT_ZZZ_D),
61000 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61001 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61002 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61003 GIR_RootConstrainSelectedInstOperands,
61004 // GIR_Coverage, 11282,
61005 GIR_EraseRootFromParent_Done,
61006 // Label 3526: @167406
61007 GIM_Try, /*On fail goto*//*Label 3527*/ GIMT_Encode4(167443), // Rule ID 11283 //
61008 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61009 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddlb),
61010 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61011 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
61012 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61013 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61014 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1719:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (UADDLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61015 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLB_ZZZ_H),
61016 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61017 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61018 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61019 GIR_RootConstrainSelectedInstOperands,
61020 // GIR_Coverage, 11283,
61021 GIR_EraseRootFromParent_Done,
61022 // Label 3527: @167443
61023 GIM_Try, /*On fail goto*//*Label 3528*/ GIMT_Encode4(167480), // Rule ID 11284 //
61024 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61025 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddlb),
61026 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61027 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61028 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61029 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61030 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1719:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (UADDLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61031 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLB_ZZZ_S),
61032 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61033 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61034 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61035 GIR_RootConstrainSelectedInstOperands,
61036 // GIR_Coverage, 11284,
61037 GIR_EraseRootFromParent_Done,
61038 // Label 3528: @167480
61039 GIM_Try, /*On fail goto*//*Label 3529*/ GIMT_Encode4(167517), // Rule ID 11285 //
61040 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61041 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddlb),
61042 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61043 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61044 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61045 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61046 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1719:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (UADDLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61047 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLB_ZZZ_D),
61048 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61049 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61050 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61051 GIR_RootConstrainSelectedInstOperands,
61052 // GIR_Coverage, 11285,
61053 GIR_EraseRootFromParent_Done,
61054 // Label 3529: @167517
61055 GIM_Try, /*On fail goto*//*Label 3530*/ GIMT_Encode4(167554), // Rule ID 11286 //
61056 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61057 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddlt),
61058 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61059 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
61060 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61061 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61062 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1720:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (UADDLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61063 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLT_ZZZ_H),
61064 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61065 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61066 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61067 GIR_RootConstrainSelectedInstOperands,
61068 // GIR_Coverage, 11286,
61069 GIR_EraseRootFromParent_Done,
61070 // Label 3530: @167554
61071 GIM_Try, /*On fail goto*//*Label 3531*/ GIMT_Encode4(167591), // Rule ID 11287 //
61072 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61073 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddlt),
61074 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61075 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61076 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61077 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61078 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1720:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (UADDLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61079 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLT_ZZZ_S),
61080 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61081 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61082 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61083 GIR_RootConstrainSelectedInstOperands,
61084 // GIR_Coverage, 11287,
61085 GIR_EraseRootFromParent_Done,
61086 // Label 3531: @167591
61087 GIM_Try, /*On fail goto*//*Label 3532*/ GIMT_Encode4(167628), // Rule ID 11288 //
61088 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61089 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddlt),
61090 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61091 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61092 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61093 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61094 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1720:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (UADDLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61095 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLT_ZZZ_D),
61096 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61097 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61098 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61099 GIR_RootConstrainSelectedInstOperands,
61100 // GIR_Coverage, 11288,
61101 GIR_EraseRootFromParent_Done,
61102 // Label 3532: @167628
61103 GIM_Try, /*On fail goto*//*Label 3533*/ GIMT_Encode4(167665), // Rule ID 11289 //
61104 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61105 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublb),
61106 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61107 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
61108 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61109 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61110 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1648:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SSUBLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61111 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLB_ZZZ_H),
61112 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61113 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61114 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61115 GIR_RootConstrainSelectedInstOperands,
61116 // GIR_Coverage, 11289,
61117 GIR_EraseRootFromParent_Done,
61118 // Label 3533: @167665
61119 GIM_Try, /*On fail goto*//*Label 3534*/ GIMT_Encode4(167702), // Rule ID 11290 //
61120 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61121 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublb),
61122 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61123 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61124 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61125 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61126 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1648:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SSUBLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61127 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLB_ZZZ_S),
61128 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61129 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61130 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61131 GIR_RootConstrainSelectedInstOperands,
61132 // GIR_Coverage, 11290,
61133 GIR_EraseRootFromParent_Done,
61134 // Label 3534: @167702
61135 GIM_Try, /*On fail goto*//*Label 3535*/ GIMT_Encode4(167739), // Rule ID 11291 //
61136 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61137 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublb),
61138 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61139 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61140 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61141 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61142 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1648:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SSUBLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61143 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLB_ZZZ_D),
61144 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61145 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61146 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61147 GIR_RootConstrainSelectedInstOperands,
61148 // GIR_Coverage, 11291,
61149 GIR_EraseRootFromParent_Done,
61150 // Label 3535: @167739
61151 GIM_Try, /*On fail goto*//*Label 3536*/ GIMT_Encode4(167776), // Rule ID 11292 //
61152 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61153 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublt),
61154 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61155 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
61156 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61157 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61158 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1650:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SSUBLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61159 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLT_ZZZ_H),
61160 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61161 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61162 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61163 GIR_RootConstrainSelectedInstOperands,
61164 // GIR_Coverage, 11292,
61165 GIR_EraseRootFromParent_Done,
61166 // Label 3536: @167776
61167 GIM_Try, /*On fail goto*//*Label 3537*/ GIMT_Encode4(167813), // Rule ID 11293 //
61168 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61169 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublt),
61170 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61171 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61172 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61173 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61174 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1650:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SSUBLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61175 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLT_ZZZ_S),
61176 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61177 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61178 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61179 GIR_RootConstrainSelectedInstOperands,
61180 // GIR_Coverage, 11293,
61181 GIR_EraseRootFromParent_Done,
61182 // Label 3537: @167813
61183 GIM_Try, /*On fail goto*//*Label 3538*/ GIMT_Encode4(167850), // Rule ID 11294 //
61184 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61185 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublt),
61186 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61187 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61188 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61189 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61190 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1650:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SSUBLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61191 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLT_ZZZ_D),
61192 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61193 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61194 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61195 GIR_RootConstrainSelectedInstOperands,
61196 // GIR_Coverage, 11294,
61197 GIR_EraseRootFromParent_Done,
61198 // Label 3538: @167850
61199 GIM_Try, /*On fail goto*//*Label 3539*/ GIMT_Encode4(167887), // Rule ID 11295 //
61200 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61201 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usublb),
61202 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61203 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
61204 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61205 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61206 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1844:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (USUBLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61207 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLB_ZZZ_H),
61208 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61209 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61210 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61211 GIR_RootConstrainSelectedInstOperands,
61212 // GIR_Coverage, 11295,
61213 GIR_EraseRootFromParent_Done,
61214 // Label 3539: @167887
61215 GIM_Try, /*On fail goto*//*Label 3540*/ GIMT_Encode4(167924), // Rule ID 11296 //
61216 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61217 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usublb),
61218 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61219 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61220 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61221 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61222 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1844:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (USUBLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61223 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLB_ZZZ_S),
61224 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61225 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61226 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61227 GIR_RootConstrainSelectedInstOperands,
61228 // GIR_Coverage, 11296,
61229 GIR_EraseRootFromParent_Done,
61230 // Label 3540: @167924
61231 GIM_Try, /*On fail goto*//*Label 3541*/ GIMT_Encode4(167961), // Rule ID 11297 //
61232 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61233 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usublb),
61234 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61235 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61236 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61237 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61238 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1844:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (USUBLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61239 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLB_ZZZ_D),
61240 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61241 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61242 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61243 GIR_RootConstrainSelectedInstOperands,
61244 // GIR_Coverage, 11297,
61245 GIR_EraseRootFromParent_Done,
61246 // Label 3541: @167961
61247 GIM_Try, /*On fail goto*//*Label 3542*/ GIMT_Encode4(167998), // Rule ID 11298 //
61248 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61249 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usublt),
61250 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61251 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
61252 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61253 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61254 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1845:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (USUBLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61255 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLT_ZZZ_H),
61256 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61257 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61258 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61259 GIR_RootConstrainSelectedInstOperands,
61260 // GIR_Coverage, 11298,
61261 GIR_EraseRootFromParent_Done,
61262 // Label 3542: @167998
61263 GIM_Try, /*On fail goto*//*Label 3543*/ GIMT_Encode4(168035), // Rule ID 11299 //
61264 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61265 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usublt),
61266 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61267 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61268 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61269 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61270 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1845:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (USUBLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61271 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLT_ZZZ_S),
61272 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61273 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61274 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61275 GIR_RootConstrainSelectedInstOperands,
61276 // GIR_Coverage, 11299,
61277 GIR_EraseRootFromParent_Done,
61278 // Label 3543: @168035
61279 GIM_Try, /*On fail goto*//*Label 3544*/ GIMT_Encode4(168072), // Rule ID 11300 //
61280 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61281 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usublt),
61282 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61283 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61284 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61285 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61286 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1845:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (USUBLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61287 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLT_ZZZ_D),
61288 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61289 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61290 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61291 GIR_RootConstrainSelectedInstOperands,
61292 // GIR_Coverage, 11300,
61293 GIR_EraseRootFromParent_Done,
61294 // Label 3544: @168072
61295 GIM_Try, /*On fail goto*//*Label 3545*/ GIMT_Encode4(168109), // Rule ID 11301 //
61296 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61297 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabdlb),
61298 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61299 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
61300 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61301 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61302 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1466:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SABDLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61303 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLB_ZZZ_H),
61304 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61305 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61306 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61307 GIR_RootConstrainSelectedInstOperands,
61308 // GIR_Coverage, 11301,
61309 GIR_EraseRootFromParent_Done,
61310 // Label 3545: @168109
61311 GIM_Try, /*On fail goto*//*Label 3546*/ GIMT_Encode4(168146), // Rule ID 11302 //
61312 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61313 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabdlb),
61314 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61315 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61316 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61317 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61318 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1466:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SABDLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61319 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLB_ZZZ_S),
61320 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61321 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61322 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61323 GIR_RootConstrainSelectedInstOperands,
61324 // GIR_Coverage, 11302,
61325 GIR_EraseRootFromParent_Done,
61326 // Label 3546: @168146
61327 GIM_Try, /*On fail goto*//*Label 3547*/ GIMT_Encode4(168183), // Rule ID 11303 //
61328 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61329 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabdlb),
61330 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61331 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61332 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61333 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61334 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1466:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SABDLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61335 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLB_ZZZ_D),
61336 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61337 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61338 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61339 GIR_RootConstrainSelectedInstOperands,
61340 // GIR_Coverage, 11303,
61341 GIR_EraseRootFromParent_Done,
61342 // Label 3547: @168183
61343 GIM_Try, /*On fail goto*//*Label 3548*/ GIMT_Encode4(168220), // Rule ID 11304 //
61344 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61345 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabdlt),
61346 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61347 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
61348 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61349 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61350 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1467:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SABDLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61351 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLT_ZZZ_H),
61352 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61353 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61354 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61355 GIR_RootConstrainSelectedInstOperands,
61356 // GIR_Coverage, 11304,
61357 GIR_EraseRootFromParent_Done,
61358 // Label 3548: @168220
61359 GIM_Try, /*On fail goto*//*Label 3549*/ GIMT_Encode4(168257), // Rule ID 11305 //
61360 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61361 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabdlt),
61362 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61363 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61364 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61365 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61366 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1467:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SABDLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61367 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLT_ZZZ_S),
61368 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61369 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61370 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61371 GIR_RootConstrainSelectedInstOperands,
61372 // GIR_Coverage, 11305,
61373 GIR_EraseRootFromParent_Done,
61374 // Label 3549: @168257
61375 GIM_Try, /*On fail goto*//*Label 3550*/ GIMT_Encode4(168294), // Rule ID 11306 //
61376 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61377 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabdlt),
61378 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61379 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61380 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61381 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61382 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1467:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SABDLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61383 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLT_ZZZ_D),
61384 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61385 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61386 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61387 GIR_RootConstrainSelectedInstOperands,
61388 // GIR_Coverage, 11306,
61389 GIR_EraseRootFromParent_Done,
61390 // Label 3550: @168294
61391 GIM_Try, /*On fail goto*//*Label 3551*/ GIMT_Encode4(168331), // Rule ID 11307 //
61392 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61393 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabdlb),
61394 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61395 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
61396 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61397 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61398 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1716:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (UABDLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61399 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLB_ZZZ_H),
61400 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61401 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61402 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61403 GIR_RootConstrainSelectedInstOperands,
61404 // GIR_Coverage, 11307,
61405 GIR_EraseRootFromParent_Done,
61406 // Label 3551: @168331
61407 GIM_Try, /*On fail goto*//*Label 3552*/ GIMT_Encode4(168368), // Rule ID 11308 //
61408 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61409 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabdlb),
61410 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61411 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61412 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61413 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61414 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1716:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (UABDLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61415 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLB_ZZZ_S),
61416 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61417 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61418 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61419 GIR_RootConstrainSelectedInstOperands,
61420 // GIR_Coverage, 11308,
61421 GIR_EraseRootFromParent_Done,
61422 // Label 3552: @168368
61423 GIM_Try, /*On fail goto*//*Label 3553*/ GIMT_Encode4(168405), // Rule ID 11309 //
61424 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61425 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabdlb),
61426 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61427 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61428 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61429 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61430 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1716:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (UABDLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61431 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLB_ZZZ_D),
61432 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61433 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61434 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61435 GIR_RootConstrainSelectedInstOperands,
61436 // GIR_Coverage, 11309,
61437 GIR_EraseRootFromParent_Done,
61438 // Label 3553: @168405
61439 GIM_Try, /*On fail goto*//*Label 3554*/ GIMT_Encode4(168442), // Rule ID 11310 //
61440 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61441 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabdlt),
61442 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61443 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
61444 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61445 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61446 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1717:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (UABDLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61447 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLT_ZZZ_H),
61448 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61449 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61450 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61451 GIR_RootConstrainSelectedInstOperands,
61452 // GIR_Coverage, 11310,
61453 GIR_EraseRootFromParent_Done,
61454 // Label 3554: @168442
61455 GIM_Try, /*On fail goto*//*Label 3555*/ GIMT_Encode4(168479), // Rule ID 11311 //
61456 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61457 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabdlt),
61458 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61459 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61460 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61461 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61462 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1717:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (UABDLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61463 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLT_ZZZ_S),
61464 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61465 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61466 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61467 GIR_RootConstrainSelectedInstOperands,
61468 // GIR_Coverage, 11311,
61469 GIR_EraseRootFromParent_Done,
61470 // Label 3555: @168479
61471 GIM_Try, /*On fail goto*//*Label 3556*/ GIMT_Encode4(168516), // Rule ID 11312 //
61472 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61473 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabdlt),
61474 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61475 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61476 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61477 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61478 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1717:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (UABDLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61479 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLT_ZZZ_D),
61480 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61481 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61482 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61483 GIR_RootConstrainSelectedInstOperands,
61484 // GIR_Coverage, 11312,
61485 GIR_EraseRootFromParent_Done,
61486 // Label 3556: @168516
61487 GIM_Try, /*On fail goto*//*Label 3557*/ GIMT_Encode4(168553), // Rule ID 11313 //
61488 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61489 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddwt),
61490 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61491 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61492 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61493 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61494 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1474:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SADDWT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61495 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWT_ZZZ_H),
61496 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61497 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61498 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61499 GIR_RootConstrainSelectedInstOperands,
61500 // GIR_Coverage, 11313,
61501 GIR_EraseRootFromParent_Done,
61502 // Label 3557: @168553
61503 GIM_Try, /*On fail goto*//*Label 3558*/ GIMT_Encode4(168590), // Rule ID 11314 //
61504 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61505 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddwt),
61506 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61507 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61508 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61509 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61510 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1474:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SADDWT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61511 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWT_ZZZ_S),
61512 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61513 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61514 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61515 GIR_RootConstrainSelectedInstOperands,
61516 // GIR_Coverage, 11314,
61517 GIR_EraseRootFromParent_Done,
61518 // Label 3558: @168590
61519 GIM_Try, /*On fail goto*//*Label 3559*/ GIMT_Encode4(168627), // Rule ID 11315 //
61520 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61521 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddwt),
61522 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61523 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
61524 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61525 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61526 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1474:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SADDWT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61527 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWT_ZZZ_D),
61528 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61529 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61530 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61531 GIR_RootConstrainSelectedInstOperands,
61532 // GIR_Coverage, 11315,
61533 GIR_EraseRootFromParent_Done,
61534 // Label 3559: @168627
61535 GIM_Try, /*On fail goto*//*Label 3560*/ GIMT_Encode4(168664), // Rule ID 11316 //
61536 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61537 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddwb),
61538 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61539 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61540 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61541 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61542 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1722:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (UADDWB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61543 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWB_ZZZ_H),
61544 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61545 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61546 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61547 GIR_RootConstrainSelectedInstOperands,
61548 // GIR_Coverage, 11316,
61549 GIR_EraseRootFromParent_Done,
61550 // Label 3560: @168664
61551 GIM_Try, /*On fail goto*//*Label 3561*/ GIMT_Encode4(168701), // Rule ID 11317 //
61552 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61553 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddwb),
61554 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61555 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61556 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61557 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61558 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1722:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (UADDWB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61559 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWB_ZZZ_S),
61560 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61561 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61562 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61563 GIR_RootConstrainSelectedInstOperands,
61564 // GIR_Coverage, 11317,
61565 GIR_EraseRootFromParent_Done,
61566 // Label 3561: @168701
61567 GIM_Try, /*On fail goto*//*Label 3562*/ GIMT_Encode4(168738), // Rule ID 11318 //
61568 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61569 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddwb),
61570 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61571 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
61572 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61573 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61574 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1722:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (UADDWB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61575 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWB_ZZZ_D),
61576 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61577 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61578 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61579 GIR_RootConstrainSelectedInstOperands,
61580 // GIR_Coverage, 11318,
61581 GIR_EraseRootFromParent_Done,
61582 // Label 3562: @168738
61583 GIM_Try, /*On fail goto*//*Label 3563*/ GIMT_Encode4(168775), // Rule ID 11319 //
61584 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61585 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddwt),
61586 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61587 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61588 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61589 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61590 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1723:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (UADDWT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61591 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWT_ZZZ_H),
61592 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61593 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61594 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61595 GIR_RootConstrainSelectedInstOperands,
61596 // GIR_Coverage, 11319,
61597 GIR_EraseRootFromParent_Done,
61598 // Label 3563: @168775
61599 GIM_Try, /*On fail goto*//*Label 3564*/ GIMT_Encode4(168812), // Rule ID 11320 //
61600 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61601 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddwt),
61602 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61603 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61604 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61605 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61606 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1723:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (UADDWT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61607 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWT_ZZZ_S),
61608 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61609 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61610 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61611 GIR_RootConstrainSelectedInstOperands,
61612 // GIR_Coverage, 11320,
61613 GIR_EraseRootFromParent_Done,
61614 // Label 3564: @168812
61615 GIM_Try, /*On fail goto*//*Label 3565*/ GIMT_Encode4(168849), // Rule ID 11321 //
61616 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61617 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddwt),
61618 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61619 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
61620 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61621 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61622 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1723:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (UADDWT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61623 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWT_ZZZ_D),
61624 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61625 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61626 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61627 GIR_RootConstrainSelectedInstOperands,
61628 // GIR_Coverage, 11321,
61629 GIR_EraseRootFromParent_Done,
61630 // Label 3565: @168849
61631 GIM_Try, /*On fail goto*//*Label 3566*/ GIMT_Encode4(168886), // Rule ID 11322 //
61632 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61633 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubwb),
61634 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61635 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61636 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61637 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61638 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1652:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SSUBWB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61639 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWB_ZZZ_H),
61640 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61641 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61642 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61643 GIR_RootConstrainSelectedInstOperands,
61644 // GIR_Coverage, 11322,
61645 GIR_EraseRootFromParent_Done,
61646 // Label 3566: @168886
61647 GIM_Try, /*On fail goto*//*Label 3567*/ GIMT_Encode4(168923), // Rule ID 11323 //
61648 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61649 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubwb),
61650 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61651 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61652 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61653 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61654 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1652:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SSUBWB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61655 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWB_ZZZ_S),
61656 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61657 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61658 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61659 GIR_RootConstrainSelectedInstOperands,
61660 // GIR_Coverage, 11323,
61661 GIR_EraseRootFromParent_Done,
61662 // Label 3567: @168923
61663 GIM_Try, /*On fail goto*//*Label 3568*/ GIMT_Encode4(168960), // Rule ID 11324 //
61664 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61665 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubwb),
61666 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61667 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
61668 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61669 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61670 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1652:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SSUBWB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61671 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWB_ZZZ_D),
61672 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61673 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61674 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61675 GIR_RootConstrainSelectedInstOperands,
61676 // GIR_Coverage, 11324,
61677 GIR_EraseRootFromParent_Done,
61678 // Label 3568: @168960
61679 GIM_Try, /*On fail goto*//*Label 3569*/ GIMT_Encode4(168997), // Rule ID 11325 //
61680 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61681 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubwt),
61682 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61683 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61684 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61685 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61686 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1653:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SSUBWT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61687 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWT_ZZZ_H),
61688 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61689 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61690 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61691 GIR_RootConstrainSelectedInstOperands,
61692 // GIR_Coverage, 11325,
61693 GIR_EraseRootFromParent_Done,
61694 // Label 3569: @168997
61695 GIM_Try, /*On fail goto*//*Label 3570*/ GIMT_Encode4(169034), // Rule ID 11326 //
61696 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61697 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubwt),
61698 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61699 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61700 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61701 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61702 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1653:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SSUBWT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61703 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWT_ZZZ_S),
61704 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61705 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61706 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61707 GIR_RootConstrainSelectedInstOperands,
61708 // GIR_Coverage, 11326,
61709 GIR_EraseRootFromParent_Done,
61710 // Label 3570: @169034
61711 GIM_Try, /*On fail goto*//*Label 3571*/ GIMT_Encode4(169071), // Rule ID 11327 //
61712 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61713 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubwt),
61714 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61715 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
61716 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61717 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61718 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1653:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SSUBWT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61719 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWT_ZZZ_D),
61720 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61721 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61722 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61723 GIR_RootConstrainSelectedInstOperands,
61724 // GIR_Coverage, 11327,
61725 GIR_EraseRootFromParent_Done,
61726 // Label 3571: @169071
61727 GIM_Try, /*On fail goto*//*Label 3572*/ GIMT_Encode4(169108), // Rule ID 11328 //
61728 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61729 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usubwb),
61730 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61731 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61732 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61733 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61734 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1846:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (USUBWB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61735 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWB_ZZZ_H),
61736 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61737 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61738 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61739 GIR_RootConstrainSelectedInstOperands,
61740 // GIR_Coverage, 11328,
61741 GIR_EraseRootFromParent_Done,
61742 // Label 3572: @169108
61743 GIM_Try, /*On fail goto*//*Label 3573*/ GIMT_Encode4(169145), // Rule ID 11329 //
61744 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61745 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usubwb),
61746 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61747 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61748 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61749 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61750 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1846:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (USUBWB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61751 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWB_ZZZ_S),
61752 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61753 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61754 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61755 GIR_RootConstrainSelectedInstOperands,
61756 // GIR_Coverage, 11329,
61757 GIR_EraseRootFromParent_Done,
61758 // Label 3573: @169145
61759 GIM_Try, /*On fail goto*//*Label 3574*/ GIMT_Encode4(169182), // Rule ID 11330 //
61760 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61761 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usubwb),
61762 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61763 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
61764 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61765 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61766 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1846:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (USUBWB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61767 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWB_ZZZ_D),
61768 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61769 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61770 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61771 GIR_RootConstrainSelectedInstOperands,
61772 // GIR_Coverage, 11330,
61773 GIR_EraseRootFromParent_Done,
61774 // Label 3574: @169182
61775 GIM_Try, /*On fail goto*//*Label 3575*/ GIMT_Encode4(169219), // Rule ID 11331 //
61776 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61777 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usubwt),
61778 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61779 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61780 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61781 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61782 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1847:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (USUBWT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61783 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWT_ZZZ_H),
61784 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61785 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61786 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61787 GIR_RootConstrainSelectedInstOperands,
61788 // GIR_Coverage, 11331,
61789 GIR_EraseRootFromParent_Done,
61790 // Label 3575: @169219
61791 GIM_Try, /*On fail goto*//*Label 3576*/ GIMT_Encode4(169256), // Rule ID 11332 //
61792 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61793 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usubwt),
61794 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61795 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61796 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61797 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61798 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1847:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (USUBWT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61799 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWT_ZZZ_S),
61800 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61801 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61802 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61803 GIR_RootConstrainSelectedInstOperands,
61804 // GIR_Coverage, 11332,
61805 GIR_EraseRootFromParent_Done,
61806 // Label 3576: @169256
61807 GIM_Try, /*On fail goto*//*Label 3577*/ GIMT_Encode4(169293), // Rule ID 11333 //
61808 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61809 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usubwt),
61810 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61811 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
61812 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61813 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61814 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1847:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (USUBWT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61815 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWT_ZZZ_D),
61816 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61817 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61818 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61819 GIR_RootConstrainSelectedInstOperands,
61820 // GIR_Coverage, 11333,
61821 GIR_EraseRootFromParent_Done,
61822 // Label 3577: @169293
61823 GIM_Try, /*On fail goto*//*Label 3578*/ GIMT_Encode4(169330), // Rule ID 11334 //
61824 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61825 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullb),
61826 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61827 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
61828 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61829 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61830 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1582:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SQDMULLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61831 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLB_ZZZ_H),
61832 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61833 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61834 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61835 GIR_RootConstrainSelectedInstOperands,
61836 // GIR_Coverage, 11334,
61837 GIR_EraseRootFromParent_Done,
61838 // Label 3578: @169330
61839 GIM_Try, /*On fail goto*//*Label 3579*/ GIMT_Encode4(169367), // Rule ID 11335 //
61840 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61841 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullb),
61842 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61843 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61844 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61845 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61846 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1582:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SQDMULLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61847 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLB_ZZZ_S),
61848 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61849 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61850 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61851 GIR_RootConstrainSelectedInstOperands,
61852 // GIR_Coverage, 11335,
61853 GIR_EraseRootFromParent_Done,
61854 // Label 3579: @169367
61855 GIM_Try, /*On fail goto*//*Label 3580*/ GIMT_Encode4(169404), // Rule ID 11336 //
61856 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61857 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullb),
61858 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61859 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61860 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61861 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61862 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1582:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SQDMULLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61863 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLB_ZZZ_D),
61864 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61865 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61866 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61867 GIR_RootConstrainSelectedInstOperands,
61868 // GIR_Coverage, 11336,
61869 GIR_EraseRootFromParent_Done,
61870 // Label 3580: @169404
61871 GIM_Try, /*On fail goto*//*Label 3581*/ GIMT_Encode4(169441), // Rule ID 11337 //
61872 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61873 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullt),
61874 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61875 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
61876 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61877 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61878 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1584:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SQDMULLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61879 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLT_ZZZ_H),
61880 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61881 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61882 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61883 GIR_RootConstrainSelectedInstOperands,
61884 // GIR_Coverage, 11337,
61885 GIR_EraseRootFromParent_Done,
61886 // Label 3581: @169441
61887 GIM_Try, /*On fail goto*//*Label 3582*/ GIMT_Encode4(169478), // Rule ID 11338 //
61888 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61889 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullt),
61890 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61891 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61892 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61893 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61894 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1584:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SQDMULLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61895 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLT_ZZZ_S),
61896 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61897 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61898 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61899 GIR_RootConstrainSelectedInstOperands,
61900 // GIR_Coverage, 11338,
61901 GIR_EraseRootFromParent_Done,
61902 // Label 3582: @169478
61903 GIM_Try, /*On fail goto*//*Label 3583*/ GIMT_Encode4(169515), // Rule ID 11339 //
61904 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61905 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullt),
61906 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61907 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61908 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61909 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61910 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1584:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SQDMULLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61911 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLT_ZZZ_D),
61912 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61913 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61914 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61915 GIR_RootConstrainSelectedInstOperands,
61916 // GIR_Coverage, 11339,
61917 GIR_EraseRootFromParent_Done,
61918 // Label 3583: @169515
61919 GIM_Try, /*On fail goto*//*Label 3584*/ GIMT_Encode4(169552), // Rule ID 11340 //
61920 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61921 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullb),
61922 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61923 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
61924 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61925 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61926 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1535:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SMULLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61927 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLB_ZZZ_H),
61928 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61929 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61930 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61931 GIR_RootConstrainSelectedInstOperands,
61932 // GIR_Coverage, 11340,
61933 GIR_EraseRootFromParent_Done,
61934 // Label 3584: @169552
61935 GIM_Try, /*On fail goto*//*Label 3585*/ GIMT_Encode4(169589), // Rule ID 11341 //
61936 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61937 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullb),
61938 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61939 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61940 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61941 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61942 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1535:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SMULLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61943 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLB_ZZZ_S),
61944 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61945 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61946 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61947 GIR_RootConstrainSelectedInstOperands,
61948 // GIR_Coverage, 11341,
61949 GIR_EraseRootFromParent_Done,
61950 // Label 3585: @169589
61951 GIM_Try, /*On fail goto*//*Label 3586*/ GIMT_Encode4(169626), // Rule ID 11342 //
61952 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61953 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullb),
61954 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
61955 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
61956 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
61957 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61958 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1535:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SMULLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
61959 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLB_ZZZ_D),
61960 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61961 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61962 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61963 GIR_RootConstrainSelectedInstOperands,
61964 // GIR_Coverage, 11342,
61965 GIR_EraseRootFromParent_Done,
61966 // Label 3586: @169626
61967 GIM_Try, /*On fail goto*//*Label 3587*/ GIMT_Encode4(169663), // Rule ID 11343 //
61968 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61969 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullt),
61970 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
61971 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
61972 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
61973 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61974 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1537:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SMULLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
61975 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLT_ZZZ_H),
61976 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61977 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61978 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61979 GIR_RootConstrainSelectedInstOperands,
61980 // GIR_Coverage, 11343,
61981 GIR_EraseRootFromParent_Done,
61982 // Label 3587: @169663
61983 GIM_Try, /*On fail goto*//*Label 3588*/ GIMT_Encode4(169700), // Rule ID 11344 //
61984 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
61985 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullt),
61986 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
61987 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
61988 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
61989 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
61990 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1537:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SMULLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
61991 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLT_ZZZ_S),
61992 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
61993 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
61994 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
61995 GIR_RootConstrainSelectedInstOperands,
61996 // GIR_Coverage, 11344,
61997 GIR_EraseRootFromParent_Done,
61998 // Label 3588: @169700
61999 GIM_Try, /*On fail goto*//*Label 3589*/ GIMT_Encode4(169737), // Rule ID 11345 //
62000 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62001 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullt),
62002 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
62003 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
62004 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
62005 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62006 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1537:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SMULLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
62007 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLT_ZZZ_D),
62008 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62009 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62010 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62011 GIR_RootConstrainSelectedInstOperands,
62012 // GIR_Coverage, 11345,
62013 GIR_EraseRootFromParent_Done,
62014 // Label 3589: @169737
62015 GIM_Try, /*On fail goto*//*Label 3590*/ GIMT_Encode4(169774), // Rule ID 11346 //
62016 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62017 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullb),
62018 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
62019 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
62020 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
62021 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62022 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1773:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (UMULLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
62023 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLB_ZZZ_H),
62024 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62025 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62026 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62027 GIR_RootConstrainSelectedInstOperands,
62028 // GIR_Coverage, 11346,
62029 GIR_EraseRootFromParent_Done,
62030 // Label 3590: @169774
62031 GIM_Try, /*On fail goto*//*Label 3591*/ GIMT_Encode4(169811), // Rule ID 11347 //
62032 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62033 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullb),
62034 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
62035 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
62036 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
62037 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62038 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1773:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (UMULLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
62039 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLB_ZZZ_S),
62040 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62041 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62042 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62043 GIR_RootConstrainSelectedInstOperands,
62044 // GIR_Coverage, 11347,
62045 GIR_EraseRootFromParent_Done,
62046 // Label 3591: @169811
62047 GIM_Try, /*On fail goto*//*Label 3592*/ GIMT_Encode4(169848), // Rule ID 11348 //
62048 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62049 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullb),
62050 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
62051 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
62052 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
62053 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62054 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1773:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (UMULLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
62055 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLB_ZZZ_D),
62056 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62057 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62058 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62059 GIR_RootConstrainSelectedInstOperands,
62060 // GIR_Coverage, 11348,
62061 GIR_EraseRootFromParent_Done,
62062 // Label 3592: @169848
62063 GIM_Try, /*On fail goto*//*Label 3593*/ GIMT_Encode4(169885), // Rule ID 11349 //
62064 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62065 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullt),
62066 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
62067 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
62068 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
62069 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62070 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1775:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (UMULLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
62071 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLT_ZZZ_H),
62072 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62073 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62074 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62075 GIR_RootConstrainSelectedInstOperands,
62076 // GIR_Coverage, 11349,
62077 GIR_EraseRootFromParent_Done,
62078 // Label 3593: @169885
62079 GIM_Try, /*On fail goto*//*Label 3594*/ GIMT_Encode4(169922), // Rule ID 11350 //
62080 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62081 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullt),
62082 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
62083 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
62084 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
62085 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62086 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1775:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (UMULLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
62087 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLT_ZZZ_S),
62088 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62089 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62090 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62091 GIR_RootConstrainSelectedInstOperands,
62092 // GIR_Coverage, 11350,
62093 GIR_EraseRootFromParent_Done,
62094 // Label 3594: @169922
62095 GIM_Try, /*On fail goto*//*Label 3595*/ GIMT_Encode4(169959), // Rule ID 11351 //
62096 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62097 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullt),
62098 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
62099 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
62100 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
62101 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62102 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1775:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (UMULLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
62103 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLT_ZZZ_D),
62104 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62105 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62106 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62107 GIR_RootConstrainSelectedInstOperands,
62108 // GIR_Coverage, 11351,
62109 GIR_EraseRootFromParent_Done,
62110 // Label 3595: @169959
62111 GIM_Try, /*On fail goto*//*Label 3596*/ GIMT_Encode4(169996), // Rule ID 11352 //
62112 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62113 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmullt_pair),
62114 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
62115 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
62116 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
62117 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62118 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1413:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (PMULLT_ZZZ_H:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
62119 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULLT_ZZZ_H),
62120 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62121 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62122 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62123 GIR_RootConstrainSelectedInstOperands,
62124 // GIR_Coverage, 11352,
62125 GIR_EraseRootFromParent_Done,
62126 // Label 3596: @169996
62127 GIM_Try, /*On fail goto*//*Label 3597*/ GIMT_Encode4(170033), // Rule ID 11353 //
62128 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62129 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmullt_pair),
62130 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
62131 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
62132 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
62133 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62134 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1413:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (PMULLT_ZZZ_D:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
62135 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULLT_ZZZ_D),
62136 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62137 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62138 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62139 GIR_RootConstrainSelectedInstOperands,
62140 // GIR_Coverage, 11353,
62141 GIR_EraseRootFromParent_Done,
62142 // Label 3597: @170033
62143 GIM_Try, /*On fail goto*//*Label 3598*/ GIMT_Encode4(170070), // Rule ID 11454 //
62144 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62145 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_raddhnb),
62146 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
62147 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
62148 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
62149 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62150 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1443:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (RADDHNB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
62151 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNB_ZZZ_B),
62152 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62153 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62154 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62155 GIR_RootConstrainSelectedInstOperands,
62156 // GIR_Coverage, 11454,
62157 GIR_EraseRootFromParent_Done,
62158 // Label 3598: @170070
62159 GIM_Try, /*On fail goto*//*Label 3599*/ GIMT_Encode4(170107), // Rule ID 11455 //
62160 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62161 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_raddhnb),
62162 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
62163 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
62164 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
62165 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62166 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1443:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (RADDHNB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
62167 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNB_ZZZ_H),
62168 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62169 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62170 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62171 GIR_RootConstrainSelectedInstOperands,
62172 // GIR_Coverage, 11455,
62173 GIR_EraseRootFromParent_Done,
62174 // Label 3599: @170107
62175 GIM_Try, /*On fail goto*//*Label 3600*/ GIMT_Encode4(170144), // Rule ID 11456 //
62176 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62177 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_raddhnb),
62178 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
62179 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
62180 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
62181 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62182 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1443:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (RADDHNB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
62183 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNB_ZZZ_S),
62184 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62185 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62186 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62187 GIR_RootConstrainSelectedInstOperands,
62188 // GIR_Coverage, 11456,
62189 GIR_EraseRootFromParent_Done,
62190 // Label 3600: @170144
62191 GIM_Try, /*On fail goto*//*Label 3601*/ GIMT_Encode4(170181), // Rule ID 11457 //
62192 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62193 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subhnb),
62194 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
62195 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
62196 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
62197 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62198 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1684:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SUBHNB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
62199 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNB_ZZZ_B),
62200 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62201 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62202 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62203 GIR_RootConstrainSelectedInstOperands,
62204 // GIR_Coverage, 11457,
62205 GIR_EraseRootFromParent_Done,
62206 // Label 3601: @170181
62207 GIM_Try, /*On fail goto*//*Label 3602*/ GIMT_Encode4(170218), // Rule ID 11458 //
62208 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62209 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subhnb),
62210 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
62211 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
62212 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
62213 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62214 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1684:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SUBHNB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
62215 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNB_ZZZ_H),
62216 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62217 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62218 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62219 GIR_RootConstrainSelectedInstOperands,
62220 // GIR_Coverage, 11458,
62221 GIR_EraseRootFromParent_Done,
62222 // Label 3602: @170218
62223 GIM_Try, /*On fail goto*//*Label 3603*/ GIMT_Encode4(170255), // Rule ID 11459 //
62224 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62225 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subhnb),
62226 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
62227 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
62228 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
62229 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62230 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1684:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (SUBHNB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
62231 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNB_ZZZ_S),
62232 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62233 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62234 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62235 GIR_RootConstrainSelectedInstOperands,
62236 // GIR_Coverage, 11459,
62237 GIR_EraseRootFromParent_Done,
62238 // Label 3603: @170255
62239 GIM_Try, /*On fail goto*//*Label 3604*/ GIMT_Encode4(170292), // Rule ID 11460 //
62240 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62241 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rsubhnb),
62242 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
62243 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
62244 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
62245 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62246 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1459:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (RSUBHNB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
62247 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNB_ZZZ_B),
62248 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62249 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62250 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62251 GIR_RootConstrainSelectedInstOperands,
62252 // GIR_Coverage, 11460,
62253 GIR_EraseRootFromParent_Done,
62254 // Label 3604: @170292
62255 GIM_Try, /*On fail goto*//*Label 3605*/ GIMT_Encode4(170329), // Rule ID 11461 //
62256 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62257 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rsubhnb),
62258 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
62259 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
62260 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
62261 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62262 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1459:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (RSUBHNB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
62263 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNB_ZZZ_H),
62264 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62265 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62266 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62267 GIR_RootConstrainSelectedInstOperands,
62268 // GIR_Coverage, 11461,
62269 GIR_EraseRootFromParent_Done,
62270 // Label 3605: @170329
62271 GIM_Try, /*On fail goto*//*Label 3606*/ GIMT_Encode4(170366), // Rule ID 11462 //
62272 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62273 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rsubhnb),
62274 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
62275 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
62276 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
62277 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62278 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1459:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (RSUBHNB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
62279 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNB_ZZZ_S),
62280 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62281 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62282 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62283 GIR_RootConstrainSelectedInstOperands,
62284 // GIR_Coverage, 11462,
62285 GIR_EraseRootFromParent_Done,
62286 // Label 3606: @170366
62287 GIM_Try, /*On fail goto*//*Label 3607*/ GIMT_Encode4(170403), // Rule ID 11478 //
62288 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62289 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqxtnt),
62290 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
62291 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
62292 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
62293 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62294 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1826:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (UQXTNT_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
62295 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNT_ZZ_B),
62296 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62297 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62298 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62299 GIR_RootConstrainSelectedInstOperands,
62300 // GIR_Coverage, 11478,
62301 GIR_EraseRootFromParent_Done,
62302 // Label 3607: @170403
62303 GIM_Try, /*On fail goto*//*Label 3608*/ GIMT_Encode4(170440), // Rule ID 11479 //
62304 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62305 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqxtnt),
62306 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
62307 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
62308 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
62309 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62310 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1826:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (UQXTNT_ZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
62311 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNT_ZZ_H),
62312 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62313 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62314 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62315 GIR_RootConstrainSelectedInstOperands,
62316 // GIR_Coverage, 11479,
62317 GIR_EraseRootFromParent_Done,
62318 // Label 3608: @170440
62319 GIM_Try, /*On fail goto*//*Label 3609*/ GIMT_Encode4(170477), // Rule ID 11480 //
62320 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62321 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqxtnt),
62322 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
62323 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
62324 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
62325 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62326 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1826:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (UQXTNT_ZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
62327 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNT_ZZ_S),
62328 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62329 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62330 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62331 GIR_RootConstrainSelectedInstOperands,
62332 // GIR_Coverage, 11480,
62333 GIR_EraseRootFromParent_Done,
62334 // Label 3609: @170477
62335 GIM_Try, /*On fail goto*//*Label 3610*/ GIMT_Encode4(170514), // Rule ID 11481 //
62336 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62337 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtunt),
62338 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
62339 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
62340 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
62341 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62342 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1635:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SQXTUNT_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
62343 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNT_ZZ_B),
62344 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62345 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62346 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62347 GIR_RootConstrainSelectedInstOperands,
62348 // GIR_Coverage, 11481,
62349 GIR_EraseRootFromParent_Done,
62350 // Label 3610: @170514
62351 GIM_Try, /*On fail goto*//*Label 3611*/ GIMT_Encode4(170551), // Rule ID 11482 //
62352 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62353 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtunt),
62354 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
62355 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
62356 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
62357 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62358 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1635:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SQXTUNT_ZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
62359 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNT_ZZ_H),
62360 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62361 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62362 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62363 GIR_RootConstrainSelectedInstOperands,
62364 // GIR_Coverage, 11482,
62365 GIR_EraseRootFromParent_Done,
62366 // Label 3611: @170551
62367 GIM_Try, /*On fail goto*//*Label 3612*/ GIMT_Encode4(170588), // Rule ID 11483 //
62368 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62369 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtunt),
62370 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
62371 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
62372 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
62373 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62374 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1635:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (SQXTUNT_ZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
62375 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNT_ZZ_S),
62376 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62377 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62378 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62379 GIR_RootConstrainSelectedInstOperands,
62380 // GIR_Coverage, 11483,
62381 GIR_EraseRootFromParent_Done,
62382 // Label 3612: @170588
62383 GIM_Try, /*On fail goto*//*Label 3613*/ GIMT_Encode4(170625), // Rule ID 11499 //
62384 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62385 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublbt),
62386 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
62387 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
62388 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
62389 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62390 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1649:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SSUBLBT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
62391 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLBT_ZZZ_H),
62392 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62393 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62394 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62395 GIR_RootConstrainSelectedInstOperands,
62396 // GIR_Coverage, 11499,
62397 GIR_EraseRootFromParent_Done,
62398 // Label 3613: @170625
62399 GIM_Try, /*On fail goto*//*Label 3614*/ GIMT_Encode4(170662), // Rule ID 11500 //
62400 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62401 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublbt),
62402 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
62403 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
62404 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
62405 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62406 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1649:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SSUBLBT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
62407 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLBT_ZZZ_S),
62408 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62409 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62410 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62411 GIR_RootConstrainSelectedInstOperands,
62412 // GIR_Coverage, 11500,
62413 GIR_EraseRootFromParent_Done,
62414 // Label 3614: @170662
62415 GIM_Try, /*On fail goto*//*Label 3615*/ GIMT_Encode4(170699), // Rule ID 11501 //
62416 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62417 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublbt),
62418 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
62419 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
62420 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
62421 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62422 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1649:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SSUBLBT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
62423 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLBT_ZZZ_D),
62424 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62425 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62426 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62427 GIR_RootConstrainSelectedInstOperands,
62428 // GIR_Coverage, 11501,
62429 GIR_EraseRootFromParent_Done,
62430 // Label 3615: @170699
62431 GIM_Try, /*On fail goto*//*Label 3616*/ GIMT_Encode4(170736), // Rule ID 11502 //
62432 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62433 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubltb),
62434 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
62435 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
62436 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
62437 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62438 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1651:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SSUBLTB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
62439 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLTB_ZZZ_H),
62440 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62441 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62442 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62443 GIR_RootConstrainSelectedInstOperands,
62444 // GIR_Coverage, 11502,
62445 GIR_EraseRootFromParent_Done,
62446 // Label 3616: @170736
62447 GIM_Try, /*On fail goto*//*Label 3617*/ GIMT_Encode4(170773), // Rule ID 11503 //
62448 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62449 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubltb),
62450 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
62451 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
62452 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
62453 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62454 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1651:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SSUBLTB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
62455 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLTB_ZZZ_S),
62456 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62457 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62458 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62459 GIR_RootConstrainSelectedInstOperands,
62460 // GIR_Coverage, 11503,
62461 GIR_EraseRootFromParent_Done,
62462 // Label 3617: @170773
62463 GIM_Try, /*On fail goto*//*Label 3618*/ GIMT_Encode4(170810), // Rule ID 11504 //
62464 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62465 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubltb),
62466 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
62467 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
62468 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
62469 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
62470 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1651:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SSUBLTB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
62471 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLTB_ZZZ_D),
62472 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
62473 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62474 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62475 GIR_RootConstrainSelectedInstOperands,
62476 // GIR_Coverage, 11504,
62477 GIR_EraseRootFromParent_Done,
62478 // Label 3618: @170810
62479 GIM_Try, /*On fail goto*//*Label 3619*/ GIMT_Encode4(170850), // Rule ID 11572 //
62480 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62481 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
62482 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
62483 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
62484 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
62485 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62486 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1871:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILEGE_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
62487 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PWW_B),
62488 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62489 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62490 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62491 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62492 GIR_RootConstrainSelectedInstOperands,
62493 // GIR_Coverage, 11572,
62494 GIR_EraseRootFromParent_Done,
62495 // Label 3619: @170850
62496 GIM_Try, /*On fail goto*//*Label 3620*/ GIMT_Encode4(170890), // Rule ID 11573 //
62497 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62498 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
62499 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
62500 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
62501 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
62502 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62503 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1871:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILEGE_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
62504 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PWW_H),
62505 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62506 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62507 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62508 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62509 GIR_RootConstrainSelectedInstOperands,
62510 // GIR_Coverage, 11573,
62511 GIR_EraseRootFromParent_Done,
62512 // Label 3620: @170890
62513 GIM_Try, /*On fail goto*//*Label 3621*/ GIMT_Encode4(170930), // Rule ID 11574 //
62514 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62515 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
62516 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
62517 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
62518 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
62519 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62520 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1871:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILEGE_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
62521 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PWW_S),
62522 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62523 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62524 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62525 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62526 GIR_RootConstrainSelectedInstOperands,
62527 // GIR_Coverage, 11574,
62528 GIR_EraseRootFromParent_Done,
62529 // Label 3621: @170930
62530 GIM_Try, /*On fail goto*//*Label 3622*/ GIMT_Encode4(170970), // Rule ID 11575 //
62531 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62532 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
62533 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
62534 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
62535 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
62536 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62537 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1871:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILEGE_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
62538 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PWW_D),
62539 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62540 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62541 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62542 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62543 GIR_RootConstrainSelectedInstOperands,
62544 // GIR_Coverage, 11575,
62545 GIR_EraseRootFromParent_Done,
62546 // Label 3622: @170970
62547 GIM_Try, /*On fail goto*//*Label 3623*/ GIMT_Encode4(171010), // Rule ID 11576 //
62548 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62549 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
62550 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
62551 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
62552 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
62553 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62554 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1877:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILEGT_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
62555 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PWW_B),
62556 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62557 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62558 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62559 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62560 GIR_RootConstrainSelectedInstOperands,
62561 // GIR_Coverage, 11576,
62562 GIR_EraseRootFromParent_Done,
62563 // Label 3623: @171010
62564 GIM_Try, /*On fail goto*//*Label 3624*/ GIMT_Encode4(171050), // Rule ID 11577 //
62565 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62566 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
62567 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
62568 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
62569 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
62570 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62571 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1877:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILEGT_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
62572 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PWW_H),
62573 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62574 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62575 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62576 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62577 GIR_RootConstrainSelectedInstOperands,
62578 // GIR_Coverage, 11577,
62579 GIR_EraseRootFromParent_Done,
62580 // Label 3624: @171050
62581 GIM_Try, /*On fail goto*//*Label 3625*/ GIMT_Encode4(171090), // Rule ID 11578 //
62582 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62583 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
62584 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
62585 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
62586 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
62587 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62588 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1877:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILEGT_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
62589 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PWW_S),
62590 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62591 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62592 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62593 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62594 GIR_RootConstrainSelectedInstOperands,
62595 // GIR_Coverage, 11578,
62596 GIR_EraseRootFromParent_Done,
62597 // Label 3625: @171090
62598 GIM_Try, /*On fail goto*//*Label 3626*/ GIMT_Encode4(171130), // Rule ID 11579 //
62599 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62600 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
62601 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
62602 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
62603 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
62604 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62605 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1877:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILEGT_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
62606 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PWW_D),
62607 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62608 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62609 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62610 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62611 GIR_RootConstrainSelectedInstOperands,
62612 // GIR_Coverage, 11579,
62613 GIR_EraseRootFromParent_Done,
62614 // Label 3626: @171130
62615 GIM_Try, /*On fail goto*//*Label 3627*/ GIMT_Encode4(171170), // Rule ID 11584 //
62616 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62617 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
62618 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
62619 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
62620 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
62621 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62622 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1889:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILEHS_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
62623 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PWW_B),
62624 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62625 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62626 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62627 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62628 GIR_RootConstrainSelectedInstOperands,
62629 // GIR_Coverage, 11584,
62630 GIR_EraseRootFromParent_Done,
62631 // Label 3627: @171170
62632 GIM_Try, /*On fail goto*//*Label 3628*/ GIMT_Encode4(171210), // Rule ID 11585 //
62633 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62634 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
62635 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
62636 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
62637 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
62638 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62639 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1889:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILEHS_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
62640 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PWW_H),
62641 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62642 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62643 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62644 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62645 GIR_RootConstrainSelectedInstOperands,
62646 // GIR_Coverage, 11585,
62647 GIR_EraseRootFromParent_Done,
62648 // Label 3628: @171210
62649 GIM_Try, /*On fail goto*//*Label 3629*/ GIMT_Encode4(171250), // Rule ID 11586 //
62650 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62651 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
62652 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
62653 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
62654 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
62655 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62656 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1889:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILEHS_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
62657 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PWW_S),
62658 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62659 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62660 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62661 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62662 GIR_RootConstrainSelectedInstOperands,
62663 // GIR_Coverage, 11586,
62664 GIR_EraseRootFromParent_Done,
62665 // Label 3629: @171250
62666 GIM_Try, /*On fail goto*//*Label 3630*/ GIMT_Encode4(171290), // Rule ID 11587 //
62667 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62668 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
62669 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
62670 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
62671 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
62672 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62673 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1889:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILEHS_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
62674 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PWW_D),
62675 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62676 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62677 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62678 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62679 GIR_RootConstrainSelectedInstOperands,
62680 // GIR_Coverage, 11587,
62681 GIR_EraseRootFromParent_Done,
62682 // Label 3630: @171290
62683 GIM_Try, /*On fail goto*//*Label 3631*/ GIMT_Encode4(171330), // Rule ID 11588 //
62684 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62685 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
62686 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
62687 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
62688 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
62689 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62690 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1883:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILEHI_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
62691 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PWW_B),
62692 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62693 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62694 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62695 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62696 GIR_RootConstrainSelectedInstOperands,
62697 // GIR_Coverage, 11588,
62698 GIR_EraseRootFromParent_Done,
62699 // Label 3631: @171330
62700 GIM_Try, /*On fail goto*//*Label 3632*/ GIMT_Encode4(171370), // Rule ID 11589 //
62701 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62702 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
62703 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
62704 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
62705 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
62706 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62707 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1883:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILEHI_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
62708 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PWW_H),
62709 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62710 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62711 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62712 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62713 GIR_RootConstrainSelectedInstOperands,
62714 // GIR_Coverage, 11589,
62715 GIR_EraseRootFromParent_Done,
62716 // Label 3632: @171370
62717 GIM_Try, /*On fail goto*//*Label 3633*/ GIMT_Encode4(171410), // Rule ID 11590 //
62718 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62719 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
62720 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
62721 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
62722 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
62723 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62724 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1883:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILEHI_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
62725 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PWW_S),
62726 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62727 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62728 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62729 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62730 GIR_RootConstrainSelectedInstOperands,
62731 // GIR_Coverage, 11590,
62732 GIR_EraseRootFromParent_Done,
62733 // Label 3633: @171410
62734 GIM_Try, /*On fail goto*//*Label 3634*/ GIMT_Encode4(171450), // Rule ID 11591 //
62735 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62736 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
62737 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
62738 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
62739 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
62740 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62741 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1883:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2) => (WHILEHI_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
62742 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PWW_D),
62743 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62744 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62745 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62746 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62747 GIR_RootConstrainSelectedInstOperands,
62748 // GIR_Coverage, 11591,
62749 GIR_EraseRootFromParent_Done,
62750 // Label 3634: @171450
62751 GIM_Try, /*On fail goto*//*Label 3635*/ GIMT_Encode4(171490), // Rule ID 11596 //
62752 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62753 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
62754 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
62755 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
62756 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
62757 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62758 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1871:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEGE_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
62759 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PXX_B),
62760 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62761 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62762 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62763 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62764 GIR_RootConstrainSelectedInstOperands,
62765 // GIR_Coverage, 11596,
62766 GIR_EraseRootFromParent_Done,
62767 // Label 3635: @171490
62768 GIM_Try, /*On fail goto*//*Label 3636*/ GIMT_Encode4(171530), // Rule ID 11597 //
62769 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62770 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
62771 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
62772 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
62773 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
62774 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62775 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1871:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEGE_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
62776 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PXX_H),
62777 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62778 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62779 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62780 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62781 GIR_RootConstrainSelectedInstOperands,
62782 // GIR_Coverage, 11597,
62783 GIR_EraseRootFromParent_Done,
62784 // Label 3636: @171530
62785 GIM_Try, /*On fail goto*//*Label 3637*/ GIMT_Encode4(171570), // Rule ID 11598 //
62786 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62787 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
62788 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
62789 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
62790 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
62791 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62792 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1871:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEGE_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
62793 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PXX_S),
62794 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62795 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62796 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62797 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62798 GIR_RootConstrainSelectedInstOperands,
62799 // GIR_Coverage, 11598,
62800 GIR_EraseRootFromParent_Done,
62801 // Label 3637: @171570
62802 GIM_Try, /*On fail goto*//*Label 3638*/ GIMT_Encode4(171610), // Rule ID 11599 //
62803 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62804 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
62805 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
62806 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
62807 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
62808 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62809 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1871:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEGE_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
62810 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PXX_D),
62811 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62812 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62813 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62814 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62815 GIR_RootConstrainSelectedInstOperands,
62816 // GIR_Coverage, 11599,
62817 GIR_EraseRootFromParent_Done,
62818 // Label 3638: @171610
62819 GIM_Try, /*On fail goto*//*Label 3639*/ GIMT_Encode4(171650), // Rule ID 11600 //
62820 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62821 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
62822 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
62823 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
62824 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
62825 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62826 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1877:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEGT_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
62827 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PXX_B),
62828 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62829 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62830 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62831 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62832 GIR_RootConstrainSelectedInstOperands,
62833 // GIR_Coverage, 11600,
62834 GIR_EraseRootFromParent_Done,
62835 // Label 3639: @171650
62836 GIM_Try, /*On fail goto*//*Label 3640*/ GIMT_Encode4(171690), // Rule ID 11601 //
62837 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62838 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
62839 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
62840 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
62841 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
62842 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62843 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1877:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEGT_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
62844 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PXX_H),
62845 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62846 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62847 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62848 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62849 GIR_RootConstrainSelectedInstOperands,
62850 // GIR_Coverage, 11601,
62851 GIR_EraseRootFromParent_Done,
62852 // Label 3640: @171690
62853 GIM_Try, /*On fail goto*//*Label 3641*/ GIMT_Encode4(171730), // Rule ID 11602 //
62854 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62855 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
62856 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
62857 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
62858 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
62859 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62860 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1877:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEGT_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
62861 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PXX_S),
62862 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62863 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62864 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62865 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62866 GIR_RootConstrainSelectedInstOperands,
62867 // GIR_Coverage, 11602,
62868 GIR_EraseRootFromParent_Done,
62869 // Label 3641: @171730
62870 GIM_Try, /*On fail goto*//*Label 3642*/ GIMT_Encode4(171770), // Rule ID 11603 //
62871 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62872 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
62873 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
62874 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
62875 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
62876 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62877 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1877:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEGT_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
62878 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PXX_D),
62879 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62880 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62881 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62882 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62883 GIR_RootConstrainSelectedInstOperands,
62884 // GIR_Coverage, 11603,
62885 GIR_EraseRootFromParent_Done,
62886 // Label 3642: @171770
62887 GIM_Try, /*On fail goto*//*Label 3643*/ GIMT_Encode4(171810), // Rule ID 11608 //
62888 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62889 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
62890 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
62891 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
62892 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
62893 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62894 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1889:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEHS_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
62895 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PXX_B),
62896 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62897 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62898 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62899 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62900 GIR_RootConstrainSelectedInstOperands,
62901 // GIR_Coverage, 11608,
62902 GIR_EraseRootFromParent_Done,
62903 // Label 3643: @171810
62904 GIM_Try, /*On fail goto*//*Label 3644*/ GIMT_Encode4(171850), // Rule ID 11609 //
62905 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62906 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
62907 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
62908 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
62909 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
62910 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62911 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1889:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEHS_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
62912 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PXX_H),
62913 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62914 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62915 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62916 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62917 GIR_RootConstrainSelectedInstOperands,
62918 // GIR_Coverage, 11609,
62919 GIR_EraseRootFromParent_Done,
62920 // Label 3644: @171850
62921 GIM_Try, /*On fail goto*//*Label 3645*/ GIMT_Encode4(171890), // Rule ID 11610 //
62922 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62923 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
62924 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
62925 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
62926 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
62927 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62928 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1889:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEHS_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
62929 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PXX_S),
62930 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62931 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62932 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62933 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62934 GIR_RootConstrainSelectedInstOperands,
62935 // GIR_Coverage, 11610,
62936 GIR_EraseRootFromParent_Done,
62937 // Label 3645: @171890
62938 GIM_Try, /*On fail goto*//*Label 3646*/ GIMT_Encode4(171930), // Rule ID 11611 //
62939 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62940 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
62941 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
62942 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
62943 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
62944 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62945 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1889:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEHS_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
62946 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PXX_D),
62947 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62948 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62949 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62950 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62951 GIR_RootConstrainSelectedInstOperands,
62952 // GIR_Coverage, 11611,
62953 GIR_EraseRootFromParent_Done,
62954 // Label 3646: @171930
62955 GIM_Try, /*On fail goto*//*Label 3647*/ GIMT_Encode4(171970), // Rule ID 11612 //
62956 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62957 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
62958 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
62959 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
62960 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
62961 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62962 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1883:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEHI_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
62963 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PXX_B),
62964 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62965 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62966 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62967 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62968 GIR_RootConstrainSelectedInstOperands,
62969 // GIR_Coverage, 11612,
62970 GIR_EraseRootFromParent_Done,
62971 // Label 3647: @171970
62972 GIM_Try, /*On fail goto*//*Label 3648*/ GIMT_Encode4(172010), // Rule ID 11613 //
62973 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62974 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
62975 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
62976 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
62977 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
62978 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62979 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1883:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEHI_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
62980 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PXX_H),
62981 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62982 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
62983 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
62984 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
62985 GIR_RootConstrainSelectedInstOperands,
62986 // GIR_Coverage, 11613,
62987 GIR_EraseRootFromParent_Done,
62988 // Label 3648: @172010
62989 GIM_Try, /*On fail goto*//*Label 3649*/ GIMT_Encode4(172050), // Rule ID 11614 //
62990 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
62991 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
62992 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
62993 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
62994 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
62995 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
62996 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1883:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEHI_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
62997 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PXX_S),
62998 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
62999 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63000 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63001 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
63002 GIR_RootConstrainSelectedInstOperands,
63003 // GIR_Coverage, 11614,
63004 GIR_EraseRootFromParent_Done,
63005 // Label 3649: @172050
63006 GIM_Try, /*On fail goto*//*Label 3650*/ GIMT_Encode4(172090), // Rule ID 11615 //
63007 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
63008 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
63009 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
63010 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
63011 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
63012 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
63013 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1883:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEHI_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
63014 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PXX_D),
63015 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
63016 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63017 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63018 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
63019 GIR_RootConstrainSelectedInstOperands,
63020 // GIR_Coverage, 11615,
63021 GIR_EraseRootFromParent_Done,
63022 // Label 3650: @172090
63023 GIM_Try, /*On fail goto*//*Label 3651*/ GIMT_Encode4(172127), // Rule ID 11624 //
63024 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2AES),
63025 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_aesd),
63026 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
63027 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
63028 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
63029 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63030 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1074:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (AESD_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
63031 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESD_ZZZ_B),
63032 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
63033 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63034 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63035 GIR_RootConstrainSelectedInstOperands,
63036 // GIR_Coverage, 11624,
63037 GIR_EraseRootFromParent_Done,
63038 // Label 3651: @172127
63039 GIM_Try, /*On fail goto*//*Label 3652*/ GIMT_Encode4(172164), // Rule ID 11626 //
63040 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2AES),
63041 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmullt_pair),
63042 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
63043 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
63044 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
63045 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63046 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1413:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (PMULLT_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
63047 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULLT_ZZZ_Q),
63048 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
63049 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63050 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63051 GIR_RootConstrainSelectedInstOperands,
63052 // GIR_Coverage, 11626,
63053 GIR_EraseRootFromParent_Done,
63054 // Label 3652: @172164
63055 GIM_Try, /*On fail goto*//*Label 3653*/ GIMT_Encode4(172201), // Rule ID 11627 //
63056 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2SM4),
63057 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sm4e),
63058 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
63059 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
63060 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
63061 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63062 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1504:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SM4E_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
63063 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM4E_ZZZ_S),
63064 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
63065 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63066 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63067 GIR_RootConstrainSelectedInstOperands,
63068 // GIR_Coverage, 11627,
63069 GIR_EraseRootFromParent_Done,
63070 // Label 3653: @172201
63071 GIM_Try, /*On fail goto*//*Label 3654*/ GIMT_Encode4(172238), // Rule ID 11628 //
63072 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2SHA3),
63073 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rax1),
63074 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
63075 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
63076 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
63077 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63078 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1445:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (RAX1_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
63079 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RAX1_ZZZ_D),
63080 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
63081 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63082 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63083 GIR_RootConstrainSelectedInstOperands,
63084 // GIR_Coverage, 11628,
63085 GIR_EraseRootFromParent_Done,
63086 // Label 3654: @172238
63087 GIM_Try, /*On fail goto*//*Label 3655*/ GIMT_Encode4(172275), // Rule ID 11629 //
63088 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2BitPerm),
63089 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bdep_x),
63090 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
63091 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
63092 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
63093 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63094 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1088:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (BDEP_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
63095 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BDEP_ZZZ_B),
63096 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
63097 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63098 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63099 GIR_RootConstrainSelectedInstOperands,
63100 // GIR_Coverage, 11629,
63101 GIR_EraseRootFromParent_Done,
63102 // Label 3655: @172275
63103 GIM_Try, /*On fail goto*//*Label 3656*/ GIMT_Encode4(172312), // Rule ID 11630 //
63104 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2BitPerm),
63105 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bdep_x),
63106 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
63107 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
63108 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
63109 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63110 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1088:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (BDEP_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
63111 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BDEP_ZZZ_H),
63112 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
63113 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63114 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63115 GIR_RootConstrainSelectedInstOperands,
63116 // GIR_Coverage, 11630,
63117 GIR_EraseRootFromParent_Done,
63118 // Label 3656: @172312
63119 GIM_Try, /*On fail goto*//*Label 3657*/ GIMT_Encode4(172349), // Rule ID 11631 //
63120 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2BitPerm),
63121 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bdep_x),
63122 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
63123 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
63124 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
63125 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63126 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1088:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (BDEP_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
63127 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BDEP_ZZZ_S),
63128 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
63129 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63130 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63131 GIR_RootConstrainSelectedInstOperands,
63132 // GIR_Coverage, 11631,
63133 GIR_EraseRootFromParent_Done,
63134 // Label 3657: @172349
63135 GIM_Try, /*On fail goto*//*Label 3658*/ GIMT_Encode4(172386), // Rule ID 11632 //
63136 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2BitPerm),
63137 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bdep_x),
63138 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
63139 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
63140 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
63141 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63142 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1088:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (BDEP_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
63143 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BDEP_ZZZ_D),
63144 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
63145 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63146 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63147 GIR_RootConstrainSelectedInstOperands,
63148 // GIR_Coverage, 11632,
63149 GIR_EraseRootFromParent_Done,
63150 // Label 3658: @172386
63151 GIM_Try, /*On fail goto*//*Label 3659*/ GIMT_Encode4(172423), // Rule ID 11633 //
63152 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2BitPerm),
63153 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bgrp_x),
63154 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
63155 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
63156 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
63157 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63158 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1105:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (BGRP_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
63159 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BGRP_ZZZ_B),
63160 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
63161 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63162 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63163 GIR_RootConstrainSelectedInstOperands,
63164 // GIR_Coverage, 11633,
63165 GIR_EraseRootFromParent_Done,
63166 // Label 3659: @172423
63167 GIM_Try, /*On fail goto*//*Label 3660*/ GIMT_Encode4(172460), // Rule ID 11634 //
63168 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2BitPerm),
63169 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bgrp_x),
63170 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
63171 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
63172 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
63173 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63174 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1105:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (BGRP_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
63175 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BGRP_ZZZ_H),
63176 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
63177 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63178 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63179 GIR_RootConstrainSelectedInstOperands,
63180 // GIR_Coverage, 11634,
63181 GIR_EraseRootFromParent_Done,
63182 // Label 3660: @172460
63183 GIM_Try, /*On fail goto*//*Label 3661*/ GIMT_Encode4(172497), // Rule ID 11635 //
63184 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2BitPerm),
63185 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bgrp_x),
63186 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
63187 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
63188 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
63189 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63190 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1105:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (BGRP_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
63191 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BGRP_ZZZ_S),
63192 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
63193 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63194 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63195 GIR_RootConstrainSelectedInstOperands,
63196 // GIR_Coverage, 11635,
63197 GIR_EraseRootFromParent_Done,
63198 // Label 3661: @172497
63199 GIM_Try, /*On fail goto*//*Label 3662*/ GIMT_Encode4(172534), // Rule ID 11636 //
63200 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2BitPerm),
63201 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bgrp_x),
63202 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
63203 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
63204 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
63205 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63206 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1105:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (BGRP_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
63207 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BGRP_ZZZ_D),
63208 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
63209 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63210 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63211 GIR_RootConstrainSelectedInstOperands,
63212 // GIR_Coverage, 11636,
63213 GIR_EraseRootFromParent_Done,
63214 // Label 3662: @172534
63215 GIM_Try, /*On fail goto*//*Label 3663*/ GIMT_Encode4(172571), // Rule ID 11790 //
63216 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63217 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnmqv),
63218 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
63219 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
63220 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
63221 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63222 // (intrinsic_wo_chain:{ *:[v8f16] } 1250:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (FMAXNMQV_H:{ *:[v8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
63223 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMQV_H),
63224 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63225 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63226 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63227 GIR_RootConstrainSelectedInstOperands,
63228 // GIR_Coverage, 11790,
63229 GIR_EraseRootFromParent_Done,
63230 // Label 3663: @172571
63231 GIM_Try, /*On fail goto*//*Label 3664*/ GIMT_Encode4(172608), // Rule ID 11791 //
63232 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63233 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnmqv),
63234 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
63235 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
63236 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
63237 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63238 // (intrinsic_wo_chain:{ *:[v4f32] } 1250:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (FMAXNMQV_S:{ *:[v4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
63239 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMQV_S),
63240 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63241 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63242 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63243 GIR_RootConstrainSelectedInstOperands,
63244 // GIR_Coverage, 11791,
63245 GIR_EraseRootFromParent_Done,
63246 // Label 3664: @172608
63247 GIM_Try, /*On fail goto*//*Label 3665*/ GIMT_Encode4(172645), // Rule ID 11792 //
63248 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63249 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnmqv),
63250 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
63251 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
63252 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
63253 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63254 // (intrinsic_wo_chain:{ *:[v2f64] } 1250:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (FMAXNMQV_D:{ *:[v2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
63255 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMQV_D),
63256 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63257 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63258 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63259 GIR_RootConstrainSelectedInstOperands,
63260 // GIR_Coverage, 11792,
63261 GIR_EraseRootFromParent_Done,
63262 // Label 3665: @172645
63263 GIM_Try, /*On fail goto*//*Label 3666*/ GIMT_Encode4(172682), // Rule ID 11793 //
63264 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63265 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnmqv),
63266 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
63267 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
63268 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
63269 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63270 // (intrinsic_wo_chain:{ *:[v8f16] } 1268:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (FMINNMQV_H:{ *:[v8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
63271 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMQV_H),
63272 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63273 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63274 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63275 GIR_RootConstrainSelectedInstOperands,
63276 // GIR_Coverage, 11793,
63277 GIR_EraseRootFromParent_Done,
63278 // Label 3666: @172682
63279 GIM_Try, /*On fail goto*//*Label 3667*/ GIMT_Encode4(172719), // Rule ID 11794 //
63280 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63281 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnmqv),
63282 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
63283 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
63284 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
63285 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63286 // (intrinsic_wo_chain:{ *:[v4f32] } 1268:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (FMINNMQV_S:{ *:[v4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
63287 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMQV_S),
63288 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63289 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63290 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63291 GIR_RootConstrainSelectedInstOperands,
63292 // GIR_Coverage, 11794,
63293 GIR_EraseRootFromParent_Done,
63294 // Label 3667: @172719
63295 GIM_Try, /*On fail goto*//*Label 3668*/ GIMT_Encode4(172756), // Rule ID 11795 //
63296 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63297 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnmqv),
63298 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
63299 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
63300 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
63301 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63302 // (intrinsic_wo_chain:{ *:[v2f64] } 1268:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (FMINNMQV_D:{ *:[v2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
63303 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMQV_D),
63304 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63305 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63306 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63307 GIR_RootConstrainSelectedInstOperands,
63308 // GIR_Coverage, 11795,
63309 GIR_EraseRootFromParent_Done,
63310 // Label 3668: @172756
63311 GIM_Try, /*On fail goto*//*Label 3669*/ GIMT_Encode4(172793), // Rule ID 11796 //
63312 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63313 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxqv),
63314 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
63315 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
63316 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
63317 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63318 // (intrinsic_wo_chain:{ *:[v8f16] } 1253:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (FMAXQV_H:{ *:[v8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
63319 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXQV_H),
63320 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63321 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63322 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63323 GIR_RootConstrainSelectedInstOperands,
63324 // GIR_Coverage, 11796,
63325 GIR_EraseRootFromParent_Done,
63326 // Label 3669: @172793
63327 GIM_Try, /*On fail goto*//*Label 3670*/ GIMT_Encode4(172830), // Rule ID 11797 //
63328 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63329 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxqv),
63330 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
63331 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
63332 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
63333 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63334 // (intrinsic_wo_chain:{ *:[v4f32] } 1253:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (FMAXQV_S:{ *:[v4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
63335 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXQV_S),
63336 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63337 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63338 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63339 GIR_RootConstrainSelectedInstOperands,
63340 // GIR_Coverage, 11797,
63341 GIR_EraseRootFromParent_Done,
63342 // Label 3670: @172830
63343 GIM_Try, /*On fail goto*//*Label 3671*/ GIMT_Encode4(172867), // Rule ID 11798 //
63344 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63345 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxqv),
63346 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
63347 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
63348 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
63349 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63350 // (intrinsic_wo_chain:{ *:[v2f64] } 1253:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (FMAXQV_D:{ *:[v2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
63351 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXQV_D),
63352 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63353 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63354 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63355 GIR_RootConstrainSelectedInstOperands,
63356 // GIR_Coverage, 11798,
63357 GIR_EraseRootFromParent_Done,
63358 // Label 3671: @172867
63359 GIM_Try, /*On fail goto*//*Label 3672*/ GIMT_Encode4(172904), // Rule ID 11799 //
63360 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63361 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminqv),
63362 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
63363 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
63364 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
63365 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63366 // (intrinsic_wo_chain:{ *:[v8f16] } 1271:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (FMINQV_H:{ *:[v8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
63367 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINQV_H),
63368 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63369 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63370 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63371 GIR_RootConstrainSelectedInstOperands,
63372 // GIR_Coverage, 11799,
63373 GIR_EraseRootFromParent_Done,
63374 // Label 3672: @172904
63375 GIM_Try, /*On fail goto*//*Label 3673*/ GIMT_Encode4(172941), // Rule ID 11800 //
63376 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63377 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminqv),
63378 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
63379 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
63380 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
63381 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63382 // (intrinsic_wo_chain:{ *:[v4f32] } 1271:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (FMINQV_S:{ *:[v4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
63383 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINQV_S),
63384 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63385 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63386 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63387 GIR_RootConstrainSelectedInstOperands,
63388 // GIR_Coverage, 11800,
63389 GIR_EraseRootFromParent_Done,
63390 // Label 3673: @172941
63391 GIM_Try, /*On fail goto*//*Label 3674*/ GIMT_Encode4(172978), // Rule ID 11801 //
63392 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63393 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminqv),
63394 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
63395 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
63396 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
63397 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63398 // (intrinsic_wo_chain:{ *:[v2f64] } 1271:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (FMINQV_D:{ *:[v2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
63399 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINQV_D),
63400 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63401 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63402 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63403 GIR_RootConstrainSelectedInstOperands,
63404 // GIR_Coverage, 11801,
63405 GIR_EraseRootFromParent_Done,
63406 // Label 3674: @172978
63407 GIM_Try, /*On fail goto*//*Label 3675*/ GIMT_Encode4(173015), // Rule ID 11802 //
63408 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63409 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorqv),
63410 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
63411 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
63412 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
63413 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63414 // (intrinsic_wo_chain:{ *:[v16i8] } 1169:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (EORQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
63415 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORQV_VPZ_B),
63416 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63417 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63418 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63419 GIR_RootConstrainSelectedInstOperands,
63420 // GIR_Coverage, 11802,
63421 GIR_EraseRootFromParent_Done,
63422 // Label 3675: @173015
63423 GIM_Try, /*On fail goto*//*Label 3676*/ GIMT_Encode4(173052), // Rule ID 11803 //
63424 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63425 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorqv),
63426 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
63427 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
63428 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
63429 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63430 // (intrinsic_wo_chain:{ *:[v8i16] } 1169:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (EORQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
63431 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORQV_VPZ_H),
63432 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63433 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63434 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63435 GIR_RootConstrainSelectedInstOperands,
63436 // GIR_Coverage, 11803,
63437 GIR_EraseRootFromParent_Done,
63438 // Label 3676: @173052
63439 GIM_Try, /*On fail goto*//*Label 3677*/ GIMT_Encode4(173089), // Rule ID 11804 //
63440 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63441 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorqv),
63442 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
63443 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
63444 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
63445 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63446 // (intrinsic_wo_chain:{ *:[v4i32] } 1169:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (EORQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
63447 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORQV_VPZ_S),
63448 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63449 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63450 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63451 GIR_RootConstrainSelectedInstOperands,
63452 // GIR_Coverage, 11804,
63453 GIR_EraseRootFromParent_Done,
63454 // Label 3677: @173089
63455 GIM_Try, /*On fail goto*//*Label 3678*/ GIMT_Encode4(173126), // Rule ID 11805 //
63456 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63457 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorqv),
63458 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
63459 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
63460 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
63461 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63462 // (intrinsic_wo_chain:{ *:[v2i64] } 1169:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (EORQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
63463 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORQV_VPZ_D),
63464 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63465 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63466 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63467 GIR_RootConstrainSelectedInstOperands,
63468 // GIR_Coverage, 11805,
63469 GIR_EraseRootFromParent_Done,
63470 // Label 3678: @173126
63471 GIM_Try, /*On fail goto*//*Label 3679*/ GIMT_Encode4(173163), // Rule ID 11806 //
63472 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63473 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_andqv),
63474 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
63475 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
63476 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
63477 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63478 // (intrinsic_wo_chain:{ *:[v16i8] } 1081:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (ANDQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
63479 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDQV_VPZ_B),
63480 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63481 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63482 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63483 GIR_RootConstrainSelectedInstOperands,
63484 // GIR_Coverage, 11806,
63485 GIR_EraseRootFromParent_Done,
63486 // Label 3679: @173163
63487 GIM_Try, /*On fail goto*//*Label 3680*/ GIMT_Encode4(173200), // Rule ID 11807 //
63488 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63489 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_andqv),
63490 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
63491 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
63492 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
63493 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63494 // (intrinsic_wo_chain:{ *:[v8i16] } 1081:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (ANDQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
63495 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDQV_VPZ_H),
63496 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63497 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63498 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63499 GIR_RootConstrainSelectedInstOperands,
63500 // GIR_Coverage, 11807,
63501 GIR_EraseRootFromParent_Done,
63502 // Label 3680: @173200
63503 GIM_Try, /*On fail goto*//*Label 3681*/ GIMT_Encode4(173237), // Rule ID 11808 //
63504 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63505 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_andqv),
63506 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
63507 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
63508 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
63509 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63510 // (intrinsic_wo_chain:{ *:[v4i32] } 1081:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (ANDQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
63511 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDQV_VPZ_S),
63512 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63513 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63514 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63515 GIR_RootConstrainSelectedInstOperands,
63516 // GIR_Coverage, 11808,
63517 GIR_EraseRootFromParent_Done,
63518 // Label 3681: @173237
63519 GIM_Try, /*On fail goto*//*Label 3682*/ GIMT_Encode4(173274), // Rule ID 11809 //
63520 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63521 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_andqv),
63522 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
63523 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
63524 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
63525 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63526 // (intrinsic_wo_chain:{ *:[v2i64] } 1081:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (ANDQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
63527 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDQV_VPZ_D),
63528 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63529 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63530 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63531 GIR_RootConstrainSelectedInstOperands,
63532 // GIR_Coverage, 11809,
63533 GIR_EraseRootFromParent_Done,
63534 // Label 3682: @173274
63535 GIM_Try, /*On fail goto*//*Label 3683*/ GIMT_Encode4(173311), // Rule ID 11810 //
63536 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63537 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addqv),
63538 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
63539 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
63540 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
63541 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63542 // (intrinsic_wo_chain:{ *:[v16i8] } 1069:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (ADDQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
63543 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDQV_VPZ_B),
63544 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63545 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63546 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63547 GIR_RootConstrainSelectedInstOperands,
63548 // GIR_Coverage, 11810,
63549 GIR_EraseRootFromParent_Done,
63550 // Label 3683: @173311
63551 GIM_Try, /*On fail goto*//*Label 3684*/ GIMT_Encode4(173348), // Rule ID 11811 //
63552 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63553 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addqv),
63554 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
63555 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
63556 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
63557 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63558 // (intrinsic_wo_chain:{ *:[v8i16] } 1069:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (ADDQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
63559 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDQV_VPZ_H),
63560 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63561 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63562 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63563 GIR_RootConstrainSelectedInstOperands,
63564 // GIR_Coverage, 11811,
63565 GIR_EraseRootFromParent_Done,
63566 // Label 3684: @173348
63567 GIM_Try, /*On fail goto*//*Label 3685*/ GIMT_Encode4(173385), // Rule ID 11812 //
63568 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63569 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addqv),
63570 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
63571 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
63572 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
63573 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63574 // (intrinsic_wo_chain:{ *:[v4i32] } 1069:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (ADDQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
63575 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDQV_VPZ_S),
63576 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63577 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63578 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63579 GIR_RootConstrainSelectedInstOperands,
63580 // GIR_Coverage, 11812,
63581 GIR_EraseRootFromParent_Done,
63582 // Label 3685: @173385
63583 GIM_Try, /*On fail goto*//*Label 3686*/ GIMT_Encode4(173422), // Rule ID 11813 //
63584 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63585 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addqv),
63586 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
63587 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
63588 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
63589 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63590 // (intrinsic_wo_chain:{ *:[v2i64] } 1069:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (ADDQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
63591 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDQV_VPZ_D),
63592 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63593 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63594 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63595 GIR_RootConstrainSelectedInstOperands,
63596 // GIR_Coverage, 11813,
63597 GIR_EraseRootFromParent_Done,
63598 // Label 3686: @173422
63599 GIM_Try, /*On fail goto*//*Label 3687*/ GIMT_Encode4(173459), // Rule ID 11814 //
63600 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63601 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxqv),
63602 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
63603 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
63604 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
63605 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63606 // (intrinsic_wo_chain:{ *:[v16i8] } 1513:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SMAXQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
63607 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXQV_VPZ_B),
63608 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63609 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63610 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63611 GIR_RootConstrainSelectedInstOperands,
63612 // GIR_Coverage, 11814,
63613 GIR_EraseRootFromParent_Done,
63614 // Label 3687: @173459
63615 GIM_Try, /*On fail goto*//*Label 3688*/ GIMT_Encode4(173496), // Rule ID 11815 //
63616 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63617 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxqv),
63618 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
63619 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
63620 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
63621 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63622 // (intrinsic_wo_chain:{ *:[v8i16] } 1513:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SMAXQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
63623 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXQV_VPZ_H),
63624 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63625 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63626 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63627 GIR_RootConstrainSelectedInstOperands,
63628 // GIR_Coverage, 11815,
63629 GIR_EraseRootFromParent_Done,
63630 // Label 3688: @173496
63631 GIM_Try, /*On fail goto*//*Label 3689*/ GIMT_Encode4(173533), // Rule ID 11816 //
63632 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63633 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxqv),
63634 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
63635 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
63636 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
63637 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63638 // (intrinsic_wo_chain:{ *:[v4i32] } 1513:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SMAXQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
63639 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXQV_VPZ_S),
63640 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63641 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63642 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63643 GIR_RootConstrainSelectedInstOperands,
63644 // GIR_Coverage, 11816,
63645 GIR_EraseRootFromParent_Done,
63646 // Label 3689: @173533
63647 GIM_Try, /*On fail goto*//*Label 3690*/ GIMT_Encode4(173570), // Rule ID 11817 //
63648 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63649 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxqv),
63650 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
63651 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
63652 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
63653 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63654 // (intrinsic_wo_chain:{ *:[v2i64] } 1513:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (SMAXQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
63655 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXQV_VPZ_D),
63656 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63657 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63658 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63659 GIR_RootConstrainSelectedInstOperands,
63660 // GIR_Coverage, 11817,
63661 GIR_EraseRootFromParent_Done,
63662 // Label 3690: @173570
63663 GIM_Try, /*On fail goto*//*Label 3691*/ GIMT_Encode4(173607), // Rule ID 11818 //
63664 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63665 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxqv),
63666 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
63667 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
63668 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
63669 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63670 // (intrinsic_wo_chain:{ *:[v16i8] } 1751:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (UMAXQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
63671 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXQV_VPZ_B),
63672 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63673 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63674 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63675 GIR_RootConstrainSelectedInstOperands,
63676 // GIR_Coverage, 11818,
63677 GIR_EraseRootFromParent_Done,
63678 // Label 3691: @173607
63679 GIM_Try, /*On fail goto*//*Label 3692*/ GIMT_Encode4(173644), // Rule ID 11819 //
63680 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63681 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxqv),
63682 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
63683 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
63684 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
63685 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63686 // (intrinsic_wo_chain:{ *:[v8i16] } 1751:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (UMAXQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
63687 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXQV_VPZ_H),
63688 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63689 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63690 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63691 GIR_RootConstrainSelectedInstOperands,
63692 // GIR_Coverage, 11819,
63693 GIR_EraseRootFromParent_Done,
63694 // Label 3692: @173644
63695 GIM_Try, /*On fail goto*//*Label 3693*/ GIMT_Encode4(173681), // Rule ID 11820 //
63696 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63697 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxqv),
63698 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
63699 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
63700 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
63701 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63702 // (intrinsic_wo_chain:{ *:[v4i32] } 1751:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (UMAXQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
63703 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXQV_VPZ_S),
63704 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63705 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63706 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63707 GIR_RootConstrainSelectedInstOperands,
63708 // GIR_Coverage, 11820,
63709 GIR_EraseRootFromParent_Done,
63710 // Label 3693: @173681
63711 GIM_Try, /*On fail goto*//*Label 3694*/ GIMT_Encode4(173718), // Rule ID 11821 //
63712 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63713 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxqv),
63714 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
63715 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
63716 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
63717 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63718 // (intrinsic_wo_chain:{ *:[v2i64] } 1751:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (UMAXQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
63719 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXQV_VPZ_D),
63720 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63721 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63722 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63723 GIR_RootConstrainSelectedInstOperands,
63724 // GIR_Coverage, 11821,
63725 GIR_EraseRootFromParent_Done,
63726 // Label 3694: @173718
63727 GIM_Try, /*On fail goto*//*Label 3695*/ GIMT_Encode4(173755), // Rule ID 11822 //
63728 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63729 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminqv),
63730 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
63731 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
63732 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
63733 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63734 // (intrinsic_wo_chain:{ *:[v16i8] } 1522:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SMINQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
63735 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINQV_VPZ_B),
63736 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63737 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63738 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63739 GIR_RootConstrainSelectedInstOperands,
63740 // GIR_Coverage, 11822,
63741 GIR_EraseRootFromParent_Done,
63742 // Label 3695: @173755
63743 GIM_Try, /*On fail goto*//*Label 3696*/ GIMT_Encode4(173792), // Rule ID 11823 //
63744 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63745 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminqv),
63746 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
63747 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
63748 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
63749 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63750 // (intrinsic_wo_chain:{ *:[v8i16] } 1522:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SMINQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
63751 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINQV_VPZ_H),
63752 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63753 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63754 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63755 GIR_RootConstrainSelectedInstOperands,
63756 // GIR_Coverage, 11823,
63757 GIR_EraseRootFromParent_Done,
63758 // Label 3696: @173792
63759 GIM_Try, /*On fail goto*//*Label 3697*/ GIMT_Encode4(173829), // Rule ID 11824 //
63760 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63761 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminqv),
63762 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
63763 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
63764 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
63765 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63766 // (intrinsic_wo_chain:{ *:[v4i32] } 1522:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SMINQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
63767 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINQV_VPZ_S),
63768 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63769 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63770 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63771 GIR_RootConstrainSelectedInstOperands,
63772 // GIR_Coverage, 11824,
63773 GIR_EraseRootFromParent_Done,
63774 // Label 3697: @173829
63775 GIM_Try, /*On fail goto*//*Label 3698*/ GIMT_Encode4(173866), // Rule ID 11825 //
63776 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63777 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminqv),
63778 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
63779 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
63780 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
63781 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63782 // (intrinsic_wo_chain:{ *:[v2i64] } 1522:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (SMINQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
63783 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINQV_VPZ_D),
63784 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63785 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63786 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63787 GIR_RootConstrainSelectedInstOperands,
63788 // GIR_Coverage, 11825,
63789 GIR_EraseRootFromParent_Done,
63790 // Label 3698: @173866
63791 GIM_Try, /*On fail goto*//*Label 3699*/ GIMT_Encode4(173903), // Rule ID 11826 //
63792 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63793 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminqv),
63794 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
63795 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
63796 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
63797 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63798 // (intrinsic_wo_chain:{ *:[v16i8] } 1760:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (UMINQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
63799 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINQV_VPZ_B),
63800 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63801 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63802 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63803 GIR_RootConstrainSelectedInstOperands,
63804 // GIR_Coverage, 11826,
63805 GIR_EraseRootFromParent_Done,
63806 // Label 3699: @173903
63807 GIM_Try, /*On fail goto*//*Label 3700*/ GIMT_Encode4(173940), // Rule ID 11827 //
63808 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63809 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminqv),
63810 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
63811 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
63812 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
63813 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63814 // (intrinsic_wo_chain:{ *:[v8i16] } 1760:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (UMINQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
63815 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINQV_VPZ_H),
63816 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63817 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63818 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63819 GIR_RootConstrainSelectedInstOperands,
63820 // GIR_Coverage, 11827,
63821 GIR_EraseRootFromParent_Done,
63822 // Label 3700: @173940
63823 GIM_Try, /*On fail goto*//*Label 3701*/ GIMT_Encode4(173977), // Rule ID 11828 //
63824 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63825 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminqv),
63826 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
63827 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
63828 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
63829 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63830 // (intrinsic_wo_chain:{ *:[v4i32] } 1760:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (UMINQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
63831 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINQV_VPZ_S),
63832 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63833 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63834 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63835 GIR_RootConstrainSelectedInstOperands,
63836 // GIR_Coverage, 11828,
63837 GIR_EraseRootFromParent_Done,
63838 // Label 3701: @173977
63839 GIM_Try, /*On fail goto*//*Label 3702*/ GIMT_Encode4(174014), // Rule ID 11829 //
63840 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63841 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminqv),
63842 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
63843 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
63844 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
63845 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
63846 // (intrinsic_wo_chain:{ *:[v2i64] } 1760:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (UMINQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
63847 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINQV_VPZ_D),
63848 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
63849 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63850 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63851 GIR_RootConstrainSelectedInstOperands,
63852 // GIR_Coverage, 11829,
63853 GIR_EraseRootFromParent_Done,
63854 // Label 3702: @174014
63855 GIM_Try, /*On fail goto*//*Label 3703*/ GIMT_Encode4(174051), // Rule ID 11830 //
63856 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63857 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
63858 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
63859 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
63860 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
63861 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63862 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1944:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (ZIPQ2_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
63863 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_B),
63864 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
63865 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63866 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63867 GIR_RootConstrainSelectedInstOperands,
63868 // GIR_Coverage, 11830,
63869 GIR_EraseRootFromParent_Done,
63870 // Label 3703: @174051
63871 GIM_Try, /*On fail goto*//*Label 3704*/ GIMT_Encode4(174088), // Rule ID 11831 //
63872 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63873 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
63874 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
63875 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
63876 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
63877 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63878 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1944:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (ZIPQ2_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
63879 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_H),
63880 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
63881 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63882 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63883 GIR_RootConstrainSelectedInstOperands,
63884 // GIR_Coverage, 11831,
63885 GIR_EraseRootFromParent_Done,
63886 // Label 3704: @174088
63887 GIM_Try, /*On fail goto*//*Label 3705*/ GIMT_Encode4(174125), // Rule ID 11832 //
63888 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63889 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
63890 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
63891 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
63892 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
63893 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63894 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1944:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (ZIPQ2_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
63895 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_S),
63896 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
63897 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63898 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63899 GIR_RootConstrainSelectedInstOperands,
63900 // GIR_Coverage, 11832,
63901 GIR_EraseRootFromParent_Done,
63902 // Label 3705: @174125
63903 GIM_Try, /*On fail goto*//*Label 3706*/ GIMT_Encode4(174162), // Rule ID 11833 //
63904 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63905 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
63906 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
63907 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
63908 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
63909 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63910 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1944:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (ZIPQ2_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
63911 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_D),
63912 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
63913 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63914 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63915 GIR_RootConstrainSelectedInstOperands,
63916 // GIR_Coverage, 11833,
63917 GIR_EraseRootFromParent_Done,
63918 // Label 3706: @174162
63919 GIM_Try, /*On fail goto*//*Label 3707*/ GIMT_Encode4(174199), // Rule ID 11834 //
63920 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63921 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
63922 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
63923 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
63924 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
63925 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63926 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1944:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (ZIPQ2_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
63927 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_H),
63928 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
63929 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63930 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63931 GIR_RootConstrainSelectedInstOperands,
63932 // GIR_Coverage, 11834,
63933 GIR_EraseRootFromParent_Done,
63934 // Label 3707: @174199
63935 GIM_Try, /*On fail goto*//*Label 3708*/ GIMT_Encode4(174236), // Rule ID 11835 //
63936 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63937 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
63938 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
63939 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
63940 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
63941 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63942 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1944:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (ZIPQ2_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
63943 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_S),
63944 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
63945 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63946 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63947 GIR_RootConstrainSelectedInstOperands,
63948 // GIR_Coverage, 11835,
63949 GIR_EraseRootFromParent_Done,
63950 // Label 3708: @174236
63951 GIM_Try, /*On fail goto*//*Label 3709*/ GIMT_Encode4(174273), // Rule ID 11836 //
63952 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63953 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
63954 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
63955 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
63956 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
63957 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63958 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1944:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (ZIPQ2_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
63959 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_D),
63960 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
63961 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63962 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63963 GIR_RootConstrainSelectedInstOperands,
63964 // GIR_Coverage, 11836,
63965 GIR_EraseRootFromParent_Done,
63966 // Label 3709: @174273
63967 GIM_Try, /*On fail goto*//*Label 3710*/ GIMT_Encode4(174310), // Rule ID 11837 //
63968 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63969 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
63970 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
63971 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
63972 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
63973 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63974 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1944:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2) => (ZIPQ2_ZZZ_H:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2)
63975 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_H),
63976 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
63977 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63978 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63979 GIR_RootConstrainSelectedInstOperands,
63980 // GIR_Coverage, 11837,
63981 GIR_EraseRootFromParent_Done,
63982 // Label 3710: @174310
63983 GIM_Try, /*On fail goto*//*Label 3711*/ GIMT_Encode4(174347), // Rule ID 11838 //
63984 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
63985 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
63986 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
63987 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
63988 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
63989 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
63990 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1869:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (UZPQ1_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
63991 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_B),
63992 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
63993 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
63994 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
63995 GIR_RootConstrainSelectedInstOperands,
63996 // GIR_Coverage, 11838,
63997 GIR_EraseRootFromParent_Done,
63998 // Label 3711: @174347
63999 GIM_Try, /*On fail goto*//*Label 3712*/ GIMT_Encode4(174384), // Rule ID 11839 //
64000 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
64001 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
64002 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
64003 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
64004 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
64005 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
64006 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1869:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (UZPQ1_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
64007 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_H),
64008 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
64009 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64010 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64011 GIR_RootConstrainSelectedInstOperands,
64012 // GIR_Coverage, 11839,
64013 GIR_EraseRootFromParent_Done,
64014 // Label 3712: @174384
64015 GIM_Try, /*On fail goto*//*Label 3713*/ GIMT_Encode4(174421), // Rule ID 11840 //
64016 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
64017 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
64018 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
64019 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
64020 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
64021 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
64022 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1869:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (UZPQ1_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
64023 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_S),
64024 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
64025 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64026 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64027 GIR_RootConstrainSelectedInstOperands,
64028 // GIR_Coverage, 11840,
64029 GIR_EraseRootFromParent_Done,
64030 // Label 3713: @174421
64031 GIM_Try, /*On fail goto*//*Label 3714*/ GIMT_Encode4(174458), // Rule ID 11841 //
64032 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
64033 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
64034 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
64035 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
64036 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
64037 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
64038 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1869:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (UZPQ1_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
64039 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_D),
64040 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
64041 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64042 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64043 GIR_RootConstrainSelectedInstOperands,
64044 // GIR_Coverage, 11841,
64045 GIR_EraseRootFromParent_Done,
64046 // Label 3714: @174458
64047 GIM_Try, /*On fail goto*//*Label 3715*/ GIMT_Encode4(174495), // Rule ID 11842 //
64048 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
64049 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
64050 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
64051 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
64052 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
64053 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
64054 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1869:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (UZPQ1_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
64055 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_H),
64056 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
64057 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64058 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64059 GIR_RootConstrainSelectedInstOperands,
64060 // GIR_Coverage, 11842,
64061 GIR_EraseRootFromParent_Done,
64062 // Label 3715: @174495
64063 GIM_Try, /*On fail goto*//*Label 3716*/ GIMT_Encode4(174532), // Rule ID 11843 //
64064 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
64065 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
64066 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
64067 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
64068 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
64069 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
64070 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1869:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (UZPQ1_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
64071 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_S),
64072 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
64073 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64074 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64075 GIR_RootConstrainSelectedInstOperands,
64076 // GIR_Coverage, 11843,
64077 GIR_EraseRootFromParent_Done,
64078 // Label 3716: @174532
64079 GIM_Try, /*On fail goto*//*Label 3717*/ GIMT_Encode4(174569), // Rule ID 11844 //
64080 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
64081 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
64082 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
64083 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
64084 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
64085 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
64086 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1869:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (UZPQ1_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
64087 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_D),
64088 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
64089 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64090 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64091 GIR_RootConstrainSelectedInstOperands,
64092 // GIR_Coverage, 11844,
64093 GIR_EraseRootFromParent_Done,
64094 // Label 3717: @174569
64095 GIM_Try, /*On fail goto*//*Label 3718*/ GIMT_Encode4(174606), // Rule ID 11845 //
64096 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
64097 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
64098 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
64099 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
64100 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
64101 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
64102 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1869:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2) => (UZPQ1_ZZZ_H:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2)
64103 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_H),
64104 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
64105 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64106 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64107 GIR_RootConstrainSelectedInstOperands,
64108 // GIR_Coverage, 11845,
64109 GIR_EraseRootFromParent_Done,
64110 // Label 3718: @174606
64111 GIM_Try, /*On fail goto*//*Label 3719*/ GIMT_Encode4(174643), // Rule ID 11846 //
64112 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
64113 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
64114 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
64115 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
64116 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
64117 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
64118 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1870:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (UZPQ2_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
64119 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_B),
64120 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
64121 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64122 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64123 GIR_RootConstrainSelectedInstOperands,
64124 // GIR_Coverage, 11846,
64125 GIR_EraseRootFromParent_Done,
64126 // Label 3719: @174643
64127 GIM_Try, /*On fail goto*//*Label 3720*/ GIMT_Encode4(174680), // Rule ID 11847 //
64128 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
64129 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
64130 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
64131 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
64132 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
64133 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
64134 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1870:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (UZPQ2_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
64135 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_H),
64136 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
64137 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64138 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64139 GIR_RootConstrainSelectedInstOperands,
64140 // GIR_Coverage, 11847,
64141 GIR_EraseRootFromParent_Done,
64142 // Label 3720: @174680
64143 GIM_Try, /*On fail goto*//*Label 3721*/ GIMT_Encode4(174717), // Rule ID 11848 //
64144 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
64145 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
64146 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
64147 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
64148 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
64149 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
64150 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1870:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (UZPQ2_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
64151 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_S),
64152 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
64153 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64154 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64155 GIR_RootConstrainSelectedInstOperands,
64156 // GIR_Coverage, 11848,
64157 GIR_EraseRootFromParent_Done,
64158 // Label 3721: @174717
64159 GIM_Try, /*On fail goto*//*Label 3722*/ GIMT_Encode4(174754), // Rule ID 11849 //
64160 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
64161 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
64162 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
64163 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
64164 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
64165 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
64166 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1870:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (UZPQ2_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
64167 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_D),
64168 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
64169 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64170 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64171 GIR_RootConstrainSelectedInstOperands,
64172 // GIR_Coverage, 11849,
64173 GIR_EraseRootFromParent_Done,
64174 // Label 3722: @174754
64175 GIM_Try, /*On fail goto*//*Label 3723*/ GIMT_Encode4(174791), // Rule ID 11850 //
64176 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
64177 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
64178 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
64179 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
64180 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
64181 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
64182 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1870:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (UZPQ2_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
64183 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_H),
64184 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
64185 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64186 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64187 GIR_RootConstrainSelectedInstOperands,
64188 // GIR_Coverage, 11850,
64189 GIR_EraseRootFromParent_Done,
64190 // Label 3723: @174791
64191 GIM_Try, /*On fail goto*//*Label 3724*/ GIMT_Encode4(174828), // Rule ID 11851 //
64192 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
64193 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
64194 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
64195 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
64196 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
64197 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
64198 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1870:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (UZPQ2_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
64199 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_S),
64200 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
64201 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64202 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64203 GIR_RootConstrainSelectedInstOperands,
64204 // GIR_Coverage, 11851,
64205 GIR_EraseRootFromParent_Done,
64206 // Label 3724: @174828
64207 GIM_Try, /*On fail goto*//*Label 3725*/ GIMT_Encode4(174865), // Rule ID 11852 //
64208 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
64209 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
64210 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
64211 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
64212 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
64213 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
64214 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1870:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (UZPQ2_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
64215 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_D),
64216 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
64217 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64218 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64219 GIR_RootConstrainSelectedInstOperands,
64220 // GIR_Coverage, 11852,
64221 GIR_EraseRootFromParent_Done,
64222 // Label 3725: @174865
64223 GIM_Try, /*On fail goto*//*Label 3726*/ GIMT_Encode4(174902), // Rule ID 11853 //
64224 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
64225 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
64226 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
64227 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
64228 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
64229 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
64230 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1870:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2) => (UZPQ2_ZZZ_H:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2)
64231 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_H),
64232 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
64233 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64234 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64235 GIR_RootConstrainSelectedInstOperands,
64236 // GIR_Coverage, 11853,
64237 GIR_EraseRootFromParent_Done,
64238 // Label 3726: @174902
64239 GIM_Try, /*On fail goto*//*Label 3727*/ GIMT_Encode4(174944), // Rule ID 3129 //
64240 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
64241 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilewr_b),
64242 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
64243 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
64244 // MIs[0] Op1
64245 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
64246 // MIs[0] Op2
64247 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
64248 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1923:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEWR_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
64249 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEWR_PXX_B),
64250 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
64251 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64252 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64253 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
64254 GIR_RootConstrainSelectedInstOperands,
64255 // GIR_Coverage, 3129,
64256 GIR_EraseRootFromParent_Done,
64257 // Label 3727: @174944
64258 GIM_Try, /*On fail goto*//*Label 3728*/ GIMT_Encode4(174986), // Rule ID 3130 //
64259 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
64260 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilewr_h),
64261 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
64262 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
64263 // MIs[0] Op1
64264 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
64265 // MIs[0] Op2
64266 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
64267 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1925:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEWR_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
64268 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEWR_PXX_H),
64269 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
64270 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64271 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64272 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
64273 GIR_RootConstrainSelectedInstOperands,
64274 // GIR_Coverage, 3130,
64275 GIR_EraseRootFromParent_Done,
64276 // Label 3728: @174986
64277 GIM_Try, /*On fail goto*//*Label 3729*/ GIMT_Encode4(175028), // Rule ID 3131 //
64278 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
64279 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilewr_s),
64280 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
64281 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
64282 // MIs[0] Op1
64283 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
64284 // MIs[0] Op2
64285 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
64286 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1926:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEWR_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
64287 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEWR_PXX_S),
64288 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
64289 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64290 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64291 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
64292 GIR_RootConstrainSelectedInstOperands,
64293 // GIR_Coverage, 3131,
64294 GIR_EraseRootFromParent_Done,
64295 // Label 3729: @175028
64296 GIM_Try, /*On fail goto*//*Label 3730*/ GIMT_Encode4(175070), // Rule ID 3132 //
64297 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
64298 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilewr_d),
64299 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
64300 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
64301 // MIs[0] Op1
64302 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
64303 // MIs[0] Op2
64304 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
64305 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1924:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILEWR_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
64306 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEWR_PXX_D),
64307 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
64308 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64309 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64310 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
64311 GIR_RootConstrainSelectedInstOperands,
64312 // GIR_Coverage, 3132,
64313 GIR_EraseRootFromParent_Done,
64314 // Label 3730: @175070
64315 GIM_Try, /*On fail goto*//*Label 3731*/ GIMT_Encode4(175112), // Rule ID 11620 //
64316 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
64317 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilerw_b),
64318 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
64319 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
64320 // MIs[0] Op1
64321 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
64322 // MIs[0] Op2
64323 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
64324 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1919:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILERW_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
64325 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILERW_PXX_B),
64326 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
64327 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64328 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64329 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
64330 GIR_RootConstrainSelectedInstOperands,
64331 // GIR_Coverage, 11620,
64332 GIR_EraseRootFromParent_Done,
64333 // Label 3731: @175112
64334 GIM_Try, /*On fail goto*//*Label 3732*/ GIMT_Encode4(175154), // Rule ID 11621 //
64335 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
64336 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilerw_h),
64337 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
64338 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
64339 // MIs[0] Op1
64340 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
64341 // MIs[0] Op2
64342 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
64343 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1921:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILERW_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
64344 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILERW_PXX_H),
64345 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
64346 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64347 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64348 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
64349 GIR_RootConstrainSelectedInstOperands,
64350 // GIR_Coverage, 11621,
64351 GIR_EraseRootFromParent_Done,
64352 // Label 3732: @175154
64353 GIM_Try, /*On fail goto*//*Label 3733*/ GIMT_Encode4(175196), // Rule ID 11622 //
64354 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
64355 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilerw_s),
64356 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
64357 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
64358 // MIs[0] Op1
64359 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
64360 // MIs[0] Op2
64361 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
64362 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1922:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILERW_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
64363 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILERW_PXX_S),
64364 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
64365 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64366 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64367 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
64368 GIR_RootConstrainSelectedInstOperands,
64369 // GIR_Coverage, 11622,
64370 GIR_EraseRootFromParent_Done,
64371 // Label 3733: @175196
64372 GIM_Try, /*On fail goto*//*Label 3734*/ GIMT_Encode4(175238), // Rule ID 11623 //
64373 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
64374 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilerw_d),
64375 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
64376 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
64377 // MIs[0] Op1
64378 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
64379 // MIs[0] Op2
64380 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
64381 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1920:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2) => (WHILERW_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
64382 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILERW_PXX_D),
64383 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
64384 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
64385 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
64386 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
64387 GIR_RootConstrainSelectedInstOperands,
64388 // GIR_Coverage, 11623,
64389 GIR_EraseRootFromParent_Done,
64390 // Label 3734: @175238
64391 GIM_Reject,
64392 // Label 2781: @175239
64393 GIM_Try, /*On fail goto*//*Label 3735*/ GIMT_Encode4(213740),
64394 GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
64395 GIM_Try, /*On fail goto*//*Label 3736*/ GIMT_Encode4(175349), // Rule ID 49 //
64396 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
64397 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usdot),
64398 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
64399 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
64400 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
64401 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
64402 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
64403 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
64404 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
64405 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
64406 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
64407 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
64408 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
64409 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
64410 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
64411 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
64412 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
64413 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
64414 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
64415 // MIs[3] Operand 1
64416 // No operand predicates
64417 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
64418 GIM_CheckIsSafeToFold, /*NumInsns*/3,
64419 // (intrinsic_wo_chain:{ *:[v2i32] } 712:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, (bitconvert:{ *:[v8i8] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V64:{ *:[v8i8] }:$Rn) => (SUDOTlanev8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
64420 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUDOTlanev8i8),
64421 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
64422 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
64423 GIR_RootToRootCopy, /*OpIdx*/4, // Rn
64424 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
64425 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
64426 GIR_RootConstrainSelectedInstOperands,
64427 // GIR_Coverage, 49,
64428 GIR_EraseRootFromParent_Done,
64429 // Label 3736: @175349
64430 GIM_Try, /*On fail goto*//*Label 3737*/ GIMT_Encode4(175451), // Rule ID 50 //
64431 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
64432 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usdot),
64433 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
64434 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
64435 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
64436 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
64437 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
64438 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
64439 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
64440 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
64441 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
64442 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
64443 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
64444 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
64445 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
64446 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
64447 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
64448 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
64449 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
64450 // MIs[3] Operand 1
64451 // No operand predicates
64452 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
64453 GIM_CheckIsSafeToFold, /*NumInsns*/3,
64454 // (intrinsic_wo_chain:{ *:[v4i32] } 712:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, (bitconvert:{ *:[v16i8] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v16i8] }:$Rn) => (SUDOTlanev16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
64455 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUDOTlanev16i8),
64456 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
64457 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
64458 GIR_RootToRootCopy, /*OpIdx*/4, // Rn
64459 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
64460 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
64461 GIR_RootConstrainSelectedInstOperands,
64462 // GIR_Coverage, 50,
64463 GIR_EraseRootFromParent_Done,
64464 // Label 3737: @175451
64465 GIM_Try, /*On fail goto*//*Label 3738*/ GIMT_Encode4(175553), // Rule ID 32 //
64466 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON),
64467 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_bfdot),
64468 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
64469 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
64470 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
64471 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
64472 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
64473 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
64474 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
64475 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
64476 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
64477 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
64478 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
64479 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
64480 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
64481 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
64482 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
64483 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
64484 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
64485 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
64486 // MIs[3] Operand 1
64487 // No operand predicates
64488 GIM_CheckIsSafeToFold, /*NumInsns*/3,
64489 // (intrinsic_wo_chain:{ *:[v2f32] } 556:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4bf16] }:$Rn, (bitconvert:{ *:[v4bf16] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (BF16DOTlanev4bf16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4bf16] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
64490 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BF16DOTlanev4bf16),
64491 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
64492 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
64493 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
64494 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
64495 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
64496 GIR_RootConstrainSelectedInstOperands,
64497 // GIR_Coverage, 32,
64498 GIR_EraseRootFromParent_Done,
64499 // Label 3738: @175553
64500 GIM_Try, /*On fail goto*//*Label 3739*/ GIMT_Encode4(175655), // Rule ID 33 //
64501 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON),
64502 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_bfdot),
64503 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
64504 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
64505 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
64506 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
64507 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
64508 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
64509 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
64510 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
64511 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
64512 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
64513 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
64514 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
64515 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
64516 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
64517 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
64518 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
64519 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
64520 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
64521 // MIs[3] Operand 1
64522 // No operand predicates
64523 GIM_CheckIsSafeToFold, /*NumInsns*/3,
64524 // (intrinsic_wo_chain:{ *:[v4f32] } 556:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, (bitconvert:{ *:[v8bf16] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (BF16DOTlanev8bf16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
64525 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BF16DOTlanev8bf16),
64526 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
64527 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
64528 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
64529 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
64530 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
64531 GIR_RootConstrainSelectedInstOperands,
64532 // GIR_Coverage, 33,
64533 GIR_EraseRootFromParent_Done,
64534 // Label 3739: @175655
64535 GIM_Try, /*On fail goto*//*Label 3740*/ GIMT_Encode4(175757), // Rule ID 47 //
64536 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
64537 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usdot),
64538 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
64539 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
64540 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
64541 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
64542 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
64543 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
64544 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
64545 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
64546 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
64547 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
64548 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
64549 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
64550 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
64551 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
64552 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
64553 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
64554 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
64555 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
64556 // MIs[3] Operand 1
64557 // No operand predicates
64558 GIM_CheckIsSafeToFold, /*NumInsns*/3,
64559 // (intrinsic_wo_chain:{ *:[v2i32] } 712:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, (bitconvert:{ *:[v8i8] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (USDOTlanev8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
64560 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USDOTlanev8i8),
64561 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
64562 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
64563 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
64564 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
64565 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
64566 GIR_RootConstrainSelectedInstOperands,
64567 // GIR_Coverage, 47,
64568 GIR_EraseRootFromParent_Done,
64569 // Label 3740: @175757
64570 GIM_Try, /*On fail goto*//*Label 3741*/ GIMT_Encode4(175859), // Rule ID 48 //
64571 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
64572 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usdot),
64573 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
64574 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
64575 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
64576 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
64577 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
64578 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
64579 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
64580 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
64581 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
64582 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
64583 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
64584 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
64585 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
64586 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
64587 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
64588 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
64589 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
64590 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
64591 // MIs[3] Operand 1
64592 // No operand predicates
64593 GIM_CheckIsSafeToFold, /*NumInsns*/3,
64594 // (intrinsic_wo_chain:{ *:[v4i32] } 712:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, (bitconvert:{ *:[v16i8] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (USDOTlanev16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
64595 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USDOTlanev16i8),
64596 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
64597 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
64598 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
64599 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
64600 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
64601 GIR_RootConstrainSelectedInstOperands,
64602 // GIR_Coverage, 48,
64603 GIR_EraseRootFromParent_Done,
64604 // Label 3741: @175859
64605 GIM_Try, /*On fail goto*//*Label 3742*/ GIMT_Encode4(175913), // Rule ID 71 //
64606 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
64607 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign),
64608 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
64609 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
64610 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
64611 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64612 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64613 // MIs[0] Operand 3
64614 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
64615 GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
64616 // (intrinsic_wo_chain:{ *:[i64] } 287:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 0:{ *:[i32] }, 0:{ *:[i64] }) => (PACIZA:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
64617 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PACIZA),
64618 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
64619 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
64620 GIR_RootConstrainSelectedInstOperands,
64621 // GIR_Coverage, 71,
64622 GIR_EraseRootFromParent_Done,
64623 // Label 3742: @175913
64624 GIM_Try, /*On fail goto*//*Label 3743*/ GIMT_Encode4(175967), // Rule ID 72 //
64625 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
64626 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign),
64627 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
64628 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
64629 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
64630 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64631 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64632 // MIs[0] Operand 3
64633 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(2),
64634 GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
64635 // (intrinsic_wo_chain:{ *:[i64] } 287:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 2:{ *:[i32] }, 0:{ *:[i64] }) => (PACDZA:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
64636 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PACDZA),
64637 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
64638 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
64639 GIR_RootConstrainSelectedInstOperands,
64640 // GIR_Coverage, 72,
64641 GIR_EraseRootFromParent_Done,
64642 // Label 3743: @175967
64643 GIM_Try, /*On fail goto*//*Label 3744*/ GIMT_Encode4(176021), // Rule ID 73 //
64644 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
64645 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign),
64646 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
64647 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
64648 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
64649 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64650 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64651 // MIs[0] Operand 3
64652 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(1),
64653 GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
64654 // (intrinsic_wo_chain:{ *:[i64] } 287:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 1:{ *:[i32] }, 0:{ *:[i64] }) => (PACIZB:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
64655 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PACIZB),
64656 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
64657 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
64658 GIR_RootConstrainSelectedInstOperands,
64659 // GIR_Coverage, 73,
64660 GIR_EraseRootFromParent_Done,
64661 // Label 3744: @176021
64662 GIM_Try, /*On fail goto*//*Label 3745*/ GIMT_Encode4(176075), // Rule ID 74 //
64663 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
64664 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign),
64665 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
64666 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
64667 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
64668 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64669 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64670 // MIs[0] Operand 3
64671 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(3),
64672 GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
64673 // (intrinsic_wo_chain:{ *:[i64] } 287:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 3:{ *:[i32] }, 0:{ *:[i64] }) => (PACDZB:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
64674 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PACDZB),
64675 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
64676 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
64677 GIR_RootConstrainSelectedInstOperands,
64678 // GIR_Coverage, 74,
64679 GIR_EraseRootFromParent_Done,
64680 // Label 3745: @176075
64681 GIM_Try, /*On fail goto*//*Label 3746*/ GIMT_Encode4(176131), // Rule ID 2551 //
64682 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
64683 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqinch),
64684 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
64685 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
64686 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
64687 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
64688 // MIs[0] pattern
64689 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
64690 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
64691 // MIs[0] imm4
64692 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
64693 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
64694 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1591:{ *:[iPTR] }, ZPR16:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (SQINCH_ZPiI:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
64695 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCH_ZPiI),
64696 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
64697 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
64698 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
64699 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
64700 GIR_RootConstrainSelectedInstOperands,
64701 // GIR_Coverage, 2551,
64702 GIR_EraseRootFromParent_Done,
64703 // Label 3746: @176131
64704 GIM_Try, /*On fail goto*//*Label 3747*/ GIMT_Encode4(176187), // Rule ID 2560 //
64705 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
64706 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincb_n32),
64707 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
64708 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
64709 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
64710 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
64711 // MIs[0] pattern
64712 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
64713 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
64714 // MIs[0] imm4
64715 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
64716 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
64717 // (intrinsic_wo_chain:{ *:[i32] } 1797:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQINCB_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
64718 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCB_WPiI),
64719 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
64720 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
64721 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
64722 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
64723 GIR_RootConstrainSelectedInstOperands,
64724 // GIR_Coverage, 2560,
64725 GIR_EraseRootFromParent_Done,
64726 // Label 3747: @176187
64727 GIM_Try, /*On fail goto*//*Label 3748*/ GIMT_Encode4(176243), // Rule ID 2561 //
64728 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
64729 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincb_n64),
64730 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
64731 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
64732 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64733 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64734 // MIs[0] pattern
64735 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
64736 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
64737 // MIs[0] imm4
64738 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
64739 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
64740 // (intrinsic_wo_chain:{ *:[i64] } 1587:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (SQINCB_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
64741 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCB_XPiI),
64742 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
64743 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
64744 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
64745 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
64746 GIR_RootConstrainSelectedInstOperands,
64747 // GIR_Coverage, 2561,
64748 GIR_EraseRootFromParent_Done,
64749 // Label 3748: @176243
64750 GIM_Try, /*On fail goto*//*Label 3749*/ GIMT_Encode4(176299), // Rule ID 9666 //
64751 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
64752 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecb_n32),
64753 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
64754 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
64755 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
64756 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
64757 // MIs[0] pattern
64758 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
64759 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
64760 // MIs[0] imm4
64761 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
64762 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
64763 // (intrinsic_wo_chain:{ *:[i32] } 1783:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQDECB_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
64764 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECB_WPiI),
64765 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
64766 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
64767 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
64768 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
64769 GIR_RootConstrainSelectedInstOperands,
64770 // GIR_Coverage, 9666,
64771 GIR_EraseRootFromParent_Done,
64772 // Label 3749: @176299
64773 GIM_Try, /*On fail goto*//*Label 3750*/ GIMT_Encode4(176355), // Rule ID 9667 //
64774 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
64775 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincb_n64),
64776 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
64777 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
64778 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64779 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64780 // MIs[0] pattern
64781 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
64782 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
64783 // MIs[0] imm4
64784 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
64785 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
64786 // (intrinsic_wo_chain:{ *:[i64] } 1798:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQINCB_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
64787 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCB_XPiI),
64788 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
64789 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
64790 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
64791 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
64792 GIR_RootConstrainSelectedInstOperands,
64793 // GIR_Coverage, 9667,
64794 GIR_EraseRootFromParent_Done,
64795 // Label 3750: @176355
64796 GIM_Try, /*On fail goto*//*Label 3751*/ GIMT_Encode4(176411), // Rule ID 9668 //
64797 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
64798 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecb_n64),
64799 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
64800 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
64801 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64802 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64803 // MIs[0] pattern
64804 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
64805 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
64806 // MIs[0] imm4
64807 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
64808 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
64809 // (intrinsic_wo_chain:{ *:[i64] } 1553:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (SQDECB_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
64810 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECB_XPiI),
64811 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
64812 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
64813 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
64814 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
64815 GIR_RootConstrainSelectedInstOperands,
64816 // GIR_Coverage, 9668,
64817 GIR_EraseRootFromParent_Done,
64818 // Label 3751: @176411
64819 GIM_Try, /*On fail goto*//*Label 3752*/ GIMT_Encode4(176467), // Rule ID 9669 //
64820 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
64821 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecb_n64),
64822 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
64823 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
64824 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64825 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64826 // MIs[0] pattern
64827 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
64828 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
64829 // MIs[0] imm4
64830 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
64831 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
64832 // (intrinsic_wo_chain:{ *:[i64] } 1784:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQDECB_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
64833 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECB_XPiI),
64834 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
64835 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
64836 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
64837 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
64838 GIR_RootConstrainSelectedInstOperands,
64839 // GIR_Coverage, 9669,
64840 GIR_EraseRootFromParent_Done,
64841 // Label 3752: @176467
64842 GIM_Try, /*On fail goto*//*Label 3753*/ GIMT_Encode4(176523), // Rule ID 9672 //
64843 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
64844 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqinch_n32),
64845 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
64846 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
64847 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
64848 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
64849 // MIs[0] pattern
64850 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
64851 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
64852 // MIs[0] imm4
64853 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
64854 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
64855 // (intrinsic_wo_chain:{ *:[i32] } 1803:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQINCH_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
64856 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCH_WPiI),
64857 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
64858 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
64859 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
64860 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
64861 GIR_RootConstrainSelectedInstOperands,
64862 // GIR_Coverage, 9672,
64863 GIR_EraseRootFromParent_Done,
64864 // Label 3753: @176523
64865 GIM_Try, /*On fail goto*//*Label 3754*/ GIMT_Encode4(176579), // Rule ID 9675 //
64866 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
64867 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdech_n32),
64868 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
64869 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
64870 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
64871 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
64872 // MIs[0] pattern
64873 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
64874 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
64875 // MIs[0] imm4
64876 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
64877 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
64878 // (intrinsic_wo_chain:{ *:[i32] } 1789:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQDECH_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
64879 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECH_WPiI),
64880 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
64881 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
64882 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
64883 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
64884 GIR_RootConstrainSelectedInstOperands,
64885 // GIR_Coverage, 9675,
64886 GIR_EraseRootFromParent_Done,
64887 // Label 3754: @176579
64888 GIM_Try, /*On fail goto*//*Label 3755*/ GIMT_Encode4(176635), // Rule ID 9676 //
64889 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
64890 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqinch_n64),
64891 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
64892 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
64893 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64894 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64895 // MIs[0] pattern
64896 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
64897 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
64898 // MIs[0] imm4
64899 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
64900 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
64901 // (intrinsic_wo_chain:{ *:[i64] } 1593:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (SQINCH_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
64902 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCH_XPiI),
64903 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
64904 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
64905 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
64906 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
64907 GIR_RootConstrainSelectedInstOperands,
64908 // GIR_Coverage, 9676,
64909 GIR_EraseRootFromParent_Done,
64910 // Label 3755: @176635
64911 GIM_Try, /*On fail goto*//*Label 3756*/ GIMT_Encode4(176691), // Rule ID 9677 //
64912 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
64913 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqinch_n64),
64914 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
64915 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
64916 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64917 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64918 // MIs[0] pattern
64919 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
64920 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
64921 // MIs[0] imm4
64922 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
64923 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
64924 // (intrinsic_wo_chain:{ *:[i64] } 1804:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQINCH_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
64925 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCH_XPiI),
64926 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
64927 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
64928 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
64929 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
64930 GIR_RootConstrainSelectedInstOperands,
64931 // GIR_Coverage, 9677,
64932 GIR_EraseRootFromParent_Done,
64933 // Label 3756: @176691
64934 GIM_Try, /*On fail goto*//*Label 3757*/ GIMT_Encode4(176747), // Rule ID 9678 //
64935 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
64936 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdech_n64),
64937 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
64938 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
64939 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64940 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64941 // MIs[0] pattern
64942 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
64943 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
64944 // MIs[0] imm4
64945 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
64946 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
64947 // (intrinsic_wo_chain:{ *:[i64] } 1559:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (SQDECH_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
64948 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECH_XPiI),
64949 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
64950 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
64951 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
64952 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
64953 GIR_RootConstrainSelectedInstOperands,
64954 // GIR_Coverage, 9678,
64955 GIR_EraseRootFromParent_Done,
64956 // Label 3757: @176747
64957 GIM_Try, /*On fail goto*//*Label 3758*/ GIMT_Encode4(176803), // Rule ID 9679 //
64958 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
64959 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdech_n64),
64960 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
64961 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
64962 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64963 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
64964 // MIs[0] pattern
64965 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
64966 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
64967 // MIs[0] imm4
64968 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
64969 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
64970 // (intrinsic_wo_chain:{ *:[i64] } 1790:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQDECH_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
64971 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECH_XPiI),
64972 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
64973 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
64974 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
64975 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
64976 GIR_RootConstrainSelectedInstOperands,
64977 // GIR_Coverage, 9679,
64978 GIR_EraseRootFromParent_Done,
64979 // Label 3758: @176803
64980 GIM_Try, /*On fail goto*//*Label 3759*/ GIMT_Encode4(176859), // Rule ID 9682 //
64981 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
64982 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincw_n32),
64983 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
64984 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
64985 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
64986 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
64987 // MIs[0] pattern
64988 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
64989 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
64990 // MIs[0] imm4
64991 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
64992 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
64993 // (intrinsic_wo_chain:{ *:[i32] } 1809:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQINCW_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
64994 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCW_WPiI),
64995 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
64996 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
64997 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
64998 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
64999 GIR_RootConstrainSelectedInstOperands,
65000 // GIR_Coverage, 9682,
65001 GIR_EraseRootFromParent_Done,
65002 // Label 3759: @176859
65003 GIM_Try, /*On fail goto*//*Label 3760*/ GIMT_Encode4(176915), // Rule ID 9685 //
65004 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65005 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecw_n32),
65006 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
65007 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
65008 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
65009 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
65010 // MIs[0] pattern
65011 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65012 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65013 // MIs[0] imm4
65014 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65015 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65016 // (intrinsic_wo_chain:{ *:[i32] } 1795:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQDECW_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65017 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECW_WPiI),
65018 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
65019 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
65020 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65021 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65022 GIR_RootConstrainSelectedInstOperands,
65023 // GIR_Coverage, 9685,
65024 GIR_EraseRootFromParent_Done,
65025 // Label 3760: @176915
65026 GIM_Try, /*On fail goto*//*Label 3761*/ GIMT_Encode4(176971), // Rule ID 9686 //
65027 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65028 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincw_n64),
65029 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
65030 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
65031 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
65032 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
65033 // MIs[0] pattern
65034 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65035 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65036 // MIs[0] imm4
65037 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65038 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65039 // (intrinsic_wo_chain:{ *:[i64] } 1599:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (SQINCW_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65040 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCW_XPiI),
65041 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
65042 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
65043 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65044 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65045 GIR_RootConstrainSelectedInstOperands,
65046 // GIR_Coverage, 9686,
65047 GIR_EraseRootFromParent_Done,
65048 // Label 3761: @176971
65049 GIM_Try, /*On fail goto*//*Label 3762*/ GIMT_Encode4(177027), // Rule ID 9687 //
65050 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65051 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincw_n64),
65052 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
65053 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
65054 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
65055 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
65056 // MIs[0] pattern
65057 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65058 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65059 // MIs[0] imm4
65060 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65061 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65062 // (intrinsic_wo_chain:{ *:[i64] } 1810:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQINCW_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65063 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCW_XPiI),
65064 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
65065 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
65066 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65067 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65068 GIR_RootConstrainSelectedInstOperands,
65069 // GIR_Coverage, 9687,
65070 GIR_EraseRootFromParent_Done,
65071 // Label 3762: @177027
65072 GIM_Try, /*On fail goto*//*Label 3763*/ GIMT_Encode4(177083), // Rule ID 9688 //
65073 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65074 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecw_n64),
65075 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
65076 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
65077 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
65078 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
65079 // MIs[0] pattern
65080 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65081 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65082 // MIs[0] imm4
65083 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65084 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65085 // (intrinsic_wo_chain:{ *:[i64] } 1565:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (SQDECW_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65086 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECW_XPiI),
65087 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
65088 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
65089 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65090 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65091 GIR_RootConstrainSelectedInstOperands,
65092 // GIR_Coverage, 9688,
65093 GIR_EraseRootFromParent_Done,
65094 // Label 3763: @177083
65095 GIM_Try, /*On fail goto*//*Label 3764*/ GIMT_Encode4(177139), // Rule ID 9689 //
65096 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65097 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecw_n64),
65098 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
65099 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
65100 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
65101 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
65102 // MIs[0] pattern
65103 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65104 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65105 // MIs[0] imm4
65106 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65107 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65108 // (intrinsic_wo_chain:{ *:[i64] } 1796:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQDECW_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65109 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECW_XPiI),
65110 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
65111 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
65112 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65113 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65114 GIR_RootConstrainSelectedInstOperands,
65115 // GIR_Coverage, 9689,
65116 GIR_EraseRootFromParent_Done,
65117 // Label 3764: @177139
65118 GIM_Try, /*On fail goto*//*Label 3765*/ GIMT_Encode4(177195), // Rule ID 9692 //
65119 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65120 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincd_n32),
65121 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
65122 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
65123 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
65124 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
65125 // MIs[0] pattern
65126 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65127 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65128 // MIs[0] imm4
65129 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65130 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65131 // (intrinsic_wo_chain:{ *:[i32] } 1800:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQINCD_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65132 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCD_WPiI),
65133 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
65134 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
65135 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65136 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65137 GIR_RootConstrainSelectedInstOperands,
65138 // GIR_Coverage, 9692,
65139 GIR_EraseRootFromParent_Done,
65140 // Label 3765: @177195
65141 GIM_Try, /*On fail goto*//*Label 3766*/ GIMT_Encode4(177251), // Rule ID 9695 //
65142 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65143 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecd_n32),
65144 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
65145 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
65146 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
65147 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
65148 // MIs[0] pattern
65149 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65150 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65151 // MIs[0] imm4
65152 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65153 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65154 // (intrinsic_wo_chain:{ *:[i32] } 1786:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQDECD_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65155 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECD_WPiI),
65156 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
65157 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
65158 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65159 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65160 GIR_RootConstrainSelectedInstOperands,
65161 // GIR_Coverage, 9695,
65162 GIR_EraseRootFromParent_Done,
65163 // Label 3766: @177251
65164 GIM_Try, /*On fail goto*//*Label 3767*/ GIMT_Encode4(177307), // Rule ID 9696 //
65165 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65166 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincd_n64),
65167 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
65168 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
65169 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
65170 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
65171 // MIs[0] pattern
65172 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65173 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65174 // MIs[0] imm4
65175 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65176 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65177 // (intrinsic_wo_chain:{ *:[i64] } 1590:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (SQINCD_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65178 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCD_XPiI),
65179 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
65180 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
65181 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65182 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65183 GIR_RootConstrainSelectedInstOperands,
65184 // GIR_Coverage, 9696,
65185 GIR_EraseRootFromParent_Done,
65186 // Label 3767: @177307
65187 GIM_Try, /*On fail goto*//*Label 3768*/ GIMT_Encode4(177363), // Rule ID 9697 //
65188 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65189 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincd_n64),
65190 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
65191 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
65192 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
65193 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
65194 // MIs[0] pattern
65195 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65196 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65197 // MIs[0] imm4
65198 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65199 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65200 // (intrinsic_wo_chain:{ *:[i64] } 1801:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQINCD_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65201 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCD_XPiI),
65202 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
65203 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
65204 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65205 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65206 GIR_RootConstrainSelectedInstOperands,
65207 // GIR_Coverage, 9697,
65208 GIR_EraseRootFromParent_Done,
65209 // Label 3768: @177363
65210 GIM_Try, /*On fail goto*//*Label 3769*/ GIMT_Encode4(177419), // Rule ID 9698 //
65211 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65212 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecd_n64),
65213 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
65214 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
65215 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
65216 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
65217 // MIs[0] pattern
65218 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65219 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65220 // MIs[0] imm4
65221 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65222 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65223 // (intrinsic_wo_chain:{ *:[i64] } 1556:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (SQDECD_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65224 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECD_XPiI),
65225 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
65226 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
65227 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65228 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65229 GIR_RootConstrainSelectedInstOperands,
65230 // GIR_Coverage, 9698,
65231 GIR_EraseRootFromParent_Done,
65232 // Label 3769: @177419
65233 GIM_Try, /*On fail goto*//*Label 3770*/ GIMT_Encode4(177475), // Rule ID 9699 //
65234 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65235 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecd_n64),
65236 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
65237 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
65238 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
65239 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
65240 // MIs[0] pattern
65241 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65242 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65243 // MIs[0] imm4
65244 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65245 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65246 // (intrinsic_wo_chain:{ *:[i64] } 1787:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQDECD_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65247 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECD_XPiI),
65248 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
65249 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
65250 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65251 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65252 GIR_RootConstrainSelectedInstOperands,
65253 // GIR_Coverage, 9699,
65254 GIR_EraseRootFromParent_Done,
65255 // Label 3770: @177475
65256 GIM_Try, /*On fail goto*//*Label 3771*/ GIMT_Encode4(177531), // Rule ID 9700 //
65257 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65258 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqinch),
65259 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
65260 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
65261 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65262 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65263 // MIs[0] pattern
65264 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65265 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65266 // MIs[0] imm4
65267 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65268 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65269 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1802:{ *:[iPTR] }, ZPR16:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQINCH_ZPiI:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65270 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCH_ZPiI),
65271 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
65272 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
65273 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65274 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65275 GIR_RootConstrainSelectedInstOperands,
65276 // GIR_Coverage, 9700,
65277 GIR_EraseRootFromParent_Done,
65278 // Label 3771: @177531
65279 GIM_Try, /*On fail goto*//*Label 3772*/ GIMT_Encode4(177587), // Rule ID 9701 //
65280 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65281 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdech),
65282 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
65283 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
65284 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65285 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65286 // MIs[0] pattern
65287 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65288 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65289 // MIs[0] imm4
65290 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65291 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65292 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1557:{ *:[iPTR] }, ZPR16:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (SQDECH_ZPiI:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65293 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECH_ZPiI),
65294 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
65295 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
65296 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65297 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65298 GIR_RootConstrainSelectedInstOperands,
65299 // GIR_Coverage, 9701,
65300 GIR_EraseRootFromParent_Done,
65301 // Label 3772: @177587
65302 GIM_Try, /*On fail goto*//*Label 3773*/ GIMT_Encode4(177643), // Rule ID 9702 //
65303 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65304 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdech),
65305 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
65306 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
65307 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65308 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65309 // MIs[0] pattern
65310 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65311 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65312 // MIs[0] imm4
65313 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65314 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65315 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1788:{ *:[iPTR] }, ZPR16:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQDECH_ZPiI:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65316 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECH_ZPiI),
65317 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
65318 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
65319 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65320 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65321 GIR_RootConstrainSelectedInstOperands,
65322 // GIR_Coverage, 9702,
65323 GIR_EraseRootFromParent_Done,
65324 // Label 3773: @177643
65325 GIM_Try, /*On fail goto*//*Label 3774*/ GIMT_Encode4(177699), // Rule ID 9703 //
65326 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65327 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincw),
65328 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
65329 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
65330 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65331 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65332 // MIs[0] pattern
65333 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65334 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65335 // MIs[0] imm4
65336 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65337 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65338 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1597:{ *:[iPTR] }, ZPR32:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (SQINCW_ZPiI:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65339 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCW_ZPiI),
65340 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
65341 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
65342 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65343 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65344 GIR_RootConstrainSelectedInstOperands,
65345 // GIR_Coverage, 9703,
65346 GIR_EraseRootFromParent_Done,
65347 // Label 3774: @177699
65348 GIM_Try, /*On fail goto*//*Label 3775*/ GIMT_Encode4(177755), // Rule ID 9704 //
65349 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65350 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincw),
65351 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
65352 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
65353 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65354 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65355 // MIs[0] pattern
65356 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65357 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65358 // MIs[0] imm4
65359 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65360 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65361 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1808:{ *:[iPTR] }, ZPR32:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQINCW_ZPiI:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65362 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCW_ZPiI),
65363 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
65364 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
65365 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65366 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65367 GIR_RootConstrainSelectedInstOperands,
65368 // GIR_Coverage, 9704,
65369 GIR_EraseRootFromParent_Done,
65370 // Label 3775: @177755
65371 GIM_Try, /*On fail goto*//*Label 3776*/ GIMT_Encode4(177811), // Rule ID 9705 //
65372 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65373 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecw),
65374 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
65375 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
65376 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65377 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65378 // MIs[0] pattern
65379 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65380 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65381 // MIs[0] imm4
65382 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65383 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65384 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1563:{ *:[iPTR] }, ZPR32:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (SQDECW_ZPiI:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65385 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECW_ZPiI),
65386 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
65387 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
65388 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65389 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65390 GIR_RootConstrainSelectedInstOperands,
65391 // GIR_Coverage, 9705,
65392 GIR_EraseRootFromParent_Done,
65393 // Label 3776: @177811
65394 GIM_Try, /*On fail goto*//*Label 3777*/ GIMT_Encode4(177867), // Rule ID 9706 //
65395 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65396 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecw),
65397 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
65398 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
65399 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65400 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65401 // MIs[0] pattern
65402 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65403 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65404 // MIs[0] imm4
65405 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65406 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65407 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1794:{ *:[iPTR] }, ZPR32:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQDECW_ZPiI:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65408 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECW_ZPiI),
65409 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
65410 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
65411 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65412 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65413 GIR_RootConstrainSelectedInstOperands,
65414 // GIR_Coverage, 9706,
65415 GIR_EraseRootFromParent_Done,
65416 // Label 3777: @177867
65417 GIM_Try, /*On fail goto*//*Label 3778*/ GIMT_Encode4(177923), // Rule ID 9707 //
65418 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65419 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincd),
65420 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
65421 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
65422 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65423 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65424 // MIs[0] pattern
65425 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65426 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65427 // MIs[0] imm4
65428 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65429 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65430 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1588:{ *:[iPTR] }, ZPR64:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (SQINCD_ZPiI:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65431 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCD_ZPiI),
65432 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
65433 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
65434 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65435 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65436 GIR_RootConstrainSelectedInstOperands,
65437 // GIR_Coverage, 9707,
65438 GIR_EraseRootFromParent_Done,
65439 // Label 3778: @177923
65440 GIM_Try, /*On fail goto*//*Label 3779*/ GIMT_Encode4(177979), // Rule ID 9708 //
65441 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65442 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincd),
65443 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
65444 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
65445 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65446 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65447 // MIs[0] pattern
65448 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65449 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65450 // MIs[0] imm4
65451 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65452 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65453 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1799:{ *:[iPTR] }, ZPR64:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQINCD_ZPiI:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65454 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCD_ZPiI),
65455 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
65456 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
65457 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65458 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65459 GIR_RootConstrainSelectedInstOperands,
65460 // GIR_Coverage, 9708,
65461 GIR_EraseRootFromParent_Done,
65462 // Label 3779: @177979
65463 GIM_Try, /*On fail goto*//*Label 3780*/ GIMT_Encode4(178035), // Rule ID 9709 //
65464 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65465 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecd),
65466 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
65467 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
65468 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65469 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65470 // MIs[0] pattern
65471 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65472 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65473 // MIs[0] imm4
65474 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65475 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65476 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1554:{ *:[iPTR] }, ZPR64:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (SQDECD_ZPiI:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65477 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECD_ZPiI),
65478 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
65479 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
65480 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65481 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65482 GIR_RootConstrainSelectedInstOperands,
65483 // GIR_Coverage, 9709,
65484 GIR_EraseRootFromParent_Done,
65485 // Label 3780: @178035
65486 GIM_Try, /*On fail goto*//*Label 3781*/ GIMT_Encode4(178091), // Rule ID 9710 //
65487 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
65488 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecd),
65489 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
65490 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
65491 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65492 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
65493 // MIs[0] pattern
65494 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
65495 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
65496 // MIs[0] imm4
65497 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
65498 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
65499 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1785:{ *:[iPTR] }, ZPR64:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4) => (UQDECD_ZPiI:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
65500 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECD_ZPiI),
65501 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
65502 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
65503 GIR_RootToRootCopy, /*OpIdx*/3, // pattern
65504 GIR_RootToRootCopy, /*OpIdx*/4, // imm4
65505 GIR_RootConstrainSelectedInstOperands,
65506 // GIR_Coverage, 9710,
65507 GIR_EraseRootFromParent_Done,
65508 // Label 3781: @178091
65509 GIM_Try, /*On fail goto*//*Label 3782*/ GIMT_Encode4(178181), // Rule ID 37 //
65510 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON),
65511 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_bfmlalb),
65512 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
65513 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
65514 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
65515 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
65516 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65517 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65518 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65519 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
65520 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
65521 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
65522 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
65523 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
65524 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
65525 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
65526 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
65527 // MIs[2] Operand 1
65528 // No operand predicates
65529 GIM_CheckIsSafeToFold, /*NumInsns*/2,
65530 // (intrinsic_wo_chain:{ *:[v4f32] } 557:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, (AArch64duplane16:{ *:[v8bf16] } V128_lo:{ *:[v8bf16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (BFMLALBIdx:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128_lo:{ *:[v8bf16] }:$Rm, (imm:{ *:[i64] }):$idx)
65531 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMLALBIdx),
65532 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
65533 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
65534 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
65535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
65536 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
65537 GIR_RootConstrainSelectedInstOperands,
65538 // GIR_Coverage, 37,
65539 GIR_EraseRootFromParent_Done,
65540 // Label 3782: @178181
65541 GIM_Try, /*On fail goto*//*Label 3783*/ GIMT_Encode4(178271), // Rule ID 38 //
65542 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON),
65543 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_bfmlalt),
65544 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
65545 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
65546 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
65547 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
65548 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65549 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65550 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65551 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
65552 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
65553 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
65554 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
65555 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
65556 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
65557 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
65558 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
65559 // MIs[2] Operand 1
65560 // No operand predicates
65561 GIM_CheckIsSafeToFold, /*NumInsns*/2,
65562 // (intrinsic_wo_chain:{ *:[v4f32] } 558:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, (AArch64duplane16:{ *:[v8bf16] } V128_lo:{ *:[v8bf16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (BFMLALTIdx:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128_lo:{ *:[v8bf16] }:$Rm, (imm:{ *:[i64] }):$idx)
65563 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMLALTIdx),
65564 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
65565 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
65566 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
65567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
65568 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
65569 GIR_RootConstrainSelectedInstOperands,
65570 // GIR_Coverage, 38,
65571 GIR_EraseRootFromParent_Done,
65572 // Label 3783: @178271
65573 GIM_Try, /*On fail goto*//*Label 3784*/ GIMT_Encode4(178361), // Rule ID 59 //
65574 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
65575 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal),
65576 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
65577 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
65578 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
65579 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
65580 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65581 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65582 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65583 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
65584 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
65585 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
65586 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
65587 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
65588 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
65589 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
65590 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
65591 // MIs[2] Operand 1
65592 // No operand predicates
65593 GIM_CheckIsSafeToFold, /*NumInsns*/2,
65594 // (intrinsic_wo_chain:{ *:[v2f32] } 589:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMLALlanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
65595 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALlanev4f16),
65596 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
65597 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
65598 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
65599 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
65600 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
65601 GIR_RootConstrainSelectedInstOperands,
65602 // GIR_Coverage, 59,
65603 GIR_EraseRootFromParent_Done,
65604 // Label 3784: @178361
65605 GIM_Try, /*On fail goto*//*Label 3785*/ GIMT_Encode4(178451), // Rule ID 60 //
65606 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
65607 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal),
65608 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
65609 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
65610 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
65611 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
65612 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65613 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65614 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65615 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
65616 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
65617 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
65618 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
65619 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
65620 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
65621 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
65622 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
65623 // MIs[2] Operand 1
65624 // No operand predicates
65625 GIM_CheckIsSafeToFold, /*NumInsns*/2,
65626 // (intrinsic_wo_chain:{ *:[v4f32] } 589:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMLALlanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
65627 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALlanev8f16),
65628 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
65629 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
65630 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
65631 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
65632 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
65633 GIR_RootConstrainSelectedInstOperands,
65634 // GIR_Coverage, 60,
65635 GIR_EraseRootFromParent_Done,
65636 // Label 3785: @178451
65637 GIM_Try, /*On fail goto*//*Label 3786*/ GIMT_Encode4(178541), // Rule ID 61 //
65638 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
65639 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl),
65640 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
65641 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
65642 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
65643 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
65644 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65645 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65646 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65647 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
65648 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
65649 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
65650 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
65651 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
65652 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
65653 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
65654 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
65655 // MIs[2] Operand 1
65656 // No operand predicates
65657 GIM_CheckIsSafeToFold, /*NumInsns*/2,
65658 // (intrinsic_wo_chain:{ *:[v2f32] } 591:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMLSLlanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
65659 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLlanev4f16),
65660 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
65661 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
65662 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
65663 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
65664 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
65665 GIR_RootConstrainSelectedInstOperands,
65666 // GIR_Coverage, 61,
65667 GIR_EraseRootFromParent_Done,
65668 // Label 3786: @178541
65669 GIM_Try, /*On fail goto*//*Label 3787*/ GIMT_Encode4(178631), // Rule ID 62 //
65670 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
65671 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl),
65672 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
65673 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
65674 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
65675 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
65676 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65677 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65678 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65679 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
65680 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
65681 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
65682 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
65683 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
65684 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
65685 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
65686 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
65687 // MIs[2] Operand 1
65688 // No operand predicates
65689 GIM_CheckIsSafeToFold, /*NumInsns*/2,
65690 // (intrinsic_wo_chain:{ *:[v4f32] } 591:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMLSLlanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
65691 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLlanev8f16),
65692 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
65693 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
65694 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
65695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
65696 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
65697 GIR_RootConstrainSelectedInstOperands,
65698 // GIR_Coverage, 62,
65699 GIR_EraseRootFromParent_Done,
65700 // Label 3787: @178631
65701 GIM_Try, /*On fail goto*//*Label 3788*/ GIMT_Encode4(178721), // Rule ID 63 //
65702 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
65703 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal2),
65704 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
65705 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
65706 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
65707 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
65708 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65709 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65710 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65711 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
65712 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
65713 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
65714 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
65715 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
65716 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
65717 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
65718 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
65719 // MIs[2] Operand 1
65720 // No operand predicates
65721 GIM_CheckIsSafeToFold, /*NumInsns*/2,
65722 // (intrinsic_wo_chain:{ *:[v2f32] } 590:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMLAL2lanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
65723 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAL2lanev4f16),
65724 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
65725 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
65726 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
65727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
65728 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
65729 GIR_RootConstrainSelectedInstOperands,
65730 // GIR_Coverage, 63,
65731 GIR_EraseRootFromParent_Done,
65732 // Label 3788: @178721
65733 GIM_Try, /*On fail goto*//*Label 3789*/ GIMT_Encode4(178811), // Rule ID 64 //
65734 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
65735 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal2),
65736 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
65737 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
65738 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
65739 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
65740 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65741 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65742 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65743 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
65744 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
65745 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
65746 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
65747 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
65748 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
65749 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
65750 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
65751 // MIs[2] Operand 1
65752 // No operand predicates
65753 GIM_CheckIsSafeToFold, /*NumInsns*/2,
65754 // (intrinsic_wo_chain:{ *:[v4f32] } 590:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMLAL2lanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
65755 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAL2lanev8f16),
65756 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
65757 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
65758 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
65759 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
65760 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
65761 GIR_RootConstrainSelectedInstOperands,
65762 // GIR_Coverage, 64,
65763 GIR_EraseRootFromParent_Done,
65764 // Label 3789: @178811
65765 GIM_Try, /*On fail goto*//*Label 3790*/ GIMT_Encode4(178901), // Rule ID 65 //
65766 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
65767 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl2),
65768 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
65769 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
65770 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
65771 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
65772 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65773 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65774 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65775 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
65776 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
65777 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
65778 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
65779 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
65780 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
65781 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
65782 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
65783 // MIs[2] Operand 1
65784 // No operand predicates
65785 GIM_CheckIsSafeToFold, /*NumInsns*/2,
65786 // (intrinsic_wo_chain:{ *:[v2f32] } 592:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMLSL2lanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
65787 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSL2lanev4f16),
65788 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
65789 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
65790 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
65791 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
65792 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
65793 GIR_RootConstrainSelectedInstOperands,
65794 // GIR_Coverage, 65,
65795 GIR_EraseRootFromParent_Done,
65796 // Label 3790: @178901
65797 GIM_Try, /*On fail goto*//*Label 3791*/ GIMT_Encode4(178991), // Rule ID 66 //
65798 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
65799 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl2),
65800 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
65801 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
65802 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
65803 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
65804 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65805 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65806 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65807 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
65808 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
65809 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
65810 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
65811 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
65812 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
65813 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
65814 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
65815 // MIs[2] Operand 1
65816 // No operand predicates
65817 GIM_CheckIsSafeToFold, /*NumInsns*/2,
65818 // (intrinsic_wo_chain:{ *:[v4f32] } 592:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMLSL2lanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
65819 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSL2lanev8f16),
65820 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
65821 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
65822 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
65823 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
65824 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
65825 GIR_RootConstrainSelectedInstOperands,
65826 // GIR_Coverage, 66,
65827 GIR_EraseRootFromParent_Done,
65828 // Label 3791: @178991
65829 GIM_Try, /*On fail goto*//*Label 3792*/ GIMT_Encode4(179081), // Rule ID 2057 //
65830 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
65831 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
65832 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
65833 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
65834 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
65835 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
65836 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65837 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65838 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65839 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
65840 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
65841 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
65842 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
65843 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
65844 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
65845 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
65846 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
65847 // MIs[2] Operand 1
65848 // No operand predicates
65849 GIM_CheckIsSafeToFold, /*NumInsns*/2,
65850 // (intrinsic_wo_chain:{ *:[v4i16] } 648:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (SQRDMLAHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
65851 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv4i16_indexed),
65852 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
65853 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
65854 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
65855 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
65856 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
65857 GIR_RootConstrainSelectedInstOperands,
65858 // GIR_Coverage, 2057,
65859 GIR_EraseRootFromParent_Done,
65860 // Label 3792: @179081
65861 GIM_Try, /*On fail goto*//*Label 3793*/ GIMT_Encode4(179171), // Rule ID 2058 //
65862 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
65863 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
65864 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
65865 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
65866 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
65867 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
65868 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65869 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65870 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65871 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
65872 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
65873 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
65874 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
65875 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
65876 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
65877 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
65878 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
65879 // MIs[2] Operand 1
65880 // No operand predicates
65881 GIM_CheckIsSafeToFold, /*NumInsns*/2,
65882 // (intrinsic_wo_chain:{ *:[v8i16] } 648:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (SQRDMLAHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
65883 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv8i16_indexed),
65884 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
65885 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
65886 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
65887 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
65888 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
65889 GIR_RootConstrainSelectedInstOperands,
65890 // GIR_Coverage, 2058,
65891 GIR_EraseRootFromParent_Done,
65892 // Label 3793: @179171
65893 GIM_Try, /*On fail goto*//*Label 3794*/ GIMT_Encode4(179261), // Rule ID 2064 //
65894 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
65895 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
65896 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
65897 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
65898 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
65899 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
65900 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65901 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65902 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65903 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
65904 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
65905 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
65906 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
65907 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
65908 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
65909 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
65910 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
65911 // MIs[2] Operand 1
65912 // No operand predicates
65913 GIM_CheckIsSafeToFold, /*NumInsns*/2,
65914 // (intrinsic_wo_chain:{ *:[v4i16] } 649:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (SQRDMLSHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
65915 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv4i16_indexed),
65916 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
65917 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
65918 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
65919 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
65920 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
65921 GIR_RootConstrainSelectedInstOperands,
65922 // GIR_Coverage, 2064,
65923 GIR_EraseRootFromParent_Done,
65924 // Label 3794: @179261
65925 GIM_Try, /*On fail goto*//*Label 3795*/ GIMT_Encode4(179351), // Rule ID 2065 //
65926 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
65927 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
65928 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
65929 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
65930 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
65931 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
65932 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65933 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65934 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65935 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
65936 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
65937 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
65938 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
65939 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
65940 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
65941 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
65942 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
65943 // MIs[2] Operand 1
65944 // No operand predicates
65945 GIM_CheckIsSafeToFold, /*NumInsns*/2,
65946 // (intrinsic_wo_chain:{ *:[v8i16] } 649:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (SQRDMLSHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
65947 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv8i16_indexed),
65948 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
65949 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
65950 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
65951 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
65952 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
65953 GIR_RootConstrainSelectedInstOperands,
65954 // GIR_Coverage, 2065,
65955 GIR_EraseRootFromParent_Done,
65956 // Label 3795: @179351
65957 GIM_Try, /*On fail goto*//*Label 3796*/ GIMT_Encode4(179441), // Rule ID 2060 //
65958 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
65959 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
65960 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
65961 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
65962 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
65963 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
65964 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65965 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65966 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
65967 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
65968 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
65969 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
65970 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
65971 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65972 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
65973 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
65974 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
65975 // MIs[2] Operand 1
65976 // No operand predicates
65977 GIM_CheckIsSafeToFold, /*NumInsns*/2,
65978 // (intrinsic_wo_chain:{ *:[v2i32] } 648:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQRDMLAHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
65979 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv2i32_indexed),
65980 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
65981 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
65982 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
65983 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
65984 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
65985 GIR_RootConstrainSelectedInstOperands,
65986 // GIR_Coverage, 2060,
65987 GIR_EraseRootFromParent_Done,
65988 // Label 3796: @179441
65989 GIM_Try, /*On fail goto*//*Label 3797*/ GIMT_Encode4(179531), // Rule ID 2061 //
65990 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
65991 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
65992 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
65993 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
65994 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
65995 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
65996 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65997 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65998 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
65999 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
66000 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
66001 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
66002 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
66003 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
66004 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
66005 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
66006 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
66007 // MIs[2] Operand 1
66008 // No operand predicates
66009 GIM_CheckIsSafeToFold, /*NumInsns*/2,
66010 // (intrinsic_wo_chain:{ *:[v4i32] } 648:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQRDMLAHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
66011 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv4i32_indexed),
66012 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
66013 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
66014 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
66015 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
66016 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
66017 GIR_RootConstrainSelectedInstOperands,
66018 // GIR_Coverage, 2061,
66019 GIR_EraseRootFromParent_Done,
66020 // Label 3797: @179531
66021 GIM_Try, /*On fail goto*//*Label 3798*/ GIMT_Encode4(179621), // Rule ID 2067 //
66022 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
66023 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
66024 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
66025 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
66026 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
66027 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
66028 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
66029 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
66030 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
66031 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
66032 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
66033 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
66034 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
66035 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
66036 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
66037 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
66038 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
66039 // MIs[2] Operand 1
66040 // No operand predicates
66041 GIM_CheckIsSafeToFold, /*NumInsns*/2,
66042 // (intrinsic_wo_chain:{ *:[v2i32] } 649:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQRDMLSHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
66043 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv2i32_indexed),
66044 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
66045 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
66046 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
66047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
66048 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
66049 GIR_RootConstrainSelectedInstOperands,
66050 // GIR_Coverage, 2067,
66051 GIR_EraseRootFromParent_Done,
66052 // Label 3798: @179621
66053 GIM_Try, /*On fail goto*//*Label 3799*/ GIMT_Encode4(179711), // Rule ID 2068 //
66054 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
66055 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
66056 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
66057 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
66058 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
66059 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
66060 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
66061 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
66062 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
66063 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
66064 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
66065 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
66066 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
66067 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
66068 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
66069 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
66070 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
66071 // MIs[2] Operand 1
66072 // No operand predicates
66073 GIM_CheckIsSafeToFold, /*NumInsns*/2,
66074 // (intrinsic_wo_chain:{ *:[v4i32] } 649:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQRDMLSHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
66075 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv4i32_indexed),
66076 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
66077 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
66078 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
66079 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
66080 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
66081 GIR_RootConstrainSelectedInstOperands,
66082 // GIR_Coverage, 2068,
66083 GIR_EraseRootFromParent_Done,
66084 // Label 3799: @179711
66085 GIM_Try, /*On fail goto*//*Label 3800*/ GIMT_Encode4(179801), // Rule ID 2062 //
66086 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
66087 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
66088 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
66089 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
66090 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
66091 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
66092 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
66093 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
66094 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
66095 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
66096 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
66097 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
66098 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
66099 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
66100 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
66101 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
66102 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
66103 // MIs[2] Operand 1
66104 // No operand predicates
66105 GIM_CheckIsSafeToFold, /*NumInsns*/2,
66106 // (intrinsic_wo_chain:{ *:[i32] } 648:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQRDMLAHv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
66107 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv1i32_indexed),
66108 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
66109 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
66110 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
66111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
66112 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
66113 GIR_RootConstrainSelectedInstOperands,
66114 // GIR_Coverage, 2062,
66115 GIR_EraseRootFromParent_Done,
66116 // Label 3800: @179801
66117 GIM_Try, /*On fail goto*//*Label 3801*/ GIMT_Encode4(179891), // Rule ID 2069 //
66118 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
66119 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
66120 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
66121 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
66122 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
66123 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
66124 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
66125 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
66126 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
66127 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
66128 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
66129 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
66130 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
66131 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
66132 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
66133 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
66134 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
66135 // MIs[2] Operand 1
66136 // No operand predicates
66137 GIM_CheckIsSafeToFold, /*NumInsns*/2,
66138 // (intrinsic_wo_chain:{ *:[i32] } 649:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SQRDMLSHv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
66139 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv1i32_indexed),
66140 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
66141 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
66142 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
66143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
66144 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
66145 GIR_RootConstrainSelectedInstOperands,
66146 // GIR_Coverage, 2069,
66147 GIR_EraseRootFromParent_Done,
66148 // Label 3801: @179891
66149 GIM_Try, /*On fail goto*//*Label 3802*/ GIMT_Encode4(179947), // Rule ID 67 //
66150 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
66151 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign),
66152 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
66153 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
66154 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
66155 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
66156 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
66157 // MIs[0] Operand 3
66158 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
66159 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
66160 // (intrinsic_wo_chain:{ *:[i64] } 287:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 0:{ *:[i32] }, GPR64sp:{ *:[i64] }:$Rn) => (PACIA:{ *:[i64] } GPR64:{ *:[i64] }:$Rd, GPR64sp:{ *:[i64] }:$Rn)
66161 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PACIA),
66162 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
66163 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
66164 GIR_RootToRootCopy, /*OpIdx*/4, // Rn
66165 GIR_RootConstrainSelectedInstOperands,
66166 // GIR_Coverage, 67,
66167 GIR_EraseRootFromParent_Done,
66168 // Label 3802: @179947
66169 GIM_Try, /*On fail goto*//*Label 3803*/ GIMT_Encode4(180003), // Rule ID 68 //
66170 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
66171 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign),
66172 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
66173 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
66174 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
66175 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
66176 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
66177 // MIs[0] Operand 3
66178 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(1),
66179 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
66180 // (intrinsic_wo_chain:{ *:[i64] } 287:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 1:{ *:[i32] }, GPR64sp:{ *:[i64] }:$Rn) => (PACIB:{ *:[i64] } GPR64:{ *:[i64] }:$Rd, GPR64sp:{ *:[i64] }:$Rn)
66181 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PACIB),
66182 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
66183 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
66184 GIR_RootToRootCopy, /*OpIdx*/4, // Rn
66185 GIR_RootConstrainSelectedInstOperands,
66186 // GIR_Coverage, 68,
66187 GIR_EraseRootFromParent_Done,
66188 // Label 3803: @180003
66189 GIM_Try, /*On fail goto*//*Label 3804*/ GIMT_Encode4(180059), // Rule ID 69 //
66190 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
66191 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign),
66192 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
66193 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
66194 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
66195 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
66196 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
66197 // MIs[0] Operand 3
66198 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(2),
66199 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
66200 // (intrinsic_wo_chain:{ *:[i64] } 287:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 2:{ *:[i32] }, GPR64sp:{ *:[i64] }:$Rn) => (PACDA:{ *:[i64] } GPR64:{ *:[i64] }:$Rd, GPR64sp:{ *:[i64] }:$Rn)
66201 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PACDA),
66202 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
66203 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
66204 GIR_RootToRootCopy, /*OpIdx*/4, // Rn
66205 GIR_RootConstrainSelectedInstOperands,
66206 // GIR_Coverage, 69,
66207 GIR_EraseRootFromParent_Done,
66208 // Label 3804: @180059
66209 GIM_Try, /*On fail goto*//*Label 3805*/ GIMT_Encode4(180115), // Rule ID 70 //
66210 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
66211 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign),
66212 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
66213 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
66214 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
66215 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
66216 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
66217 // MIs[0] Operand 3
66218 GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(3),
66219 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
66220 // (intrinsic_wo_chain:{ *:[i64] } 287:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 3:{ *:[i32] }, GPR64sp:{ *:[i64] }:$Rn) => (PACDB:{ *:[i64] } GPR64:{ *:[i64] }:$Rd, GPR64sp:{ *:[i64] }:$Rn)
66221 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PACDB),
66222 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
66223 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
66224 GIR_RootToRootCopy, /*OpIdx*/4, // Rn
66225 GIR_RootConstrainSelectedInstOperands,
66226 // GIR_Coverage, 70,
66227 GIR_EraseRootFromParent_Done,
66228 // Label 3805: @180115
66229 GIM_Try, /*On fail goto*//*Label 3806*/ GIMT_Encode4(180170), // Rule ID 2715 //
66230 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
66231 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftmad_x),
66232 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
66233 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
66234 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
66235 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66236 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66237 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66238 // MIs[0] imm
66239 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66240 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
66241 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1326:{ *:[iPTR] }, ZPR16:{ *:[nxv8f16] }:$Zn, ZPR16:{ *:[nxv8f16] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$imm) => (FTMAD_ZZI_H:{ *:[nxv8f16] } ZPR16:{ *:[nxv8f16] }:$Zn, ZPR16:{ *:[nxv8f16] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$imm)
66242 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTMAD_ZZI_H),
66243 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
66244 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
66245 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
66246 GIR_RootToRootCopy, /*OpIdx*/4, // imm
66247 GIR_RootConstrainSelectedInstOperands,
66248 // GIR_Coverage, 2715,
66249 GIR_EraseRootFromParent_Done,
66250 // Label 3806: @180170
66251 GIM_Try, /*On fail goto*//*Label 3807*/ GIMT_Encode4(180225), // Rule ID 2716 //
66252 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
66253 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftmad_x),
66254 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
66255 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
66256 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
66257 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66258 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66259 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66260 // MIs[0] imm
66261 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66262 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
66263 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1326:{ *:[iPTR] }, ZPR32:{ *:[nxv4f32] }:$Zn, ZPR32:{ *:[nxv4f32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$imm) => (FTMAD_ZZI_S:{ *:[nxv4f32] } ZPR32:{ *:[nxv4f32] }:$Zn, ZPR32:{ *:[nxv4f32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$imm)
66264 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTMAD_ZZI_S),
66265 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
66266 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
66267 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
66268 GIR_RootToRootCopy, /*OpIdx*/4, // imm
66269 GIR_RootConstrainSelectedInstOperands,
66270 // GIR_Coverage, 2716,
66271 GIR_EraseRootFromParent_Done,
66272 // Label 3807: @180225
66273 GIM_Try, /*On fail goto*//*Label 3808*/ GIMT_Encode4(180280), // Rule ID 2717 //
66274 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
66275 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftmad_x),
66276 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
66277 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
66278 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
66279 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66280 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66281 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66282 // MIs[0] imm
66283 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66284 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
66285 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1326:{ *:[iPTR] }, ZPR64:{ *:[nxv2f64] }:$Zn, ZPR64:{ *:[nxv2f64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$imm) => (FTMAD_ZZI_D:{ *:[nxv2f64] } ZPR64:{ *:[nxv2f64] }:$Zn, ZPR64:{ *:[nxv2f64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$imm)
66286 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTMAD_ZZI_D),
66287 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
66288 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
66289 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
66290 GIR_RootToRootCopy, /*OpIdx*/4, // imm
66291 GIR_RootConstrainSelectedInstOperands,
66292 // GIR_Coverage, 2717,
66293 GIR_EraseRootFromParent_Done,
66294 // Label 3808: @180280
66295 GIM_Try, /*On fail goto*//*Label 3809*/ GIMT_Encode4(180335), // Rule ID 3475 //
66296 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
66297 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_merging),
66298 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
66299 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
66300 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
66301 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66302 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66303 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
66304 // MIs[0] Idx
66305 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66306 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_1_1),
66307 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1409:{ *:[iPTR] }, ZPRAny:{ *:[nxv8i16] }:$Zd, PPR16:{ *:[nxv8i1] }:$Pn, (timm:{ *:[i32] })<<P:Predicate_timm32_1_1>>:$Idx) => (PMOV_ZIP_H:{ *:[nxv8i16] } ZPRAny:{ *:[nxv8i16] }:$Zd, (timm:{ *:[i32] })<<P:Predicate_timm32_1_1>>:$Idx, PPR16:{ *:[nxv8i1] }:$Pn)
66308 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_H),
66309 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
66310 GIR_RootToRootCopy, /*OpIdx*/2, // Zd
66311 GIR_RootToRootCopy, /*OpIdx*/4, // Idx
66312 GIR_RootToRootCopy, /*OpIdx*/3, // Pn
66313 GIR_RootConstrainSelectedInstOperands,
66314 // GIR_Coverage, 3475,
66315 GIR_EraseRootFromParent_Done,
66316 // Label 3809: @180335
66317 GIM_Try, /*On fail goto*//*Label 3810*/ GIMT_Encode4(180390), // Rule ID 3476 //
66318 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
66319 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_merging),
66320 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
66321 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
66322 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
66323 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66324 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66325 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
66326 // MIs[0] Idx
66327 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66328 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_1_3),
66329 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1409:{ *:[iPTR] }, ZPRAny:{ *:[nxv4i32] }:$Zd, PPR32:{ *:[nxv4i1] }:$Pn, (timm:{ *:[i32] })<<P:Predicate_timm32_1_3>>:$Idx) => (PMOV_ZIP_S:{ *:[nxv4i32] } ZPRAny:{ *:[nxv4i32] }:$Zd, (timm:{ *:[i32] })<<P:Predicate_timm32_1_3>>:$Idx, PPR32:{ *:[nxv4i1] }:$Pn)
66330 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_S),
66331 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
66332 GIR_RootToRootCopy, /*OpIdx*/2, // Zd
66333 GIR_RootToRootCopy, /*OpIdx*/4, // Idx
66334 GIR_RootToRootCopy, /*OpIdx*/3, // Pn
66335 GIR_RootConstrainSelectedInstOperands,
66336 // GIR_Coverage, 3476,
66337 GIR_EraseRootFromParent_Done,
66338 // Label 3810: @180390
66339 GIM_Try, /*On fail goto*//*Label 3811*/ GIMT_Encode4(180445), // Rule ID 3477 //
66340 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
66341 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_merging),
66342 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
66343 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
66344 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
66345 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66346 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66347 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
66348 // MIs[0] Idx
66349 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66350 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_1_7),
66351 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1409:{ *:[iPTR] }, ZPRAny:{ *:[nxv2i64] }:$Zd, PPR64:{ *:[nxv2i1] }:$Pn, (timm:{ *:[i32] })<<P:Predicate_timm32_1_7>>:$Idx) => (PMOV_ZIP_D:{ *:[nxv2i64] } ZPRAny:{ *:[nxv2i64] }:$Zd, (timm:{ *:[i32] })<<P:Predicate_timm32_1_7>>:$Idx, PPR64:{ *:[nxv2i1] }:$Pn)
66352 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_D),
66353 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
66354 GIR_RootToRootCopy, /*OpIdx*/2, // Zd
66355 GIR_RootToRootCopy, /*OpIdx*/4, // Idx
66356 GIR_RootToRootCopy, /*OpIdx*/3, // Pn
66357 GIR_RootConstrainSelectedInstOperands,
66358 // GIR_Coverage, 3477,
66359 GIR_EraseRootFromParent_Done,
66360 // Label 3811: @180445
66361 GIM_Try, /*On fail goto*//*Label 3812*/ GIMT_Encode4(180500), // Rule ID 3713 //
66362 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
66363 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_xar),
66364 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
66365 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
66366 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
66367 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
66368 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
66369 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
66370 // MIs[0] imm
66371 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66372 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm0_63),
66373 // (intrinsic_wo_chain:{ *:[v2i64] } 525:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_timm0_63>>:$imm) => (XAR:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_timm0_63>>:$imm)
66374 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XAR),
66375 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
66376 GIR_RootToRootCopy, /*OpIdx*/2, // Vn
66377 GIR_RootToRootCopy, /*OpIdx*/3, // Vm
66378 GIR_RootToRootCopy, /*OpIdx*/4, // imm
66379 GIR_RootConstrainSelectedInstOperands,
66380 // GIR_Coverage, 3713,
66381 GIR_EraseRootFromParent_Done,
66382 // Label 3812: @180500
66383 GIM_Try, /*On fail goto*//*Label 3813*/ GIMT_Encode4(180547), // Rule ID 2775 //
66384 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasB16B16_HasSVE2orSME2),
66385 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul_lane),
66386 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
66387 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
66388 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
66389 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66390 // MIs[0] idx
66391 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66392 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
66393 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1290:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx) => (BFMUL_ZZZI:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)
66394 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMUL_ZZZI),
66395 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
66396 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66397 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66398 GIR_RootToRootCopy, /*OpIdx*/4, // idx
66399 GIR_RootConstrainSelectedInstOperands,
66400 // GIR_Coverage, 2775,
66401 GIR_EraseRootFromParent_Done,
66402 // Label 3813: @180547
66403 GIM_Try, /*On fail goto*//*Label 3814*/ GIMT_Encode4(180594), // Rule ID 2776 //
66404 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
66405 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul_lane),
66406 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
66407 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
66408 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
66409 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66410 // MIs[0] idx
66411 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66412 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
66413 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1290:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx) => (FMUL_ZZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)
66414 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_H),
66415 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
66416 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66417 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66418 GIR_RootToRootCopy, /*OpIdx*/4, // idx
66419 GIR_RootConstrainSelectedInstOperands,
66420 // GIR_Coverage, 2776,
66421 GIR_EraseRootFromParent_Done,
66422 // Label 3814: @180594
66423 GIM_Try, /*On fail goto*//*Label 3815*/ GIMT_Encode4(180641), // Rule ID 2777 //
66424 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
66425 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul_lane),
66426 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
66427 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
66428 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
66429 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66430 // MIs[0] idx
66431 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66432 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
66433 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1290:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx) => (FMUL_ZZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
66434 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_S),
66435 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
66436 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66437 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66438 GIR_RootToRootCopy, /*OpIdx*/4, // idx
66439 GIR_RootConstrainSelectedInstOperands,
66440 // GIR_Coverage, 2777,
66441 GIR_EraseRootFromParent_Done,
66442 // Label 3815: @180641
66443 GIM_Try, /*On fail goto*//*Label 3816*/ GIMT_Encode4(180688), // Rule ID 2778 //
66444 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
66445 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul_lane),
66446 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
66447 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
66448 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
66449 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66450 // MIs[0] idx
66451 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66452 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
66453 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1290:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx) => (FMUL_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)
66454 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_D),
66455 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
66456 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66457 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66458 GIR_RootToRootCopy, /*OpIdx*/4, // idx
66459 GIR_RootConstrainSelectedInstOperands,
66460 // GIR_Coverage, 2778,
66461 GIR_EraseRootFromParent_Done,
66462 // Label 3816: @180688
66463 GIM_Try, /*On fail goto*//*Label 3817*/ GIMT_Encode4(180735), // Rule ID 2929 //
66464 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
66465 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mul_lane),
66466 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
66467 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
66468 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
66469 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66470 // MIs[0] Op3
66471 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66472 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
66473 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1390:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3) => (MUL_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
66474 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MUL_ZZZI_H),
66475 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
66476 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66477 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66478 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66479 GIR_RootConstrainSelectedInstOperands,
66480 // GIR_Coverage, 2929,
66481 GIR_EraseRootFromParent_Done,
66482 // Label 3817: @180735
66483 GIM_Try, /*On fail goto*//*Label 3818*/ GIMT_Encode4(180782), // Rule ID 2930 //
66484 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
66485 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mul_lane),
66486 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
66487 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
66488 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
66489 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66490 // MIs[0] Op3
66491 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66492 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
66493 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1390:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3) => (MUL_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
66494 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MUL_ZZZI_S),
66495 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
66496 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66497 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66498 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66499 GIR_RootConstrainSelectedInstOperands,
66500 // GIR_Coverage, 2930,
66501 GIR_EraseRootFromParent_Done,
66502 // Label 3818: @180782
66503 GIM_Try, /*On fail goto*//*Label 3819*/ GIMT_Encode4(180829), // Rule ID 2931 //
66504 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
66505 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mul_lane),
66506 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
66507 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
66508 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
66509 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66510 // MIs[0] Op3
66511 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66512 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
66513 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1390:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op3) => (MUL_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op3)
66514 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MUL_ZZZI_D),
66515 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
66516 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66517 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66518 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66519 GIR_RootConstrainSelectedInstOperands,
66520 // GIR_Coverage, 2931,
66521 GIR_EraseRootFromParent_Done,
66522 // Label 3819: @180829
66523 GIM_Try, /*On fail goto*//*Label 3820*/ GIMT_Encode4(180876), // Rule ID 2932 //
66524 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
66525 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullb_lane),
66526 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
66527 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
66528 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
66529 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66530 // MIs[0] Op3
66531 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66532 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
66533 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1536:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3) => (SMULLB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
66534 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLB_ZZZI_S),
66535 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
66536 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66537 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66538 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66539 GIR_RootConstrainSelectedInstOperands,
66540 // GIR_Coverage, 2932,
66541 GIR_EraseRootFromParent_Done,
66542 // Label 3820: @180876
66543 GIM_Try, /*On fail goto*//*Label 3821*/ GIMT_Encode4(180923), // Rule ID 2933 //
66544 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
66545 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullb_lane),
66546 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
66547 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
66548 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
66549 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66550 // MIs[0] Op3
66551 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66552 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
66553 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1536:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3) => (SMULLB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
66554 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLB_ZZZI_D),
66555 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
66556 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66557 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66558 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66559 GIR_RootConstrainSelectedInstOperands,
66560 // GIR_Coverage, 2933,
66561 GIR_EraseRootFromParent_Done,
66562 // Label 3821: @180923
66563 GIM_Try, /*On fail goto*//*Label 3822*/ GIMT_Encode4(180970), // Rule ID 2981 //
66564 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
66565 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssra),
66566 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
66567 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
66568 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
66569 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66570 // MIs[0] Op3
66571 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66572 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
66573 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1647:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3) => (SSRA_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
66574 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRA_ZZI_B),
66575 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
66576 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66577 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66578 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66579 GIR_RootConstrainSelectedInstOperands,
66580 // GIR_Coverage, 2981,
66581 GIR_EraseRootFromParent_Done,
66582 // Label 3822: @180970
66583 GIM_Try, /*On fail goto*//*Label 3823*/ GIMT_Encode4(181017), // Rule ID 2983 //
66584 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
66585 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssra),
66586 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
66587 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
66588 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
66589 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66590 // MIs[0] Op3
66591 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66592 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
66593 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1647:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3) => (SSRA_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
66594 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRA_ZZI_H),
66595 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
66596 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66597 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66598 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66599 GIR_RootConstrainSelectedInstOperands,
66600 // GIR_Coverage, 2983,
66601 GIR_EraseRootFromParent_Done,
66602 // Label 3823: @181017
66603 GIM_Try, /*On fail goto*//*Label 3824*/ GIMT_Encode4(181064), // Rule ID 2985 //
66604 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
66605 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssra),
66606 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
66607 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
66608 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
66609 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66610 // MIs[0] Op3
66611 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66612 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
66613 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1647:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3) => (SSRA_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
66614 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRA_ZZI_S),
66615 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
66616 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66617 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66618 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66619 GIR_RootConstrainSelectedInstOperands,
66620 // GIR_Coverage, 2985,
66621 GIR_EraseRootFromParent_Done,
66622 // Label 3824: @181064
66623 GIM_Try, /*On fail goto*//*Label 3825*/ GIMT_Encode4(181111), // Rule ID 2987 //
66624 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
66625 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssra),
66626 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
66627 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
66628 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
66629 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66630 // MIs[0] Op3
66631 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66632 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR64),
66633 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1647:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3) => (SSRA_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)
66634 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRA_ZZI_D),
66635 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
66636 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66637 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66638 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66639 GIR_RootConstrainSelectedInstOperands,
66640 // GIR_Coverage, 2987,
66641 GIR_EraseRootFromParent_Done,
66642 // Label 3825: @181111
66643 GIM_Try, /*On fail goto*//*Label 3826*/ GIMT_Encode4(181158), // Rule ID 3009 //
66644 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
66645 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrunt),
66646 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
66647 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
66648 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
66649 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66650 // MIs[0] Op3
66651 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66652 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
66653 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1627:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3) => (SQSHRUNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
66654 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNT_ZZI_B),
66655 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
66656 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66657 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66658 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66659 GIR_RootConstrainSelectedInstOperands,
66660 // GIR_Coverage, 3009,
66661 GIR_EraseRootFromParent_Done,
66662 // Label 3826: @181158
66663 GIM_Try, /*On fail goto*//*Label 3827*/ GIMT_Encode4(181205), // Rule ID 3010 //
66664 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
66665 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrunt),
66666 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
66667 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
66668 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
66669 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66670 // MIs[0] Op3
66671 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66672 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
66673 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1627:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3) => (SQSHRUNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
66674 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNT_ZZI_H),
66675 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
66676 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66677 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66678 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66679 GIR_RootConstrainSelectedInstOperands,
66680 // GIR_Coverage, 3010,
66681 GIR_EraseRootFromParent_Done,
66682 // Label 3827: @181205
66683 GIM_Try, /*On fail goto*//*Label 3828*/ GIMT_Encode4(181252), // Rule ID 3011 //
66684 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
66685 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrunt),
66686 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
66687 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
66688 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
66689 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66690 // MIs[0] Op3
66691 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66692 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
66693 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1627:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3) => (SQSHRUNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
66694 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNT_ZZI_S),
66695 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
66696 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66697 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66698 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66699 GIR_RootConstrainSelectedInstOperands,
66700 // GIR_Coverage, 3011,
66701 GIR_EraseRootFromParent_Done,
66702 // Label 3828: @181252
66703 GIM_Try, /*On fail goto*//*Label 3829*/ GIMT_Encode4(181299), // Rule ID 3080 //
66704 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
66705 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_xar),
66706 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
66707 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
66708 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
66709 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66710 // MIs[0] Op3
66711 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66712 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
66713 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1928:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3) => (XAR_ZZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
66714 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XAR_ZZZI_B),
66715 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
66716 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66717 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66718 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66719 GIR_RootConstrainSelectedInstOperands,
66720 // GIR_Coverage, 3080,
66721 GIR_EraseRootFromParent_Done,
66722 // Label 3829: @181299
66723 GIM_Try, /*On fail goto*//*Label 3830*/ GIMT_Encode4(181346), // Rule ID 3081 //
66724 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
66725 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_xar),
66726 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
66727 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
66728 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
66729 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66730 // MIs[0] Op3
66731 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66732 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
66733 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1928:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3) => (XAR_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
66734 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XAR_ZZZI_H),
66735 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
66736 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66737 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66738 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66739 GIR_RootConstrainSelectedInstOperands,
66740 // GIR_Coverage, 3081,
66741 GIR_EraseRootFromParent_Done,
66742 // Label 3830: @181346
66743 GIM_Try, /*On fail goto*//*Label 3831*/ GIMT_Encode4(181393), // Rule ID 3082 //
66744 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
66745 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_xar),
66746 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
66747 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
66748 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
66749 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66750 // MIs[0] Op3
66751 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66752 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
66753 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1928:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3) => (XAR_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
66754 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XAR_ZZZI_S),
66755 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
66756 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66757 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66758 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66759 GIR_RootConstrainSelectedInstOperands,
66760 // GIR_Coverage, 3082,
66761 GIR_EraseRootFromParent_Done,
66762 // Label 3831: @181393
66763 GIM_Try, /*On fail goto*//*Label 3832*/ GIMT_Encode4(181440), // Rule ID 3083 //
66764 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
66765 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_xar),
66766 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
66767 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
66768 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
66769 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66770 // MIs[0] Op3
66771 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66772 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR64),
66773 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1928:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3) => (XAR_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)
66774 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XAR_ZZZI_D),
66775 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
66776 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66777 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66778 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66779 GIR_RootConstrainSelectedInstOperands,
66780 // GIR_Coverage, 3083,
66781 GIR_EraseRootFromParent_Done,
66782 // Label 3832: @181440
66783 GIM_Try, /*On fail goto*//*Label 3833*/ GIMT_Encode4(181487), // Rule ID 3459 //
66784 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
66785 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_extq),
66786 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
66787 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
66788 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
66789 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66790 // MIs[0] Op3
66791 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66792 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_15),
66793 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1173:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3) => (EXTQ_ZZI:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3)
66794 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTQ_ZZI),
66795 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
66796 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66797 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66798 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66799 GIR_RootConstrainSelectedInstOperands,
66800 // GIR_Coverage, 3459,
66801 GIR_EraseRootFromParent_Done,
66802 // Label 3833: @181487
66803 GIM_Try, /*On fail goto*//*Label 3834*/ GIMT_Encode4(181534), // Rule ID 3460 //
66804 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
66805 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_extq),
66806 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
66807 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
66808 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
66809 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66810 // MIs[0] Op3
66811 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66812 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_15),
66813 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1173:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3) => (EXTQ_ZZI:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3)
66814 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTQ_ZZI),
66815 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
66816 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66817 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66818 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66819 GIR_RootConstrainSelectedInstOperands,
66820 // GIR_Coverage, 3460,
66821 GIR_EraseRootFromParent_Done,
66822 // Label 3834: @181534
66823 GIM_Try, /*On fail goto*//*Label 3835*/ GIMT_Encode4(181581), // Rule ID 3461 //
66824 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
66825 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_extq),
66826 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
66827 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
66828 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
66829 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66830 // MIs[0] Op3
66831 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66832 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_15),
66833 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1173:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3) => (EXTQ_ZZI:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3)
66834 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTQ_ZZI),
66835 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
66836 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66837 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66838 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66839 GIR_RootConstrainSelectedInstOperands,
66840 // GIR_Coverage, 3461,
66841 GIR_EraseRootFromParent_Done,
66842 // Label 3835: @181581
66843 GIM_Try, /*On fail goto*//*Label 3836*/ GIMT_Encode4(181628), // Rule ID 3462 //
66844 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
66845 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_extq),
66846 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
66847 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
66848 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
66849 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66850 // MIs[0] Op3
66851 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66852 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_15),
66853 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1173:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3) => (EXTQ_ZZI:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3)
66854 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTQ_ZZI),
66855 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
66856 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66857 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66858 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66859 GIR_RootConstrainSelectedInstOperands,
66860 // GIR_Coverage, 3462,
66861 GIR_EraseRootFromParent_Done,
66862 // Label 3836: @181628
66863 GIM_Try, /*On fail goto*//*Label 3837*/ GIMT_Encode4(181675), // Rule ID 3463 //
66864 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
66865 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_extq),
66866 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
66867 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
66868 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
66869 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66870 // MIs[0] Op3
66871 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66872 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_15),
66873 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1173:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3) => (EXTQ_ZZI:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3)
66874 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTQ_ZZI),
66875 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
66876 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66877 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66878 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66879 GIR_RootConstrainSelectedInstOperands,
66880 // GIR_Coverage, 3463,
66881 GIR_EraseRootFromParent_Done,
66882 // Label 3837: @181675
66883 GIM_Try, /*On fail goto*//*Label 3838*/ GIMT_Encode4(181722), // Rule ID 3464 //
66884 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
66885 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_extq),
66886 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
66887 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
66888 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
66889 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66890 // MIs[0] Op3
66891 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66892 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_15),
66893 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1173:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3) => (EXTQ_ZZI:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3)
66894 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTQ_ZZI),
66895 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
66896 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66897 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66898 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66899 GIR_RootConstrainSelectedInstOperands,
66900 // GIR_Coverage, 3464,
66901 GIR_EraseRootFromParent_Done,
66902 // Label 3838: @181722
66903 GIM_Try, /*On fail goto*//*Label 3839*/ GIMT_Encode4(181769), // Rule ID 3465 //
66904 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
66905 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_extq),
66906 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
66907 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
66908 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
66909 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66910 // MIs[0] Op3
66911 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66912 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_15),
66913 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1173:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3) => (EXTQ_ZZI:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3)
66914 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTQ_ZZI),
66915 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
66916 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66917 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66918 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66919 GIR_RootConstrainSelectedInstOperands,
66920 // GIR_Coverage, 3465,
66921 GIR_EraseRootFromParent_Done,
66922 // Label 3839: @181769
66923 GIM_Try, /*On fail goto*//*Label 3840*/ GIMT_Encode4(181816), // Rule ID 3466 //
66924 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
66925 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_extq),
66926 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
66927 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
66928 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
66929 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66930 // MIs[0] Op3
66931 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66932 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_15),
66933 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1173:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3) => (EXTQ_ZZI:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3)
66934 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTQ_ZZI),
66935 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
66936 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66937 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66938 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66939 GIR_RootConstrainSelectedInstOperands,
66940 // GIR_Coverage, 3466,
66941 GIR_EraseRootFromParent_Done,
66942 // Label 3840: @181816
66943 GIM_Try, /*On fail goto*//*Label 3841*/ GIMT_Encode4(181863), // Rule ID 10983 //
66944 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
66945 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh_lane),
66946 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
66947 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
66948 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
66949 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66950 // MIs[0] Op3
66951 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66952 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
66953 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1577:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3) => (SQDMULH_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
66954 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZI_H),
66955 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
66956 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66957 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66958 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66959 GIR_RootConstrainSelectedInstOperands,
66960 // GIR_Coverage, 10983,
66961 GIR_EraseRootFromParent_Done,
66962 // Label 3841: @181863
66963 GIM_Try, /*On fail goto*//*Label 3842*/ GIMT_Encode4(181910), // Rule ID 10984 //
66964 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
66965 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh_lane),
66966 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
66967 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
66968 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
66969 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66970 // MIs[0] Op3
66971 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66972 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
66973 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1577:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3) => (SQDMULH_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
66974 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZI_S),
66975 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
66976 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66977 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66978 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66979 GIR_RootConstrainSelectedInstOperands,
66980 // GIR_Coverage, 10984,
66981 GIR_EraseRootFromParent_Done,
66982 // Label 3842: @181910
66983 GIM_Try, /*On fail goto*//*Label 3843*/ GIMT_Encode4(181957), // Rule ID 10985 //
66984 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
66985 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh_lane),
66986 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
66987 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
66988 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
66989 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
66990 // MIs[0] Op3
66991 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
66992 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
66993 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1577:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op3) => (SQDMULH_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op3)
66994 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZI_D),
66995 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
66996 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
66997 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
66998 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
66999 GIR_RootConstrainSelectedInstOperands,
67000 // GIR_Coverage, 10985,
67001 GIR_EraseRootFromParent_Done,
67002 // Label 3843: @181957
67003 GIM_Try, /*On fail goto*//*Label 3844*/ GIMT_Encode4(182004), // Rule ID 10986 //
67004 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67005 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh_lane),
67006 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
67007 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
67008 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
67009 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67010 // MIs[0] Op3
67011 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67012 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
67013 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1608:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3) => (SQRDMULH_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
67014 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZI_H),
67015 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67016 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67017 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67018 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67019 GIR_RootConstrainSelectedInstOperands,
67020 // GIR_Coverage, 10986,
67021 GIR_EraseRootFromParent_Done,
67022 // Label 3844: @182004
67023 GIM_Try, /*On fail goto*//*Label 3845*/ GIMT_Encode4(182051), // Rule ID 10987 //
67024 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67025 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh_lane),
67026 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
67027 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
67028 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
67029 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67030 // MIs[0] Op3
67031 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67032 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
67033 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1608:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3) => (SQRDMULH_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
67034 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZI_S),
67035 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67036 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67037 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67038 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67039 GIR_RootConstrainSelectedInstOperands,
67040 // GIR_Coverage, 10987,
67041 GIR_EraseRootFromParent_Done,
67042 // Label 3845: @182051
67043 GIM_Try, /*On fail goto*//*Label 3846*/ GIMT_Encode4(182098), // Rule ID 10988 //
67044 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67045 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh_lane),
67046 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
67047 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
67048 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
67049 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67050 // MIs[0] Op3
67051 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67052 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
67053 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1608:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op3) => (SQRDMULH_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op3)
67054 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZI_D),
67055 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67056 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67057 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67058 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67059 GIR_RootConstrainSelectedInstOperands,
67060 // GIR_Coverage, 10988,
67061 GIR_EraseRootFromParent_Done,
67062 // Label 3846: @182098
67063 GIM_Try, /*On fail goto*//*Label 3847*/ GIMT_Encode4(182145), // Rule ID 11011 //
67064 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67065 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullt_lane),
67066 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
67067 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
67068 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
67069 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67070 // MIs[0] Op3
67071 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67072 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
67073 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1538:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3) => (SMULLT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
67074 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLT_ZZZI_S),
67075 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67076 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67077 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67078 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67079 GIR_RootConstrainSelectedInstOperands,
67080 // GIR_Coverage, 11011,
67081 GIR_EraseRootFromParent_Done,
67082 // Label 3847: @182145
67083 GIM_Try, /*On fail goto*//*Label 3848*/ GIMT_Encode4(182192), // Rule ID 11012 //
67084 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67085 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullt_lane),
67086 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
67087 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
67088 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
67089 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67090 // MIs[0] Op3
67091 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67092 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
67093 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1538:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3) => (SMULLT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
67094 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLT_ZZZI_D),
67095 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67096 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67097 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67098 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67099 GIR_RootConstrainSelectedInstOperands,
67100 // GIR_Coverage, 11012,
67101 GIR_EraseRootFromParent_Done,
67102 // Label 3848: @182192
67103 GIM_Try, /*On fail goto*//*Label 3849*/ GIMT_Encode4(182239), // Rule ID 11013 //
67104 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67105 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullb_lane),
67106 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
67107 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
67108 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
67109 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67110 // MIs[0] Op3
67111 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67112 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
67113 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1774:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3) => (UMULLB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
67114 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLB_ZZZI_S),
67115 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67116 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67117 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67118 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67119 GIR_RootConstrainSelectedInstOperands,
67120 // GIR_Coverage, 11013,
67121 GIR_EraseRootFromParent_Done,
67122 // Label 3849: @182239
67123 GIM_Try, /*On fail goto*//*Label 3850*/ GIMT_Encode4(182286), // Rule ID 11014 //
67124 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67125 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullb_lane),
67126 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
67127 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
67128 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
67129 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67130 // MIs[0] Op3
67131 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67132 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
67133 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1774:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3) => (UMULLB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
67134 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLB_ZZZI_D),
67135 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67136 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67137 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67138 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67139 GIR_RootConstrainSelectedInstOperands,
67140 // GIR_Coverage, 11014,
67141 GIR_EraseRootFromParent_Done,
67142 // Label 3850: @182286
67143 GIM_Try, /*On fail goto*//*Label 3851*/ GIMT_Encode4(182333), // Rule ID 11015 //
67144 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67145 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullt_lane),
67146 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
67147 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
67148 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
67149 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67150 // MIs[0] Op3
67151 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67152 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
67153 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1776:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3) => (UMULLT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
67154 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLT_ZZZI_S),
67155 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67156 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67157 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67158 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67159 GIR_RootConstrainSelectedInstOperands,
67160 // GIR_Coverage, 11015,
67161 GIR_EraseRootFromParent_Done,
67162 // Label 3851: @182333
67163 GIM_Try, /*On fail goto*//*Label 3852*/ GIMT_Encode4(182380), // Rule ID 11016 //
67164 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67165 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullt_lane),
67166 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
67167 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
67168 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
67169 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67170 // MIs[0] Op3
67171 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67172 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
67173 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1776:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3) => (UMULLT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
67174 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLT_ZZZI_D),
67175 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67176 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67177 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67178 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67179 GIR_RootConstrainSelectedInstOperands,
67180 // GIR_Coverage, 11016,
67181 GIR_EraseRootFromParent_Done,
67182 // Label 3852: @182380
67183 GIM_Try, /*On fail goto*//*Label 3853*/ GIMT_Encode4(182427), // Rule ID 11017 //
67184 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67185 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullb_lane),
67186 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
67187 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
67188 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
67189 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67190 // MIs[0] Op3
67191 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67192 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
67193 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1583:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3) => (SQDMULLB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
67194 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLB_ZZZI_S),
67195 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67196 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67197 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67198 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67199 GIR_RootConstrainSelectedInstOperands,
67200 // GIR_Coverage, 11017,
67201 GIR_EraseRootFromParent_Done,
67202 // Label 3853: @182427
67203 GIM_Try, /*On fail goto*//*Label 3854*/ GIMT_Encode4(182474), // Rule ID 11018 //
67204 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67205 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullb_lane),
67206 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
67207 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
67208 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
67209 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67210 // MIs[0] Op3
67211 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67212 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
67213 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1583:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3) => (SQDMULLB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
67214 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLB_ZZZI_D),
67215 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67216 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67217 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67218 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67219 GIR_RootConstrainSelectedInstOperands,
67220 // GIR_Coverage, 11018,
67221 GIR_EraseRootFromParent_Done,
67222 // Label 3854: @182474
67223 GIM_Try, /*On fail goto*//*Label 3855*/ GIMT_Encode4(182521), // Rule ID 11019 //
67224 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67225 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullt_lane),
67226 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
67227 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
67228 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
67229 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67230 // MIs[0] Op3
67231 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67232 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
67233 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1585:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3) => (SQDMULLT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
67234 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLT_ZZZI_S),
67235 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67236 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67237 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67238 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67239 GIR_RootConstrainSelectedInstOperands,
67240 // GIR_Coverage, 11019,
67241 GIR_EraseRootFromParent_Done,
67242 // Label 3855: @182521
67243 GIM_Try, /*On fail goto*//*Label 3856*/ GIMT_Encode4(182568), // Rule ID 11020 //
67244 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67245 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullt_lane),
67246 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
67247 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
67248 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
67249 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67250 // MIs[0] Op3
67251 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67252 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
67253 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1585:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3) => (SQDMULLT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
67254 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLT_ZZZI_D),
67255 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67256 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67257 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67258 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67259 GIR_RootConstrainSelectedInstOperands,
67260 // GIR_Coverage, 11020,
67261 GIR_EraseRootFromParent_Done,
67262 // Label 3856: @182568
67263 GIM_Try, /*On fail goto*//*Label 3857*/ GIMT_Encode4(182615), // Rule ID 11264 //
67264 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67265 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshr),
67266 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
67267 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
67268 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
67269 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67270 // MIs[0] Op3
67271 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67272 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
67273 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1643:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3) => (SRSHR_ZPmI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
67274 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHR_ZPmI_B),
67275 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
67276 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67277 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67278 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67279 GIR_RootConstrainSelectedInstOperands,
67280 // GIR_Coverage, 11264,
67281 GIR_EraseRootFromParent_Done,
67282 // Label 3857: @182615
67283 GIM_Try, /*On fail goto*//*Label 3858*/ GIMT_Encode4(182662), // Rule ID 11265 //
67284 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67285 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshr),
67286 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
67287 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
67288 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
67289 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67290 // MIs[0] Op3
67291 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67292 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
67293 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1643:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3) => (SRSHR_ZPmI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
67294 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHR_ZPmI_H),
67295 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
67296 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67297 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67298 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67299 GIR_RootConstrainSelectedInstOperands,
67300 // GIR_Coverage, 11265,
67301 GIR_EraseRootFromParent_Done,
67302 // Label 3858: @182662
67303 GIM_Try, /*On fail goto*//*Label 3859*/ GIMT_Encode4(182709), // Rule ID 11266 //
67304 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67305 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshr),
67306 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
67307 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
67308 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
67309 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67310 // MIs[0] Op3
67311 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67312 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
67313 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1643:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3) => (SRSHR_ZPmI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
67314 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHR_ZPmI_S),
67315 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
67316 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67317 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67318 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67319 GIR_RootConstrainSelectedInstOperands,
67320 // GIR_Coverage, 11266,
67321 GIR_EraseRootFromParent_Done,
67322 // Label 3859: @182709
67323 GIM_Try, /*On fail goto*//*Label 3860*/ GIMT_Encode4(182756), // Rule ID 11267 //
67324 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67325 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshr),
67326 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
67327 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
67328 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
67329 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67330 // MIs[0] Op3
67331 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67332 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR64),
67333 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1643:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3) => (SRSHR_ZPmI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)
67334 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHR_ZPmI_D),
67335 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
67336 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67337 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67338 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67339 GIR_RootConstrainSelectedInstOperands,
67340 // GIR_Coverage, 11267,
67341 GIR_EraseRootFromParent_Done,
67342 // Label 3860: @182756
67343 GIM_Try, /*On fail goto*//*Label 3861*/ GIMT_Encode4(182803), // Rule ID 11268 //
67344 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67345 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshr),
67346 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
67347 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
67348 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
67349 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67350 // MIs[0] Op3
67351 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67352 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
67353 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1834:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3) => (URSHR_ZPmI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
67354 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHR_ZPmI_B),
67355 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
67356 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67357 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67358 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67359 GIR_RootConstrainSelectedInstOperands,
67360 // GIR_Coverage, 11268,
67361 GIR_EraseRootFromParent_Done,
67362 // Label 3861: @182803
67363 GIM_Try, /*On fail goto*//*Label 3862*/ GIMT_Encode4(182850), // Rule ID 11270 //
67364 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67365 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshr),
67366 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
67367 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
67368 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
67369 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67370 // MIs[0] Op3
67371 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67372 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
67373 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1834:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3) => (URSHR_ZPmI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
67374 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHR_ZPmI_H),
67375 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
67376 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67377 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67378 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67379 GIR_RootConstrainSelectedInstOperands,
67380 // GIR_Coverage, 11270,
67381 GIR_EraseRootFromParent_Done,
67382 // Label 3862: @182850
67383 GIM_Try, /*On fail goto*//*Label 3863*/ GIMT_Encode4(182897), // Rule ID 11272 //
67384 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67385 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshr),
67386 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
67387 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
67388 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
67389 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67390 // MIs[0] Op3
67391 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67392 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
67393 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1834:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3) => (URSHR_ZPmI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
67394 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHR_ZPmI_S),
67395 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
67396 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67397 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67398 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67399 GIR_RootConstrainSelectedInstOperands,
67400 // GIR_Coverage, 11272,
67401 GIR_EraseRootFromParent_Done,
67402 // Label 3863: @182897
67403 GIM_Try, /*On fail goto*//*Label 3864*/ GIMT_Encode4(182944), // Rule ID 11274 //
67404 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67405 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshr),
67406 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
67407 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
67408 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
67409 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67410 // MIs[0] Op3
67411 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67412 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR64),
67413 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1834:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3) => (URSHR_ZPmI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)
67414 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHR_ZPmI_D),
67415 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
67416 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67417 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67418 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67419 GIR_RootConstrainSelectedInstOperands,
67420 // GIR_Coverage, 11274,
67421 GIR_EraseRootFromParent_Done,
67422 // Label 3864: @182944
67423 GIM_Try, /*On fail goto*//*Label 3865*/ GIMT_Encode4(182991), // Rule ID 11276 //
67424 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67425 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshlu),
67426 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
67427 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
67428 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
67429 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67430 // MIs[0] Op3
67431 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67432 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL8),
67433 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1623:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op3) => (SQSHLU_ZPmI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL8>>:$Op3)
67434 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLU_ZPmI_B),
67435 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
67436 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67437 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67438 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67439 GIR_RootConstrainSelectedInstOperands,
67440 // GIR_Coverage, 11276,
67441 GIR_EraseRootFromParent_Done,
67442 // Label 3865: @182991
67443 GIM_Try, /*On fail goto*//*Label 3866*/ GIMT_Encode4(183038), // Rule ID 11277 //
67444 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67445 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshlu),
67446 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
67447 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
67448 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
67449 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67450 // MIs[0] Op3
67451 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67452 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL16),
67453 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1623:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op3) => (SQSHLU_ZPmI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL16>>:$Op3)
67454 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLU_ZPmI_H),
67455 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
67456 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67457 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67458 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67459 GIR_RootConstrainSelectedInstOperands,
67460 // GIR_Coverage, 11277,
67461 GIR_EraseRootFromParent_Done,
67462 // Label 3866: @183038
67463 GIM_Try, /*On fail goto*//*Label 3867*/ GIMT_Encode4(183085), // Rule ID 11278 //
67464 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67465 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshlu),
67466 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
67467 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
67468 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
67469 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67470 // MIs[0] Op3
67471 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67472 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL32),
67473 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1623:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op3) => (SQSHLU_ZPmI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL32>>:$Op3)
67474 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLU_ZPmI_S),
67475 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
67476 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67477 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67478 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67479 GIR_RootConstrainSelectedInstOperands,
67480 // GIR_Coverage, 11278,
67481 GIR_EraseRootFromParent_Done,
67482 // Label 3867: @183085
67483 GIM_Try, /*On fail goto*//*Label 3868*/ GIMT_Encode4(183132), // Rule ID 11279 //
67484 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67485 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshlu),
67486 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
67487 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
67488 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
67489 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67490 // MIs[0] Op3
67491 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67492 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftL64),
67493 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1623:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL64>>:$Op3) => (SQSHLU_ZPmI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftL64>>:$Op3)
67494 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLU_ZPmI_D),
67495 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
67496 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67497 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67498 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67499 GIR_RootConstrainSelectedInstOperands,
67500 // GIR_Coverage, 11279,
67501 GIR_EraseRootFromParent_Done,
67502 // Label 3868: @183132
67503 GIM_Try, /*On fail goto*//*Label 3869*/ GIMT_Encode4(183179), // Rule ID 11354 //
67504 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67505 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usra),
67506 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
67507 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
67508 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
67509 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67510 // MIs[0] Op3
67511 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67512 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
67513 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1843:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3) => (USRA_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
67514 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRA_ZZI_B),
67515 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
67516 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67517 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67518 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67519 GIR_RootConstrainSelectedInstOperands,
67520 // GIR_Coverage, 11354,
67521 GIR_EraseRootFromParent_Done,
67522 // Label 3869: @183179
67523 GIM_Try, /*On fail goto*//*Label 3870*/ GIMT_Encode4(183226), // Rule ID 11356 //
67524 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67525 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usra),
67526 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
67527 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
67528 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
67529 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67530 // MIs[0] Op3
67531 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67532 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
67533 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1843:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3) => (USRA_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
67534 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRA_ZZI_H),
67535 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
67536 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67537 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67538 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67539 GIR_RootConstrainSelectedInstOperands,
67540 // GIR_Coverage, 11356,
67541 GIR_EraseRootFromParent_Done,
67542 // Label 3870: @183226
67543 GIM_Try, /*On fail goto*//*Label 3871*/ GIMT_Encode4(183273), // Rule ID 11358 //
67544 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67545 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usra),
67546 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
67547 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
67548 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
67549 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67550 // MIs[0] Op3
67551 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67552 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
67553 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1843:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3) => (USRA_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
67554 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRA_ZZI_S),
67555 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
67556 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67557 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67558 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67559 GIR_RootConstrainSelectedInstOperands,
67560 // GIR_Coverage, 11358,
67561 GIR_EraseRootFromParent_Done,
67562 // Label 3871: @183273
67563 GIM_Try, /*On fail goto*//*Label 3872*/ GIMT_Encode4(183320), // Rule ID 11360 //
67564 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67565 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usra),
67566 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
67567 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
67568 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
67569 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67570 // MIs[0] Op3
67571 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67572 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR64),
67573 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1843:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3) => (USRA_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)
67574 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRA_ZZI_D),
67575 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
67576 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67577 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67578 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67579 GIR_RootConstrainSelectedInstOperands,
67580 // GIR_Coverage, 11360,
67581 GIR_EraseRootFromParent_Done,
67582 // Label 3872: @183320
67583 GIM_Try, /*On fail goto*//*Label 3873*/ GIMT_Encode4(183367), // Rule ID 11362 //
67584 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67585 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srsra),
67586 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
67587 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
67588 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
67589 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67590 // MIs[0] Op3
67591 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67592 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
67593 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1644:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3) => (SRSRA_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
67594 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRA_ZZI_B),
67595 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
67596 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67597 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67598 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67599 GIR_RootConstrainSelectedInstOperands,
67600 // GIR_Coverage, 11362,
67601 GIR_EraseRootFromParent_Done,
67602 // Label 3873: @183367
67603 GIM_Try, /*On fail goto*//*Label 3874*/ GIMT_Encode4(183414), // Rule ID 11363 //
67604 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67605 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srsra),
67606 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
67607 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
67608 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
67609 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67610 // MIs[0] Op3
67611 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67612 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
67613 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1644:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3) => (SRSRA_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
67614 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRA_ZZI_H),
67615 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
67616 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67617 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67618 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67619 GIR_RootConstrainSelectedInstOperands,
67620 // GIR_Coverage, 11363,
67621 GIR_EraseRootFromParent_Done,
67622 // Label 3874: @183414
67623 GIM_Try, /*On fail goto*//*Label 3875*/ GIMT_Encode4(183461), // Rule ID 11364 //
67624 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67625 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srsra),
67626 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
67627 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
67628 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
67629 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67630 // MIs[0] Op3
67631 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67632 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
67633 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1644:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3) => (SRSRA_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
67634 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRA_ZZI_S),
67635 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
67636 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67637 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67638 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67639 GIR_RootConstrainSelectedInstOperands,
67640 // GIR_Coverage, 11364,
67641 GIR_EraseRootFromParent_Done,
67642 // Label 3875: @183461
67643 GIM_Try, /*On fail goto*//*Label 3876*/ GIMT_Encode4(183508), // Rule ID 11365 //
67644 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67645 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srsra),
67646 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
67647 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
67648 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
67649 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67650 // MIs[0] Op3
67651 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67652 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR64),
67653 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1644:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3) => (SRSRA_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)
67654 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRA_ZZI_D),
67655 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
67656 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67657 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67658 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67659 GIR_RootConstrainSelectedInstOperands,
67660 // GIR_Coverage, 11365,
67661 GIR_EraseRootFromParent_Done,
67662 // Label 3876: @183508
67663 GIM_Try, /*On fail goto*//*Label 3877*/ GIMT_Encode4(183555), // Rule ID 11370 //
67664 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67665 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ursra),
67666 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
67667 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
67668 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
67669 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67670 // MIs[0] Op3
67671 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67672 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
67673 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1836:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3) => (URSRA_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
67674 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRA_ZZI_B),
67675 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
67676 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67677 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67678 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67679 GIR_RootConstrainSelectedInstOperands,
67680 // GIR_Coverage, 11370,
67681 GIR_EraseRootFromParent_Done,
67682 // Label 3877: @183555
67683 GIM_Try, /*On fail goto*//*Label 3878*/ GIMT_Encode4(183602), // Rule ID 11371 //
67684 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67685 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ursra),
67686 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
67687 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
67688 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
67689 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67690 // MIs[0] Op3
67691 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67692 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
67693 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1836:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3) => (URSRA_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
67694 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRA_ZZI_H),
67695 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
67696 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67697 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67698 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67699 GIR_RootConstrainSelectedInstOperands,
67700 // GIR_Coverage, 11371,
67701 GIR_EraseRootFromParent_Done,
67702 // Label 3878: @183602
67703 GIM_Try, /*On fail goto*//*Label 3879*/ GIMT_Encode4(183649), // Rule ID 11372 //
67704 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67705 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ursra),
67706 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
67707 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
67708 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
67709 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67710 // MIs[0] Op3
67711 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67712 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
67713 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1836:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3) => (URSRA_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
67714 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRA_ZZI_S),
67715 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
67716 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67717 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67718 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67719 GIR_RootConstrainSelectedInstOperands,
67720 // GIR_Coverage, 11372,
67721 GIR_EraseRootFromParent_Done,
67722 // Label 3879: @183649
67723 GIM_Try, /*On fail goto*//*Label 3880*/ GIMT_Encode4(183696), // Rule ID 11373 //
67724 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67725 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ursra),
67726 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
67727 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
67728 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
67729 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67730 // MIs[0] Op3
67731 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67732 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR64),
67733 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1836:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3) => (URSRA_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR64>>:$Op3)
67734 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRA_ZZI_D),
67735 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
67736 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67737 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67738 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67739 GIR_RootConstrainSelectedInstOperands,
67740 // GIR_Coverage, 11373,
67741 GIR_EraseRootFromParent_Done,
67742 // Label 3880: @183696
67743 GIM_Try, /*On fail goto*//*Label 3881*/ GIMT_Encode4(183743), // Rule ID 11433 //
67744 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67745 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrunt),
67746 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
67747 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
67748 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
67749 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67750 // MIs[0] Op3
67751 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67752 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
67753 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1621:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3) => (SQRSHRUNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
67754 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNT_ZZI_B),
67755 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67756 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67757 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67758 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67759 GIR_RootConstrainSelectedInstOperands,
67760 // GIR_Coverage, 11433,
67761 GIR_EraseRootFromParent_Done,
67762 // Label 3881: @183743
67763 GIM_Try, /*On fail goto*//*Label 3882*/ GIMT_Encode4(183790), // Rule ID 11434 //
67764 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67765 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrunt),
67766 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
67767 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
67768 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
67769 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67770 // MIs[0] Op3
67771 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67772 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
67773 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1621:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3) => (SQRSHRUNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
67774 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNT_ZZI_H),
67775 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67776 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67777 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67778 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67779 GIR_RootConstrainSelectedInstOperands,
67780 // GIR_Coverage, 11434,
67781 GIR_EraseRootFromParent_Done,
67782 // Label 3882: @183790
67783 GIM_Try, /*On fail goto*//*Label 3883*/ GIMT_Encode4(183837), // Rule ID 11435 //
67784 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67785 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrunt),
67786 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
67787 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
67788 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
67789 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67790 // MIs[0] Op3
67791 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67792 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
67793 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1621:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3) => (SQRSHRUNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
67794 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNT_ZZI_S),
67795 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67796 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67797 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67798 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67799 GIR_RootConstrainSelectedInstOperands,
67800 // GIR_Coverage, 11435,
67801 GIR_EraseRootFromParent_Done,
67802 // Label 3883: @183837
67803 GIM_Try, /*On fail goto*//*Label 3884*/ GIMT_Encode4(183884), // Rule ID 11436 //
67804 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67805 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shrnt),
67806 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
67807 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
67808 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
67809 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67810 // MIs[0] Op3
67811 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67812 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
67813 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1500:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3) => (SHRNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
67814 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNT_ZZI_B),
67815 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67816 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67817 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67818 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67819 GIR_RootConstrainSelectedInstOperands,
67820 // GIR_Coverage, 11436,
67821 GIR_EraseRootFromParent_Done,
67822 // Label 3884: @183884
67823 GIM_Try, /*On fail goto*//*Label 3885*/ GIMT_Encode4(183931), // Rule ID 11437 //
67824 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67825 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shrnt),
67826 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
67827 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
67828 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
67829 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67830 // MIs[0] Op3
67831 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67832 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
67833 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1500:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3) => (SHRNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
67834 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNT_ZZI_H),
67835 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67836 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67837 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67838 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67839 GIR_RootConstrainSelectedInstOperands,
67840 // GIR_Coverage, 11437,
67841 GIR_EraseRootFromParent_Done,
67842 // Label 3885: @183931
67843 GIM_Try, /*On fail goto*//*Label 3886*/ GIMT_Encode4(183978), // Rule ID 11438 //
67844 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67845 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shrnt),
67846 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
67847 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
67848 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
67849 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67850 // MIs[0] Op3
67851 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67852 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
67853 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1500:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3) => (SHRNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
67854 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNT_ZZI_S),
67855 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67856 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67857 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67858 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67859 GIR_RootConstrainSelectedInstOperands,
67860 // GIR_Coverage, 11438,
67861 GIR_EraseRootFromParent_Done,
67862 // Label 3886: @183978
67863 GIM_Try, /*On fail goto*//*Label 3887*/ GIMT_Encode4(184025), // Rule ID 11439 //
67864 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67865 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rshrnt),
67866 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
67867 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
67868 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
67869 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67870 // MIs[0] Op3
67871 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67872 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
67873 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1458:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3) => (RSHRNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
67874 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNT_ZZI_B),
67875 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67876 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67877 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67878 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67879 GIR_RootConstrainSelectedInstOperands,
67880 // GIR_Coverage, 11439,
67881 GIR_EraseRootFromParent_Done,
67882 // Label 3887: @184025
67883 GIM_Try, /*On fail goto*//*Label 3888*/ GIMT_Encode4(184072), // Rule ID 11440 //
67884 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67885 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rshrnt),
67886 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
67887 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
67888 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
67889 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67890 // MIs[0] Op3
67891 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67892 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
67893 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1458:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3) => (RSHRNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
67894 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNT_ZZI_H),
67895 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67896 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67897 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67898 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67899 GIR_RootConstrainSelectedInstOperands,
67900 // GIR_Coverage, 11440,
67901 GIR_EraseRootFromParent_Done,
67902 // Label 3888: @184072
67903 GIM_Try, /*On fail goto*//*Label 3889*/ GIMT_Encode4(184119), // Rule ID 11441 //
67904 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67905 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rshrnt),
67906 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
67907 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
67908 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
67909 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67910 // MIs[0] Op3
67911 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67912 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
67913 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1458:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3) => (RSHRNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
67914 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNT_ZZI_S),
67915 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67916 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67917 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67918 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67919 GIR_RootConstrainSelectedInstOperands,
67920 // GIR_Coverage, 11441,
67921 GIR_EraseRootFromParent_Done,
67922 // Label 3889: @184119
67923 GIM_Try, /*On fail goto*//*Label 3890*/ GIMT_Encode4(184166), // Rule ID 11442 //
67924 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67925 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrnt),
67926 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
67927 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
67928 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
67929 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67930 // MIs[0] Op3
67931 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67932 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
67933 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1625:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3) => (SQSHRNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
67934 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNT_ZZI_B),
67935 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67936 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67937 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67938 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67939 GIR_RootConstrainSelectedInstOperands,
67940 // GIR_Coverage, 11442,
67941 GIR_EraseRootFromParent_Done,
67942 // Label 3890: @184166
67943 GIM_Try, /*On fail goto*//*Label 3891*/ GIMT_Encode4(184213), // Rule ID 11443 //
67944 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67945 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrnt),
67946 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
67947 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
67948 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
67949 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67950 // MIs[0] Op3
67951 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67952 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
67953 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1625:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3) => (SQSHRNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
67954 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNT_ZZI_H),
67955 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67956 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67957 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67958 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67959 GIR_RootConstrainSelectedInstOperands,
67960 // GIR_Coverage, 11443,
67961 GIR_EraseRootFromParent_Done,
67962 // Label 3891: @184213
67963 GIM_Try, /*On fail goto*//*Label 3892*/ GIMT_Encode4(184260), // Rule ID 11444 //
67964 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67965 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrnt),
67966 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
67967 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
67968 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
67969 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67970 // MIs[0] Op3
67971 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67972 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
67973 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1625:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3) => (SQSHRNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
67974 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNT_ZZI_S),
67975 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67976 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67977 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67978 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67979 GIR_RootConstrainSelectedInstOperands,
67980 // GIR_Coverage, 11444,
67981 GIR_EraseRootFromParent_Done,
67982 // Label 3892: @184260
67983 GIM_Try, /*On fail goto*//*Label 3893*/ GIMT_Encode4(184307), // Rule ID 11445 //
67984 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
67985 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrnt),
67986 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
67987 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
67988 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
67989 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
67990 // MIs[0] Op3
67991 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
67992 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
67993 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1615:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3) => (SQRSHRNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
67994 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNT_ZZI_B),
67995 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
67996 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
67997 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
67998 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
67999 GIR_RootConstrainSelectedInstOperands,
68000 // GIR_Coverage, 11445,
68001 GIR_EraseRootFromParent_Done,
68002 // Label 3893: @184307
68003 GIM_Try, /*On fail goto*//*Label 3894*/ GIMT_Encode4(184354), // Rule ID 11446 //
68004 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
68005 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrnt),
68006 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
68007 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
68008 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
68009 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68010 // MIs[0] Op3
68011 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
68012 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
68013 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1615:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3) => (SQRSHRNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
68014 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNT_ZZI_H),
68015 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68016 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
68017 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
68018 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
68019 GIR_RootConstrainSelectedInstOperands,
68020 // GIR_Coverage, 11446,
68021 GIR_EraseRootFromParent_Done,
68022 // Label 3894: @184354
68023 GIM_Try, /*On fail goto*//*Label 3895*/ GIMT_Encode4(184401), // Rule ID 11447 //
68024 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
68025 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrnt),
68026 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
68027 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
68028 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
68029 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68030 // MIs[0] Op3
68031 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
68032 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
68033 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1615:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3) => (SQRSHRNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
68034 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNT_ZZI_S),
68035 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68036 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
68037 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
68038 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
68039 GIR_RootConstrainSelectedInstOperands,
68040 // GIR_Coverage, 11447,
68041 GIR_EraseRootFromParent_Done,
68042 // Label 3895: @184401
68043 GIM_Try, /*On fail goto*//*Label 3896*/ GIMT_Encode4(184448), // Rule ID 11448 //
68044 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
68045 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshrnt),
68046 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
68047 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
68048 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
68049 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68050 // MIs[0] Op3
68051 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
68052 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
68053 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1820:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3) => (UQSHRNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
68054 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNT_ZZI_B),
68055 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68056 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
68057 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
68058 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
68059 GIR_RootConstrainSelectedInstOperands,
68060 // GIR_Coverage, 11448,
68061 GIR_EraseRootFromParent_Done,
68062 // Label 3896: @184448
68063 GIM_Try, /*On fail goto*//*Label 3897*/ GIMT_Encode4(184495), // Rule ID 11449 //
68064 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
68065 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshrnt),
68066 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
68067 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
68068 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
68069 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68070 // MIs[0] Op3
68071 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
68072 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
68073 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1820:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3) => (UQSHRNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
68074 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNT_ZZI_H),
68075 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68076 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
68077 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
68078 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
68079 GIR_RootConstrainSelectedInstOperands,
68080 // GIR_Coverage, 11449,
68081 GIR_EraseRootFromParent_Done,
68082 // Label 3897: @184495
68083 GIM_Try, /*On fail goto*//*Label 3898*/ GIMT_Encode4(184542), // Rule ID 11450 //
68084 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
68085 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshrnt),
68086 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
68087 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
68088 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
68089 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68090 // MIs[0] Op3
68091 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
68092 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
68093 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1820:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3) => (UQSHRNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
68094 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNT_ZZI_S),
68095 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68096 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
68097 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
68098 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
68099 GIR_RootConstrainSelectedInstOperands,
68100 // GIR_Coverage, 11450,
68101 GIR_EraseRootFromParent_Done,
68102 // Label 3898: @184542
68103 GIM_Try, /*On fail goto*//*Label 3899*/ GIMT_Encode4(184589), // Rule ID 11451 //
68104 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
68105 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshrnt),
68106 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
68107 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
68108 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
68109 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68110 // MIs[0] Op3
68111 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
68112 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR8),
68113 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1817:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3) => (UQRSHRNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR8>>:$Op3)
68114 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNT_ZZI_B),
68115 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68116 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
68117 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
68118 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
68119 GIR_RootConstrainSelectedInstOperands,
68120 // GIR_Coverage, 11451,
68121 GIR_EraseRootFromParent_Done,
68122 // Label 3899: @184589
68123 GIM_Try, /*On fail goto*//*Label 3900*/ GIMT_Encode4(184636), // Rule ID 11452 //
68124 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
68125 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshrnt),
68126 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
68127 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
68128 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
68129 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68130 // MIs[0] Op3
68131 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
68132 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR16),
68133 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1817:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3) => (UQRSHRNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR16>>:$Op3)
68134 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNT_ZZI_H),
68135 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68136 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
68137 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
68138 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
68139 GIR_RootConstrainSelectedInstOperands,
68140 // GIR_Coverage, 11452,
68141 GIR_EraseRootFromParent_Done,
68142 // Label 3900: @184636
68143 GIM_Try, /*On fail goto*//*Label 3901*/ GIMT_Encode4(184683), // Rule ID 11453 //
68144 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
68145 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshrnt),
68146 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
68147 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
68148 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
68149 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68150 // MIs[0] Op3
68151 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
68152 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tvecshiftR32),
68153 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1817:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3) => (UQRSHRNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_tvecshiftR32>>:$Op3)
68154 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNT_ZZI_S),
68155 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68156 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
68157 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
68158 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
68159 GIR_RootConstrainSelectedInstOperands,
68160 // GIR_Coverage, 11453,
68161 GIR_EraseRootFromParent_Done,
68162 // Label 3901: @184683
68163 GIM_Try, /*On fail goto*//*Label 3902*/ GIMT_Encode4(184750), // Rule ID 2507 //
68164 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
68165 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urecpe),
68166 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
68167 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
68168 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
68169 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
68170 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68171 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68172 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68173 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68174 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1827:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (URECPE_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
68175 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68176 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68177 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68178 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68179 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URECPE_ZPmZ_S_UNDEF),
68180 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68181 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68182 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68183 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68184 GIR_RootConstrainSelectedInstOperands,
68185 // GIR_Coverage, 2507,
68186 GIR_EraseRootFromParent_Done,
68187 // Label 3902: @184750
68188 GIM_Try, /*On fail goto*//*Label 3903*/ GIMT_Encode4(184817), // Rule ID 7362 //
68189 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
68190 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
68191 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
68192 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
68193 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
68194 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
68195 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68196 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68197 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68198 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68199 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1126:{ *:[iPTR] }, (undef:{ *:[nxv16i8] }), nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (CLS_ZPmZ_B_UNDEF:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
68200 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68201 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68202 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68203 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68204 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_B_UNDEF),
68205 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68206 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68207 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68208 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68209 GIR_RootConstrainSelectedInstOperands,
68210 // GIR_Coverage, 7362,
68211 GIR_EraseRootFromParent_Done,
68212 // Label 3903: @184817
68213 GIM_Try, /*On fail goto*//*Label 3904*/ GIMT_Encode4(184884), // Rule ID 7364 //
68214 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
68215 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
68216 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
68217 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
68218 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
68219 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
68220 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68221 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68222 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68223 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68224 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1126:{ *:[iPTR] }, (undef:{ *:[nxv8i16] }), nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (CLS_ZPmZ_H_UNDEF:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
68225 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68226 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68227 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68228 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68229 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_H_UNDEF),
68230 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68231 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68232 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68233 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68234 GIR_RootConstrainSelectedInstOperands,
68235 // GIR_Coverage, 7364,
68236 GIR_EraseRootFromParent_Done,
68237 // Label 3904: @184884
68238 GIM_Try, /*On fail goto*//*Label 3905*/ GIMT_Encode4(184951), // Rule ID 7366 //
68239 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
68240 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
68241 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
68242 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
68243 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
68244 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
68245 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68246 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68247 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68248 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68249 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1126:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (CLS_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
68250 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68251 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68252 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68253 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68254 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_S_UNDEF),
68255 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68256 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68257 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68258 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68259 GIR_RootConstrainSelectedInstOperands,
68260 // GIR_Coverage, 7366,
68261 GIR_EraseRootFromParent_Done,
68262 // Label 3905: @184951
68263 GIM_Try, /*On fail goto*//*Label 3906*/ GIMT_Encode4(185018), // Rule ID 7368 //
68264 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
68265 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
68266 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
68267 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
68268 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
68269 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
68270 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68271 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68272 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68273 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68274 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1126:{ *:[iPTR] }, (undef:{ *:[nxv2i64] }), nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (CLS_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
68275 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68276 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68277 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68278 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68279 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_D_UNDEF),
68280 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68281 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68282 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68283 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68284 GIR_RootConstrainSelectedInstOperands,
68285 // GIR_Coverage, 7368,
68286 GIR_EraseRootFromParent_Done,
68287 // Label 3906: @185018
68288 GIM_Try, /*On fail goto*//*Label 3907*/ GIMT_Encode4(185085), // Rule ID 7398 //
68289 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
68290 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
68291 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
68292 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
68293 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
68294 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
68295 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68296 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68297 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68298 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68299 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1146:{ *:[iPTR] }, (undef:{ *:[nxv16i8] }), nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (CNOT_ZPmZ_B_UNDEF:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
68300 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68301 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68302 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68303 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68304 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_B_UNDEF),
68305 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68306 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68307 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68308 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68309 GIR_RootConstrainSelectedInstOperands,
68310 // GIR_Coverage, 7398,
68311 GIR_EraseRootFromParent_Done,
68312 // Label 3907: @185085
68313 GIM_Try, /*On fail goto*//*Label 3908*/ GIMT_Encode4(185152), // Rule ID 7400 //
68314 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
68315 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
68316 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
68317 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
68318 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
68319 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
68320 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68321 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68322 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68323 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68324 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1146:{ *:[iPTR] }, (undef:{ *:[nxv8i16] }), nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (CNOT_ZPmZ_H_UNDEF:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
68325 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68326 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68327 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68328 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68329 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_H_UNDEF),
68330 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68331 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68332 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68333 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68334 GIR_RootConstrainSelectedInstOperands,
68335 // GIR_Coverage, 7400,
68336 GIR_EraseRootFromParent_Done,
68337 // Label 3908: @185152
68338 GIM_Try, /*On fail goto*//*Label 3909*/ GIMT_Encode4(185219), // Rule ID 7402 //
68339 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
68340 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
68341 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
68342 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
68343 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
68344 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
68345 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68346 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68347 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68348 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68349 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1146:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (CNOT_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
68350 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68351 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68352 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68353 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68354 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_S_UNDEF),
68355 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68356 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68357 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68358 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68359 GIR_RootConstrainSelectedInstOperands,
68360 // GIR_Coverage, 7402,
68361 GIR_EraseRootFromParent_Done,
68362 // Label 3909: @185219
68363 GIM_Try, /*On fail goto*//*Label 3910*/ GIMT_Encode4(185286), // Rule ID 7404 //
68364 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
68365 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
68366 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
68367 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
68368 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
68369 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
68370 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68371 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68372 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68373 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68374 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1146:{ *:[iPTR] }, (undef:{ *:[nxv2i64] }), nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (CNOT_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
68375 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68376 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68377 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68378 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68379 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_D_UNDEF),
68380 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68381 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68382 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68383 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68384 GIR_RootConstrainSelectedInstOperands,
68385 // GIR_Coverage, 7404,
68386 GIR_EraseRootFromParent_Done,
68387 // Label 3910: @185286
68388 GIM_Try, /*On fail goto*//*Label 3911*/ GIMT_Encode4(185353), // Rule ID 7410 //
68389 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
68390 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
68391 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
68392 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
68393 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
68394 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
68395 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68396 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68397 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68398 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68399 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1397:{ *:[iPTR] }, (undef:{ *:[nxv16i8] }), nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (NOT_ZPmZ_B_UNDEF:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
68400 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68401 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68402 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68403 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68404 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_B_UNDEF),
68405 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68406 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68407 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68408 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68409 GIR_RootConstrainSelectedInstOperands,
68410 // GIR_Coverage, 7410,
68411 GIR_EraseRootFromParent_Done,
68412 // Label 3911: @185353
68413 GIM_Try, /*On fail goto*//*Label 3912*/ GIMT_Encode4(185420), // Rule ID 7412 //
68414 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
68415 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
68416 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
68417 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
68418 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
68419 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
68420 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68421 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68422 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68423 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68424 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1397:{ *:[iPTR] }, (undef:{ *:[nxv8i16] }), nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (NOT_ZPmZ_H_UNDEF:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
68425 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68426 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68427 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68428 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68429 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_H_UNDEF),
68430 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68431 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68432 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68433 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68434 GIR_RootConstrainSelectedInstOperands,
68435 // GIR_Coverage, 7412,
68436 GIR_EraseRootFromParent_Done,
68437 // Label 3912: @185420
68438 GIM_Try, /*On fail goto*//*Label 3913*/ GIMT_Encode4(185487), // Rule ID 7414 //
68439 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
68440 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
68441 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
68442 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
68443 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
68444 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
68445 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68446 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68447 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68448 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68449 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1397:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (NOT_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
68450 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68451 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68452 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68453 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68454 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_S_UNDEF),
68455 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68456 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68457 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68458 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68459 GIR_RootConstrainSelectedInstOperands,
68460 // GIR_Coverage, 7414,
68461 GIR_EraseRootFromParent_Done,
68462 // Label 3913: @185487
68463 GIM_Try, /*On fail goto*//*Label 3914*/ GIMT_Encode4(185554), // Rule ID 7416 //
68464 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
68465 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
68466 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
68467 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
68468 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
68469 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
68470 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68471 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68472 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68473 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68474 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1397:{ *:[iPTR] }, (undef:{ *:[nxv2i64] }), nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (NOT_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
68475 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68476 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68477 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68478 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68479 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_D_UNDEF),
68480 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68481 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68482 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68483 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68484 GIR_RootConstrainSelectedInstOperands,
68485 // GIR_Coverage, 7416,
68486 GIR_EraseRootFromParent_Done,
68487 // Label 3914: @185554
68488 GIM_Try, /*On fail goto*//*Label 3915*/ GIMT_Encode4(185621), // Rule ID 11146 //
68489 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
68490 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ursqrte),
68491 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
68492 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
68493 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
68494 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
68495 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68496 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68497 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68498 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68499 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1835:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (URSQRTE_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
68500 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68501 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68502 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68503 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68504 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSQRTE_ZPmZ_S_UNDEF),
68505 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68506 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68507 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68508 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68509 GIR_RootConstrainSelectedInstOperands,
68510 // GIR_Coverage, 11146,
68511 GIR_EraseRootFromParent_Done,
68512 // Label 3915: @185621
68513 GIM_Try, /*On fail goto*//*Label 3916*/ GIMT_Encode4(185688), // Rule ID 11148 //
68514 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
68515 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
68516 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
68517 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
68518 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
68519 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
68520 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68521 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68522 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68523 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68524 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1540:{ *:[iPTR] }, (undef:{ *:[nxv16i8] }), nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SQABS_ZPmZ_B_UNDEF:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
68525 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68526 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68527 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68528 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68529 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_B_UNDEF),
68530 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68531 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68532 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68533 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68534 GIR_RootConstrainSelectedInstOperands,
68535 // GIR_Coverage, 11148,
68536 GIR_EraseRootFromParent_Done,
68537 // Label 3916: @185688
68538 GIM_Try, /*On fail goto*//*Label 3917*/ GIMT_Encode4(185755), // Rule ID 11150 //
68539 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
68540 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
68541 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
68542 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
68543 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
68544 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
68545 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68546 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68547 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68548 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68549 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1540:{ *:[iPTR] }, (undef:{ *:[nxv8i16] }), nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SQABS_ZPmZ_H_UNDEF:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
68550 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68551 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68552 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68553 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68554 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_H_UNDEF),
68555 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68556 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68557 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68558 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68559 GIR_RootConstrainSelectedInstOperands,
68560 // GIR_Coverage, 11150,
68561 GIR_EraseRootFromParent_Done,
68562 // Label 3917: @185755
68563 GIM_Try, /*On fail goto*//*Label 3918*/ GIMT_Encode4(185822), // Rule ID 11152 //
68564 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
68565 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
68566 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
68567 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
68568 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
68569 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
68570 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68571 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68572 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68573 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68574 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1540:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SQABS_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
68575 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68576 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68577 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68578 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68579 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_S_UNDEF),
68580 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68581 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68582 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68583 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68584 GIR_RootConstrainSelectedInstOperands,
68585 // GIR_Coverage, 11152,
68586 GIR_EraseRootFromParent_Done,
68587 // Label 3918: @185822
68588 GIM_Try, /*On fail goto*//*Label 3919*/ GIMT_Encode4(185889), // Rule ID 11154 //
68589 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
68590 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
68591 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
68592 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
68593 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
68594 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
68595 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68596 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68597 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68598 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68599 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1540:{ *:[iPTR] }, (undef:{ *:[nxv2i64] }), nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (SQABS_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
68600 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68601 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68602 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68603 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68604 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_D_UNDEF),
68605 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68606 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68607 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68608 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68609 GIR_RootConstrainSelectedInstOperands,
68610 // GIR_Coverage, 11154,
68611 GIR_EraseRootFromParent_Done,
68612 // Label 3919: @185889
68613 GIM_Try, /*On fail goto*//*Label 3920*/ GIMT_Encode4(185956), // Rule ID 11160 //
68614 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
68615 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
68616 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
68617 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
68618 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
68619 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
68620 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68621 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68622 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68623 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68624 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1600:{ *:[iPTR] }, (undef:{ *:[nxv16i8] }), nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SQNEG_ZPmZ_B_UNDEF:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
68625 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68626 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68627 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68628 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68629 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_B_UNDEF),
68630 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68631 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68632 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68633 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68634 GIR_RootConstrainSelectedInstOperands,
68635 // GIR_Coverage, 11160,
68636 GIR_EraseRootFromParent_Done,
68637 // Label 3920: @185956
68638 GIM_Try, /*On fail goto*//*Label 3921*/ GIMT_Encode4(186023), // Rule ID 11162 //
68639 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
68640 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
68641 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
68642 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
68643 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
68644 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
68645 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68646 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68647 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68648 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68649 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1600:{ *:[iPTR] }, (undef:{ *:[nxv8i16] }), nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SQNEG_ZPmZ_H_UNDEF:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
68650 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68651 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68652 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68653 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68654 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_H_UNDEF),
68655 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68656 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68657 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68658 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68659 GIR_RootConstrainSelectedInstOperands,
68660 // GIR_Coverage, 11162,
68661 GIR_EraseRootFromParent_Done,
68662 // Label 3921: @186023
68663 GIM_Try, /*On fail goto*//*Label 3922*/ GIMT_Encode4(186090), // Rule ID 11164 //
68664 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
68665 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
68666 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
68667 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
68668 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
68669 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
68670 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68671 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68672 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68673 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68674 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1600:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SQNEG_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
68675 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68676 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68677 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68678 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68679 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_S_UNDEF),
68680 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68681 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68682 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68683 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68684 GIR_RootConstrainSelectedInstOperands,
68685 // GIR_Coverage, 11164,
68686 GIR_EraseRootFromParent_Done,
68687 // Label 3922: @186090
68688 GIM_Try, /*On fail goto*//*Label 3923*/ GIMT_Encode4(186157), // Rule ID 11166 //
68689 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
68690 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
68691 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
68692 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
68693 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
68694 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
68695 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
68696 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
68697 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
68698 GIM_CheckIsSafeToFold, /*NumInsns*/1,
68699 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1600:{ *:[iPTR] }, (undef:{ *:[nxv2i64] }), nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (SQNEG_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
68700 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
68701 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
68702 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
68703 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
68704 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_D_UNDEF),
68705 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
68706 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
68707 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
68708 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
68709 GIR_RootConstrainSelectedInstOperands,
68710 // GIR_Coverage, 11166,
68711 GIR_EraseRootFromParent_Done,
68712 // Label 3923: @186157
68713 GIM_Try, /*On fail goto*//*Label 3924*/ GIMT_Encode4(186211), // Rule ID 30 //
68714 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON),
68715 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_bfdot),
68716 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
68717 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
68718 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
68719 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
68720 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
68721 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
68722 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
68723 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
68724 // (intrinsic_wo_chain:{ *:[v2f32] } 556:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) => (BFDOTv4bf16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm)
68725 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFDOTv4bf16),
68726 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
68727 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
68728 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
68729 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
68730 GIR_RootConstrainSelectedInstOperands,
68731 // GIR_Coverage, 30,
68732 GIR_EraseRootFromParent_Done,
68733 // Label 3924: @186211
68734 GIM_Try, /*On fail goto*//*Label 3925*/ GIMT_Encode4(186265), // Rule ID 31 //
68735 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON),
68736 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_bfdot),
68737 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
68738 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
68739 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
68740 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
68741 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68742 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68743 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68744 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68745 // (intrinsic_wo_chain:{ *:[v4f32] } 556:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFDOTv8bf16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm)
68746 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFDOTv8bf16),
68747 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
68748 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
68749 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
68750 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
68751 GIR_RootConstrainSelectedInstOperands,
68752 // GIR_Coverage, 31,
68753 GIR_EraseRootFromParent_Done,
68754 // Label 3925: @186265
68755 GIM_Try, /*On fail goto*//*Label 3926*/ GIMT_Encode4(186319), // Rule ID 34 //
68756 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON),
68757 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_bfmmla),
68758 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
68759 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
68760 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
68761 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
68762 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68763 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68764 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68765 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68766 // (intrinsic_wo_chain:{ *:[v4f32] } 559:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFMMLA:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm)
68767 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMMLA),
68768 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
68769 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
68770 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
68771 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
68772 GIR_RootConstrainSelectedInstOperands,
68773 // GIR_Coverage, 34,
68774 GIR_EraseRootFromParent_Done,
68775 // Label 3926: @186319
68776 GIM_Try, /*On fail goto*//*Label 3927*/ GIMT_Encode4(186373), // Rule ID 35 //
68777 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON),
68778 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_bfmlalb),
68779 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
68780 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
68781 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
68782 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
68783 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68784 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68785 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68786 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68787 // (intrinsic_wo_chain:{ *:[v4f32] } 557:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFMLALB:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm)
68788 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMLALB),
68789 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
68790 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
68791 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
68792 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
68793 GIR_RootConstrainSelectedInstOperands,
68794 // GIR_Coverage, 35,
68795 GIR_EraseRootFromParent_Done,
68796 // Label 3927: @186373
68797 GIM_Try, /*On fail goto*//*Label 3928*/ GIMT_Encode4(186427), // Rule ID 36 //
68798 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON),
68799 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_bfmlalt),
68800 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
68801 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
68802 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
68803 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
68804 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68805 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68806 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68807 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68808 // (intrinsic_wo_chain:{ *:[v4f32] } 558:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFMLALT:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm)
68809 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMLALT),
68810 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
68811 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
68812 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
68813 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
68814 GIR_RootConstrainSelectedInstOperands,
68815 // GIR_Coverage, 36,
68816 GIR_EraseRootFromParent_Done,
68817 // Label 3928: @186427
68818 GIM_Try, /*On fail goto*//*Label 3929*/ GIMT_Encode4(186481), // Rule ID 42 //
68819 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
68820 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smmla),
68821 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
68822 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
68823 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
68824 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
68825 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68826 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68827 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68828 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68829 // (intrinsic_wo_chain:{ *:[v4i32] } 638:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMMLA:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
68830 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMMLA),
68831 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
68832 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
68833 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
68834 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
68835 GIR_RootConstrainSelectedInstOperands,
68836 // GIR_Coverage, 42,
68837 GIR_EraseRootFromParent_Done,
68838 // Label 3929: @186481
68839 GIM_Try, /*On fail goto*//*Label 3930*/ GIMT_Encode4(186535), // Rule ID 43 //
68840 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
68841 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ummla),
68842 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
68843 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
68844 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
68845 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
68846 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68847 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68848 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68849 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68850 // (intrinsic_wo_chain:{ *:[v4i32] } 699:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMMLA:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
68851 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMMLA),
68852 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
68853 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
68854 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
68855 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
68856 GIR_RootConstrainSelectedInstOperands,
68857 // GIR_Coverage, 43,
68858 GIR_EraseRootFromParent_Done,
68859 // Label 3930: @186535
68860 GIM_Try, /*On fail goto*//*Label 3931*/ GIMT_Encode4(186589), // Rule ID 44 //
68861 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
68862 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usmmla),
68863 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
68864 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
68865 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
68866 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
68867 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68868 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68869 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68870 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68871 // (intrinsic_wo_chain:{ *:[v4i32] } 715:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (USMMLA:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
68872 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMMLA),
68873 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
68874 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
68875 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
68876 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
68877 GIR_RootConstrainSelectedInstOperands,
68878 // GIR_Coverage, 44,
68879 GIR_EraseRootFromParent_Done,
68880 // Label 3931: @186589
68881 GIM_Try, /*On fail goto*//*Label 3932*/ GIMT_Encode4(186643), // Rule ID 45 //
68882 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
68883 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usdot),
68884 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
68885 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
68886 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
68887 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
68888 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
68889 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
68890 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
68891 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
68892 // (intrinsic_wo_chain:{ *:[v2i32] } 712:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (USDOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
68893 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USDOTv8i8),
68894 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
68895 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
68896 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
68897 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
68898 GIR_RootConstrainSelectedInstOperands,
68899 // GIR_Coverage, 45,
68900 GIR_EraseRootFromParent_Done,
68901 // Label 3932: @186643
68902 GIM_Try, /*On fail goto*//*Label 3933*/ GIMT_Encode4(186697), // Rule ID 46 //
68903 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
68904 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usdot),
68905 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
68906 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
68907 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
68908 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
68909 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68910 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68911 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68912 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68913 // (intrinsic_wo_chain:{ *:[v4i32] } 712:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (USDOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
68914 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USDOTv16i8),
68915 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
68916 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
68917 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
68918 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
68919 GIR_RootConstrainSelectedInstOperands,
68920 // GIR_Coverage, 46,
68921 GIR_EraseRootFromParent_Done,
68922 // Label 3933: @186697
68923 GIM_Try, /*On fail goto*//*Label 3934*/ GIMT_Encode4(186751), // Rule ID 51 //
68924 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
68925 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal),
68926 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
68927 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
68928 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
68929 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
68930 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
68931 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
68932 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
68933 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
68934 // (intrinsic_wo_chain:{ *:[v2f32] } 589:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMLALv4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
68935 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALv4f16),
68936 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
68937 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
68938 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
68939 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
68940 GIR_RootConstrainSelectedInstOperands,
68941 // GIR_Coverage, 51,
68942 GIR_EraseRootFromParent_Done,
68943 // Label 3934: @186751
68944 GIM_Try, /*On fail goto*//*Label 3935*/ GIMT_Encode4(186805), // Rule ID 52 //
68945 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
68946 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal),
68947 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
68948 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
68949 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
68950 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
68951 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68952 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68953 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68954 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68955 // (intrinsic_wo_chain:{ *:[v4f32] } 589:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMLALv8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
68956 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALv8f16),
68957 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
68958 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
68959 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
68960 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
68961 GIR_RootConstrainSelectedInstOperands,
68962 // GIR_Coverage, 52,
68963 GIR_EraseRootFromParent_Done,
68964 // Label 3935: @186805
68965 GIM_Try, /*On fail goto*//*Label 3936*/ GIMT_Encode4(186859), // Rule ID 53 //
68966 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
68967 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl),
68968 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
68969 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
68970 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
68971 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
68972 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
68973 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
68974 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
68975 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
68976 // (intrinsic_wo_chain:{ *:[v2f32] } 591:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMLSLv4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
68977 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLv4f16),
68978 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
68979 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
68980 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
68981 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
68982 GIR_RootConstrainSelectedInstOperands,
68983 // GIR_Coverage, 53,
68984 GIR_EraseRootFromParent_Done,
68985 // Label 3936: @186859
68986 GIM_Try, /*On fail goto*//*Label 3937*/ GIMT_Encode4(186913), // Rule ID 54 //
68987 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
68988 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl),
68989 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
68990 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
68991 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
68992 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
68993 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68994 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68995 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68996 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
68997 // (intrinsic_wo_chain:{ *:[v4f32] } 591:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMLSLv8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
68998 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLv8f16),
68999 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69000 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69001 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69002 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69003 GIR_RootConstrainSelectedInstOperands,
69004 // GIR_Coverage, 54,
69005 GIR_EraseRootFromParent_Done,
69006 // Label 3937: @186913
69007 GIM_Try, /*On fail goto*//*Label 3938*/ GIMT_Encode4(186967), // Rule ID 55 //
69008 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
69009 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal2),
69010 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
69011 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
69012 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
69013 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
69014 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69015 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69016 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69017 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69018 // (intrinsic_wo_chain:{ *:[v2f32] } 590:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMLAL2v4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
69019 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAL2v4f16),
69020 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69021 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69022 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69023 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69024 GIR_RootConstrainSelectedInstOperands,
69025 // GIR_Coverage, 55,
69026 GIR_EraseRootFromParent_Done,
69027 // Label 3938: @186967
69028 GIM_Try, /*On fail goto*//*Label 3939*/ GIMT_Encode4(187021), // Rule ID 56 //
69029 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
69030 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal2),
69031 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
69032 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
69033 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
69034 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
69035 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69036 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69037 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69038 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69039 // (intrinsic_wo_chain:{ *:[v4f32] } 590:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMLAL2v8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
69040 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAL2v8f16),
69041 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69042 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69043 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69044 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69045 GIR_RootConstrainSelectedInstOperands,
69046 // GIR_Coverage, 56,
69047 GIR_EraseRootFromParent_Done,
69048 // Label 3939: @187021
69049 GIM_Try, /*On fail goto*//*Label 3940*/ GIMT_Encode4(187075), // Rule ID 57 //
69050 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
69051 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl2),
69052 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
69053 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
69054 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
69055 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
69056 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69057 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69058 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69059 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69060 // (intrinsic_wo_chain:{ *:[v2f32] } 592:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMLSL2v4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
69061 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSL2v4f16),
69062 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69063 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69064 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69065 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69066 GIR_RootConstrainSelectedInstOperands,
69067 // GIR_Coverage, 57,
69068 GIR_EraseRootFromParent_Done,
69069 // Label 3940: @187075
69070 GIM_Try, /*On fail goto*//*Label 3941*/ GIMT_Encode4(187129), // Rule ID 58 //
69071 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
69072 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl2),
69073 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
69074 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
69075 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
69076 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
69077 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69078 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69079 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69080 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69081 // (intrinsic_wo_chain:{ *:[v4f32] } 592:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMLSL2v8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
69082 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSL2v8f16),
69083 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69084 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69085 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69086 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69087 GIR_RootConstrainSelectedInstOperands,
69088 // GIR_Coverage, 58,
69089 GIR_EraseRootFromParent_Done,
69090 // Label 3941: @187129
69091 GIM_Try, /*On fail goto*//*Label 3942*/ GIMT_Encode4(187183), // Rule ID 1574 //
69092 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
69093 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
69094 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
69095 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
69096 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
69097 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
69098 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69099 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69100 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69101 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69102 // (intrinsic_wo_chain:{ *:[v4i16] } 648:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQRDMLAHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
69103 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv4i16),
69104 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69105 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69106 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69107 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69108 GIR_RootConstrainSelectedInstOperands,
69109 // GIR_Coverage, 1574,
69110 GIR_EraseRootFromParent_Done,
69111 // Label 3942: @187183
69112 GIM_Try, /*On fail goto*//*Label 3943*/ GIMT_Encode4(187237), // Rule ID 1575 //
69113 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
69114 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
69115 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
69116 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
69117 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
69118 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
69119 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69120 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69121 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69122 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69123 // (intrinsic_wo_chain:{ *:[v8i16] } 648:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQRDMLAHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
69124 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv8i16),
69125 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69126 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69127 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69128 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69129 GIR_RootConstrainSelectedInstOperands,
69130 // GIR_Coverage, 1575,
69131 GIR_EraseRootFromParent_Done,
69132 // Label 3943: @187237
69133 GIM_Try, /*On fail goto*//*Label 3944*/ GIMT_Encode4(187291), // Rule ID 1576 //
69134 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
69135 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
69136 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
69137 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
69138 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
69139 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
69140 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69141 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69142 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69143 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69144 // (intrinsic_wo_chain:{ *:[v2i32] } 648:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQRDMLAHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
69145 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv2i32),
69146 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69147 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69148 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69149 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69150 GIR_RootConstrainSelectedInstOperands,
69151 // GIR_Coverage, 1576,
69152 GIR_EraseRootFromParent_Done,
69153 // Label 3944: @187291
69154 GIM_Try, /*On fail goto*//*Label 3945*/ GIMT_Encode4(187345), // Rule ID 1577 //
69155 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
69156 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
69157 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
69158 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
69159 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
69160 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
69161 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69162 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69163 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69164 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69165 // (intrinsic_wo_chain:{ *:[v4i32] } 648:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQRDMLAHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
69166 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv4i32),
69167 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69168 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69169 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69170 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69171 GIR_RootConstrainSelectedInstOperands,
69172 // GIR_Coverage, 1577,
69173 GIR_EraseRootFromParent_Done,
69174 // Label 3945: @187345
69175 GIM_Try, /*On fail goto*//*Label 3946*/ GIMT_Encode4(187399), // Rule ID 1578 //
69176 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
69177 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
69178 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
69179 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
69180 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
69181 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
69182 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69183 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69184 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69185 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69186 // (intrinsic_wo_chain:{ *:[v4i16] } 649:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SQRDMLSHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
69187 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv4i16),
69188 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69189 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69190 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69191 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69192 GIR_RootConstrainSelectedInstOperands,
69193 // GIR_Coverage, 1578,
69194 GIR_EraseRootFromParent_Done,
69195 // Label 3946: @187399
69196 GIM_Try, /*On fail goto*//*Label 3947*/ GIMT_Encode4(187453), // Rule ID 1579 //
69197 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
69198 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
69199 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
69200 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
69201 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
69202 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
69203 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69204 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69205 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69206 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69207 // (intrinsic_wo_chain:{ *:[v8i16] } 649:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SQRDMLSHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
69208 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv8i16),
69209 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69210 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69211 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69212 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69213 GIR_RootConstrainSelectedInstOperands,
69214 // GIR_Coverage, 1579,
69215 GIR_EraseRootFromParent_Done,
69216 // Label 3947: @187453
69217 GIM_Try, /*On fail goto*//*Label 3948*/ GIMT_Encode4(187507), // Rule ID 1580 //
69218 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
69219 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
69220 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
69221 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
69222 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
69223 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
69224 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69225 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69226 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69227 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69228 // (intrinsic_wo_chain:{ *:[v2i32] } 649:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SQRDMLSHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
69229 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv2i32),
69230 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69231 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69232 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69233 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69234 GIR_RootConstrainSelectedInstOperands,
69235 // GIR_Coverage, 1580,
69236 GIR_EraseRootFromParent_Done,
69237 // Label 3948: @187507
69238 GIM_Try, /*On fail goto*//*Label 3949*/ GIMT_Encode4(187561), // Rule ID 1581 //
69239 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
69240 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
69241 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
69242 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
69243 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
69244 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
69245 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69246 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69247 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69248 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69249 // (intrinsic_wo_chain:{ *:[v4i32] } 649:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SQRDMLSHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
69250 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv4i32),
69251 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69252 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69253 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69254 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69255 GIR_RootConstrainSelectedInstOperands,
69256 // GIR_Coverage, 1581,
69257 GIR_EraseRootFromParent_Done,
69258 // Label 3949: @187561
69259 GIM_Try, /*On fail goto*//*Label 3950*/ GIMT_Encode4(187615), // Rule ID 2292 //
69260 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
69261 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha1c),
69262 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
69263 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
69264 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
69265 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
69266 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69267 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69268 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
69269 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69270 // (intrinsic_wo_chain:{ *:[v4i32] } 502:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1Crrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
69271 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA1Crrr),
69272 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69273 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69274 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69275 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69276 GIR_RootConstrainSelectedInstOperands,
69277 // GIR_Coverage, 2292,
69278 GIR_EraseRootFromParent_Done,
69279 // Label 3950: @187615
69280 GIM_Try, /*On fail goto*//*Label 3951*/ GIMT_Encode4(187669), // Rule ID 2293 //
69281 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
69282 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha1p),
69283 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
69284 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
69285 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
69286 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
69287 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69288 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69289 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
69290 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69291 // (intrinsic_wo_chain:{ *:[v4i32] } 505:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1Prrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
69292 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA1Prrr),
69293 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69294 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69295 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69296 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69297 GIR_RootConstrainSelectedInstOperands,
69298 // GIR_Coverage, 2293,
69299 GIR_EraseRootFromParent_Done,
69300 // Label 3951: @187669
69301 GIM_Try, /*On fail goto*//*Label 3952*/ GIMT_Encode4(187723), // Rule ID 2294 //
69302 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
69303 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha1m),
69304 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
69305 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
69306 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
69307 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
69308 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69309 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69310 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
69311 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69312 // (intrinsic_wo_chain:{ *:[v4i32] } 504:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1Mrrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
69313 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA1Mrrr),
69314 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69315 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69316 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69317 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69318 GIR_RootConstrainSelectedInstOperands,
69319 // GIR_Coverage, 2294,
69320 GIR_EraseRootFromParent_Done,
69321 // Label 3952: @187723
69322 GIM_Try, /*On fail goto*//*Label 3953*/ GIMT_Encode4(187777), // Rule ID 2295 //
69323 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
69324 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha1su0),
69325 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
69326 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
69327 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
69328 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
69329 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69330 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69331 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69332 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69333 // (intrinsic_wo_chain:{ *:[v4i32] } 506:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA1SU0rrr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
69334 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA1SU0rrr),
69335 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69336 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69337 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69338 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69339 GIR_RootConstrainSelectedInstOperands,
69340 // GIR_Coverage, 2295,
69341 GIR_EraseRootFromParent_Done,
69342 // Label 3953: @187777
69343 GIM_Try, /*On fail goto*//*Label 3954*/ GIMT_Encode4(187831), // Rule ID 2296 //
69344 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
69345 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha256h),
69346 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
69347 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
69348 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
69349 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
69350 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69351 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69352 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69353 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69354 // (intrinsic_wo_chain:{ *:[v4i32] } 508:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA256Hrrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
69355 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA256Hrrr),
69356 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69357 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69358 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69359 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69360 GIR_RootConstrainSelectedInstOperands,
69361 // GIR_Coverage, 2296,
69362 GIR_EraseRootFromParent_Done,
69363 // Label 3954: @187831
69364 GIM_Try, /*On fail goto*//*Label 3955*/ GIMT_Encode4(187885), // Rule ID 2297 //
69365 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
69366 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha256h2),
69367 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
69368 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
69369 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
69370 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
69371 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69372 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69373 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69374 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69375 // (intrinsic_wo_chain:{ *:[v4i32] } 509:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA256H2rrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
69376 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA256H2rrr),
69377 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69378 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69379 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69380 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69381 GIR_RootConstrainSelectedInstOperands,
69382 // GIR_Coverage, 2297,
69383 GIR_EraseRootFromParent_Done,
69384 // Label 3955: @187885
69385 GIM_Try, /*On fail goto*//*Label 3956*/ GIMT_Encode4(187939), // Rule ID 2298 //
69386 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
69387 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha256su1),
69388 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
69389 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
69390 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
69391 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
69392 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69393 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69394 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69395 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69396 // (intrinsic_wo_chain:{ *:[v4i32] } 511:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SHA256SU1rrr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
69397 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA256SU1rrr),
69398 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69399 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69400 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69401 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69402 GIR_RootConstrainSelectedInstOperands,
69403 // GIR_Coverage, 2298,
69404 GIR_EraseRootFromParent_Done,
69405 // Label 3956: @187939
69406 GIM_Try, /*On fail goto*//*Label 3957*/ GIMT_Encode4(187996), // Rule ID 3537 //
69407 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME),
69408 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_psel),
69409 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
69410 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
69411 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
69412 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
69413 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
69414 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
69415 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
69416 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::MatrixIndexGPR32_12_15RegClassID),
69417 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1432:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$Pn, PPR8:{ *:[nxv16i1] }:$Pm, MatrixIndexGPR32Op12_15:{ *:[i32] }:$idx) => (PSEL_PPPRI_B:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[i32] }:$idx, 0:{ *:[i32] })
69418 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PSEL_PPPRI_B),
69419 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
69420 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
69421 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
69422 GIR_RootToRootCopy, /*OpIdx*/4, // idx
69423 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
69424 GIR_RootConstrainSelectedInstOperands,
69425 // GIR_Coverage, 3537,
69426 GIR_EraseRootFromParent_Done,
69427 // Label 3957: @187996
69428 GIM_Try, /*On fail goto*//*Label 3958*/ GIMT_Encode4(188053), // Rule ID 3538 //
69429 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME),
69430 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_psel),
69431 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
69432 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
69433 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
69434 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
69435 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
69436 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
69437 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
69438 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::MatrixIndexGPR32_12_15RegClassID),
69439 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1432:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$Pn, PPR16:{ *:[nxv8i1] }:$Pm, MatrixIndexGPR32Op12_15:{ *:[i32] }:$idx) => (PSEL_PPPRI_H:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[i32] }:$idx, 0:{ *:[i32] })
69440 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PSEL_PPPRI_H),
69441 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
69442 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
69443 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
69444 GIR_RootToRootCopy, /*OpIdx*/4, // idx
69445 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
69446 GIR_RootConstrainSelectedInstOperands,
69447 // GIR_Coverage, 3538,
69448 GIR_EraseRootFromParent_Done,
69449 // Label 3958: @188053
69450 GIM_Try, /*On fail goto*//*Label 3959*/ GIMT_Encode4(188110), // Rule ID 3539 //
69451 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME),
69452 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_psel),
69453 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
69454 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
69455 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
69456 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
69457 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
69458 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
69459 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
69460 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::MatrixIndexGPR32_12_15RegClassID),
69461 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1432:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$Pn, PPR32:{ *:[nxv4i1] }:$Pm, MatrixIndexGPR32Op12_15:{ *:[i32] }:$idx) => (PSEL_PPPRI_S:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv4i1] }:$Pm, ?:{ *:[i32] }:$idx, 0:{ *:[i32] })
69462 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PSEL_PPPRI_S),
69463 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
69464 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
69465 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
69466 GIR_RootToRootCopy, /*OpIdx*/4, // idx
69467 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
69468 GIR_RootConstrainSelectedInstOperands,
69469 // GIR_Coverage, 3539,
69470 GIR_EraseRootFromParent_Done,
69471 // Label 3959: @188110
69472 GIM_Try, /*On fail goto*//*Label 3960*/ GIMT_Encode4(188167), // Rule ID 3540 //
69473 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME),
69474 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_psel),
69475 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
69476 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
69477 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
69478 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
69479 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
69480 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
69481 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
69482 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::MatrixIndexGPR32_12_15RegClassID),
69483 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1432:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$Pn, PPR64:{ *:[nxv2i1] }:$Pm, MatrixIndexGPR32Op12_15:{ *:[i32] }:$idx) => (PSEL_PPPRI_D:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv2i1] }:$Pm, ?:{ *:[i32] }:$idx, 0:{ *:[i32] })
69484 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PSEL_PPPRI_D),
69485 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
69486 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
69487 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
69488 GIR_RootToRootCopy, /*OpIdx*/4, // idx
69489 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
69490 GIR_RootConstrainSelectedInstOperands,
69491 // GIR_Coverage, 3540,
69492 GIR_EraseRootFromParent_Done,
69493 // Label 3960: @188167
69494 GIM_Try, /*On fail goto*//*Label 3961*/ GIMT_Encode4(188221), // Rule ID 3685 //
69495 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
69496 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha512h),
69497 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
69498 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
69499 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
69500 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
69501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69502 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69503 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69504 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69505 // (intrinsic_wo_chain:{ *:[v2i64] } 512:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) => (SHA512H:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
69506 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA512H),
69507 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
69508 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69509 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69510 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69511 GIR_RootConstrainSelectedInstOperands,
69512 // GIR_Coverage, 3685,
69513 GIR_EraseRootFromParent_Done,
69514 // Label 3961: @188221
69515 GIM_Try, /*On fail goto*//*Label 3962*/ GIMT_Encode4(188275), // Rule ID 3686 //
69516 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
69517 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha512h2),
69518 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
69519 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
69520 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
69521 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
69522 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69523 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69524 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69525 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69526 // (intrinsic_wo_chain:{ *:[v2i64] } 513:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) => (SHA512H2:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
69527 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA512H2),
69528 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
69529 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69530 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69531 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69532 GIR_RootConstrainSelectedInstOperands,
69533 // GIR_Coverage, 3686,
69534 GIR_EraseRootFromParent_Done,
69535 // Label 3962: @188275
69536 GIM_Try, /*On fail goto*//*Label 3963*/ GIMT_Encode4(188329), // Rule ID 3687 //
69537 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
69538 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha512su1),
69539 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
69540 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
69541 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
69542 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
69543 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69544 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69545 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69546 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69547 // (intrinsic_wo_chain:{ *:[v2i64] } 515:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) => (SHA512SU1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
69548 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA512SU1),
69549 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
69550 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69551 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69552 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69553 GIR_RootConstrainSelectedInstOperands,
69554 // GIR_Coverage, 3687,
69555 GIR_EraseRootFromParent_Done,
69556 // Label 3963: @188329
69557 GIM_Try, /*On fail goto*//*Label 3964*/ GIMT_Encode4(188383), // Rule ID 3688 //
69558 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
69559 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3u),
69560 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
69561 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
69562 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
69563 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
69564 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69565 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69566 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69567 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69568 // (intrinsic_wo_chain:{ *:[v16i8] } 500:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm) => (EOR3:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)
69569 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
69570 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
69571 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69572 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69573 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69574 GIR_RootConstrainSelectedInstOperands,
69575 // GIR_Coverage, 3688,
69576 GIR_EraseRootFromParent_Done,
69577 // Label 3964: @188383
69578 GIM_Try, /*On fail goto*//*Label 3965*/ GIMT_Encode4(188437), // Rule ID 3689 //
69579 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
69580 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3u),
69581 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
69582 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
69583 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
69584 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
69585 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69586 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69587 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69588 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69589 // (intrinsic_wo_chain:{ *:[v8i16] } 500:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm) => (EOR3:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)
69590 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
69591 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
69592 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69593 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69594 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69595 GIR_RootConstrainSelectedInstOperands,
69596 // GIR_Coverage, 3689,
69597 GIR_EraseRootFromParent_Done,
69598 // Label 3965: @188437
69599 GIM_Try, /*On fail goto*//*Label 3966*/ GIMT_Encode4(188491), // Rule ID 3690 //
69600 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
69601 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3u),
69602 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
69603 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
69604 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
69605 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
69606 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69607 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69608 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69609 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69610 // (intrinsic_wo_chain:{ *:[v4i32] } 500:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) => (EOR3:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
69611 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
69612 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
69613 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69614 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69615 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69616 GIR_RootConstrainSelectedInstOperands,
69617 // GIR_Coverage, 3690,
69618 GIR_EraseRootFromParent_Done,
69619 // Label 3966: @188491
69620 GIM_Try, /*On fail goto*//*Label 3967*/ GIMT_Encode4(188545), // Rule ID 3691 //
69621 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
69622 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3u),
69623 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
69624 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
69625 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
69626 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
69627 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69628 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69629 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69630 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69631 // (intrinsic_wo_chain:{ *:[v2i64] } 500:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) => (EOR3:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
69632 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
69633 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
69634 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69635 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69636 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69637 GIR_RootConstrainSelectedInstOperands,
69638 // GIR_Coverage, 3691,
69639 GIR_EraseRootFromParent_Done,
69640 // Label 3967: @188545
69641 GIM_Try, /*On fail goto*//*Label 3968*/ GIMT_Encode4(188599), // Rule ID 3700 //
69642 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
69643 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxu),
69644 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
69645 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
69646 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
69647 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
69648 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69649 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69650 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69651 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69652 // (intrinsic_wo_chain:{ *:[v16i8] } 498:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm) => (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)
69653 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
69654 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
69655 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69656 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69657 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69658 GIR_RootConstrainSelectedInstOperands,
69659 // GIR_Coverage, 3700,
69660 GIR_EraseRootFromParent_Done,
69661 // Label 3968: @188599
69662 GIM_Try, /*On fail goto*//*Label 3969*/ GIMT_Encode4(188653), // Rule ID 3701 //
69663 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
69664 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxu),
69665 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
69666 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
69667 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
69668 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
69669 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69670 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69671 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69672 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69673 // (intrinsic_wo_chain:{ *:[v8i16] } 498:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm) => (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)
69674 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
69675 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
69676 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69677 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69678 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69679 GIR_RootConstrainSelectedInstOperands,
69680 // GIR_Coverage, 3701,
69681 GIR_EraseRootFromParent_Done,
69682 // Label 3969: @188653
69683 GIM_Try, /*On fail goto*//*Label 3970*/ GIMT_Encode4(188707), // Rule ID 3702 //
69684 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
69685 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxu),
69686 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
69687 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
69688 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
69689 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
69690 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69691 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69692 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69693 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69694 // (intrinsic_wo_chain:{ *:[v4i32] } 498:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) => (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
69695 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
69696 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
69697 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69698 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69699 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69700 GIR_RootConstrainSelectedInstOperands,
69701 // GIR_Coverage, 3702,
69702 GIR_EraseRootFromParent_Done,
69703 // Label 3970: @188707
69704 GIM_Try, /*On fail goto*//*Label 3971*/ GIMT_Encode4(188761), // Rule ID 3703 //
69705 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
69706 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxu),
69707 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
69708 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
69709 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
69710 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
69711 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69712 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69713 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69714 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69715 // (intrinsic_wo_chain:{ *:[v2i64] } 498:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) => (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
69716 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
69717 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
69718 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69719 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69720 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69721 GIR_RootConstrainSelectedInstOperands,
69722 // GIR_Coverage, 3703,
69723 GIR_EraseRootFromParent_Done,
69724 // Label 3971: @188761
69725 GIM_Try, /*On fail goto*//*Label 3972*/ GIMT_Encode4(188815), // Rule ID 3704 //
69726 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
69727 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3s),
69728 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
69729 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
69730 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
69731 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
69732 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69733 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69734 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69735 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69736 // (intrinsic_wo_chain:{ *:[v16i8] } 499:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm) => (EOR3:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)
69737 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
69738 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
69739 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69740 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69741 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69742 GIR_RootConstrainSelectedInstOperands,
69743 // GIR_Coverage, 3704,
69744 GIR_EraseRootFromParent_Done,
69745 // Label 3972: @188815
69746 GIM_Try, /*On fail goto*//*Label 3973*/ GIMT_Encode4(188869), // Rule ID 3705 //
69747 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
69748 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3s),
69749 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
69750 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
69751 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
69752 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
69753 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69754 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69755 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69756 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69757 // (intrinsic_wo_chain:{ *:[v8i16] } 499:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm) => (EOR3:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)
69758 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
69759 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
69760 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69761 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69762 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69763 GIR_RootConstrainSelectedInstOperands,
69764 // GIR_Coverage, 3705,
69765 GIR_EraseRootFromParent_Done,
69766 // Label 3973: @188869
69767 GIM_Try, /*On fail goto*//*Label 3974*/ GIMT_Encode4(188923), // Rule ID 3706 //
69768 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
69769 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3s),
69770 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
69771 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
69772 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
69773 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
69774 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69775 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69776 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69777 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69778 // (intrinsic_wo_chain:{ *:[v4i32] } 499:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) => (EOR3:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
69779 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
69780 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
69781 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69782 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69783 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69784 GIR_RootConstrainSelectedInstOperands,
69785 // GIR_Coverage, 3706,
69786 GIR_EraseRootFromParent_Done,
69787 // Label 3974: @188923
69788 GIM_Try, /*On fail goto*//*Label 3975*/ GIMT_Encode4(188977), // Rule ID 3707 //
69789 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
69790 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3s),
69791 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
69792 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
69793 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
69794 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
69795 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69796 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69797 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69798 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69799 // (intrinsic_wo_chain:{ *:[v2i64] } 499:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) => (EOR3:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
69800 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
69801 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
69802 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69803 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69804 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69805 GIR_RootConstrainSelectedInstOperands,
69806 // GIR_Coverage, 3707,
69807 GIR_EraseRootFromParent_Done,
69808 // Label 3975: @188977
69809 GIM_Try, /*On fail goto*//*Label 3976*/ GIMT_Encode4(189031), // Rule ID 3708 //
69810 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
69811 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxs),
69812 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
69813 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
69814 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
69815 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
69816 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69817 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69818 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69819 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69820 // (intrinsic_wo_chain:{ *:[v16i8] } 497:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm) => (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)
69821 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
69822 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
69823 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69824 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69825 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69826 GIR_RootConstrainSelectedInstOperands,
69827 // GIR_Coverage, 3708,
69828 GIR_EraseRootFromParent_Done,
69829 // Label 3976: @189031
69830 GIM_Try, /*On fail goto*//*Label 3977*/ GIMT_Encode4(189085), // Rule ID 3709 //
69831 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
69832 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxs),
69833 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
69834 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
69835 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
69836 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
69837 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69838 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69839 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69840 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69841 // (intrinsic_wo_chain:{ *:[v8i16] } 497:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm) => (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)
69842 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
69843 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
69844 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69845 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69846 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69847 GIR_RootConstrainSelectedInstOperands,
69848 // GIR_Coverage, 3709,
69849 GIR_EraseRootFromParent_Done,
69850 // Label 3977: @189085
69851 GIM_Try, /*On fail goto*//*Label 3978*/ GIMT_Encode4(189139), // Rule ID 3710 //
69852 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
69853 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxs),
69854 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
69855 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
69856 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
69857 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
69858 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69859 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69860 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69861 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69862 // (intrinsic_wo_chain:{ *:[v4i32] } 497:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) => (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
69863 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
69864 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
69865 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69866 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69867 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69868 GIR_RootConstrainSelectedInstOperands,
69869 // GIR_Coverage, 3710,
69870 GIR_EraseRootFromParent_Done,
69871 // Label 3978: @189139
69872 GIM_Try, /*On fail goto*//*Label 3979*/ GIMT_Encode4(189193), // Rule ID 3711 //
69873 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
69874 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxs),
69875 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
69876 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
69877 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
69878 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
69879 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69880 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69881 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69882 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69883 // (intrinsic_wo_chain:{ *:[v2i64] } 497:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm) => (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
69884 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
69885 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
69886 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69887 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69888 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69889 GIR_RootConstrainSelectedInstOperands,
69890 // GIR_Coverage, 3711,
69891 GIR_EraseRootFromParent_Done,
69892 // Label 3979: @189193
69893 GIM_Try, /*On fail goto*//*Label 3980*/ GIMT_Encode4(189247), // Rule ID 3715 //
69894 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
69895 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3ss1),
69896 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
69897 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
69898 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
69899 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
69900 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69901 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69902 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69903 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69904 // (intrinsic_wo_chain:{ *:[v4i32] } 518:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va) => (SM3SS1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
69905 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3SS1),
69906 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
69907 GIR_RootToRootCopy, /*OpIdx*/2, // Vn
69908 GIR_RootToRootCopy, /*OpIdx*/3, // Vm
69909 GIR_RootToRootCopy, /*OpIdx*/4, // Va
69910 GIR_RootConstrainSelectedInstOperands,
69911 // GIR_Coverage, 3715,
69912 GIR_EraseRootFromParent_Done,
69913 // Label 3980: @189247
69914 GIM_Try, /*On fail goto*//*Label 3981*/ GIMT_Encode4(189301), // Rule ID 3716 //
69915 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
69916 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3partw1),
69917 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
69918 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
69919 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
69920 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
69921 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69922 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69923 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69924 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69925 // (intrinsic_wo_chain:{ *:[v4i32] } 516:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) => (SM3PARTW1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
69926 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3PARTW1),
69927 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
69928 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69929 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69930 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69931 GIR_RootConstrainSelectedInstOperands,
69932 // GIR_Coverage, 3716,
69933 GIR_EraseRootFromParent_Done,
69934 // Label 3981: @189301
69935 GIM_Try, /*On fail goto*//*Label 3982*/ GIMT_Encode4(189355), // Rule ID 3717 //
69936 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
69937 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3partw2),
69938 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
69939 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
69940 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
69941 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
69942 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69943 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69944 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69945 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
69946 // (intrinsic_wo_chain:{ *:[v4i32] } 517:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm) => (SM3PARTW2:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
69947 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3PARTW2),
69948 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
69949 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
69950 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
69951 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
69952 GIR_RootConstrainSelectedInstOperands,
69953 // GIR_Coverage, 3717,
69954 GIR_EraseRootFromParent_Done,
69955 // Label 3982: @189355
69956 GIM_Try, /*On fail goto*//*Label 3983*/ GIMT_Encode4(189412), // Rule ID 3734 //
69957 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
69958 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
69959 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
69960 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
69961 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
69962 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
69963 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69964 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69965 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69966 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69967 // (intrinsic_wo_chain:{ *:[v4f16] } 719:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FCMLAv4f16:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4f16] }:$Rm, 0:{ *:[i32] })
69968 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16),
69969 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69970 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69971 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69972 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69973 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
69974 GIR_RootConstrainSelectedInstOperands,
69975 // GIR_Coverage, 3734,
69976 GIR_EraseRootFromParent_Done,
69977 // Label 3983: @189412
69978 GIM_Try, /*On fail goto*//*Label 3984*/ GIMT_Encode4(189469), // Rule ID 3735 //
69979 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
69980 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
69981 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
69982 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
69983 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
69984 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
69985 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69986 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69987 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69988 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
69989 // (intrinsic_wo_chain:{ *:[v4f16] } 722:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FCMLAv4f16:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4f16] }:$Rm, 1:{ *:[i32] })
69990 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16),
69991 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
69992 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
69993 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
69994 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
69995 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
69996 GIR_RootConstrainSelectedInstOperands,
69997 // GIR_Coverage, 3735,
69998 GIR_EraseRootFromParent_Done,
69999 // Label 3984: @189469
70000 GIM_Try, /*On fail goto*//*Label 3985*/ GIMT_Encode4(189526), // Rule ID 3736 //
70001 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
70002 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
70003 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
70004 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
70005 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
70006 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
70007 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70008 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70009 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70010 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70011 // (intrinsic_wo_chain:{ *:[v4f16] } 720:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FCMLAv4f16:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4f16] }:$Rm, 2:{ *:[i32] })
70012 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16),
70013 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70014 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70015 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70016 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70017 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
70018 GIR_RootConstrainSelectedInstOperands,
70019 // GIR_Coverage, 3736,
70020 GIR_EraseRootFromParent_Done,
70021 // Label 3985: @189526
70022 GIM_Try, /*On fail goto*//*Label 3986*/ GIMT_Encode4(189583), // Rule ID 3737 //
70023 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
70024 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
70025 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
70026 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
70027 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
70028 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
70029 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70030 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70031 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70032 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70033 // (intrinsic_wo_chain:{ *:[v4f16] } 721:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FCMLAv4f16:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4f16] }:$Rm, 3:{ *:[i32] })
70034 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16),
70035 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70036 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70037 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70038 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70039 GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
70040 GIR_RootConstrainSelectedInstOperands,
70041 // GIR_Coverage, 3737,
70042 GIR_EraseRootFromParent_Done,
70043 // Label 3986: @189583
70044 GIM_Try, /*On fail goto*//*Label 3987*/ GIMT_Encode4(189640), // Rule ID 3742 //
70045 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
70046 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
70047 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
70048 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
70049 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
70050 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
70051 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70052 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70053 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70054 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70055 // (intrinsic_wo_chain:{ *:[v8f16] } 719:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCMLAv8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v8f16] }:$Rm, 0:{ *:[i32] })
70056 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16),
70057 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70058 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70059 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70060 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70061 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
70062 GIR_RootConstrainSelectedInstOperands,
70063 // GIR_Coverage, 3742,
70064 GIR_EraseRootFromParent_Done,
70065 // Label 3987: @189640
70066 GIM_Try, /*On fail goto*//*Label 3988*/ GIMT_Encode4(189697), // Rule ID 3743 //
70067 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
70068 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
70069 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
70070 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
70071 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
70072 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
70073 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70074 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70075 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70076 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70077 // (intrinsic_wo_chain:{ *:[v8f16] } 722:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCMLAv8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v8f16] }:$Rm, 1:{ *:[i32] })
70078 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16),
70079 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70080 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70081 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70082 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70083 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
70084 GIR_RootConstrainSelectedInstOperands,
70085 // GIR_Coverage, 3743,
70086 GIR_EraseRootFromParent_Done,
70087 // Label 3988: @189697
70088 GIM_Try, /*On fail goto*//*Label 3989*/ GIMT_Encode4(189754), // Rule ID 3744 //
70089 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
70090 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
70091 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
70092 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
70093 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
70094 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
70095 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70096 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70097 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70098 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70099 // (intrinsic_wo_chain:{ *:[v8f16] } 720:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCMLAv8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v8f16] }:$Rm, 2:{ *:[i32] })
70100 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16),
70101 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70102 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70103 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70104 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70105 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
70106 GIR_RootConstrainSelectedInstOperands,
70107 // GIR_Coverage, 3744,
70108 GIR_EraseRootFromParent_Done,
70109 // Label 3989: @189754
70110 GIM_Try, /*On fail goto*//*Label 3990*/ GIMT_Encode4(189811), // Rule ID 3745 //
70111 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
70112 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
70113 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
70114 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
70115 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
70116 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
70117 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70118 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70119 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70120 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70121 // (intrinsic_wo_chain:{ *:[v8f16] } 721:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCMLAv8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v8f16] }:$Rm, 3:{ *:[i32] })
70122 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16),
70123 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70124 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70125 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70126 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70127 GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
70128 GIR_RootConstrainSelectedInstOperands,
70129 // GIR_Coverage, 3745,
70130 GIR_EraseRootFromParent_Done,
70131 // Label 3990: @189811
70132 GIM_Try, /*On fail goto*//*Label 3991*/ GIMT_Encode4(189868), // Rule ID 3750 //
70133 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
70134 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
70135 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
70136 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
70137 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
70138 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
70139 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70140 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70141 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70142 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70143 // (intrinsic_wo_chain:{ *:[v2f32] } 719:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FCMLAv2f32:{ *:[v2f32] } ?:{ *:[v2f32] }:$Rd, ?:{ *:[v2f32] }:$Rn, ?:{ *:[v2f32] }:$Rm, 0:{ *:[i32] })
70144 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f32),
70145 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70146 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70147 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70148 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70149 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
70150 GIR_RootConstrainSelectedInstOperands,
70151 // GIR_Coverage, 3750,
70152 GIR_EraseRootFromParent_Done,
70153 // Label 3991: @189868
70154 GIM_Try, /*On fail goto*//*Label 3992*/ GIMT_Encode4(189925), // Rule ID 3751 //
70155 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
70156 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
70157 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
70158 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
70159 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
70160 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
70161 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70162 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70163 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70164 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70165 // (intrinsic_wo_chain:{ *:[v2f32] } 722:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FCMLAv2f32:{ *:[v2f32] } ?:{ *:[v2f32] }:$Rd, ?:{ *:[v2f32] }:$Rn, ?:{ *:[v2f32] }:$Rm, 1:{ *:[i32] })
70166 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f32),
70167 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70168 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70169 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70170 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70171 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
70172 GIR_RootConstrainSelectedInstOperands,
70173 // GIR_Coverage, 3751,
70174 GIR_EraseRootFromParent_Done,
70175 // Label 3992: @189925
70176 GIM_Try, /*On fail goto*//*Label 3993*/ GIMT_Encode4(189982), // Rule ID 3752 //
70177 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
70178 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
70179 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
70180 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
70181 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
70182 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
70183 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70184 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70185 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70186 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70187 // (intrinsic_wo_chain:{ *:[v2f32] } 720:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FCMLAv2f32:{ *:[v2f32] } ?:{ *:[v2f32] }:$Rd, ?:{ *:[v2f32] }:$Rn, ?:{ *:[v2f32] }:$Rm, 2:{ *:[i32] })
70188 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f32),
70189 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70190 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70191 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70192 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70193 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
70194 GIR_RootConstrainSelectedInstOperands,
70195 // GIR_Coverage, 3752,
70196 GIR_EraseRootFromParent_Done,
70197 // Label 3993: @189982
70198 GIM_Try, /*On fail goto*//*Label 3994*/ GIMT_Encode4(190039), // Rule ID 3753 //
70199 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
70200 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
70201 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
70202 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
70203 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
70204 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
70205 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70206 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70207 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70208 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70209 // (intrinsic_wo_chain:{ *:[v2f32] } 721:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FCMLAv2f32:{ *:[v2f32] } ?:{ *:[v2f32] }:$Rd, ?:{ *:[v2f32] }:$Rn, ?:{ *:[v2f32] }:$Rm, 3:{ *:[i32] })
70210 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f32),
70211 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70212 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70213 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70214 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70215 GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
70216 GIR_RootConstrainSelectedInstOperands,
70217 // GIR_Coverage, 3753,
70218 GIR_EraseRootFromParent_Done,
70219 // Label 3994: @190039
70220 GIM_Try, /*On fail goto*//*Label 3995*/ GIMT_Encode4(190096), // Rule ID 3754 //
70221 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
70222 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
70223 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
70224 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
70225 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
70226 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
70227 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70228 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70229 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70230 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70231 // (intrinsic_wo_chain:{ *:[v4f32] } 719:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FCMLAv4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v4f32] }:$Rm, 0:{ *:[i32] })
70232 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32),
70233 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70234 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70235 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70236 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70237 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
70238 GIR_RootConstrainSelectedInstOperands,
70239 // GIR_Coverage, 3754,
70240 GIR_EraseRootFromParent_Done,
70241 // Label 3995: @190096
70242 GIM_Try, /*On fail goto*//*Label 3996*/ GIMT_Encode4(190153), // Rule ID 3755 //
70243 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
70244 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
70245 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
70246 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
70247 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
70248 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
70249 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70250 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70251 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70252 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70253 // (intrinsic_wo_chain:{ *:[v4f32] } 722:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FCMLAv4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v4f32] }:$Rm, 1:{ *:[i32] })
70254 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32),
70255 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70256 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70257 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70258 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70259 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
70260 GIR_RootConstrainSelectedInstOperands,
70261 // GIR_Coverage, 3755,
70262 GIR_EraseRootFromParent_Done,
70263 // Label 3996: @190153
70264 GIM_Try, /*On fail goto*//*Label 3997*/ GIMT_Encode4(190210), // Rule ID 3756 //
70265 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
70266 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
70267 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
70268 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
70269 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
70270 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
70271 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70272 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70273 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70274 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70275 // (intrinsic_wo_chain:{ *:[v4f32] } 720:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FCMLAv4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v4f32] }:$Rm, 2:{ *:[i32] })
70276 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32),
70277 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70278 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70279 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70280 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70281 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
70282 GIR_RootConstrainSelectedInstOperands,
70283 // GIR_Coverage, 3756,
70284 GIR_EraseRootFromParent_Done,
70285 // Label 3997: @190210
70286 GIM_Try, /*On fail goto*//*Label 3998*/ GIMT_Encode4(190267), // Rule ID 3757 //
70287 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
70288 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
70289 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
70290 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
70291 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
70292 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
70293 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70294 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70295 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70296 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70297 // (intrinsic_wo_chain:{ *:[v4f32] } 721:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FCMLAv4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v4f32] }:$Rm, 3:{ *:[i32] })
70298 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32),
70299 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70300 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70301 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70302 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70303 GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
70304 GIR_RootConstrainSelectedInstOperands,
70305 // GIR_Coverage, 3757,
70306 GIR_EraseRootFromParent_Done,
70307 // Label 3998: @190267
70308 GIM_Try, /*On fail goto*//*Label 3999*/ GIMT_Encode4(190324), // Rule ID 3758 //
70309 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
70310 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
70311 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
70312 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
70313 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
70314 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
70315 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70316 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70317 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70318 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70319 // (intrinsic_wo_chain:{ *:[v2f64] } 719:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FCMLAv2f64:{ *:[v2f64] } ?:{ *:[v2f64] }:$Rd, ?:{ *:[v2f64] }:$Rn, ?:{ *:[v2f64] }:$Rm, 0:{ *:[i32] })
70320 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f64),
70321 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70322 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70323 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70324 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70325 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
70326 GIR_RootConstrainSelectedInstOperands,
70327 // GIR_Coverage, 3758,
70328 GIR_EraseRootFromParent_Done,
70329 // Label 3999: @190324
70330 GIM_Try, /*On fail goto*//*Label 4000*/ GIMT_Encode4(190381), // Rule ID 3759 //
70331 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
70332 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
70333 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
70334 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
70335 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
70336 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
70337 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70338 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70339 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70340 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70341 // (intrinsic_wo_chain:{ *:[v2f64] } 722:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FCMLAv2f64:{ *:[v2f64] } ?:{ *:[v2f64] }:$Rd, ?:{ *:[v2f64] }:$Rn, ?:{ *:[v2f64] }:$Rm, 1:{ *:[i32] })
70342 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f64),
70343 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70344 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70345 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70346 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70347 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
70348 GIR_RootConstrainSelectedInstOperands,
70349 // GIR_Coverage, 3759,
70350 GIR_EraseRootFromParent_Done,
70351 // Label 4000: @190381
70352 GIM_Try, /*On fail goto*//*Label 4001*/ GIMT_Encode4(190438), // Rule ID 3760 //
70353 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
70354 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
70355 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
70356 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
70357 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
70358 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
70359 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70360 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70361 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70362 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70363 // (intrinsic_wo_chain:{ *:[v2f64] } 720:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FCMLAv2f64:{ *:[v2f64] } ?:{ *:[v2f64] }:$Rd, ?:{ *:[v2f64] }:$Rn, ?:{ *:[v2f64] }:$Rm, 2:{ *:[i32] })
70364 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f64),
70365 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70366 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70367 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70368 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70369 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
70370 GIR_RootConstrainSelectedInstOperands,
70371 // GIR_Coverage, 3760,
70372 GIR_EraseRootFromParent_Done,
70373 // Label 4001: @190438
70374 GIM_Try, /*On fail goto*//*Label 4002*/ GIMT_Encode4(190495), // Rule ID 3761 //
70375 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
70376 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
70377 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
70378 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
70379 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
70380 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
70381 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70382 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70383 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70384 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70385 // (intrinsic_wo_chain:{ *:[v2f64] } 721:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FCMLAv2f64:{ *:[v2f64] } ?:{ *:[v2f64] }:$Rd, ?:{ *:[v2f64] }:$Rn, ?:{ *:[v2f64] }:$Rm, 3:{ *:[i32] })
70386 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f64),
70387 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70388 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70389 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70390 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70391 GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
70392 GIR_RootConstrainSelectedInstOperands,
70393 // GIR_Coverage, 3761,
70394 GIR_EraseRootFromParent_Done,
70395 // Label 4002: @190495
70396 GIM_Try, /*On fail goto*//*Label 4003*/ GIMT_Encode4(190549), // Rule ID 4880 //
70397 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRDM),
70398 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
70399 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
70400 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
70401 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
70402 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
70403 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
70404 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
70405 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
70406 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
70407 // (intrinsic_wo_chain:{ *:[i32] } 648:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQRDMLAHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
70408 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv1i32),
70409 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70410 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70411 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70412 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70413 GIR_RootConstrainSelectedInstOperands,
70414 // GIR_Coverage, 4880,
70415 GIR_EraseRootFromParent_Done,
70416 // Label 4003: @190549
70417 GIM_Try, /*On fail goto*//*Label 4004*/ GIMT_Encode4(190603), // Rule ID 4881 //
70418 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRDM),
70419 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
70420 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
70421 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
70422 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
70423 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
70424 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
70425 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
70426 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
70427 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
70428 // (intrinsic_wo_chain:{ *:[i32] } 649:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm) => (SQRDMLSHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
70429 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv1i32),
70430 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70431 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70432 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70433 GIR_RootToRootCopy, /*OpIdx*/4, // Rm
70434 GIR_RootConstrainSelectedInstOperands,
70435 // GIR_Coverage, 4881,
70436 GIR_EraseRootFromParent_Done,
70437 // Label 4004: @190603
70438 GIM_Try, /*On fail goto*//*Label 4005*/ GIMT_Encode4(190654), // Rule ID 5238 //
70439 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_tbx1),
70440 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
70441 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
70442 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
70443 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
70444 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70445 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70446 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70447 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
70448 // (intrinsic_wo_chain:{ *:[v8i8] } 682:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri) => (TBXv8i8One:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri)
70449 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXv8i8One),
70450 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70451 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70452 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
70453 GIR_RootToRootCopy, /*OpIdx*/4, // Ri
70454 GIR_RootConstrainSelectedInstOperands,
70455 // GIR_Coverage, 5238,
70456 GIR_EraseRootFromParent_Done,
70457 // Label 4005: @190654
70458 GIM_Try, /*On fail goto*//*Label 4006*/ GIMT_Encode4(190705), // Rule ID 5239 //
70459 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_tbx1),
70460 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
70461 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
70462 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
70463 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
70464 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70465 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70466 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70467 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
70468 // (intrinsic_wo_chain:{ *:[v16i8] } 682:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn) => (TBXv16i8One:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn)
70469 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXv16i8One),
70470 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
70471 GIR_RootToRootCopy, /*OpIdx*/2, // Rd
70472 GIR_RootToRootCopy, /*OpIdx*/3, // Ri
70473 GIR_RootToRootCopy, /*OpIdx*/4, // Rn
70474 GIR_RootConstrainSelectedInstOperands,
70475 // GIR_Coverage, 5239,
70476 GIR_EraseRootFromParent_Done,
70477 // Label 4006: @190705
70478 GIM_Try, /*On fail goto*//*Label 4007*/ GIMT_Encode4(190747), // Rule ID 2597 //
70479 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
70480 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
70481 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
70482 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
70483 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
70484 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
70485 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70486 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1699:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (TBX_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
70487 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_B),
70488 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
70489 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70490 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70491 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70492 GIR_RootConstrainSelectedInstOperands,
70493 // GIR_Coverage, 2597,
70494 GIR_EraseRootFromParent_Done,
70495 // Label 4007: @190747
70496 GIM_Try, /*On fail goto*//*Label 4008*/ GIMT_Encode4(190789), // Rule ID 2598 //
70497 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
70498 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
70499 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
70500 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
70501 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
70502 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
70503 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70504 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1699:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (TBX_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
70505 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_H),
70506 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
70507 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70508 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70509 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70510 GIR_RootConstrainSelectedInstOperands,
70511 // GIR_Coverage, 2598,
70512 GIR_EraseRootFromParent_Done,
70513 // Label 4008: @190789
70514 GIM_Try, /*On fail goto*//*Label 4009*/ GIMT_Encode4(190831), // Rule ID 2599 //
70515 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
70516 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
70517 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
70518 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
70519 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
70520 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
70521 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70522 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1699:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (TBX_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
70523 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_S),
70524 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
70525 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70526 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70527 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70528 GIR_RootConstrainSelectedInstOperands,
70529 // GIR_Coverage, 2599,
70530 GIR_EraseRootFromParent_Done,
70531 // Label 4009: @190831
70532 GIM_Try, /*On fail goto*//*Label 4010*/ GIMT_Encode4(190873), // Rule ID 2600 //
70533 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
70534 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
70535 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
70536 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
70537 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
70538 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
70539 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70540 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1699:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (TBX_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
70541 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_D),
70542 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
70543 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70544 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70545 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70546 GIR_RootConstrainSelectedInstOperands,
70547 // GIR_Coverage, 2600,
70548 GIR_EraseRootFromParent_Done,
70549 // Label 4010: @190873
70550 GIM_Try, /*On fail goto*//*Label 4011*/ GIMT_Encode4(190915), // Rule ID 2601 //
70551 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
70552 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
70553 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
70554 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
70555 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
70556 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
70557 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70558 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1699:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (TBX_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
70559 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_H),
70560 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
70561 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70562 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70563 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70564 GIR_RootConstrainSelectedInstOperands,
70565 // GIR_Coverage, 2601,
70566 GIR_EraseRootFromParent_Done,
70567 // Label 4011: @190915
70568 GIM_Try, /*On fail goto*//*Label 4012*/ GIMT_Encode4(190957), // Rule ID 2602 //
70569 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
70570 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
70571 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
70572 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
70573 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
70574 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
70575 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70576 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1699:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (TBX_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
70577 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_S),
70578 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
70579 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70580 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70581 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70582 GIR_RootConstrainSelectedInstOperands,
70583 // GIR_Coverage, 2602,
70584 GIR_EraseRootFromParent_Done,
70585 // Label 4012: @190957
70586 GIM_Try, /*On fail goto*//*Label 4013*/ GIMT_Encode4(190999), // Rule ID 2603 //
70587 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
70588 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
70589 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
70590 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
70591 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
70592 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
70593 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70594 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1699:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (TBX_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
70595 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_D),
70596 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
70597 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70598 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70599 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70600 GIR_RootConstrainSelectedInstOperands,
70601 // GIR_Coverage, 2603,
70602 GIR_EraseRootFromParent_Done,
70603 // Label 4013: @190999
70604 GIM_Try, /*On fail goto*//*Label 4014*/ GIMT_Encode4(191041), // Rule ID 2604 //
70605 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
70606 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
70607 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
70608 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
70609 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
70610 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
70611 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70612 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1699:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (TBX_ZZZ_H:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
70613 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_H),
70614 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
70615 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70616 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70617 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70618 GIR_RootConstrainSelectedInstOperands,
70619 // GIR_Coverage, 2604,
70620 GIR_EraseRootFromParent_Done,
70621 // Label 4014: @191041
70622 GIM_Try, /*On fail goto*//*Label 4015*/ GIMT_Encode4(191083), // Rule ID 2648 //
70623 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
70624 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_and_z),
70625 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
70626 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
70627 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
70628 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
70629 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
70630 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1080:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3) => (AND_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
70631 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
70632 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
70633 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70634 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70635 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70636 GIR_RootConstrainSelectedInstOperands,
70637 // GIR_Coverage, 2648,
70638 GIR_EraseRootFromParent_Done,
70639 // Label 4015: @191083
70640 GIM_Try, /*On fail goto*//*Label 4016*/ GIMT_Encode4(191125), // Rule ID 2649 //
70641 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
70642 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_and_z),
70643 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
70644 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
70645 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
70646 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
70647 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
70648 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1080:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3) => (AND_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
70649 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
70650 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
70651 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70652 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70653 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70654 GIR_RootConstrainSelectedInstOperands,
70655 // GIR_Coverage, 2649,
70656 GIR_EraseRootFromParent_Done,
70657 // Label 4016: @191125
70658 GIM_Try, /*On fail goto*//*Label 4017*/ GIMT_Encode4(191167), // Rule ID 2650 //
70659 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
70660 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_and_z),
70661 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
70662 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
70663 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
70664 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
70665 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
70666 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1080:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3) => (AND_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
70667 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
70668 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
70669 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70670 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70671 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70672 GIR_RootConstrainSelectedInstOperands,
70673 // GIR_Coverage, 2650,
70674 GIR_EraseRootFromParent_Done,
70675 // Label 4017: @191167
70676 GIM_Try, /*On fail goto*//*Label 4018*/ GIMT_Encode4(191209), // Rule ID 2651 //
70677 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
70678 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_and_z),
70679 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
70680 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
70681 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
70682 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
70683 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
70684 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1080:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3) => (AND_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
70685 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
70686 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
70687 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70688 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70689 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70690 GIR_RootConstrainSelectedInstOperands,
70691 // GIR_Coverage, 2651,
70692 GIR_EraseRootFromParent_Done,
70693 // Label 4018: @191209
70694 GIM_Try, /*On fail goto*//*Label 4019*/ GIMT_Encode4(191251), // Rule ID 2652 //
70695 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
70696 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_and_z),
70697 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
70698 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
70699 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
70700 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
70701 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
70702 // (intrinsic_wo_chain:{ *:[nxv1i1] } 1080:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3) => (AND_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
70703 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
70704 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
70705 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70706 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70707 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70708 GIR_RootConstrainSelectedInstOperands,
70709 // GIR_Coverage, 2652,
70710 GIR_EraseRootFromParent_Done,
70711 // Label 4019: @191251
70712 GIM_Try, /*On fail goto*//*Label 4020*/ GIMT_Encode4(191293), // Rule ID 2691 //
70713 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasB16B16_HasSVE2orSME2),
70714 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
70715 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
70716 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
70717 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
70718 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
70719 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70720 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1179:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3) => (BFADD_ZPmZZ:{ *:[nxv8bf16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3)
70721 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFADD_ZPmZZ),
70722 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
70723 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70724 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70725 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70726 GIR_RootConstrainSelectedInstOperands,
70727 // GIR_Coverage, 2691,
70728 GIR_EraseRootFromParent_Done,
70729 // Label 4020: @191293
70730 GIM_Try, /*On fail goto*//*Label 4021*/ GIMT_Encode4(191335), // Rule ID 2697 //
70731 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
70732 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
70733 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
70734 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
70735 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
70736 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
70737 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70738 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1179:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FADD_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
70739 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmZ_H),
70740 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
70741 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70742 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70743 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70744 GIR_RootConstrainSelectedInstOperands,
70745 // GIR_Coverage, 2697,
70746 GIR_EraseRootFromParent_Done,
70747 // Label 4021: @191335
70748 GIM_Try, /*On fail goto*//*Label 4022*/ GIMT_Encode4(191377), // Rule ID 2701 //
70749 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
70750 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
70751 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
70752 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
70753 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
70754 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
70755 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70756 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1179:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FADD_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
70757 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmZ_S),
70758 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
70759 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70760 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70761 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70762 GIR_RootConstrainSelectedInstOperands,
70763 // GIR_Coverage, 2701,
70764 GIR_EraseRootFromParent_Done,
70765 // Label 4022: @191377
70766 GIM_Try, /*On fail goto*//*Label 4023*/ GIMT_Encode4(191419), // Rule ID 2705 //
70767 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
70768 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
70769 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
70770 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
70771 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
70772 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
70773 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70774 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1179:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FADD_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
70775 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmZ_D),
70776 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
70777 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70778 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70779 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70780 GIR_RootConstrainSelectedInstOperands,
70781 // GIR_Coverage, 2705,
70782 GIR_EraseRootFromParent_Done,
70783 // Label 4023: @191419
70784 GIM_Try, /*On fail goto*//*Label 4024*/ GIMT_Encode4(191461), // Rule ID 2709 //
70785 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
70786 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fscale),
70787 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
70788 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
70789 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
70790 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
70791 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70792 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1321:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (FSCALE_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
70793 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSCALE_ZPmZ_H),
70794 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
70795 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70796 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70797 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70798 GIR_RootConstrainSelectedInstOperands,
70799 // GIR_Coverage, 2709,
70800 GIR_EraseRootFromParent_Done,
70801 // Label 4024: @191461
70802 GIM_Try, /*On fail goto*//*Label 4025*/ GIMT_Encode4(191503), // Rule ID 2710 //
70803 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
70804 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fscale),
70805 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
70806 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
70807 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
70808 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
70809 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70810 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1321:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (FSCALE_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
70811 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSCALE_ZPmZ_S),
70812 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
70813 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70814 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70815 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70816 GIR_RootConstrainSelectedInstOperands,
70817 // GIR_Coverage, 2710,
70818 GIR_EraseRootFromParent_Done,
70819 // Label 4025: @191503
70820 GIM_Try, /*On fail goto*//*Label 4026*/ GIMT_Encode4(191545), // Rule ID 2711 //
70821 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
70822 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fscale),
70823 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
70824 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
70825 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
70826 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
70827 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70828 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1321:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (FSCALE_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
70829 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSCALE_ZPmZ_D),
70830 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
70831 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70832 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70833 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70834 GIR_RootConstrainSelectedInstOperands,
70835 // GIR_Coverage, 2711,
70836 GIR_EraseRootFromParent_Done,
70837 // Label 4026: @191545
70838 GIM_Try, /*On fail goto*//*Label 4027*/ GIMT_Encode4(191587), // Rule ID 2787 //
70839 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
70840 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtnt_f16f32),
70841 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
70842 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
70843 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
70844 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
70845 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70846 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1211:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FCVTNT_ZPmZ_StoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
70847 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNT_ZPmZ_StoH),
70848 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
70849 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70850 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70851 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70852 GIR_RootConstrainSelectedInstOperands,
70853 // GIR_Coverage, 2787,
70854 GIR_EraseRootFromParent_Done,
70855 // Label 4027: @191587
70856 GIM_Try, /*On fail goto*//*Label 4028*/ GIMT_Encode4(191629), // Rule ID 2788 //
70857 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
70858 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtnt_f32f64),
70859 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
70860 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
70861 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
70862 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
70863 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70864 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1212:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FCVTNT_ZPmZ_DtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
70865 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNT_ZPmZ_DtoS),
70866 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
70867 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70868 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70869 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70870 GIR_RootConstrainSelectedInstOperands,
70871 // GIR_Coverage, 2788,
70872 GIR_EraseRootFromParent_Done,
70873 // Label 4028: @191629
70874 GIM_Try, /*On fail goto*//*Label 4029*/ GIMT_Encode4(191671), // Rule ID 2789 //
70875 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
70876 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtlt_f32f16),
70877 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
70878 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
70879 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
70880 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
70881 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70882 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1207:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FCVTLT_ZPmZ_HtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
70883 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTLT_ZPmZ_HtoS),
70884 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
70885 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70886 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70887 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70888 GIR_RootConstrainSelectedInstOperands,
70889 // GIR_Coverage, 2789,
70890 GIR_EraseRootFromParent_Done,
70891 // Label 4029: @191671
70892 GIM_Try, /*On fail goto*//*Label 4030*/ GIMT_Encode4(191713), // Rule ID 2790 //
70893 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
70894 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtlt_f64f32),
70895 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
70896 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
70897 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
70898 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
70899 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70900 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1208:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FCVTLT_ZPmZ_StoD:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
70901 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTLT_ZPmZ_StoD),
70902 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
70903 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70904 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70905 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70906 GIR_RootConstrainSelectedInstOperands,
70907 // GIR_Coverage, 2790,
70908 GIR_EraseRootFromParent_Done,
70909 // Label 4030: @191713
70910 GIM_Try, /*On fail goto*//*Label 4031*/ GIMT_Encode4(191755), // Rule ID 2791 //
70911 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
70912 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtxnt_f32f64),
70913 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
70914 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
70915 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
70916 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
70917 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70918 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1214:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FCVTXNT_ZPmZ_DtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
70919 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTXNT_ZPmZ_DtoS),
70920 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
70921 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70922 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70923 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70924 GIR_RootConstrainSelectedInstOperands,
70925 // GIR_Coverage, 2791,
70926 GIR_EraseRootFromParent_Done,
70927 // Label 4031: @191755
70928 GIM_Try, /*On fail goto*//*Label 4032*/ GIMT_Encode4(191797), // Rule ID 2792 //
70929 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
70930 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_faddp),
70931 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
70932 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
70933 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
70934 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
70935 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70936 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1182:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FADDP_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
70937 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDP_ZPmZZ_H),
70938 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
70939 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70940 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70941 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70942 GIR_RootConstrainSelectedInstOperands,
70943 // GIR_Coverage, 2792,
70944 GIR_EraseRootFromParent_Done,
70945 // Label 4032: @191797
70946 GIM_Try, /*On fail goto*//*Label 4033*/ GIMT_Encode4(191839), // Rule ID 2793 //
70947 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
70948 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_faddp),
70949 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
70950 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
70951 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
70952 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
70953 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70954 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1182:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FADDP_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
70955 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDP_ZPmZZ_S),
70956 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
70957 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70958 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70959 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70960 GIR_RootConstrainSelectedInstOperands,
70961 // GIR_Coverage, 2793,
70962 GIR_EraseRootFromParent_Done,
70963 // Label 4033: @191839
70964 GIM_Try, /*On fail goto*//*Label 4034*/ GIMT_Encode4(191881), // Rule ID 2794 //
70965 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
70966 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_faddp),
70967 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
70968 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
70969 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
70970 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
70971 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70972 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1182:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FADDP_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
70973 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDP_ZPmZZ_D),
70974 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
70975 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70976 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70977 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70978 GIR_RootConstrainSelectedInstOperands,
70979 // GIR_Coverage, 2794,
70980 GIR_EraseRootFromParent_Done,
70981 // Label 4034: @191881
70982 GIM_Try, /*On fail goto*//*Label 4035*/ GIMT_Encode4(191923), // Rule ID 2796 //
70983 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasSVEorSME),
70984 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bfmlalb),
70985 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
70986 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
70987 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
70988 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
70989 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
70990 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1096:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3) => (BFMLALB_ZZZ:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3)
70991 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMLALB_ZZZ),
70992 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
70993 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
70994 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
70995 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
70996 GIR_RootConstrainSelectedInstOperands,
70997 // GIR_Coverage, 2796,
70998 GIR_EraseRootFromParent_Done,
70999 // Label 4035: @191923
71000 GIM_Try, /*On fail goto*//*Label 4036*/ GIMT_Encode4(191965), // Rule ID 2808 //
71001 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
71002 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvt_f32f16),
71003 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
71004 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
71005 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
71006 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
71007 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71008 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1200:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FCVT_ZPmZ_HtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
71009 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVT_ZPmZ_HtoS),
71010 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71011 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71012 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71013 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71014 GIR_RootConstrainSelectedInstOperands,
71015 // GIR_Coverage, 2808,
71016 GIR_EraseRootFromParent_Done,
71017 // Label 4036: @191965
71018 GIM_Try, /*On fail goto*//*Label 4037*/ GIMT_Encode4(192007), // Rule ID 2810 //
71019 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
71020 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvt_f16f32),
71021 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
71022 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
71023 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
71024 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
71025 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71026 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1198:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FCVT_ZPmZ_StoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
71027 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVT_ZPmZ_StoH),
71028 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71029 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71030 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71031 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71032 GIR_RootConstrainSelectedInstOperands,
71033 // GIR_Coverage, 2810,
71034 GIR_EraseRootFromParent_Done,
71035 // Label 4037: @192007
71036 GIM_Try, /*On fail goto*//*Label 4038*/ GIMT_Encode4(192049), // Rule ID 2818 //
71037 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71038 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_flogb),
71039 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
71040 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
71041 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
71042 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
71043 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71044 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1235:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FLOGB_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
71045 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FLOGB_ZPmZ_H),
71046 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71047 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71048 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71049 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71050 GIR_RootConstrainSelectedInstOperands,
71051 // GIR_Coverage, 2818,
71052 GIR_EraseRootFromParent_Done,
71053 // Label 4038: @192049
71054 GIM_Try, /*On fail goto*//*Label 4039*/ GIMT_Encode4(192091), // Rule ID 2819 //
71055 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71056 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_flogb),
71057 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
71058 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
71059 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
71060 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
71061 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71062 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1235:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FLOGB_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
71063 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FLOGB_ZPmZ_S),
71064 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71065 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71066 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71067 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71068 GIR_RootConstrainSelectedInstOperands,
71069 // GIR_Coverage, 2819,
71070 GIR_EraseRootFromParent_Done,
71071 // Label 4039: @192091
71072 GIM_Try, /*On fail goto*//*Label 4040*/ GIMT_Encode4(192133), // Rule ID 2820 //
71073 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71074 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_flogb),
71075 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
71076 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
71077 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
71078 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
71079 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71080 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1235:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FLOGB_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
71081 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FLOGB_ZPmZ_D),
71082 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71083 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71084 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71085 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71086 GIR_RootConstrainSelectedInstOperands,
71087 // GIR_Coverage, 2820,
71088 GIR_EraseRootFromParent_Done,
71089 // Label 4040: @192133
71090 GIM_Try, /*On fail goto*//*Label 4041*/ GIMT_Encode4(192175), // Rule ID 2824 //
71091 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71092 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtx_f32f64),
71093 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
71094 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
71095 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
71096 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
71097 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71098 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1213:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FCVTX_ZPmZ_DtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
71099 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTX_ZPmZ_DtoS),
71100 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71101 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71102 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71103 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71104 GIR_RootConstrainSelectedInstOperands,
71105 // GIR_Coverage, 2824,
71106 GIR_EraseRootFromParent_Done,
71107 // Label 4041: @192175
71108 GIM_Try, /*On fail goto*//*Label 4042*/ GIMT_Encode4(192217), // Rule ID 2868 //
71109 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
71110 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdiv),
71111 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
71112 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
71113 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
71114 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
71115 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71116 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1487:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SDIV_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
71117 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDIV_ZPmZ_S),
71118 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
71119 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71120 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71121 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71122 GIR_RootConstrainSelectedInstOperands,
71123 // GIR_Coverage, 2868,
71124 GIR_EraseRootFromParent_Done,
71125 // Label 4042: @192217
71126 GIM_Try, /*On fail goto*//*Label 4043*/ GIMT_Encode4(192259), // Rule ID 2869 //
71127 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
71128 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdiv),
71129 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
71130 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
71131 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
71132 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
71133 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71134 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1487:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SDIV_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
71135 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDIV_ZPmZ_D),
71136 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
71137 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71138 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71139 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71140 GIR_RootConstrainSelectedInstOperands,
71141 // GIR_Coverage, 2869,
71142 GIR_EraseRootFromParent_Done,
71143 // Label 4043: @192259
71144 GIM_Try, /*On fail goto*//*Label 4044*/ GIMT_Encode4(192301), // Rule ID 2898 //
71145 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71146 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah),
71147 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
71148 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
71149 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
71150 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
71151 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71152 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1603:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SQRDMLAH_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
71153 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZ_B),
71154 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
71155 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71156 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71157 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71158 GIR_RootConstrainSelectedInstOperands,
71159 // GIR_Coverage, 2898,
71160 GIR_EraseRootFromParent_Done,
71161 // Label 4044: @192301
71162 GIM_Try, /*On fail goto*//*Label 4045*/ GIMT_Encode4(192343), // Rule ID 2899 //
71163 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71164 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah),
71165 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
71166 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
71167 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
71168 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
71169 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71170 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1603:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SQRDMLAH_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
71171 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZ_H),
71172 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
71173 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71174 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71175 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71176 GIR_RootConstrainSelectedInstOperands,
71177 // GIR_Coverage, 2899,
71178 GIR_EraseRootFromParent_Done,
71179 // Label 4045: @192343
71180 GIM_Try, /*On fail goto*//*Label 4046*/ GIMT_Encode4(192385), // Rule ID 2900 //
71181 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71182 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah),
71183 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
71184 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
71185 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
71186 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
71187 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71188 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1603:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SQRDMLAH_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
71189 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZ_S),
71190 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
71191 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71192 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71193 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71194 GIR_RootConstrainSelectedInstOperands,
71195 // GIR_Coverage, 2900,
71196 GIR_EraseRootFromParent_Done,
71197 // Label 4046: @192385
71198 GIM_Try, /*On fail goto*//*Label 4047*/ GIMT_Encode4(192427), // Rule ID 2901 //
71199 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71200 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah),
71201 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
71202 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
71203 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
71204 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
71205 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71206 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1603:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SQRDMLAH_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
71207 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZ_D),
71208 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
71209 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71210 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71211 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71212 GIR_RootConstrainSelectedInstOperands,
71213 // GIR_Coverage, 2901,
71214 GIR_EraseRootFromParent_Done,
71215 // Label 4047: @192427
71216 GIM_Try, /*On fail goto*//*Label 4048*/ GIMT_Encode4(192469), // Rule ID 2902 //
71217 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71218 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalb),
71219 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
71220 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
71221 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
71222 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
71223 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71224 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1524:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SMLALB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
71225 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALB_ZZZ_H),
71226 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
71227 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71228 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71229 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71230 GIR_RootConstrainSelectedInstOperands,
71231 // GIR_Coverage, 2902,
71232 GIR_EraseRootFromParent_Done,
71233 // Label 4048: @192469
71234 GIM_Try, /*On fail goto*//*Label 4049*/ GIMT_Encode4(192511), // Rule ID 2903 //
71235 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71236 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalb),
71237 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
71238 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
71239 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
71240 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
71241 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71242 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1524:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SMLALB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
71243 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALB_ZZZ_S),
71244 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
71245 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71246 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71247 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71248 GIR_RootConstrainSelectedInstOperands,
71249 // GIR_Coverage, 2903,
71250 GIR_EraseRootFromParent_Done,
71251 // Label 4049: @192511
71252 GIM_Try, /*On fail goto*//*Label 4050*/ GIMT_Encode4(192553), // Rule ID 2904 //
71253 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71254 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalb),
71255 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
71256 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
71257 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
71258 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
71259 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71260 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1524:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SMLALB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
71261 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALB_ZZZ_D),
71262 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
71263 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71264 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71265 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71266 GIR_RootConstrainSelectedInstOperands,
71267 // GIR_Coverage, 2904,
71268 GIR_EraseRootFromParent_Done,
71269 // Label 4050: @192553
71270 GIM_Try, /*On fail goto*//*Label 4051*/ GIMT_Encode4(192595), // Rule ID 2934 //
71271 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71272 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shadd),
71273 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
71274 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
71275 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
71276 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
71277 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71278 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1498:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SHADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
71279 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHADD_ZPmZ_B),
71280 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
71281 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71282 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71283 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71284 GIR_RootConstrainSelectedInstOperands,
71285 // GIR_Coverage, 2934,
71286 GIR_EraseRootFromParent_Done,
71287 // Label 4051: @192595
71288 GIM_Try, /*On fail goto*//*Label 4052*/ GIMT_Encode4(192637), // Rule ID 2936 //
71289 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71290 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shadd),
71291 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
71292 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
71293 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
71294 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
71295 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71296 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1498:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SHADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
71297 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHADD_ZPmZ_H),
71298 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
71299 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71300 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71301 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71302 GIR_RootConstrainSelectedInstOperands,
71303 // GIR_Coverage, 2936,
71304 GIR_EraseRootFromParent_Done,
71305 // Label 4052: @192637
71306 GIM_Try, /*On fail goto*//*Label 4053*/ GIMT_Encode4(192679), // Rule ID 2938 //
71307 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71308 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shadd),
71309 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
71310 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
71311 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
71312 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
71313 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71314 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1498:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SHADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
71315 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHADD_ZPmZ_S),
71316 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
71317 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71318 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71319 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71320 GIR_RootConstrainSelectedInstOperands,
71321 // GIR_Coverage, 2938,
71322 GIR_EraseRootFromParent_Done,
71323 // Label 4053: @192679
71324 GIM_Try, /*On fail goto*//*Label 4054*/ GIMT_Encode4(192721), // Rule ID 2940 //
71325 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71326 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shadd),
71327 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
71328 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
71329 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
71330 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
71331 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71332 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1498:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SHADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
71333 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHADD_ZPmZ_D),
71334 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
71335 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71336 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71337 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71338 GIR_RootConstrainSelectedInstOperands,
71339 // GIR_Coverage, 2940,
71340 GIR_EraseRootFromParent_Done,
71341 // Label 4054: @192721
71342 GIM_Try, /*On fail goto*//*Label 4055*/ GIMT_Encode4(192763), // Rule ID 2942 //
71343 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71344 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sadalp),
71345 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
71346 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
71347 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
71348 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
71349 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71350 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1468:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SADALP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
71351 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALP_ZPmZ_H),
71352 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
71353 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71354 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71355 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71356 GIR_RootConstrainSelectedInstOperands,
71357 // GIR_Coverage, 2942,
71358 GIR_EraseRootFromParent_Done,
71359 // Label 4055: @192763
71360 GIM_Try, /*On fail goto*//*Label 4056*/ GIMT_Encode4(192805), // Rule ID 2943 //
71361 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71362 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sadalp),
71363 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
71364 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
71365 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
71366 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
71367 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71368 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1468:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SADALP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
71369 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALP_ZPmZ_S),
71370 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
71371 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71372 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71373 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71374 GIR_RootConstrainSelectedInstOperands,
71375 // GIR_Coverage, 2943,
71376 GIR_EraseRootFromParent_Done,
71377 // Label 4056: @192805
71378 GIM_Try, /*On fail goto*//*Label 4057*/ GIMT_Encode4(192847), // Rule ID 2944 //
71379 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71380 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sadalp),
71381 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
71382 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
71383 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
71384 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
71385 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71386 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1468:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SADALP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
71387 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALP_ZPmZ_D),
71388 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
71389 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71390 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71391 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71392 GIR_RootConstrainSelectedInstOperands,
71393 // GIR_Coverage, 2944,
71394 GIR_EraseRootFromParent_Done,
71395 // Label 4057: @192847
71396 GIM_Try, /*On fail goto*//*Label 4058*/ GIMT_Encode4(192889), // Rule ID 2945 //
71397 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71398 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urecpe),
71399 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
71400 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
71401 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
71402 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
71403 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71404 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1827:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (URECPE_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
71405 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URECPE_ZPmZ_S),
71406 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71407 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71408 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71409 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71410 GIR_RootConstrainSelectedInstOperands,
71411 // GIR_Coverage, 2945,
71412 GIR_EraseRootFromParent_Done,
71413 // Label 4058: @192889
71414 GIM_Try, /*On fail goto*//*Label 4059*/ GIMT_Encode4(192931), // Rule ID 2946 //
71415 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71416 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
71417 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
71418 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
71419 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
71420 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
71421 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71422 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1540:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SQABS_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
71423 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_B),
71424 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71425 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71426 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71427 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71428 GIR_RootConstrainSelectedInstOperands,
71429 // GIR_Coverage, 2946,
71430 GIR_EraseRootFromParent_Done,
71431 // Label 4059: @192931
71432 GIM_Try, /*On fail goto*//*Label 4060*/ GIMT_Encode4(192973), // Rule ID 2947 //
71433 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71434 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
71435 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
71436 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
71437 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
71438 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
71439 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71440 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1540:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SQABS_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
71441 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_H),
71442 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71443 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71444 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71445 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71446 GIR_RootConstrainSelectedInstOperands,
71447 // GIR_Coverage, 2947,
71448 GIR_EraseRootFromParent_Done,
71449 // Label 4060: @192973
71450 GIM_Try, /*On fail goto*//*Label 4061*/ GIMT_Encode4(193015), // Rule ID 2948 //
71451 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71452 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
71453 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
71454 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
71455 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
71456 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
71457 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71458 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1540:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SQABS_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
71459 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_S),
71460 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71461 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71462 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71463 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71464 GIR_RootConstrainSelectedInstOperands,
71465 // GIR_Coverage, 2948,
71466 GIR_EraseRootFromParent_Done,
71467 // Label 4061: @193015
71468 GIM_Try, /*On fail goto*//*Label 4062*/ GIMT_Encode4(193057), // Rule ID 2949 //
71469 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71470 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
71471 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
71472 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
71473 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
71474 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
71475 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71476 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1540:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SQABS_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
71477 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_D),
71478 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71479 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71480 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71481 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71482 GIR_RootConstrainSelectedInstOperands,
71483 // GIR_Coverage, 2949,
71484 GIR_EraseRootFromParent_Done,
71485 // Label 4062: @193057
71486 GIM_Try, /*On fail goto*//*Label 4063*/ GIMT_Encode4(193099), // Rule ID 2966 //
71487 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71488 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorbt),
71489 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
71490 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
71491 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
71492 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
71493 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71494 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1168:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (EORBT_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
71495 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORBT_ZZZ_B),
71496 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71497 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71498 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71499 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71500 GIR_RootConstrainSelectedInstOperands,
71501 // GIR_Coverage, 2966,
71502 GIR_EraseRootFromParent_Done,
71503 // Label 4063: @193099
71504 GIM_Try, /*On fail goto*//*Label 4064*/ GIMT_Encode4(193141), // Rule ID 2967 //
71505 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71506 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorbt),
71507 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
71508 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
71509 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
71510 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
71511 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71512 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1168:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (EORBT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
71513 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORBT_ZZZ_H),
71514 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71515 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71516 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71517 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71518 GIR_RootConstrainSelectedInstOperands,
71519 // GIR_Coverage, 2967,
71520 GIR_EraseRootFromParent_Done,
71521 // Label 4064: @193141
71522 GIM_Try, /*On fail goto*//*Label 4065*/ GIMT_Encode4(193183), // Rule ID 2968 //
71523 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71524 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorbt),
71525 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
71526 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
71527 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
71528 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
71529 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71530 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1168:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (EORBT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
71531 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORBT_ZZZ_S),
71532 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71533 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71534 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71535 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71536 GIR_RootConstrainSelectedInstOperands,
71537 // GIR_Coverage, 2968,
71538 GIR_EraseRootFromParent_Done,
71539 // Label 4065: @193183
71540 GIM_Try, /*On fail goto*//*Label 4066*/ GIMT_Encode4(193225), // Rule ID 2969 //
71541 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71542 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorbt),
71543 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
71544 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
71545 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
71546 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
71547 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71548 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1168:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (EORBT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
71549 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORBT_ZZZ_D),
71550 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71551 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71552 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71553 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71554 GIR_RootConstrainSelectedInstOperands,
71555 // GIR_Coverage, 2969,
71556 GIR_EraseRootFromParent_Done,
71557 // Label 4066: @193225
71558 GIM_Try, /*On fail goto*//*Label 4067*/ GIMT_Encode4(193267), // Rule ID 2993 //
71559 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71560 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saba),
71561 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
71562 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
71563 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
71564 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
71565 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71566 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1461:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SABA_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
71567 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABA_ZZZ_B),
71568 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
71569 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71570 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71571 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71572 GIR_RootConstrainSelectedInstOperands,
71573 // GIR_Coverage, 2993,
71574 GIR_EraseRootFromParent_Done,
71575 // Label 4067: @193267
71576 GIM_Try, /*On fail goto*//*Label 4068*/ GIMT_Encode4(193309), // Rule ID 2995 //
71577 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71578 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saba),
71579 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
71580 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
71581 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
71582 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
71583 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71584 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1461:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SABA_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
71585 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABA_ZZZ_H),
71586 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
71587 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71588 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71589 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71590 GIR_RootConstrainSelectedInstOperands,
71591 // GIR_Coverage, 2995,
71592 GIR_EraseRootFromParent_Done,
71593 // Label 4068: @193309
71594 GIM_Try, /*On fail goto*//*Label 4069*/ GIMT_Encode4(193351), // Rule ID 2997 //
71595 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71596 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saba),
71597 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
71598 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
71599 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
71600 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
71601 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71602 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1461:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SABA_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
71603 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABA_ZZZ_S),
71604 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
71605 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71606 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71607 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71608 GIR_RootConstrainSelectedInstOperands,
71609 // GIR_Coverage, 2997,
71610 GIR_EraseRootFromParent_Done,
71611 // Label 4069: @193351
71612 GIM_Try, /*On fail goto*//*Label 4070*/ GIMT_Encode4(193393), // Rule ID 2999 //
71613 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71614 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saba),
71615 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
71616 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
71617 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
71618 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
71619 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71620 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1461:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SABA_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
71621 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABA_ZZZ_D),
71622 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
71623 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71624 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71625 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71626 GIR_RootConstrainSelectedInstOperands,
71627 // GIR_Coverage, 2999,
71628 GIR_EraseRootFromParent_Done,
71629 // Label 4070: @193393
71630 GIM_Try, /*On fail goto*//*Label 4071*/ GIMT_Encode4(193435), // Rule ID 3001 //
71631 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71632 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabalb),
71633 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
71634 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
71635 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
71636 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
71637 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71638 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1462:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SABALB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
71639 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALB_ZZZ_H),
71640 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
71641 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71642 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71643 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71644 GIR_RootConstrainSelectedInstOperands,
71645 // GIR_Coverage, 3001,
71646 GIR_EraseRootFromParent_Done,
71647 // Label 4071: @193435
71648 GIM_Try, /*On fail goto*//*Label 4072*/ GIMT_Encode4(193477), // Rule ID 3002 //
71649 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71650 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabalb),
71651 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
71652 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
71653 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
71654 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
71655 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71656 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1462:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SABALB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
71657 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALB_ZZZ_S),
71658 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
71659 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71660 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71661 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71662 GIR_RootConstrainSelectedInstOperands,
71663 // GIR_Coverage, 3002,
71664 GIR_EraseRootFromParent_Done,
71665 // Label 4072: @193477
71666 GIM_Try, /*On fail goto*//*Label 4073*/ GIMT_Encode4(193519), // Rule ID 3003 //
71667 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71668 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabalb),
71669 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
71670 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
71671 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
71672 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
71673 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71674 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1462:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SABALB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
71675 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALB_ZZZ_D),
71676 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
71677 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71678 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71679 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71680 GIR_RootConstrainSelectedInstOperands,
71681 // GIR_Coverage, 3003,
71682 GIR_EraseRootFromParent_Done,
71683 // Label 4073: @193519
71684 GIM_Try, /*On fail goto*//*Label 4074*/ GIMT_Encode4(193561), // Rule ID 3004 //
71685 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71686 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adclb),
71687 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
71688 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
71689 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
71690 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
71691 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71692 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1060:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (ADCLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
71693 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADCLB_ZZZ_S),
71694 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
71695 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71696 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71697 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71698 GIR_RootConstrainSelectedInstOperands,
71699 // GIR_Coverage, 3004,
71700 GIR_EraseRootFromParent_Done,
71701 // Label 4074: @193561
71702 GIM_Try, /*On fail goto*//*Label 4075*/ GIMT_Encode4(193603), // Rule ID 3005 //
71703 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71704 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adclb),
71705 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
71706 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
71707 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
71708 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
71709 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71710 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1060:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (ADCLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
71711 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADCLB_ZZZ_D),
71712 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
71713 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71714 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71715 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71716 GIR_RootConstrainSelectedInstOperands,
71717 // GIR_Coverage, 3005,
71718 GIR_EraseRootFromParent_Done,
71719 // Label 4075: @193603
71720 GIM_Try, /*On fail goto*//*Label 4076*/ GIMT_Encode4(193645), // Rule ID 3015 //
71721 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71722 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addhnt),
71723 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
71724 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
71725 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
71726 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
71727 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71728 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1067:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (ADDHNT_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
71729 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNT_ZZZ_B),
71730 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71731 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71732 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71733 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71734 GIR_RootConstrainSelectedInstOperands,
71735 // GIR_Coverage, 3015,
71736 GIR_EraseRootFromParent_Done,
71737 // Label 4076: @193645
71738 GIM_Try, /*On fail goto*//*Label 4077*/ GIMT_Encode4(193687), // Rule ID 3016 //
71739 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71740 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addhnt),
71741 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
71742 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
71743 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
71744 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
71745 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71746 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1067:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (ADDHNT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
71747 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNT_ZZZ_H),
71748 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71749 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71750 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71751 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71752 GIR_RootConstrainSelectedInstOperands,
71753 // GIR_Coverage, 3016,
71754 GIR_EraseRootFromParent_Done,
71755 // Label 4077: @193687
71756 GIM_Try, /*On fail goto*//*Label 4078*/ GIMT_Encode4(193729), // Rule ID 3017 //
71757 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71758 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addhnt),
71759 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
71760 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
71761 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
71762 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
71763 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71764 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1067:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (ADDHNT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
71765 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNT_ZZZ_S),
71766 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71767 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71768 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71769 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71770 GIR_RootConstrainSelectedInstOperands,
71771 // GIR_Coverage, 3017,
71772 GIR_EraseRootFromParent_Done,
71773 // Label 4078: @193729
71774 GIM_Try, /*On fail goto*//*Label 4079*/ GIMT_Encode4(193771), // Rule ID 3034 //
71775 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
71776 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
71777 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
71778 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
71779 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
71780 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
71781 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71782 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1126:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (CLS_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
71783 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_B),
71784 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71785 GIR_RootToRootCopy, /*OpIdx*/2, // Op3
71786 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
71787 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
71788 GIR_RootConstrainSelectedInstOperands,
71789 // GIR_Coverage, 3034,
71790 GIR_EraseRootFromParent_Done,
71791 // Label 4079: @193771
71792 GIM_Try, /*On fail goto*//*Label 4080*/ GIMT_Encode4(193813), // Rule ID 3035 //
71793 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
71794 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
71795 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
71796 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
71797 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
71798 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
71799 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71800 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1126:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (CLS_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
71801 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_H),
71802 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71803 GIR_RootToRootCopy, /*OpIdx*/2, // Op3
71804 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
71805 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
71806 GIR_RootConstrainSelectedInstOperands,
71807 // GIR_Coverage, 3035,
71808 GIR_EraseRootFromParent_Done,
71809 // Label 4080: @193813
71810 GIM_Try, /*On fail goto*//*Label 4081*/ GIMT_Encode4(193855), // Rule ID 3036 //
71811 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
71812 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
71813 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
71814 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
71815 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
71816 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
71817 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71818 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1126:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (CLS_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
71819 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_S),
71820 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71821 GIR_RootToRootCopy, /*OpIdx*/2, // Op3
71822 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
71823 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
71824 GIR_RootConstrainSelectedInstOperands,
71825 // GIR_Coverage, 3036,
71826 GIR_EraseRootFromParent_Done,
71827 // Label 4081: @193855
71828 GIM_Try, /*On fail goto*//*Label 4082*/ GIMT_Encode4(193897), // Rule ID 3037 //
71829 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
71830 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
71831 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
71832 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
71833 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
71834 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
71835 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71836 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1126:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (CLS_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
71837 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_D),
71838 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
71839 GIR_RootToRootCopy, /*OpIdx*/2, // Op3
71840 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
71841 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
71842 GIR_RootConstrainSelectedInstOperands,
71843 // GIR_Coverage, 3037,
71844 GIR_EraseRootFromParent_Done,
71845 // Label 4082: @193897
71846 GIM_Try, /*On fail goto*//*Label 4083*/ GIMT_Encode4(193939), // Rule ID 3072 //
71847 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71848 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor3),
71849 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
71850 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
71851 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
71852 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
71853 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71854 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1167:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (EOR3_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
71855 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
71856 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
71857 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71858 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71859 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71860 GIR_RootConstrainSelectedInstOperands,
71861 // GIR_Coverage, 3072,
71862 GIR_EraseRootFromParent_Done,
71863 // Label 4083: @193939
71864 GIM_Try, /*On fail goto*//*Label 4084*/ GIMT_Encode4(193981), // Rule ID 3074 //
71865 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71866 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor3),
71867 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
71868 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
71869 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
71870 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
71871 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71872 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1167:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (EOR3_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
71873 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
71874 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
71875 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71876 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71877 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71878 GIR_RootConstrainSelectedInstOperands,
71879 // GIR_Coverage, 3074,
71880 GIR_EraseRootFromParent_Done,
71881 // Label 4084: @193981
71882 GIM_Try, /*On fail goto*//*Label 4085*/ GIMT_Encode4(194023), // Rule ID 3076 //
71883 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71884 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor3),
71885 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
71886 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
71887 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
71888 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
71889 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71890 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1167:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (EOR3_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
71891 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
71892 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
71893 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71894 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71895 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71896 GIR_RootConstrainSelectedInstOperands,
71897 // GIR_Coverage, 3076,
71898 GIR_EraseRootFromParent_Done,
71899 // Label 4085: @194023
71900 GIM_Try, /*On fail goto*//*Label 4086*/ GIMT_Encode4(194065), // Rule ID 3078 //
71901 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
71902 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor3),
71903 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
71904 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
71905 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
71906 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
71907 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
71908 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1167:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (EOR3_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
71909 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
71910 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
71911 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71912 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71913 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71914 GIR_RootConstrainSelectedInstOperands,
71915 // GIR_Coverage, 3078,
71916 GIR_EraseRootFromParent_Done,
71917 // Label 4086: @194065
71918 GIM_Try, /*On fail goto*//*Label 4087*/ GIMT_Encode4(194110), // Rule ID 3103 //
71919 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
71920 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpeq_wide),
71921 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
71922 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
71923 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
71924 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
71925 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
71926 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1131:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPEQ_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
71927 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_WIDE_PPzZZ_B),
71928 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
71929 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71930 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71931 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71932 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
71933 GIR_RootConstrainSelectedInstOperands,
71934 // GIR_Coverage, 3103,
71935 GIR_EraseRootFromParent_Done,
71936 // Label 4087: @194110
71937 GIM_Try, /*On fail goto*//*Label 4088*/ GIMT_Encode4(194155), // Rule ID 3104 //
71938 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
71939 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpeq_wide),
71940 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
71941 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
71942 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
71943 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
71944 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
71945 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1131:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPEQ_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
71946 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_WIDE_PPzZZ_H),
71947 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
71948 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71949 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71950 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71951 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
71952 GIR_RootConstrainSelectedInstOperands,
71953 // GIR_Coverage, 3104,
71954 GIR_EraseRootFromParent_Done,
71955 // Label 4088: @194155
71956 GIM_Try, /*On fail goto*//*Label 4089*/ GIMT_Encode4(194200), // Rule ID 3105 //
71957 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
71958 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpeq_wide),
71959 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
71960 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
71961 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
71962 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
71963 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
71964 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1131:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPEQ_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
71965 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_WIDE_PPzZZ_S),
71966 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
71967 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71968 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71969 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71970 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
71971 GIR_RootConstrainSelectedInstOperands,
71972 // GIR_Coverage, 3105,
71973 GIR_EraseRootFromParent_Done,
71974 // Label 4089: @194200
71975 GIM_Try, /*On fail goto*//*Label 4090*/ GIMT_Encode4(194245), // Rule ID 3106 //
71976 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
71977 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpge_wide),
71978 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
71979 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
71980 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
71981 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
71982 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
71983 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1133:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPGE_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
71984 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPGE_WIDE_PPzZZ_B),
71985 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
71986 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
71987 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
71988 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
71989 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
71990 GIR_RootConstrainSelectedInstOperands,
71991 // GIR_Coverage, 3106,
71992 GIR_EraseRootFromParent_Done,
71993 // Label 4090: @194245
71994 GIM_Try, /*On fail goto*//*Label 4091*/ GIMT_Encode4(194290), // Rule ID 3107 //
71995 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
71996 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpge_wide),
71997 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
71998 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
71999 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
72000 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
72001 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
72002 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1133:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPGE_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
72003 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPGE_WIDE_PPzZZ_H),
72004 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
72005 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72006 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72007 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72008 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
72009 GIR_RootConstrainSelectedInstOperands,
72010 // GIR_Coverage, 3107,
72011 GIR_EraseRootFromParent_Done,
72012 // Label 4091: @194290
72013 GIM_Try, /*On fail goto*//*Label 4092*/ GIMT_Encode4(194335), // Rule ID 3108 //
72014 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72015 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpge_wide),
72016 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
72017 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
72018 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
72019 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
72020 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
72021 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1133:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPGE_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
72022 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPGE_WIDE_PPzZZ_S),
72023 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
72024 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72025 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72026 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72027 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
72028 GIR_RootConstrainSelectedInstOperands,
72029 // GIR_Coverage, 3108,
72030 GIR_EraseRootFromParent_Done,
72031 // Label 4092: @194335
72032 GIM_Try, /*On fail goto*//*Label 4093*/ GIMT_Encode4(194377), // Rule ID 3163 //
72033 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72034 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_facge),
72035 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
72036 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
72037 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
72038 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
72039 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
72040 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1177:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FACGE_PPzZZ_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
72041 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGE_PPzZZ_H),
72042 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
72043 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72044 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72045 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72046 GIR_RootConstrainSelectedInstOperands,
72047 // GIR_Coverage, 3163,
72048 GIR_EraseRootFromParent_Done,
72049 // Label 4093: @194377
72050 GIM_Try, /*On fail goto*//*Label 4094*/ GIMT_Encode4(194419), // Rule ID 3164 //
72051 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72052 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_facge),
72053 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
72054 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
72055 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
72056 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
72057 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
72058 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1177:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FACGE_PPzZZ_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
72059 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGE_PPzZZ_S),
72060 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
72061 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72062 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72063 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72064 GIR_RootConstrainSelectedInstOperands,
72065 // GIR_Coverage, 3164,
72066 GIR_EraseRootFromParent_Done,
72067 // Label 4094: @194419
72068 GIM_Try, /*On fail goto*//*Label 4095*/ GIMT_Encode4(194461), // Rule ID 3165 //
72069 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72070 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_facge),
72071 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
72072 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
72073 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
72074 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
72075 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
72076 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1177:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FACGE_PPzZZ_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
72077 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGE_PPzZZ_D),
72078 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
72079 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72080 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72081 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72082 GIR_RootConstrainSelectedInstOperands,
72083 // GIR_Coverage, 3165,
72084 GIR_EraseRootFromParent_Done,
72085 // Label 4095: @194461
72086 GIM_Try, /*On fail goto*//*Label 4096*/ GIMT_Encode4(194503), // Rule ID 3217 //
72087 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72088 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr),
72089 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
72090 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
72091 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
72092 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
72093 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72094 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1083:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (ASR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
72095 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_ZPmZ_B),
72096 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72097 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72098 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72099 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72100 GIR_RootConstrainSelectedInstOperands,
72101 // GIR_Coverage, 3217,
72102 GIR_EraseRootFromParent_Done,
72103 // Label 4096: @194503
72104 GIM_Try, /*On fail goto*//*Label 4097*/ GIMT_Encode4(194545), // Rule ID 3218 //
72105 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72106 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr),
72107 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
72108 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
72109 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
72110 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
72111 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72112 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1083:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (ASR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
72113 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_ZPmZ_H),
72114 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72115 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72116 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72117 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72118 GIR_RootConstrainSelectedInstOperands,
72119 // GIR_Coverage, 3218,
72120 GIR_EraseRootFromParent_Done,
72121 // Label 4097: @194545
72122 GIM_Try, /*On fail goto*//*Label 4098*/ GIMT_Encode4(194587), // Rule ID 3219 //
72123 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72124 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr),
72125 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
72126 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
72127 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
72128 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
72129 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72130 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1083:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (ASR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
72131 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_ZPmZ_S),
72132 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72133 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72134 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72135 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72136 GIR_RootConstrainSelectedInstOperands,
72137 // GIR_Coverage, 3219,
72138 GIR_EraseRootFromParent_Done,
72139 // Label 4098: @194587
72140 GIM_Try, /*On fail goto*//*Label 4099*/ GIMT_Encode4(194629), // Rule ID 3220 //
72141 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72142 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr),
72143 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
72144 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
72145 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
72146 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
72147 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72148 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1083:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (ASR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
72149 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_ZPmZ_D),
72150 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72151 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72152 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72153 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72154 GIR_RootConstrainSelectedInstOperands,
72155 // GIR_Coverage, 3220,
72156 GIR_EraseRootFromParent_Done,
72157 // Label 4099: @194629
72158 GIM_Try, /*On fail goto*//*Label 4100*/ GIMT_Encode4(194671), // Rule ID 3229 //
72159 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72160 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr_wide),
72161 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
72162 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
72163 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
72164 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
72165 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72166 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1085:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (ASR_WIDE_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
72167 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_WIDE_ZPmZ_B),
72168 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72169 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72170 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72171 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72172 GIR_RootConstrainSelectedInstOperands,
72173 // GIR_Coverage, 3229,
72174 GIR_EraseRootFromParent_Done,
72175 // Label 4100: @194671
72176 GIM_Try, /*On fail goto*//*Label 4101*/ GIMT_Encode4(194713), // Rule ID 3230 //
72177 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72178 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr_wide),
72179 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
72180 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
72181 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
72182 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
72183 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72184 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1085:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (ASR_WIDE_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
72185 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_WIDE_ZPmZ_H),
72186 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72187 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72188 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72189 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72190 GIR_RootConstrainSelectedInstOperands,
72191 // GIR_Coverage, 3230,
72192 GIR_EraseRootFromParent_Done,
72193 // Label 4101: @194713
72194 GIM_Try, /*On fail goto*//*Label 4102*/ GIMT_Encode4(194755), // Rule ID 3231 //
72195 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72196 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr_wide),
72197 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
72198 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
72199 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
72200 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
72201 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72202 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1085:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (ASR_WIDE_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
72203 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_WIDE_ZPmZ_S),
72204 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72205 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72206 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72207 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72208 GIR_RootConstrainSelectedInstOperands,
72209 // GIR_Coverage, 3231,
72210 GIR_EraseRootFromParent_Done,
72211 // Label 4102: @194755
72212 GIM_Try, /*On fail goto*//*Label 4103*/ GIMT_Encode4(194797), // Rule ID 3271 //
72213 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72214 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
72215 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
72216 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
72217 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
72218 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
72219 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72220 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1122:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (CLASTA_ZPZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
72221 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_B),
72222 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72223 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72224 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72225 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72226 GIR_RootConstrainSelectedInstOperands,
72227 // GIR_Coverage, 3271,
72228 GIR_EraseRootFromParent_Done,
72229 // Label 4103: @194797
72230 GIM_Try, /*On fail goto*//*Label 4104*/ GIMT_Encode4(194839), // Rule ID 3272 //
72231 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72232 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
72233 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
72234 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
72235 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
72236 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
72237 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72238 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1122:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (CLASTA_ZPZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
72239 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_H),
72240 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72241 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72242 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72243 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72244 GIR_RootConstrainSelectedInstOperands,
72245 // GIR_Coverage, 3272,
72246 GIR_EraseRootFromParent_Done,
72247 // Label 4104: @194839
72248 GIM_Try, /*On fail goto*//*Label 4105*/ GIMT_Encode4(194881), // Rule ID 3273 //
72249 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72250 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
72251 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
72252 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
72253 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
72254 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
72255 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72256 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1122:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (CLASTA_ZPZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
72257 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_S),
72258 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72259 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72260 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72261 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72262 GIR_RootConstrainSelectedInstOperands,
72263 // GIR_Coverage, 3273,
72264 GIR_EraseRootFromParent_Done,
72265 // Label 4105: @194881
72266 GIM_Try, /*On fail goto*//*Label 4106*/ GIMT_Encode4(194923), // Rule ID 3274 //
72267 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72268 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
72269 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
72270 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
72271 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
72272 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
72273 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72274 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1122:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CLASTA_ZPZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
72275 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_D),
72276 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72277 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72278 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72279 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72280 GIR_RootConstrainSelectedInstOperands,
72281 // GIR_Coverage, 3274,
72282 GIR_EraseRootFromParent_Done,
72283 // Label 4106: @194923
72284 GIM_Try, /*On fail goto*//*Label 4107*/ GIMT_Encode4(194965), // Rule ID 3275 //
72285 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72286 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
72287 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
72288 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
72289 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
72290 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
72291 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72292 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1122:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (CLASTA_ZPZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
72293 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_H),
72294 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72295 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72296 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72297 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72298 GIR_RootConstrainSelectedInstOperands,
72299 // GIR_Coverage, 3275,
72300 GIR_EraseRootFromParent_Done,
72301 // Label 4107: @194965
72302 GIM_Try, /*On fail goto*//*Label 4108*/ GIMT_Encode4(195007), // Rule ID 3276 //
72303 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72304 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
72305 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
72306 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
72307 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
72308 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
72309 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72310 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1122:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (CLASTA_ZPZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
72311 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_S),
72312 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72313 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72314 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72315 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72316 GIR_RootConstrainSelectedInstOperands,
72317 // GIR_Coverage, 3276,
72318 GIR_EraseRootFromParent_Done,
72319 // Label 4108: @195007
72320 GIM_Try, /*On fail goto*//*Label 4109*/ GIMT_Encode4(195049), // Rule ID 3277 //
72321 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72322 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
72323 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
72324 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
72325 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
72326 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
72327 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72328 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1122:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (CLASTA_ZPZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
72329 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_D),
72330 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72331 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72332 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72333 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72334 GIR_RootConstrainSelectedInstOperands,
72335 // GIR_Coverage, 3277,
72336 GIR_EraseRootFromParent_Done,
72337 // Label 4109: @195049
72338 GIM_Try, /*On fail goto*//*Label 4110*/ GIMT_Encode4(195091), // Rule ID 3278 //
72339 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72340 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
72341 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
72342 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
72343 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
72344 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
72345 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72346 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1122:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3) => (CLASTA_ZPZ_H:{ *:[nxv8bf16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3)
72347 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_H),
72348 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72349 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72350 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72351 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72352 GIR_RootConstrainSelectedInstOperands,
72353 // GIR_Coverage, 3278,
72354 GIR_EraseRootFromParent_Done,
72355 // Label 4110: @195091
72356 GIM_Try, /*On fail goto*//*Label 4111*/ GIMT_Encode4(195133), // Rule ID 3359 //
72357 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72358 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brkpa_z),
72359 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
72360 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
72361 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
72362 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
72363 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
72364 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1114:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3) => (BRKPA_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
72365 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKPA_PPzPP),
72366 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
72367 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72368 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72369 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72370 GIR_RootConstrainSelectedInstOperands,
72371 // GIR_Coverage, 3359,
72372 GIR_EraseRootFromParent_Done,
72373 // Label 4111: @195133
72374 GIM_Try, /*On fail goto*//*Label 4112*/ GIMT_Encode4(195175), // Rule ID 3360 //
72375 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72376 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brkn_z),
72377 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
72378 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
72379 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
72380 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
72381 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
72382 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1113:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3) => (BRKN_PPzP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
72383 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKN_PPzP),
72384 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pdm]
72385 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72386 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72387 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72388 GIR_RootConstrainSelectedInstOperands,
72389 // GIR_Coverage, 3360,
72390 GIR_EraseRootFromParent_Done,
72391 // Label 4112: @195175
72392 GIM_Try, /*On fail goto*//*Label 4113*/ GIMT_Encode4(195217), // Rule ID 3361 //
72393 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72394 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brka),
72395 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
72396 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
72397 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
72398 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
72399 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
72400 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1109:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3) => (BRKA_PPmP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
72401 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKA_PPmP),
72402 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
72403 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72404 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72405 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72406 GIR_RootConstrainSelectedInstOperands,
72407 // GIR_Coverage, 3361,
72408 GIR_EraseRootFromParent_Done,
72409 // Label 4113: @195217
72410 GIM_Try, /*On fail goto*//*Label 4114*/ GIMT_Encode4(195262), // Rule ID 3363 //
72411 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
72412 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_match),
72413 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
72414 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
72415 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
72416 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
72417 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
72418 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1381:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (MATCH_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
72419 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MATCH_PPzZZ_B),
72420 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
72421 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72422 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72423 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72424 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
72425 GIR_RootConstrainSelectedInstOperands,
72426 // GIR_Coverage, 3363,
72427 GIR_EraseRootFromParent_Done,
72428 // Label 4114: @195262
72429 GIM_Try, /*On fail goto*//*Label 4115*/ GIMT_Encode4(195307), // Rule ID 3364 //
72430 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
72431 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_match),
72432 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
72433 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
72434 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
72435 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
72436 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
72437 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1381:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (MATCH_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
72438 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MATCH_PPzZZ_H),
72439 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
72440 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72441 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72442 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72443 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
72444 GIR_RootConstrainSelectedInstOperands,
72445 // GIR_Coverage, 3364,
72446 GIR_EraseRootFromParent_Done,
72447 // Label 4115: @195307
72448 GIM_Try, /*On fail goto*//*Label 4116*/ GIMT_Encode4(195349), // Rule ID 3365 //
72449 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
72450 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_histcnt),
72451 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
72452 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
72453 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
72454 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
72455 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72456 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1329:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (HISTCNT_ZPzZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
72457 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HISTCNT_ZPzZZ_S),
72458 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
72459 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72460 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72461 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72462 GIR_RootConstrainSelectedInstOperands,
72463 // GIR_Coverage, 3365,
72464 GIR_EraseRootFromParent_Done,
72465 // Label 4116: @195349
72466 GIM_Try, /*On fail goto*//*Label 4117*/ GIMT_Encode4(195391), // Rule ID 3366 //
72467 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
72468 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_histcnt),
72469 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
72470 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
72471 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
72472 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
72473 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72474 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1329:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (HISTCNT_ZPzZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
72475 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HISTCNT_ZPzZZ_D),
72476 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
72477 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72478 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72479 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72480 GIR_RootConstrainSelectedInstOperands,
72481 // GIR_Coverage, 3366,
72482 GIR_EraseRootFromParent_Done,
72483 // Label 4117: @195391
72484 GIM_Try, /*On fail goto*//*Label 4118*/ GIMT_Encode4(195433), // Rule ID 3370 //
72485 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasSVEorSME),
72486 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bfdot),
72487 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
72488 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
72489 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
72490 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
72491 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72492 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1094:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3) => (BFDOT_ZZZ:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3)
72493 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFDOT_ZZZ),
72494 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
72495 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72496 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72497 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72498 GIR_RootConstrainSelectedInstOperands,
72499 // GIR_Coverage, 3370,
72500 GIR_EraseRootFromParent_Done,
72501 // Label 4118: @195433
72502 GIM_Try, /*On fail goto*//*Label 4119*/ GIMT_Encode4(195475), // Rule ID 3372 //
72503 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasSVE),
72504 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bfmmla),
72505 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
72506 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
72507 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
72508 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
72509 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72510 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1104:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3) => (BFMMLA_ZZZ:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3)
72511 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMMLA_ZZZ),
72512 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
72513 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72514 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72515 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72516 GIR_RootConstrainSelectedInstOperands,
72517 // GIR_Coverage, 3372,
72518 GIR_EraseRootFromParent_Done,
72519 // Label 4119: @195475
72520 GIM_Try, /*On fail goto*//*Label 4120*/ GIMT_Encode4(195517), // Rule ID 3373 //
72521 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasSVEorSME),
72522 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvt_bf16f32),
72523 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
72524 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
72525 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
72526 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
72527 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72528 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1197:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (BFCVT_ZPmZ:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
72529 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVT_ZPmZ),
72530 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
72531 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72532 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72533 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72534 GIR_RootConstrainSelectedInstOperands,
72535 // GIR_Coverage, 3373,
72536 GIR_EraseRootFromParent_Done,
72537 // Label 4120: @195517
72538 GIM_Try, /*On fail goto*//*Label 4121*/ GIMT_Encode4(195559), // Rule ID 3374 //
72539 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8_HasSVE),
72540 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smmla),
72541 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
72542 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
72543 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
72544 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
72545 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72546 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1532:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SMMLA_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
72547 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMMLA_ZZZ),
72548 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
72549 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72550 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72551 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72552 GIR_RootConstrainSelectedInstOperands,
72553 // GIR_Coverage, 3374,
72554 GIR_EraseRootFromParent_Done,
72555 // Label 4121: @195559
72556 GIM_Try, /*On fail goto*//*Label 4122*/ GIMT_Encode4(195601), // Rule ID 3375 //
72557 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8_HasSVEorSME),
72558 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usdot),
72559 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
72560 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
72561 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
72562 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
72563 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72564 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1837:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (USDOT_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
72565 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USDOT_ZZZ),
72566 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
72567 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72568 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72569 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72570 GIR_RootConstrainSelectedInstOperands,
72571 // GIR_Coverage, 3375,
72572 GIR_EraseRootFromParent_Done,
72573 // Label 4122: @195601
72574 GIM_Try, /*On fail goto*//*Label 4123*/ GIMT_Encode4(195643), // Rule ID 3377 //
72575 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP32_HasSVE),
72576 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmmla),
72577 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
72578 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
72579 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
72580 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
72581 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72582 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1287:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FMMLA_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
72583 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMMLA_ZZZ_S),
72584 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
72585 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72586 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72587 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72588 GIR_RootConstrainSelectedInstOperands,
72589 // GIR_Coverage, 3377,
72590 GIR_EraseRootFromParent_Done,
72591 // Label 4123: @195643
72592 GIM_Try, /*On fail goto*//*Label 4124*/ GIMT_Encode4(195685), // Rule ID 3416 //
72593 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2),
72594 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fclamp),
72595 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
72596 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
72597 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
72598 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
72599 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72600 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1186:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FCLAMP_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
72601 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCLAMP_ZZZ_H),
72602 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
72603 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72604 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72605 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72606 GIR_RootConstrainSelectedInstOperands,
72607 // GIR_Coverage, 3416,
72608 GIR_EraseRootFromParent_Done,
72609 // Label 4124: @195685
72610 GIM_Try, /*On fail goto*//*Label 4125*/ GIMT_Encode4(195727), // Rule ID 3418 //
72611 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2),
72612 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fclamp),
72613 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
72614 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
72615 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
72616 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
72617 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72618 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1186:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FCLAMP_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
72619 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCLAMP_ZZZ_S),
72620 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
72621 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72622 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72623 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72624 GIR_RootConstrainSelectedInstOperands,
72625 // GIR_Coverage, 3418,
72626 GIR_EraseRootFromParent_Done,
72627 // Label 4125: @195727
72628 GIM_Try, /*On fail goto*//*Label 4126*/ GIMT_Encode4(195769), // Rule ID 3420 //
72629 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2),
72630 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fclamp),
72631 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
72632 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
72633 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
72634 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
72635 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72636 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1186:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FCLAMP_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
72637 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCLAMP_ZZZ_D),
72638 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
72639 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72640 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72641 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72642 GIR_RootConstrainSelectedInstOperands,
72643 // GIR_Coverage, 3420,
72644 GIR_EraseRootFromParent_Done,
72645 // Label 4126: @195769
72646 GIM_Try, /*On fail goto*//*Label 4127*/ GIMT_Encode4(195811), // Rule ID 3422 //
72647 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasB16B16_HasSVE2orSME2),
72648 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fclamp),
72649 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
72650 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
72651 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
72652 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
72653 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72654 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1186:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3) => (BFCLAMP_ZZZ:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3)
72655 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCLAMP_ZZZ),
72656 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
72657 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72658 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72659 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72660 GIR_RootConstrainSelectedInstOperands,
72661 // GIR_Coverage, 3422,
72662 GIR_EraseRootFromParent_Done,
72663 // Label 4127: @195811
72664 GIM_Try, /*On fail goto*//*Label 4128*/ GIMT_Encode4(195853), // Rule ID 3424 //
72665 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2),
72666 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdot_x2),
72667 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
72668 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
72669 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
72670 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
72671 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72672 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1493:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SDOT_ZZZ_HtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
72673 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDOT_ZZZ_HtoS),
72674 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
72675 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72676 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72677 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72678 GIR_RootConstrainSelectedInstOperands,
72679 // GIR_Coverage, 3424,
72680 GIR_EraseRootFromParent_Done,
72681 // Label 4128: @195853
72682 GIM_Try, /*On fail goto*//*Label 4129*/ GIMT_Encode4(195895), // Rule ID 3529 //
72683 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME),
72684 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sclamp),
72685 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
72686 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
72687 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
72688 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
72689 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72690 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1477:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SCLAMP_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
72691 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCLAMP_ZZZ_B),
72692 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
72693 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72694 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72695 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72696 GIR_RootConstrainSelectedInstOperands,
72697 // GIR_Coverage, 3529,
72698 GIR_EraseRootFromParent_Done,
72699 // Label 4129: @195895
72700 GIM_Try, /*On fail goto*//*Label 4130*/ GIMT_Encode4(195937), // Rule ID 3531 //
72701 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME),
72702 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sclamp),
72703 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
72704 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
72705 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
72706 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
72707 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72708 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1477:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SCLAMP_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
72709 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCLAMP_ZZZ_H),
72710 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
72711 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72712 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72713 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72714 GIR_RootConstrainSelectedInstOperands,
72715 // GIR_Coverage, 3531,
72716 GIR_EraseRootFromParent_Done,
72717 // Label 4130: @195937
72718 GIM_Try, /*On fail goto*//*Label 4131*/ GIMT_Encode4(195979), // Rule ID 3533 //
72719 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME),
72720 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sclamp),
72721 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
72722 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
72723 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
72724 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
72725 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72726 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1477:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SCLAMP_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
72727 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCLAMP_ZZZ_S),
72728 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
72729 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72730 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72731 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72732 GIR_RootConstrainSelectedInstOperands,
72733 // GIR_Coverage, 3533,
72734 GIR_EraseRootFromParent_Done,
72735 // Label 4131: @195979
72736 GIM_Try, /*On fail goto*//*Label 4132*/ GIMT_Encode4(196021), // Rule ID 3535 //
72737 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME),
72738 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sclamp),
72739 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
72740 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
72741 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
72742 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
72743 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72744 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1477:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SCLAMP_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
72745 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCLAMP_ZZZ_D),
72746 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
72747 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72748 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72749 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72750 GIR_RootConstrainSelectedInstOperands,
72751 // GIR_Coverage, 3535,
72752 GIR_EraseRootFromParent_Done,
72753 // Label 4132: @196021
72754 GIM_Try, /*On fail goto*//*Label 4133*/ GIMT_Encode4(196063), // Rule ID 7152 //
72755 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72756 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subr),
72757 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
72758 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
72759 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
72760 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
72761 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72762 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1686:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SUBR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
72763 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_B),
72764 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72765 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72766 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72767 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72768 GIR_RootConstrainSelectedInstOperands,
72769 // GIR_Coverage, 7152,
72770 GIR_EraseRootFromParent_Done,
72771 // Label 4133: @196063
72772 GIM_Try, /*On fail goto*//*Label 4134*/ GIMT_Encode4(196105), // Rule ID 7153 //
72773 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72774 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subr),
72775 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
72776 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
72777 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
72778 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
72779 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72780 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1686:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SUBR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
72781 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_H),
72782 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72783 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72784 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72785 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72786 GIR_RootConstrainSelectedInstOperands,
72787 // GIR_Coverage, 7153,
72788 GIR_EraseRootFromParent_Done,
72789 // Label 4134: @196105
72790 GIM_Try, /*On fail goto*//*Label 4135*/ GIMT_Encode4(196147), // Rule ID 7154 //
72791 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72792 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subr),
72793 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
72794 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
72795 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
72796 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
72797 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72798 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1686:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SUBR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
72799 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_S),
72800 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72801 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72802 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72803 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72804 GIR_RootConstrainSelectedInstOperands,
72805 // GIR_Coverage, 7154,
72806 GIR_EraseRootFromParent_Done,
72807 // Label 4135: @196147
72808 GIM_Try, /*On fail goto*//*Label 4136*/ GIMT_Encode4(196189), // Rule ID 7155 //
72809 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72810 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subr),
72811 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
72812 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
72813 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
72814 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
72815 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72816 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1686:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SUBR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
72817 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_D),
72818 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72819 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72820 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72821 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72822 GIR_RootConstrainSelectedInstOperands,
72823 // GIR_Coverage, 7155,
72824 GIR_EraseRootFromParent_Done,
72825 // Label 4136: @196189
72826 GIM_Try, /*On fail goto*//*Label 4137*/ GIMT_Encode4(196231), // Rule ID 7172 //
72827 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72828 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic),
72829 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
72830 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
72831 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
72832 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
72833 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72834 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1106:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (BIC_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
72835 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZPmZ_B),
72836 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72837 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72838 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72839 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72840 GIR_RootConstrainSelectedInstOperands,
72841 // GIR_Coverage, 7172,
72842 GIR_EraseRootFromParent_Done,
72843 // Label 4137: @196231
72844 GIM_Try, /*On fail goto*//*Label 4138*/ GIMT_Encode4(196273), // Rule ID 7173 //
72845 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72846 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic),
72847 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
72848 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
72849 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
72850 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
72851 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72852 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1106:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (BIC_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
72853 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZPmZ_H),
72854 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72855 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72856 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72857 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72858 GIR_RootConstrainSelectedInstOperands,
72859 // GIR_Coverage, 7173,
72860 GIR_EraseRootFromParent_Done,
72861 // Label 4138: @196273
72862 GIM_Try, /*On fail goto*//*Label 4139*/ GIMT_Encode4(196315), // Rule ID 7174 //
72863 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72864 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic),
72865 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
72866 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
72867 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
72868 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
72869 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72870 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1106:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (BIC_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
72871 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZPmZ_S),
72872 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72873 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72874 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72875 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72876 GIR_RootConstrainSelectedInstOperands,
72877 // GIR_Coverage, 7174,
72878 GIR_EraseRootFromParent_Done,
72879 // Label 4139: @196315
72880 GIM_Try, /*On fail goto*//*Label 4140*/ GIMT_Encode4(196357), // Rule ID 7175 //
72881 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72882 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic),
72883 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
72884 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
72885 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
72886 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
72887 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72888 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1106:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (BIC_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
72889 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZPmZ_D),
72890 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72891 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72892 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72893 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72894 GIR_RootConstrainSelectedInstOperands,
72895 // GIR_Coverage, 7175,
72896 GIR_EraseRootFromParent_Done,
72897 // Label 4140: @196357
72898 GIM_Try, /*On fail goto*//*Label 4141*/ GIMT_Encode4(196399), // Rule ID 7288 //
72899 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72900 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smulh),
72901 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
72902 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
72903 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
72904 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
72905 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72906 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1533:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SMULH_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
72907 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULH_ZPmZ_B),
72908 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72909 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72910 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72911 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72912 GIR_RootConstrainSelectedInstOperands,
72913 // GIR_Coverage, 7288,
72914 GIR_EraseRootFromParent_Done,
72915 // Label 4141: @196399
72916 GIM_Try, /*On fail goto*//*Label 4142*/ GIMT_Encode4(196441), // Rule ID 7289 //
72917 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72918 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smulh),
72919 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
72920 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
72921 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
72922 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
72923 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72924 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1533:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SMULH_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
72925 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULH_ZPmZ_H),
72926 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72927 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72928 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72929 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72930 GIR_RootConstrainSelectedInstOperands,
72931 // GIR_Coverage, 7289,
72932 GIR_EraseRootFromParent_Done,
72933 // Label 4142: @196441
72934 GIM_Try, /*On fail goto*//*Label 4143*/ GIMT_Encode4(196483), // Rule ID 7290 //
72935 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72936 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smulh),
72937 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
72938 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
72939 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
72940 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
72941 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72942 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1533:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SMULH_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
72943 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULH_ZPmZ_S),
72944 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72945 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72946 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72947 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72948 GIR_RootConstrainSelectedInstOperands,
72949 // GIR_Coverage, 7290,
72950 GIR_EraseRootFromParent_Done,
72951 // Label 4143: @196483
72952 GIM_Try, /*On fail goto*//*Label 4144*/ GIMT_Encode4(196525), // Rule ID 7291 //
72953 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72954 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smulh),
72955 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
72956 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
72957 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
72958 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
72959 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72960 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1533:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SMULH_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
72961 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULH_ZPmZ_D),
72962 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72963 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72964 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72965 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72966 GIR_RootConstrainSelectedInstOperands,
72967 // GIR_Coverage, 7291,
72968 GIR_EraseRootFromParent_Done,
72969 // Label 4144: @196525
72970 GIM_Try, /*On fail goto*//*Label 4145*/ GIMT_Encode4(196567), // Rule ID 7292 //
72971 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72972 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umulh),
72973 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
72974 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
72975 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
72976 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
72977 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72978 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1771:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UMULH_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
72979 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULH_ZPmZ_B),
72980 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72981 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
72982 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
72983 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
72984 GIR_RootConstrainSelectedInstOperands,
72985 // GIR_Coverage, 7292,
72986 GIR_EraseRootFromParent_Done,
72987 // Label 4145: @196567
72988 GIM_Try, /*On fail goto*//*Label 4146*/ GIMT_Encode4(196609), // Rule ID 7293 //
72989 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
72990 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umulh),
72991 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
72992 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
72993 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
72994 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
72995 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
72996 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1771:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UMULH_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
72997 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULH_ZPmZ_H),
72998 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
72999 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73000 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73001 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73002 GIR_RootConstrainSelectedInstOperands,
73003 // GIR_Coverage, 7293,
73004 GIR_EraseRootFromParent_Done,
73005 // Label 4146: @196609
73006 GIM_Try, /*On fail goto*//*Label 4147*/ GIMT_Encode4(196651), // Rule ID 7294 //
73007 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73008 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umulh),
73009 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
73010 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
73011 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
73012 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
73013 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73014 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1771:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UMULH_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
73015 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULH_ZPmZ_S),
73016 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73017 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73018 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73019 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73020 GIR_RootConstrainSelectedInstOperands,
73021 // GIR_Coverage, 7294,
73022 GIR_EraseRootFromParent_Done,
73023 // Label 4147: @196651
73024 GIM_Try, /*On fail goto*//*Label 4148*/ GIMT_Encode4(196693), // Rule ID 7295 //
73025 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73026 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umulh),
73027 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
73028 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
73029 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
73030 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
73031 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73032 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1771:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (UMULH_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
73033 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULH_ZPmZ_D),
73034 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73035 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73036 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73037 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73038 GIR_RootConstrainSelectedInstOperands,
73039 // GIR_Coverage, 7295,
73040 GIR_EraseRootFromParent_Done,
73041 // Label 4148: @196693
73042 GIM_Try, /*On fail goto*//*Label 4149*/ GIMT_Encode4(196735), // Rule ID 7304 //
73043 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73044 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udiv),
73045 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
73046 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
73047 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
73048 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
73049 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73050 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1734:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UDIV_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
73051 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDIV_ZPmZ_S),
73052 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73053 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73054 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73055 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73056 GIR_RootConstrainSelectedInstOperands,
73057 // GIR_Coverage, 7304,
73058 GIR_EraseRootFromParent_Done,
73059 // Label 4149: @196735
73060 GIM_Try, /*On fail goto*//*Label 4150*/ GIMT_Encode4(196777), // Rule ID 7305 //
73061 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73062 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udiv),
73063 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
73064 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
73065 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
73066 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
73067 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73068 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1734:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (UDIV_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
73069 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDIV_ZPmZ_D),
73070 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73071 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73072 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73073 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73074 GIR_RootConstrainSelectedInstOperands,
73075 // GIR_Coverage, 7305,
73076 GIR_EraseRootFromParent_Done,
73077 // Label 4150: @196777
73078 GIM_Try, /*On fail goto*//*Label 4151*/ GIMT_Encode4(196819), // Rule ID 7306 //
73079 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73080 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdivr),
73081 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
73082 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
73083 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
73084 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
73085 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73086 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1489:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SDIVR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
73087 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDIVR_ZPmZ_S),
73088 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73089 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73090 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73091 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73092 GIR_RootConstrainSelectedInstOperands,
73093 // GIR_Coverage, 7306,
73094 GIR_EraseRootFromParent_Done,
73095 // Label 4151: @196819
73096 GIM_Try, /*On fail goto*//*Label 4152*/ GIMT_Encode4(196861), // Rule ID 7307 //
73097 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73098 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdivr),
73099 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
73100 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
73101 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
73102 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
73103 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73104 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1489:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SDIVR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
73105 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDIVR_ZPmZ_D),
73106 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73107 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73108 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73109 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73110 GIR_RootConstrainSelectedInstOperands,
73111 // GIR_Coverage, 7307,
73112 GIR_EraseRootFromParent_Done,
73113 // Label 4152: @196861
73114 GIM_Try, /*On fail goto*//*Label 4153*/ GIMT_Encode4(196903), // Rule ID 7308 //
73115 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73116 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udivr),
73117 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
73118 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
73119 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
73120 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
73121 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73122 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1736:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UDIVR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
73123 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDIVR_ZPmZ_S),
73124 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73125 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73126 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73127 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73128 GIR_RootConstrainSelectedInstOperands,
73129 // GIR_Coverage, 7308,
73130 GIR_EraseRootFromParent_Done,
73131 // Label 4153: @196903
73132 GIM_Try, /*On fail goto*//*Label 4154*/ GIMT_Encode4(196945), // Rule ID 7309 //
73133 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73134 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udivr),
73135 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
73136 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
73137 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
73138 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
73139 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73140 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1736:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (UDIVR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
73141 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDIVR_ZPmZ_D),
73142 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73143 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73144 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73145 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73146 GIR_RootConstrainSelectedInstOperands,
73147 // GIR_Coverage, 7309,
73148 GIR_EraseRootFromParent_Done,
73149 // Label 4154: @196945
73150 GIM_Try, /*On fail goto*//*Label 4155*/ GIMT_Encode4(196987), // Rule ID 7394 //
73151 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73152 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
73153 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
73154 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
73155 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
73156 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
73157 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73158 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1146:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (CNOT_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
73159 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_B),
73160 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73161 GIR_RootToRootCopy, /*OpIdx*/2, // Op3
73162 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
73163 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
73164 GIR_RootConstrainSelectedInstOperands,
73165 // GIR_Coverage, 7394,
73166 GIR_EraseRootFromParent_Done,
73167 // Label 4155: @196987
73168 GIM_Try, /*On fail goto*//*Label 4156*/ GIMT_Encode4(197029), // Rule ID 7395 //
73169 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73170 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
73171 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
73172 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
73173 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
73174 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
73175 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73176 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1146:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (CNOT_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
73177 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_H),
73178 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73179 GIR_RootToRootCopy, /*OpIdx*/2, // Op3
73180 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
73181 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
73182 GIR_RootConstrainSelectedInstOperands,
73183 // GIR_Coverage, 7395,
73184 GIR_EraseRootFromParent_Done,
73185 // Label 4156: @197029
73186 GIM_Try, /*On fail goto*//*Label 4157*/ GIMT_Encode4(197071), // Rule ID 7396 //
73187 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73188 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
73189 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
73190 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
73191 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
73192 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
73193 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73194 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1146:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (CNOT_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
73195 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_S),
73196 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73197 GIR_RootToRootCopy, /*OpIdx*/2, // Op3
73198 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
73199 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
73200 GIR_RootConstrainSelectedInstOperands,
73201 // GIR_Coverage, 7396,
73202 GIR_EraseRootFromParent_Done,
73203 // Label 4157: @197071
73204 GIM_Try, /*On fail goto*//*Label 4158*/ GIMT_Encode4(197113), // Rule ID 7397 //
73205 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73206 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
73207 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
73208 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
73209 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
73210 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
73211 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73212 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1146:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (CNOT_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
73213 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_D),
73214 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73215 GIR_RootToRootCopy, /*OpIdx*/2, // Op3
73216 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
73217 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
73218 GIR_RootConstrainSelectedInstOperands,
73219 // GIR_Coverage, 7397,
73220 GIR_EraseRootFromParent_Done,
73221 // Label 4158: @197113
73222 GIM_Try, /*On fail goto*//*Label 4159*/ GIMT_Encode4(197155), // Rule ID 7406 //
73223 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73224 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
73225 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
73226 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
73227 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
73228 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
73229 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73230 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1397:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (NOT_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
73231 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_B),
73232 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73233 GIR_RootToRootCopy, /*OpIdx*/2, // Op3
73234 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
73235 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
73236 GIR_RootConstrainSelectedInstOperands,
73237 // GIR_Coverage, 7406,
73238 GIR_EraseRootFromParent_Done,
73239 // Label 4159: @197155
73240 GIM_Try, /*On fail goto*//*Label 4160*/ GIMT_Encode4(197197), // Rule ID 7407 //
73241 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73242 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
73243 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
73244 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
73245 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
73246 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
73247 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73248 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1397:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (NOT_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
73249 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_H),
73250 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73251 GIR_RootToRootCopy, /*OpIdx*/2, // Op3
73252 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
73253 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
73254 GIR_RootConstrainSelectedInstOperands,
73255 // GIR_Coverage, 7407,
73256 GIR_EraseRootFromParent_Done,
73257 // Label 4160: @197197
73258 GIM_Try, /*On fail goto*//*Label 4161*/ GIMT_Encode4(197239), // Rule ID 7408 //
73259 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73260 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
73261 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
73262 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
73263 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
73264 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
73265 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73266 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1397:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (NOT_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
73267 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_S),
73268 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73269 GIR_RootToRootCopy, /*OpIdx*/2, // Op3
73270 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
73271 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
73272 GIR_RootConstrainSelectedInstOperands,
73273 // GIR_Coverage, 7408,
73274 GIR_EraseRootFromParent_Done,
73275 // Label 4161: @197239
73276 GIM_Try, /*On fail goto*//*Label 4162*/ GIMT_Encode4(197281), // Rule ID 7409 //
73277 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73278 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
73279 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
73280 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
73281 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
73282 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
73283 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73284 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1397:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (NOT_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
73285 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_D),
73286 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73287 GIR_RootToRootCopy, /*OpIdx*/2, // Op3
73288 GIR_RootToRootCopy, /*OpIdx*/3, // Op1
73289 GIR_RootToRootCopy, /*OpIdx*/4, // Op2
73290 GIR_RootConstrainSelectedInstOperands,
73291 // GIR_Coverage, 7409,
73292 GIR_EraseRootFromParent_Done,
73293 // Label 4162: @197281
73294 GIM_Try, /*On fail goto*//*Label 4163*/ GIMT_Encode4(197323), // Rule ID 7488 //
73295 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73296 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabd),
73297 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
73298 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
73299 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
73300 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
73301 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73302 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1464:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SABD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
73303 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABD_ZPmZ_B),
73304 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73305 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73306 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73307 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73308 GIR_RootConstrainSelectedInstOperands,
73309 // GIR_Coverage, 7488,
73310 GIR_EraseRootFromParent_Done,
73311 // Label 4163: @197323
73312 GIM_Try, /*On fail goto*//*Label 4164*/ GIMT_Encode4(197365), // Rule ID 7489 //
73313 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73314 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabd),
73315 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
73316 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
73317 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
73318 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
73319 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73320 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1464:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SABD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
73321 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABD_ZPmZ_H),
73322 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73323 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73324 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73325 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73326 GIR_RootConstrainSelectedInstOperands,
73327 // GIR_Coverage, 7489,
73328 GIR_EraseRootFromParent_Done,
73329 // Label 4164: @197365
73330 GIM_Try, /*On fail goto*//*Label 4165*/ GIMT_Encode4(197407), // Rule ID 7490 //
73331 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73332 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabd),
73333 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
73334 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
73335 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
73336 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
73337 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73338 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1464:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SABD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
73339 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABD_ZPmZ_S),
73340 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73341 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73342 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73343 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73344 GIR_RootConstrainSelectedInstOperands,
73345 // GIR_Coverage, 7490,
73346 GIR_EraseRootFromParent_Done,
73347 // Label 4165: @197407
73348 GIM_Try, /*On fail goto*//*Label 4166*/ GIMT_Encode4(197449), // Rule ID 7491 //
73349 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73350 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabd),
73351 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
73352 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
73353 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
73354 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
73355 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73356 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1464:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SABD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
73357 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABD_ZPmZ_D),
73358 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73359 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73360 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73361 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73362 GIR_RootConstrainSelectedInstOperands,
73363 // GIR_Coverage, 7491,
73364 GIR_EraseRootFromParent_Done,
73365 // Label 4166: @197449
73366 GIM_Try, /*On fail goto*//*Label 4167*/ GIMT_Encode4(197491), // Rule ID 7492 //
73367 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73368 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabd),
73369 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
73370 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
73371 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
73372 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
73373 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73374 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1714:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UABD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
73375 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABD_ZPmZ_B),
73376 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73377 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73378 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73379 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73380 GIR_RootConstrainSelectedInstOperands,
73381 // GIR_Coverage, 7492,
73382 GIR_EraseRootFromParent_Done,
73383 // Label 4167: @197491
73384 GIM_Try, /*On fail goto*//*Label 4168*/ GIMT_Encode4(197533), // Rule ID 7493 //
73385 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73386 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabd),
73387 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
73388 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
73389 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
73390 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
73391 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73392 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1714:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UABD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
73393 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABD_ZPmZ_H),
73394 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73395 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73396 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73397 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73398 GIR_RootConstrainSelectedInstOperands,
73399 // GIR_Coverage, 7493,
73400 GIR_EraseRootFromParent_Done,
73401 // Label 4168: @197533
73402 GIM_Try, /*On fail goto*//*Label 4169*/ GIMT_Encode4(197575), // Rule ID 7494 //
73403 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73404 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabd),
73405 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
73406 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
73407 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
73408 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
73409 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73410 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1714:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UABD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
73411 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABD_ZPmZ_S),
73412 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73413 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73414 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73415 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73416 GIR_RootConstrainSelectedInstOperands,
73417 // GIR_Coverage, 7494,
73418 GIR_EraseRootFromParent_Done,
73419 // Label 4169: @197575
73420 GIM_Try, /*On fail goto*//*Label 4170*/ GIMT_Encode4(197617), // Rule ID 7495 //
73421 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73422 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabd),
73423 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
73424 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
73425 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
73426 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
73427 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73428 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1714:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (UABD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
73429 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABD_ZPmZ_D),
73430 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73431 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73432 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73433 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73434 GIR_RootConstrainSelectedInstOperands,
73435 // GIR_Coverage, 7495,
73436 GIR_EraseRootFromParent_Done,
73437 // Label 4170: @197617
73438 GIM_Try, /*On fail goto*//*Label 4171*/ GIMT_Encode4(197659), // Rule ID 7691 //
73439 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73440 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
73441 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
73442 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
73443 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
73444 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
73445 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73446 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1323:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FSUB_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
73447 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmZ_H),
73448 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73449 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73450 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73451 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73452 GIR_RootConstrainSelectedInstOperands,
73453 // GIR_Coverage, 7691,
73454 GIR_EraseRootFromParent_Done,
73455 // Label 4171: @197659
73456 GIM_Try, /*On fail goto*//*Label 4172*/ GIMT_Encode4(197701), // Rule ID 7695 //
73457 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73458 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
73459 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
73460 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
73461 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
73462 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
73463 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73464 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1323:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FSUB_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
73465 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmZ_S),
73466 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73467 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73468 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73469 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73470 GIR_RootConstrainSelectedInstOperands,
73471 // GIR_Coverage, 7695,
73472 GIR_EraseRootFromParent_Done,
73473 // Label 4172: @197701
73474 GIM_Try, /*On fail goto*//*Label 4173*/ GIMT_Encode4(197743), // Rule ID 7699 //
73475 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73476 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
73477 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
73478 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
73479 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
73480 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
73481 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73482 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1323:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FSUB_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
73483 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmZ_D),
73484 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73485 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73486 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73487 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73488 GIR_RootConstrainSelectedInstOperands,
73489 // GIR_Coverage, 7699,
73490 GIR_EraseRootFromParent_Done,
73491 // Label 4173: @197743
73492 GIM_Try, /*On fail goto*//*Label 4174*/ GIMT_Encode4(197785), // Rule ID 7709 //
73493 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73494 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
73495 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
73496 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
73497 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
73498 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
73499 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73500 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1325:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FSUBR_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
73501 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmZ_H),
73502 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73503 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73504 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73505 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73506 GIR_RootConstrainSelectedInstOperands,
73507 // GIR_Coverage, 7709,
73508 GIR_EraseRootFromParent_Done,
73509 // Label 4174: @197785
73510 GIM_Try, /*On fail goto*//*Label 4175*/ GIMT_Encode4(197827), // Rule ID 7710 //
73511 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73512 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
73513 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
73514 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
73515 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
73516 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
73517 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73518 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1325:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FSUBR_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
73519 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmZ_S),
73520 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73521 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73522 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73523 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73524 GIR_RootConstrainSelectedInstOperands,
73525 // GIR_Coverage, 7710,
73526 GIR_EraseRootFromParent_Done,
73527 // Label 4175: @197827
73528 GIM_Try, /*On fail goto*//*Label 4176*/ GIMT_Encode4(197869), // Rule ID 7711 //
73529 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73530 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
73531 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
73532 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
73533 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
73534 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
73535 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73536 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1325:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FSUBR_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
73537 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmZ_D),
73538 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73539 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73540 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73541 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73542 GIR_RootConstrainSelectedInstOperands,
73543 // GIR_Coverage, 7711,
73544 GIR_EraseRootFromParent_Done,
73545 // Label 4176: @197869
73546 GIM_Try, /*On fail goto*//*Label 4177*/ GIMT_Encode4(197911), // Rule ID 7748 //
73547 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73548 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd),
73549 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
73550 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
73551 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
73552 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
73553 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73554 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1174:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FABD_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
73555 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPmZ_H),
73556 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73557 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73558 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73559 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73560 GIR_RootConstrainSelectedInstOperands,
73561 // GIR_Coverage, 7748,
73562 GIR_EraseRootFromParent_Done,
73563 // Label 4177: @197911
73564 GIM_Try, /*On fail goto*//*Label 4178*/ GIMT_Encode4(197953), // Rule ID 7749 //
73565 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73566 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd),
73567 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
73568 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
73569 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
73570 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
73571 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73572 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1174:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FABD_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
73573 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPmZ_S),
73574 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73575 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73576 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73577 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73578 GIR_RootConstrainSelectedInstOperands,
73579 // GIR_Coverage, 7749,
73580 GIR_EraseRootFromParent_Done,
73581 // Label 4178: @197953
73582 GIM_Try, /*On fail goto*//*Label 4179*/ GIMT_Encode4(197995), // Rule ID 7750 //
73583 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73584 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd),
73585 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
73586 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
73587 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
73588 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
73589 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73590 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1174:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FABD_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
73591 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPmZ_D),
73592 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73593 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73594 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73595 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73596 GIR_RootConstrainSelectedInstOperands,
73597 // GIR_Coverage, 7750,
73598 GIR_EraseRootFromParent_Done,
73599 // Label 4179: @197995
73600 GIM_Try, /*On fail goto*//*Label 4180*/ GIMT_Encode4(198037), // Rule ID 7751 //
73601 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73602 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx),
73603 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
73604 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
73605 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
73606 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
73607 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73608 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1292:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FMULX_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
73609 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPmZ_H),
73610 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73611 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73612 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73613 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73614 GIR_RootConstrainSelectedInstOperands,
73615 // GIR_Coverage, 7751,
73616 GIR_EraseRootFromParent_Done,
73617 // Label 4180: @198037
73618 GIM_Try, /*On fail goto*//*Label 4181*/ GIMT_Encode4(198079), // Rule ID 7752 //
73619 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73620 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx),
73621 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
73622 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
73623 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
73624 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
73625 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73626 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1292:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FMULX_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
73627 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPmZ_S),
73628 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73629 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73630 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73631 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73632 GIR_RootConstrainSelectedInstOperands,
73633 // GIR_Coverage, 7752,
73634 GIR_EraseRootFromParent_Done,
73635 // Label 4181: @198079
73636 GIM_Try, /*On fail goto*//*Label 4182*/ GIMT_Encode4(198121), // Rule ID 7753 //
73637 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73638 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx),
73639 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
73640 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
73641 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
73642 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
73643 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73644 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1292:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FMULX_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
73645 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPmZ_D),
73646 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73647 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73648 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73649 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73650 GIR_RootConstrainSelectedInstOperands,
73651 // GIR_Coverage, 7753,
73652 GIR_EraseRootFromParent_Done,
73653 // Label 4182: @198121
73654 GIM_Try, /*On fail goto*//*Label 4183*/ GIMT_Encode4(198163), // Rule ID 7754 //
73655 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73656 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdivr),
73657 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
73658 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
73659 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
73660 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
73661 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73662 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1231:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FDIVR_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
73663 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDIVR_ZPmZ_H),
73664 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73665 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73666 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73667 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73668 GIR_RootConstrainSelectedInstOperands,
73669 // GIR_Coverage, 7754,
73670 GIR_EraseRootFromParent_Done,
73671 // Label 4183: @198163
73672 GIM_Try, /*On fail goto*//*Label 4184*/ GIMT_Encode4(198205), // Rule ID 7755 //
73673 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73674 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdivr),
73675 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
73676 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
73677 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
73678 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
73679 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73680 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1231:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FDIVR_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
73681 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDIVR_ZPmZ_S),
73682 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73683 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73684 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73685 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73686 GIR_RootConstrainSelectedInstOperands,
73687 // GIR_Coverage, 7755,
73688 GIR_EraseRootFromParent_Done,
73689 // Label 4184: @198205
73690 GIM_Try, /*On fail goto*//*Label 4185*/ GIMT_Encode4(198247), // Rule ID 7756 //
73691 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73692 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdivr),
73693 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
73694 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
73695 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
73696 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
73697 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73698 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1231:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FDIVR_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
73699 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDIVR_ZPmZ_D),
73700 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73701 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73702 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73703 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73704 GIR_RootConstrainSelectedInstOperands,
73705 // GIR_Coverage, 7756,
73706 GIR_EraseRootFromParent_Done,
73707 // Label 4185: @198247
73708 GIM_Try, /*On fail goto*//*Label 4186*/ GIMT_Encode4(198289), // Rule ID 7757 //
73709 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73710 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdiv),
73711 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
73712 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
73713 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
73714 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
73715 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73716 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1229:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FDIV_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
73717 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDIV_ZPmZ_H),
73718 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73719 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73720 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73721 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73722 GIR_RootConstrainSelectedInstOperands,
73723 // GIR_Coverage, 7757,
73724 GIR_EraseRootFromParent_Done,
73725 // Label 4186: @198289
73726 GIM_Try, /*On fail goto*//*Label 4187*/ GIMT_Encode4(198331), // Rule ID 7758 //
73727 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73728 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdiv),
73729 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
73730 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
73731 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
73732 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
73733 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73734 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1229:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FDIV_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
73735 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDIV_ZPmZ_S),
73736 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73737 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73738 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73739 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73740 GIR_RootConstrainSelectedInstOperands,
73741 // GIR_Coverage, 7758,
73742 GIR_EraseRootFromParent_Done,
73743 // Label 4187: @198331
73744 GIM_Try, /*On fail goto*//*Label 4188*/ GIMT_Encode4(198373), // Rule ID 7759 //
73745 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73746 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdiv),
73747 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
73748 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
73749 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
73750 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
73751 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73752 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1229:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FDIV_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
73753 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDIV_ZPmZ_D),
73754 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
73755 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73756 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73757 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73758 GIR_RootConstrainSelectedInstOperands,
73759 // GIR_Coverage, 7759,
73760 GIR_EraseRootFromParent_Done,
73761 // Label 4188: @198373
73762 GIM_Try, /*On fail goto*//*Label 4189*/ GIMT_Encode4(198415), // Rule ID 7796 //
73763 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73764 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd_u),
73765 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
73766 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
73767 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
73768 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
73769 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73770 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1175:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FABD_ZPZZ_H_UNDEF:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
73771 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPZZ_H_UNDEF),
73772 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73773 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73774 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73775 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73776 GIR_RootConstrainSelectedInstOperands,
73777 // GIR_Coverage, 7796,
73778 GIR_EraseRootFromParent_Done,
73779 // Label 4189: @198415
73780 GIM_Try, /*On fail goto*//*Label 4190*/ GIMT_Encode4(198457), // Rule ID 7798 //
73781 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73782 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd_u),
73783 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
73784 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
73785 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
73786 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
73787 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73788 // (intrinsic_wo_chain:{ *:[nxv4f16] } 1175:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3) => (FABD_ZPZZ_H_UNDEF:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3)
73789 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPZZ_H_UNDEF),
73790 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73791 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73792 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73793 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73794 GIR_RootConstrainSelectedInstOperands,
73795 // GIR_Coverage, 7798,
73796 GIR_EraseRootFromParent_Done,
73797 // Label 4190: @198457
73798 GIM_Try, /*On fail goto*//*Label 4191*/ GIMT_Encode4(198499), // Rule ID 7800 //
73799 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73800 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd_u),
73801 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
73802 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
73803 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
73804 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
73805 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73806 // (intrinsic_wo_chain:{ *:[nxv2f16] } 1175:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3) => (FABD_ZPZZ_H_UNDEF:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3)
73807 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPZZ_H_UNDEF),
73808 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73809 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73810 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73811 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73812 GIR_RootConstrainSelectedInstOperands,
73813 // GIR_Coverage, 7800,
73814 GIR_EraseRootFromParent_Done,
73815 // Label 4191: @198499
73816 GIM_Try, /*On fail goto*//*Label 4192*/ GIMT_Encode4(198541), // Rule ID 7802 //
73817 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73818 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd_u),
73819 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
73820 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
73821 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
73822 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
73823 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73824 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1175:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FABD_ZPZZ_S_UNDEF:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
73825 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPZZ_S_UNDEF),
73826 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73827 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73828 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73829 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73830 GIR_RootConstrainSelectedInstOperands,
73831 // GIR_Coverage, 7802,
73832 GIR_EraseRootFromParent_Done,
73833 // Label 4192: @198541
73834 GIM_Try, /*On fail goto*//*Label 4193*/ GIMT_Encode4(198583), // Rule ID 7804 //
73835 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73836 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd_u),
73837 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
73838 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
73839 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
73840 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
73841 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73842 // (intrinsic_wo_chain:{ *:[nxv2f32] } 1175:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3) => (FABD_ZPZZ_S_UNDEF:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3)
73843 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPZZ_S_UNDEF),
73844 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73845 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73846 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73847 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73848 GIR_RootConstrainSelectedInstOperands,
73849 // GIR_Coverage, 7804,
73850 GIR_EraseRootFromParent_Done,
73851 // Label 4193: @198583
73852 GIM_Try, /*On fail goto*//*Label 4194*/ GIMT_Encode4(198625), // Rule ID 7806 //
73853 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73854 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd_u),
73855 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
73856 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
73857 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
73858 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
73859 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73860 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1175:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FABD_ZPZZ_D_UNDEF:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
73861 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPZZ_D_UNDEF),
73862 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73863 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73864 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73865 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73866 GIR_RootConstrainSelectedInstOperands,
73867 // GIR_Coverage, 7806,
73868 GIR_EraseRootFromParent_Done,
73869 // Label 4194: @198625
73870 GIM_Try, /*On fail goto*//*Label 4195*/ GIMT_Encode4(198667), // Rule ID 7808 //
73871 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73872 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx_u),
73873 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
73874 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
73875 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
73876 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
73877 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73878 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1293:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FMULX_ZPZZ_H_UNDEF:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
73879 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPZZ_H_UNDEF),
73880 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73881 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73882 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73883 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73884 GIR_RootConstrainSelectedInstOperands,
73885 // GIR_Coverage, 7808,
73886 GIR_EraseRootFromParent_Done,
73887 // Label 4195: @198667
73888 GIM_Try, /*On fail goto*//*Label 4196*/ GIMT_Encode4(198709), // Rule ID 7809 //
73889 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73890 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx_u),
73891 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
73892 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
73893 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
73894 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
73895 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73896 // (intrinsic_wo_chain:{ *:[nxv4f16] } 1293:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3) => (FMULX_ZPZZ_H_UNDEF:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3)
73897 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPZZ_H_UNDEF),
73898 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73899 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73900 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73901 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73902 GIR_RootConstrainSelectedInstOperands,
73903 // GIR_Coverage, 7809,
73904 GIR_EraseRootFromParent_Done,
73905 // Label 4196: @198709
73906 GIM_Try, /*On fail goto*//*Label 4197*/ GIMT_Encode4(198751), // Rule ID 7810 //
73907 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73908 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx_u),
73909 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
73910 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
73911 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
73912 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
73913 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73914 // (intrinsic_wo_chain:{ *:[nxv2f16] } 1293:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3) => (FMULX_ZPZZ_H_UNDEF:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3)
73915 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPZZ_H_UNDEF),
73916 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73917 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73918 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73919 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73920 GIR_RootConstrainSelectedInstOperands,
73921 // GIR_Coverage, 7810,
73922 GIR_EraseRootFromParent_Done,
73923 // Label 4197: @198751
73924 GIM_Try, /*On fail goto*//*Label 4198*/ GIMT_Encode4(198793), // Rule ID 7811 //
73925 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73926 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx_u),
73927 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
73928 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
73929 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
73930 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
73931 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73932 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1293:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FMULX_ZPZZ_S_UNDEF:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
73933 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPZZ_S_UNDEF),
73934 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73935 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73936 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73937 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73938 GIR_RootConstrainSelectedInstOperands,
73939 // GIR_Coverage, 7811,
73940 GIR_EraseRootFromParent_Done,
73941 // Label 4198: @198793
73942 GIM_Try, /*On fail goto*//*Label 4199*/ GIMT_Encode4(198835), // Rule ID 7812 //
73943 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73944 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx_u),
73945 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
73946 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
73947 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
73948 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
73949 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73950 // (intrinsic_wo_chain:{ *:[nxv2f32] } 1293:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3) => (FMULX_ZPZZ_S_UNDEF:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3)
73951 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPZZ_S_UNDEF),
73952 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73953 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73954 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73955 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73956 GIR_RootConstrainSelectedInstOperands,
73957 // GIR_Coverage, 7812,
73958 GIR_EraseRootFromParent_Done,
73959 // Label 4199: @198835
73960 GIM_Try, /*On fail goto*//*Label 4200*/ GIMT_Encode4(198877), // Rule ID 7813 //
73961 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73962 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx_u),
73963 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
73964 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
73965 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
73966 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
73967 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
73968 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1293:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FMULX_ZPZZ_D_UNDEF:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
73969 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPZZ_D_UNDEF),
73970 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
73971 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73972 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73973 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73974 GIR_RootConstrainSelectedInstOperands,
73975 // GIR_Coverage, 7813,
73976 GIR_EraseRootFromParent_Done,
73977 // Label 4200: @198877
73978 GIM_Try, /*On fail goto*//*Label 4201*/ GIMT_Encode4(198919), // Rule ID 8056 //
73979 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73980 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brkpb_z),
73981 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
73982 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
73983 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
73984 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
73985 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
73986 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1115:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3) => (BRKPB_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
73987 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKPB_PPzPP),
73988 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
73989 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
73990 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
73991 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
73992 GIR_RootConstrainSelectedInstOperands,
73993 // GIR_Coverage, 8056,
73994 GIR_EraseRootFromParent_Done,
73995 // Label 4201: @198919
73996 GIM_Try, /*On fail goto*//*Label 4202*/ GIMT_Encode4(198961), // Rule ID 8058 //
73997 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
73998 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brkb),
73999 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
74000 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
74001 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
74002 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
74003 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
74004 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1111:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3) => (BRKB_PPmP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
74005 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKB_PPmP),
74006 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74007 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74008 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74009 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74010 GIR_RootConstrainSelectedInstOperands,
74011 // GIR_Coverage, 8058,
74012 GIR_EraseRootFromParent_Done,
74013 // Label 4202: @198961
74014 GIM_Try, /*On fail goto*//*Label 4203*/ GIMT_Encode4(199003), // Rule ID 8059 //
74015 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74016 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic_z),
74017 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
74018 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
74019 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
74020 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
74021 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74022 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1108:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3) => (BIC_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
74023 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
74024 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74025 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74026 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74027 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74028 GIR_RootConstrainSelectedInstOperands,
74029 // GIR_Coverage, 8059,
74030 GIR_EraseRootFromParent_Done,
74031 // Label 4203: @199003
74032 GIM_Try, /*On fail goto*//*Label 4204*/ GIMT_Encode4(199045), // Rule ID 8060 //
74033 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74034 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic_z),
74035 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
74036 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
74037 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
74038 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
74039 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74040 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1108:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3) => (BIC_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
74041 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
74042 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74043 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74044 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74045 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74046 GIR_RootConstrainSelectedInstOperands,
74047 // GIR_Coverage, 8060,
74048 GIR_EraseRootFromParent_Done,
74049 // Label 4204: @199045
74050 GIM_Try, /*On fail goto*//*Label 4205*/ GIMT_Encode4(199087), // Rule ID 8061 //
74051 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74052 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic_z),
74053 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
74054 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
74055 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
74056 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
74057 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74058 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1108:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3) => (BIC_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
74059 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
74060 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74061 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74062 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74063 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74064 GIR_RootConstrainSelectedInstOperands,
74065 // GIR_Coverage, 8061,
74066 GIR_EraseRootFromParent_Done,
74067 // Label 4205: @199087
74068 GIM_Try, /*On fail goto*//*Label 4206*/ GIMT_Encode4(199129), // Rule ID 8062 //
74069 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74070 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic_z),
74071 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
74072 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
74073 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
74074 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
74075 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74076 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1108:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3) => (BIC_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
74077 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
74078 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74079 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74080 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74081 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74082 GIR_RootConstrainSelectedInstOperands,
74083 // GIR_Coverage, 8062,
74084 GIR_EraseRootFromParent_Done,
74085 // Label 4206: @199129
74086 GIM_Try, /*On fail goto*//*Label 4207*/ GIMT_Encode4(199171), // Rule ID 8063 //
74087 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74088 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic_z),
74089 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
74090 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
74091 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
74092 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
74093 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74094 // (intrinsic_wo_chain:{ *:[nxv1i1] } 1108:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3) => (BIC_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
74095 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
74096 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74097 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74098 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74099 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74100 GIR_RootConstrainSelectedInstOperands,
74101 // GIR_Coverage, 8063,
74102 GIR_EraseRootFromParent_Done,
74103 // Label 4207: @199171
74104 GIM_Try, /*On fail goto*//*Label 4208*/ GIMT_Encode4(199213), // Rule ID 8084 //
74105 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74106 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor_z),
74107 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
74108 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
74109 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
74110 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
74111 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74112 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1166:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3) => (EOR_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
74113 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
74114 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74115 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74116 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74117 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74118 GIR_RootConstrainSelectedInstOperands,
74119 // GIR_Coverage, 8084,
74120 GIR_EraseRootFromParent_Done,
74121 // Label 4208: @199213
74122 GIM_Try, /*On fail goto*//*Label 4209*/ GIMT_Encode4(199255), // Rule ID 8085 //
74123 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74124 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor_z),
74125 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
74126 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
74127 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
74128 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
74129 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74130 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1166:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3) => (EOR_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
74131 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
74132 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74133 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74134 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74135 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74136 GIR_RootConstrainSelectedInstOperands,
74137 // GIR_Coverage, 8085,
74138 GIR_EraseRootFromParent_Done,
74139 // Label 4209: @199255
74140 GIM_Try, /*On fail goto*//*Label 4210*/ GIMT_Encode4(199297), // Rule ID 8086 //
74141 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74142 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor_z),
74143 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
74144 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
74145 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
74146 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
74147 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74148 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1166:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3) => (EOR_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
74149 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
74150 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74151 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74152 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74153 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74154 GIR_RootConstrainSelectedInstOperands,
74155 // GIR_Coverage, 8086,
74156 GIR_EraseRootFromParent_Done,
74157 // Label 4210: @199297
74158 GIM_Try, /*On fail goto*//*Label 4211*/ GIMT_Encode4(199339), // Rule ID 8087 //
74159 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74160 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor_z),
74161 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
74162 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
74163 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
74164 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
74165 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74166 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1166:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3) => (EOR_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
74167 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
74168 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74169 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74170 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74171 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74172 GIR_RootConstrainSelectedInstOperands,
74173 // GIR_Coverage, 8087,
74174 GIR_EraseRootFromParent_Done,
74175 // Label 4211: @199339
74176 GIM_Try, /*On fail goto*//*Label 4212*/ GIMT_Encode4(199381), // Rule ID 8088 //
74177 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74178 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor_z),
74179 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
74180 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
74181 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
74182 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
74183 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74184 // (intrinsic_wo_chain:{ *:[nxv1i1] } 1166:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3) => (EOR_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
74185 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
74186 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74187 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74188 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74189 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74190 GIR_RootConstrainSelectedInstOperands,
74191 // GIR_Coverage, 8088,
74192 GIR_EraseRootFromParent_Done,
74193 // Label 4212: @199381
74194 GIM_Try, /*On fail goto*//*Label 4213*/ GIMT_Encode4(199423), // Rule ID 8104 //
74195 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74196 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orr_z),
74197 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
74198 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
74199 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
74200 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
74201 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74202 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1402:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3) => (ORR_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
74203 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORR_PPzPP),
74204 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74205 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74206 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74207 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74208 GIR_RootConstrainSelectedInstOperands,
74209 // GIR_Coverage, 8104,
74210 GIR_EraseRootFromParent_Done,
74211 // Label 4213: @199423
74212 GIM_Try, /*On fail goto*//*Label 4214*/ GIMT_Encode4(199465), // Rule ID 8105 //
74213 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74214 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orr_z),
74215 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
74216 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
74217 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
74218 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
74219 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74220 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1402:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3) => (ORR_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
74221 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORR_PPzPP),
74222 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74223 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74224 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74225 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74226 GIR_RootConstrainSelectedInstOperands,
74227 // GIR_Coverage, 8105,
74228 GIR_EraseRootFromParent_Done,
74229 // Label 4214: @199465
74230 GIM_Try, /*On fail goto*//*Label 4215*/ GIMT_Encode4(199507), // Rule ID 8106 //
74231 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74232 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orr_z),
74233 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
74234 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
74235 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
74236 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
74237 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74238 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1402:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3) => (ORR_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
74239 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORR_PPzPP),
74240 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74241 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74242 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74243 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74244 GIR_RootConstrainSelectedInstOperands,
74245 // GIR_Coverage, 8106,
74246 GIR_EraseRootFromParent_Done,
74247 // Label 4215: @199507
74248 GIM_Try, /*On fail goto*//*Label 4216*/ GIMT_Encode4(199549), // Rule ID 8107 //
74249 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74250 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orr_z),
74251 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
74252 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
74253 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
74254 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
74255 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74256 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1402:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3) => (ORR_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
74257 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORR_PPzPP),
74258 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74259 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74260 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74261 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74262 GIR_RootConstrainSelectedInstOperands,
74263 // GIR_Coverage, 8107,
74264 GIR_EraseRootFromParent_Done,
74265 // Label 4216: @199549
74266 GIM_Try, /*On fail goto*//*Label 4217*/ GIMT_Encode4(199591), // Rule ID 8108 //
74267 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74268 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orr_z),
74269 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
74270 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
74271 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
74272 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
74273 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74274 // (intrinsic_wo_chain:{ *:[nxv1i1] } 1402:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3) => (ORR_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
74275 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORR_PPzPP),
74276 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74277 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74278 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74279 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74280 GIR_RootConstrainSelectedInstOperands,
74281 // GIR_Coverage, 8108,
74282 GIR_EraseRootFromParent_Done,
74283 // Label 4217: @199591
74284 GIM_Try, /*On fail goto*//*Label 4218*/ GIMT_Encode4(199633), // Rule ID 8109 //
74285 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74286 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orn_z),
74287 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
74288 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
74289 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
74290 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
74291 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74292 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1398:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3) => (ORN_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
74293 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORN_PPzPP),
74294 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74295 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74296 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74297 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74298 GIR_RootConstrainSelectedInstOperands,
74299 // GIR_Coverage, 8109,
74300 GIR_EraseRootFromParent_Done,
74301 // Label 4218: @199633
74302 GIM_Try, /*On fail goto*//*Label 4219*/ GIMT_Encode4(199675), // Rule ID 8110 //
74303 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74304 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orn_z),
74305 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
74306 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
74307 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
74308 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
74309 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74310 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1398:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3) => (ORN_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
74311 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORN_PPzPP),
74312 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74313 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74314 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74315 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74316 GIR_RootConstrainSelectedInstOperands,
74317 // GIR_Coverage, 8110,
74318 GIR_EraseRootFromParent_Done,
74319 // Label 4219: @199675
74320 GIM_Try, /*On fail goto*//*Label 4220*/ GIMT_Encode4(199717), // Rule ID 8111 //
74321 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74322 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orn_z),
74323 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
74324 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
74325 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
74326 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
74327 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74328 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1398:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3) => (ORN_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
74329 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORN_PPzPP),
74330 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74331 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74332 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74333 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74334 GIR_RootConstrainSelectedInstOperands,
74335 // GIR_Coverage, 8111,
74336 GIR_EraseRootFromParent_Done,
74337 // Label 4220: @199717
74338 GIM_Try, /*On fail goto*//*Label 4221*/ GIMT_Encode4(199759), // Rule ID 8112 //
74339 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74340 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orn_z),
74341 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
74342 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
74343 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
74344 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
74345 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74346 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1398:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3) => (ORN_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
74347 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORN_PPzPP),
74348 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74349 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74350 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74351 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74352 GIR_RootConstrainSelectedInstOperands,
74353 // GIR_Coverage, 8112,
74354 GIR_EraseRootFromParent_Done,
74355 // Label 4221: @199759
74356 GIM_Try, /*On fail goto*//*Label 4222*/ GIMT_Encode4(199801), // Rule ID 8113 //
74357 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74358 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orn_z),
74359 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
74360 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
74361 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
74362 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
74363 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74364 // (intrinsic_wo_chain:{ *:[nxv1i1] } 1398:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3) => (ORN_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
74365 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORN_PPzPP),
74366 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74367 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74368 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74369 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74370 GIR_RootConstrainSelectedInstOperands,
74371 // GIR_Coverage, 8113,
74372 GIR_EraseRootFromParent_Done,
74373 // Label 4222: @199801
74374 GIM_Try, /*On fail goto*//*Label 4223*/ GIMT_Encode4(199843), // Rule ID 8114 //
74375 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74376 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nor_z),
74377 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
74378 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
74379 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
74380 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
74381 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74382 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1396:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3) => (NOR_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
74383 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOR_PPzPP),
74384 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74385 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74386 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74387 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74388 GIR_RootConstrainSelectedInstOperands,
74389 // GIR_Coverage, 8114,
74390 GIR_EraseRootFromParent_Done,
74391 // Label 4223: @199843
74392 GIM_Try, /*On fail goto*//*Label 4224*/ GIMT_Encode4(199885), // Rule ID 8115 //
74393 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74394 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nor_z),
74395 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
74396 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
74397 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
74398 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
74399 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74400 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1396:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3) => (NOR_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
74401 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOR_PPzPP),
74402 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74403 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74404 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74405 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74406 GIR_RootConstrainSelectedInstOperands,
74407 // GIR_Coverage, 8115,
74408 GIR_EraseRootFromParent_Done,
74409 // Label 4224: @199885
74410 GIM_Try, /*On fail goto*//*Label 4225*/ GIMT_Encode4(199927), // Rule ID 8116 //
74411 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74412 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nor_z),
74413 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
74414 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
74415 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
74416 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
74417 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74418 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1396:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3) => (NOR_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
74419 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOR_PPzPP),
74420 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74421 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74422 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74423 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74424 GIR_RootConstrainSelectedInstOperands,
74425 // GIR_Coverage, 8116,
74426 GIR_EraseRootFromParent_Done,
74427 // Label 4225: @199927
74428 GIM_Try, /*On fail goto*//*Label 4226*/ GIMT_Encode4(199969), // Rule ID 8117 //
74429 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74430 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nor_z),
74431 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
74432 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
74433 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
74434 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
74435 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74436 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1396:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3) => (NOR_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
74437 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOR_PPzPP),
74438 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74439 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74440 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74441 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74442 GIR_RootConstrainSelectedInstOperands,
74443 // GIR_Coverage, 8117,
74444 GIR_EraseRootFromParent_Done,
74445 // Label 4226: @199969
74446 GIM_Try, /*On fail goto*//*Label 4227*/ GIMT_Encode4(200011), // Rule ID 8118 //
74447 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74448 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nor_z),
74449 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
74450 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
74451 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
74452 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
74453 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74454 // (intrinsic_wo_chain:{ *:[nxv1i1] } 1396:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3) => (NOR_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
74455 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOR_PPzPP),
74456 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74457 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74458 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74459 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74460 GIR_RootConstrainSelectedInstOperands,
74461 // GIR_Coverage, 8118,
74462 GIR_EraseRootFromParent_Done,
74463 // Label 4227: @200011
74464 GIM_Try, /*On fail goto*//*Label 4228*/ GIMT_Encode4(200053), // Rule ID 8119 //
74465 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74466 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nand_z),
74467 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
74468 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
74469 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
74470 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
74471 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74472 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1392:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3) => (NAND_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
74473 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NAND_PPzPP),
74474 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74475 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74476 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74477 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74478 GIR_RootConstrainSelectedInstOperands,
74479 // GIR_Coverage, 8119,
74480 GIR_EraseRootFromParent_Done,
74481 // Label 4228: @200053
74482 GIM_Try, /*On fail goto*//*Label 4229*/ GIMT_Encode4(200095), // Rule ID 8120 //
74483 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74484 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nand_z),
74485 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
74486 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
74487 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
74488 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
74489 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74490 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1392:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3) => (NAND_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
74491 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NAND_PPzPP),
74492 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74493 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74494 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74495 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74496 GIR_RootConstrainSelectedInstOperands,
74497 // GIR_Coverage, 8120,
74498 GIR_EraseRootFromParent_Done,
74499 // Label 4229: @200095
74500 GIM_Try, /*On fail goto*//*Label 4230*/ GIMT_Encode4(200137), // Rule ID 8121 //
74501 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74502 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nand_z),
74503 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
74504 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
74505 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
74506 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
74507 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74508 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1392:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3) => (NAND_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
74509 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NAND_PPzPP),
74510 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74511 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74512 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74513 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74514 GIR_RootConstrainSelectedInstOperands,
74515 // GIR_Coverage, 8121,
74516 GIR_EraseRootFromParent_Done,
74517 // Label 4230: @200137
74518 GIM_Try, /*On fail goto*//*Label 4231*/ GIMT_Encode4(200179), // Rule ID 8122 //
74519 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74520 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nand_z),
74521 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
74522 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
74523 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
74524 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
74525 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74526 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1392:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3) => (NAND_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
74527 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NAND_PPzPP),
74528 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74529 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74530 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74531 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74532 GIR_RootConstrainSelectedInstOperands,
74533 // GIR_Coverage, 8122,
74534 GIR_EraseRootFromParent_Done,
74535 // Label 4231: @200179
74536 GIM_Try, /*On fail goto*//*Label 4232*/ GIMT_Encode4(200221), // Rule ID 8123 //
74537 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74538 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nand_z),
74539 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
74540 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
74541 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
74542 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
74543 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
74544 // (intrinsic_wo_chain:{ *:[nxv1i1] } 1392:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3) => (NAND_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
74545 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NAND_PPzPP),
74546 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74547 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74548 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74549 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74550 GIR_RootConstrainSelectedInstOperands,
74551 // GIR_Coverage, 8123,
74552 GIR_EraseRootFromParent_Done,
74553 // Label 4232: @200221
74554 GIM_Try, /*On fail goto*//*Label 4233*/ GIMT_Encode4(200263), // Rule ID 8132 //
74555 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74556 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
74557 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
74558 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
74559 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
74560 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
74561 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
74562 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1124:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (CLASTB_ZPZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
74563 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_B),
74564 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
74565 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74566 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74567 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74568 GIR_RootConstrainSelectedInstOperands,
74569 // GIR_Coverage, 8132,
74570 GIR_EraseRootFromParent_Done,
74571 // Label 4233: @200263
74572 GIM_Try, /*On fail goto*//*Label 4234*/ GIMT_Encode4(200305), // Rule ID 8133 //
74573 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74574 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
74575 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
74576 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
74577 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
74578 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
74579 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
74580 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1124:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (CLASTB_ZPZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
74581 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_H),
74582 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
74583 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74584 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74585 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74586 GIR_RootConstrainSelectedInstOperands,
74587 // GIR_Coverage, 8133,
74588 GIR_EraseRootFromParent_Done,
74589 // Label 4234: @200305
74590 GIM_Try, /*On fail goto*//*Label 4235*/ GIMT_Encode4(200347), // Rule ID 8134 //
74591 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74592 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
74593 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
74594 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
74595 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
74596 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
74597 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
74598 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1124:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (CLASTB_ZPZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
74599 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_S),
74600 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
74601 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74602 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74603 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74604 GIR_RootConstrainSelectedInstOperands,
74605 // GIR_Coverage, 8134,
74606 GIR_EraseRootFromParent_Done,
74607 // Label 4235: @200347
74608 GIM_Try, /*On fail goto*//*Label 4236*/ GIMT_Encode4(200389), // Rule ID 8135 //
74609 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74610 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
74611 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
74612 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
74613 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
74614 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
74615 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
74616 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1124:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CLASTB_ZPZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
74617 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_D),
74618 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
74619 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74620 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74621 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74622 GIR_RootConstrainSelectedInstOperands,
74623 // GIR_Coverage, 8135,
74624 GIR_EraseRootFromParent_Done,
74625 // Label 4236: @200389
74626 GIM_Try, /*On fail goto*//*Label 4237*/ GIMT_Encode4(200431), // Rule ID 8136 //
74627 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74628 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
74629 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
74630 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
74631 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
74632 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
74633 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
74634 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1124:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (CLASTB_ZPZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
74635 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_H),
74636 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
74637 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74638 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74639 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74640 GIR_RootConstrainSelectedInstOperands,
74641 // GIR_Coverage, 8136,
74642 GIR_EraseRootFromParent_Done,
74643 // Label 4237: @200431
74644 GIM_Try, /*On fail goto*//*Label 4238*/ GIMT_Encode4(200473), // Rule ID 8137 //
74645 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74646 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
74647 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
74648 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
74649 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
74650 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
74651 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
74652 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1124:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (CLASTB_ZPZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
74653 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_S),
74654 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
74655 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74656 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74657 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74658 GIR_RootConstrainSelectedInstOperands,
74659 // GIR_Coverage, 8137,
74660 GIR_EraseRootFromParent_Done,
74661 // Label 4238: @200473
74662 GIM_Try, /*On fail goto*//*Label 4239*/ GIMT_Encode4(200515), // Rule ID 8138 //
74663 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74664 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
74665 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
74666 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
74667 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
74668 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
74669 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
74670 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1124:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (CLASTB_ZPZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
74671 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_D),
74672 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
74673 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74674 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74675 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74676 GIR_RootConstrainSelectedInstOperands,
74677 // GIR_Coverage, 8138,
74678 GIR_EraseRootFromParent_Done,
74679 // Label 4239: @200515
74680 GIM_Try, /*On fail goto*//*Label 4240*/ GIMT_Encode4(200557), // Rule ID 8139 //
74681 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74682 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
74683 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
74684 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
74685 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
74686 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
74687 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
74688 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1124:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3) => (CLASTB_ZPZ_H:{ *:[nxv8bf16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3)
74689 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_H),
74690 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
74691 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74692 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74693 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74694 GIR_RootConstrainSelectedInstOperands,
74695 // GIR_Coverage, 8139,
74696 GIR_EraseRootFromParent_Done,
74697 // Label 4240: @200557
74698 GIM_Try, /*On fail goto*//*Label 4241*/ GIMT_Encode4(200602), // Rule ID 8870 //
74699 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74700 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpne_wide),
74701 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
74702 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
74703 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
74704 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
74705 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
74706 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1145:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPNE_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
74707 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPNE_WIDE_PPzZZ_B),
74708 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74709 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74710 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74711 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74712 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
74713 GIR_RootConstrainSelectedInstOperands,
74714 // GIR_Coverage, 8870,
74715 GIR_EraseRootFromParent_Done,
74716 // Label 4241: @200602
74717 GIM_Try, /*On fail goto*//*Label 4242*/ GIMT_Encode4(200647), // Rule ID 8871 //
74718 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74719 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpne_wide),
74720 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
74721 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
74722 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
74723 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
74724 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
74725 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1145:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPNE_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
74726 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPNE_WIDE_PPzZZ_H),
74727 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74728 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74729 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74730 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74731 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
74732 GIR_RootConstrainSelectedInstOperands,
74733 // GIR_Coverage, 8871,
74734 GIR_EraseRootFromParent_Done,
74735 // Label 4242: @200647
74736 GIM_Try, /*On fail goto*//*Label 4243*/ GIMT_Encode4(200692), // Rule ID 8872 //
74737 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74738 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpne_wide),
74739 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
74740 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
74741 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
74742 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
74743 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
74744 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1145:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPNE_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
74745 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPNE_WIDE_PPzZZ_S),
74746 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74747 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74748 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74749 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74750 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
74751 GIR_RootConstrainSelectedInstOperands,
74752 // GIR_Coverage, 8872,
74753 GIR_EraseRootFromParent_Done,
74754 // Label 4243: @200692
74755 GIM_Try, /*On fail goto*//*Label 4244*/ GIMT_Encode4(200737), // Rule ID 8873 //
74756 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74757 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpgt_wide),
74758 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
74759 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
74760 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
74761 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
74762 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
74763 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1135:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPGT_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
74764 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPGT_WIDE_PPzZZ_B),
74765 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74766 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74767 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74768 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74769 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
74770 GIR_RootConstrainSelectedInstOperands,
74771 // GIR_Coverage, 8873,
74772 GIR_EraseRootFromParent_Done,
74773 // Label 4244: @200737
74774 GIM_Try, /*On fail goto*//*Label 4245*/ GIMT_Encode4(200782), // Rule ID 8874 //
74775 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74776 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpgt_wide),
74777 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
74778 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
74779 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
74780 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
74781 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
74782 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1135:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPGT_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
74783 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPGT_WIDE_PPzZZ_H),
74784 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74785 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74786 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74787 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74788 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
74789 GIR_RootConstrainSelectedInstOperands,
74790 // GIR_Coverage, 8874,
74791 GIR_EraseRootFromParent_Done,
74792 // Label 4245: @200782
74793 GIM_Try, /*On fail goto*//*Label 4246*/ GIMT_Encode4(200827), // Rule ID 8875 //
74794 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74795 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpgt_wide),
74796 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
74797 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
74798 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
74799 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
74800 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
74801 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1135:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPGT_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
74802 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPGT_WIDE_PPzZZ_S),
74803 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74804 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74805 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74806 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74807 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
74808 GIR_RootConstrainSelectedInstOperands,
74809 // GIR_Coverage, 8875,
74810 GIR_EraseRootFromParent_Done,
74811 // Label 4246: @200827
74812 GIM_Try, /*On fail goto*//*Label 4247*/ GIMT_Encode4(200872), // Rule ID 8876 //
74813 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74814 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmplt_wide),
74815 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
74816 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
74817 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
74818 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
74819 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
74820 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1143:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPLT_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
74821 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLT_WIDE_PPzZZ_B),
74822 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74823 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74824 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74825 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74826 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
74827 GIR_RootConstrainSelectedInstOperands,
74828 // GIR_Coverage, 8876,
74829 GIR_EraseRootFromParent_Done,
74830 // Label 4247: @200872
74831 GIM_Try, /*On fail goto*//*Label 4248*/ GIMT_Encode4(200917), // Rule ID 8877 //
74832 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74833 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmplt_wide),
74834 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
74835 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
74836 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
74837 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
74838 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
74839 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1143:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPLT_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
74840 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLT_WIDE_PPzZZ_H),
74841 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74842 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74843 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74844 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74845 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
74846 GIR_RootConstrainSelectedInstOperands,
74847 // GIR_Coverage, 8877,
74848 GIR_EraseRootFromParent_Done,
74849 // Label 4248: @200917
74850 GIM_Try, /*On fail goto*//*Label 4249*/ GIMT_Encode4(200962), // Rule ID 8878 //
74851 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74852 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmplt_wide),
74853 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
74854 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
74855 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
74856 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
74857 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
74858 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1143:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPLT_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
74859 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLT_WIDE_PPzZZ_S),
74860 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74861 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74862 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74863 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74864 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
74865 GIR_RootConstrainSelectedInstOperands,
74866 // GIR_Coverage, 8878,
74867 GIR_EraseRootFromParent_Done,
74868 // Label 4249: @200962
74869 GIM_Try, /*On fail goto*//*Label 4250*/ GIMT_Encode4(201007), // Rule ID 8879 //
74870 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74871 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmple_wide),
74872 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
74873 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
74874 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
74875 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
74876 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
74877 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1140:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPLE_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
74878 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLE_WIDE_PPzZZ_B),
74879 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74880 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74881 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74882 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74883 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
74884 GIR_RootConstrainSelectedInstOperands,
74885 // GIR_Coverage, 8879,
74886 GIR_EraseRootFromParent_Done,
74887 // Label 4250: @201007
74888 GIM_Try, /*On fail goto*//*Label 4251*/ GIMT_Encode4(201052), // Rule ID 8880 //
74889 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74890 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmple_wide),
74891 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
74892 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
74893 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
74894 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
74895 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
74896 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1140:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPLE_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
74897 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLE_WIDE_PPzZZ_H),
74898 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74899 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74900 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74901 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74902 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
74903 GIR_RootConstrainSelectedInstOperands,
74904 // GIR_Coverage, 8880,
74905 GIR_EraseRootFromParent_Done,
74906 // Label 4251: @201052
74907 GIM_Try, /*On fail goto*//*Label 4252*/ GIMT_Encode4(201097), // Rule ID 8881 //
74908 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74909 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmple_wide),
74910 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
74911 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
74912 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
74913 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
74914 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
74915 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1140:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPLE_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
74916 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLE_WIDE_PPzZZ_S),
74917 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74918 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74919 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74920 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74921 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
74922 GIR_RootConstrainSelectedInstOperands,
74923 // GIR_Coverage, 8881,
74924 GIR_EraseRootFromParent_Done,
74925 // Label 4252: @201097
74926 GIM_Try, /*On fail goto*//*Label 4253*/ GIMT_Encode4(201142), // Rule ID 8882 //
74927 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74928 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmphs_wide),
74929 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
74930 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
74931 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
74932 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
74933 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
74934 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1139:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPHS_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
74935 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPHS_WIDE_PPzZZ_B),
74936 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74937 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74938 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74939 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74940 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
74941 GIR_RootConstrainSelectedInstOperands,
74942 // GIR_Coverage, 8882,
74943 GIR_EraseRootFromParent_Done,
74944 // Label 4253: @201142
74945 GIM_Try, /*On fail goto*//*Label 4254*/ GIMT_Encode4(201187), // Rule ID 8883 //
74946 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74947 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmphs_wide),
74948 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
74949 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
74950 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
74951 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
74952 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
74953 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1139:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPHS_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
74954 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPHS_WIDE_PPzZZ_H),
74955 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74956 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74957 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74958 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74959 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
74960 GIR_RootConstrainSelectedInstOperands,
74961 // GIR_Coverage, 8883,
74962 GIR_EraseRootFromParent_Done,
74963 // Label 4254: @201187
74964 GIM_Try, /*On fail goto*//*Label 4255*/ GIMT_Encode4(201232), // Rule ID 8884 //
74965 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74966 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmphs_wide),
74967 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
74968 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
74969 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
74970 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
74971 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
74972 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1139:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPHS_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
74973 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPHS_WIDE_PPzZZ_S),
74974 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74975 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74976 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74977 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74978 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
74979 GIR_RootConstrainSelectedInstOperands,
74980 // GIR_Coverage, 8884,
74981 GIR_EraseRootFromParent_Done,
74982 // Label 4255: @201232
74983 GIM_Try, /*On fail goto*//*Label 4256*/ GIMT_Encode4(201277), // Rule ID 8885 //
74984 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
74985 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmphi_wide),
74986 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
74987 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
74988 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
74989 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
74990 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
74991 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1137:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPHI_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
74992 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPHI_WIDE_PPzZZ_B),
74993 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
74994 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
74995 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
74996 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
74997 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
74998 GIR_RootConstrainSelectedInstOperands,
74999 // GIR_Coverage, 8885,
75000 GIR_EraseRootFromParent_Done,
75001 // Label 4256: @201277
75002 GIM_Try, /*On fail goto*//*Label 4257*/ GIMT_Encode4(201322), // Rule ID 8886 //
75003 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75004 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmphi_wide),
75005 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
75006 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
75007 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
75008 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75009 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
75010 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1137:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPHI_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75011 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPHI_WIDE_PPzZZ_H),
75012 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
75013 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75014 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75015 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75016 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
75017 GIR_RootConstrainSelectedInstOperands,
75018 // GIR_Coverage, 8886,
75019 GIR_EraseRootFromParent_Done,
75020 // Label 4257: @201322
75021 GIM_Try, /*On fail goto*//*Label 4258*/ GIMT_Encode4(201367), // Rule ID 8887 //
75022 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75023 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmphi_wide),
75024 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
75025 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
75026 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
75027 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75028 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
75029 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1137:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPHI_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75030 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPHI_WIDE_PPzZZ_S),
75031 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
75032 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75033 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75034 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75035 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
75036 GIR_RootConstrainSelectedInstOperands,
75037 // GIR_Coverage, 8887,
75038 GIR_EraseRootFromParent_Done,
75039 // Label 4258: @201367
75040 GIM_Try, /*On fail goto*//*Label 4259*/ GIMT_Encode4(201412), // Rule ID 8888 //
75041 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75042 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmplo_wide),
75043 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
75044 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
75045 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
75046 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75047 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
75048 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1141:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPLO_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75049 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLO_WIDE_PPzZZ_B),
75050 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
75051 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75052 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75053 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75054 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
75055 GIR_RootConstrainSelectedInstOperands,
75056 // GIR_Coverage, 8888,
75057 GIR_EraseRootFromParent_Done,
75058 // Label 4259: @201412
75059 GIM_Try, /*On fail goto*//*Label 4260*/ GIMT_Encode4(201457), // Rule ID 8889 //
75060 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75061 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmplo_wide),
75062 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
75063 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
75064 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
75065 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75066 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
75067 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1141:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPLO_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75068 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLO_WIDE_PPzZZ_H),
75069 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
75070 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75071 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75072 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75073 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
75074 GIR_RootConstrainSelectedInstOperands,
75075 // GIR_Coverage, 8889,
75076 GIR_EraseRootFromParent_Done,
75077 // Label 4260: @201457
75078 GIM_Try, /*On fail goto*//*Label 4261*/ GIMT_Encode4(201502), // Rule ID 8890 //
75079 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75080 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmplo_wide),
75081 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
75082 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
75083 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
75084 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75085 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
75086 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1141:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPLO_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75087 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLO_WIDE_PPzZZ_S),
75088 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
75089 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75090 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75091 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75092 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
75093 GIR_RootConstrainSelectedInstOperands,
75094 // GIR_Coverage, 8890,
75095 GIR_EraseRootFromParent_Done,
75096 // Label 4261: @201502
75097 GIM_Try, /*On fail goto*//*Label 4262*/ GIMT_Encode4(201547), // Rule ID 8891 //
75098 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75099 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpls_wide),
75100 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
75101 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
75102 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
75103 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75104 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
75105 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1142:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPLS_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75106 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLS_WIDE_PPzZZ_B),
75107 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
75108 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75109 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75110 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75111 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
75112 GIR_RootConstrainSelectedInstOperands,
75113 // GIR_Coverage, 8891,
75114 GIR_EraseRootFromParent_Done,
75115 // Label 4262: @201547
75116 GIM_Try, /*On fail goto*//*Label 4263*/ GIMT_Encode4(201592), // Rule ID 8892 //
75117 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75118 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpls_wide),
75119 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
75120 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
75121 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
75122 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75123 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
75124 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1142:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPLS_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75125 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLS_WIDE_PPzZZ_H),
75126 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
75127 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75128 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75129 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75130 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
75131 GIR_RootConstrainSelectedInstOperands,
75132 // GIR_Coverage, 8892,
75133 GIR_EraseRootFromParent_Done,
75134 // Label 4263: @201592
75135 GIM_Try, /*On fail goto*//*Label 4264*/ GIMT_Encode4(201637), // Rule ID 8893 //
75136 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75137 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpls_wide),
75138 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
75139 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
75140 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
75141 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75142 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
75143 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1142:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (CMPLS_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75144 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLS_WIDE_PPzZZ_S),
75145 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
75146 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75147 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75148 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75149 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
75150 GIR_RootConstrainSelectedInstOperands,
75151 // GIR_Coverage, 8893,
75152 GIR_EraseRootFromParent_Done,
75153 // Label 4264: @201637
75154 GIM_Try, /*On fail goto*//*Label 4265*/ GIMT_Encode4(201679), // Rule ID 9290 //
75155 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75156 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_facgt),
75157 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
75158 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
75159 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
75160 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
75161 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
75162 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1178:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FACGT_PPzZZ_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
75163 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGT_PPzZZ_H),
75164 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
75165 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75166 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75167 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75168 GIR_RootConstrainSelectedInstOperands,
75169 // GIR_Coverage, 9290,
75170 GIR_EraseRootFromParent_Done,
75171 // Label 4265: @201679
75172 GIM_Try, /*On fail goto*//*Label 4266*/ GIMT_Encode4(201721), // Rule ID 9291 //
75173 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75174 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_facgt),
75175 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
75176 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
75177 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
75178 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
75179 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
75180 // (intrinsic_wo_chain:{ *:[nxv4i1] } 1178:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FACGT_PPzZZ_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
75181 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGT_PPzZZ_S),
75182 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
75183 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75184 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75185 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75186 GIR_RootConstrainSelectedInstOperands,
75187 // GIR_Coverage, 9291,
75188 GIR_EraseRootFromParent_Done,
75189 // Label 4266: @201721
75190 GIM_Try, /*On fail goto*//*Label 4267*/ GIMT_Encode4(201763), // Rule ID 9292 //
75191 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75192 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_facgt),
75193 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
75194 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
75195 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
75196 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75197 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
75198 // (intrinsic_wo_chain:{ *:[nxv2i1] } 1178:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FACGT_PPzZZ_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
75199 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGT_PPzZZ_D),
75200 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
75201 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75202 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75203 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75204 GIR_RootConstrainSelectedInstOperands,
75205 // GIR_Coverage, 9292,
75206 GIR_EraseRootFromParent_Done,
75207 // Label 4267: @201763
75208 GIM_Try, /*On fail goto*//*Label 4268*/ GIMT_Encode4(201805), // Rule ID 9830 //
75209 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75210 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr),
75211 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
75212 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
75213 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
75214 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
75215 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75216 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1377:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (LSR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
75217 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_ZPmZ_B),
75218 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
75219 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75220 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75221 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75222 GIR_RootConstrainSelectedInstOperands,
75223 // GIR_Coverage, 9830,
75224 GIR_EraseRootFromParent_Done,
75225 // Label 4268: @201805
75226 GIM_Try, /*On fail goto*//*Label 4269*/ GIMT_Encode4(201847), // Rule ID 9831 //
75227 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75228 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr),
75229 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
75230 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
75231 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
75232 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
75233 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75234 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1377:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (LSR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
75235 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_ZPmZ_H),
75236 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
75237 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75238 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75239 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75240 GIR_RootConstrainSelectedInstOperands,
75241 // GIR_Coverage, 9831,
75242 GIR_EraseRootFromParent_Done,
75243 // Label 4269: @201847
75244 GIM_Try, /*On fail goto*//*Label 4270*/ GIMT_Encode4(201889), // Rule ID 9832 //
75245 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75246 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr),
75247 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
75248 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
75249 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
75250 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
75251 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75252 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1377:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (LSR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
75253 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_ZPmZ_S),
75254 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
75255 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75256 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75257 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75258 GIR_RootConstrainSelectedInstOperands,
75259 // GIR_Coverage, 9832,
75260 GIR_EraseRootFromParent_Done,
75261 // Label 4270: @201889
75262 GIM_Try, /*On fail goto*//*Label 4271*/ GIMT_Encode4(201931), // Rule ID 9833 //
75263 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75264 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr),
75265 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
75266 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
75267 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
75268 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75269 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75270 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1377:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (LSR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75271 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_ZPmZ_D),
75272 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
75273 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75274 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75275 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75276 GIR_RootConstrainSelectedInstOperands,
75277 // GIR_Coverage, 9833,
75278 GIR_EraseRootFromParent_Done,
75279 // Label 4271: @201931
75280 GIM_Try, /*On fail goto*//*Label 4272*/ GIMT_Encode4(201973), // Rule ID 9834 //
75281 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75282 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl),
75283 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
75284 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
75285 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
75286 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
75287 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75288 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1374:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (LSL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
75289 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_ZPmZ_B),
75290 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
75291 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75292 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75293 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75294 GIR_RootConstrainSelectedInstOperands,
75295 // GIR_Coverage, 9834,
75296 GIR_EraseRootFromParent_Done,
75297 // Label 4272: @201973
75298 GIM_Try, /*On fail goto*//*Label 4273*/ GIMT_Encode4(202015), // Rule ID 9835 //
75299 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75300 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl),
75301 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
75302 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
75303 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
75304 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
75305 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75306 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1374:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (LSL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
75307 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_ZPmZ_H),
75308 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
75309 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75310 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75311 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75312 GIR_RootConstrainSelectedInstOperands,
75313 // GIR_Coverage, 9835,
75314 GIR_EraseRootFromParent_Done,
75315 // Label 4273: @202015
75316 GIM_Try, /*On fail goto*//*Label 4274*/ GIMT_Encode4(202057), // Rule ID 9836 //
75317 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75318 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl),
75319 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
75320 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
75321 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
75322 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
75323 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75324 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1374:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (LSL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
75325 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_ZPmZ_S),
75326 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
75327 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75328 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75329 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75330 GIR_RootConstrainSelectedInstOperands,
75331 // GIR_Coverage, 9836,
75332 GIR_EraseRootFromParent_Done,
75333 // Label 4274: @202057
75334 GIM_Try, /*On fail goto*//*Label 4275*/ GIMT_Encode4(202099), // Rule ID 9837 //
75335 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75336 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl),
75337 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
75338 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
75339 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
75340 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75341 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75342 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1374:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (LSL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75343 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_ZPmZ_D),
75344 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
75345 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75346 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75347 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75348 GIR_RootConstrainSelectedInstOperands,
75349 // GIR_Coverage, 9837,
75350 GIR_EraseRootFromParent_Done,
75351 // Label 4275: @202099
75352 GIM_Try, /*On fail goto*//*Label 4276*/ GIMT_Encode4(202141), // Rule ID 9850 //
75353 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75354 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr_wide),
75355 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
75356 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
75357 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
75358 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75359 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75360 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1379:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (LSR_WIDE_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75361 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_WIDE_ZPmZ_B),
75362 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
75363 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75364 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75365 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75366 GIR_RootConstrainSelectedInstOperands,
75367 // GIR_Coverage, 9850,
75368 GIR_EraseRootFromParent_Done,
75369 // Label 4276: @202141
75370 GIM_Try, /*On fail goto*//*Label 4277*/ GIMT_Encode4(202183), // Rule ID 9851 //
75371 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75372 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr_wide),
75373 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
75374 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
75375 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
75376 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75377 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75378 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1379:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (LSR_WIDE_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75379 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_WIDE_ZPmZ_H),
75380 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
75381 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75382 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75383 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75384 GIR_RootConstrainSelectedInstOperands,
75385 // GIR_Coverage, 9851,
75386 GIR_EraseRootFromParent_Done,
75387 // Label 4277: @202183
75388 GIM_Try, /*On fail goto*//*Label 4278*/ GIMT_Encode4(202225), // Rule ID 9852 //
75389 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75390 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr_wide),
75391 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
75392 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
75393 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
75394 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75395 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75396 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1379:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (LSR_WIDE_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75397 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_WIDE_ZPmZ_S),
75398 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
75399 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75400 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75401 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75402 GIR_RootConstrainSelectedInstOperands,
75403 // GIR_Coverage, 9852,
75404 GIR_EraseRootFromParent_Done,
75405 // Label 4278: @202225
75406 GIM_Try, /*On fail goto*//*Label 4279*/ GIMT_Encode4(202267), // Rule ID 9853 //
75407 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75408 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl_wide),
75409 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
75410 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
75411 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
75412 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75413 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75414 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1376:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (LSL_WIDE_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75415 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_WIDE_ZPmZ_B),
75416 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
75417 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75418 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75419 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75420 GIR_RootConstrainSelectedInstOperands,
75421 // GIR_Coverage, 9853,
75422 GIR_EraseRootFromParent_Done,
75423 // Label 4279: @202267
75424 GIM_Try, /*On fail goto*//*Label 4280*/ GIMT_Encode4(202309), // Rule ID 9854 //
75425 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75426 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl_wide),
75427 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
75428 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
75429 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
75430 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75431 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75432 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1376:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (LSL_WIDE_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75433 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_WIDE_ZPmZ_H),
75434 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
75435 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75436 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75437 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75438 GIR_RootConstrainSelectedInstOperands,
75439 // GIR_Coverage, 9854,
75440 GIR_EraseRootFromParent_Done,
75441 // Label 4280: @202309
75442 GIM_Try, /*On fail goto*//*Label 4281*/ GIMT_Encode4(202351), // Rule ID 9855 //
75443 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75444 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl_wide),
75445 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
75446 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
75447 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
75448 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75449 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75450 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1376:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (LSL_WIDE_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75451 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_WIDE_ZPmZ_S),
75452 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
75453 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75454 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75455 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75456 GIR_RootConstrainSelectedInstOperands,
75457 // GIR_Coverage, 9855,
75458 GIR_EraseRootFromParent_Done,
75459 // Label 4281: @202351
75460 GIM_Try, /*On fail goto*//*Label 4282*/ GIMT_Encode4(202393), // Rule ID 9882 //
75461 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75462 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvt_f16f64),
75463 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
75464 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
75465 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
75466 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75467 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75468 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1199:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FCVT_ZPmZ_DtoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
75469 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVT_ZPmZ_DtoH),
75470 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75471 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75472 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75473 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75474 GIR_RootConstrainSelectedInstOperands,
75475 // GIR_Coverage, 9882,
75476 GIR_EraseRootFromParent_Done,
75477 // Label 4282: @202393
75478 GIM_Try, /*On fail goto*//*Label 4283*/ GIMT_Encode4(202435), // Rule ID 9886 //
75479 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75480 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvt_f64f16),
75481 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
75482 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
75483 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
75484 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
75485 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75486 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1202:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FCVT_ZPmZ_HtoD:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
75487 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVT_ZPmZ_HtoD),
75488 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75489 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75490 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75491 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75492 GIR_RootConstrainSelectedInstOperands,
75493 // GIR_Coverage, 9886,
75494 GIR_EraseRootFromParent_Done,
75495 // Label 4283: @202435
75496 GIM_Try, /*On fail goto*//*Label 4284*/ GIMT_Encode4(202477), // Rule ID 9890 //
75497 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75498 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvt_f32f64),
75499 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
75500 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
75501 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
75502 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75503 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75504 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1201:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FCVT_ZPmZ_DtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
75505 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVT_ZPmZ_DtoS),
75506 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75507 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75508 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75509 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75510 GIR_RootConstrainSelectedInstOperands,
75511 // GIR_Coverage, 9890,
75512 GIR_EraseRootFromParent_Done,
75513 // Label 4284: @202477
75514 GIM_Try, /*On fail goto*//*Label 4285*/ GIMT_Encode4(202519), // Rule ID 9894 //
75515 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75516 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvt_f64f32),
75517 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
75518 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
75519 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
75520 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
75521 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75522 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1203:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FCVT_ZPmZ_StoD:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
75523 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVT_ZPmZ_StoD),
75524 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75525 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75526 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75527 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75528 GIR_RootConstrainSelectedInstOperands,
75529 // GIR_Coverage, 9894,
75530 GIR_EraseRootFromParent_Done,
75531 // Label 4285: @202519
75532 GIM_Try, /*On fail goto*//*Label 4286*/ GIMT_Encode4(202561), // Rule ID 9898 //
75533 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75534 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_scvtf_f64i32),
75535 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
75536 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
75537 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
75538 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
75539 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75540 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1484:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SCVTF_ZPmZ_StoD:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
75541 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTF_ZPmZ_StoD),
75542 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75543 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75544 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75545 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75546 GIR_RootConstrainSelectedInstOperands,
75547 // GIR_Coverage, 9898,
75548 GIR_EraseRootFromParent_Done,
75549 // Label 4286: @202561
75550 GIM_Try, /*On fail goto*//*Label 4287*/ GIMT_Encode4(202603), // Rule ID 9902 //
75551 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75552 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ucvtf_f64i32),
75553 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
75554 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
75555 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
75556 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
75557 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75558 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1731:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UCVTF_ZPmZ_StoD:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
75559 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTF_ZPmZ_StoD),
75560 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75561 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75562 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75563 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75564 GIR_RootConstrainSelectedInstOperands,
75565 // GIR_Coverage, 9902,
75566 GIR_EraseRootFromParent_Done,
75567 // Label 4287: @202603
75568 GIM_Try, /*On fail goto*//*Label 4288*/ GIMT_Encode4(202645), // Rule ID 9906 //
75569 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75570 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ucvtf_f16i32),
75571 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
75572 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
75573 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
75574 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
75575 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75576 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1728:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UCVTF_ZPmZ_StoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
75577 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTF_ZPmZ_StoH),
75578 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75579 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75580 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75581 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75582 GIR_RootConstrainSelectedInstOperands,
75583 // GIR_Coverage, 9906,
75584 GIR_EraseRootFromParent_Done,
75585 // Label 4288: @202645
75586 GIM_Try, /*On fail goto*//*Label 4289*/ GIMT_Encode4(202687), // Rule ID 9910 //
75587 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75588 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_scvtf_f32i64),
75589 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
75590 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
75591 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
75592 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75593 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75594 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1483:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SCVTF_ZPmZ_DtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75595 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTF_ZPmZ_DtoS),
75596 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75597 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75598 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75599 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75600 GIR_RootConstrainSelectedInstOperands,
75601 // GIR_Coverage, 9910,
75602 GIR_EraseRootFromParent_Done,
75603 // Label 4289: @202687
75604 GIM_Try, /*On fail goto*//*Label 4290*/ GIMT_Encode4(202729), // Rule ID 9914 //
75605 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75606 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_scvtf_f16i32),
75607 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
75608 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
75609 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
75610 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
75611 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75612 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1481:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SCVTF_ZPmZ_StoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
75613 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTF_ZPmZ_StoH),
75614 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75615 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75616 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75617 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75618 GIR_RootConstrainSelectedInstOperands,
75619 // GIR_Coverage, 9914,
75620 GIR_EraseRootFromParent_Done,
75621 // Label 4290: @202729
75622 GIM_Try, /*On fail goto*//*Label 4291*/ GIMT_Encode4(202771), // Rule ID 9918 //
75623 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75624 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_scvtf_f16i64),
75625 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
75626 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
75627 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
75628 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75629 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75630 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1482:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SCVTF_ZPmZ_DtoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75631 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTF_ZPmZ_DtoH),
75632 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75633 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75634 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75635 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75636 GIR_RootConstrainSelectedInstOperands,
75637 // GIR_Coverage, 9918,
75638 GIR_EraseRootFromParent_Done,
75639 // Label 4291: @202771
75640 GIM_Try, /*On fail goto*//*Label 4292*/ GIMT_Encode4(202813), // Rule ID 9922 //
75641 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75642 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ucvtf_f32i64),
75643 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
75644 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
75645 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
75646 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75647 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75648 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1730:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (UCVTF_ZPmZ_DtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75649 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTF_ZPmZ_DtoS),
75650 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75651 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75652 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75653 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75654 GIR_RootConstrainSelectedInstOperands,
75655 // GIR_Coverage, 9922,
75656 GIR_EraseRootFromParent_Done,
75657 // Label 4292: @202813
75658 GIM_Try, /*On fail goto*//*Label 4293*/ GIMT_Encode4(202855), // Rule ID 9926 //
75659 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75660 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ucvtf_f16i64),
75661 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
75662 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
75663 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
75664 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75665 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75666 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1729:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (UCVTF_ZPmZ_DtoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75667 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTF_ZPmZ_DtoH),
75668 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75669 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75670 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75671 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75672 GIR_RootConstrainSelectedInstOperands,
75673 // GIR_Coverage, 9926,
75674 GIR_EraseRootFromParent_Done,
75675 // Label 4293: @202855
75676 GIM_Try, /*On fail goto*//*Label 4294*/ GIMT_Encode4(202897), // Rule ID 9936 //
75677 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75678 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzs_i32f64),
75679 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
75680 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
75681 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
75682 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75683 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75684 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1217:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FCVTZS_ZPmZ_DtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
75685 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZS_ZPmZ_DtoS),
75686 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75687 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75688 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75689 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75690 GIR_RootConstrainSelectedInstOperands,
75691 // GIR_Coverage, 9936,
75692 GIR_EraseRootFromParent_Done,
75693 // Label 4294: @202897
75694 GIM_Try, /*On fail goto*//*Label 4295*/ GIMT_Encode4(202939), // Rule ID 9937 //
75695 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75696 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzu_i32f64),
75697 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
75698 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
75699 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
75700 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75701 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75702 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1224:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FCVTZU_ZPmZ_DtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
75703 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZU_ZPmZ_DtoS),
75704 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75705 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75706 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75707 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75708 GIR_RootConstrainSelectedInstOperands,
75709 // GIR_Coverage, 9937,
75710 GIR_EraseRootFromParent_Done,
75711 // Label 4295: @202939
75712 GIM_Try, /*On fail goto*//*Label 4296*/ GIMT_Encode4(202981), // Rule ID 9938 //
75713 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75714 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzs_i64f32),
75715 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
75716 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
75717 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
75718 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
75719 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75720 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1219:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FCVTZS_ZPmZ_StoD:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
75721 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZS_ZPmZ_StoD),
75722 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75723 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75724 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75725 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75726 GIR_RootConstrainSelectedInstOperands,
75727 // GIR_Coverage, 9938,
75728 GIR_EraseRootFromParent_Done,
75729 // Label 4296: @202981
75730 GIM_Try, /*On fail goto*//*Label 4297*/ GIMT_Encode4(203023), // Rule ID 9942 //
75731 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75732 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzs_i32f16),
75733 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
75734 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
75735 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
75736 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
75737 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75738 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1216:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FCVTZS_ZPmZ_HtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
75739 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZS_ZPmZ_HtoS),
75740 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75741 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75742 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75743 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75744 GIR_RootConstrainSelectedInstOperands,
75745 // GIR_Coverage, 9942,
75746 GIR_EraseRootFromParent_Done,
75747 // Label 4297: @203023
75748 GIM_Try, /*On fail goto*//*Label 4298*/ GIMT_Encode4(203065), // Rule ID 9946 //
75749 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75750 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzs_i64f16),
75751 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
75752 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
75753 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
75754 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
75755 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75756 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1218:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FCVTZS_ZPmZ_HtoD:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
75757 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZS_ZPmZ_HtoD),
75758 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75759 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75760 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75761 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75762 GIR_RootConstrainSelectedInstOperands,
75763 // GIR_Coverage, 9946,
75764 GIR_EraseRootFromParent_Done,
75765 // Label 4298: @203065
75766 GIM_Try, /*On fail goto*//*Label 4299*/ GIMT_Encode4(203107), // Rule ID 9950 //
75767 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75768 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzu_i32f16),
75769 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
75770 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
75771 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
75772 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
75773 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75774 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1223:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FCVTZU_ZPmZ_HtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
75775 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZU_ZPmZ_HtoS),
75776 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75777 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75778 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75779 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75780 GIR_RootConstrainSelectedInstOperands,
75781 // GIR_Coverage, 9950,
75782 GIR_EraseRootFromParent_Done,
75783 // Label 4299: @203107
75784 GIM_Try, /*On fail goto*//*Label 4300*/ GIMT_Encode4(203149), // Rule ID 9954 //
75785 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75786 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzu_i64f16),
75787 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
75788 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
75789 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
75790 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
75791 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75792 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1225:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FCVTZU_ZPmZ_HtoD:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
75793 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZU_ZPmZ_HtoD),
75794 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75795 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75796 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75797 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75798 GIR_RootConstrainSelectedInstOperands,
75799 // GIR_Coverage, 9954,
75800 GIR_EraseRootFromParent_Done,
75801 // Label 4300: @203149
75802 GIM_Try, /*On fail goto*//*Label 4301*/ GIMT_Encode4(203191), // Rule ID 9958 //
75803 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
75804 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzu_i64f32),
75805 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
75806 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
75807 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
75808 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
75809 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75810 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1226:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FCVTZU_ZPmZ_StoD:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
75811 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZU_ZPmZ_StoD),
75812 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75813 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75814 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75815 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75816 GIR_RootConstrainSelectedInstOperands,
75817 // GIR_Coverage, 9958,
75818 GIR_EraseRootFromParent_Done,
75819 // Label 4301: @203191
75820 GIM_Try, /*On fail goto*//*Label 4302*/ GIMT_Encode4(203233), // Rule ID 10136 //
75821 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasSVEorSME),
75822 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bfmlalt),
75823 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
75824 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
75825 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
75826 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
75827 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75828 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1098:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3) => (BFMLALT_ZZZ:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3)
75829 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMLALT_ZZZ),
75830 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
75831 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75832 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75833 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75834 GIR_RootConstrainSelectedInstOperands,
75835 // GIR_Coverage, 10136,
75836 GIR_EraseRootFromParent_Done,
75837 // Label 4302: @203233
75838 GIM_Try, /*On fail goto*//*Label 4303*/ GIMT_Encode4(203275), // Rule ID 10138 //
75839 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasSVEorSME),
75840 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtnt_bf16f32),
75841 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
75842 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
75843 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
75844 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
75845 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75846 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1210:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (BFCVTNT_ZPmZ:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
75847 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVTNT_ZPmZ),
75848 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
75849 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75850 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75851 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75852 GIR_RootConstrainSelectedInstOperands,
75853 // GIR_Coverage, 10138,
75854 GIR_EraseRootFromParent_Done,
75855 // Label 4303: @203275
75856 GIM_Try, /*On fail goto*//*Label 4304*/ GIMT_Encode4(203317), // Rule ID 10917 //
75857 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8_HasSVE),
75858 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ummla),
75859 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
75860 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
75861 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
75862 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
75863 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75864 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1770:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UMMLA_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
75865 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMMLA_ZZZ),
75866 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
75867 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75868 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75869 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75870 GIR_RootConstrainSelectedInstOperands,
75871 // GIR_Coverage, 10917,
75872 GIR_EraseRootFromParent_Done,
75873 // Label 4304: @203317
75874 GIM_Try, /*On fail goto*//*Label 4305*/ GIMT_Encode4(203359), // Rule ID 10918 //
75875 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8_HasSVE),
75876 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usmmla),
75877 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
75878 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
75879 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
75880 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
75881 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75882 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1841:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (USMMLA_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
75883 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMMLA_ZZZ),
75884 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
75885 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75886 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75887 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75888 GIR_RootConstrainSelectedInstOperands,
75889 // GIR_Coverage, 10918,
75890 GIR_EraseRootFromParent_Done,
75891 // Label 4305: @203359
75892 GIM_Try, /*On fail goto*//*Label 4306*/ GIMT_Encode4(203401), // Rule ID 10920 //
75893 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE),
75894 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmmla),
75895 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
75896 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
75897 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
75898 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75899 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75900 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1287:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FMMLA_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
75901 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMMLA_ZZZ_D),
75902 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
75903 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75904 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75905 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75906 GIR_RootConstrainSelectedInstOperands,
75907 // GIR_Coverage, 10920,
75908 GIR_EraseRootFromParent_Done,
75909 // Label 4306: @203401
75910 GIM_Try, /*On fail goto*//*Label 4307*/ GIMT_Encode4(203443), // Rule ID 10979 //
75911 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
75912 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh),
75913 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
75914 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
75915 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
75916 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
75917 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75918 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1605:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SQRDMLSH_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
75919 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZ_B),
75920 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
75921 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75922 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75923 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75924 GIR_RootConstrainSelectedInstOperands,
75925 // GIR_Coverage, 10979,
75926 GIR_EraseRootFromParent_Done,
75927 // Label 4307: @203443
75928 GIM_Try, /*On fail goto*//*Label 4308*/ GIMT_Encode4(203485), // Rule ID 10980 //
75929 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
75930 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh),
75931 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
75932 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
75933 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
75934 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
75935 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75936 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1605:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SQRDMLSH_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
75937 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZ_H),
75938 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
75939 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75940 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75941 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75942 GIR_RootConstrainSelectedInstOperands,
75943 // GIR_Coverage, 10980,
75944 GIR_EraseRootFromParent_Done,
75945 // Label 4308: @203485
75946 GIM_Try, /*On fail goto*//*Label 4309*/ GIMT_Encode4(203527), // Rule ID 10981 //
75947 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
75948 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh),
75949 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
75950 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
75951 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
75952 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
75953 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75954 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1605:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SQRDMLSH_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
75955 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZ_S),
75956 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
75957 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75958 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75959 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75960 GIR_RootConstrainSelectedInstOperands,
75961 // GIR_Coverage, 10981,
75962 GIR_EraseRootFromParent_Done,
75963 // Label 4309: @203527
75964 GIM_Try, /*On fail goto*//*Label 4310*/ GIMT_Encode4(203569), // Rule ID 10982 //
75965 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
75966 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh),
75967 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
75968 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
75969 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
75970 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
75971 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75972 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1605:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SQRDMLSH_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
75973 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZ_D),
75974 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
75975 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75976 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75977 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75978 GIR_RootConstrainSelectedInstOperands,
75979 // GIR_Coverage, 10982,
75980 GIR_EraseRootFromParent_Done,
75981 // Label 4310: @203569
75982 GIM_Try, /*On fail goto*//*Label 4311*/ GIMT_Encode4(203611), // Rule ID 11035 //
75983 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
75984 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalt),
75985 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
75986 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
75987 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
75988 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
75989 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
75990 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1526:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SMLALT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
75991 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALT_ZZZ_H),
75992 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
75993 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
75994 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
75995 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
75996 GIR_RootConstrainSelectedInstOperands,
75997 // GIR_Coverage, 11035,
75998 GIR_EraseRootFromParent_Done,
75999 // Label 4311: @203611
76000 GIM_Try, /*On fail goto*//*Label 4312*/ GIMT_Encode4(203653), // Rule ID 11036 //
76001 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76002 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalt),
76003 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
76004 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
76005 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
76006 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
76007 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76008 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1526:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SMLALT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
76009 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALT_ZZZ_S),
76010 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76011 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76012 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76013 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76014 GIR_RootConstrainSelectedInstOperands,
76015 // GIR_Coverage, 11036,
76016 GIR_EraseRootFromParent_Done,
76017 // Label 4312: @203653
76018 GIM_Try, /*On fail goto*//*Label 4313*/ GIMT_Encode4(203695), // Rule ID 11037 //
76019 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76020 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalt),
76021 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
76022 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
76023 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
76024 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
76025 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76026 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1526:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SMLALT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
76027 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALT_ZZZ_D),
76028 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76029 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76030 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76031 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76032 GIR_RootConstrainSelectedInstOperands,
76033 // GIR_Coverage, 11037,
76034 GIR_EraseRootFromParent_Done,
76035 // Label 4313: @203695
76036 GIM_Try, /*On fail goto*//*Label 4314*/ GIMT_Encode4(203737), // Rule ID 11038 //
76037 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76038 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalb),
76039 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
76040 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
76041 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
76042 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
76043 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76044 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1762:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UMLALB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
76045 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALB_ZZZ_H),
76046 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76047 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76048 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76049 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76050 GIR_RootConstrainSelectedInstOperands,
76051 // GIR_Coverage, 11038,
76052 GIR_EraseRootFromParent_Done,
76053 // Label 4314: @203737
76054 GIM_Try, /*On fail goto*//*Label 4315*/ GIMT_Encode4(203779), // Rule ID 11039 //
76055 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76056 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalb),
76057 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
76058 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
76059 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
76060 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
76061 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76062 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1762:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UMLALB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
76063 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALB_ZZZ_S),
76064 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76065 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76066 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76067 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76068 GIR_RootConstrainSelectedInstOperands,
76069 // GIR_Coverage, 11039,
76070 GIR_EraseRootFromParent_Done,
76071 // Label 4315: @203779
76072 GIM_Try, /*On fail goto*//*Label 4316*/ GIMT_Encode4(203821), // Rule ID 11040 //
76073 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76074 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalb),
76075 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
76076 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
76077 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
76078 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
76079 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76080 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1762:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UMLALB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
76081 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALB_ZZZ_D),
76082 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76083 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76084 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76085 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76086 GIR_RootConstrainSelectedInstOperands,
76087 // GIR_Coverage, 11040,
76088 GIR_EraseRootFromParent_Done,
76089 // Label 4316: @203821
76090 GIM_Try, /*On fail goto*//*Label 4317*/ GIMT_Encode4(203863), // Rule ID 11041 //
76091 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76092 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalt),
76093 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
76094 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
76095 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
76096 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
76097 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76098 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1764:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UMLALT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
76099 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALT_ZZZ_H),
76100 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76101 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76102 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76103 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76104 GIR_RootConstrainSelectedInstOperands,
76105 // GIR_Coverage, 11041,
76106 GIR_EraseRootFromParent_Done,
76107 // Label 4317: @203863
76108 GIM_Try, /*On fail goto*//*Label 4318*/ GIMT_Encode4(203905), // Rule ID 11042 //
76109 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76110 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalt),
76111 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
76112 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
76113 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
76114 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
76115 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76116 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1764:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UMLALT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
76117 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALT_ZZZ_S),
76118 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76119 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76120 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76121 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76122 GIR_RootConstrainSelectedInstOperands,
76123 // GIR_Coverage, 11042,
76124 GIR_EraseRootFromParent_Done,
76125 // Label 4318: @203905
76126 GIM_Try, /*On fail goto*//*Label 4319*/ GIMT_Encode4(203947), // Rule ID 11043 //
76127 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76128 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalt),
76129 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
76130 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
76131 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
76132 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
76133 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76134 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1764:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UMLALT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
76135 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALT_ZZZ_D),
76136 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76137 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76138 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76139 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76140 GIR_RootConstrainSelectedInstOperands,
76141 // GIR_Coverage, 11043,
76142 GIR_EraseRootFromParent_Done,
76143 // Label 4319: @203947
76144 GIM_Try, /*On fail goto*//*Label 4320*/ GIMT_Encode4(203989), // Rule ID 11044 //
76145 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76146 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslb),
76147 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
76148 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
76149 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
76150 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
76151 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76152 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1528:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SMLSLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
76153 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLB_ZZZ_H),
76154 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76155 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76156 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76157 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76158 GIR_RootConstrainSelectedInstOperands,
76159 // GIR_Coverage, 11044,
76160 GIR_EraseRootFromParent_Done,
76161 // Label 4320: @203989
76162 GIM_Try, /*On fail goto*//*Label 4321*/ GIMT_Encode4(204031), // Rule ID 11045 //
76163 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76164 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslb),
76165 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
76166 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
76167 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
76168 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
76169 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76170 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1528:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SMLSLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
76171 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLB_ZZZ_S),
76172 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76173 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76174 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76175 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76176 GIR_RootConstrainSelectedInstOperands,
76177 // GIR_Coverage, 11045,
76178 GIR_EraseRootFromParent_Done,
76179 // Label 4321: @204031
76180 GIM_Try, /*On fail goto*//*Label 4322*/ GIMT_Encode4(204073), // Rule ID 11046 //
76181 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76182 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslb),
76183 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
76184 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
76185 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
76186 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
76187 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76188 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1528:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SMLSLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
76189 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLB_ZZZ_D),
76190 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76191 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76192 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76193 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76194 GIR_RootConstrainSelectedInstOperands,
76195 // GIR_Coverage, 11046,
76196 GIR_EraseRootFromParent_Done,
76197 // Label 4322: @204073
76198 GIM_Try, /*On fail goto*//*Label 4323*/ GIMT_Encode4(204115), // Rule ID 11047 //
76199 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76200 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslt),
76201 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
76202 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
76203 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
76204 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
76205 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76206 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1530:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SMLSLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
76207 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLT_ZZZ_H),
76208 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76209 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76210 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76211 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76212 GIR_RootConstrainSelectedInstOperands,
76213 // GIR_Coverage, 11047,
76214 GIR_EraseRootFromParent_Done,
76215 // Label 4323: @204115
76216 GIM_Try, /*On fail goto*//*Label 4324*/ GIMT_Encode4(204157), // Rule ID 11048 //
76217 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76218 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslt),
76219 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
76220 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
76221 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
76222 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
76223 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76224 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1530:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SMLSLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
76225 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLT_ZZZ_S),
76226 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76227 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76228 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76229 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76230 GIR_RootConstrainSelectedInstOperands,
76231 // GIR_Coverage, 11048,
76232 GIR_EraseRootFromParent_Done,
76233 // Label 4324: @204157
76234 GIM_Try, /*On fail goto*//*Label 4325*/ GIMT_Encode4(204199), // Rule ID 11049 //
76235 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76236 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslt),
76237 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
76238 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
76239 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
76240 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
76241 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76242 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1530:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SMLSLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
76243 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLT_ZZZ_D),
76244 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76245 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76246 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76247 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76248 GIR_RootConstrainSelectedInstOperands,
76249 // GIR_Coverage, 11049,
76250 GIR_EraseRootFromParent_Done,
76251 // Label 4325: @204199
76252 GIM_Try, /*On fail goto*//*Label 4326*/ GIMT_Encode4(204241), // Rule ID 11050 //
76253 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76254 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslb),
76255 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
76256 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
76257 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
76258 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
76259 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76260 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1766:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UMLSLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
76261 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLB_ZZZ_H),
76262 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76263 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76264 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76265 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76266 GIR_RootConstrainSelectedInstOperands,
76267 // GIR_Coverage, 11050,
76268 GIR_EraseRootFromParent_Done,
76269 // Label 4326: @204241
76270 GIM_Try, /*On fail goto*//*Label 4327*/ GIMT_Encode4(204283), // Rule ID 11051 //
76271 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76272 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslb),
76273 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
76274 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
76275 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
76276 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
76277 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76278 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1766:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UMLSLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
76279 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLB_ZZZ_S),
76280 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76281 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76282 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76283 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76284 GIR_RootConstrainSelectedInstOperands,
76285 // GIR_Coverage, 11051,
76286 GIR_EraseRootFromParent_Done,
76287 // Label 4327: @204283
76288 GIM_Try, /*On fail goto*//*Label 4328*/ GIMT_Encode4(204325), // Rule ID 11052 //
76289 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76290 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslb),
76291 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
76292 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
76293 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
76294 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
76295 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76296 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1766:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UMLSLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
76297 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLB_ZZZ_D),
76298 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76299 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76300 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76301 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76302 GIR_RootConstrainSelectedInstOperands,
76303 // GIR_Coverage, 11052,
76304 GIR_EraseRootFromParent_Done,
76305 // Label 4328: @204325
76306 GIM_Try, /*On fail goto*//*Label 4329*/ GIMT_Encode4(204367), // Rule ID 11053 //
76307 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76308 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslt),
76309 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
76310 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
76311 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
76312 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
76313 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76314 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1768:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UMLSLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
76315 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLT_ZZZ_H),
76316 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76317 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76318 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76319 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76320 GIR_RootConstrainSelectedInstOperands,
76321 // GIR_Coverage, 11053,
76322 GIR_EraseRootFromParent_Done,
76323 // Label 4329: @204367
76324 GIM_Try, /*On fail goto*//*Label 4330*/ GIMT_Encode4(204409), // Rule ID 11054 //
76325 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76326 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslt),
76327 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
76328 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
76329 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
76330 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
76331 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76332 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1768:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UMLSLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
76333 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLT_ZZZ_S),
76334 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76335 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76336 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76337 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76338 GIR_RootConstrainSelectedInstOperands,
76339 // GIR_Coverage, 11054,
76340 GIR_EraseRootFromParent_Done,
76341 // Label 4330: @204409
76342 GIM_Try, /*On fail goto*//*Label 4331*/ GIMT_Encode4(204451), // Rule ID 11055 //
76343 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76344 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslt),
76345 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
76346 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
76347 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
76348 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
76349 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76350 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1768:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UMLSLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
76351 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLT_ZZZ_D),
76352 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76353 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76354 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76355 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76356 GIR_RootConstrainSelectedInstOperands,
76357 // GIR_Coverage, 11055,
76358 GIR_EraseRootFromParent_Done,
76359 // Label 4331: @204451
76360 GIM_Try, /*On fail goto*//*Label 4332*/ GIMT_Encode4(204493), // Rule ID 11064 //
76361 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76362 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalb),
76363 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
76364 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
76365 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
76366 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
76367 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76368 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1566:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SQDMLALB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
76369 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALB_ZZZ_H),
76370 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76371 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76372 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76373 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76374 GIR_RootConstrainSelectedInstOperands,
76375 // GIR_Coverage, 11064,
76376 GIR_EraseRootFromParent_Done,
76377 // Label 4332: @204493
76378 GIM_Try, /*On fail goto*//*Label 4333*/ GIMT_Encode4(204535), // Rule ID 11065 //
76379 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76380 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalb),
76381 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
76382 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
76383 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
76384 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
76385 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76386 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1566:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SQDMLALB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
76387 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALB_ZZZ_S),
76388 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76389 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76390 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76391 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76392 GIR_RootConstrainSelectedInstOperands,
76393 // GIR_Coverage, 11065,
76394 GIR_EraseRootFromParent_Done,
76395 // Label 4333: @204535
76396 GIM_Try, /*On fail goto*//*Label 4334*/ GIMT_Encode4(204577), // Rule ID 11066 //
76397 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76398 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalb),
76399 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
76400 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
76401 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
76402 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
76403 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76404 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1566:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SQDMLALB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
76405 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALB_ZZZ_D),
76406 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76407 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76408 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76409 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76410 GIR_RootConstrainSelectedInstOperands,
76411 // GIR_Coverage, 11066,
76412 GIR_EraseRootFromParent_Done,
76413 // Label 4334: @204577
76414 GIM_Try, /*On fail goto*//*Label 4335*/ GIMT_Encode4(204619), // Rule ID 11067 //
76415 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76416 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalt),
76417 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
76418 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
76419 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
76420 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
76421 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76422 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1569:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SQDMLALT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
76423 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALT_ZZZ_H),
76424 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76425 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76426 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76427 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76428 GIR_RootConstrainSelectedInstOperands,
76429 // GIR_Coverage, 11067,
76430 GIR_EraseRootFromParent_Done,
76431 // Label 4335: @204619
76432 GIM_Try, /*On fail goto*//*Label 4336*/ GIMT_Encode4(204661), // Rule ID 11068 //
76433 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76434 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalt),
76435 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
76436 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
76437 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
76438 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
76439 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76440 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1569:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SQDMLALT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
76441 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALT_ZZZ_S),
76442 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76443 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76444 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76445 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76446 GIR_RootConstrainSelectedInstOperands,
76447 // GIR_Coverage, 11068,
76448 GIR_EraseRootFromParent_Done,
76449 // Label 4336: @204661
76450 GIM_Try, /*On fail goto*//*Label 4337*/ GIMT_Encode4(204703), // Rule ID 11069 //
76451 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76452 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalt),
76453 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
76454 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
76455 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
76456 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
76457 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76458 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1569:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SQDMLALT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
76459 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALT_ZZZ_D),
76460 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76461 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76462 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76463 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76464 GIR_RootConstrainSelectedInstOperands,
76465 // GIR_Coverage, 11069,
76466 GIR_EraseRootFromParent_Done,
76467 // Label 4337: @204703
76468 GIM_Try, /*On fail goto*//*Label 4338*/ GIMT_Encode4(204745), // Rule ID 11070 //
76469 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76470 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslb),
76471 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
76472 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
76473 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
76474 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
76475 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76476 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1571:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SQDMLSLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
76477 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLB_ZZZ_H),
76478 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76479 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76480 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76481 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76482 GIR_RootConstrainSelectedInstOperands,
76483 // GIR_Coverage, 11070,
76484 GIR_EraseRootFromParent_Done,
76485 // Label 4338: @204745
76486 GIM_Try, /*On fail goto*//*Label 4339*/ GIMT_Encode4(204787), // Rule ID 11071 //
76487 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76488 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslb),
76489 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
76490 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
76491 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
76492 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
76493 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76494 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1571:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SQDMLSLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
76495 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLB_ZZZ_S),
76496 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76497 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76498 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76499 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76500 GIR_RootConstrainSelectedInstOperands,
76501 // GIR_Coverage, 11071,
76502 GIR_EraseRootFromParent_Done,
76503 // Label 4339: @204787
76504 GIM_Try, /*On fail goto*//*Label 4340*/ GIMT_Encode4(204829), // Rule ID 11072 //
76505 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76506 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslb),
76507 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
76508 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
76509 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
76510 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
76511 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76512 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1571:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SQDMLSLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
76513 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLB_ZZZ_D),
76514 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76515 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76516 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76517 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76518 GIR_RootConstrainSelectedInstOperands,
76519 // GIR_Coverage, 11072,
76520 GIR_EraseRootFromParent_Done,
76521 // Label 4340: @204829
76522 GIM_Try, /*On fail goto*//*Label 4341*/ GIMT_Encode4(204871), // Rule ID 11073 //
76523 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76524 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslt),
76525 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
76526 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
76527 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
76528 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
76529 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76530 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1574:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SQDMLSLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
76531 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLT_ZZZ_H),
76532 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76533 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76534 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76535 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76536 GIR_RootConstrainSelectedInstOperands,
76537 // GIR_Coverage, 11073,
76538 GIR_EraseRootFromParent_Done,
76539 // Label 4341: @204871
76540 GIM_Try, /*On fail goto*//*Label 4342*/ GIMT_Encode4(204913), // Rule ID 11074 //
76541 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76542 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslt),
76543 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
76544 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
76545 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
76546 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
76547 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76548 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1574:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SQDMLSLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
76549 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLT_ZZZ_S),
76550 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76551 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76552 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76553 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76554 GIR_RootConstrainSelectedInstOperands,
76555 // GIR_Coverage, 11074,
76556 GIR_EraseRootFromParent_Done,
76557 // Label 4342: @204913
76558 GIM_Try, /*On fail goto*//*Label 4343*/ GIMT_Encode4(204955), // Rule ID 11075 //
76559 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76560 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslt),
76561 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
76562 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
76563 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
76564 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
76565 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76566 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1574:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SQDMLSLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
76567 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLT_ZZZ_D),
76568 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76569 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76570 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76571 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76572 GIR_RootConstrainSelectedInstOperands,
76573 // GIR_Coverage, 11075,
76574 GIR_EraseRootFromParent_Done,
76575 // Label 4343: @204955
76576 GIM_Try, /*On fail goto*//*Label 4344*/ GIMT_Encode4(204997), // Rule ID 11076 //
76577 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76578 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalbt),
76579 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
76580 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
76581 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
76582 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
76583 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76584 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1568:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SQDMLALBT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
76585 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALBT_ZZZ_H),
76586 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76587 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76588 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76589 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76590 GIR_RootConstrainSelectedInstOperands,
76591 // GIR_Coverage, 11076,
76592 GIR_EraseRootFromParent_Done,
76593 // Label 4344: @204997
76594 GIM_Try, /*On fail goto*//*Label 4345*/ GIMT_Encode4(205039), // Rule ID 11077 //
76595 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76596 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalbt),
76597 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
76598 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
76599 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
76600 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
76601 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76602 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1568:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SQDMLALBT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
76603 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALBT_ZZZ_S),
76604 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76605 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76606 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76607 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76608 GIR_RootConstrainSelectedInstOperands,
76609 // GIR_Coverage, 11077,
76610 GIR_EraseRootFromParent_Done,
76611 // Label 4345: @205039
76612 GIM_Try, /*On fail goto*//*Label 4346*/ GIMT_Encode4(205081), // Rule ID 11078 //
76613 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76614 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalbt),
76615 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
76616 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
76617 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
76618 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
76619 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76620 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1568:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SQDMLALBT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
76621 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALBT_ZZZ_D),
76622 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76623 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76624 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76625 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76626 GIR_RootConstrainSelectedInstOperands,
76627 // GIR_Coverage, 11078,
76628 GIR_EraseRootFromParent_Done,
76629 // Label 4346: @205081
76630 GIM_Try, /*On fail goto*//*Label 4347*/ GIMT_Encode4(205123), // Rule ID 11079 //
76631 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76632 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslbt),
76633 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
76634 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
76635 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
76636 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
76637 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76638 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1573:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SQDMLSLBT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
76639 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLBT_ZZZ_H),
76640 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76641 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76642 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76643 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76644 GIR_RootConstrainSelectedInstOperands,
76645 // GIR_Coverage, 11079,
76646 GIR_EraseRootFromParent_Done,
76647 // Label 4347: @205123
76648 GIM_Try, /*On fail goto*//*Label 4348*/ GIMT_Encode4(205165), // Rule ID 11080 //
76649 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76650 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslbt),
76651 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
76652 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
76653 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
76654 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
76655 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76656 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1573:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SQDMLSLBT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
76657 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLBT_ZZZ_S),
76658 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76659 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76660 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76661 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76662 GIR_RootConstrainSelectedInstOperands,
76663 // GIR_Coverage, 11080,
76664 GIR_EraseRootFromParent_Done,
76665 // Label 4348: @205165
76666 GIM_Try, /*On fail goto*//*Label 4349*/ GIMT_Encode4(205207), // Rule ID 11081 //
76667 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76668 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslbt),
76669 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
76670 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
76671 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
76672 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
76673 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76674 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1573:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SQDMLSLBT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
76675 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLBT_ZZZ_D),
76676 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
76677 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76678 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76679 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76680 GIR_RootConstrainSelectedInstOperands,
76681 // GIR_Coverage, 11081,
76682 GIR_EraseRootFromParent_Done,
76683 // Label 4349: @205207
76684 GIM_Try, /*On fail goto*//*Label 4350*/ GIMT_Encode4(205249), // Rule ID 11082 //
76685 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76686 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhadd),
76687 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
76688 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
76689 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
76690 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
76691 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76692 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1741:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UHADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
76693 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHADD_ZPmZ_B),
76694 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
76695 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76696 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76697 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76698 GIR_RootConstrainSelectedInstOperands,
76699 // GIR_Coverage, 11082,
76700 GIR_EraseRootFromParent_Done,
76701 // Label 4350: @205249
76702 GIM_Try, /*On fail goto*//*Label 4351*/ GIMT_Encode4(205291), // Rule ID 11084 //
76703 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76704 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhadd),
76705 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
76706 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
76707 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
76708 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
76709 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76710 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1741:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UHADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
76711 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHADD_ZPmZ_H),
76712 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
76713 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76714 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76715 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76716 GIR_RootConstrainSelectedInstOperands,
76717 // GIR_Coverage, 11084,
76718 GIR_EraseRootFromParent_Done,
76719 // Label 4351: @205291
76720 GIM_Try, /*On fail goto*//*Label 4352*/ GIMT_Encode4(205333), // Rule ID 11086 //
76721 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76722 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhadd),
76723 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
76724 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
76725 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
76726 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
76727 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76728 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1741:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UHADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
76729 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHADD_ZPmZ_S),
76730 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
76731 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76732 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76733 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76734 GIR_RootConstrainSelectedInstOperands,
76735 // GIR_Coverage, 11086,
76736 GIR_EraseRootFromParent_Done,
76737 // Label 4352: @205333
76738 GIM_Try, /*On fail goto*//*Label 4353*/ GIMT_Encode4(205375), // Rule ID 11088 //
76739 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76740 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhadd),
76741 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
76742 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
76743 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
76744 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
76745 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76746 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1741:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (UHADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
76747 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHADD_ZPmZ_D),
76748 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
76749 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76750 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76751 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76752 GIR_RootConstrainSelectedInstOperands,
76753 // GIR_Coverage, 11088,
76754 GIR_EraseRootFromParent_Done,
76755 // Label 4353: @205375
76756 GIM_Try, /*On fail goto*//*Label 4354*/ GIMT_Encode4(205417), // Rule ID 11090 //
76757 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76758 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsub),
76759 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
76760 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
76761 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
76762 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
76763 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76764 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1501:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SHSUB_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
76765 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUB_ZPmZ_B),
76766 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
76767 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76768 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76769 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76770 GIR_RootConstrainSelectedInstOperands,
76771 // GIR_Coverage, 11090,
76772 GIR_EraseRootFromParent_Done,
76773 // Label 4354: @205417
76774 GIM_Try, /*On fail goto*//*Label 4355*/ GIMT_Encode4(205459), // Rule ID 11091 //
76775 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76776 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsub),
76777 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
76778 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
76779 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
76780 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
76781 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76782 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1501:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SHSUB_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
76783 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUB_ZPmZ_H),
76784 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
76785 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76786 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76787 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76788 GIR_RootConstrainSelectedInstOperands,
76789 // GIR_Coverage, 11091,
76790 GIR_EraseRootFromParent_Done,
76791 // Label 4355: @205459
76792 GIM_Try, /*On fail goto*//*Label 4356*/ GIMT_Encode4(205501), // Rule ID 11092 //
76793 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76794 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsub),
76795 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
76796 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
76797 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
76798 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
76799 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76800 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1501:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SHSUB_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
76801 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUB_ZPmZ_S),
76802 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
76803 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76804 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76805 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76806 GIR_RootConstrainSelectedInstOperands,
76807 // GIR_Coverage, 11092,
76808 GIR_EraseRootFromParent_Done,
76809 // Label 4356: @205501
76810 GIM_Try, /*On fail goto*//*Label 4357*/ GIMT_Encode4(205543), // Rule ID 11093 //
76811 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76812 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsub),
76813 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
76814 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
76815 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
76816 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
76817 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76818 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1501:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SHSUB_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
76819 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUB_ZPmZ_D),
76820 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
76821 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76822 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76823 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76824 GIR_RootConstrainSelectedInstOperands,
76825 // GIR_Coverage, 11093,
76826 GIR_EraseRootFromParent_Done,
76827 // Label 4357: @205543
76828 GIM_Try, /*On fail goto*//*Label 4358*/ GIMT_Encode4(205585), // Rule ID 11094 //
76829 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76830 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsub),
76831 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
76832 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
76833 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
76834 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
76835 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76836 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1742:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UHSUB_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
76837 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUB_ZPmZ_B),
76838 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
76839 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76840 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76841 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76842 GIR_RootConstrainSelectedInstOperands,
76843 // GIR_Coverage, 11094,
76844 GIR_EraseRootFromParent_Done,
76845 // Label 4358: @205585
76846 GIM_Try, /*On fail goto*//*Label 4359*/ GIMT_Encode4(205627), // Rule ID 11095 //
76847 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76848 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsub),
76849 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
76850 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
76851 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
76852 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
76853 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76854 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1742:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UHSUB_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
76855 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUB_ZPmZ_H),
76856 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
76857 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76858 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76859 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76860 GIR_RootConstrainSelectedInstOperands,
76861 // GIR_Coverage, 11095,
76862 GIR_EraseRootFromParent_Done,
76863 // Label 4359: @205627
76864 GIM_Try, /*On fail goto*//*Label 4360*/ GIMT_Encode4(205669), // Rule ID 11096 //
76865 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76866 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsub),
76867 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
76868 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
76869 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
76870 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
76871 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76872 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1742:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UHSUB_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
76873 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUB_ZPmZ_S),
76874 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
76875 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76876 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76877 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76878 GIR_RootConstrainSelectedInstOperands,
76879 // GIR_Coverage, 11096,
76880 GIR_EraseRootFromParent_Done,
76881 // Label 4360: @205669
76882 GIM_Try, /*On fail goto*//*Label 4361*/ GIMT_Encode4(205711), // Rule ID 11097 //
76883 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76884 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsub),
76885 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
76886 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
76887 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
76888 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
76889 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76890 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1742:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (UHSUB_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
76891 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUB_ZPmZ_D),
76892 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
76893 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76894 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76895 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76896 GIR_RootConstrainSelectedInstOperands,
76897 // GIR_Coverage, 11097,
76898 GIR_EraseRootFromParent_Done,
76899 // Label 4361: @205711
76900 GIM_Try, /*On fail goto*//*Label 4362*/ GIMT_Encode4(205753), // Rule ID 11098 //
76901 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76902 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srhadd),
76903 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
76904 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
76905 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
76906 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
76907 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76908 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1636:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SRHADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
76909 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRHADD_ZPmZ_B),
76910 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
76911 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76912 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76913 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76914 GIR_RootConstrainSelectedInstOperands,
76915 // GIR_Coverage, 11098,
76916 GIR_EraseRootFromParent_Done,
76917 // Label 4362: @205753
76918 GIM_Try, /*On fail goto*//*Label 4363*/ GIMT_Encode4(205795), // Rule ID 11100 //
76919 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76920 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srhadd),
76921 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
76922 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
76923 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
76924 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
76925 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76926 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1636:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SRHADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
76927 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRHADD_ZPmZ_H),
76928 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
76929 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76930 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76931 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76932 GIR_RootConstrainSelectedInstOperands,
76933 // GIR_Coverage, 11100,
76934 GIR_EraseRootFromParent_Done,
76935 // Label 4363: @205795
76936 GIM_Try, /*On fail goto*//*Label 4364*/ GIMT_Encode4(205837), // Rule ID 11102 //
76937 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76938 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srhadd),
76939 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
76940 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
76941 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
76942 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
76943 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76944 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1636:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SRHADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
76945 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRHADD_ZPmZ_S),
76946 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
76947 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76948 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76949 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76950 GIR_RootConstrainSelectedInstOperands,
76951 // GIR_Coverage, 11102,
76952 GIR_EraseRootFromParent_Done,
76953 // Label 4364: @205837
76954 GIM_Try, /*On fail goto*//*Label 4365*/ GIMT_Encode4(205879), // Rule ID 11104 //
76955 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76956 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srhadd),
76957 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
76958 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
76959 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
76960 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
76961 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76962 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1636:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SRHADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
76963 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRHADD_ZPmZ_D),
76964 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
76965 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76966 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76967 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76968 GIR_RootConstrainSelectedInstOperands,
76969 // GIR_Coverage, 11104,
76970 GIR_EraseRootFromParent_Done,
76971 // Label 4365: @205879
76972 GIM_Try, /*On fail goto*//*Label 4366*/ GIMT_Encode4(205921), // Rule ID 11106 //
76973 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76974 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urhadd),
76975 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
76976 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
76977 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
76978 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
76979 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76980 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1828:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (URHADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
76981 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URHADD_ZPmZ_B),
76982 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
76983 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
76984 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
76985 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
76986 GIR_RootConstrainSelectedInstOperands,
76987 // GIR_Coverage, 11106,
76988 GIR_EraseRootFromParent_Done,
76989 // Label 4366: @205921
76990 GIM_Try, /*On fail goto*//*Label 4367*/ GIMT_Encode4(205963), // Rule ID 11108 //
76991 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
76992 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urhadd),
76993 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
76994 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
76995 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
76996 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
76997 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
76998 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1828:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (URHADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
76999 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URHADD_ZPmZ_H),
77000 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77001 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77002 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77003 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77004 GIR_RootConstrainSelectedInstOperands,
77005 // GIR_Coverage, 11108,
77006 GIR_EraseRootFromParent_Done,
77007 // Label 4367: @205963
77008 GIM_Try, /*On fail goto*//*Label 4368*/ GIMT_Encode4(206005), // Rule ID 11110 //
77009 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77010 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urhadd),
77011 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
77012 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
77013 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
77014 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
77015 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77016 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1828:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (URHADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
77017 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URHADD_ZPmZ_S),
77018 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77019 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77020 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77021 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77022 GIR_RootConstrainSelectedInstOperands,
77023 // GIR_Coverage, 11110,
77024 GIR_EraseRootFromParent_Done,
77025 // Label 4368: @206005
77026 GIM_Try, /*On fail goto*//*Label 4369*/ GIMT_Encode4(206047), // Rule ID 11112 //
77027 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77028 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urhadd),
77029 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
77030 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
77031 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
77032 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
77033 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77034 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1828:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (URHADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
77035 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URHADD_ZPmZ_D),
77036 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77037 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77038 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77039 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77040 GIR_RootConstrainSelectedInstOperands,
77041 // GIR_Coverage, 11112,
77042 GIR_EraseRootFromParent_Done,
77043 // Label 4369: @206047
77044 GIM_Try, /*On fail goto*//*Label 4370*/ GIMT_Encode4(206089), // Rule ID 11114 //
77045 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77046 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsubr),
77047 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
77048 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
77049 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
77050 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
77051 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77052 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1502:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SHSUBR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
77053 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBR_ZPmZ_B),
77054 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77055 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77056 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77057 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77058 GIR_RootConstrainSelectedInstOperands,
77059 // GIR_Coverage, 11114,
77060 GIR_EraseRootFromParent_Done,
77061 // Label 4370: @206089
77062 GIM_Try, /*On fail goto*//*Label 4371*/ GIMT_Encode4(206131), // Rule ID 11115 //
77063 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77064 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsubr),
77065 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
77066 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
77067 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
77068 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
77069 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77070 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1502:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SHSUBR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
77071 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBR_ZPmZ_H),
77072 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77073 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77074 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77075 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77076 GIR_RootConstrainSelectedInstOperands,
77077 // GIR_Coverage, 11115,
77078 GIR_EraseRootFromParent_Done,
77079 // Label 4371: @206131
77080 GIM_Try, /*On fail goto*//*Label 4372*/ GIMT_Encode4(206173), // Rule ID 11116 //
77081 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77082 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsubr),
77083 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
77084 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
77085 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
77086 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
77087 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77088 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1502:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SHSUBR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
77089 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBR_ZPmZ_S),
77090 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77091 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77092 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77093 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77094 GIR_RootConstrainSelectedInstOperands,
77095 // GIR_Coverage, 11116,
77096 GIR_EraseRootFromParent_Done,
77097 // Label 4372: @206173
77098 GIM_Try, /*On fail goto*//*Label 4373*/ GIMT_Encode4(206215), // Rule ID 11117 //
77099 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77100 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsubr),
77101 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
77102 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
77103 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
77104 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
77105 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77106 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1502:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SHSUBR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
77107 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBR_ZPmZ_D),
77108 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77109 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77110 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77111 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77112 GIR_RootConstrainSelectedInstOperands,
77113 // GIR_Coverage, 11117,
77114 GIR_EraseRootFromParent_Done,
77115 // Label 4373: @206215
77116 GIM_Try, /*On fail goto*//*Label 4374*/ GIMT_Encode4(206257), // Rule ID 11118 //
77117 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77118 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsubr),
77119 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
77120 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
77121 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
77122 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
77123 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77124 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1743:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UHSUBR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
77125 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBR_ZPmZ_B),
77126 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77127 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77128 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77129 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77130 GIR_RootConstrainSelectedInstOperands,
77131 // GIR_Coverage, 11118,
77132 GIR_EraseRootFromParent_Done,
77133 // Label 4374: @206257
77134 GIM_Try, /*On fail goto*//*Label 4375*/ GIMT_Encode4(206299), // Rule ID 11119 //
77135 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77136 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsubr),
77137 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
77138 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
77139 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
77140 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
77141 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77142 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1743:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UHSUBR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
77143 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBR_ZPmZ_H),
77144 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77145 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77146 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77147 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77148 GIR_RootConstrainSelectedInstOperands,
77149 // GIR_Coverage, 11119,
77150 GIR_EraseRootFromParent_Done,
77151 // Label 4375: @206299
77152 GIM_Try, /*On fail goto*//*Label 4376*/ GIMT_Encode4(206341), // Rule ID 11120 //
77153 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77154 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsubr),
77155 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
77156 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
77157 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
77158 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
77159 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77160 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1743:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UHSUBR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
77161 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBR_ZPmZ_S),
77162 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77163 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77164 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77165 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77166 GIR_RootConstrainSelectedInstOperands,
77167 // GIR_Coverage, 11120,
77168 GIR_EraseRootFromParent_Done,
77169 // Label 4376: @206341
77170 GIM_Try, /*On fail goto*//*Label 4377*/ GIMT_Encode4(206383), // Rule ID 11121 //
77171 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77172 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsubr),
77173 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
77174 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
77175 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
77176 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
77177 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77178 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1743:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (UHSUBR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
77179 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBR_ZPmZ_D),
77180 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77181 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77182 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77183 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77184 GIR_RootConstrainSelectedInstOperands,
77185 // GIR_Coverage, 11121,
77186 GIR_EraseRootFromParent_Done,
77187 // Label 4377: @206383
77188 GIM_Try, /*On fail goto*//*Label 4378*/ GIMT_Encode4(206425), // Rule ID 11122 //
77189 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77190 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uadalp),
77191 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
77192 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
77193 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
77194 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
77195 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77196 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1718:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UADALP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
77197 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALP_ZPmZ_H),
77198 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
77199 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77200 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77201 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77202 GIR_RootConstrainSelectedInstOperands,
77203 // GIR_Coverage, 11122,
77204 GIR_EraseRootFromParent_Done,
77205 // Label 4378: @206425
77206 GIM_Try, /*On fail goto*//*Label 4379*/ GIMT_Encode4(206467), // Rule ID 11123 //
77207 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77208 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uadalp),
77209 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
77210 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
77211 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
77212 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
77213 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77214 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1718:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UADALP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
77215 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALP_ZPmZ_S),
77216 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
77217 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77218 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77219 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77220 GIR_RootConstrainSelectedInstOperands,
77221 // GIR_Coverage, 11123,
77222 GIR_EraseRootFromParent_Done,
77223 // Label 4379: @206467
77224 GIM_Try, /*On fail goto*//*Label 4380*/ GIMT_Encode4(206509), // Rule ID 11124 //
77225 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77226 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uadalp),
77227 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
77228 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
77229 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
77230 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
77231 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77232 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1718:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UADALP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
77233 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALP_ZPmZ_D),
77234 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
77235 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77236 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77237 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77238 GIR_RootConstrainSelectedInstOperands,
77239 // GIR_Coverage, 11124,
77240 GIR_EraseRootFromParent_Done,
77241 // Label 4380: @206509
77242 GIM_Try, /*On fail goto*//*Label 4381*/ GIMT_Encode4(206551), // Rule ID 11125 //
77243 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77244 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addp),
77245 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
77246 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
77247 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
77248 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
77249 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77250 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1068:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (ADDP_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
77251 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDP_ZPmZ_B),
77252 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77253 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77254 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77255 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77256 GIR_RootConstrainSelectedInstOperands,
77257 // GIR_Coverage, 11125,
77258 GIR_EraseRootFromParent_Done,
77259 // Label 4381: @206551
77260 GIM_Try, /*On fail goto*//*Label 4382*/ GIMT_Encode4(206593), // Rule ID 11126 //
77261 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77262 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addp),
77263 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
77264 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
77265 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
77266 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
77267 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77268 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1068:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (ADDP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
77269 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDP_ZPmZ_H),
77270 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77271 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77272 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77273 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77274 GIR_RootConstrainSelectedInstOperands,
77275 // GIR_Coverage, 11126,
77276 GIR_EraseRootFromParent_Done,
77277 // Label 4382: @206593
77278 GIM_Try, /*On fail goto*//*Label 4383*/ GIMT_Encode4(206635), // Rule ID 11127 //
77279 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77280 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addp),
77281 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
77282 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
77283 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
77284 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
77285 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77286 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1068:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (ADDP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
77287 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDP_ZPmZ_S),
77288 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77289 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77290 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77291 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77292 GIR_RootConstrainSelectedInstOperands,
77293 // GIR_Coverage, 11127,
77294 GIR_EraseRootFromParent_Done,
77295 // Label 4383: @206635
77296 GIM_Try, /*On fail goto*//*Label 4384*/ GIMT_Encode4(206677), // Rule ID 11128 //
77297 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77298 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addp),
77299 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
77300 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
77301 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
77302 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
77303 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77304 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1068:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (ADDP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
77305 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDP_ZPmZ_D),
77306 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77307 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77308 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77309 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77310 GIR_RootConstrainSelectedInstOperands,
77311 // GIR_Coverage, 11128,
77312 GIR_EraseRootFromParent_Done,
77313 // Label 4384: @206677
77314 GIM_Try, /*On fail goto*//*Label 4385*/ GIMT_Encode4(206719), // Rule ID 11129 //
77315 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77316 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxp),
77317 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
77318 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
77319 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
77320 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
77321 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77322 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1512:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SMAXP_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
77323 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXP_ZPmZ_B),
77324 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77325 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77326 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77327 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77328 GIR_RootConstrainSelectedInstOperands,
77329 // GIR_Coverage, 11129,
77330 GIR_EraseRootFromParent_Done,
77331 // Label 4385: @206719
77332 GIM_Try, /*On fail goto*//*Label 4386*/ GIMT_Encode4(206761), // Rule ID 11130 //
77333 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77334 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxp),
77335 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
77336 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
77337 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
77338 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
77339 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77340 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1512:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SMAXP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
77341 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXP_ZPmZ_H),
77342 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77343 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77344 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77345 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77346 GIR_RootConstrainSelectedInstOperands,
77347 // GIR_Coverage, 11130,
77348 GIR_EraseRootFromParent_Done,
77349 // Label 4386: @206761
77350 GIM_Try, /*On fail goto*//*Label 4387*/ GIMT_Encode4(206803), // Rule ID 11131 //
77351 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77352 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxp),
77353 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
77354 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
77355 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
77356 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
77357 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77358 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1512:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SMAXP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
77359 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXP_ZPmZ_S),
77360 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77361 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77362 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77363 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77364 GIR_RootConstrainSelectedInstOperands,
77365 // GIR_Coverage, 11131,
77366 GIR_EraseRootFromParent_Done,
77367 // Label 4387: @206803
77368 GIM_Try, /*On fail goto*//*Label 4388*/ GIMT_Encode4(206845), // Rule ID 11132 //
77369 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77370 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxp),
77371 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
77372 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
77373 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
77374 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
77375 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77376 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1512:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SMAXP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
77377 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXP_ZPmZ_D),
77378 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77379 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77380 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77381 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77382 GIR_RootConstrainSelectedInstOperands,
77383 // GIR_Coverage, 11132,
77384 GIR_EraseRootFromParent_Done,
77385 // Label 4388: @206845
77386 GIM_Try, /*On fail goto*//*Label 4389*/ GIMT_Encode4(206887), // Rule ID 11133 //
77387 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77388 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxp),
77389 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
77390 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
77391 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
77392 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
77393 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77394 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1750:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UMAXP_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
77395 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXP_ZPmZ_B),
77396 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77397 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77398 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77399 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77400 GIR_RootConstrainSelectedInstOperands,
77401 // GIR_Coverage, 11133,
77402 GIR_EraseRootFromParent_Done,
77403 // Label 4389: @206887
77404 GIM_Try, /*On fail goto*//*Label 4390*/ GIMT_Encode4(206929), // Rule ID 11134 //
77405 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77406 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxp),
77407 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
77408 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
77409 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
77410 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
77411 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77412 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1750:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UMAXP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
77413 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXP_ZPmZ_H),
77414 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77415 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77416 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77417 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77418 GIR_RootConstrainSelectedInstOperands,
77419 // GIR_Coverage, 11134,
77420 GIR_EraseRootFromParent_Done,
77421 // Label 4390: @206929
77422 GIM_Try, /*On fail goto*//*Label 4391*/ GIMT_Encode4(206971), // Rule ID 11135 //
77423 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77424 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxp),
77425 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
77426 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
77427 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
77428 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
77429 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77430 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1750:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UMAXP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
77431 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXP_ZPmZ_S),
77432 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77433 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77434 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77435 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77436 GIR_RootConstrainSelectedInstOperands,
77437 // GIR_Coverage, 11135,
77438 GIR_EraseRootFromParent_Done,
77439 // Label 4391: @206971
77440 GIM_Try, /*On fail goto*//*Label 4392*/ GIMT_Encode4(207013), // Rule ID 11136 //
77441 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77442 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxp),
77443 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
77444 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
77445 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
77446 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
77447 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77448 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1750:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (UMAXP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
77449 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXP_ZPmZ_D),
77450 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77451 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77452 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77453 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77454 GIR_RootConstrainSelectedInstOperands,
77455 // GIR_Coverage, 11136,
77456 GIR_EraseRootFromParent_Done,
77457 // Label 4392: @207013
77458 GIM_Try, /*On fail goto*//*Label 4393*/ GIMT_Encode4(207055), // Rule ID 11137 //
77459 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77460 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminp),
77461 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
77462 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
77463 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
77464 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
77465 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77466 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1521:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SMINP_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
77467 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINP_ZPmZ_B),
77468 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77469 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77470 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77471 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77472 GIR_RootConstrainSelectedInstOperands,
77473 // GIR_Coverage, 11137,
77474 GIR_EraseRootFromParent_Done,
77475 // Label 4393: @207055
77476 GIM_Try, /*On fail goto*//*Label 4394*/ GIMT_Encode4(207097), // Rule ID 11138 //
77477 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77478 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminp),
77479 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
77480 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
77481 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
77482 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
77483 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77484 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1521:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SMINP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
77485 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINP_ZPmZ_H),
77486 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77487 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77488 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77489 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77490 GIR_RootConstrainSelectedInstOperands,
77491 // GIR_Coverage, 11138,
77492 GIR_EraseRootFromParent_Done,
77493 // Label 4394: @207097
77494 GIM_Try, /*On fail goto*//*Label 4395*/ GIMT_Encode4(207139), // Rule ID 11139 //
77495 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77496 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminp),
77497 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
77498 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
77499 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
77500 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
77501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77502 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1521:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SMINP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
77503 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINP_ZPmZ_S),
77504 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77505 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77506 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77507 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77508 GIR_RootConstrainSelectedInstOperands,
77509 // GIR_Coverage, 11139,
77510 GIR_EraseRootFromParent_Done,
77511 // Label 4395: @207139
77512 GIM_Try, /*On fail goto*//*Label 4396*/ GIMT_Encode4(207181), // Rule ID 11140 //
77513 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77514 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminp),
77515 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
77516 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
77517 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
77518 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
77519 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77520 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1521:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SMINP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
77521 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINP_ZPmZ_D),
77522 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77523 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77524 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77525 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77526 GIR_RootConstrainSelectedInstOperands,
77527 // GIR_Coverage, 11140,
77528 GIR_EraseRootFromParent_Done,
77529 // Label 4396: @207181
77530 GIM_Try, /*On fail goto*//*Label 4397*/ GIMT_Encode4(207223), // Rule ID 11141 //
77531 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77532 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminp),
77533 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
77534 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
77535 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
77536 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
77537 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77538 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1759:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UMINP_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
77539 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINP_ZPmZ_B),
77540 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77541 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77542 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77543 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77544 GIR_RootConstrainSelectedInstOperands,
77545 // GIR_Coverage, 11141,
77546 GIR_EraseRootFromParent_Done,
77547 // Label 4397: @207223
77548 GIM_Try, /*On fail goto*//*Label 4398*/ GIMT_Encode4(207265), // Rule ID 11142 //
77549 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77550 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminp),
77551 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
77552 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
77553 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
77554 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
77555 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77556 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1759:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UMINP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
77557 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINP_ZPmZ_H),
77558 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77559 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77560 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77561 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77562 GIR_RootConstrainSelectedInstOperands,
77563 // GIR_Coverage, 11142,
77564 GIR_EraseRootFromParent_Done,
77565 // Label 4398: @207265
77566 GIM_Try, /*On fail goto*//*Label 4399*/ GIMT_Encode4(207307), // Rule ID 11143 //
77567 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77568 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminp),
77569 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
77570 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
77571 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
77572 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
77573 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77574 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1759:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UMINP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
77575 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINP_ZPmZ_S),
77576 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77577 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77578 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77579 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77580 GIR_RootConstrainSelectedInstOperands,
77581 // GIR_Coverage, 11143,
77582 GIR_EraseRootFromParent_Done,
77583 // Label 4399: @207307
77584 GIM_Try, /*On fail goto*//*Label 4400*/ GIMT_Encode4(207349), // Rule ID 11144 //
77585 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77586 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminp),
77587 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
77588 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
77589 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
77590 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
77591 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77592 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1759:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (UMINP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
77593 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINP_ZPmZ_D),
77594 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77595 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77596 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77597 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77598 GIR_RootConstrainSelectedInstOperands,
77599 // GIR_Coverage, 11144,
77600 GIR_EraseRootFromParent_Done,
77601 // Label 4400: @207349
77602 GIM_Try, /*On fail goto*//*Label 4401*/ GIMT_Encode4(207391), // Rule ID 11145 //
77603 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77604 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ursqrte),
77605 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
77606 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
77607 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
77608 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
77609 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77610 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1835:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (URSQRTE_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
77611 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSQRTE_ZPmZ_S),
77612 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
77613 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77614 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77615 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77616 GIR_RootConstrainSelectedInstOperands,
77617 // GIR_Coverage, 11145,
77618 GIR_EraseRootFromParent_Done,
77619 // Label 4401: @207391
77620 GIM_Try, /*On fail goto*//*Label 4402*/ GIMT_Encode4(207433), // Rule ID 11156 //
77621 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77622 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
77623 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
77624 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
77625 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
77626 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
77627 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77628 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1600:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SQNEG_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
77629 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_B),
77630 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
77631 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77632 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77633 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77634 GIR_RootConstrainSelectedInstOperands,
77635 // GIR_Coverage, 11156,
77636 GIR_EraseRootFromParent_Done,
77637 // Label 4402: @207433
77638 GIM_Try, /*On fail goto*//*Label 4403*/ GIMT_Encode4(207475), // Rule ID 11157 //
77639 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77640 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
77641 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
77642 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
77643 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
77644 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
77645 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77646 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1600:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SQNEG_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
77647 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_H),
77648 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
77649 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77650 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77651 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77652 GIR_RootConstrainSelectedInstOperands,
77653 // GIR_Coverage, 11157,
77654 GIR_EraseRootFromParent_Done,
77655 // Label 4403: @207475
77656 GIM_Try, /*On fail goto*//*Label 4404*/ GIMT_Encode4(207517), // Rule ID 11158 //
77657 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77658 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
77659 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
77660 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
77661 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
77662 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
77663 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77664 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1600:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SQNEG_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
77665 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_S),
77666 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
77667 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77668 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77669 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77670 GIR_RootConstrainSelectedInstOperands,
77671 // GIR_Coverage, 11158,
77672 GIR_EraseRootFromParent_Done,
77673 // Label 4404: @207517
77674 GIM_Try, /*On fail goto*//*Label 4405*/ GIMT_Encode4(207559), // Rule ID 11159 //
77675 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77676 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
77677 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
77678 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
77679 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
77680 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
77681 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77682 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1600:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SQNEG_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
77683 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_D),
77684 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
77685 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77686 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77687 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77688 GIR_RootConstrainSelectedInstOperands,
77689 // GIR_Coverage, 11159,
77690 GIR_EraseRootFromParent_Done,
77691 // Label 4405: @207559
77692 GIM_Try, /*On fail goto*//*Label 4406*/ GIMT_Encode4(207601), // Rule ID 11168 //
77693 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77694 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqadd),
77695 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
77696 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
77697 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
77698 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
77699 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77700 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1541:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SQADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
77701 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZPmZ_B),
77702 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77703 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77704 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77705 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77706 GIR_RootConstrainSelectedInstOperands,
77707 // GIR_Coverage, 11168,
77708 GIR_EraseRootFromParent_Done,
77709 // Label 4406: @207601
77710 GIM_Try, /*On fail goto*//*Label 4407*/ GIMT_Encode4(207643), // Rule ID 11169 //
77711 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77712 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqadd),
77713 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
77714 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
77715 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
77716 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
77717 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77718 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1541:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SQADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
77719 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZPmZ_H),
77720 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77721 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77722 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77723 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77724 GIR_RootConstrainSelectedInstOperands,
77725 // GIR_Coverage, 11169,
77726 GIR_EraseRootFromParent_Done,
77727 // Label 4407: @207643
77728 GIM_Try, /*On fail goto*//*Label 4408*/ GIMT_Encode4(207685), // Rule ID 11170 //
77729 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77730 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqadd),
77731 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
77732 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
77733 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
77734 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
77735 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77736 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1541:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SQADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
77737 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZPmZ_S),
77738 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77739 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77740 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77741 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77742 GIR_RootConstrainSelectedInstOperands,
77743 // GIR_Coverage, 11170,
77744 GIR_EraseRootFromParent_Done,
77745 // Label 4408: @207685
77746 GIM_Try, /*On fail goto*//*Label 4409*/ GIMT_Encode4(207727), // Rule ID 11171 //
77747 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77748 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqadd),
77749 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
77750 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
77751 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
77752 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
77753 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77754 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1541:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SQADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
77755 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZPmZ_D),
77756 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77757 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77758 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77759 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77760 GIR_RootConstrainSelectedInstOperands,
77761 // GIR_Coverage, 11171,
77762 GIR_EraseRootFromParent_Done,
77763 // Label 4409: @207727
77764 GIM_Try, /*On fail goto*//*Label 4410*/ GIMT_Encode4(207769), // Rule ID 11172 //
77765 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77766 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqadd),
77767 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
77768 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
77769 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
77770 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
77771 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77772 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1777:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UQADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
77773 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZPmZ_B),
77774 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77775 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77776 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77777 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77778 GIR_RootConstrainSelectedInstOperands,
77779 // GIR_Coverage, 11172,
77780 GIR_EraseRootFromParent_Done,
77781 // Label 4410: @207769
77782 GIM_Try, /*On fail goto*//*Label 4411*/ GIMT_Encode4(207811), // Rule ID 11173 //
77783 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77784 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqadd),
77785 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
77786 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
77787 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
77788 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
77789 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77790 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1777:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UQADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
77791 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZPmZ_H),
77792 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77793 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77794 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77795 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77796 GIR_RootConstrainSelectedInstOperands,
77797 // GIR_Coverage, 11173,
77798 GIR_EraseRootFromParent_Done,
77799 // Label 4411: @207811
77800 GIM_Try, /*On fail goto*//*Label 4412*/ GIMT_Encode4(207853), // Rule ID 11174 //
77801 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77802 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqadd),
77803 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
77804 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
77805 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
77806 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
77807 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77808 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1777:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UQADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
77809 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZPmZ_S),
77810 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77811 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77812 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77813 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77814 GIR_RootConstrainSelectedInstOperands,
77815 // GIR_Coverage, 11174,
77816 GIR_EraseRootFromParent_Done,
77817 // Label 4412: @207853
77818 GIM_Try, /*On fail goto*//*Label 4413*/ GIMT_Encode4(207895), // Rule ID 11175 //
77819 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77820 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqadd),
77821 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
77822 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
77823 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
77824 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
77825 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77826 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1777:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (UQADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
77827 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZPmZ_D),
77828 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77829 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77830 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77831 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77832 GIR_RootConstrainSelectedInstOperands,
77833 // GIR_Coverage, 11175,
77834 GIR_EraseRootFromParent_Done,
77835 // Label 4413: @207895
77836 GIM_Try, /*On fail goto*//*Label 4414*/ GIMT_Encode4(207937), // Rule ID 11176 //
77837 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77838 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsub),
77839 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
77840 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
77841 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
77842 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
77843 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77844 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1628:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SQSUB_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
77845 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZPmZ_B),
77846 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77847 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77848 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77849 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77850 GIR_RootConstrainSelectedInstOperands,
77851 // GIR_Coverage, 11176,
77852 GIR_EraseRootFromParent_Done,
77853 // Label 4414: @207937
77854 GIM_Try, /*On fail goto*//*Label 4415*/ GIMT_Encode4(207979), // Rule ID 11177 //
77855 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77856 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsub),
77857 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
77858 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
77859 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
77860 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
77861 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77862 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1628:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SQSUB_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
77863 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZPmZ_H),
77864 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77865 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77866 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77867 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77868 GIR_RootConstrainSelectedInstOperands,
77869 // GIR_Coverage, 11177,
77870 GIR_EraseRootFromParent_Done,
77871 // Label 4415: @207979
77872 GIM_Try, /*On fail goto*//*Label 4416*/ GIMT_Encode4(208021), // Rule ID 11178 //
77873 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77874 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsub),
77875 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
77876 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
77877 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
77878 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
77879 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77880 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1628:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SQSUB_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
77881 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZPmZ_S),
77882 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77883 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77884 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77885 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77886 GIR_RootConstrainSelectedInstOperands,
77887 // GIR_Coverage, 11178,
77888 GIR_EraseRootFromParent_Done,
77889 // Label 4416: @208021
77890 GIM_Try, /*On fail goto*//*Label 4417*/ GIMT_Encode4(208063), // Rule ID 11179 //
77891 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77892 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsub),
77893 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
77894 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
77895 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
77896 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
77897 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77898 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1628:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SQSUB_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
77899 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZPmZ_D),
77900 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77901 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77902 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77903 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77904 GIR_RootConstrainSelectedInstOperands,
77905 // GIR_Coverage, 11179,
77906 GIR_EraseRootFromParent_Done,
77907 // Label 4417: @208063
77908 GIM_Try, /*On fail goto*//*Label 4418*/ GIMT_Encode4(208105), // Rule ID 11180 //
77909 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77910 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsub),
77911 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
77912 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
77913 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
77914 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
77915 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77916 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1821:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UQSUB_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
77917 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZPmZ_B),
77918 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77919 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77920 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77921 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77922 GIR_RootConstrainSelectedInstOperands,
77923 // GIR_Coverage, 11180,
77924 GIR_EraseRootFromParent_Done,
77925 // Label 4418: @208105
77926 GIM_Try, /*On fail goto*//*Label 4419*/ GIMT_Encode4(208147), // Rule ID 11181 //
77927 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77928 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsub),
77929 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
77930 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
77931 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
77932 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
77933 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77934 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1821:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UQSUB_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
77935 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZPmZ_H),
77936 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77937 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77938 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77939 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77940 GIR_RootConstrainSelectedInstOperands,
77941 // GIR_Coverage, 11181,
77942 GIR_EraseRootFromParent_Done,
77943 // Label 4419: @208147
77944 GIM_Try, /*On fail goto*//*Label 4420*/ GIMT_Encode4(208189), // Rule ID 11182 //
77945 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77946 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsub),
77947 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
77948 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
77949 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
77950 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
77951 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77952 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1821:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UQSUB_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
77953 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZPmZ_S),
77954 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77955 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77956 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77957 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77958 GIR_RootConstrainSelectedInstOperands,
77959 // GIR_Coverage, 11182,
77960 GIR_EraseRootFromParent_Done,
77961 // Label 4420: @208189
77962 GIM_Try, /*On fail goto*//*Label 4421*/ GIMT_Encode4(208231), // Rule ID 11183 //
77963 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77964 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsub),
77965 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
77966 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
77967 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
77968 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
77969 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77970 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1821:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (UQSUB_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
77971 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZPmZ_D),
77972 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77973 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77974 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77975 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77976 GIR_RootConstrainSelectedInstOperands,
77977 // GIR_Coverage, 11183,
77978 GIR_EraseRootFromParent_Done,
77979 // Label 4421: @208231
77980 GIM_Try, /*On fail goto*//*Label 4422*/ GIMT_Encode4(208273), // Rule ID 11184 //
77981 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
77982 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_suqadd),
77983 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
77984 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
77985 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
77986 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
77987 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
77988 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1692:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SUQADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
77989 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADD_ZPmZ_B),
77990 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
77991 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
77992 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
77993 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
77994 GIR_RootConstrainSelectedInstOperands,
77995 // GIR_Coverage, 11184,
77996 GIR_EraseRootFromParent_Done,
77997 // Label 4422: @208273
77998 GIM_Try, /*On fail goto*//*Label 4423*/ GIMT_Encode4(208315), // Rule ID 11185 //
77999 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78000 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_suqadd),
78001 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
78002 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
78003 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
78004 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
78005 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78006 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1692:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SUQADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
78007 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADD_ZPmZ_H),
78008 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78009 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78010 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78011 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78012 GIR_RootConstrainSelectedInstOperands,
78013 // GIR_Coverage, 11185,
78014 GIR_EraseRootFromParent_Done,
78015 // Label 4423: @208315
78016 GIM_Try, /*On fail goto*//*Label 4424*/ GIMT_Encode4(208357), // Rule ID 11186 //
78017 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78018 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_suqadd),
78019 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
78020 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
78021 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
78022 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
78023 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78024 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1692:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SUQADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
78025 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADD_ZPmZ_S),
78026 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78027 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78028 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78029 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78030 GIR_RootConstrainSelectedInstOperands,
78031 // GIR_Coverage, 11186,
78032 GIR_EraseRootFromParent_Done,
78033 // Label 4424: @208357
78034 GIM_Try, /*On fail goto*//*Label 4425*/ GIMT_Encode4(208399), // Rule ID 11187 //
78035 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78036 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_suqadd),
78037 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
78038 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
78039 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
78040 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
78041 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78042 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1692:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SUQADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
78043 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADD_ZPmZ_D),
78044 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78045 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78046 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78047 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78048 GIR_RootConstrainSelectedInstOperands,
78049 // GIR_Coverage, 11187,
78050 GIR_EraseRootFromParent_Done,
78051 // Label 4425: @208399
78052 GIM_Try, /*On fail goto*//*Label 4426*/ GIMT_Encode4(208441), // Rule ID 11188 //
78053 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78054 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usqadd),
78055 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
78056 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
78057 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
78058 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
78059 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78060 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1842:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (USQADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
78061 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADD_ZPmZ_B),
78062 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78063 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78064 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78065 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78066 GIR_RootConstrainSelectedInstOperands,
78067 // GIR_Coverage, 11188,
78068 GIR_EraseRootFromParent_Done,
78069 // Label 4426: @208441
78070 GIM_Try, /*On fail goto*//*Label 4427*/ GIMT_Encode4(208483), // Rule ID 11189 //
78071 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78072 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usqadd),
78073 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
78074 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
78075 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
78076 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
78077 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78078 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1842:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (USQADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
78079 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADD_ZPmZ_H),
78080 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78081 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78082 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78083 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78084 GIR_RootConstrainSelectedInstOperands,
78085 // GIR_Coverage, 11189,
78086 GIR_EraseRootFromParent_Done,
78087 // Label 4427: @208483
78088 GIM_Try, /*On fail goto*//*Label 4428*/ GIMT_Encode4(208525), // Rule ID 11190 //
78089 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78090 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usqadd),
78091 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
78092 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
78093 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
78094 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
78095 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78096 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1842:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (USQADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
78097 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADD_ZPmZ_S),
78098 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78099 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78100 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78101 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78102 GIR_RootConstrainSelectedInstOperands,
78103 // GIR_Coverage, 11190,
78104 GIR_EraseRootFromParent_Done,
78105 // Label 4428: @208525
78106 GIM_Try, /*On fail goto*//*Label 4429*/ GIMT_Encode4(208567), // Rule ID 11191 //
78107 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78108 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usqadd),
78109 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
78110 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
78111 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
78112 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
78113 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78114 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1842:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (USQADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
78115 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADD_ZPmZ_D),
78116 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78117 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78118 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78119 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78120 GIR_RootConstrainSelectedInstOperands,
78121 // GIR_Coverage, 11191,
78122 GIR_EraseRootFromParent_Done,
78123 // Label 4429: @208567
78124 GIM_Try, /*On fail goto*//*Label 4430*/ GIMT_Encode4(208609), // Rule ID 11192 //
78125 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78126 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsubr),
78127 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
78128 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
78129 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
78130 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
78131 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78132 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1631:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SQSUBR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
78133 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBR_ZPmZ_B),
78134 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78135 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78136 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78137 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78138 GIR_RootConstrainSelectedInstOperands,
78139 // GIR_Coverage, 11192,
78140 GIR_EraseRootFromParent_Done,
78141 // Label 4430: @208609
78142 GIM_Try, /*On fail goto*//*Label 4431*/ GIMT_Encode4(208651), // Rule ID 11193 //
78143 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78144 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsubr),
78145 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
78146 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
78147 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
78148 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
78149 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78150 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1631:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SQSUBR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
78151 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBR_ZPmZ_H),
78152 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78153 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78154 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78155 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78156 GIR_RootConstrainSelectedInstOperands,
78157 // GIR_Coverage, 11193,
78158 GIR_EraseRootFromParent_Done,
78159 // Label 4431: @208651
78160 GIM_Try, /*On fail goto*//*Label 4432*/ GIMT_Encode4(208693), // Rule ID 11194 //
78161 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78162 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsubr),
78163 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
78164 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
78165 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
78166 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
78167 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78168 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1631:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SQSUBR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
78169 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBR_ZPmZ_S),
78170 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78171 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78172 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78173 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78174 GIR_RootConstrainSelectedInstOperands,
78175 // GIR_Coverage, 11194,
78176 GIR_EraseRootFromParent_Done,
78177 // Label 4432: @208693
78178 GIM_Try, /*On fail goto*//*Label 4433*/ GIMT_Encode4(208735), // Rule ID 11195 //
78179 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78180 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsubr),
78181 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
78182 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
78183 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
78184 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
78185 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78186 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1631:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SQSUBR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
78187 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBR_ZPmZ_D),
78188 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78189 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78190 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78191 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78192 GIR_RootConstrainSelectedInstOperands,
78193 // GIR_Coverage, 11195,
78194 GIR_EraseRootFromParent_Done,
78195 // Label 4433: @208735
78196 GIM_Try, /*On fail goto*//*Label 4434*/ GIMT_Encode4(208777), // Rule ID 11196 //
78197 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78198 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsubr),
78199 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
78200 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
78201 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
78202 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
78203 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78204 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1824:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UQSUBR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
78205 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBR_ZPmZ_B),
78206 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78207 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78208 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78209 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78210 GIR_RootConstrainSelectedInstOperands,
78211 // GIR_Coverage, 11196,
78212 GIR_EraseRootFromParent_Done,
78213 // Label 4434: @208777
78214 GIM_Try, /*On fail goto*//*Label 4435*/ GIMT_Encode4(208819), // Rule ID 11197 //
78215 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78216 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsubr),
78217 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
78218 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
78219 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
78220 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
78221 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78222 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1824:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UQSUBR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
78223 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBR_ZPmZ_H),
78224 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78225 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78226 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78227 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78228 GIR_RootConstrainSelectedInstOperands,
78229 // GIR_Coverage, 11197,
78230 GIR_EraseRootFromParent_Done,
78231 // Label 4435: @208819
78232 GIM_Try, /*On fail goto*//*Label 4436*/ GIMT_Encode4(208861), // Rule ID 11198 //
78233 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78234 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsubr),
78235 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
78236 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
78237 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
78238 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
78239 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78240 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1824:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UQSUBR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
78241 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBR_ZPmZ_S),
78242 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78243 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78244 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78245 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78246 GIR_RootConstrainSelectedInstOperands,
78247 // GIR_Coverage, 11198,
78248 GIR_EraseRootFromParent_Done,
78249 // Label 4436: @208861
78250 GIM_Try, /*On fail goto*//*Label 4437*/ GIMT_Encode4(208903), // Rule ID 11199 //
78251 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78252 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsubr),
78253 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
78254 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
78255 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
78256 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
78257 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78258 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1824:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (UQSUBR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
78259 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBR_ZPmZ_D),
78260 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78261 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78262 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78263 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78264 GIR_RootConstrainSelectedInstOperands,
78265 // GIR_Coverage, 11199,
78266 GIR_EraseRootFromParent_Done,
78267 // Label 4437: @208903
78268 GIM_Try, /*On fail goto*//*Label 4438*/ GIMT_Encode4(208945), // Rule ID 11200 //
78269 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78270 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshl),
78271 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
78272 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
78273 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
78274 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
78275 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78276 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1638:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SRSHL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
78277 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHL_ZPmZ_B),
78278 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78279 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78280 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78281 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78282 GIR_RootConstrainSelectedInstOperands,
78283 // GIR_Coverage, 11200,
78284 GIR_EraseRootFromParent_Done,
78285 // Label 4438: @208945
78286 GIM_Try, /*On fail goto*//*Label 4439*/ GIMT_Encode4(208987), // Rule ID 11201 //
78287 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78288 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshl),
78289 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
78290 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
78291 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
78292 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
78293 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78294 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1638:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SRSHL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
78295 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHL_ZPmZ_H),
78296 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78297 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78298 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78299 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78300 GIR_RootConstrainSelectedInstOperands,
78301 // GIR_Coverage, 11201,
78302 GIR_EraseRootFromParent_Done,
78303 // Label 4439: @208987
78304 GIM_Try, /*On fail goto*//*Label 4440*/ GIMT_Encode4(209029), // Rule ID 11202 //
78305 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78306 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshl),
78307 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
78308 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
78309 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
78310 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
78311 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78312 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1638:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SRSHL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
78313 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHL_ZPmZ_S),
78314 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78315 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78316 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78317 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78318 GIR_RootConstrainSelectedInstOperands,
78319 // GIR_Coverage, 11202,
78320 GIR_EraseRootFromParent_Done,
78321 // Label 4440: @209029
78322 GIM_Try, /*On fail goto*//*Label 4441*/ GIMT_Encode4(209071), // Rule ID 11203 //
78323 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78324 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshl),
78325 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
78326 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
78327 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
78328 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
78329 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78330 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1638:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SRSHL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
78331 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHL_ZPmZ_D),
78332 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78333 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78334 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78335 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78336 GIR_RootConstrainSelectedInstOperands,
78337 // GIR_Coverage, 11203,
78338 GIR_EraseRootFromParent_Done,
78339 // Label 4441: @209071
78340 GIM_Try, /*On fail goto*//*Label 4442*/ GIMT_Encode4(209113), // Rule ID 11204 //
78341 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78342 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshl),
78343 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
78344 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
78345 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
78346 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
78347 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78348 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1829:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (URSHL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
78349 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHL_ZPmZ_B),
78350 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78351 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78352 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78353 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78354 GIR_RootConstrainSelectedInstOperands,
78355 // GIR_Coverage, 11204,
78356 GIR_EraseRootFromParent_Done,
78357 // Label 4442: @209113
78358 GIM_Try, /*On fail goto*//*Label 4443*/ GIMT_Encode4(209155), // Rule ID 11205 //
78359 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78360 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshl),
78361 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
78362 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
78363 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
78364 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
78365 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78366 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1829:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (URSHL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
78367 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHL_ZPmZ_H),
78368 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78369 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78370 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78371 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78372 GIR_RootConstrainSelectedInstOperands,
78373 // GIR_Coverage, 11205,
78374 GIR_EraseRootFromParent_Done,
78375 // Label 4443: @209155
78376 GIM_Try, /*On fail goto*//*Label 4444*/ GIMT_Encode4(209197), // Rule ID 11206 //
78377 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78378 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshl),
78379 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
78380 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
78381 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
78382 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
78383 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78384 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1829:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (URSHL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
78385 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHL_ZPmZ_S),
78386 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78387 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78388 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78389 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78390 GIR_RootConstrainSelectedInstOperands,
78391 // GIR_Coverage, 11206,
78392 GIR_EraseRootFromParent_Done,
78393 // Label 4444: @209197
78394 GIM_Try, /*On fail goto*//*Label 4445*/ GIMT_Encode4(209239), // Rule ID 11207 //
78395 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78396 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshl),
78397 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
78398 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
78399 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
78400 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
78401 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78402 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1829:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (URSHL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
78403 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHL_ZPmZ_D),
78404 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78405 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78406 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78407 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78408 GIR_RootConstrainSelectedInstOperands,
78409 // GIR_Coverage, 11207,
78410 GIR_EraseRootFromParent_Done,
78411 // Label 4445: @209239
78412 GIM_Try, /*On fail goto*//*Label 4446*/ GIMT_Encode4(209281), // Rule ID 11208 //
78413 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78414 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshl),
78415 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
78416 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
78417 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
78418 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
78419 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78420 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1622:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SQSHL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
78421 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHL_ZPmZ_B),
78422 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78423 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78424 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78425 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78426 GIR_RootConstrainSelectedInstOperands,
78427 // GIR_Coverage, 11208,
78428 GIR_EraseRootFromParent_Done,
78429 // Label 4446: @209281
78430 GIM_Try, /*On fail goto*//*Label 4447*/ GIMT_Encode4(209323), // Rule ID 11209 //
78431 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78432 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshl),
78433 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
78434 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
78435 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
78436 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
78437 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78438 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1622:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SQSHL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
78439 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHL_ZPmZ_H),
78440 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78441 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78442 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78443 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78444 GIR_RootConstrainSelectedInstOperands,
78445 // GIR_Coverage, 11209,
78446 GIR_EraseRootFromParent_Done,
78447 // Label 4447: @209323
78448 GIM_Try, /*On fail goto*//*Label 4448*/ GIMT_Encode4(209365), // Rule ID 11210 //
78449 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78450 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshl),
78451 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
78452 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
78453 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
78454 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
78455 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78456 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1622:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SQSHL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
78457 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHL_ZPmZ_S),
78458 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78459 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78460 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78461 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78462 GIR_RootConstrainSelectedInstOperands,
78463 // GIR_Coverage, 11210,
78464 GIR_EraseRootFromParent_Done,
78465 // Label 4448: @209365
78466 GIM_Try, /*On fail goto*//*Label 4449*/ GIMT_Encode4(209407), // Rule ID 11211 //
78467 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78468 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshl),
78469 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
78470 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
78471 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
78472 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
78473 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78474 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1622:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SQSHL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
78475 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHL_ZPmZ_D),
78476 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78477 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78478 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78479 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78480 GIR_RootConstrainSelectedInstOperands,
78481 // GIR_Coverage, 11211,
78482 GIR_EraseRootFromParent_Done,
78483 // Label 4449: @209407
78484 GIM_Try, /*On fail goto*//*Label 4450*/ GIMT_Encode4(209449), // Rule ID 11212 //
78485 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78486 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshl),
78487 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
78488 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
78489 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
78490 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
78491 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78492 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1818:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UQSHL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
78493 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHL_ZPmZ_B),
78494 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78495 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78496 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78497 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78498 GIR_RootConstrainSelectedInstOperands,
78499 // GIR_Coverage, 11212,
78500 GIR_EraseRootFromParent_Done,
78501 // Label 4450: @209449
78502 GIM_Try, /*On fail goto*//*Label 4451*/ GIMT_Encode4(209491), // Rule ID 11213 //
78503 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78504 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshl),
78505 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
78506 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
78507 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
78508 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
78509 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78510 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1818:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UQSHL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
78511 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHL_ZPmZ_H),
78512 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78513 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78514 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78515 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78516 GIR_RootConstrainSelectedInstOperands,
78517 // GIR_Coverage, 11213,
78518 GIR_EraseRootFromParent_Done,
78519 // Label 4451: @209491
78520 GIM_Try, /*On fail goto*//*Label 4452*/ GIMT_Encode4(209533), // Rule ID 11214 //
78521 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78522 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshl),
78523 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
78524 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
78525 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
78526 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
78527 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78528 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1818:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UQSHL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
78529 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHL_ZPmZ_S),
78530 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78531 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78532 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78533 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78534 GIR_RootConstrainSelectedInstOperands,
78535 // GIR_Coverage, 11214,
78536 GIR_EraseRootFromParent_Done,
78537 // Label 4452: @209533
78538 GIM_Try, /*On fail goto*//*Label 4453*/ GIMT_Encode4(209575), // Rule ID 11215 //
78539 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78540 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshl),
78541 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
78542 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
78543 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
78544 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
78545 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78546 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1818:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (UQSHL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
78547 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHL_ZPmZ_D),
78548 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78549 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78550 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78551 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78552 GIR_RootConstrainSelectedInstOperands,
78553 // GIR_Coverage, 11215,
78554 GIR_EraseRootFromParent_Done,
78555 // Label 4453: @209575
78556 GIM_Try, /*On fail goto*//*Label 4454*/ GIMT_Encode4(209617), // Rule ID 11216 //
78557 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78558 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshl),
78559 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
78560 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
78561 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
78562 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
78563 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78564 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1609:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SQRSHL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
78565 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHL_ZPmZ_B),
78566 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78567 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78568 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78569 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78570 GIR_RootConstrainSelectedInstOperands,
78571 // GIR_Coverage, 11216,
78572 GIR_EraseRootFromParent_Done,
78573 // Label 4454: @209617
78574 GIM_Try, /*On fail goto*//*Label 4455*/ GIMT_Encode4(209659), // Rule ID 11217 //
78575 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78576 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshl),
78577 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
78578 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
78579 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
78580 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
78581 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78582 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1609:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SQRSHL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
78583 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHL_ZPmZ_H),
78584 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78585 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78586 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78587 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78588 GIR_RootConstrainSelectedInstOperands,
78589 // GIR_Coverage, 11217,
78590 GIR_EraseRootFromParent_Done,
78591 // Label 4455: @209659
78592 GIM_Try, /*On fail goto*//*Label 4456*/ GIMT_Encode4(209701), // Rule ID 11218 //
78593 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78594 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshl),
78595 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
78596 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
78597 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
78598 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
78599 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78600 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1609:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SQRSHL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
78601 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHL_ZPmZ_S),
78602 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78603 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78604 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78605 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78606 GIR_RootConstrainSelectedInstOperands,
78607 // GIR_Coverage, 11218,
78608 GIR_EraseRootFromParent_Done,
78609 // Label 4456: @209701
78610 GIM_Try, /*On fail goto*//*Label 4457*/ GIMT_Encode4(209743), // Rule ID 11219 //
78611 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78612 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshl),
78613 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
78614 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
78615 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
78616 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
78617 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78618 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1609:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SQRSHL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
78619 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHL_ZPmZ_D),
78620 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78621 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78622 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78623 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78624 GIR_RootConstrainSelectedInstOperands,
78625 // GIR_Coverage, 11219,
78626 GIR_EraseRootFromParent_Done,
78627 // Label 4457: @209743
78628 GIM_Try, /*On fail goto*//*Label 4458*/ GIMT_Encode4(209785), // Rule ID 11220 //
78629 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78630 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshl),
78631 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
78632 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
78633 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
78634 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
78635 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78636 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1811:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UQRSHL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
78637 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHL_ZPmZ_B),
78638 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78639 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78640 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78641 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78642 GIR_RootConstrainSelectedInstOperands,
78643 // GIR_Coverage, 11220,
78644 GIR_EraseRootFromParent_Done,
78645 // Label 4458: @209785
78646 GIM_Try, /*On fail goto*//*Label 4459*/ GIMT_Encode4(209827), // Rule ID 11221 //
78647 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78648 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshl),
78649 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
78650 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
78651 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
78652 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
78653 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78654 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1811:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UQRSHL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
78655 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHL_ZPmZ_H),
78656 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78657 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78658 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78659 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78660 GIR_RootConstrainSelectedInstOperands,
78661 // GIR_Coverage, 11221,
78662 GIR_EraseRootFromParent_Done,
78663 // Label 4459: @209827
78664 GIM_Try, /*On fail goto*//*Label 4460*/ GIMT_Encode4(209869), // Rule ID 11222 //
78665 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78666 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshl),
78667 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
78668 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
78669 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
78670 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
78671 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78672 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1811:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UQRSHL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
78673 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHL_ZPmZ_S),
78674 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78675 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78676 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78677 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78678 GIR_RootConstrainSelectedInstOperands,
78679 // GIR_Coverage, 11222,
78680 GIR_EraseRootFromParent_Done,
78681 // Label 4460: @209869
78682 GIM_Try, /*On fail goto*//*Label 4461*/ GIMT_Encode4(209911), // Rule ID 11223 //
78683 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78684 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshl),
78685 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
78686 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
78687 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
78688 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
78689 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78690 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1811:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (UQRSHL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
78691 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHL_ZPmZ_D),
78692 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
78693 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78694 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78695 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78696 GIR_RootConstrainSelectedInstOperands,
78697 // GIR_Coverage, 11223,
78698 GIR_EraseRootFromParent_Done,
78699 // Label 4461: @209911
78700 GIM_Try, /*On fail goto*//*Label 4462*/ GIMT_Encode4(209953), // Rule ID 11386 //
78701 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78702 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaba),
78703 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
78704 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
78705 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
78706 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
78707 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78708 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1711:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UABA_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
78709 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABA_ZZZ_B),
78710 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
78711 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78712 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78713 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78714 GIR_RootConstrainSelectedInstOperands,
78715 // GIR_Coverage, 11386,
78716 GIR_EraseRootFromParent_Done,
78717 // Label 4462: @209953
78718 GIM_Try, /*On fail goto*//*Label 4463*/ GIMT_Encode4(209995), // Rule ID 11388 //
78719 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78720 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaba),
78721 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
78722 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
78723 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
78724 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
78725 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78726 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1711:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UABA_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
78727 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABA_ZZZ_H),
78728 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
78729 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78730 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78731 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78732 GIR_RootConstrainSelectedInstOperands,
78733 // GIR_Coverage, 11388,
78734 GIR_EraseRootFromParent_Done,
78735 // Label 4463: @209995
78736 GIM_Try, /*On fail goto*//*Label 4464*/ GIMT_Encode4(210037), // Rule ID 11390 //
78737 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78738 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaba),
78739 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
78740 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
78741 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
78742 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
78743 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78744 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1711:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UABA_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
78745 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABA_ZZZ_S),
78746 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
78747 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78748 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78749 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78750 GIR_RootConstrainSelectedInstOperands,
78751 // GIR_Coverage, 11390,
78752 GIR_EraseRootFromParent_Done,
78753 // Label 4464: @210037
78754 GIM_Try, /*On fail goto*//*Label 4465*/ GIMT_Encode4(210079), // Rule ID 11392 //
78755 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78756 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaba),
78757 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
78758 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
78759 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
78760 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
78761 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78762 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1711:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (UABA_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
78763 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABA_ZZZ_D),
78764 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
78765 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78766 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78767 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78768 GIR_RootConstrainSelectedInstOperands,
78769 // GIR_Coverage, 11392,
78770 GIR_EraseRootFromParent_Done,
78771 // Label 4465: @210079
78772 GIM_Try, /*On fail goto*//*Label 4466*/ GIMT_Encode4(210121), // Rule ID 11394 //
78773 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78774 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabalt),
78775 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
78776 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
78777 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
78778 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
78779 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78780 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1463:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SABALT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
78781 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALT_ZZZ_H),
78782 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
78783 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78784 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78785 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78786 GIR_RootConstrainSelectedInstOperands,
78787 // GIR_Coverage, 11394,
78788 GIR_EraseRootFromParent_Done,
78789 // Label 4466: @210121
78790 GIM_Try, /*On fail goto*//*Label 4467*/ GIMT_Encode4(210163), // Rule ID 11395 //
78791 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78792 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabalt),
78793 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
78794 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
78795 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
78796 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
78797 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78798 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1463:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SABALT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
78799 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALT_ZZZ_S),
78800 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
78801 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78802 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78803 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78804 GIR_RootConstrainSelectedInstOperands,
78805 // GIR_Coverage, 11395,
78806 GIR_EraseRootFromParent_Done,
78807 // Label 4467: @210163
78808 GIM_Try, /*On fail goto*//*Label 4468*/ GIMT_Encode4(210205), // Rule ID 11396 //
78809 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78810 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabalt),
78811 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
78812 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
78813 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
78814 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
78815 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78816 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1463:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SABALT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
78817 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALT_ZZZ_D),
78818 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
78819 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78820 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78821 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78822 GIR_RootConstrainSelectedInstOperands,
78823 // GIR_Coverage, 11396,
78824 GIR_EraseRootFromParent_Done,
78825 // Label 4468: @210205
78826 GIM_Try, /*On fail goto*//*Label 4469*/ GIMT_Encode4(210247), // Rule ID 11397 //
78827 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78828 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabalb),
78829 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
78830 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
78831 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
78832 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
78833 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78834 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1712:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UABALB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
78835 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALB_ZZZ_H),
78836 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
78837 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78838 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78839 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78840 GIR_RootConstrainSelectedInstOperands,
78841 // GIR_Coverage, 11397,
78842 GIR_EraseRootFromParent_Done,
78843 // Label 4469: @210247
78844 GIM_Try, /*On fail goto*//*Label 4470*/ GIMT_Encode4(210289), // Rule ID 11398 //
78845 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78846 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabalb),
78847 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
78848 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
78849 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
78850 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
78851 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78852 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1712:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UABALB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
78853 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALB_ZZZ_S),
78854 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
78855 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78856 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78857 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78858 GIR_RootConstrainSelectedInstOperands,
78859 // GIR_Coverage, 11398,
78860 GIR_EraseRootFromParent_Done,
78861 // Label 4470: @210289
78862 GIM_Try, /*On fail goto*//*Label 4471*/ GIMT_Encode4(210331), // Rule ID 11399 //
78863 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78864 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabalb),
78865 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
78866 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
78867 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
78868 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
78869 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78870 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1712:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UABALB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
78871 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALB_ZZZ_D),
78872 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
78873 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78874 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78875 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78876 GIR_RootConstrainSelectedInstOperands,
78877 // GIR_Coverage, 11399,
78878 GIR_EraseRootFromParent_Done,
78879 // Label 4471: @210331
78880 GIM_Try, /*On fail goto*//*Label 4472*/ GIMT_Encode4(210373), // Rule ID 11400 //
78881 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78882 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabalt),
78883 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
78884 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
78885 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
78886 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
78887 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78888 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1713:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UABALT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
78889 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALT_ZZZ_H),
78890 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
78891 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78892 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78893 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78894 GIR_RootConstrainSelectedInstOperands,
78895 // GIR_Coverage, 11400,
78896 GIR_EraseRootFromParent_Done,
78897 // Label 4472: @210373
78898 GIM_Try, /*On fail goto*//*Label 4473*/ GIMT_Encode4(210415), // Rule ID 11401 //
78899 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78900 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabalt),
78901 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
78902 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
78903 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
78904 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
78905 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78906 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1713:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UABALT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
78907 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALT_ZZZ_S),
78908 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
78909 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78910 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78911 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78912 GIR_RootConstrainSelectedInstOperands,
78913 // GIR_Coverage, 11401,
78914 GIR_EraseRootFromParent_Done,
78915 // Label 4473: @210415
78916 GIM_Try, /*On fail goto*//*Label 4474*/ GIMT_Encode4(210457), // Rule ID 11402 //
78917 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78918 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabalt),
78919 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
78920 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
78921 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
78922 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
78923 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78924 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1713:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UABALT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
78925 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALT_ZZZ_D),
78926 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
78927 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78928 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78929 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78930 GIR_RootConstrainSelectedInstOperands,
78931 // GIR_Coverage, 11402,
78932 GIR_EraseRootFromParent_Done,
78933 // Label 4474: @210457
78934 GIM_Try, /*On fail goto*//*Label 4475*/ GIMT_Encode4(210499), // Rule ID 11403 //
78935 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78936 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adclt),
78937 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
78938 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
78939 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
78940 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
78941 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78942 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1061:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (ADCLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
78943 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADCLT_ZZZ_S),
78944 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
78945 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78946 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78947 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78948 GIR_RootConstrainSelectedInstOperands,
78949 // GIR_Coverage, 11403,
78950 GIR_EraseRootFromParent_Done,
78951 // Label 4475: @210499
78952 GIM_Try, /*On fail goto*//*Label 4476*/ GIMT_Encode4(210541), // Rule ID 11404 //
78953 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78954 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adclt),
78955 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
78956 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
78957 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
78958 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
78959 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78960 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1061:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (ADCLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
78961 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADCLT_ZZZ_D),
78962 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
78963 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78964 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78965 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78966 GIR_RootConstrainSelectedInstOperands,
78967 // GIR_Coverage, 11404,
78968 GIR_EraseRootFromParent_Done,
78969 // Label 4476: @210541
78970 GIM_Try, /*On fail goto*//*Label 4477*/ GIMT_Encode4(210583), // Rule ID 11405 //
78971 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78972 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sbclb),
78973 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
78974 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
78975 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
78976 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
78977 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78978 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1475:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SBCLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
78979 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBCLB_ZZZ_S),
78980 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
78981 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
78982 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
78983 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
78984 GIR_RootConstrainSelectedInstOperands,
78985 // GIR_Coverage, 11405,
78986 GIR_EraseRootFromParent_Done,
78987 // Label 4477: @210583
78988 GIM_Try, /*On fail goto*//*Label 4478*/ GIMT_Encode4(210625), // Rule ID 11406 //
78989 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
78990 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sbclb),
78991 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
78992 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
78993 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
78994 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
78995 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
78996 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1475:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SBCLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
78997 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBCLB_ZZZ_D),
78998 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
78999 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79000 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79001 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79002 GIR_RootConstrainSelectedInstOperands,
79003 // GIR_Coverage, 11406,
79004 GIR_EraseRootFromParent_Done,
79005 // Label 4478: @210625
79006 GIM_Try, /*On fail goto*//*Label 4479*/ GIMT_Encode4(210667), // Rule ID 11407 //
79007 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79008 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sbclt),
79009 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
79010 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
79011 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
79012 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
79013 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79014 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1476:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SBCLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
79015 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBCLT_ZZZ_S),
79016 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
79017 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79018 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79019 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79020 GIR_RootConstrainSelectedInstOperands,
79021 // GIR_Coverage, 11407,
79022 GIR_EraseRootFromParent_Done,
79023 // Label 4479: @210667
79024 GIM_Try, /*On fail goto*//*Label 4480*/ GIMT_Encode4(210709), // Rule ID 11408 //
79025 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79026 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sbclt),
79027 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
79028 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
79029 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
79030 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
79031 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79032 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1476:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SBCLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
79033 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBCLT_ZZZ_D),
79034 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
79035 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79036 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79037 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79038 GIR_RootConstrainSelectedInstOperands,
79039 // GIR_Coverage, 11408,
79040 GIR_EraseRootFromParent_Done,
79041 // Label 4480: @210709
79042 GIM_Try, /*On fail goto*//*Label 4481*/ GIMT_Encode4(210751), // Rule ID 11463 //
79043 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79044 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_raddhnt),
79045 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
79046 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
79047 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
79048 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
79049 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79050 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1444:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (RADDHNT_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
79051 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNT_ZZZ_B),
79052 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
79053 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79054 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79055 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79056 GIR_RootConstrainSelectedInstOperands,
79057 // GIR_Coverage, 11463,
79058 GIR_EraseRootFromParent_Done,
79059 // Label 4481: @210751
79060 GIM_Try, /*On fail goto*//*Label 4482*/ GIMT_Encode4(210793), // Rule ID 11464 //
79061 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79062 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_raddhnt),
79063 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
79064 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
79065 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
79066 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
79067 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79068 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1444:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (RADDHNT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
79069 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNT_ZZZ_H),
79070 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
79071 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79072 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79073 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79074 GIR_RootConstrainSelectedInstOperands,
79075 // GIR_Coverage, 11464,
79076 GIR_EraseRootFromParent_Done,
79077 // Label 4482: @210793
79078 GIM_Try, /*On fail goto*//*Label 4483*/ GIMT_Encode4(210835), // Rule ID 11465 //
79079 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79080 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_raddhnt),
79081 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
79082 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
79083 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
79084 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
79085 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79086 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1444:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (RADDHNT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
79087 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNT_ZZZ_S),
79088 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
79089 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79090 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79091 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79092 GIR_RootConstrainSelectedInstOperands,
79093 // GIR_Coverage, 11465,
79094 GIR_EraseRootFromParent_Done,
79095 // Label 4483: @210835
79096 GIM_Try, /*On fail goto*//*Label 4484*/ GIMT_Encode4(210877), // Rule ID 11466 //
79097 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79098 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subhnt),
79099 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
79100 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
79101 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
79102 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
79103 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79104 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1685:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SUBHNT_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
79105 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNT_ZZZ_B),
79106 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
79107 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79108 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79109 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79110 GIR_RootConstrainSelectedInstOperands,
79111 // GIR_Coverage, 11466,
79112 GIR_EraseRootFromParent_Done,
79113 // Label 4484: @210877
79114 GIM_Try, /*On fail goto*//*Label 4485*/ GIMT_Encode4(210919), // Rule ID 11467 //
79115 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79116 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subhnt),
79117 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
79118 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
79119 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
79120 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
79121 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79122 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1685:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SUBHNT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
79123 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNT_ZZZ_H),
79124 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
79125 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79126 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79127 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79128 GIR_RootConstrainSelectedInstOperands,
79129 // GIR_Coverage, 11467,
79130 GIR_EraseRootFromParent_Done,
79131 // Label 4485: @210919
79132 GIM_Try, /*On fail goto*//*Label 4486*/ GIMT_Encode4(210961), // Rule ID 11468 //
79133 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79134 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subhnt),
79135 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
79136 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
79137 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
79138 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
79139 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79140 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1685:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SUBHNT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
79141 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNT_ZZZ_S),
79142 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
79143 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79144 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79145 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79146 GIR_RootConstrainSelectedInstOperands,
79147 // GIR_Coverage, 11468,
79148 GIR_EraseRootFromParent_Done,
79149 // Label 4486: @210961
79150 GIM_Try, /*On fail goto*//*Label 4487*/ GIMT_Encode4(211003), // Rule ID 11469 //
79151 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79152 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rsubhnt),
79153 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
79154 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
79155 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
79156 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
79157 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79158 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1460:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (RSUBHNT_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
79159 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNT_ZZZ_B),
79160 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
79161 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79162 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79163 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79164 GIR_RootConstrainSelectedInstOperands,
79165 // GIR_Coverage, 11469,
79166 GIR_EraseRootFromParent_Done,
79167 // Label 4487: @211003
79168 GIM_Try, /*On fail goto*//*Label 4488*/ GIMT_Encode4(211045), // Rule ID 11470 //
79169 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79170 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rsubhnt),
79171 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
79172 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
79173 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
79174 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
79175 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79176 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1460:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (RSUBHNT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
79177 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNT_ZZZ_H),
79178 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
79179 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79180 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79181 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79182 GIR_RootConstrainSelectedInstOperands,
79183 // GIR_Coverage, 11470,
79184 GIR_EraseRootFromParent_Done,
79185 // Label 4488: @211045
79186 GIM_Try, /*On fail goto*//*Label 4489*/ GIMT_Encode4(211087), // Rule ID 11471 //
79187 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79188 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rsubhnt),
79189 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
79190 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
79191 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
79192 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
79193 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79194 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1460:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (RSUBHNT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
79195 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNT_ZZZ_S),
79196 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
79197 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79198 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79199 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79200 GIR_RootConstrainSelectedInstOperands,
79201 // GIR_Coverage, 11471,
79202 GIR_EraseRootFromParent_Done,
79203 // Label 4489: @211087
79204 GIM_Try, /*On fail goto*//*Label 4490*/ GIMT_Encode4(211132), // Rule ID 11484 //
79205 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
79206 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nmatch),
79207 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
79208 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
79209 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
79210 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
79211 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
79212 // (intrinsic_wo_chain:{ *:[nxv16i1] } 1395:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (NMATCH_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
79213 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NMATCH_PPzZZ_B),
79214 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
79215 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79216 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79217 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79218 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
79219 GIR_RootConstrainSelectedInstOperands,
79220 // GIR_Coverage, 11484,
79221 GIR_EraseRootFromParent_Done,
79222 // Label 4490: @211132
79223 GIM_Try, /*On fail goto*//*Label 4491*/ GIMT_Encode4(211177), // Rule ID 11485 //
79224 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
79225 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nmatch),
79226 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
79227 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
79228 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
79229 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
79230 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
79231 // (intrinsic_wo_chain:{ *:[nxv8i1] } 1395:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (NMATCH_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
79232 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NMATCH_PPzZZ_H),
79233 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
79234 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79235 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79236 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79237 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
79238 GIR_RootConstrainSelectedInstOperands,
79239 // GIR_Coverage, 11485,
79240 GIR_EraseRootFromParent_Done,
79241 // Label 4491: @211177
79242 GIM_Try, /*On fail goto*//*Label 4492*/ GIMT_Encode4(211219), // Rule ID 11486 //
79243 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79244 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eortb),
79245 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
79246 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
79247 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
79248 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
79249 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79250 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1170:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (EORTB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
79251 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORTB_ZZZ_B),
79252 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
79253 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79254 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79255 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79256 GIR_RootConstrainSelectedInstOperands,
79257 // GIR_Coverage, 11486,
79258 GIR_EraseRootFromParent_Done,
79259 // Label 4492: @211219
79260 GIM_Try, /*On fail goto*//*Label 4493*/ GIMT_Encode4(211261), // Rule ID 11487 //
79261 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79262 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eortb),
79263 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
79264 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
79265 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
79266 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
79267 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79268 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1170:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (EORTB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
79269 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORTB_ZZZ_H),
79270 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
79271 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79272 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79273 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79274 GIR_RootConstrainSelectedInstOperands,
79275 // GIR_Coverage, 11487,
79276 GIR_EraseRootFromParent_Done,
79277 // Label 4493: @211261
79278 GIM_Try, /*On fail goto*//*Label 4494*/ GIMT_Encode4(211303), // Rule ID 11488 //
79279 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79280 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eortb),
79281 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
79282 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
79283 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
79284 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
79285 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79286 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1170:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (EORTB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
79287 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORTB_ZZZ_S),
79288 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
79289 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79290 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79291 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79292 GIR_RootConstrainSelectedInstOperands,
79293 // GIR_Coverage, 11488,
79294 GIR_EraseRootFromParent_Done,
79295 // Label 4494: @211303
79296 GIM_Try, /*On fail goto*//*Label 4495*/ GIMT_Encode4(211345), // Rule ID 11489 //
79297 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79298 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eortb),
79299 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
79300 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
79301 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
79302 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
79303 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79304 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1170:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (EORTB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
79305 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORTB_ZZZ_D),
79306 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
79307 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79308 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79309 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79310 GIR_RootConstrainSelectedInstOperands,
79311 // GIR_Coverage, 11489,
79312 GIR_EraseRootFromParent_Done,
79313 // Label 4495: @211345
79314 GIM_Try, /*On fail goto*//*Label 4496*/ GIMT_Encode4(211387), // Rule ID 11505 //
79315 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79316 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnmp),
79317 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
79318 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
79319 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
79320 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
79321 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79322 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1249:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FMAXNMP_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
79323 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMP_ZPmZZ_H),
79324 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79325 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79326 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79327 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79328 GIR_RootConstrainSelectedInstOperands,
79329 // GIR_Coverage, 11505,
79330 GIR_EraseRootFromParent_Done,
79331 // Label 4496: @211387
79332 GIM_Try, /*On fail goto*//*Label 4497*/ GIMT_Encode4(211429), // Rule ID 11506 //
79333 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79334 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnmp),
79335 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
79336 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
79337 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
79338 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
79339 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79340 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1249:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FMAXNMP_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
79341 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMP_ZPmZZ_S),
79342 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79343 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79344 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79345 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79346 GIR_RootConstrainSelectedInstOperands,
79347 // GIR_Coverage, 11506,
79348 GIR_EraseRootFromParent_Done,
79349 // Label 4497: @211429
79350 GIM_Try, /*On fail goto*//*Label 4498*/ GIMT_Encode4(211471), // Rule ID 11507 //
79351 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79352 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnmp),
79353 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
79354 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
79355 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
79356 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
79357 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79358 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1249:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FMAXNMP_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
79359 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMP_ZPmZZ_D),
79360 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79361 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79362 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79363 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79364 GIR_RootConstrainSelectedInstOperands,
79365 // GIR_Coverage, 11507,
79366 GIR_EraseRootFromParent_Done,
79367 // Label 4498: @211471
79368 GIM_Try, /*On fail goto*//*Label 4499*/ GIMT_Encode4(211513), // Rule ID 11508 //
79369 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79370 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnmp),
79371 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
79372 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
79373 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
79374 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
79375 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79376 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1267:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FMINNMP_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
79377 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMP_ZPmZZ_H),
79378 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79379 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79380 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79381 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79382 GIR_RootConstrainSelectedInstOperands,
79383 // GIR_Coverage, 11508,
79384 GIR_EraseRootFromParent_Done,
79385 // Label 4499: @211513
79386 GIM_Try, /*On fail goto*//*Label 4500*/ GIMT_Encode4(211555), // Rule ID 11509 //
79387 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79388 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnmp),
79389 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
79390 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
79391 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
79392 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
79393 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79394 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1267:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FMINNMP_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
79395 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMP_ZPmZZ_S),
79396 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79397 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79398 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79399 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79400 GIR_RootConstrainSelectedInstOperands,
79401 // GIR_Coverage, 11509,
79402 GIR_EraseRootFromParent_Done,
79403 // Label 4500: @211555
79404 GIM_Try, /*On fail goto*//*Label 4501*/ GIMT_Encode4(211597), // Rule ID 11510 //
79405 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79406 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnmp),
79407 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
79408 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
79409 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
79410 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
79411 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79412 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1267:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FMINNMP_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
79413 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMP_ZPmZZ_D),
79414 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79415 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79416 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79417 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79418 GIR_RootConstrainSelectedInstOperands,
79419 // GIR_Coverage, 11510,
79420 GIR_EraseRootFromParent_Done,
79421 // Label 4501: @211597
79422 GIM_Try, /*On fail goto*//*Label 4502*/ GIMT_Encode4(211639), // Rule ID 11511 //
79423 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79424 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxp),
79425 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
79426 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
79427 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
79428 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
79429 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79430 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1252:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FMAXP_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
79431 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXP_ZPmZZ_H),
79432 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79433 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79434 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79435 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79436 GIR_RootConstrainSelectedInstOperands,
79437 // GIR_Coverage, 11511,
79438 GIR_EraseRootFromParent_Done,
79439 // Label 4502: @211639
79440 GIM_Try, /*On fail goto*//*Label 4503*/ GIMT_Encode4(211681), // Rule ID 11512 //
79441 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79442 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxp),
79443 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
79444 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
79445 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
79446 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
79447 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79448 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1252:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FMAXP_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
79449 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXP_ZPmZZ_S),
79450 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79451 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79452 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79453 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79454 GIR_RootConstrainSelectedInstOperands,
79455 // GIR_Coverage, 11512,
79456 GIR_EraseRootFromParent_Done,
79457 // Label 4503: @211681
79458 GIM_Try, /*On fail goto*//*Label 4504*/ GIMT_Encode4(211723), // Rule ID 11513 //
79459 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79460 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxp),
79461 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
79462 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
79463 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
79464 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
79465 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79466 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1252:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FMAXP_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
79467 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXP_ZPmZZ_D),
79468 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79469 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79470 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79471 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79472 GIR_RootConstrainSelectedInstOperands,
79473 // GIR_Coverage, 11513,
79474 GIR_EraseRootFromParent_Done,
79475 // Label 4504: @211723
79476 GIM_Try, /*On fail goto*//*Label 4505*/ GIMT_Encode4(211765), // Rule ID 11514 //
79477 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79478 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminp),
79479 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
79480 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
79481 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
79482 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
79483 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79484 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1270:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FMINP_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
79485 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINP_ZPmZZ_H),
79486 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79487 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79488 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79489 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79490 GIR_RootConstrainSelectedInstOperands,
79491 // GIR_Coverage, 11514,
79492 GIR_EraseRootFromParent_Done,
79493 // Label 4505: @211765
79494 GIM_Try, /*On fail goto*//*Label 4506*/ GIMT_Encode4(211807), // Rule ID 11515 //
79495 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79496 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminp),
79497 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
79498 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
79499 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
79500 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
79501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79502 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1270:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (FMINP_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
79503 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINP_ZPmZZ_S),
79504 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79505 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79506 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79507 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79508 GIR_RootConstrainSelectedInstOperands,
79509 // GIR_Coverage, 11515,
79510 GIR_EraseRootFromParent_Done,
79511 // Label 4506: @211807
79512 GIM_Try, /*On fail goto*//*Label 4507*/ GIMT_Encode4(211849), // Rule ID 11516 //
79513 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79514 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminp),
79515 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
79516 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
79517 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
79518 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
79519 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79520 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1270:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (FMINP_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
79521 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINP_ZPmZZ_D),
79522 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79523 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79524 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79525 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79526 GIR_RootConstrainSelectedInstOperands,
79527 // GIR_Coverage, 11516,
79528 GIR_EraseRootFromParent_Done,
79529 // Label 4507: @211849
79530 GIM_Try, /*On fail goto*//*Label 4508*/ GIMT_Encode4(211891), // Rule ID 11521 //
79531 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79532 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlalb),
79533 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
79534 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
79535 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
79536 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
79537 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79538 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1276:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FMLALB_ZZZ_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
79539 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALB_ZZZ_SHH),
79540 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
79541 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79542 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79543 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79544 GIR_RootConstrainSelectedInstOperands,
79545 // GIR_Coverage, 11521,
79546 GIR_EraseRootFromParent_Done,
79547 // Label 4508: @211891
79548 GIM_Try, /*On fail goto*//*Label 4509*/ GIMT_Encode4(211933), // Rule ID 11522 //
79549 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79550 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlalt),
79551 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
79552 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
79553 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
79554 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
79555 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79556 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1278:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FMLALT_ZZZ_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
79557 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALT_ZZZ_SHH),
79558 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
79559 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79560 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79561 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79562 GIR_RootConstrainSelectedInstOperands,
79563 // GIR_Coverage, 11522,
79564 GIR_EraseRootFromParent_Done,
79565 // Label 4509: @211933
79566 GIM_Try, /*On fail goto*//*Label 4510*/ GIMT_Encode4(211975), // Rule ID 11523 //
79567 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79568 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlslb),
79569 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
79570 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
79571 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
79572 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
79573 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79574 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1283:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FMLSLB_ZZZ_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
79575 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLB_ZZZ_SHH),
79576 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
79577 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79578 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79579 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79580 GIR_RootConstrainSelectedInstOperands,
79581 // GIR_Coverage, 11523,
79582 GIR_EraseRootFromParent_Done,
79583 // Label 4510: @211975
79584 GIM_Try, /*On fail goto*//*Label 4511*/ GIMT_Encode4(212017), // Rule ID 11524 //
79585 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79586 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlslt),
79587 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
79588 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
79589 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
79590 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
79591 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79592 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1285:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FMLSLT_ZZZ_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
79593 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLT_ZZZ_SHH),
79594 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
79595 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79596 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79597 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79598 GIR_RootConstrainSelectedInstOperands,
79599 // GIR_Coverage, 11524,
79600 GIR_EraseRootFromParent_Done,
79601 // Label 4511: @212017
79602 GIM_Try, /*On fail goto*//*Label 4512*/ GIMT_Encode4(212059), // Rule ID 11525 //
79603 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79604 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bcax),
79605 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
79606 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
79607 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
79608 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
79609 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79610 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1087:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (BCAX_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
79611 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
79612 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79613 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79614 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79615 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79616 GIR_RootConstrainSelectedInstOperands,
79617 // GIR_Coverage, 11525,
79618 GIR_EraseRootFromParent_Done,
79619 // Label 4512: @212059
79620 GIM_Try, /*On fail goto*//*Label 4513*/ GIMT_Encode4(212101), // Rule ID 11527 //
79621 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79622 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bcax),
79623 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
79624 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
79625 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
79626 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
79627 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79628 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1087:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (BCAX_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
79629 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
79630 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79631 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79632 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79633 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79634 GIR_RootConstrainSelectedInstOperands,
79635 // GIR_Coverage, 11527,
79636 GIR_EraseRootFromParent_Done,
79637 // Label 4513: @212101
79638 GIM_Try, /*On fail goto*//*Label 4514*/ GIMT_Encode4(212143), // Rule ID 11529 //
79639 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79640 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bcax),
79641 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
79642 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
79643 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
79644 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
79645 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79646 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1087:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (BCAX_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
79647 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
79648 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79649 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79650 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79651 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79652 GIR_RootConstrainSelectedInstOperands,
79653 // GIR_Coverage, 11529,
79654 GIR_EraseRootFromParent_Done,
79655 // Label 4514: @212143
79656 GIM_Try, /*On fail goto*//*Label 4515*/ GIMT_Encode4(212185), // Rule ID 11531 //
79657 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79658 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bcax),
79659 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
79660 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
79661 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
79662 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
79663 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79664 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1087:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (BCAX_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
79665 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
79666 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79667 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79668 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79669 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79670 GIR_RootConstrainSelectedInstOperands,
79671 // GIR_Coverage, 11531,
79672 GIR_EraseRootFromParent_Done,
79673 // Label 4515: @212185
79674 GIM_Try, /*On fail goto*//*Label 4516*/ GIMT_Encode4(212227), // Rule ID 11533 //
79675 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79676 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bsl),
79677 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
79678 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
79679 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
79680 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
79681 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79682 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1116:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
79683 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
79684 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79685 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79686 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79687 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79688 GIR_RootConstrainSelectedInstOperands,
79689 // GIR_Coverage, 11533,
79690 GIR_EraseRootFromParent_Done,
79691 // Label 4516: @212227
79692 GIM_Try, /*On fail goto*//*Label 4517*/ GIMT_Encode4(212269), // Rule ID 11535 //
79693 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79694 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bsl),
79695 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
79696 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
79697 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
79698 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
79699 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79700 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1116:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
79701 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
79702 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79703 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79704 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79705 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79706 GIR_RootConstrainSelectedInstOperands,
79707 // GIR_Coverage, 11535,
79708 GIR_EraseRootFromParent_Done,
79709 // Label 4517: @212269
79710 GIM_Try, /*On fail goto*//*Label 4518*/ GIMT_Encode4(212311), // Rule ID 11537 //
79711 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79712 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bsl),
79713 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
79714 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
79715 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
79716 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
79717 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79718 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1116:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
79719 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
79720 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79721 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79722 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79723 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79724 GIR_RootConstrainSelectedInstOperands,
79725 // GIR_Coverage, 11537,
79726 GIR_EraseRootFromParent_Done,
79727 // Label 4518: @212311
79728 GIM_Try, /*On fail goto*//*Label 4519*/ GIMT_Encode4(212353), // Rule ID 11539 //
79729 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79730 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bsl),
79731 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
79732 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
79733 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
79734 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
79735 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79736 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1116:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
79737 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
79738 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79739 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79740 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79741 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79742 GIR_RootConstrainSelectedInstOperands,
79743 // GIR_Coverage, 11539,
79744 GIR_EraseRootFromParent_Done,
79745 // Label 4519: @212353
79746 GIM_Try, /*On fail goto*//*Label 4520*/ GIMT_Encode4(212395), // Rule ID 11541 //
79747 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79748 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bsl1n),
79749 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
79750 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
79751 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
79752 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
79753 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79754 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1117:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (BSL1N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
79755 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
79756 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79757 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79758 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79759 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79760 GIR_RootConstrainSelectedInstOperands,
79761 // GIR_Coverage, 11541,
79762 GIR_EraseRootFromParent_Done,
79763 // Label 4520: @212395
79764 GIM_Try, /*On fail goto*//*Label 4521*/ GIMT_Encode4(212437), // Rule ID 11542 //
79765 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79766 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bsl1n),
79767 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
79768 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
79769 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
79770 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
79771 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79772 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1117:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (BSL1N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
79773 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
79774 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79775 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79776 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79777 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79778 GIR_RootConstrainSelectedInstOperands,
79779 // GIR_Coverage, 11542,
79780 GIR_EraseRootFromParent_Done,
79781 // Label 4521: @212437
79782 GIM_Try, /*On fail goto*//*Label 4522*/ GIMT_Encode4(212479), // Rule ID 11543 //
79783 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79784 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bsl1n),
79785 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
79786 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
79787 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
79788 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
79789 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79790 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1117:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (BSL1N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
79791 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
79792 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79793 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79794 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79795 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79796 GIR_RootConstrainSelectedInstOperands,
79797 // GIR_Coverage, 11543,
79798 GIR_EraseRootFromParent_Done,
79799 // Label 4522: @212479
79800 GIM_Try, /*On fail goto*//*Label 4523*/ GIMT_Encode4(212521), // Rule ID 11544 //
79801 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79802 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bsl1n),
79803 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
79804 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
79805 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
79806 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
79807 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79808 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1117:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (BSL1N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
79809 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
79810 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79811 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79812 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79813 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79814 GIR_RootConstrainSelectedInstOperands,
79815 // GIR_Coverage, 11544,
79816 GIR_EraseRootFromParent_Done,
79817 // Label 4523: @212521
79818 GIM_Try, /*On fail goto*//*Label 4524*/ GIMT_Encode4(212563), // Rule ID 11545 //
79819 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79820 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bsl2n),
79821 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
79822 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
79823 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
79824 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
79825 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79826 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1118:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
79827 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
79828 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79829 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79830 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79831 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79832 GIR_RootConstrainSelectedInstOperands,
79833 // GIR_Coverage, 11545,
79834 GIR_EraseRootFromParent_Done,
79835 // Label 4524: @212563
79836 GIM_Try, /*On fail goto*//*Label 4525*/ GIMT_Encode4(212605), // Rule ID 11546 //
79837 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79838 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bsl2n),
79839 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
79840 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
79841 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
79842 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
79843 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79844 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1118:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
79845 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
79846 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79847 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79848 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79849 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79850 GIR_RootConstrainSelectedInstOperands,
79851 // GIR_Coverage, 11546,
79852 GIR_EraseRootFromParent_Done,
79853 // Label 4525: @212605
79854 GIM_Try, /*On fail goto*//*Label 4526*/ GIMT_Encode4(212647), // Rule ID 11547 //
79855 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79856 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bsl2n),
79857 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
79858 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
79859 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
79860 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
79861 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79862 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1118:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
79863 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
79864 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79865 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79866 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79867 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79868 GIR_RootConstrainSelectedInstOperands,
79869 // GIR_Coverage, 11547,
79870 GIR_EraseRootFromParent_Done,
79871 // Label 4526: @212647
79872 GIM_Try, /*On fail goto*//*Label 4527*/ GIMT_Encode4(212689), // Rule ID 11548 //
79873 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79874 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bsl2n),
79875 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
79876 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
79877 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
79878 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
79879 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79880 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1118:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
79881 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
79882 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79883 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79884 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79885 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79886 GIR_RootConstrainSelectedInstOperands,
79887 // GIR_Coverage, 11548,
79888 GIR_EraseRootFromParent_Done,
79889 // Label 4527: @212689
79890 GIM_Try, /*On fail goto*//*Label 4528*/ GIMT_Encode4(212731), // Rule ID 11549 //
79891 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79892 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nbsl),
79893 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
79894 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
79895 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
79896 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
79897 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79898 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1393:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
79899 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
79900 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79901 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79902 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79903 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79904 GIR_RootConstrainSelectedInstOperands,
79905 // GIR_Coverage, 11549,
79906 GIR_EraseRootFromParent_Done,
79907 // Label 4528: @212731
79908 GIM_Try, /*On fail goto*//*Label 4529*/ GIMT_Encode4(212773), // Rule ID 11551 //
79909 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79910 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nbsl),
79911 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
79912 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
79913 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
79914 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
79915 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79916 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1393:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
79917 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
79918 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79919 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79920 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79921 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79922 GIR_RootConstrainSelectedInstOperands,
79923 // GIR_Coverage, 11551,
79924 GIR_EraseRootFromParent_Done,
79925 // Label 4529: @212773
79926 GIM_Try, /*On fail goto*//*Label 4530*/ GIMT_Encode4(212815), // Rule ID 11553 //
79927 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79928 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nbsl),
79929 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
79930 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
79931 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
79932 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
79933 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79934 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1393:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
79935 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
79936 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79937 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79938 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79939 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79940 GIR_RootConstrainSelectedInstOperands,
79941 // GIR_Coverage, 11553,
79942 GIR_EraseRootFromParent_Done,
79943 // Label 4530: @212815
79944 GIM_Try, /*On fail goto*//*Label 4531*/ GIMT_Encode4(212857), // Rule ID 11555 //
79945 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
79946 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nbsl),
79947 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
79948 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
79949 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
79950 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
79951 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79952 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1393:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
79953 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
79954 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
79955 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79956 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79957 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79958 GIR_RootConstrainSelectedInstOperands,
79959 // GIR_Coverage, 11555,
79960 GIR_EraseRootFromParent_Done,
79961 // Label 4531: @212857
79962 GIM_Try, /*On fail goto*//*Label 4532*/ GIMT_Encode4(212899), // Rule ID 11637 //
79963 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME),
79964 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uclamp),
79965 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
79966 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
79967 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
79968 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
79969 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79970 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1724:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UCLAMP_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
79971 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCLAMP_ZZZ_B),
79972 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
79973 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79974 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79975 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79976 GIR_RootConstrainSelectedInstOperands,
79977 // GIR_Coverage, 11637,
79978 GIR_EraseRootFromParent_Done,
79979 // Label 4532: @212899
79980 GIM_Try, /*On fail goto*//*Label 4533*/ GIMT_Encode4(212941), // Rule ID 11639 //
79981 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME),
79982 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uclamp),
79983 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
79984 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
79985 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
79986 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
79987 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
79988 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1724:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UCLAMP_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
79989 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCLAMP_ZZZ_H),
79990 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
79991 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
79992 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
79993 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
79994 GIR_RootConstrainSelectedInstOperands,
79995 // GIR_Coverage, 11639,
79996 GIR_EraseRootFromParent_Done,
79997 // Label 4533: @212941
79998 GIM_Try, /*On fail goto*//*Label 4534*/ GIMT_Encode4(212983), // Rule ID 11641 //
79999 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME),
80000 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uclamp),
80001 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
80002 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
80003 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
80004 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
80005 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80006 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1724:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (UCLAMP_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
80007 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCLAMP_ZZZ_S),
80008 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
80009 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80010 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80011 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80012 GIR_RootConstrainSelectedInstOperands,
80013 // GIR_Coverage, 11641,
80014 GIR_EraseRootFromParent_Done,
80015 // Label 4534: @212983
80016 GIM_Try, /*On fail goto*//*Label 4535*/ GIMT_Encode4(213025), // Rule ID 11643 //
80017 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME),
80018 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uclamp),
80019 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
80020 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
80021 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
80022 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
80023 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80024 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1724:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (UCLAMP_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
80025 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCLAMP_ZZZ_D),
80026 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
80027 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80028 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80029 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80030 GIR_RootConstrainSelectedInstOperands,
80031 // GIR_Coverage, 11643,
80032 GIR_EraseRootFromParent_Done,
80033 // Label 4535: @213025
80034 GIM_Try, /*On fail goto*//*Label 4536*/ GIMT_Encode4(213067), // Rule ID 11645 //
80035 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2),
80036 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdot_x2),
80037 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
80038 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
80039 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80040 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80041 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80042 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1233:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (FDOT_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
80043 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOT_ZZZ_S),
80044 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
80045 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80046 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80047 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80048 GIR_RootConstrainSelectedInstOperands,
80049 // GIR_Coverage, 11645,
80050 GIR_EraseRootFromParent_Done,
80051 // Label 4536: @213067
80052 GIM_Try, /*On fail goto*//*Label 4537*/ GIMT_Encode4(213109), // Rule ID 11647 //
80053 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2),
80054 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bfmlslb),
80055 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
80056 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
80057 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80058 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80059 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80060 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1100:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3) => (BFMLSLB_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3)
80061 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMLSLB_ZZZ_S),
80062 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
80063 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80064 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80065 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80066 GIR_RootConstrainSelectedInstOperands,
80067 // GIR_Coverage, 11647,
80068 GIR_EraseRootFromParent_Done,
80069 // Label 4537: @213109
80070 GIM_Try, /*On fail goto*//*Label 4538*/ GIMT_Encode4(213151), // Rule ID 11648 //
80071 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2),
80072 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bfmlslt),
80073 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
80074 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
80075 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80076 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80077 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80078 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1102:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3) => (BFMLSLT_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3)
80079 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMLSLT_ZZZ_S),
80080 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
80081 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80082 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80083 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80084 GIR_RootConstrainSelectedInstOperands,
80085 // GIR_Coverage, 11648,
80086 GIR_EraseRootFromParent_Done,
80087 // Label 4538: @213151
80088 GIM_Try, /*On fail goto*//*Label 4539*/ GIMT_Encode4(213193), // Rule ID 11651 //
80089 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2),
80090 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udot_x2),
80091 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
80092 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
80093 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80094 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80095 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80096 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1740:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UDOT_ZZZ_HtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
80097 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDOT_ZZZ_HtoS),
80098 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
80099 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80100 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80101 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80102 GIR_RootConstrainSelectedInstOperands,
80103 // GIR_Coverage, 11651,
80104 GIR_EraseRootFromParent_Done,
80105 // Label 4539: @213193
80106 GIM_Try, /*On fail goto*//*Label 4540*/ GIMT_Encode4(213235), // Rule ID 11770 //
80107 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasB16B16_HasSVE2orSME2),
80108 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
80109 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
80110 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
80111 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80112 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80113 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80114 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1323:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3) => (BFSUB_ZPmZZ:{ *:[nxv8bf16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3)
80115 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFSUB_ZPmZZ),
80116 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
80117 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80118 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80119 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80120 GIR_RootConstrainSelectedInstOperands,
80121 // GIR_Coverage, 11770,
80122 GIR_EraseRootFromParent_Done,
80123 // Label 4540: @213235
80124 GIM_Try, /*On fail goto*//*Label 4541*/ GIMT_Encode4(213277), // Rule ID 11782 //
80125 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasB16B16_HasSVE2orSME2),
80126 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmax),
80127 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
80128 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
80129 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80130 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80131 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80132 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1237:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3) => (BFMAX_ZPmZZ:{ *:[nxv8bf16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3)
80133 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMAX_ZPmZZ),
80134 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
80135 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80136 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80137 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80138 GIR_RootConstrainSelectedInstOperands,
80139 // GIR_Coverage, 11782,
80140 GIR_EraseRootFromParent_Done,
80141 // Label 4541: @213277
80142 GIM_Try, /*On fail goto*//*Label 4542*/ GIMT_Encode4(213319), // Rule ID 11783 //
80143 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasB16B16_HasSVE2orSME2),
80144 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmin),
80145 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
80146 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
80147 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80148 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80149 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80150 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1255:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3) => (BFMIN_ZPmZZ:{ *:[nxv8bf16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3)
80151 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMIN_ZPmZZ),
80152 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
80153 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80154 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80155 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80156 GIR_RootConstrainSelectedInstOperands,
80157 // GIR_Coverage, 11783,
80158 GIR_EraseRootFromParent_Done,
80159 // Label 4542: @213319
80160 GIM_Try, /*On fail goto*//*Label 4543*/ GIMT_Encode4(213361), // Rule ID 11786 //
80161 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasB16B16_HasSVE2orSME2),
80162 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnm),
80163 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
80164 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
80165 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80166 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80167 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80168 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1243:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3) => (BFMAXNM_ZPmZZ:{ *:[nxv8bf16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3)
80169 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMAXNM_ZPmZZ),
80170 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
80171 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80172 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80173 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80174 GIR_RootConstrainSelectedInstOperands,
80175 // GIR_Coverage, 11786,
80176 GIR_EraseRootFromParent_Done,
80177 // Label 4543: @213361
80178 GIM_Try, /*On fail goto*//*Label 4544*/ GIMT_Encode4(213403), // Rule ID 11787 //
80179 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasB16B16_HasSVE2orSME2),
80180 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnm),
80181 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
80182 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
80183 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80184 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80185 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80186 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1261:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3) => (BFMINNM_ZPmZZ:{ *:[nxv8bf16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3)
80187 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMINNM_ZPmZZ),
80188 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
80189 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80190 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80191 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80192 GIR_RootConstrainSelectedInstOperands,
80193 // GIR_Coverage, 11787,
80194 GIR_EraseRootFromParent_Done,
80195 // Label 4544: @213403
80196 GIM_Try, /*On fail goto*//*Label 4545*/ GIMT_Encode4(213445), // Rule ID 11854 //
80197 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
80198 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
80199 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
80200 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
80201 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
80202 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
80203 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80204 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1700:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (TBXQ_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
80205 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_B),
80206 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
80207 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80208 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80209 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80210 GIR_RootConstrainSelectedInstOperands,
80211 // GIR_Coverage, 11854,
80212 GIR_EraseRootFromParent_Done,
80213 // Label 4545: @213445
80214 GIM_Try, /*On fail goto*//*Label 4546*/ GIMT_Encode4(213487), // Rule ID 11855 //
80215 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
80216 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
80217 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
80218 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
80219 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80220 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80221 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80222 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1700:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (TBXQ_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
80223 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_H),
80224 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
80225 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80226 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80227 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80228 GIR_RootConstrainSelectedInstOperands,
80229 // GIR_Coverage, 11855,
80230 GIR_EraseRootFromParent_Done,
80231 // Label 4546: @213487
80232 GIM_Try, /*On fail goto*//*Label 4547*/ GIMT_Encode4(213529), // Rule ID 11856 //
80233 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
80234 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
80235 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
80236 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
80237 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
80238 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
80239 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80240 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1700:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (TBXQ_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
80241 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_S),
80242 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
80243 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80244 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80245 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80246 GIR_RootConstrainSelectedInstOperands,
80247 // GIR_Coverage, 11856,
80248 GIR_EraseRootFromParent_Done,
80249 // Label 4547: @213529
80250 GIM_Try, /*On fail goto*//*Label 4548*/ GIMT_Encode4(213571), // Rule ID 11857 //
80251 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
80252 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
80253 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
80254 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
80255 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
80256 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
80257 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80258 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1700:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (TBXQ_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
80259 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_D),
80260 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
80261 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80262 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80263 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80264 GIR_RootConstrainSelectedInstOperands,
80265 // GIR_Coverage, 11857,
80266 GIR_EraseRootFromParent_Done,
80267 // Label 4548: @213571
80268 GIM_Try, /*On fail goto*//*Label 4549*/ GIMT_Encode4(213613), // Rule ID 11858 //
80269 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
80270 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
80271 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
80272 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
80273 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80274 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80275 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80276 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1700:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (TBXQ_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
80277 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_H),
80278 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
80279 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80280 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80281 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80282 GIR_RootConstrainSelectedInstOperands,
80283 // GIR_Coverage, 11858,
80284 GIR_EraseRootFromParent_Done,
80285 // Label 4549: @213613
80286 GIM_Try, /*On fail goto*//*Label 4550*/ GIMT_Encode4(213655), // Rule ID 11859 //
80287 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
80288 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
80289 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
80290 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
80291 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
80292 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
80293 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80294 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1700:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (TBXQ_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
80295 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_S),
80296 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
80297 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80298 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80299 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80300 GIR_RootConstrainSelectedInstOperands,
80301 // GIR_Coverage, 11859,
80302 GIR_EraseRootFromParent_Done,
80303 // Label 4550: @213655
80304 GIM_Try, /*On fail goto*//*Label 4551*/ GIMT_Encode4(213697), // Rule ID 11860 //
80305 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
80306 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
80307 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
80308 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
80309 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
80310 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
80311 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80312 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1700:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (TBXQ_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
80313 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_D),
80314 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
80315 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80316 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80317 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80318 GIR_RootConstrainSelectedInstOperands,
80319 // GIR_Coverage, 11860,
80320 GIR_EraseRootFromParent_Done,
80321 // Label 4551: @213697
80322 GIM_Try, /*On fail goto*//*Label 4552*/ GIMT_Encode4(213739), // Rule ID 11861 //
80323 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2p1),
80324 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
80325 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
80326 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
80327 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80328 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80329 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80330 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1700:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (TBXQ_ZZZ_H:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
80331 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_H),
80332 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
80333 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80334 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80335 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80336 GIR_RootConstrainSelectedInstOperands,
80337 // GIR_Coverage, 11861,
80338 GIR_EraseRootFromParent_Done,
80339 // Label 4552: @213739
80340 GIM_Reject,
80341 // Label 3735: @213740
80342 GIM_Try, /*On fail goto*//*Label 4553*/ GIMT_Encode4(221356),
80343 GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
80344 GIM_Try, /*On fail goto*//*Label 4554*/ GIMT_Encode4(213795), // Rule ID 2890 //
80345 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
80346 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_u),
80347 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
80348 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
80349 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
80350 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
80351 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
80352 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80353 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1384:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op4) => (MLA_ZPZZZ_B_UNDEF:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i8] }:$Op4)
80354 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPZZZ_B_UNDEF),
80355 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
80356 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80357 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80358 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80359 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
80360 GIR_RootConstrainSelectedInstOperands,
80361 // GIR_Coverage, 2890,
80362 GIR_EraseRootFromParent_Done,
80363 // Label 4554: @213795
80364 GIM_Try, /*On fail goto*//*Label 4555*/ GIMT_Encode4(213842), // Rule ID 2892 //
80365 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
80366 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_u),
80367 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
80368 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
80369 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80370 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80371 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
80372 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80373 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1384:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op4) => (MLA_ZPZZZ_H_UNDEF:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i16] }:$Op4)
80374 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPZZZ_H_UNDEF),
80375 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
80376 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80377 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80378 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80379 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
80380 GIR_RootConstrainSelectedInstOperands,
80381 // GIR_Coverage, 2892,
80382 GIR_EraseRootFromParent_Done,
80383 // Label 4555: @213842
80384 GIM_Try, /*On fail goto*//*Label 4556*/ GIMT_Encode4(213889), // Rule ID 2894 //
80385 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
80386 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_u),
80387 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
80388 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
80389 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
80390 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
80391 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
80392 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80393 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1384:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op4) => (MLA_ZPZZZ_S_UNDEF:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i32] }:$Op4)
80394 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPZZZ_S_UNDEF),
80395 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
80396 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80397 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80398 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80399 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
80400 GIR_RootConstrainSelectedInstOperands,
80401 // GIR_Coverage, 2894,
80402 GIR_EraseRootFromParent_Done,
80403 // Label 4556: @213889
80404 GIM_Try, /*On fail goto*//*Label 4557*/ GIMT_Encode4(213936), // Rule ID 2896 //
80405 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
80406 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_u),
80407 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
80408 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
80409 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
80410 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
80411 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
80412 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80413 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1384:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op4) => (MLA_ZPZZZ_D_UNDEF:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i64] }:$Op4)
80414 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPZZZ_D_UNDEF),
80415 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
80416 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80417 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80418 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80419 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
80420 GIR_RootConstrainSelectedInstOperands,
80421 // GIR_Coverage, 2896,
80422 GIR_EraseRootFromParent_Done,
80423 // Label 4557: @213936
80424 GIM_Try, /*On fail goto*//*Label 4558*/ GIMT_Encode4(213983), // Rule ID 7244 //
80425 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
80426 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_u),
80427 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
80428 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
80429 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
80430 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
80431 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
80432 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80433 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1387:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op4) => (MLS_ZPZZZ_B_UNDEF:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i8] }:$Op4)
80434 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPZZZ_B_UNDEF),
80435 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
80436 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80437 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80438 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80439 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
80440 GIR_RootConstrainSelectedInstOperands,
80441 // GIR_Coverage, 7244,
80442 GIR_EraseRootFromParent_Done,
80443 // Label 4558: @213983
80444 GIM_Try, /*On fail goto*//*Label 4559*/ GIMT_Encode4(214030), // Rule ID 7246 //
80445 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
80446 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_u),
80447 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
80448 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
80449 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80450 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80451 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
80452 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80453 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1387:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op4) => (MLS_ZPZZZ_H_UNDEF:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i16] }:$Op4)
80454 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPZZZ_H_UNDEF),
80455 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
80456 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80457 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80458 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80459 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
80460 GIR_RootConstrainSelectedInstOperands,
80461 // GIR_Coverage, 7246,
80462 GIR_EraseRootFromParent_Done,
80463 // Label 4559: @214030
80464 GIM_Try, /*On fail goto*//*Label 4560*/ GIMT_Encode4(214077), // Rule ID 7248 //
80465 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
80466 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_u),
80467 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
80468 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
80469 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
80470 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
80471 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
80472 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80473 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1387:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op4) => (MLS_ZPZZZ_S_UNDEF:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i32] }:$Op4)
80474 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPZZZ_S_UNDEF),
80475 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
80476 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80477 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80478 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80479 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
80480 GIR_RootConstrainSelectedInstOperands,
80481 // GIR_Coverage, 7248,
80482 GIR_EraseRootFromParent_Done,
80483 // Label 4560: @214077
80484 GIM_Try, /*On fail goto*//*Label 4561*/ GIMT_Encode4(214124), // Rule ID 7250 //
80485 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
80486 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_u),
80487 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
80488 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
80489 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
80490 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
80491 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
80492 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80493 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1387:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op4) => (MLS_ZPZZZ_D_UNDEF:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i64] }:$Op4)
80494 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPZZZ_D_UNDEF),
80495 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
80496 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80497 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80498 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80499 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
80500 GIR_RootConstrainSelectedInstOperands,
80501 // GIR_Coverage, 7250,
80502 GIR_EraseRootFromParent_Done,
80503 // Label 4561: @214124
80504 GIM_Try, /*On fail goto*//*Label 4562*/ GIMT_Encode4(214204), // Rule ID 5354 //
80505 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcopy_lane),
80506 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
80507 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
80508 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
80509 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
80510 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
80511 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80512 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80513 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
80514 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
80515 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
80516 // MIs[1] Operand 1
80517 // No operand predicates
80518 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80519 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
80520 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
80521 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
80522 // MIs[2] Operand 1
80523 // No operand predicates
80524 GIM_CheckIsSafeToFold, /*NumInsns*/2,
80525 // (intrinsic_wo_chain:{ *:[v16i8] } 723:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, V128:{ *:[v16i8] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx2) => (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, V128:{ *:[v16i8] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx2)
80526 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
80527 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
80528 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
80529 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
80530 GIR_RootToRootCopy, /*OpIdx*/4, // Vs
80531 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
80532 GIR_RootConstrainSelectedInstOperands,
80533 // GIR_Coverage, 5354,
80534 GIR_EraseRootFromParent_Done,
80535 // Label 4562: @214204
80536 GIM_Try, /*On fail goto*//*Label 4563*/ GIMT_Encode4(214284), // Rule ID 5355 //
80537 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcopy_lane),
80538 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
80539 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
80540 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
80541 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
80542 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
80543 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80544 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80545 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
80546 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
80547 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
80548 // MIs[1] Operand 1
80549 // No operand predicates
80550 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80551 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
80552 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
80553 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
80554 // MIs[2] Operand 1
80555 // No operand predicates
80556 GIM_CheckIsSafeToFold, /*NumInsns*/2,
80557 // (intrinsic_wo_chain:{ *:[v8i16] } 723:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, V128:{ *:[v8i16] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx2) => (INSvi16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, V128:{ *:[v8i16] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx2)
80558 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
80559 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
80560 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
80561 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
80562 GIR_RootToRootCopy, /*OpIdx*/4, // Vs
80563 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
80564 GIR_RootConstrainSelectedInstOperands,
80565 // GIR_Coverage, 5355,
80566 GIR_EraseRootFromParent_Done,
80567 // Label 4563: @214284
80568 GIM_Try, /*On fail goto*//*Label 4564*/ GIMT_Encode4(214364), // Rule ID 5356 //
80569 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcopy_lane),
80570 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
80571 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
80572 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
80573 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
80574 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
80575 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80576 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80577 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
80578 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
80579 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
80580 // MIs[1] Operand 1
80581 // No operand predicates
80582 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80583 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
80584 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
80585 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
80586 // MIs[2] Operand 1
80587 // No operand predicates
80588 GIM_CheckIsSafeToFold, /*NumInsns*/2,
80589 // (intrinsic_wo_chain:{ *:[v4i32] } 723:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, V128:{ *:[v4i32] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx2) => (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, V128:{ *:[v4i32] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx2)
80590 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
80591 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
80592 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
80593 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
80594 GIR_RootToRootCopy, /*OpIdx*/4, // Vs
80595 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
80596 GIR_RootConstrainSelectedInstOperands,
80597 // GIR_Coverage, 5356,
80598 GIR_EraseRootFromParent_Done,
80599 // Label 4564: @214364
80600 GIM_Try, /*On fail goto*//*Label 4565*/ GIMT_Encode4(214444), // Rule ID 5357 //
80601 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcopy_lane),
80602 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
80603 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
80604 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
80605 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
80606 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
80607 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80608 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80609 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
80610 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
80611 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
80612 // MIs[1] Operand 1
80613 // No operand predicates
80614 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80615 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
80616 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
80617 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
80618 // MIs[2] Operand 1
80619 // No operand predicates
80620 GIM_CheckIsSafeToFold, /*NumInsns*/2,
80621 // (intrinsic_wo_chain:{ *:[v2i64] } 723:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, V128:{ *:[v2i64] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx2) => (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, V128:{ *:[v2i64] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx2)
80622 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
80623 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
80624 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
80625 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
80626 GIR_RootToRootCopy, /*OpIdx*/4, // Vs
80627 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
80628 GIR_RootConstrainSelectedInstOperands,
80629 // GIR_Coverage, 5357,
80630 GIR_EraseRootFromParent_Done,
80631 // Label 4565: @214444
80632 GIM_Try, /*On fail goto*//*Label 4566*/ GIMT_Encode4(214508), // Rule ID 3718 //
80633 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
80634 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3tt1a),
80635 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
80636 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
80637 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
80638 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
80639 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80640 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80641 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80642 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80643 // MIs[0] imm
80644 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
80645 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS_timm),
80646 // (intrinsic_wo_chain:{ *:[v4i32] } 519:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm) => (SM3TT1A:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)
80647 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3TT1A),
80648 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
80649 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
80650 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
80651 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
80652 GIR_RootToRootCopy, /*OpIdx*/5, // imm
80653 GIR_RootConstrainSelectedInstOperands,
80654 // GIR_Coverage, 3718,
80655 GIR_EraseRootFromParent_Done,
80656 // Label 4566: @214508
80657 GIM_Try, /*On fail goto*//*Label 4567*/ GIMT_Encode4(214572), // Rule ID 3719 //
80658 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
80659 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3tt1b),
80660 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
80661 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
80662 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
80663 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
80664 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80665 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80666 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80667 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80668 // MIs[0] imm
80669 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
80670 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS_timm),
80671 // (intrinsic_wo_chain:{ *:[v4i32] } 520:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm) => (SM3TT1B:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)
80672 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3TT1B),
80673 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
80674 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
80675 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
80676 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
80677 GIR_RootToRootCopy, /*OpIdx*/5, // imm
80678 GIR_RootConstrainSelectedInstOperands,
80679 // GIR_Coverage, 3719,
80680 GIR_EraseRootFromParent_Done,
80681 // Label 4567: @214572
80682 GIM_Try, /*On fail goto*//*Label 4568*/ GIMT_Encode4(214636), // Rule ID 3720 //
80683 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
80684 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3tt2a),
80685 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
80686 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
80687 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
80688 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
80689 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80690 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80691 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80692 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80693 // MIs[0] imm
80694 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
80695 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS_timm),
80696 // (intrinsic_wo_chain:{ *:[v4i32] } 521:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm) => (SM3TT2A:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)
80697 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3TT2A),
80698 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
80699 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
80700 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
80701 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
80702 GIR_RootToRootCopy, /*OpIdx*/5, // imm
80703 GIR_RootConstrainSelectedInstOperands,
80704 // GIR_Coverage, 3720,
80705 GIR_EraseRootFromParent_Done,
80706 // Label 4568: @214636
80707 GIM_Try, /*On fail goto*//*Label 4569*/ GIMT_Encode4(214700), // Rule ID 3721 //
80708 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
80709 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3tt2b),
80710 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
80711 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
80712 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
80713 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
80714 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80715 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80716 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80717 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
80718 // MIs[0] imm
80719 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
80720 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS_timm),
80721 // (intrinsic_wo_chain:{ *:[v4i32] } 522:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm) => (SM3TT2B:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)
80722 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3TT2B),
80723 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
80724 GIR_RootToRootCopy, /*OpIdx*/2, // Vd
80725 GIR_RootToRootCopy, /*OpIdx*/3, // Vn
80726 GIR_RootToRootCopy, /*OpIdx*/4, // Vm
80727 GIR_RootToRootCopy, /*OpIdx*/5, // imm
80728 GIR_RootConstrainSelectedInstOperands,
80729 // GIR_Coverage, 3721,
80730 GIR_EraseRootFromParent_Done,
80731 // Label 4569: @214700
80732 GIM_Try, /*On fail goto*//*Label 4570*/ GIMT_Encode4(214752), // Rule ID 2771 //
80733 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasB16B16_HasSVE2orSME2),
80734 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla_lane),
80735 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
80736 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
80737 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80738 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80739 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80740 // MIs[0] idx
80741 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
80742 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
80743 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1274:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$op1, nxv8bf16:{ *:[nxv8bf16] }:$op2, nxv8bf16:{ *:[nxv8bf16] }:$op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx) => (BFMLA_ZZZI:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$op1, ?:{ *:[nxv8bf16] }:$op2, ?:{ *:[nxv8bf16] }:$op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)
80744 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMLA_ZZZI),
80745 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
80746 GIR_RootToRootCopy, /*OpIdx*/2, // op1
80747 GIR_RootToRootCopy, /*OpIdx*/3, // op2
80748 GIR_RootToRootCopy, /*OpIdx*/4, // op3
80749 GIR_RootToRootCopy, /*OpIdx*/5, // idx
80750 GIR_RootConstrainSelectedInstOperands,
80751 // GIR_Coverage, 2771,
80752 GIR_EraseRootFromParent_Done,
80753 // Label 4570: @214752
80754 GIM_Try, /*On fail goto*//*Label 4571*/ GIMT_Encode4(214804), // Rule ID 2772 //
80755 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
80756 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla_lane),
80757 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
80758 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
80759 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80760 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80761 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80762 // MIs[0] idx
80763 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
80764 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
80765 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1274:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx) => (FMLA_ZZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)
80766 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZZZI_H),
80767 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
80768 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80769 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80770 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80771 GIR_RootToRootCopy, /*OpIdx*/5, // idx
80772 GIR_RootConstrainSelectedInstOperands,
80773 // GIR_Coverage, 2772,
80774 GIR_EraseRootFromParent_Done,
80775 // Label 4571: @214804
80776 GIM_Try, /*On fail goto*//*Label 4572*/ GIMT_Encode4(214856), // Rule ID 2773 //
80777 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
80778 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla_lane),
80779 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
80780 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
80781 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
80782 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
80783 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80784 // MIs[0] idx
80785 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
80786 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
80787 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1274:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx) => (FMLA_ZZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
80788 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZZZI_S),
80789 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
80790 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80791 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80792 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80793 GIR_RootToRootCopy, /*OpIdx*/5, // idx
80794 GIR_RootConstrainSelectedInstOperands,
80795 // GIR_Coverage, 2773,
80796 GIR_EraseRootFromParent_Done,
80797 // Label 4572: @214856
80798 GIM_Try, /*On fail goto*//*Label 4573*/ GIMT_Encode4(214908), // Rule ID 2774 //
80799 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
80800 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla_lane),
80801 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
80802 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
80803 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
80804 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
80805 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80806 // MIs[0] idx
80807 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
80808 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
80809 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1274:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx) => (FMLA_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)
80810 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZZZI_D),
80811 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
80812 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80813 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80814 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80815 GIR_RootToRootCopy, /*OpIdx*/5, // idx
80816 GIR_RootConstrainSelectedInstOperands,
80817 // GIR_Coverage, 2774,
80818 GIR_EraseRootFromParent_Done,
80819 // Label 4573: @214908
80820 GIM_Try, /*On fail goto*//*Label 4574*/ GIMT_Encode4(214960), // Rule ID 2795 //
80821 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasSVEorSME),
80822 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bfmlalb_lane_v2),
80823 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
80824 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
80825 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80826 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80827 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80828 // MIs[0] Op4
80829 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
80830 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
80831 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1097:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (BFMLALB_ZZZI:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
80832 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMLALB_ZZZI),
80833 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
80834 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80835 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80836 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80837 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
80838 GIR_RootConstrainSelectedInstOperands,
80839 // GIR_Coverage, 2795,
80840 GIR_EraseRootFromParent_Done,
80841 // Label 4574: @214960
80842 GIM_Try, /*On fail goto*//*Label 4575*/ GIMT_Encode4(215012), // Rule ID 2905 //
80843 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
80844 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_lane),
80845 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
80846 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
80847 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80848 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80849 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80850 // MIs[0] Op4
80851 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
80852 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
80853 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1383:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (MLA_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
80854 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZZZI_H),
80855 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
80856 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80857 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80858 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80859 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
80860 GIR_RootConstrainSelectedInstOperands,
80861 // GIR_Coverage, 2905,
80862 GIR_EraseRootFromParent_Done,
80863 // Label 4575: @215012
80864 GIM_Try, /*On fail goto*//*Label 4576*/ GIMT_Encode4(215064), // Rule ID 2906 //
80865 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
80866 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_lane),
80867 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
80868 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
80869 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
80870 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
80871 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80872 // MIs[0] Op4
80873 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
80874 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
80875 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1383:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (MLA_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
80876 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZZZI_S),
80877 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
80878 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80879 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80880 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80881 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
80882 GIR_RootConstrainSelectedInstOperands,
80883 // GIR_Coverage, 2906,
80884 GIR_EraseRootFromParent_Done,
80885 // Label 4576: @215064
80886 GIM_Try, /*On fail goto*//*Label 4577*/ GIMT_Encode4(215116), // Rule ID 2907 //
80887 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
80888 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_lane),
80889 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
80890 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
80891 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
80892 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
80893 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80894 // MIs[0] Op4
80895 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
80896 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
80897 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1383:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4) => (MLA_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)
80898 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZZZI_D),
80899 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
80900 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80901 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80902 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80903 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
80904 GIR_RootConstrainSelectedInstOperands,
80905 // GIR_Coverage, 2907,
80906 GIR_EraseRootFromParent_Done,
80907 // Label 4577: @215116
80908 GIM_Try, /*On fail goto*//*Label 4578*/ GIMT_Encode4(215168), // Rule ID 2908 //
80909 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
80910 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalb_lane),
80911 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
80912 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
80913 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80914 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80915 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80916 // MIs[0] Op4
80917 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
80918 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
80919 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1525:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (SMLALB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
80920 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALB_ZZZI_S),
80921 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
80922 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80923 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80924 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80925 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
80926 GIR_RootConstrainSelectedInstOperands,
80927 // GIR_Coverage, 2908,
80928 GIR_EraseRootFromParent_Done,
80929 // Label 4578: @215168
80930 GIM_Try, /*On fail goto*//*Label 4579*/ GIMT_Encode4(215220), // Rule ID 2909 //
80931 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
80932 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalb_lane),
80933 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
80934 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
80935 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
80936 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
80937 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80938 // MIs[0] Op4
80939 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
80940 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
80941 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1525:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (SMLALB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
80942 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALB_ZZZI_D),
80943 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
80944 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80945 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80946 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80947 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
80948 GIR_RootConstrainSelectedInstOperands,
80949 // GIR_Coverage, 2909,
80950 GIR_EraseRootFromParent_Done,
80951 // Label 4579: @215220
80952 GIM_Try, /*On fail goto*//*Label 4580*/ GIMT_Encode4(215272), // Rule ID 2912 //
80953 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
80954 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdot_lane),
80955 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
80956 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
80957 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
80958 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
80959 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80960 // MIs[0] Op4
80961 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
80962 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
80963 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1491:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (SDOT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
80964 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDOT_ZZZI_S),
80965 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
80966 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80967 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80968 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80969 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
80970 GIR_RootConstrainSelectedInstOperands,
80971 // GIR_Coverage, 2912,
80972 GIR_EraseRootFromParent_Done,
80973 // Label 4580: @215272
80974 GIM_Try, /*On fail goto*//*Label 4581*/ GIMT_Encode4(215324), // Rule ID 2913 //
80975 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
80976 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdot_lane),
80977 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
80978 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
80979 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
80980 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
80981 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
80982 // MIs[0] Op4
80983 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
80984 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
80985 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1491:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4) => (SDOT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)
80986 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDOT_ZZZI_D),
80987 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
80988 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
80989 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
80990 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
80991 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
80992 GIR_RootConstrainSelectedInstOperands,
80993 // GIR_Coverage, 2913,
80994 GIR_EraseRootFromParent_Done,
80995 // Label 4581: @215324
80996 GIM_Try, /*On fail goto*//*Label 4582*/ GIMT_Encode4(215376), // Rule ID 3371 //
80997 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasSVEorSME),
80998 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bfdot_lane_v2),
80999 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81000 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81001 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81002 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81003 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81004 // MIs[0] Op4
81005 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81006 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81007 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1095:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (BFDOT_ZZI:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81008 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFDOT_ZZI),
81009 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81010 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81011 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81012 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81013 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81014 GIR_RootConstrainSelectedInstOperands,
81015 // GIR_Coverage, 3371,
81016 GIR_EraseRootFromParent_Done,
81017 // Label 4582: @215376
81018 GIM_Try, /*On fail goto*//*Label 4583*/ GIMT_Encode4(215428), // Rule ID 3376 //
81019 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8_HasSVEorSME),
81020 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usdot_lane),
81021 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81022 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81023 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
81024 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
81025 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81026 // MIs[0] Op4
81027 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81028 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81029 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1838:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (USDOT_ZZZI:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81030 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USDOT_ZZZI),
81031 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81032 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81033 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81034 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81035 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81036 GIR_RootConstrainSelectedInstOperands,
81037 // GIR_Coverage, 3376,
81038 GIR_EraseRootFromParent_Done,
81039 // Label 4583: @215428
81040 GIM_Try, /*On fail goto*//*Label 4584*/ GIMT_Encode4(215480), // Rule ID 3425 //
81041 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2),
81042 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdot_lane_x2),
81043 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81044 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81045 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81046 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81047 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81048 // MIs[0] Op4
81049 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81050 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81051 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1492:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (SDOT_ZZZI_HtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81052 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDOT_ZZZI_HtoS),
81053 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81054 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81055 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81056 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81057 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81058 GIR_RootConstrainSelectedInstOperands,
81059 // GIR_Coverage, 3425,
81060 GIR_EraseRootFromParent_Done,
81061 // Label 4584: @215480
81062 GIM_Try, /*On fail goto*//*Label 4585*/ GIMT_Encode4(215532), // Rule ID 7314 //
81063 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
81064 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udot_lane),
81065 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81066 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81067 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
81068 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
81069 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81070 // MIs[0] Op4
81071 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81072 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81073 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1738:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (UDOT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81074 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDOT_ZZZI_S),
81075 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81076 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81077 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81078 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81079 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81080 GIR_RootConstrainSelectedInstOperands,
81081 // GIR_Coverage, 7314,
81082 GIR_EraseRootFromParent_Done,
81083 // Label 4585: @215532
81084 GIM_Try, /*On fail goto*//*Label 4586*/ GIMT_Encode4(215584), // Rule ID 7315 //
81085 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
81086 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udot_lane),
81087 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
81088 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
81089 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81090 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81091 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81092 // MIs[0] Op4
81093 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81094 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
81095 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1738:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4) => (UDOT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)
81096 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDOT_ZZZI_D),
81097 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81098 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81099 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81100 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81101 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81102 GIR_RootConstrainSelectedInstOperands,
81103 // GIR_Coverage, 7315,
81104 GIR_EraseRootFromParent_Done,
81105 // Label 4586: @215584
81106 GIM_Try, /*On fail goto*//*Label 4587*/ GIMT_Encode4(215636), // Rule ID 7958 //
81107 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
81108 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_lane),
81109 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
81110 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
81111 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81112 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81113 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81114 // MIs[0] idx
81115 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81116 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81117 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1281:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx) => (FMLS_ZZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)
81118 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZZZI_H),
81119 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81120 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81121 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81122 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81123 GIR_RootToRootCopy, /*OpIdx*/5, // idx
81124 GIR_RootConstrainSelectedInstOperands,
81125 // GIR_Coverage, 7958,
81126 GIR_EraseRootFromParent_Done,
81127 // Label 4587: @215636
81128 GIM_Try, /*On fail goto*//*Label 4588*/ GIMT_Encode4(215688), // Rule ID 7959 //
81129 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
81130 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_lane),
81131 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81132 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81133 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
81134 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
81135 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81136 // MIs[0] idx
81137 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81138 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81139 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1281:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx) => (FMLS_ZZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
81140 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZZZI_S),
81141 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81142 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81143 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81144 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81145 GIR_RootToRootCopy, /*OpIdx*/5, // idx
81146 GIR_RootConstrainSelectedInstOperands,
81147 // GIR_Coverage, 7959,
81148 GIR_EraseRootFromParent_Done,
81149 // Label 4588: @215688
81150 GIM_Try, /*On fail goto*//*Label 4589*/ GIMT_Encode4(215740), // Rule ID 7960 //
81151 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
81152 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_lane),
81153 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
81154 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
81155 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
81156 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
81157 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81158 // MIs[0] idx
81159 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81160 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
81161 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1281:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx) => (FMLS_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)
81162 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZZZI_D),
81163 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81164 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81165 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81166 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81167 GIR_RootToRootCopy, /*OpIdx*/5, // idx
81168 GIR_RootConstrainSelectedInstOperands,
81169 // GIR_Coverage, 7960,
81170 GIR_EraseRootFromParent_Done,
81171 // Label 4589: @215740
81172 GIM_Try, /*On fail goto*//*Label 4590*/ GIMT_Encode4(215792), // Rule ID 10137 //
81173 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasSVEorSME),
81174 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bfmlalt_lane_v2),
81175 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81176 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81177 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81178 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81179 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81180 // MIs[0] Op4
81181 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81182 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81183 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1099:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (BFMLALT_ZZZI:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
81184 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMLALT_ZZZI),
81185 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81186 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81187 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81188 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81189 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81190 GIR_RootConstrainSelectedInstOperands,
81191 // GIR_Coverage, 10137,
81192 GIR_EraseRootFromParent_Done,
81193 // Label 4590: @215792
81194 GIM_Try, /*On fail goto*//*Label 4591*/ GIMT_Encode4(215844), // Rule ID 10919 //
81195 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8_HasSVEorSME),
81196 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sudot_lane),
81197 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81198 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81199 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
81200 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
81201 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81202 // MIs[0] Op4
81203 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81204 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81205 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1687:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (SUDOT_ZZZI:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81206 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUDOT_ZZZI),
81207 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81208 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81209 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81210 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81211 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81212 GIR_RootConstrainSelectedInstOperands,
81213 // GIR_Coverage, 10919,
81214 GIR_EraseRootFromParent_Done,
81215 // Label 4591: @215844
81216 GIM_Try, /*On fail goto*//*Label 4592*/ GIMT_Encode4(215896), // Rule ID 10970 //
81217 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81218 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_lane),
81219 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
81220 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
81221 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81222 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81223 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81224 // MIs[0] Op4
81225 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81226 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81227 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1386:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (MLS_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
81228 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZZZI_H),
81229 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81230 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81231 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81232 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81233 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81234 GIR_RootConstrainSelectedInstOperands,
81235 // GIR_Coverage, 10970,
81236 GIR_EraseRootFromParent_Done,
81237 // Label 4592: @215896
81238 GIM_Try, /*On fail goto*//*Label 4593*/ GIMT_Encode4(215948), // Rule ID 10971 //
81239 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81240 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_lane),
81241 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81242 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81243 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
81244 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
81245 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81246 // MIs[0] Op4
81247 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81248 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81249 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1386:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (MLS_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81250 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZZZI_S),
81251 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81252 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81253 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81254 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81255 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81256 GIR_RootConstrainSelectedInstOperands,
81257 // GIR_Coverage, 10971,
81258 GIR_EraseRootFromParent_Done,
81259 // Label 4593: @215948
81260 GIM_Try, /*On fail goto*//*Label 4594*/ GIMT_Encode4(216000), // Rule ID 10972 //
81261 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81262 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_lane),
81263 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
81264 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
81265 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
81266 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
81267 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81268 // MIs[0] Op4
81269 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81270 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
81271 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1386:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4) => (MLS_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)
81272 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZZZI_D),
81273 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81274 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81275 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81276 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81277 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81278 GIR_RootConstrainSelectedInstOperands,
81279 // GIR_Coverage, 10972,
81280 GIR_EraseRootFromParent_Done,
81281 // Label 4594: @216000
81282 GIM_Try, /*On fail goto*//*Label 4595*/ GIMT_Encode4(216052), // Rule ID 10973 //
81283 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81284 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah_lane),
81285 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
81286 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
81287 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81288 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81289 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81290 // MIs[0] Op4
81291 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81292 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81293 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1604:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (SQRDMLAH_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
81294 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZI_H),
81295 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81296 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81297 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81298 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81299 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81300 GIR_RootConstrainSelectedInstOperands,
81301 // GIR_Coverage, 10973,
81302 GIR_EraseRootFromParent_Done,
81303 // Label 4595: @216052
81304 GIM_Try, /*On fail goto*//*Label 4596*/ GIMT_Encode4(216104), // Rule ID 10974 //
81305 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81306 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah_lane),
81307 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81308 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81309 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
81310 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
81311 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81312 // MIs[0] Op4
81313 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81314 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81315 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1604:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (SQRDMLAH_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81316 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZI_S),
81317 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81318 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81319 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81320 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81321 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81322 GIR_RootConstrainSelectedInstOperands,
81323 // GIR_Coverage, 10974,
81324 GIR_EraseRootFromParent_Done,
81325 // Label 4596: @216104
81326 GIM_Try, /*On fail goto*//*Label 4597*/ GIMT_Encode4(216156), // Rule ID 10975 //
81327 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81328 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah_lane),
81329 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
81330 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
81331 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
81332 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
81333 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81334 // MIs[0] Op4
81335 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81336 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
81337 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1604:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4) => (SQRDMLAH_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)
81338 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZI_D),
81339 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81340 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81341 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81342 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81343 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81344 GIR_RootConstrainSelectedInstOperands,
81345 // GIR_Coverage, 10975,
81346 GIR_EraseRootFromParent_Done,
81347 // Label 4597: @216156
81348 GIM_Try, /*On fail goto*//*Label 4598*/ GIMT_Encode4(216208), // Rule ID 10976 //
81349 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81350 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh_lane),
81351 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
81352 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
81353 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81354 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81355 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81356 // MIs[0] Op4
81357 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81358 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81359 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1606:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (SQRDMLSH_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
81360 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZI_H),
81361 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81362 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81363 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81364 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81365 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81366 GIR_RootConstrainSelectedInstOperands,
81367 // GIR_Coverage, 10976,
81368 GIR_EraseRootFromParent_Done,
81369 // Label 4598: @216208
81370 GIM_Try, /*On fail goto*//*Label 4599*/ GIMT_Encode4(216260), // Rule ID 10977 //
81371 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81372 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh_lane),
81373 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81374 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81375 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
81376 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
81377 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81378 // MIs[0] Op4
81379 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81380 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81381 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1606:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (SQRDMLSH_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81382 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZI_S),
81383 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81384 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81385 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81386 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81387 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81388 GIR_RootConstrainSelectedInstOperands,
81389 // GIR_Coverage, 10977,
81390 GIR_EraseRootFromParent_Done,
81391 // Label 4599: @216260
81392 GIM_Try, /*On fail goto*//*Label 4600*/ GIMT_Encode4(216312), // Rule ID 10978 //
81393 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81394 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh_lane),
81395 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
81396 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
81397 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
81398 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
81399 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81400 // MIs[0] Op4
81401 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81402 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
81403 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1606:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4) => (SQRDMLSH_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)
81404 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZI_D),
81405 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81406 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81407 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81408 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81409 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81410 GIR_RootConstrainSelectedInstOperands,
81411 // GIR_Coverage, 10978,
81412 GIR_EraseRootFromParent_Done,
81413 // Label 4600: @216312
81414 GIM_Try, /*On fail goto*//*Label 4601*/ GIMT_Encode4(216364), // Rule ID 11021 //
81415 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81416 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalt_lane),
81417 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81418 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81419 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81420 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81421 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81422 // MIs[0] Op4
81423 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81424 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81425 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1527:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (SMLALT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
81426 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALT_ZZZI_S),
81427 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81428 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81429 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81430 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81431 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81432 GIR_RootConstrainSelectedInstOperands,
81433 // GIR_Coverage, 11021,
81434 GIR_EraseRootFromParent_Done,
81435 // Label 4601: @216364
81436 GIM_Try, /*On fail goto*//*Label 4602*/ GIMT_Encode4(216416), // Rule ID 11022 //
81437 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81438 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalt_lane),
81439 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
81440 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
81441 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
81442 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
81443 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81444 // MIs[0] Op4
81445 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81446 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81447 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1527:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (SMLALT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81448 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALT_ZZZI_D),
81449 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81450 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81451 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81452 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81453 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81454 GIR_RootConstrainSelectedInstOperands,
81455 // GIR_Coverage, 11022,
81456 GIR_EraseRootFromParent_Done,
81457 // Label 4602: @216416
81458 GIM_Try, /*On fail goto*//*Label 4603*/ GIMT_Encode4(216468), // Rule ID 11023 //
81459 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81460 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalb_lane),
81461 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81462 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81463 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81464 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81465 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81466 // MIs[0] Op4
81467 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81468 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81469 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1763:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (UMLALB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
81470 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALB_ZZZI_S),
81471 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81472 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81473 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81474 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81475 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81476 GIR_RootConstrainSelectedInstOperands,
81477 // GIR_Coverage, 11023,
81478 GIR_EraseRootFromParent_Done,
81479 // Label 4603: @216468
81480 GIM_Try, /*On fail goto*//*Label 4604*/ GIMT_Encode4(216520), // Rule ID 11024 //
81481 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81482 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalb_lane),
81483 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
81484 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
81485 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
81486 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
81487 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81488 // MIs[0] Op4
81489 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81490 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81491 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1763:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (UMLALB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81492 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALB_ZZZI_D),
81493 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81494 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81495 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81496 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81497 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81498 GIR_RootConstrainSelectedInstOperands,
81499 // GIR_Coverage, 11024,
81500 GIR_EraseRootFromParent_Done,
81501 // Label 4604: @216520
81502 GIM_Try, /*On fail goto*//*Label 4605*/ GIMT_Encode4(216572), // Rule ID 11025 //
81503 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81504 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalt_lane),
81505 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81506 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81507 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81508 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81509 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81510 // MIs[0] Op4
81511 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81512 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81513 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1765:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (UMLALT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
81514 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALT_ZZZI_S),
81515 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81516 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81517 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81518 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81519 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81520 GIR_RootConstrainSelectedInstOperands,
81521 // GIR_Coverage, 11025,
81522 GIR_EraseRootFromParent_Done,
81523 // Label 4605: @216572
81524 GIM_Try, /*On fail goto*//*Label 4606*/ GIMT_Encode4(216624), // Rule ID 11026 //
81525 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81526 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalt_lane),
81527 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
81528 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
81529 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
81530 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
81531 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81532 // MIs[0] Op4
81533 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81534 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81535 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1765:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (UMLALT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81536 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALT_ZZZI_D),
81537 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81538 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81539 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81540 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81541 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81542 GIR_RootConstrainSelectedInstOperands,
81543 // GIR_Coverage, 11026,
81544 GIR_EraseRootFromParent_Done,
81545 // Label 4606: @216624
81546 GIM_Try, /*On fail goto*//*Label 4607*/ GIMT_Encode4(216676), // Rule ID 11027 //
81547 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81548 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslb_lane),
81549 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81550 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81551 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81552 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81553 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81554 // MIs[0] Op4
81555 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81556 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81557 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1529:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (SMLSLB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
81558 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLB_ZZZI_S),
81559 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81560 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81561 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81562 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81563 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81564 GIR_RootConstrainSelectedInstOperands,
81565 // GIR_Coverage, 11027,
81566 GIR_EraseRootFromParent_Done,
81567 // Label 4607: @216676
81568 GIM_Try, /*On fail goto*//*Label 4608*/ GIMT_Encode4(216728), // Rule ID 11028 //
81569 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81570 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslb_lane),
81571 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
81572 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
81573 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
81574 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
81575 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81576 // MIs[0] Op4
81577 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81578 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81579 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1529:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (SMLSLB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81580 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLB_ZZZI_D),
81581 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81582 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81583 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81584 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81585 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81586 GIR_RootConstrainSelectedInstOperands,
81587 // GIR_Coverage, 11028,
81588 GIR_EraseRootFromParent_Done,
81589 // Label 4608: @216728
81590 GIM_Try, /*On fail goto*//*Label 4609*/ GIMT_Encode4(216780), // Rule ID 11029 //
81591 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81592 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslt_lane),
81593 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81594 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81595 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81596 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81597 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81598 // MIs[0] Op4
81599 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81600 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81601 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1531:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (SMLSLT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
81602 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLT_ZZZI_S),
81603 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81604 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81605 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81606 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81607 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81608 GIR_RootConstrainSelectedInstOperands,
81609 // GIR_Coverage, 11029,
81610 GIR_EraseRootFromParent_Done,
81611 // Label 4609: @216780
81612 GIM_Try, /*On fail goto*//*Label 4610*/ GIMT_Encode4(216832), // Rule ID 11030 //
81613 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81614 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslt_lane),
81615 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
81616 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
81617 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
81618 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
81619 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81620 // MIs[0] Op4
81621 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81622 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81623 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1531:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (SMLSLT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81624 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLT_ZZZI_D),
81625 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81626 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81627 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81628 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81629 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81630 GIR_RootConstrainSelectedInstOperands,
81631 // GIR_Coverage, 11030,
81632 GIR_EraseRootFromParent_Done,
81633 // Label 4610: @216832
81634 GIM_Try, /*On fail goto*//*Label 4611*/ GIMT_Encode4(216884), // Rule ID 11031 //
81635 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81636 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslb_lane),
81637 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81638 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81639 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81640 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81641 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81642 // MIs[0] Op4
81643 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81644 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81645 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1767:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (UMLSLB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
81646 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLB_ZZZI_S),
81647 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81648 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81649 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81650 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81651 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81652 GIR_RootConstrainSelectedInstOperands,
81653 // GIR_Coverage, 11031,
81654 GIR_EraseRootFromParent_Done,
81655 // Label 4611: @216884
81656 GIM_Try, /*On fail goto*//*Label 4612*/ GIMT_Encode4(216936), // Rule ID 11032 //
81657 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81658 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslb_lane),
81659 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
81660 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
81661 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
81662 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
81663 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81664 // MIs[0] Op4
81665 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81666 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81667 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1767:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (UMLSLB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81668 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLB_ZZZI_D),
81669 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81670 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81671 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81672 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81673 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81674 GIR_RootConstrainSelectedInstOperands,
81675 // GIR_Coverage, 11032,
81676 GIR_EraseRootFromParent_Done,
81677 // Label 4612: @216936
81678 GIM_Try, /*On fail goto*//*Label 4613*/ GIMT_Encode4(216988), // Rule ID 11033 //
81679 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81680 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslt_lane),
81681 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81682 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81683 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81684 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81685 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81686 // MIs[0] Op4
81687 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81688 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81689 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1769:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (UMLSLT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
81690 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLT_ZZZI_S),
81691 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81692 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81693 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81694 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81695 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81696 GIR_RootConstrainSelectedInstOperands,
81697 // GIR_Coverage, 11033,
81698 GIR_EraseRootFromParent_Done,
81699 // Label 4613: @216988
81700 GIM_Try, /*On fail goto*//*Label 4614*/ GIMT_Encode4(217040), // Rule ID 11034 //
81701 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81702 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslt_lane),
81703 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
81704 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
81705 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
81706 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
81707 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81708 // MIs[0] Op4
81709 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81710 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81711 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1769:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (UMLSLT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81712 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLT_ZZZI_D),
81713 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81714 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81715 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81716 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81717 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81718 GIR_RootConstrainSelectedInstOperands,
81719 // GIR_Coverage, 11034,
81720 GIR_EraseRootFromParent_Done,
81721 // Label 4614: @217040
81722 GIM_Try, /*On fail goto*//*Label 4615*/ GIMT_Encode4(217092), // Rule ID 11056 //
81723 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81724 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalb_lane),
81725 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81726 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81727 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81728 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81729 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81730 // MIs[0] Op4
81731 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81732 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81733 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1567:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (SQDMLALB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
81734 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALB_ZZZI_S),
81735 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81736 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81737 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81738 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81739 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81740 GIR_RootConstrainSelectedInstOperands,
81741 // GIR_Coverage, 11056,
81742 GIR_EraseRootFromParent_Done,
81743 // Label 4615: @217092
81744 GIM_Try, /*On fail goto*//*Label 4616*/ GIMT_Encode4(217144), // Rule ID 11057 //
81745 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81746 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalb_lane),
81747 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
81748 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
81749 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
81750 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
81751 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81752 // MIs[0] Op4
81753 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81754 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81755 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1567:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (SQDMLALB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81756 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALB_ZZZI_D),
81757 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81758 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81759 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81760 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81761 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81762 GIR_RootConstrainSelectedInstOperands,
81763 // GIR_Coverage, 11057,
81764 GIR_EraseRootFromParent_Done,
81765 // Label 4616: @217144
81766 GIM_Try, /*On fail goto*//*Label 4617*/ GIMT_Encode4(217196), // Rule ID 11058 //
81767 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81768 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalt_lane),
81769 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81770 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81771 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81772 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81773 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81774 // MIs[0] Op4
81775 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81776 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81777 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1570:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (SQDMLALT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
81778 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALT_ZZZI_S),
81779 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81780 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81781 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81782 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81783 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81784 GIR_RootConstrainSelectedInstOperands,
81785 // GIR_Coverage, 11058,
81786 GIR_EraseRootFromParent_Done,
81787 // Label 4617: @217196
81788 GIM_Try, /*On fail goto*//*Label 4618*/ GIMT_Encode4(217248), // Rule ID 11059 //
81789 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81790 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalt_lane),
81791 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
81792 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
81793 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
81794 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
81795 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81796 // MIs[0] Op4
81797 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81798 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81799 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1570:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (SQDMLALT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81800 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALT_ZZZI_D),
81801 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81802 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81803 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81804 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81805 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81806 GIR_RootConstrainSelectedInstOperands,
81807 // GIR_Coverage, 11059,
81808 GIR_EraseRootFromParent_Done,
81809 // Label 4618: @217248
81810 GIM_Try, /*On fail goto*//*Label 4619*/ GIMT_Encode4(217300), // Rule ID 11060 //
81811 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81812 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslb_lane),
81813 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81814 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81815 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81816 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81817 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81818 // MIs[0] Op4
81819 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81820 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81821 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1572:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (SQDMLSLB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
81822 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLB_ZZZI_S),
81823 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81824 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81825 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81826 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81827 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81828 GIR_RootConstrainSelectedInstOperands,
81829 // GIR_Coverage, 11060,
81830 GIR_EraseRootFromParent_Done,
81831 // Label 4619: @217300
81832 GIM_Try, /*On fail goto*//*Label 4620*/ GIMT_Encode4(217352), // Rule ID 11061 //
81833 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81834 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslb_lane),
81835 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
81836 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
81837 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
81838 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
81839 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81840 // MIs[0] Op4
81841 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81842 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81843 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1572:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (SQDMLSLB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81844 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLB_ZZZI_D),
81845 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81846 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81847 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81848 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81849 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81850 GIR_RootConstrainSelectedInstOperands,
81851 // GIR_Coverage, 11061,
81852 GIR_EraseRootFromParent_Done,
81853 // Label 4620: @217352
81854 GIM_Try, /*On fail goto*//*Label 4621*/ GIMT_Encode4(217404), // Rule ID 11062 //
81855 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81856 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslt_lane),
81857 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81858 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81859 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81860 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81861 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81862 // MIs[0] Op4
81863 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81864 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81865 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1575:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (SQDMLSLT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
81866 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLT_ZZZI_S),
81867 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81868 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81869 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81870 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81871 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81872 GIR_RootConstrainSelectedInstOperands,
81873 // GIR_Coverage, 11062,
81874 GIR_EraseRootFromParent_Done,
81875 // Label 4621: @217404
81876 GIM_Try, /*On fail goto*//*Label 4622*/ GIMT_Encode4(217456), // Rule ID 11063 //
81877 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81878 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslt_lane),
81879 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
81880 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
81881 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
81882 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
81883 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81884 // MIs[0] Op4
81885 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81886 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81887 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1575:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (SQDMLSLT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81888 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLT_ZZZI_D),
81889 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81890 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81891 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81892 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81893 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81894 GIR_RootConstrainSelectedInstOperands,
81895 // GIR_Coverage, 11063,
81896 GIR_EraseRootFromParent_Done,
81897 // Label 4622: @217456
81898 GIM_Try, /*On fail goto*//*Label 4623*/ GIMT_Encode4(217508), // Rule ID 11517 //
81899 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81900 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlalb_lane),
81901 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81902 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81903 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81904 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81905 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81906 // MIs[0] Op4
81907 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81908 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81909 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1277:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (FMLALB_ZZZI_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
81910 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALB_ZZZI_SHH),
81911 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81912 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81913 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81914 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81915 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81916 GIR_RootConstrainSelectedInstOperands,
81917 // GIR_Coverage, 11517,
81918 GIR_EraseRootFromParent_Done,
81919 // Label 4623: @217508
81920 GIM_Try, /*On fail goto*//*Label 4624*/ GIMT_Encode4(217560), // Rule ID 11518 //
81921 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81922 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlalt_lane),
81923 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81924 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81925 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81926 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81927 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81928 // MIs[0] Op4
81929 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81930 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81931 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1279:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (FMLALT_ZZZI_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
81932 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALT_ZZZI_SHH),
81933 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81934 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81935 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81936 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81937 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81938 GIR_RootConstrainSelectedInstOperands,
81939 // GIR_Coverage, 11518,
81940 GIR_EraseRootFromParent_Done,
81941 // Label 4624: @217560
81942 GIM_Try, /*On fail goto*//*Label 4625*/ GIMT_Encode4(217612), // Rule ID 11519 //
81943 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81944 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlslb_lane),
81945 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81946 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81947 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81948 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81949 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81950 // MIs[0] Op4
81951 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81952 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81953 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1284:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (FMLSLB_ZZZI_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
81954 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLB_ZZZI_SHH),
81955 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81956 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81957 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81958 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81959 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81960 GIR_RootConstrainSelectedInstOperands,
81961 // GIR_Coverage, 11519,
81962 GIR_EraseRootFromParent_Done,
81963 // Label 4625: @217612
81964 GIM_Try, /*On fail goto*//*Label 4626*/ GIMT_Encode4(217664), // Rule ID 11520 //
81965 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
81966 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlslt_lane),
81967 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81968 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81969 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81970 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81971 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81972 // MIs[0] Op4
81973 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81974 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
81975 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1286:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (FMLSLT_ZZZI_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
81976 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLT_ZZZI_SHH),
81977 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
81978 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
81979 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
81980 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
81981 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
81982 GIR_RootConstrainSelectedInstOperands,
81983 // GIR_Coverage, 11520,
81984 GIR_EraseRootFromParent_Done,
81985 // Label 4626: @217664
81986 GIM_Try, /*On fail goto*//*Label 4627*/ GIMT_Encode4(217716), // Rule ID 11646 //
81987 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2),
81988 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdot_lane_x2),
81989 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
81990 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
81991 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
81992 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
81993 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
81994 // MIs[0] Op4
81995 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
81996 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
81997 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1232:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (FDOT_ZZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
81998 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOT_ZZZI_S),
81999 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82000 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82001 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82002 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82003 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82004 GIR_RootConstrainSelectedInstOperands,
82005 // GIR_Coverage, 11646,
82006 GIR_EraseRootFromParent_Done,
82007 // Label 4627: @217716
82008 GIM_Try, /*On fail goto*//*Label 4628*/ GIMT_Encode4(217768), // Rule ID 11649 //
82009 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2),
82010 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bfmlslb_lane),
82011 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
82012 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
82013 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
82014 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
82015 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82016 // MIs[0] Op4
82017 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
82018 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
82019 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1101:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (BFMLSLB_ZZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
82020 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMLSLB_ZZZI_S),
82021 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82022 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82023 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82024 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82025 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82026 GIR_RootConstrainSelectedInstOperands,
82027 // GIR_Coverage, 11649,
82028 GIR_EraseRootFromParent_Done,
82029 // Label 4628: @217768
82030 GIM_Try, /*On fail goto*//*Label 4629*/ GIMT_Encode4(217820), // Rule ID 11650 //
82031 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2),
82032 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bfmlslt_lane),
82033 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
82034 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
82035 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
82036 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
82037 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82038 // MIs[0] Op4
82039 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
82040 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
82041 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1103:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4) => (BFMLSLT_ZZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
82042 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMLSLT_ZZZI_S),
82043 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82044 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82045 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82046 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82047 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82048 GIR_RootConstrainSelectedInstOperands,
82049 // GIR_Coverage, 11650,
82050 GIR_EraseRootFromParent_Done,
82051 // Label 4629: @217820
82052 GIM_Try, /*On fail goto*//*Label 4630*/ GIMT_Encode4(217872), // Rule ID 11652 //
82053 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_HasSME2),
82054 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udot_lane_x2),
82055 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
82056 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
82057 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
82058 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
82059 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82060 // MIs[0] Op4
82061 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
82062 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
82063 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1739:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4) => (UDOT_ZZZI_HtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
82064 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDOT_ZZZI_HtoS),
82065 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82066 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82067 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82068 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82069 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82070 GIR_RootConstrainSelectedInstOperands,
82071 // GIR_Coverage, 11652,
82072 GIR_EraseRootFromParent_Done,
82073 // Label 4630: @217872
82074 GIM_Try, /*On fail goto*//*Label 4631*/ GIMT_Encode4(217924), // Rule ID 11769 //
82075 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasB16B16_HasSVE2orSME2),
82076 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_lane),
82077 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
82078 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
82079 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
82080 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
82081 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82082 // MIs[0] idx
82083 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
82084 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
82085 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1281:{ *:[iPTR] }, nxv8bf16:{ *:[nxv8bf16] }:$op1, nxv8bf16:{ *:[nxv8bf16] }:$op2, nxv8bf16:{ *:[nxv8bf16] }:$op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx) => (BFMLS_ZZZI:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$op1, ?:{ *:[nxv8bf16] }:$op2, ?:{ *:[nxv8bf16] }:$op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)
82086 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMLS_ZZZI),
82087 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82088 GIR_RootToRootCopy, /*OpIdx*/2, // op1
82089 GIR_RootToRootCopy, /*OpIdx*/3, // op2
82090 GIR_RootToRootCopy, /*OpIdx*/4, // op3
82091 GIR_RootToRootCopy, /*OpIdx*/5, // idx
82092 GIR_RootConstrainSelectedInstOperands,
82093 // GIR_Coverage, 11769,
82094 GIR_EraseRootFromParent_Done,
82095 // Label 4631: @217924
82096 GIM_Try, /*On fail goto*//*Label 4632*/ GIMT_Encode4(217971), // Rule ID 2747 //
82097 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82098 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla),
82099 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
82100 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
82101 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
82102 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
82103 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
82104 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82105 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1273:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4) => (FMLA_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
82106 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZPmZZ_H),
82107 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82108 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82109 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82110 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82111 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82112 GIR_RootConstrainSelectedInstOperands,
82113 // GIR_Coverage, 2747,
82114 GIR_EraseRootFromParent_Done,
82115 // Label 4632: @217971
82116 GIM_Try, /*On fail goto*//*Label 4633*/ GIMT_Encode4(218018), // Rule ID 2750 //
82117 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82118 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla),
82119 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
82120 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
82121 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
82122 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
82123 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
82124 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82125 // (intrinsic_wo_chain:{ *:[nxv4f16] } 1273:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4) => (FMLA_ZPmZZ_H:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
82126 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZPmZZ_H),
82127 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82128 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82129 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82130 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82131 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82132 GIR_RootConstrainSelectedInstOperands,
82133 // GIR_Coverage, 2750,
82134 GIR_EraseRootFromParent_Done,
82135 // Label 4633: @218018
82136 GIM_Try, /*On fail goto*//*Label 4634*/ GIMT_Encode4(218065), // Rule ID 2753 //
82137 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82138 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla),
82139 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
82140 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
82141 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
82142 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
82143 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
82144 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82145 // (intrinsic_wo_chain:{ *:[nxv2f16] } 1273:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4) => (FMLA_ZPmZZ_H:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
82146 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZPmZZ_H),
82147 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82148 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82149 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82150 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82151 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82152 GIR_RootConstrainSelectedInstOperands,
82153 // GIR_Coverage, 2753,
82154 GIR_EraseRootFromParent_Done,
82155 // Label 4634: @218065
82156 GIM_Try, /*On fail goto*//*Label 4635*/ GIMT_Encode4(218112), // Rule ID 2756 //
82157 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82158 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla),
82159 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
82160 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
82161 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
82162 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
82163 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
82164 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82165 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1273:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4) => (FMLA_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
82166 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZPmZZ_S),
82167 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82168 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82169 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82170 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82171 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82172 GIR_RootConstrainSelectedInstOperands,
82173 // GIR_Coverage, 2756,
82174 GIR_EraseRootFromParent_Done,
82175 // Label 4635: @218112
82176 GIM_Try, /*On fail goto*//*Label 4636*/ GIMT_Encode4(218159), // Rule ID 2759 //
82177 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82178 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla),
82179 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
82180 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
82181 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
82182 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
82183 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
82184 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82185 // (intrinsic_wo_chain:{ *:[nxv2f32] } 1273:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4) => (FMLA_ZPmZZ_S:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
82186 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZPmZZ_S),
82187 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82188 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82189 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82190 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82191 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82192 GIR_RootConstrainSelectedInstOperands,
82193 // GIR_Coverage, 2759,
82194 GIR_EraseRootFromParent_Done,
82195 // Label 4636: @218159
82196 GIM_Try, /*On fail goto*//*Label 4637*/ GIMT_Encode4(218206), // Rule ID 2762 //
82197 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82198 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla),
82199 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
82200 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
82201 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
82202 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
82203 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
82204 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82205 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1273:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4) => (FMLA_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
82206 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZPmZZ_D),
82207 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82208 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82209 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82210 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82211 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82212 GIR_RootConstrainSelectedInstOperands,
82213 // GIR_Coverage, 2762,
82214 GIR_EraseRootFromParent_Done,
82215 // Label 4637: @218206
82216 GIM_Try, /*On fail goto*//*Label 4638*/ GIMT_Encode4(218253), // Rule ID 2765 //
82217 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasB16B16_HasSVE2orSME2),
82218 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla),
82219 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
82220 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
82221 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
82222 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
82223 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
82224 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82225 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1273:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3, nxv8bf16:{ *:[nxv8bf16] }:$Op4) => (BFMLA_ZPmZZ:{ *:[nxv8bf16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3, ?:{ *:[nxv8bf16] }:$Op4)
82226 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMLA_ZPmZZ),
82227 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82228 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82229 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82230 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82231 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82232 GIR_RootConstrainSelectedInstOperands,
82233 // GIR_Coverage, 2765,
82234 GIR_EraseRootFromParent_Done,
82235 // Label 4638: @218253
82236 GIM_Try, /*On fail goto*//*Label 4639*/ GIMT_Encode4(218300), // Rule ID 2768 //
82237 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82238 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmad),
82239 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
82240 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
82241 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
82242 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
82243 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
82244 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82245 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1236:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4) => (FMAD_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
82246 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAD_ZPmZZ_H),
82247 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
82248 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82249 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82250 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82251 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82252 GIR_RootConstrainSelectedInstOperands,
82253 // GIR_Coverage, 2768,
82254 GIR_EraseRootFromParent_Done,
82255 // Label 4639: @218300
82256 GIM_Try, /*On fail goto*//*Label 4640*/ GIMT_Encode4(218347), // Rule ID 2769 //
82257 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82258 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmad),
82259 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
82260 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
82261 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
82262 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
82263 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
82264 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82265 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1236:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4) => (FMAD_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
82266 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAD_ZPmZZ_S),
82267 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
82268 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82269 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82270 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82271 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82272 GIR_RootConstrainSelectedInstOperands,
82273 // GIR_Coverage, 2769,
82274 GIR_EraseRootFromParent_Done,
82275 // Label 4640: @218347
82276 GIM_Try, /*On fail goto*//*Label 4641*/ GIMT_Encode4(218394), // Rule ID 2770 //
82277 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82278 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmad),
82279 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
82280 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
82281 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
82282 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
82283 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
82284 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82285 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1236:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4) => (FMAD_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
82286 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAD_ZPmZZ_D),
82287 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
82288 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82289 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82290 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82291 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82292 GIR_RootConstrainSelectedInstOperands,
82293 // GIR_Coverage, 2770,
82294 GIR_EraseRootFromParent_Done,
82295 // Label 4641: @218394
82296 GIM_Try, /*On fail goto*//*Label 4642*/ GIMT_Encode4(218441), // Rule ID 2870 //
82297 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82298 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mad),
82299 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
82300 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
82301 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
82302 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
82303 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
82304 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82305 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1380:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op4) => (MAD_ZPmZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i8] }:$Op4)
82306 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MAD_ZPmZZ_B),
82307 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
82308 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82309 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82310 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82311 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82312 GIR_RootConstrainSelectedInstOperands,
82313 // GIR_Coverage, 2870,
82314 GIR_EraseRootFromParent_Done,
82315 // Label 4642: @218441
82316 GIM_Try, /*On fail goto*//*Label 4643*/ GIMT_Encode4(218488), // Rule ID 2873 //
82317 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82318 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mad),
82319 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
82320 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
82321 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
82322 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
82323 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
82324 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82325 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1380:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op4) => (MAD_ZPmZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i16] }:$Op4)
82326 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MAD_ZPmZZ_H),
82327 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
82328 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82329 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82330 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82331 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82332 GIR_RootConstrainSelectedInstOperands,
82333 // GIR_Coverage, 2873,
82334 GIR_EraseRootFromParent_Done,
82335 // Label 4643: @218488
82336 GIM_Try, /*On fail goto*//*Label 4644*/ GIMT_Encode4(218535), // Rule ID 2876 //
82337 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82338 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mad),
82339 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
82340 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
82341 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
82342 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
82343 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
82344 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82345 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1380:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op4) => (MAD_ZPmZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i32] }:$Op4)
82346 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MAD_ZPmZZ_S),
82347 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
82348 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82349 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82350 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82351 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82352 GIR_RootConstrainSelectedInstOperands,
82353 // GIR_Coverage, 2876,
82354 GIR_EraseRootFromParent_Done,
82355 // Label 4644: @218535
82356 GIM_Try, /*On fail goto*//*Label 4645*/ GIMT_Encode4(218582), // Rule ID 2879 //
82357 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82358 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mad),
82359 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
82360 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
82361 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
82362 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
82363 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
82364 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82365 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1380:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op4) => (MAD_ZPmZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i64] }:$Op4)
82366 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MAD_ZPmZZ_D),
82367 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
82368 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82369 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82370 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82371 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82372 GIR_RootConstrainSelectedInstOperands,
82373 // GIR_Coverage, 2879,
82374 GIR_EraseRootFromParent_Done,
82375 // Label 4645: @218582
82376 GIM_Try, /*On fail goto*//*Label 4646*/ GIMT_Encode4(218629), // Rule ID 2882 //
82377 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82378 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla),
82379 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
82380 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
82381 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
82382 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
82383 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
82384 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82385 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1382:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op4) => (MLA_ZPmZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i8] }:$Op4)
82386 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPmZZ_B),
82387 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82388 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82389 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82390 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82391 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82392 GIR_RootConstrainSelectedInstOperands,
82393 // GIR_Coverage, 2882,
82394 GIR_EraseRootFromParent_Done,
82395 // Label 4646: @218629
82396 GIM_Try, /*On fail goto*//*Label 4647*/ GIMT_Encode4(218676), // Rule ID 2884 //
82397 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82398 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla),
82399 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
82400 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
82401 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
82402 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
82403 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
82404 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82405 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1382:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op4) => (MLA_ZPmZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i16] }:$Op4)
82406 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPmZZ_H),
82407 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82408 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82409 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82410 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82411 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82412 GIR_RootConstrainSelectedInstOperands,
82413 // GIR_Coverage, 2884,
82414 GIR_EraseRootFromParent_Done,
82415 // Label 4647: @218676
82416 GIM_Try, /*On fail goto*//*Label 4648*/ GIMT_Encode4(218723), // Rule ID 2886 //
82417 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82418 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla),
82419 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
82420 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
82421 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
82422 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
82423 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
82424 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82425 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1382:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op4) => (MLA_ZPmZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i32] }:$Op4)
82426 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPmZZ_S),
82427 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82428 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82429 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82430 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82431 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82432 GIR_RootConstrainSelectedInstOperands,
82433 // GIR_Coverage, 2886,
82434 GIR_EraseRootFromParent_Done,
82435 // Label 4648: @218723
82436 GIM_Try, /*On fail goto*//*Label 4649*/ GIMT_Encode4(218770), // Rule ID 2888 //
82437 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82438 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla),
82439 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
82440 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
82441 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
82442 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
82443 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
82444 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82445 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1382:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op4) => (MLA_ZPmZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i64] }:$Op4)
82446 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPmZZ_D),
82447 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82448 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82449 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82450 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82451 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82452 GIR_RootConstrainSelectedInstOperands,
82453 // GIR_Coverage, 2888,
82454 GIR_EraseRootFromParent_Done,
82455 // Label 4649: @218770
82456 GIM_Try, /*On fail goto*//*Label 4650*/ GIMT_Encode4(218817), // Rule ID 7224 //
82457 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82458 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_msb),
82459 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
82460 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
82461 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
82462 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
82463 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
82464 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82465 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1388:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op4) => (MSB_ZPmZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i8] }:$Op4)
82466 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSB_ZPmZZ_B),
82467 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
82468 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82469 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82470 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82471 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82472 GIR_RootConstrainSelectedInstOperands,
82473 // GIR_Coverage, 7224,
82474 GIR_EraseRootFromParent_Done,
82475 // Label 4650: @218817
82476 GIM_Try, /*On fail goto*//*Label 4651*/ GIMT_Encode4(218864), // Rule ID 7227 //
82477 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82478 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_msb),
82479 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
82480 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
82481 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
82482 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
82483 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
82484 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82485 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1388:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op4) => (MSB_ZPmZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i16] }:$Op4)
82486 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSB_ZPmZZ_H),
82487 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
82488 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82489 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82490 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82491 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82492 GIR_RootConstrainSelectedInstOperands,
82493 // GIR_Coverage, 7227,
82494 GIR_EraseRootFromParent_Done,
82495 // Label 4651: @218864
82496 GIM_Try, /*On fail goto*//*Label 4652*/ GIMT_Encode4(218911), // Rule ID 7230 //
82497 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82498 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_msb),
82499 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
82500 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
82501 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
82502 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
82503 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
82504 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82505 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1388:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op4) => (MSB_ZPmZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i32] }:$Op4)
82506 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSB_ZPmZZ_S),
82507 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
82508 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82509 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82510 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82511 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82512 GIR_RootConstrainSelectedInstOperands,
82513 // GIR_Coverage, 7230,
82514 GIR_EraseRootFromParent_Done,
82515 // Label 4652: @218911
82516 GIM_Try, /*On fail goto*//*Label 4653*/ GIMT_Encode4(218958), // Rule ID 7233 //
82517 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82518 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_msb),
82519 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
82520 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
82521 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
82522 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
82523 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
82524 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82525 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1388:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op4) => (MSB_ZPmZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i64] }:$Op4)
82526 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSB_ZPmZZ_D),
82527 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
82528 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82529 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82530 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82531 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82532 GIR_RootConstrainSelectedInstOperands,
82533 // GIR_Coverage, 7233,
82534 GIR_EraseRootFromParent_Done,
82535 // Label 4653: @218958
82536 GIM_Try, /*On fail goto*//*Label 4654*/ GIMT_Encode4(219005), // Rule ID 7236 //
82537 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82538 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls),
82539 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
82540 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
82541 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
82542 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
82543 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
82544 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82545 // (intrinsic_wo_chain:{ *:[nxv16i8] } 1385:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op4) => (MLS_ZPmZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i8] }:$Op4)
82546 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPmZZ_B),
82547 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82548 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82549 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82550 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82551 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82552 GIR_RootConstrainSelectedInstOperands,
82553 // GIR_Coverage, 7236,
82554 GIR_EraseRootFromParent_Done,
82555 // Label 4654: @219005
82556 GIM_Try, /*On fail goto*//*Label 4655*/ GIMT_Encode4(219052), // Rule ID 7238 //
82557 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82558 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls),
82559 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
82560 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
82561 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
82562 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
82563 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
82564 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82565 // (intrinsic_wo_chain:{ *:[nxv8i16] } 1385:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op4) => (MLS_ZPmZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i16] }:$Op4)
82566 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPmZZ_H),
82567 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82568 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82569 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82570 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82571 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82572 GIR_RootConstrainSelectedInstOperands,
82573 // GIR_Coverage, 7238,
82574 GIR_EraseRootFromParent_Done,
82575 // Label 4655: @219052
82576 GIM_Try, /*On fail goto*//*Label 4656*/ GIMT_Encode4(219099), // Rule ID 7240 //
82577 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82578 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls),
82579 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
82580 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
82581 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
82582 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
82583 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
82584 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82585 // (intrinsic_wo_chain:{ *:[nxv4i32] } 1385:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op4) => (MLS_ZPmZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i32] }:$Op4)
82586 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPmZZ_S),
82587 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82588 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82589 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82590 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82591 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82592 GIR_RootConstrainSelectedInstOperands,
82593 // GIR_Coverage, 7240,
82594 GIR_EraseRootFromParent_Done,
82595 // Label 4656: @219099
82596 GIM_Try, /*On fail goto*//*Label 4657*/ GIMT_Encode4(219146), // Rule ID 7242 //
82597 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82598 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls),
82599 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
82600 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
82601 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
82602 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
82603 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
82604 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82605 // (intrinsic_wo_chain:{ *:[nxv2i64] } 1385:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op4) => (MLS_ZPmZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i64] }:$Op4)
82606 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPmZZ_D),
82607 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82608 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82609 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82610 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82611 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82612 GIR_RootConstrainSelectedInstOperands,
82613 // GIR_Coverage, 7242,
82614 GIR_EraseRootFromParent_Done,
82615 // Label 4657: @219146
82616 GIM_Try, /*On fail goto*//*Label 4658*/ GIMT_Encode4(219193), // Rule ID 7871 //
82617 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82618 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls),
82619 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
82620 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
82621 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
82622 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
82623 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
82624 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82625 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1280:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4) => (FMLS_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
82626 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPmZZ_H),
82627 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82628 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82629 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82630 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82631 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82632 GIR_RootConstrainSelectedInstOperands,
82633 // GIR_Coverage, 7871,
82634 GIR_EraseRootFromParent_Done,
82635 // Label 4658: @219193
82636 GIM_Try, /*On fail goto*//*Label 4659*/ GIMT_Encode4(219240), // Rule ID 7874 //
82637 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82638 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls),
82639 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
82640 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
82641 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
82642 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
82643 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
82644 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82645 // (intrinsic_wo_chain:{ *:[nxv4f16] } 1280:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4) => (FMLS_ZPmZZ_H:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
82646 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPmZZ_H),
82647 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82648 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82649 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82650 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82651 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82652 GIR_RootConstrainSelectedInstOperands,
82653 // GIR_Coverage, 7874,
82654 GIR_EraseRootFromParent_Done,
82655 // Label 4659: @219240
82656 GIM_Try, /*On fail goto*//*Label 4660*/ GIMT_Encode4(219287), // Rule ID 7877 //
82657 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82658 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls),
82659 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
82660 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
82661 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
82662 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
82663 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
82664 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82665 // (intrinsic_wo_chain:{ *:[nxv2f16] } 1280:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4) => (FMLS_ZPmZZ_H:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
82666 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPmZZ_H),
82667 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82668 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82669 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82670 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82671 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82672 GIR_RootConstrainSelectedInstOperands,
82673 // GIR_Coverage, 7877,
82674 GIR_EraseRootFromParent_Done,
82675 // Label 4660: @219287
82676 GIM_Try, /*On fail goto*//*Label 4661*/ GIMT_Encode4(219334), // Rule ID 7880 //
82677 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82678 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls),
82679 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
82680 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
82681 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
82682 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
82683 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
82684 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82685 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1280:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4) => (FMLS_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
82686 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPmZZ_S),
82687 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82688 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82689 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82690 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82691 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82692 GIR_RootConstrainSelectedInstOperands,
82693 // GIR_Coverage, 7880,
82694 GIR_EraseRootFromParent_Done,
82695 // Label 4661: @219334
82696 GIM_Try, /*On fail goto*//*Label 4662*/ GIMT_Encode4(219381), // Rule ID 7883 //
82697 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82698 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls),
82699 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
82700 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
82701 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
82702 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
82703 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
82704 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82705 // (intrinsic_wo_chain:{ *:[nxv2f32] } 1280:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4) => (FMLS_ZPmZZ_S:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
82706 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPmZZ_S),
82707 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82708 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82709 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82710 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82711 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82712 GIR_RootConstrainSelectedInstOperands,
82713 // GIR_Coverage, 7883,
82714 GIR_EraseRootFromParent_Done,
82715 // Label 4662: @219381
82716 GIM_Try, /*On fail goto*//*Label 4663*/ GIMT_Encode4(219428), // Rule ID 7886 //
82717 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82718 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls),
82719 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
82720 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
82721 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
82722 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
82723 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
82724 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82725 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1280:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4) => (FMLS_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
82726 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPmZZ_D),
82727 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82728 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82729 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82730 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82731 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82732 GIR_RootConstrainSelectedInstOperands,
82733 // GIR_Coverage, 7886,
82734 GIR_EraseRootFromParent_Done,
82735 // Label 4663: @219428
82736 GIM_Try, /*On fail goto*//*Label 4664*/ GIMT_Encode4(219475), // Rule ID 7889 //
82737 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82738 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla),
82739 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
82740 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
82741 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
82742 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
82743 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
82744 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82745 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1296:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4) => (FNMLA_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
82746 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPmZZ_H),
82747 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82748 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82749 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82750 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82751 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82752 GIR_RootConstrainSelectedInstOperands,
82753 // GIR_Coverage, 7889,
82754 GIR_EraseRootFromParent_Done,
82755 // Label 4664: @219475
82756 GIM_Try, /*On fail goto*//*Label 4665*/ GIMT_Encode4(219522), // Rule ID 7890 //
82757 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82758 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla),
82759 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
82760 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
82761 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
82762 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
82763 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
82764 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82765 // (intrinsic_wo_chain:{ *:[nxv4f16] } 1296:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4) => (FNMLA_ZPmZZ_H:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
82766 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPmZZ_H),
82767 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82768 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82769 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82770 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82771 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82772 GIR_RootConstrainSelectedInstOperands,
82773 // GIR_Coverage, 7890,
82774 GIR_EraseRootFromParent_Done,
82775 // Label 4665: @219522
82776 GIM_Try, /*On fail goto*//*Label 4666*/ GIMT_Encode4(219569), // Rule ID 7891 //
82777 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82778 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla),
82779 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
82780 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
82781 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
82782 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
82783 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
82784 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82785 // (intrinsic_wo_chain:{ *:[nxv2f16] } 1296:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4) => (FNMLA_ZPmZZ_H:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
82786 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPmZZ_H),
82787 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82788 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82789 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82790 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82791 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82792 GIR_RootConstrainSelectedInstOperands,
82793 // GIR_Coverage, 7891,
82794 GIR_EraseRootFromParent_Done,
82795 // Label 4666: @219569
82796 GIM_Try, /*On fail goto*//*Label 4667*/ GIMT_Encode4(219616), // Rule ID 7892 //
82797 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82798 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla),
82799 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
82800 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
82801 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
82802 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
82803 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
82804 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82805 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1296:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4) => (FNMLA_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
82806 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPmZZ_S),
82807 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82808 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82809 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82810 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82811 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82812 GIR_RootConstrainSelectedInstOperands,
82813 // GIR_Coverage, 7892,
82814 GIR_EraseRootFromParent_Done,
82815 // Label 4667: @219616
82816 GIM_Try, /*On fail goto*//*Label 4668*/ GIMT_Encode4(219663), // Rule ID 7893 //
82817 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82818 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla),
82819 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
82820 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
82821 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
82822 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
82823 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
82824 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82825 // (intrinsic_wo_chain:{ *:[nxv2f32] } 1296:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4) => (FNMLA_ZPmZZ_S:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
82826 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPmZZ_S),
82827 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82828 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82829 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82830 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82831 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82832 GIR_RootConstrainSelectedInstOperands,
82833 // GIR_Coverage, 7893,
82834 GIR_EraseRootFromParent_Done,
82835 // Label 4668: @219663
82836 GIM_Try, /*On fail goto*//*Label 4669*/ GIMT_Encode4(219710), // Rule ID 7894 //
82837 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82838 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla),
82839 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
82840 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
82841 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
82842 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
82843 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
82844 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82845 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1296:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4) => (FNMLA_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
82846 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPmZZ_D),
82847 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82848 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82849 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82850 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82851 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82852 GIR_RootConstrainSelectedInstOperands,
82853 // GIR_Coverage, 7894,
82854 GIR_EraseRootFromParent_Done,
82855 // Label 4669: @219710
82856 GIM_Try, /*On fail goto*//*Label 4670*/ GIMT_Encode4(219757), // Rule ID 7895 //
82857 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82858 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls),
82859 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
82860 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
82861 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
82862 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
82863 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
82864 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82865 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1298:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4) => (FNMLS_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
82866 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPmZZ_H),
82867 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82868 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82869 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82870 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82871 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82872 GIR_RootConstrainSelectedInstOperands,
82873 // GIR_Coverage, 7895,
82874 GIR_EraseRootFromParent_Done,
82875 // Label 4670: @219757
82876 GIM_Try, /*On fail goto*//*Label 4671*/ GIMT_Encode4(219804), // Rule ID 7896 //
82877 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82878 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls),
82879 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
82880 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
82881 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
82882 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
82883 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
82884 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82885 // (intrinsic_wo_chain:{ *:[nxv4f16] } 1298:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4) => (FNMLS_ZPmZZ_H:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
82886 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPmZZ_H),
82887 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82888 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82889 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82890 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82891 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82892 GIR_RootConstrainSelectedInstOperands,
82893 // GIR_Coverage, 7896,
82894 GIR_EraseRootFromParent_Done,
82895 // Label 4671: @219804
82896 GIM_Try, /*On fail goto*//*Label 4672*/ GIMT_Encode4(219851), // Rule ID 7897 //
82897 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82898 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls),
82899 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
82900 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
82901 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
82902 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
82903 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
82904 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82905 // (intrinsic_wo_chain:{ *:[nxv2f16] } 1298:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4) => (FNMLS_ZPmZZ_H:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
82906 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPmZZ_H),
82907 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82908 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82909 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82910 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82911 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82912 GIR_RootConstrainSelectedInstOperands,
82913 // GIR_Coverage, 7897,
82914 GIR_EraseRootFromParent_Done,
82915 // Label 4672: @219851
82916 GIM_Try, /*On fail goto*//*Label 4673*/ GIMT_Encode4(219898), // Rule ID 7898 //
82917 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82918 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls),
82919 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
82920 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
82921 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
82922 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
82923 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
82924 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82925 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1298:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4) => (FNMLS_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
82926 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPmZZ_S),
82927 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82928 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82929 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82930 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82931 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82932 GIR_RootConstrainSelectedInstOperands,
82933 // GIR_Coverage, 7898,
82934 GIR_EraseRootFromParent_Done,
82935 // Label 4673: @219898
82936 GIM_Try, /*On fail goto*//*Label 4674*/ GIMT_Encode4(219945), // Rule ID 7899 //
82937 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82938 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls),
82939 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
82940 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
82941 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
82942 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
82943 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
82944 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82945 // (intrinsic_wo_chain:{ *:[nxv2f32] } 1298:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4) => (FNMLS_ZPmZZ_S:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
82946 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPmZZ_S),
82947 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82948 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82949 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82950 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82951 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82952 GIR_RootConstrainSelectedInstOperands,
82953 // GIR_Coverage, 7899,
82954 GIR_EraseRootFromParent_Done,
82955 // Label 4674: @219945
82956 GIM_Try, /*On fail goto*//*Label 4675*/ GIMT_Encode4(219992), // Rule ID 7900 //
82957 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82958 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls),
82959 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
82960 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
82961 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
82962 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
82963 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
82964 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82965 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1298:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4) => (FNMLS_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
82966 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPmZZ_D),
82967 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
82968 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82969 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82970 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82971 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82972 GIR_RootConstrainSelectedInstOperands,
82973 // GIR_Coverage, 7900,
82974 GIR_EraseRootFromParent_Done,
82975 // Label 4675: @219992
82976 GIM_Try, /*On fail goto*//*Label 4676*/ GIMT_Encode4(220039), // Rule ID 7901 //
82977 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82978 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmsb),
82979 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
82980 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
82981 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
82982 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
82983 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
82984 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
82985 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1288:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4) => (FMSB_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
82986 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSB_ZPmZZ_H),
82987 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
82988 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
82989 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
82990 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
82991 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
82992 GIR_RootConstrainSelectedInstOperands,
82993 // GIR_Coverage, 7901,
82994 GIR_EraseRootFromParent_Done,
82995 // Label 4676: @220039
82996 GIM_Try, /*On fail goto*//*Label 4677*/ GIMT_Encode4(220086), // Rule ID 7902 //
82997 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
82998 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmsb),
82999 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
83000 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
83001 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
83002 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
83003 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
83004 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83005 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1288:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4) => (FMSB_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
83006 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSB_ZPmZZ_S),
83007 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
83008 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83009 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83010 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83011 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83012 GIR_RootConstrainSelectedInstOperands,
83013 // GIR_Coverage, 7902,
83014 GIR_EraseRootFromParent_Done,
83015 // Label 4677: @220086
83016 GIM_Try, /*On fail goto*//*Label 4678*/ GIMT_Encode4(220133), // Rule ID 7903 //
83017 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83018 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmsb),
83019 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
83020 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
83021 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
83022 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
83023 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
83024 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83025 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1288:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4) => (FMSB_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
83026 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSB_ZPmZZ_D),
83027 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
83028 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83029 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83030 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83031 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83032 GIR_RootConstrainSelectedInstOperands,
83033 // GIR_Coverage, 7903,
83034 GIR_EraseRootFromParent_Done,
83035 // Label 4678: @220133
83036 GIM_Try, /*On fail goto*//*Label 4679*/ GIMT_Encode4(220180), // Rule ID 7904 //
83037 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83038 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmad),
83039 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
83040 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
83041 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
83042 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
83043 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
83044 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83045 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1295:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4) => (FNMAD_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
83046 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMAD_ZPmZZ_H),
83047 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
83048 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83049 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83050 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83051 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83052 GIR_RootConstrainSelectedInstOperands,
83053 // GIR_Coverage, 7904,
83054 GIR_EraseRootFromParent_Done,
83055 // Label 4679: @220180
83056 GIM_Try, /*On fail goto*//*Label 4680*/ GIMT_Encode4(220227), // Rule ID 7905 //
83057 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83058 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmad),
83059 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
83060 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
83061 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
83062 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
83063 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
83064 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83065 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1295:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4) => (FNMAD_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
83066 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMAD_ZPmZZ_S),
83067 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
83068 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83069 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83070 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83071 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83072 GIR_RootConstrainSelectedInstOperands,
83073 // GIR_Coverage, 7905,
83074 GIR_EraseRootFromParent_Done,
83075 // Label 4680: @220227
83076 GIM_Try, /*On fail goto*//*Label 4681*/ GIMT_Encode4(220274), // Rule ID 7906 //
83077 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83078 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmad),
83079 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
83080 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
83081 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
83082 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
83083 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
83084 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83085 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1295:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4) => (FNMAD_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
83086 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMAD_ZPmZZ_D),
83087 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
83088 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83089 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83090 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83091 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83092 GIR_RootConstrainSelectedInstOperands,
83093 // GIR_Coverage, 7906,
83094 GIR_EraseRootFromParent_Done,
83095 // Label 4681: @220274
83096 GIM_Try, /*On fail goto*//*Label 4682*/ GIMT_Encode4(220321), // Rule ID 7907 //
83097 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83098 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmsb),
83099 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
83100 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
83101 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
83102 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
83103 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
83104 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83105 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1300:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4) => (FNMSB_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
83106 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSB_ZPmZZ_H),
83107 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
83108 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83109 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83110 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83111 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83112 GIR_RootConstrainSelectedInstOperands,
83113 // GIR_Coverage, 7907,
83114 GIR_EraseRootFromParent_Done,
83115 // Label 4682: @220321
83116 GIM_Try, /*On fail goto*//*Label 4683*/ GIMT_Encode4(220368), // Rule ID 7908 //
83117 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83118 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmsb),
83119 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
83120 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
83121 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
83122 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
83123 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
83124 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83125 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1300:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4) => (FNMSB_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
83126 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSB_ZPmZZ_S),
83127 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
83128 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83129 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83130 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83131 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83132 GIR_RootConstrainSelectedInstOperands,
83133 // GIR_Coverage, 7908,
83134 GIR_EraseRootFromParent_Done,
83135 // Label 4683: @220368
83136 GIM_Try, /*On fail goto*//*Label 4684*/ GIMT_Encode4(220415), // Rule ID 7909 //
83137 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83138 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmsb),
83139 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
83140 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
83141 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
83142 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
83143 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
83144 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83145 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1300:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4) => (FNMSB_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
83146 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSB_ZPmZZ_D),
83147 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
83148 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83149 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83150 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83151 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83152 GIR_RootConstrainSelectedInstOperands,
83153 // GIR_Coverage, 7909,
83154 GIR_EraseRootFromParent_Done,
83155 // Label 4684: @220415
83156 GIM_Try, /*On fail goto*//*Label 4685*/ GIMT_Encode4(220462), // Rule ID 7910 //
83157 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83158 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_u),
83159 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
83160 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
83161 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
83162 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
83163 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
83164 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83165 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1282:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4) => (FMLS_ZPZZZ_H_UNDEF:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
83166 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPZZZ_H_UNDEF),
83167 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
83168 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83169 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83170 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83171 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83172 GIR_RootConstrainSelectedInstOperands,
83173 // GIR_Coverage, 7910,
83174 GIR_EraseRootFromParent_Done,
83175 // Label 4685: @220462
83176 GIM_Try, /*On fail goto*//*Label 4686*/ GIMT_Encode4(220509), // Rule ID 7913 //
83177 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83178 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_u),
83179 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
83180 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
83181 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
83182 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
83183 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
83184 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83185 // (intrinsic_wo_chain:{ *:[nxv4f16] } 1282:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4) => (FMLS_ZPZZZ_H_UNDEF:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
83186 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPZZZ_H_UNDEF),
83187 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
83188 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83189 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83190 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83191 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83192 GIR_RootConstrainSelectedInstOperands,
83193 // GIR_Coverage, 7913,
83194 GIR_EraseRootFromParent_Done,
83195 // Label 4686: @220509
83196 GIM_Try, /*On fail goto*//*Label 4687*/ GIMT_Encode4(220556), // Rule ID 7916 //
83197 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83198 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_u),
83199 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
83200 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
83201 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
83202 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
83203 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
83204 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83205 // (intrinsic_wo_chain:{ *:[nxv2f16] } 1282:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4) => (FMLS_ZPZZZ_H_UNDEF:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
83206 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPZZZ_H_UNDEF),
83207 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
83208 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83209 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83210 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83211 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83212 GIR_RootConstrainSelectedInstOperands,
83213 // GIR_Coverage, 7916,
83214 GIR_EraseRootFromParent_Done,
83215 // Label 4687: @220556
83216 GIM_Try, /*On fail goto*//*Label 4688*/ GIMT_Encode4(220603), // Rule ID 7919 //
83217 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83218 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_u),
83219 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
83220 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
83221 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
83222 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
83223 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
83224 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83225 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1282:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4) => (FMLS_ZPZZZ_S_UNDEF:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
83226 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPZZZ_S_UNDEF),
83227 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
83228 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83229 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83230 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83231 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83232 GIR_RootConstrainSelectedInstOperands,
83233 // GIR_Coverage, 7919,
83234 GIR_EraseRootFromParent_Done,
83235 // Label 4688: @220603
83236 GIM_Try, /*On fail goto*//*Label 4689*/ GIMT_Encode4(220650), // Rule ID 7922 //
83237 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83238 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_u),
83239 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
83240 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
83241 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
83242 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
83243 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
83244 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83245 // (intrinsic_wo_chain:{ *:[nxv2f32] } 1282:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4) => (FMLS_ZPZZZ_S_UNDEF:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
83246 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPZZZ_S_UNDEF),
83247 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
83248 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83249 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83250 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83251 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83252 GIR_RootConstrainSelectedInstOperands,
83253 // GIR_Coverage, 7922,
83254 GIR_EraseRootFromParent_Done,
83255 // Label 4689: @220650
83256 GIM_Try, /*On fail goto*//*Label 4690*/ GIMT_Encode4(220697), // Rule ID 7925 //
83257 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83258 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_u),
83259 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
83260 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
83261 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
83262 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
83263 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
83264 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83265 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1282:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4) => (FMLS_ZPZZZ_D_UNDEF:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
83266 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPZZZ_D_UNDEF),
83267 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
83268 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83269 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83270 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83271 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83272 GIR_RootConstrainSelectedInstOperands,
83273 // GIR_Coverage, 7925,
83274 GIR_EraseRootFromParent_Done,
83275 // Label 4690: @220697
83276 GIM_Try, /*On fail goto*//*Label 4691*/ GIMT_Encode4(220744), // Rule ID 7928 //
83277 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83278 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla_u),
83279 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
83280 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
83281 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
83282 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
83283 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
83284 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83285 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1297:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4) => (FNMLA_ZPZZZ_H_UNDEF:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
83286 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPZZZ_H_UNDEF),
83287 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
83288 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83289 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83290 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83291 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83292 GIR_RootConstrainSelectedInstOperands,
83293 // GIR_Coverage, 7928,
83294 GIR_EraseRootFromParent_Done,
83295 // Label 4691: @220744
83296 GIM_Try, /*On fail goto*//*Label 4692*/ GIMT_Encode4(220791), // Rule ID 7931 //
83297 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83298 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla_u),
83299 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
83300 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
83301 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
83302 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
83303 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
83304 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83305 // (intrinsic_wo_chain:{ *:[nxv4f16] } 1297:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4) => (FNMLA_ZPZZZ_H_UNDEF:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
83306 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPZZZ_H_UNDEF),
83307 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
83308 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83309 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83310 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83311 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83312 GIR_RootConstrainSelectedInstOperands,
83313 // GIR_Coverage, 7931,
83314 GIR_EraseRootFromParent_Done,
83315 // Label 4692: @220791
83316 GIM_Try, /*On fail goto*//*Label 4693*/ GIMT_Encode4(220838), // Rule ID 7934 //
83317 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83318 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla_u),
83319 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
83320 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
83321 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
83322 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
83323 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
83324 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83325 // (intrinsic_wo_chain:{ *:[nxv2f16] } 1297:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4) => (FNMLA_ZPZZZ_H_UNDEF:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
83326 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPZZZ_H_UNDEF),
83327 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
83328 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83329 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83330 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83331 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83332 GIR_RootConstrainSelectedInstOperands,
83333 // GIR_Coverage, 7934,
83334 GIR_EraseRootFromParent_Done,
83335 // Label 4693: @220838
83336 GIM_Try, /*On fail goto*//*Label 4694*/ GIMT_Encode4(220885), // Rule ID 7937 //
83337 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83338 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla_u),
83339 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
83340 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
83341 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
83342 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
83343 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
83344 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83345 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1297:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4) => (FNMLA_ZPZZZ_S_UNDEF:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
83346 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPZZZ_S_UNDEF),
83347 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
83348 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83349 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83350 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83351 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83352 GIR_RootConstrainSelectedInstOperands,
83353 // GIR_Coverage, 7937,
83354 GIR_EraseRootFromParent_Done,
83355 // Label 4694: @220885
83356 GIM_Try, /*On fail goto*//*Label 4695*/ GIMT_Encode4(220932), // Rule ID 7940 //
83357 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83358 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla_u),
83359 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
83360 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
83361 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
83362 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
83363 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
83364 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83365 // (intrinsic_wo_chain:{ *:[nxv2f32] } 1297:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4) => (FNMLA_ZPZZZ_S_UNDEF:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
83366 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPZZZ_S_UNDEF),
83367 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
83368 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83369 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83370 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83371 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83372 GIR_RootConstrainSelectedInstOperands,
83373 // GIR_Coverage, 7940,
83374 GIR_EraseRootFromParent_Done,
83375 // Label 4695: @220932
83376 GIM_Try, /*On fail goto*//*Label 4696*/ GIMT_Encode4(220979), // Rule ID 7943 //
83377 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83378 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla_u),
83379 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
83380 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
83381 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
83382 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
83383 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
83384 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83385 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1297:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4) => (FNMLA_ZPZZZ_D_UNDEF:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
83386 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPZZZ_D_UNDEF),
83387 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
83388 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83389 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83390 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83391 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83392 GIR_RootConstrainSelectedInstOperands,
83393 // GIR_Coverage, 7943,
83394 GIR_EraseRootFromParent_Done,
83395 // Label 4696: @220979
83396 GIM_Try, /*On fail goto*//*Label 4697*/ GIMT_Encode4(221026), // Rule ID 7946 //
83397 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83398 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls_u),
83399 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
83400 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
83401 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
83402 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
83403 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
83404 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83405 // (intrinsic_wo_chain:{ *:[nxv8f16] } 1299:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4) => (FNMLS_ZPZZZ_H_UNDEF:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
83406 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPZZZ_H_UNDEF),
83407 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
83408 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83409 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83410 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83411 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83412 GIR_RootConstrainSelectedInstOperands,
83413 // GIR_Coverage, 7946,
83414 GIR_EraseRootFromParent_Done,
83415 // Label 4697: @221026
83416 GIM_Try, /*On fail goto*//*Label 4698*/ GIMT_Encode4(221073), // Rule ID 7948 //
83417 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83418 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls_u),
83419 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
83420 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
83421 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
83422 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
83423 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
83424 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83425 // (intrinsic_wo_chain:{ *:[nxv4f16] } 1299:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4) => (FNMLS_ZPZZZ_H_UNDEF:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
83426 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPZZZ_H_UNDEF),
83427 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
83428 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83429 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83430 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83431 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83432 GIR_RootConstrainSelectedInstOperands,
83433 // GIR_Coverage, 7948,
83434 GIR_EraseRootFromParent_Done,
83435 // Label 4698: @221073
83436 GIM_Try, /*On fail goto*//*Label 4699*/ GIMT_Encode4(221120), // Rule ID 7950 //
83437 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83438 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls_u),
83439 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
83440 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
83441 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
83442 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
83443 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
83444 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83445 // (intrinsic_wo_chain:{ *:[nxv2f16] } 1299:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4) => (FNMLS_ZPZZZ_H_UNDEF:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
83446 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPZZZ_H_UNDEF),
83447 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
83448 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83449 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83450 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83451 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83452 GIR_RootConstrainSelectedInstOperands,
83453 // GIR_Coverage, 7950,
83454 GIR_EraseRootFromParent_Done,
83455 // Label 4699: @221120
83456 GIM_Try, /*On fail goto*//*Label 4700*/ GIMT_Encode4(221167), // Rule ID 7952 //
83457 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83458 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls_u),
83459 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
83460 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
83461 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
83462 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
83463 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
83464 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83465 // (intrinsic_wo_chain:{ *:[nxv4f32] } 1299:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4) => (FNMLS_ZPZZZ_S_UNDEF:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
83466 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPZZZ_S_UNDEF),
83467 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
83468 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83469 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83470 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83471 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83472 GIR_RootConstrainSelectedInstOperands,
83473 // GIR_Coverage, 7952,
83474 GIR_EraseRootFromParent_Done,
83475 // Label 4700: @221167
83476 GIM_Try, /*On fail goto*//*Label 4701*/ GIMT_Encode4(221214), // Rule ID 7954 //
83477 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83478 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls_u),
83479 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
83480 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
83481 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
83482 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
83483 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
83484 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83485 // (intrinsic_wo_chain:{ *:[nxv2f32] } 1299:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4) => (FNMLS_ZPZZZ_S_UNDEF:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
83486 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPZZZ_S_UNDEF),
83487 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
83488 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83489 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83490 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83491 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83492 GIR_RootConstrainSelectedInstOperands,
83493 // GIR_Coverage, 7954,
83494 GIR_EraseRootFromParent_Done,
83495 // Label 4701: @221214
83496 GIM_Try, /*On fail goto*//*Label 4702*/ GIMT_Encode4(221261), // Rule ID 7956 //
83497 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
83498 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls_u),
83499 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
83500 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
83501 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
83502 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
83503 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
83504 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83505 // (intrinsic_wo_chain:{ *:[nxv2f64] } 1299:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4) => (FNMLS_ZPZZZ_D_UNDEF:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
83506 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPZZZ_D_UNDEF),
83507 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
83508 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83509 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83510 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83511 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83512 GIR_RootConstrainSelectedInstOperands,
83513 // GIR_Coverage, 7956,
83514 GIR_EraseRootFromParent_Done,
83515 // Label 4702: @221261
83516 GIM_Try, /*On fail goto*//*Label 4703*/ GIMT_Encode4(221308), // Rule ID 11763 //
83517 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasB16B16_HasSVE2orSME2),
83518 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls),
83519 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
83520 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
83521 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
83522 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
83523 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
83524 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83525 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1280:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3, nxv8bf16:{ *:[nxv8bf16] }:$Op4) => (BFMLS_ZPmZZ:{ *:[nxv8bf16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3, ?:{ *:[nxv8bf16] }:$Op4)
83526 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMLS_ZPmZZ),
83527 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
83528 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83529 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83530 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83531 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83532 GIR_RootConstrainSelectedInstOperands,
83533 // GIR_Coverage, 11763,
83534 GIR_EraseRootFromParent_Done,
83535 // Label 4703: @221308
83536 GIM_Try, /*On fail goto*//*Label 4704*/ GIMT_Encode4(221355), // Rule ID 11766 //
83537 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasB16B16_HasSVE2orSME2),
83538 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_u),
83539 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
83540 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
83541 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
83542 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
83543 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
83544 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
83545 // (intrinsic_wo_chain:{ *:[nxv8bf16] } 1282:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3, nxv8bf16:{ *:[nxv8bf16] }:$Op4) => (BFMLS_ZPZZZ_UNDEF:{ *:[nxv8bf16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3, ?:{ *:[nxv8bf16] }:$Op4)
83546 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMLS_ZPZZZ_UNDEF),
83547 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
83548 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
83549 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
83550 GIR_RootToRootCopy, /*OpIdx*/4, // Op3
83551 GIR_RootToRootCopy, /*OpIdx*/5, // Op4
83552 GIR_RootConstrainSelectedInstOperands,
83553 // GIR_Coverage, 11766,
83554 GIR_EraseRootFromParent_Done,
83555 // Label 4704: @221355
83556 GIM_Reject,
83557 // Label 4553: @221356
83558 GIM_Reject,
83559 // Label 33: @221357
83560 GIM_Try, /*On fail goto*//*Label 4705*/ GIMT_Encode4(221435),
83561 GIM_CheckNumOperands, /*MI*/0, /*Expected*/1,
83562 GIM_Try, /*On fail goto*//*Label 4706*/ GIMT_Encode4(221387), // Rule ID 89 //
83563 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTME),
83564 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_tcommit),
83565 // (intrinsic_void 1947:{ *:[iPTR] }) => (TCOMMIT)
83566 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TCOMMIT),
83567 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
83568 GIR_RootConstrainSelectedInstOperands,
83569 // GIR_Coverage, 89,
83570 GIR_EraseRootFromParent_Done,
83571 // Label 4706: @221387
83572 GIM_Try, /*On fail goto*//*Label 4707*/ GIMT_Encode4(221412), // Rule ID 2326 //
83573 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
83574 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_setffr),
83575 // (intrinsic_void 1497:{ *:[iPTR] }) => (SETFFR:{ *:[i64] })
83576 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SETFFR),
83577 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::FFR*/0,
83578 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
83579 GIR_RootConstrainSelectedInstOperands,
83580 // GIR_Coverage, 2326,
83581 GIR_EraseRootFromParent_Done,
83582 // Label 4707: @221412
83583 GIM_Try, /*On fail goto*//*Label 4708*/ GIMT_Encode4(221434), // Rule ID 6852 //
83584 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_clrex),
83585 // (intrinsic_void 482:{ *:[iPTR] }) => (CLREX 15:{ *:[i64] })
83586 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLREX),
83587 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
83588 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
83589 GIR_RootConstrainSelectedInstOperands,
83590 // GIR_Coverage, 6852,
83591 GIR_EraseRootFromParent_Done,
83592 // Label 4708: @221434
83593 GIM_Reject,
83594 // Label 4705: @221435
83595 GIM_Try, /*On fail goto*//*Label 4709*/ GIMT_Encode4(222008),
83596 GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
83597 GIM_Try, /*On fail goto*//*Label 4710*/ GIMT_Encode4(221475), // Rule ID 90 //
83598 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTME),
83599 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_tcancel),
83600 // MIs[0] imm
83601 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
83602 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm64_0_65535),
83603 // (intrinsic_void 1946:{ *:[iPTR] }, (timm:{ *:[i64] })<<P:Predicate_timm64_0_65535>>:$imm) => (TCANCEL (timm:{ *:[i64] }):$imm)
83604 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TCANCEL),
83605 GIR_RootToRootCopy, /*OpIdx*/1, // imm
83606 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
83607 GIR_RootConstrainSelectedInstOperands,
83608 // GIR_Coverage, 90,
83609 GIR_EraseRootFromParent_Done,
83610 // Label 4710: @221475
83611 GIM_Try, /*On fail goto*//*Label 4711*/ GIMT_Encode4(221500), // Rule ID 237 //
83612 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_break),
83613 // MIs[0] imm
83614 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
83615 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_65535),
83616 // (intrinsic_void 480:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_65535>>:$imm) => (BRK (timm:{ *:[i32] }):$imm)
83617 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRK),
83618 GIR_RootToRootCopy, /*OpIdx*/1, // imm
83619 GIR_RootConstrainSelectedInstOperands,
83620 // GIR_Coverage, 237,
83621 GIR_EraseRootFromParent_Done,
83622 // Label 4711: @221500
83623 GIM_Try, /*On fail goto*//*Label 4712*/ GIMT_Encode4(221525), // Rule ID 238 //
83624 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_hlt),
83625 // MIs[0] imm
83626 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
83627 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_65535),
83628 // (intrinsic_void 539:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_65535>>:$imm) => (HLT (timm:{ *:[i32] }):$imm)
83629 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HLT),
83630 GIR_RootToRootCopy, /*OpIdx*/1, // imm
83631 GIR_RootConstrainSelectedInstOperands,
83632 // GIR_Coverage, 238,
83633 GIR_EraseRootFromParent_Done,
83634 // Label 4712: @221525
83635 GIM_Try, /*On fail goto*//*Label 4713*/ GIMT_Encode4(221557), // Rule ID 3520 //
83636 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEandIsNonStreamingSafe),
83637 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_zero),
83638 // MIs[0] imm
83639 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
83640 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_255),
83641 // (intrinsic_void 1038:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_255>>:$imm) => (ZERO_M_PSEUDO (timm:{ *:[i32] })<<P:Predicate_timm32_0_255>>:$imm)
83642 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZERO_M_PSEUDO),
83643 GIR_RootToRootCopy, /*OpIdx*/1, // imm
83644 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
83645 GIR_RootConstrainSelectedInstOperands,
83646 // GIR_Coverage, 3520,
83647 GIR_EraseRootFromParent_Done,
83648 // Label 4713: @221557
83649 GIM_Try, /*On fail goto*//*Label 4714*/ GIMT_Encode4(221597), // Rule ID 16 //
83650 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_hint),
83651 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
83652 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
83653 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
83654 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_127),
83655 // MIs[1] Operand 1
83656 // No operand predicates
83657 GIM_CheckIsSafeToFold, /*NumInsns*/1,
83658 // (intrinsic_void 538:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_127>>:$imm) => (HINT (imm:{ *:[i32] }):$imm)
83659 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HINT),
83660 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
83661 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
83662 GIR_RootConstrainSelectedInstOperands,
83663 // GIR_Coverage, 16,
83664 GIR_EraseRootFromParent_Done,
83665 // Label 4714: @221597
83666 GIM_Try, /*On fail goto*//*Label 4715*/ GIMT_Encode4(221637), // Rule ID 17 //
83667 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_dmb),
83668 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
83669 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
83670 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
83671 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32_0_15),
83672 // MIs[1] Operand 1
83673 // No operand predicates
83674 GIM_CheckIsSafeToFold, /*NumInsns*/1,
83675 // (intrinsic_void 526:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm) => (DMB (imm:{ *:[i32] }):$CRm)
83676 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DMB),
83677 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm
83678 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
83679 GIR_RootConstrainSelectedInstOperands,
83680 // GIR_Coverage, 17,
83681 GIR_EraseRootFromParent_Done,
83682 // Label 4715: @221637
83683 GIM_Try, /*On fail goto*//*Label 4716*/ GIMT_Encode4(221677), // Rule ID 18 //
83684 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_dsb),
83685 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
83686 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
83687 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
83688 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32_0_15),
83689 // MIs[1] Operand 1
83690 // No operand predicates
83691 GIM_CheckIsSafeToFold, /*NumInsns*/1,
83692 // (intrinsic_void 527:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm) => (DSB (imm:{ *:[i32] }):$CRm)
83693 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DSB),
83694 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm
83695 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
83696 GIR_RootConstrainSelectedInstOperands,
83697 // GIR_Coverage, 18,
83698 GIR_EraseRootFromParent_Done,
83699 // Label 4716: @221677
83700 GIM_Try, /*On fail goto*//*Label 4717*/ GIMT_Encode4(221717), // Rule ID 19 //
83701 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_isb),
83702 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
83703 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
83704 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
83705 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32_0_15),
83706 // MIs[1] Operand 1
83707 // No operand predicates
83708 GIM_CheckIsSafeToFold, /*NumInsns*/1,
83709 // (intrinsic_void 542:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm) => (ISB (imm:{ *:[i32] }):$CRm)
83710 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ISB),
83711 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm
83712 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
83713 GIR_RootConstrainSelectedInstOperands,
83714 // GIR_Coverage, 19,
83715 GIR_EraseRootFromParent_Done,
83716 // Label 4717: @221717
83717 GIM_Try, /*On fail goto*//*Label 4718*/ GIMT_Encode4(221741), // Rule ID 84 //
83718 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_get_fpcr),
83719 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
83720 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
83721 // (intrinsic_w_chain:{ *:[i64] } 535:{ *:[iPTR] }) => (MRS_FPCR:{ *:[i64] })
83722 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MRS_FPCR),
83723 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
83724 GIR_RootConstrainSelectedInstOperands,
83725 // GIR_Coverage, 84,
83726 GIR_EraseRootFromParent_Done,
83727 // Label 4718: @221741
83728 GIM_Try, /*On fail goto*//*Label 4719*/ GIMT_Encode4(221765), // Rule ID 86 //
83729 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_get_fpsr),
83730 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
83731 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
83732 // (intrinsic_w_chain:{ *:[i64] } 536:{ *:[iPTR] }) => (MRS_FPSR:{ *:[i64] })
83733 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MRS_FPSR),
83734 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
83735 GIR_RootConstrainSelectedInstOperands,
83736 // GIR_Coverage, 86,
83737 GIR_EraseRootFromParent_Done,
83738 // Label 4719: @221765
83739 GIM_Try, /*On fail goto*//*Label 4720*/ GIMT_Encode4(221796), // Rule ID 88 //
83740 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTME),
83741 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_tstart),
83742 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
83743 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
83744 // (intrinsic_w_chain:{ *:[i64] } 1948:{ *:[iPTR] }) => (TSTART:{ *:[i64] })
83745 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TSTART),
83746 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
83747 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
83748 GIR_RootConstrainSelectedInstOperands,
83749 // GIR_Coverage, 88,
83750 GIR_EraseRootFromParent_Done,
83751 // Label 4720: @221796
83752 GIM_Try, /*On fail goto*//*Label 4721*/ GIMT_Encode4(221823), // Rule ID 91 //
83753 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTME),
83754 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ttest),
83755 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
83756 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
83757 // (intrinsic_w_chain:{ *:[i64] } 1949:{ *:[iPTR] }) => (TTEST:{ *:[i64] })
83758 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TTEST),
83759 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
83760 GIR_RootConstrainSelectedInstOperands,
83761 // GIR_Coverage, 91,
83762 GIR_EraseRootFromParent_Done,
83763 // Label 4721: @221823
83764 GIM_Try, /*On fail goto*//*Label 4722*/ GIMT_Encode4(221854), // Rule ID 2325 //
83765 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
83766 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rdffr),
83767 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
83768 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
83769 // (intrinsic_w_chain:{ *:[nxv16i1] } 1447:{ *:[iPTR] }) => (RDFFR_P:{ *:[nxv16i1] })
83770 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RDFFR_P),
83771 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
83772 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
83773 GIR_RootConstrainSelectedInstOperands,
83774 // GIR_Coverage, 2325,
83775 GIR_EraseRootFromParent_Done,
83776 // Label 4722: @221854
83777 GIM_Try, /*On fail goto*//*Label 4723*/ GIMT_Encode4(221894), // Rule ID 12015 //
83778 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEandIsNonStreamingSafe),
83779 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sme_get_tpidr2),
83780 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
83781 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
83782 // (intrinsic_w_chain:{ *:[i64] } 795:{ *:[iPTR] }) => (MRS:{ *:[i64] }:{ *:[i32] } 56965:{ *:[i32] })
83783 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MRS),
83784 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
83785 GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(56965),
83786 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
83787 GIR_RootConstrainSelectedInstOperands,
83788 // GIR_Coverage, 12015,
83789 GIR_EraseRootFromParent_Done,
83790 // Label 4723: @221894
83791 GIM_Try, /*On fail goto*//*Label 4724*/ GIMT_Encode4(221928), // Rule ID 2327 //
83792 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
83793 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_wrffr),
83794 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
83795 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
83796 // (intrinsic_void 1927:{ *:[iPTR] }, PPR8:{ *:[nxv16i1] }:$Pn) => (WRFFR:{ *:[i64] } PPR8:{ *:[nxv16i1] }:$Pn)
83797 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WRFFR),
83798 GIR_RootToRootCopy, /*OpIdx*/1, // Pn
83799 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::FFR*/0,
83800 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
83801 GIR_RootConstrainSelectedInstOperands,
83802 // GIR_Coverage, 2327,
83803 GIR_EraseRootFromParent_Done,
83804 // Label 4724: @221928
83805 GIM_Try, /*On fail goto*//*Label 4725*/ GIMT_Encode4(221951), // Rule ID 85 //
83806 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_set_fpcr),
83807 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
83808 // (intrinsic_void 736:{ *:[iPTR] }, i64:{ *:[i64] }:$val) => (MSR_FPCR i64:{ *:[i64] }:$val)
83809 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSR_FPCR),
83810 GIR_RootToRootCopy, /*OpIdx*/1, // val
83811 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::FPCR*/0,
83812 GIR_RootConstrainSelectedInstOperands,
83813 // GIR_Coverage, 85,
83814 GIR_EraseRootFromParent_Done,
83815 // Label 4725: @221951
83816 GIM_Try, /*On fail goto*//*Label 4726*/ GIMT_Encode4(221974), // Rule ID 87 //
83817 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_set_fpsr),
83818 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
83819 // (intrinsic_void 737:{ *:[iPTR] }, i64:{ *:[i64] }:$val) => (MSR_FPSR i64:{ *:[i64] }:$val)
83820 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSR_FPSR),
83821 GIR_RootToRootCopy, /*OpIdx*/1, // val
83822 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::FPSR*/0,
83823 GIR_RootConstrainSelectedInstOperands,
83824 // GIR_Coverage, 87,
83825 GIR_EraseRootFromParent_Done,
83826 // Label 4726: @221974
83827 GIM_Try, /*On fail goto*//*Label 4727*/ GIMT_Encode4(222007), // Rule ID 12014 //
83828 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEandIsNonStreamingSafe),
83829 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_set_tpidr2),
83830 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
83831 // (intrinsic_void 852:{ *:[iPTR] }, i64:{ *:[i64] }:$val) => (MSR 56965:{ *:[i32] }, GPR64:{ *:[i64] }:$val)
83832 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSR),
83833 GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(56965),
83834 GIR_RootToRootCopy, /*OpIdx*/1, // val
83835 GIR_RootConstrainSelectedInstOperands,
83836 // GIR_Coverage, 12014,
83837 GIR_EraseRootFromParent_Done,
83838 // Label 4727: @222007
83839 GIM_Reject,
83840 // Label 4709: @222008
83841 GIM_Try, /*On fail goto*//*Label 4728*/ GIMT_Encode4(222675),
83842 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
83843 GIM_Try, /*On fail goto*//*Label 4729*/ GIMT_Encode4(222092), // Rule ID 6818 //
83844 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
83845 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
83846 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
83847 // MIs[0] addr
83848 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
83849 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
83850 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_1),
83851 // (intrinsic_w_chain:{ *:[i64] } 548:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
83852 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
83853 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDXRB),
83854 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
83855 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr
83856 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
83857 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
83858 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
83859 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
83860 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
83861 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
83862 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
83863 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
83864 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
83865 // GIR_Coverage, 6818,
83866 GIR_EraseRootFromParent_Done,
83867 // Label 4729: @222092
83868 GIM_Try, /*On fail goto*//*Label 4730*/ GIMT_Encode4(222168), // Rule ID 6819 //
83869 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
83870 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
83871 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
83872 // MIs[0] addr
83873 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
83874 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
83875 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_2),
83876 // (intrinsic_w_chain:{ *:[i64] } 548:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_2>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
83877 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
83878 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDXRH),
83879 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
83880 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr
83881 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
83882 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
83883 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
83884 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
83885 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
83886 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
83887 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
83888 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
83889 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
83890 // GIR_Coverage, 6819,
83891 GIR_EraseRootFromParent_Done,
83892 // Label 4730: @222168
83893 GIM_Try, /*On fail goto*//*Label 4731*/ GIMT_Encode4(222244), // Rule ID 6820 //
83894 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
83895 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
83896 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
83897 // MIs[0] addr
83898 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
83899 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
83900 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_4),
83901 // (intrinsic_w_chain:{ *:[i64] } 548:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_4>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
83902 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
83903 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDXRW),
83904 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
83905 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr
83906 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
83907 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
83908 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
83909 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
83910 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
83911 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
83912 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
83913 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
83914 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
83915 // GIR_Coverage, 6820,
83916 GIR_EraseRootFromParent_Done,
83917 // Label 4731: @222244
83918 GIM_Try, /*On fail goto*//*Label 4732*/ GIMT_Encode4(222286), // Rule ID 6821 //
83919 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
83920 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
83921 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
83922 // MIs[0] addr
83923 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
83924 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
83925 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_8),
83926 // (intrinsic_w_chain:{ *:[i64] } 548:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_8>> => (LDXRX:{ *:[i64] } GPR64sp:{ *:[i64] }:$addr)
83927 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDXRX),
83928 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
83929 GIR_RootToRootCopy, /*OpIdx*/2, // addr
83930 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
83931 GIR_RootConstrainSelectedInstOperands,
83932 // GIR_Coverage, 6821,
83933 GIR_EraseRootFromParent_Done,
83934 // Label 4732: @222286
83935 GIM_Try, /*On fail goto*//*Label 4733*/ GIMT_Encode4(222362), // Rule ID 6825 //
83936 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
83937 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
83938 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
83939 // MIs[0] addr
83940 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
83941 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
83942 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_1),
83943 // (intrinsic_w_chain:{ *:[i64] } 545:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_1>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
83944 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
83945 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDAXRB),
83946 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
83947 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr
83948 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
83949 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
83950 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
83951 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
83952 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
83953 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
83954 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
83955 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
83956 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
83957 // GIR_Coverage, 6825,
83958 GIR_EraseRootFromParent_Done,
83959 // Label 4733: @222362
83960 GIM_Try, /*On fail goto*//*Label 4734*/ GIMT_Encode4(222438), // Rule ID 6826 //
83961 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
83962 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
83963 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
83964 // MIs[0] addr
83965 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
83966 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
83967 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_2),
83968 // (intrinsic_w_chain:{ *:[i64] } 545:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_2>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
83969 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
83970 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDAXRH),
83971 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
83972 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr
83973 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
83974 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
83975 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
83976 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
83977 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
83978 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
83979 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
83980 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
83981 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
83982 // GIR_Coverage, 6826,
83983 GIR_EraseRootFromParent_Done,
83984 // Label 4734: @222438
83985 GIM_Try, /*On fail goto*//*Label 4735*/ GIMT_Encode4(222514), // Rule ID 6827 //
83986 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
83987 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
83988 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
83989 // MIs[0] addr
83990 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
83991 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
83992 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_4),
83993 // (intrinsic_w_chain:{ *:[i64] } 545:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_4>> => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
83994 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
83995 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDAXRW),
83996 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
83997 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr
83998 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
83999 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
84000 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
84001 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
84002 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
84003 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
84004 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
84005 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
84006 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
84007 // GIR_Coverage, 6827,
84008 GIR_EraseRootFromParent_Done,
84009 // Label 4735: @222514
84010 GIM_Try, /*On fail goto*//*Label 4736*/ GIMT_Encode4(222556), // Rule ID 6828 //
84011 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
84012 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
84013 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84014 // MIs[0] addr
84015 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
84016 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84017 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_8),
84018 // (intrinsic_w_chain:{ *:[i64] } 545:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_8>> => (LDAXRX:{ *:[i64] } GPR64sp:{ *:[i64] }:$addr)
84019 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAXRX),
84020 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
84021 GIR_RootToRootCopy, /*OpIdx*/2, // addr
84022 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84023 GIR_RootConstrainSelectedInstOperands,
84024 // GIR_Coverage, 6828,
84025 GIR_EraseRootFromParent_Done,
84026 // Label 4736: @222556
84027 GIM_Try, /*On fail goto*//*Label 4737*/ GIMT_Encode4(222596), // Rule ID 20 //
84028 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGCS),
84029 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_gcspopm),
84030 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
84031 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84032 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84033 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84034 // (intrinsic_w_chain:{ *:[i64] } 533:{ *:[iPTR] }, GPR64:{ *:[i64] }:$src) => (GCSPOPM:{ *:[i64] } GPR64:{ *:[i64] }:$src)
84035 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::GCSPOPM),
84036 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
84037 GIR_RootToRootCopy, /*OpIdx*/2, // src
84038 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84039 GIR_RootConstrainSelectedInstOperands,
84040 // GIR_Coverage, 20,
84041 GIR_EraseRootFromParent_Done,
84042 // Label 4737: @222596
84043 GIM_Try, /*On fail goto*//*Label 4738*/ GIMT_Encode4(222636), // Rule ID 2324 //
84044 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
84045 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rdffr_z),
84046 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
84047 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
84048 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
84049 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
84050 // (intrinsic_w_chain:{ *:[nxv16i1] } 1448:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$Pg) => (RDFFR_PPz:{ *:[nxv16i1] } PPRAny:{ *:[nxv16i1] }:$Pg)
84051 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RDFFR_PPz),
84052 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
84053 GIR_RootToRootCopy, /*OpIdx*/2, // Pg
84054 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84055 GIR_RootConstrainSelectedInstOperands,
84056 // GIR_Coverage, 2324,
84057 GIR_EraseRootFromParent_Done,
84058 // Label 4738: @222636
84059 GIM_Try, /*On fail goto*//*Label 4739*/ GIMT_Encode4(222674), // Rule ID 3870 //
84060 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMTE),
84061 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_irg_sp),
84062 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
84063 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84064 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84065 // (intrinsic_w_chain:{ *:[i64] } 541:{ *:[iPTR] }, i64:{ *:[i64] }:$Rm) => (IRGstack:{ *:[i64] } SP:{ *:[i64] }, i64:{ *:[i64] }:$Rm)
84066 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::IRGstack),
84067 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
84068 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::SP), /*AddRegisterRegFlags*/GIMT_Encode2(0),
84069 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
84070 GIR_RootConstrainSelectedInstOperands,
84071 // GIR_Coverage, 3870,
84072 GIR_EraseRootFromParent_Done,
84073 // Label 4739: @222674
84074 GIM_Reject,
84075 // Label 4728: @222675
84076 GIM_Try, /*On fail goto*//*Label 4740*/ GIMT_Encode4(225436),
84077 GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
84078 GIM_Try, /*On fail goto*//*Label 4741*/ GIMT_Encode4(222780), // Rule ID 6836 //
84079 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
84080 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84081 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84082 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84083 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
84084 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
84085 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
84086 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
84087 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
84088 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
84089 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
84090 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84091 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(255),
84092 // MIs[0] addr
84093 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84094 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84095 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_1),
84096 GIM_CheckIsSafeToFold, /*NumInsns*/2,
84097 // (intrinsic_w_chain:{ *:[i32] } 1057:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 255:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_1>> => (STXRB:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr)
84098 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRB),
84099 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val
84101 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84102 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
84103 GIR_RootConstrainSelectedInstOperands,
84104 // GIR_Coverage, 6836,
84105 GIR_EraseRootFromParent_Done,
84106 // Label 4741: @222780
84107 GIM_Try, /*On fail goto*//*Label 4742*/ GIMT_Encode4(222877), // Rule ID 6837 //
84108 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
84109 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84110 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84111 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84112 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
84113 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
84114 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
84115 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
84116 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
84117 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
84118 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
84119 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84120 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
84121 // MIs[0] addr
84122 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84123 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84124 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_2),
84125 GIM_CheckIsSafeToFold, /*NumInsns*/2,
84126 // (intrinsic_w_chain:{ *:[i32] } 1057:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 65535:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_2>> => (STXRH:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr)
84127 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRH),
84128 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84129 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val
84130 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84131 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
84132 GIR_RootConstrainSelectedInstOperands,
84133 // GIR_Coverage, 6837,
84134 GIR_EraseRootFromParent_Done,
84135 // Label 4742: @222877
84136 GIM_Try, /*On fail goto*//*Label 4743*/ GIMT_Encode4(222974), // Rule ID 6846 //
84137 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
84138 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84139 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84140 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84141 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
84142 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
84143 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
84144 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
84145 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
84146 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
84147 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
84148 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84149 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(255),
84150 // MIs[0] addr
84151 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84152 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84153 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_1),
84154 GIM_CheckIsSafeToFold, /*NumInsns*/2,
84155 // (intrinsic_w_chain:{ *:[i32] } 1055:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 255:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_1>> => (STLXRB:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr)
84156 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRB),
84157 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84158 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val
84159 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84160 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
84161 GIR_RootConstrainSelectedInstOperands,
84162 // GIR_Coverage, 6846,
84163 GIR_EraseRootFromParent_Done,
84164 // Label 4743: @222974
84165 GIM_Try, /*On fail goto*//*Label 4744*/ GIMT_Encode4(223071), // Rule ID 6847 //
84166 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
84167 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84168 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84169 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84170 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
84171 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
84172 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
84173 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
84174 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
84175 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
84176 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
84177 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84178 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
84179 // MIs[0] addr
84180 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84181 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84182 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_2),
84183 GIM_CheckIsSafeToFold, /*NumInsns*/2,
84184 // (intrinsic_w_chain:{ *:[i32] } 1055:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 65535:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_2>> => (STLXRH:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr)
84185 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRH),
84186 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val
84188 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84189 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
84190 GIR_RootConstrainSelectedInstOperands,
84191 // GIR_Coverage, 6847,
84192 GIR_EraseRootFromParent_Done,
84193 // Label 4744: @223071
84194 GIM_Try, /*On fail goto*//*Label 4745*/ GIMT_Encode4(223182), // Rule ID 6839 //
84195 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
84196 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84197 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84198 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84199 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
84200 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
84201 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
84202 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
84203 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84204 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
84205 // MIs[0] addr
84206 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84207 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84208 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_1),
84209 GIM_CheckIsSafeToFold, /*NumInsns*/1,
84210 // (intrinsic_w_chain:{ *:[i32] } 1057:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 255:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_1>> => (STXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
84211 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
84212 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
84213 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
84214 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(16), // val
84215 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
84216 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
84217 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRB),
84218 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84219 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
84220 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84221 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
84222 GIR_RootConstrainSelectedInstOperands,
84223 // GIR_Coverage, 6839,
84224 GIR_EraseRootFromParent_Done,
84225 // Label 4745: @223182
84226 GIM_Try, /*On fail goto*//*Label 4746*/ GIMT_Encode4(223293), // Rule ID 6840 //
84227 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
84228 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84229 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84230 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84231 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
84232 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
84233 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
84234 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
84235 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84236 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
84237 // MIs[0] addr
84238 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84239 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84240 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_2),
84241 GIM_CheckIsSafeToFold, /*NumInsns*/1,
84242 // (intrinsic_w_chain:{ *:[i32] } 1057:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 65535:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_2>> => (STXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
84243 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
84244 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
84245 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
84246 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(16), // val
84247 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
84248 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
84249 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRH),
84250 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84251 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
84252 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84253 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
84254 GIR_RootConstrainSelectedInstOperands,
84255 // GIR_Coverage, 6840,
84256 GIR_EraseRootFromParent_Done,
84257 // Label 4746: @223293
84258 GIM_Try, /*On fail goto*//*Label 4747*/ GIMT_Encode4(223404), // Rule ID 6841 //
84259 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
84260 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84261 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84262 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84263 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
84264 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
84265 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
84266 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
84267 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84268 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967295),
84269 // MIs[0] addr
84270 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84271 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84272 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_4),
84273 GIM_CheckIsSafeToFold, /*NumInsns*/1,
84274 // (intrinsic_w_chain:{ *:[i32] } 1057:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 4294967295:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_4>> => (STXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
84275 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
84276 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
84277 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
84278 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(16), // val
84279 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
84280 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
84281 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRW),
84282 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84283 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
84284 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84285 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
84286 GIR_RootConstrainSelectedInstOperands,
84287 // GIR_Coverage, 6841,
84288 GIR_EraseRootFromParent_Done,
84289 // Label 4747: @223404
84290 GIM_Try, /*On fail goto*//*Label 4748*/ GIMT_Encode4(223515), // Rule ID 6849 //
84291 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
84292 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84293 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84294 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84295 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
84296 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
84297 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
84298 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
84299 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84300 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
84301 // MIs[0] addr
84302 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84303 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84304 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_1),
84305 GIM_CheckIsSafeToFold, /*NumInsns*/1,
84306 // (intrinsic_w_chain:{ *:[i32] } 1055:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 255:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_1>> => (STLXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
84307 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
84308 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
84309 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
84310 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(16), // val
84311 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
84312 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
84313 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRB),
84314 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84315 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
84316 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84317 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
84318 GIR_RootConstrainSelectedInstOperands,
84319 // GIR_Coverage, 6849,
84320 GIR_EraseRootFromParent_Done,
84321 // Label 4748: @223515
84322 GIM_Try, /*On fail goto*//*Label 4749*/ GIMT_Encode4(223626), // Rule ID 6850 //
84323 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
84324 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84325 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84326 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84327 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
84328 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
84329 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
84330 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
84331 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84332 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
84333 // MIs[0] addr
84334 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84335 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84336 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_2),
84337 GIM_CheckIsSafeToFold, /*NumInsns*/1,
84338 // (intrinsic_w_chain:{ *:[i32] } 1055:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 65535:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_2>> => (STLXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
84339 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
84340 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
84341 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
84342 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(16), // val
84343 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
84344 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
84345 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRH),
84346 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84347 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
84348 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84349 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
84350 GIR_RootConstrainSelectedInstOperands,
84351 // GIR_Coverage, 6850,
84352 GIR_EraseRootFromParent_Done,
84353 // Label 4749: @223626
84354 GIM_Try, /*On fail goto*//*Label 4750*/ GIMT_Encode4(223737), // Rule ID 6851 //
84355 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
84356 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84357 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84358 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84359 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
84360 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
84361 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
84362 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
84363 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84364 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967295),
84365 // MIs[0] addr
84366 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84367 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84368 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_4),
84369 GIM_CheckIsSafeToFold, /*NumInsns*/1,
84370 // (intrinsic_w_chain:{ *:[i32] } 1055:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 4294967295:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_4>> => (STLXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
84371 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
84372 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
84373 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
84374 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(16), // val
84375 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
84376 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
84377 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRW),
84378 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84379 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
84380 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84381 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
84382 GIR_RootConstrainSelectedInstOperands,
84383 // GIR_Coverage, 6851,
84384 GIR_EraseRootFromParent_Done,
84385 // Label 4750: @223737
84386 GIM_Try, /*On fail goto*//*Label 4751*/ GIMT_Encode4(223788), // Rule ID 82 //
84387 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::hwasan_check_memaccess_fixedshadow),
84388 // MIs[0] ptr
84389 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
84390 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64noipRegClassID),
84391 // MIs[0] accessinfo
84392 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
84393 // MIs[0] fixed_shadow
84394 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
84395 // (intrinsic_void 185:{ *:[iPTR] }, GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo, (timm:{ *:[i64] }):$fixed_shadow) => (HWASAN_CHECK_MEMACCESS_FIXEDSHADOW:{ *:[i64] } GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo, (timm:{ *:[i64] }):$fixed_shadow)
84396 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HWASAN_CHECK_MEMACCESS_FIXEDSHADOW),
84397 GIR_RootToRootCopy, /*OpIdx*/1, // ptr
84398 GIR_RootToRootCopy, /*OpIdx*/2, // accessinfo
84399 GIR_RootToRootCopy, /*OpIdx*/3, // fixed_shadow
84400 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X16*/0,
84401 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X17*/1,
84402 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::LR*/2,
84403 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/3,
84404 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84405 GIR_RootConstrainSelectedInstOperands,
84406 // GIR_Coverage, 82,
84407 GIR_EraseRootFromParent_Done,
84408 // Label 4751: @223788
84409 GIM_Try, /*On fail goto*//*Label 4752*/ GIMT_Encode4(223839), // Rule ID 83 //
84410 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::hwasan_check_memaccess_shortgranules_fixedshadow),
84411 // MIs[0] ptr
84412 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
84413 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64noipRegClassID),
84414 // MIs[0] accessinfo
84415 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
84416 // MIs[0] fixed_shadow
84417 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
84418 // (intrinsic_void 187:{ *:[iPTR] }, GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo, (timm:{ *:[i64] }):$fixed_shadow) => (HWASAN_CHECK_MEMACCESS_SHORTGRANULES_FIXEDSHADOW:{ *:[i64] } GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo, (timm:{ *:[i64] }):$fixed_shadow)
84419 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES_FIXEDSHADOW),
84420 GIR_RootToRootCopy, /*OpIdx*/1, // ptr
84421 GIR_RootToRootCopy, /*OpIdx*/2, // accessinfo
84422 GIR_RootToRootCopy, /*OpIdx*/3, // fixed_shadow
84423 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X16*/0,
84424 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X17*/1,
84425 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::LR*/2,
84426 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/3,
84427 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84428 GIR_RootConstrainSelectedInstOperands,
84429 // GIR_Coverage, 83,
84430 GIR_EraseRootFromParent_Done,
84431 // Label 4752: @223839
84432 GIM_Try, /*On fail goto*//*Label 4753*/ GIMT_Encode4(223908), // Rule ID 6838 //
84433 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
84434 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84435 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84436 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84437 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
84438 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
84439 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
84440 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84441 // MIs[0] addr
84442 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84443 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84444 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_4),
84445 GIM_CheckIsSafeToFold, /*NumInsns*/1,
84446 // (intrinsic_w_chain:{ *:[i32] } 1057:{ *:[iPTR] }, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$val), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_4>> => (STXRW:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr)
84447 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRW),
84448 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84449 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
84450 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84451 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
84452 GIR_RootConstrainSelectedInstOperands,
84453 // GIR_Coverage, 6838,
84454 GIR_EraseRootFromParent_Done,
84455 // Label 4753: @223908
84456 GIM_Try, /*On fail goto*//*Label 4754*/ GIMT_Encode4(223977), // Rule ID 6848 //
84457 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
84458 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84459 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84460 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84461 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
84462 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
84463 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
84464 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84465 // MIs[0] addr
84466 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84467 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84468 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_4),
84469 GIM_CheckIsSafeToFold, /*NumInsns*/1,
84470 // (intrinsic_w_chain:{ *:[i32] } 1055:{ *:[iPTR] }, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$val), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_4>> => (STLXRW:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr)
84471 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRW),
84472 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
84474 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84475 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
84476 GIR_RootConstrainSelectedInstOperands,
84477 // GIR_Coverage, 6848,
84478 GIR_EraseRootFromParent_Done,
84479 // Label 4754: @223977
84480 GIM_Try, /*On fail goto*//*Label 4755*/ GIMT_Encode4(224031), // Rule ID 8525 //
84481 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
84482 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prf),
84483 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
84484 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
84485 // MIs[0] base
84486 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
84487 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84488 // MIs[0] prfop
84489 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
84490 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
84491 // (intrinsic_void 1415:{ *:[iPTR] }, PPR_3b:{ *:[nxv16i1] }:$gp, GPR64:{ *:[i64] }:$base, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFB_PRI (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR_3b:{ *:[nxv16i1] }:$gp, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
84492 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_PRI),
84493 GIR_RootToRootCopy, /*OpIdx*/3, // prfop
84494 GIR_RootToRootCopy, /*OpIdx*/1, // gp
84495 GIR_RootToRootCopy, /*OpIdx*/2, // base
84496 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
84497 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84498 GIR_RootConstrainSelectedInstOperands,
84499 // GIR_Coverage, 8525,
84500 GIR_EraseRootFromParent_Done,
84501 // Label 4755: @224031
84502 GIM_Try, /*On fail goto*//*Label 4756*/ GIMT_Encode4(224085), // Rule ID 8528 //
84503 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
84504 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prf),
84505 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
84506 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
84507 // MIs[0] base
84508 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
84509 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84510 // MIs[0] prfop
84511 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
84512 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
84513 // (intrinsic_void 1415:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$gp, GPR64:{ *:[i64] }:$base, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFH_PRI (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR_3b:{ *:[nxv8i1] }:$gp, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
84514 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFH_PRI),
84515 GIR_RootToRootCopy, /*OpIdx*/3, // prfop
84516 GIR_RootToRootCopy, /*OpIdx*/1, // gp
84517 GIR_RootToRootCopy, /*OpIdx*/2, // base
84518 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
84519 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84520 GIR_RootConstrainSelectedInstOperands,
84521 // GIR_Coverage, 8528,
84522 GIR_EraseRootFromParent_Done,
84523 // Label 4756: @224085
84524 GIM_Try, /*On fail goto*//*Label 4757*/ GIMT_Encode4(224139), // Rule ID 8531 //
84525 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
84526 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prf),
84527 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
84528 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
84529 // MIs[0] base
84530 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
84531 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84532 // MIs[0] prfop
84533 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
84534 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
84535 // (intrinsic_void 1415:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$gp, GPR64:{ *:[i64] }:$base, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFW_PRI (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR_3b:{ *:[nxv4i1] }:$gp, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
84536 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFW_PRI),
84537 GIR_RootToRootCopy, /*OpIdx*/3, // prfop
84538 GIR_RootToRootCopy, /*OpIdx*/1, // gp
84539 GIR_RootToRootCopy, /*OpIdx*/2, // base
84540 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
84541 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84542 GIR_RootConstrainSelectedInstOperands,
84543 // GIR_Coverage, 8531,
84544 GIR_EraseRootFromParent_Done,
84545 // Label 4757: @224139
84546 GIM_Try, /*On fail goto*//*Label 4758*/ GIMT_Encode4(224193), // Rule ID 8534 //
84547 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
84548 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prf),
84549 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
84550 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
84551 // MIs[0] base
84552 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
84553 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84554 // MIs[0] prfop
84555 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
84556 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
84557 // (intrinsic_void 1415:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$gp, GPR64:{ *:[i64] }:$base, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFD_PRI (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR_3b:{ *:[nxv2i1] }:$gp, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
84558 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFD_PRI),
84559 GIR_RootToRootCopy, /*OpIdx*/3, // prfop
84560 GIR_RootToRootCopy, /*OpIdx*/1, // gp
84561 GIR_RootToRootCopy, /*OpIdx*/2, // base
84562 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
84563 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84564 GIR_RootConstrainSelectedInstOperands,
84565 // GIR_Coverage, 8534,
84566 GIR_EraseRootFromParent_Done,
84567 // Label 4758: @224193
84568 GIM_Try, /*On fail goto*//*Label 4759*/ GIMT_Encode4(224247), // Rule ID 15 //
84569 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_space),
84570 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
84571 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
84572 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
84573 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84574 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
84575 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
84576 // MIs[1] Operand 1
84577 // No operand predicates
84578 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84579 GIM_CheckIsSafeToFold, /*NumInsns*/1,
84580 // (intrinsic_w_chain:{ *:[i64] } 1048:{ *:[iPTR] }, (imm:{ *:[i32] }):$size, GPR64:{ *:[i64] }:$Rn) => (SPACE:{ *:[i64] } (imm:{ *:[i32] }):$size, GPR64:{ *:[i64] }:$Rn)
84581 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SPACE),
84582 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
84583 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // size
84584 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
84585 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
84586 GIR_RootConstrainSelectedInstOperands,
84587 // GIR_Coverage, 15,
84588 GIR_EraseRootFromParent_Done,
84589 // Label 4759: @224247
84590 GIM_Try, /*On fail goto*//*Label 4760*/ GIMT_Encode4(224315), // Rule ID 80 //
84591 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::hwasan_check_memaccess),
84592 // MIs[0] Operand 1
84593 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
84594 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID),
84595 // MIs[0] ptr
84596 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
84597 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64noipRegClassID),
84598 // MIs[0] accessinfo
84599 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
84600 // (intrinsic_void 184:{ *:[iPTR] }, X9:{ *:[i64] }, GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo) => (HWASAN_CHECK_MEMACCESS:{ *:[i64] } GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo)
84601 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
84602 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::X9), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
84603 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // X9
84604 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HWASAN_CHECK_MEMACCESS),
84605 GIR_RootToRootCopy, /*OpIdx*/2, // ptr
84606 GIR_RootToRootCopy, /*OpIdx*/3, // accessinfo
84607 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X16*/0,
84608 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X17*/1,
84609 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::LR*/2,
84610 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/3,
84611 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84612 GIR_RootConstrainSelectedInstOperands,
84613 // GIR_Coverage, 80,
84614 GIR_EraseRootFromParent_Done,
84615 // Label 4760: @224315
84616 GIM_Try, /*On fail goto*//*Label 4761*/ GIMT_Encode4(224383), // Rule ID 81 //
84617 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::hwasan_check_memaccess_shortgranules),
84618 // MIs[0] Operand 1
84619 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
84620 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64common_and_GPR64noipRegClassID),
84621 // MIs[0] ptr
84622 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
84623 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64noipRegClassID),
84624 // MIs[0] accessinfo
84625 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
84626 // (intrinsic_void 186:{ *:[iPTR] }, X20:{ *:[i64] }, GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo) => (HWASAN_CHECK_MEMACCESS_SHORTGRANULES:{ *:[i64] } GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo)
84627 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
84628 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::X20), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
84629 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // X20
84630 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES),
84631 GIR_RootToRootCopy, /*OpIdx*/2, // ptr
84632 GIR_RootToRootCopy, /*OpIdx*/3, // accessinfo
84633 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X16*/0,
84634 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X17*/1,
84635 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::LR*/2,
84636 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/3,
84637 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84638 GIR_RootConstrainSelectedInstOperands,
84639 // GIR_Coverage, 81,
84640 GIR_EraseRootFromParent_Done,
84641 // Label 4761: @224383
84642 GIM_Try, /*On fail goto*//*Label 4762*/ GIMT_Encode4(224463), // Rule ID 6832 //
84643 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
84644 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84645 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84646 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84647 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84648 // MIs[0] addr
84649 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84650 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84651 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_1),
84652 // (intrinsic_w_chain:{ *:[i32] } 1057:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_1>> => (STXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
84653 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
84654 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
84655 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
84656 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(16), // val
84657 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
84658 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
84659 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRB),
84660 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84661 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
84662 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84663 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84664 GIR_RootConstrainSelectedInstOperands,
84665 // GIR_Coverage, 6832,
84666 GIR_EraseRootFromParent_Done,
84667 // Label 4762: @224463
84668 GIM_Try, /*On fail goto*//*Label 4763*/ GIMT_Encode4(224543), // Rule ID 6833 //
84669 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
84670 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84671 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84672 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84673 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84674 // MIs[0] addr
84675 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84676 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84677 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_2),
84678 // (intrinsic_w_chain:{ *:[i32] } 1057:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_2>> => (STXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
84679 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
84680 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
84681 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
84682 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(16), // val
84683 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
84684 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
84685 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRH),
84686 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84687 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
84688 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84689 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84690 GIR_RootConstrainSelectedInstOperands,
84691 // GIR_Coverage, 6833,
84692 GIR_EraseRootFromParent_Done,
84693 // Label 4763: @224543
84694 GIM_Try, /*On fail goto*//*Label 4764*/ GIMT_Encode4(224623), // Rule ID 6834 //
84695 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
84696 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84697 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84698 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84699 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84700 // MIs[0] addr
84701 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84702 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84703 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_4),
84704 // (intrinsic_w_chain:{ *:[i32] } 1057:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_4>> => (STXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
84705 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
84706 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
84707 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
84708 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(16), // val
84709 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
84710 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
84711 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRW),
84712 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84713 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
84714 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84715 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84716 GIR_RootConstrainSelectedInstOperands,
84717 // GIR_Coverage, 6834,
84718 GIR_EraseRootFromParent_Done,
84719 // Label 4764: @224623
84720 GIM_Try, /*On fail goto*//*Label 4765*/ GIMT_Encode4(224674), // Rule ID 6835 //
84721 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
84722 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84723 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84724 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84725 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84726 // MIs[0] addr
84727 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84728 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84729 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_8),
84730 // (intrinsic_w_chain:{ *:[i32] } 1057:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_8>> => (STXRX:{ *:[i32] } GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)
84731 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRX),
84732 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84733 GIR_RootToRootCopy, /*OpIdx*/2, // val
84734 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84735 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84736 GIR_RootConstrainSelectedInstOperands,
84737 // GIR_Coverage, 6835,
84738 GIR_EraseRootFromParent_Done,
84739 // Label 4765: @224674
84740 GIM_Try, /*On fail goto*//*Label 4766*/ GIMT_Encode4(224754), // Rule ID 6842 //
84741 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
84742 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84743 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84744 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84745 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84746 // MIs[0] addr
84747 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84748 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84749 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_1),
84750 // (intrinsic_w_chain:{ *:[i32] } 1055:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_1>> => (STLXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
84751 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
84752 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
84753 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
84754 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(16), // val
84755 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
84756 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
84757 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRB),
84758 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84759 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
84760 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84761 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84762 GIR_RootConstrainSelectedInstOperands,
84763 // GIR_Coverage, 6842,
84764 GIR_EraseRootFromParent_Done,
84765 // Label 4766: @224754
84766 GIM_Try, /*On fail goto*//*Label 4767*/ GIMT_Encode4(224834), // Rule ID 6843 //
84767 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
84768 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84769 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84770 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84771 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84772 // MIs[0] addr
84773 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84774 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84775 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_2),
84776 // (intrinsic_w_chain:{ *:[i32] } 1055:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_2>> => (STLXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
84777 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
84778 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
84779 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
84780 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(16), // val
84781 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
84782 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
84783 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRH),
84784 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84785 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
84786 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84787 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84788 GIR_RootConstrainSelectedInstOperands,
84789 // GIR_Coverage, 6843,
84790 GIR_EraseRootFromParent_Done,
84791 // Label 4767: @224834
84792 GIM_Try, /*On fail goto*//*Label 4768*/ GIMT_Encode4(224914), // Rule ID 6844 //
84793 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
84794 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84795 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84796 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84797 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84798 // MIs[0] addr
84799 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84800 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84801 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_4),
84802 // (intrinsic_w_chain:{ *:[i32] } 1055:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_4>> => (STLXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
84803 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
84804 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
84805 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
84806 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(16), // val
84807 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
84808 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
84809 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRW),
84810 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84811 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
84812 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84813 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84814 GIR_RootConstrainSelectedInstOperands,
84815 // GIR_Coverage, 6844,
84816 GIR_EraseRootFromParent_Done,
84817 // Label 4768: @224914
84818 GIM_Try, /*On fail goto*//*Label 4769*/ GIMT_Encode4(224965), // Rule ID 6845 //
84819 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
84820 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
84821 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
84822 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
84823 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84824 // MIs[0] addr
84825 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84826 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84827 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_8),
84828 // (intrinsic_w_chain:{ *:[i32] } 1055:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_8>> => (STLXRX:{ *:[i32] } GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)
84829 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRX),
84830 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
84831 GIR_RootToRootCopy, /*OpIdx*/2, // val
84832 GIR_RootToRootCopy, /*OpIdx*/3, // addr
84833 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84834 GIR_RootConstrainSelectedInstOperands,
84835 // GIR_Coverage, 6845,
84836 GIR_EraseRootFromParent_Done,
84837 // Label 4769: @224965
84838 GIM_Try, /*On fail goto*//*Label 4770*/ GIMT_Encode4(225018), // Rule ID 8400 //
84839 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
84840 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ld1uwq),
84841 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
84842 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
84843 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
84844 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
84845 // MIs[0] base
84846 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84847 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84848 // (intrinsic_w_chain:{ *:[nxv4i32] } 1351:{ *:[iPTR] }, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base) => (LD1W_Q_IMM:{ *:[nxv4i32] } PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
84849 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1W_Q_IMM),
84850 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
84851 GIR_RootToRootCopy, /*OpIdx*/2, // Pg
84852 GIR_RootToRootCopy, /*OpIdx*/3, // base
84853 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
84854 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84855 GIR_RootConstrainSelectedInstOperands,
84856 // GIR_Coverage, 8400,
84857 GIR_EraseRootFromParent_Done,
84858 // Label 4770: @225018
84859 GIM_Try, /*On fail goto*//*Label 4771*/ GIMT_Encode4(225071), // Rule ID 8403 //
84860 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
84861 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ld1uwq),
84862 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
84863 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
84864 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
84865 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
84866 // MIs[0] base
84867 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84868 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84869 // (intrinsic_w_chain:{ *:[nxv4f32] } 1351:{ *:[iPTR] }, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base) => (LD1W_Q_IMM:{ *:[nxv4f32] } PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
84870 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1W_Q_IMM),
84871 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
84872 GIR_RootToRootCopy, /*OpIdx*/2, // Pg
84873 GIR_RootToRootCopy, /*OpIdx*/3, // base
84874 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
84875 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84876 GIR_RootConstrainSelectedInstOperands,
84877 // GIR_Coverage, 8403,
84878 GIR_EraseRootFromParent_Done,
84879 // Label 4771: @225071
84880 GIM_Try, /*On fail goto*//*Label 4772*/ GIMT_Encode4(225124), // Rule ID 8412 //
84881 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
84882 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ld1udq),
84883 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
84884 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
84885 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
84886 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
84887 // MIs[0] base
84888 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84889 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84890 // (intrinsic_w_chain:{ *:[nxv2i64] } 1350:{ *:[iPTR] }, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base) => (LD1D_Q_IMM:{ *:[nxv2i64] } PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
84891 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1D_Q_IMM),
84892 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
84893 GIR_RootToRootCopy, /*OpIdx*/2, // Pg
84894 GIR_RootToRootCopy, /*OpIdx*/3, // base
84895 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
84896 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84897 GIR_RootConstrainSelectedInstOperands,
84898 // GIR_Coverage, 8412,
84899 GIR_EraseRootFromParent_Done,
84900 // Label 4772: @225124
84901 GIM_Try, /*On fail goto*//*Label 4773*/ GIMT_Encode4(225177), // Rule ID 8415 //
84902 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
84903 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ld1udq),
84904 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
84905 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
84906 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
84907 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
84908 // MIs[0] base
84909 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84910 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84911 // (intrinsic_w_chain:{ *:[nxv2f64] } 1350:{ *:[iPTR] }, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base) => (LD1D_Q_IMM:{ *:[nxv2f64] } PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
84912 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1D_Q_IMM),
84913 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
84914 GIR_RootToRootCopy, /*OpIdx*/2, // Pg
84915 GIR_RootToRootCopy, /*OpIdx*/3, // base
84916 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
84917 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84918 GIR_RootConstrainSelectedInstOperands,
84919 // GIR_Coverage, 8415,
84920 GIR_EraseRootFromParent_Done,
84921 // Label 4773: @225177
84922 GIM_Try, /*On fail goto*//*Label 4774*/ GIMT_Encode4(225223), // Rule ID 148 //
84923 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMTE),
84924 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_irg),
84925 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
84926 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
84927 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84928 // MIs[0] Rn
84929 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
84930 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84931 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
84932 // (intrinsic_w_chain:{ *:[i64] } 540:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (IRG:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
84933 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::IRG),
84934 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
84935 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
84936 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
84937 GIR_RootConstrainSelectedInstOperands,
84938 // GIR_Coverage, 148,
84939 GIR_EraseRootFromParent_Done,
84940 // Label 4774: @225223
84941 GIM_Try, /*On fail goto*//*Label 4775*/ GIMT_Encode4(225276), // Rule ID 8406 //
84942 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
84943 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_st1wq),
84944 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
84945 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
84946 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
84947 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
84948 // MIs[0] base
84949 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84950 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84951 // (intrinsic_void 1668:{ *:[iPTR] }, ZPR128:{ *:[nxv4i32] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base) => (ST1W_Q_IMM Z_q:{ *:[nxv4i32] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
84952 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1W_Q_IMM),
84953 GIR_RootToRootCopy, /*OpIdx*/1, // Zt
84954 GIR_RootToRootCopy, /*OpIdx*/2, // Pg
84955 GIR_RootToRootCopy, /*OpIdx*/3, // base
84956 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
84957 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84958 GIR_RootConstrainSelectedInstOperands,
84959 // GIR_Coverage, 8406,
84960 GIR_EraseRootFromParent_Done,
84961 // Label 4775: @225276
84962 GIM_Try, /*On fail goto*//*Label 4776*/ GIMT_Encode4(225329), // Rule ID 8409 //
84963 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
84964 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_st1wq),
84965 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
84966 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
84967 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
84968 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
84969 // MIs[0] base
84970 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84971 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84972 // (intrinsic_void 1668:{ *:[iPTR] }, ZPR128:{ *:[nxv4f32] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base) => (ST1W_Q_IMM Z_q:{ *:[nxv4f32] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
84973 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1W_Q_IMM),
84974 GIR_RootToRootCopy, /*OpIdx*/1, // Zt
84975 GIR_RootToRootCopy, /*OpIdx*/2, // Pg
84976 GIR_RootToRootCopy, /*OpIdx*/3, // base
84977 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
84978 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
84979 GIR_RootConstrainSelectedInstOperands,
84980 // GIR_Coverage, 8409,
84981 GIR_EraseRootFromParent_Done,
84982 // Label 4776: @225329
84983 GIM_Try, /*On fail goto*//*Label 4777*/ GIMT_Encode4(225382), // Rule ID 8418 //
84984 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
84985 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_st1dq),
84986 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
84987 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
84988 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
84989 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
84990 // MIs[0] base
84991 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
84992 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
84993 // (intrinsic_void 1664:{ *:[iPTR] }, ZPR128:{ *:[nxv2i64] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base) => (ST1D_Q_IMM Z_q:{ *:[nxv2i64] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
84994 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1D_Q_IMM),
84995 GIR_RootToRootCopy, /*OpIdx*/1, // Zt
84996 GIR_RootToRootCopy, /*OpIdx*/2, // Pg
84997 GIR_RootToRootCopy, /*OpIdx*/3, // base
84998 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
84999 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85000 GIR_RootConstrainSelectedInstOperands,
85001 // GIR_Coverage, 8418,
85002 GIR_EraseRootFromParent_Done,
85003 // Label 4777: @225382
85004 GIM_Try, /*On fail goto*//*Label 4778*/ GIMT_Encode4(225435), // Rule ID 8421 //
85005 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
85006 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_st1dq),
85007 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
85008 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
85009 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85010 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85011 // MIs[0] base
85012 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
85013 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85014 // (intrinsic_void 1664:{ *:[iPTR] }, ZPR128:{ *:[nxv2f64] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base) => (ST1D_Q_IMM Z_q:{ *:[nxv2f64] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
85015 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1D_Q_IMM),
85016 GIR_RootToRootCopy, /*OpIdx*/1, // Zt
85017 GIR_RootToRootCopy, /*OpIdx*/2, // Pg
85018 GIR_RootToRootCopy, /*OpIdx*/3, // base
85019 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
85020 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85021 GIR_RootConstrainSelectedInstOperands,
85022 // GIR_Coverage, 8421,
85023 GIR_EraseRootFromParent_Done,
85024 // Label 4778: @225435
85025 GIM_Reject,
85026 // Label 4740: @225436
85027 GIM_Try, /*On fail goto*//*Label 4779*/ GIMT_Encode4(227135),
85028 GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
85029 GIM_Try, /*On fail goto*//*Label 4780*/ GIMT_Encode4(225515), // Rule ID 3324 //
85030 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85031 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_scalar_offset),
85032 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
85033 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
85034 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
85035 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85036 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85037 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
85038 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
85039 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
85040 // MIs[1] Operand 1
85041 // No operand predicates
85042 // MIs[0] prfop
85043 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85044 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85045 GIM_CheckIsSafeToFold, /*NumInsns*/1,
85046 // (intrinsic_void 1417:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR32:{ *:[nxv4i32] }:$Zn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFB_S_PZI (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR32:{ *:[nxv4i32] }:$Zn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)
85047 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_S_PZI),
85048 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85049 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85050 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
85051 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
85052 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
85053 GIR_RootConstrainSelectedInstOperands,
85054 // GIR_Coverage, 3324,
85055 GIR_EraseRootFromParent_Done,
85056 // Label 4780: @225515
85057 GIM_Try, /*On fail goto*//*Label 4781*/ GIMT_Encode4(225586), // Rule ID 3337 //
85058 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85059 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_scalar_offset),
85060 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
85061 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
85062 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
85063 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85064 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85065 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
85066 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
85067 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
85068 // MIs[1] Operand 1
85069 // No operand predicates
85070 // MIs[0] prfop
85071 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85072 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85073 GIM_CheckIsSafeToFold, /*NumInsns*/1,
85074 // (intrinsic_void 1417:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR32:{ *:[nxv2i64] }:$Zn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFB_D_PZI (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR32:{ *:[nxv2i64] }:$Zn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)
85075 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_D_PZI),
85076 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85077 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85078 GIR_RootToRootCopy, /*OpIdx*/2, // Zn
85079 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
85080 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
85081 GIR_RootConstrainSelectedInstOperands,
85082 // GIR_Coverage, 3337,
85083 GIR_EraseRootFromParent_Done,
85084 // Label 4781: @225586
85085 GIM_Try, /*On fail goto*//*Label 4782*/ GIMT_Encode4(225645), // Rule ID 3509 //
85086 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
85087 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_addha),
85088 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
85089 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
85090 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
85091 // MIs[0] tile
85092 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
85093 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
85094 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85095 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85096 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85097 // (intrinsic_void 752:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv4i1] }:$pn, PPR3bAny:{ *:[nxv4i1] }:$pm, ZPR32:{ *:[nxv4i32] }:$zn) => (ADDHA_MPPZ_S_PSEUDO_S (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, ?:{ *:[nxv4i1] }:$pn, ?:{ *:[nxv4i1] }:$pm, ?:{ *:[nxv4i32] }:$zn)
85098 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHA_MPPZ_S_PSEUDO_S),
85099 GIR_RootToRootCopy, /*OpIdx*/1, // tile
85100 GIR_RootToRootCopy, /*OpIdx*/2, // pn
85101 GIR_RootToRootCopy, /*OpIdx*/3, // pm
85102 GIR_RootToRootCopy, /*OpIdx*/4, // zn
85103 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85104 GIR_RootConstrainSelectedInstOperands,
85105 // GIR_Coverage, 3509,
85106 GIR_EraseRootFromParent_Done,
85107 // Label 4782: @225645
85108 GIM_Try, /*On fail goto*//*Label 4783*/ GIMT_Encode4(225704), // Rule ID 3510 //
85109 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
85110 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_addha),
85111 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
85112 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
85113 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
85114 // MIs[0] tile
85115 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
85116 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
85117 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85118 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85119 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85120 // (intrinsic_void 752:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv2i1] }:$pn, PPR3bAny:{ *:[nxv2i1] }:$pm, ZPR64:{ *:[nxv2i64] }:$zn) => (ADDHA_MPPZ_D_PSEUDO_D (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, ?:{ *:[nxv2i1] }:$pn, ?:{ *:[nxv2i1] }:$pm, ?:{ *:[nxv2i64] }:$zn)
85121 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHA_MPPZ_D_PSEUDO_D),
85122 GIR_RootToRootCopy, /*OpIdx*/1, // tile
85123 GIR_RootToRootCopy, /*OpIdx*/2, // pn
85124 GIR_RootToRootCopy, /*OpIdx*/3, // pm
85125 GIR_RootToRootCopy, /*OpIdx*/4, // zn
85126 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85127 GIR_RootConstrainSelectedInstOperands,
85128 // GIR_Coverage, 3510,
85129 GIR_EraseRootFromParent_Done,
85130 // Label 4783: @225704
85131 GIM_Try, /*On fail goto*//*Label 4784*/ GIMT_Encode4(225763), // Rule ID 11864 //
85132 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
85133 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_addva),
85134 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
85135 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
85136 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
85137 // MIs[0] tile
85138 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
85139 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
85140 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85141 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85142 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85143 // (intrinsic_void 753:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv4i1] }:$pn, PPR3bAny:{ *:[nxv4i1] }:$pm, ZPR32:{ *:[nxv4i32] }:$zn) => (ADDVA_MPPZ_S_PSEUDO_S (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, ?:{ *:[nxv4i1] }:$pn, ?:{ *:[nxv4i1] }:$pm, ?:{ *:[nxv4i32] }:$zn)
85144 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVA_MPPZ_S_PSEUDO_S),
85145 GIR_RootToRootCopy, /*OpIdx*/1, // tile
85146 GIR_RootToRootCopy, /*OpIdx*/2, // pn
85147 GIR_RootToRootCopy, /*OpIdx*/3, // pm
85148 GIR_RootToRootCopy, /*OpIdx*/4, // zn
85149 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85150 GIR_RootConstrainSelectedInstOperands,
85151 // GIR_Coverage, 11864,
85152 GIR_EraseRootFromParent_Done,
85153 // Label 4784: @225763
85154 GIM_Try, /*On fail goto*//*Label 4785*/ GIMT_Encode4(225822), // Rule ID 11865 //
85155 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
85156 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_addva),
85157 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
85158 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
85159 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
85160 // MIs[0] tile
85161 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
85162 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
85163 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85164 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85165 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85166 // (intrinsic_void 753:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv2i1] }:$pn, PPR3bAny:{ *:[nxv2i1] }:$pm, ZPR64:{ *:[nxv2i64] }:$zn) => (ADDVA_MPPZ_D_PSEUDO_D (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, ?:{ *:[nxv2i1] }:$pn, ?:{ *:[nxv2i1] }:$pm, ?:{ *:[nxv2i64] }:$zn)
85167 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVA_MPPZ_D_PSEUDO_D),
85168 GIR_RootToRootCopy, /*OpIdx*/1, // tile
85169 GIR_RootToRootCopy, /*OpIdx*/2, // pn
85170 GIR_RootToRootCopy, /*OpIdx*/3, // pm
85171 GIR_RootToRootCopy, /*OpIdx*/4, // zn
85172 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85173 GIR_RootConstrainSelectedInstOperands,
85174 // GIR_Coverage, 11865,
85175 GIR_EraseRootFromParent_Done,
85176 // Label 4785: @225822
85177 GIM_Try, /*On fail goto*//*Label 4786*/ GIMT_Encode4(225882), // Rule ID 3322 //
85178 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85179 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_uxtw_index),
85180 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
85181 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
85182 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85183 // MIs[0] Rn
85184 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85185 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85186 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85187 // MIs[0] prfop
85188 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85189 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85190 // (intrinsic_void 1419:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW8Only:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFB_S_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW8Only:{ *:[nxv4i32] }:$Zm)
85191 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_S_UXTW_SCALED),
85192 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85193 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85194 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85195 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85196 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85197 GIR_RootConstrainSelectedInstOperands,
85198 // GIR_Coverage, 3322,
85199 GIR_EraseRootFromParent_Done,
85200 // Label 4786: @225882
85201 GIM_Try, /*On fail goto*//*Label 4787*/ GIMT_Encode4(225942), // Rule ID 3323 //
85202 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85203 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_sxtw_index),
85204 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
85205 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
85206 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85207 // MIs[0] Rn
85208 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85209 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85210 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85211 // MIs[0] prfop
85212 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85213 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85214 // (intrinsic_void 1418:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW8Only:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFB_S_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW8Only:{ *:[nxv4i32] }:$Zm)
85215 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_S_SXTW_SCALED),
85216 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85217 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85218 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85219 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85220 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85221 GIR_RootConstrainSelectedInstOperands,
85222 // GIR_Coverage, 3323,
85223 GIR_EraseRootFromParent_Done,
85224 // Label 4787: @225942
85225 GIM_Try, /*On fail goto*//*Label 4788*/ GIMT_Encode4(226002), // Rule ID 3334 //
85226 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85227 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_uxtw_index),
85228 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
85229 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
85230 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85231 // MIs[0] Rn
85232 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85233 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85234 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85235 // MIs[0] prfop
85236 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85237 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85238 // (intrinsic_void 1419:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW8Only:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFB_D_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW8Only:{ *:[nxv2i64] }:$Zm)
85239 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_D_UXTW_SCALED),
85240 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85241 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85242 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85243 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85244 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85245 GIR_RootConstrainSelectedInstOperands,
85246 // GIR_Coverage, 3334,
85247 GIR_EraseRootFromParent_Done,
85248 // Label 4788: @226002
85249 GIM_Try, /*On fail goto*//*Label 4789*/ GIMT_Encode4(226062), // Rule ID 3335 //
85250 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85251 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_sxtw_index),
85252 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
85253 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
85254 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85255 // MIs[0] Rn
85256 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85257 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85258 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85259 // MIs[0] prfop
85260 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85261 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85262 // (intrinsic_void 1418:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW8Only:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFB_D_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW8Only:{ *:[nxv2i64] }:$Zm)
85263 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_D_SXTW_SCALED),
85264 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85265 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85266 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85267 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85268 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85269 GIR_RootConstrainSelectedInstOperands,
85270 // GIR_Coverage, 3335,
85271 GIR_EraseRootFromParent_Done,
85272 // Label 4789: @226062
85273 GIM_Try, /*On fail goto*//*Label 4790*/ GIMT_Encode4(226122), // Rule ID 3336 //
85274 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85275 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_index),
85276 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
85277 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
85278 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85279 // MIs[0] Rn
85280 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85281 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85282 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85283 // MIs[0] prfop
85284 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85285 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85286 // (intrinsic_void 1416:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL8:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFB_D_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL8:{ *:[nxv2i64] }:$Zm)
85287 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_D_SCALED),
85288 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85289 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85290 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85291 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85292 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85293 GIR_RootConstrainSelectedInstOperands,
85294 // GIR_Coverage, 3336,
85295 GIR_EraseRootFromParent_Done,
85296 // Label 4790: @226122
85297 GIM_Try, /*On fail goto*//*Label 4791*/ GIMT_Encode4(226182), // Rule ID 8537 //
85298 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85299 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfh_gather_uxtw_index),
85300 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
85301 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
85302 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85303 // MIs[0] Rn
85304 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85305 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85306 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85307 // MIs[0] prfop
85308 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85309 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85310 // (intrinsic_void 1427:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW16:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFH_S_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW16:{ *:[nxv4i32] }:$Zm)
85311 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFH_S_UXTW_SCALED),
85312 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85313 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85314 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85315 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85316 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85317 GIR_RootConstrainSelectedInstOperands,
85318 // GIR_Coverage, 8537,
85319 GIR_EraseRootFromParent_Done,
85320 // Label 4791: @226182
85321 GIM_Try, /*On fail goto*//*Label 4792*/ GIMT_Encode4(226242), // Rule ID 8538 //
85322 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85323 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfh_gather_sxtw_index),
85324 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
85325 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
85326 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85327 // MIs[0] Rn
85328 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85329 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85330 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85331 // MIs[0] prfop
85332 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85333 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85334 // (intrinsic_void 1426:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW16:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFH_S_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW16:{ *:[nxv4i32] }:$Zm)
85335 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFH_S_SXTW_SCALED),
85336 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85337 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85338 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85339 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85340 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85341 GIR_RootConstrainSelectedInstOperands,
85342 // GIR_Coverage, 8538,
85343 GIR_EraseRootFromParent_Done,
85344 // Label 4792: @226242
85345 GIM_Try, /*On fail goto*//*Label 4793*/ GIMT_Encode4(226302), // Rule ID 8539 //
85346 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85347 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfw_gather_uxtw_index),
85348 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
85349 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
85350 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85351 // MIs[0] Rn
85352 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85353 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85354 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85355 // MIs[0] prfop
85356 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85357 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85358 // (intrinsic_void 1431:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW32:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFW_S_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW32:{ *:[nxv4i32] }:$Zm)
85359 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFW_S_UXTW_SCALED),
85360 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85361 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85362 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85363 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85364 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85365 GIR_RootConstrainSelectedInstOperands,
85366 // GIR_Coverage, 8539,
85367 GIR_EraseRootFromParent_Done,
85368 // Label 4793: @226302
85369 GIM_Try, /*On fail goto*//*Label 4794*/ GIMT_Encode4(226362), // Rule ID 8540 //
85370 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85371 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfw_gather_sxtw_index),
85372 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
85373 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
85374 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85375 // MIs[0] Rn
85376 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85377 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85378 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85379 // MIs[0] prfop
85380 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85381 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85382 // (intrinsic_void 1430:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW32:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFW_S_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW32:{ *:[nxv4i32] }:$Zm)
85383 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFW_S_SXTW_SCALED),
85384 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85385 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85386 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85387 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85388 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85389 GIR_RootConstrainSelectedInstOperands,
85390 // GIR_Coverage, 8540,
85391 GIR_EraseRootFromParent_Done,
85392 // Label 4794: @226362
85393 GIM_Try, /*On fail goto*//*Label 4795*/ GIMT_Encode4(226422), // Rule ID 8541 //
85394 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85395 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfd_gather_uxtw_index),
85396 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
85397 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
85398 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85399 // MIs[0] Rn
85400 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85401 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85402 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85403 // MIs[0] prfop
85404 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85405 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85406 // (intrinsic_void 1423:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW64:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFD_S_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW64:{ *:[nxv4i32] }:$Zm)
85407 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFD_S_UXTW_SCALED),
85408 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85409 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85410 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85411 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85412 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85413 GIR_RootConstrainSelectedInstOperands,
85414 // GIR_Coverage, 8541,
85415 GIR_EraseRootFromParent_Done,
85416 // Label 4795: @226422
85417 GIM_Try, /*On fail goto*//*Label 4796*/ GIMT_Encode4(226482), // Rule ID 8542 //
85418 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85419 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfd_gather_sxtw_index),
85420 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
85421 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
85422 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85423 // MIs[0] Rn
85424 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85425 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85426 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85427 // MIs[0] prfop
85428 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85429 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85430 // (intrinsic_void 1422:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW64:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFD_S_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW64:{ *:[nxv4i32] }:$Zm)
85431 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFD_S_SXTW_SCALED),
85432 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85433 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85434 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85435 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85436 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85437 GIR_RootConstrainSelectedInstOperands,
85438 // GIR_Coverage, 8542,
85439 GIR_EraseRootFromParent_Done,
85440 // Label 4796: @226482
85441 GIM_Try, /*On fail goto*//*Label 4797*/ GIMT_Encode4(226542), // Rule ID 8543 //
85442 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85443 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfh_gather_uxtw_index),
85444 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
85445 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
85446 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85447 // MIs[0] Rn
85448 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85449 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85450 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85451 // MIs[0] prfop
85452 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85453 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85454 // (intrinsic_void 1427:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW16:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFH_D_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW16:{ *:[nxv2i64] }:$Zm)
85455 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFH_D_UXTW_SCALED),
85456 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85457 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85458 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85459 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85460 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85461 GIR_RootConstrainSelectedInstOperands,
85462 // GIR_Coverage, 8543,
85463 GIR_EraseRootFromParent_Done,
85464 // Label 4797: @226542
85465 GIM_Try, /*On fail goto*//*Label 4798*/ GIMT_Encode4(226602), // Rule ID 8544 //
85466 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85467 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfh_gather_sxtw_index),
85468 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
85469 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
85470 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85471 // MIs[0] Rn
85472 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85473 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85474 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85475 // MIs[0] prfop
85476 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85477 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85478 // (intrinsic_void 1426:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW16:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFH_D_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW16:{ *:[nxv2i64] }:$Zm)
85479 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFH_D_SXTW_SCALED),
85480 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85481 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85482 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85483 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85484 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85485 GIR_RootConstrainSelectedInstOperands,
85486 // GIR_Coverage, 8544,
85487 GIR_EraseRootFromParent_Done,
85488 // Label 4798: @226602
85489 GIM_Try, /*On fail goto*//*Label 4799*/ GIMT_Encode4(226662), // Rule ID 8545 //
85490 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85491 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfw_gather_uxtw_index),
85492 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
85493 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
85494 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85495 // MIs[0] Rn
85496 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85497 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85498 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85499 // MIs[0] prfop
85500 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85501 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85502 // (intrinsic_void 1431:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW32:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFW_D_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW32:{ *:[nxv2i64] }:$Zm)
85503 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFW_D_UXTW_SCALED),
85504 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85505 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85506 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85507 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85508 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85509 GIR_RootConstrainSelectedInstOperands,
85510 // GIR_Coverage, 8545,
85511 GIR_EraseRootFromParent_Done,
85512 // Label 4799: @226662
85513 GIM_Try, /*On fail goto*//*Label 4800*/ GIMT_Encode4(226722), // Rule ID 8546 //
85514 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85515 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfw_gather_sxtw_index),
85516 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
85517 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
85518 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85519 // MIs[0] Rn
85520 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85521 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85522 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85523 // MIs[0] prfop
85524 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85525 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85526 // (intrinsic_void 1430:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW32:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFW_D_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW32:{ *:[nxv2i64] }:$Zm)
85527 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFW_D_SXTW_SCALED),
85528 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85529 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85530 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85531 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85532 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85533 GIR_RootConstrainSelectedInstOperands,
85534 // GIR_Coverage, 8546,
85535 GIR_EraseRootFromParent_Done,
85536 // Label 4800: @226722
85537 GIM_Try, /*On fail goto*//*Label 4801*/ GIMT_Encode4(226782), // Rule ID 8547 //
85538 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85539 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfd_gather_uxtw_index),
85540 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
85541 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
85542 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85543 // MIs[0] Rn
85544 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85545 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85546 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85547 // MIs[0] prfop
85548 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85549 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85550 // (intrinsic_void 1423:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW64:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFD_D_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW64:{ *:[nxv2i64] }:$Zm)
85551 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFD_D_UXTW_SCALED),
85552 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85553 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85554 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85555 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85556 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85557 GIR_RootConstrainSelectedInstOperands,
85558 // GIR_Coverage, 8547,
85559 GIR_EraseRootFromParent_Done,
85560 // Label 4801: @226782
85561 GIM_Try, /*On fail goto*//*Label 4802*/ GIMT_Encode4(226842), // Rule ID 8548 //
85562 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85563 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfd_gather_sxtw_index),
85564 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
85565 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
85566 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85567 // MIs[0] Rn
85568 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85569 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85570 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85571 // MIs[0] prfop
85572 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85573 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85574 // (intrinsic_void 1422:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW64:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFD_D_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW64:{ *:[nxv2i64] }:$Zm)
85575 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFD_D_SXTW_SCALED),
85576 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85577 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85578 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85579 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85580 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85581 GIR_RootConstrainSelectedInstOperands,
85582 // GIR_Coverage, 8548,
85583 GIR_EraseRootFromParent_Done,
85584 // Label 4802: @226842
85585 GIM_Try, /*On fail goto*//*Label 4803*/ GIMT_Encode4(226902), // Rule ID 8549 //
85586 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85587 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfh_gather_index),
85588 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
85589 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
85590 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85591 // MIs[0] Rn
85592 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85593 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85594 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85595 // MIs[0] prfop
85596 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85597 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85598 // (intrinsic_void 1424:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL16:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFH_D_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL16:{ *:[nxv2i64] }:$Zm)
85599 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFH_D_SCALED),
85600 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85601 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85602 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85603 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85604 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85605 GIR_RootConstrainSelectedInstOperands,
85606 // GIR_Coverage, 8549,
85607 GIR_EraseRootFromParent_Done,
85608 // Label 4803: @226902
85609 GIM_Try, /*On fail goto*//*Label 4804*/ GIMT_Encode4(226962), // Rule ID 8550 //
85610 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85611 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfw_gather_index),
85612 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
85613 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
85614 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85615 // MIs[0] Rn
85616 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85617 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85618 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85619 // MIs[0] prfop
85620 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85621 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85622 // (intrinsic_void 1428:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL32:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFW_D_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL32:{ *:[nxv2i64] }:$Zm)
85623 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFW_D_SCALED),
85624 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85625 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85626 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85627 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85628 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85629 GIR_RootConstrainSelectedInstOperands,
85630 // GIR_Coverage, 8550,
85631 GIR_EraseRootFromParent_Done,
85632 // Label 4804: @226962
85633 GIM_Try, /*On fail goto*//*Label 4805*/ GIMT_Encode4(227022), // Rule ID 8551 //
85634 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
85635 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfd_gather_index),
85636 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
85637 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
85638 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85639 // MIs[0] Rn
85640 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
85641 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
85642 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
85643 // MIs[0] prfop
85644 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
85645 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
85646 // (intrinsic_void 1420:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL64:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop) => (PRFD_D_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL64:{ *:[nxv2i64] }:$Zm)
85647 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFD_D_SCALED),
85648 GIR_RootToRootCopy, /*OpIdx*/4, // prfop
85649 GIR_RootToRootCopy, /*OpIdx*/1, // Pg
85650 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
85651 GIR_RootToRootCopy, /*OpIdx*/3, // Zm
85652 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85653 GIR_RootConstrainSelectedInstOperands,
85654 // GIR_Coverage, 8551,
85655 GIR_EraseRootFromParent_Done,
85656 // Label 4805: @227022
85657 GIM_Try, /*On fail goto*//*Label 4806*/ GIMT_Encode4(227078), // Rule ID 12368 //
85658 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxp),
85659 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
85660 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
85661 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
85662 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
85663 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
85664 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
85665 // MIs[0] addr
85666 GIM_CheckPointerToAny, /*MI*/0, /*Op*/4, /*SizeInBits*/64,
85667 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
85668 // (intrinsic_w_chain:{ *:[i32] } 1054:{ *:[iPTR] }, GPR64:{ *:[i64] }:$lo, GPR64:{ *:[i64] }:$hi, GPR64:{ *:[i64] }:$addr) => (STLXPX:{ *:[i32] } GPR64:{ *:[i64] }:$lo, GPR64:{ *:[i64] }:$hi, GPR64:{ *:[i64] }:$addr)
85669 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXPX),
85670 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
85671 GIR_RootToRootCopy, /*OpIdx*/2, // lo
85672 GIR_RootToRootCopy, /*OpIdx*/3, // hi
85673 GIR_RootToRootCopy, /*OpIdx*/4, // addr
85674 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85675 GIR_RootConstrainSelectedInstOperands,
85676 // GIR_Coverage, 12368,
85677 GIR_EraseRootFromParent_Done,
85678 // Label 4806: @227078
85679 GIM_Try, /*On fail goto*//*Label 4807*/ GIMT_Encode4(227134), // Rule ID 12369 //
85680 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxp),
85681 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
85682 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
85683 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
85684 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
85685 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
85686 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
85687 // MIs[0] addr
85688 GIM_CheckPointerToAny, /*MI*/0, /*Op*/4, /*SizeInBits*/64,
85689 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
85690 // (intrinsic_w_chain:{ *:[i32] } 1056:{ *:[iPTR] }, GPR64:{ *:[i64] }:$lo, GPR64:{ *:[i64] }:$hi, GPR64:{ *:[i64] }:$addr) => (STXPX:{ *:[i32] } GPR64:{ *:[i64] }:$lo, GPR64:{ *:[i64] }:$hi, GPR64:{ *:[i64] }:$addr)
85691 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXPX),
85692 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
85693 GIR_RootToRootCopy, /*OpIdx*/2, // lo
85694 GIR_RootToRootCopy, /*OpIdx*/3, // hi
85695 GIR_RootToRootCopy, /*OpIdx*/4, // addr
85696 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85697 GIR_RootConstrainSelectedInstOperands,
85698 // GIR_Coverage, 12369,
85699 GIR_EraseRootFromParent_Done,
85700 // Label 4807: @227134
85701 GIM_Reject,
85702 // Label 4779: @227135
85703 GIM_Try, /*On fail goto*//*Label 4808*/ GIMT_Encode4(229184),
85704 GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
85705 GIM_Try, /*On fail goto*//*Label 4809*/ GIMT_Encode4(227203), // Rule ID 3502 //
85706 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
85707 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mopa),
85708 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
85709 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
85710 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
85711 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
85712 // MIs[0] tile
85713 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
85714 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
85715 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85716 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85717 // (intrinsic_void 814:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv4i1] }:$Pn, PPR3bAny:{ *:[nxv4i1] }:$Pm, nxv4f32:{ *:[nxv4f32] }:$Zn, nxv4f32:{ *:[nxv4f32] }:$Zm) => (FMOPA_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv4i1] }:$Pn, ?:{ *:[nxv4i1] }:$Pm, ?:{ *:[nxv4f32] }:$Zn, ?:{ *:[nxv4f32] }:$Zm)
85718 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPA_MPPZZ_S_PSEUDO),
85719 GIR_RootToRootCopy, /*OpIdx*/1, // tile
85720 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
85721 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
85722 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
85723 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
85724 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85725 GIR_RootConstrainSelectedInstOperands,
85726 // GIR_Coverage, 3502,
85727 GIR_EraseRootFromParent_Done,
85728 // Label 4809: @227203
85729 GIM_Try, /*On fail goto*//*Label 4810*/ GIMT_Encode4(227263), // Rule ID 3503 //
85730 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF64F64),
85731 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mopa),
85732 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
85733 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
85734 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
85735 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
85736 // MIs[0] tile
85737 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
85738 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
85739 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85740 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85741 // (intrinsic_void 814:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv2i1] }:$Pn, PPR3bAny:{ *:[nxv2i1] }:$Pm, nxv2f64:{ *:[nxv2f64] }:$Zn, nxv2f64:{ *:[nxv2f64] }:$Zm) => (FMOPA_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv2i1] }:$Pn, ?:{ *:[nxv2i1] }:$Pm, ?:{ *:[nxv2f64] }:$Zn, ?:{ *:[nxv2f64] }:$Zm)
85742 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPA_MPPZZ_D_PSEUDO),
85743 GIR_RootToRootCopy, /*OpIdx*/1, // tile
85744 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
85745 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
85746 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
85747 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
85748 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85749 GIR_RootConstrainSelectedInstOperands,
85750 // GIR_Coverage, 3503,
85751 GIR_EraseRootFromParent_Done,
85752 // Label 4810: @227263
85753 GIM_Try, /*On fail goto*//*Label 4811*/ GIMT_Encode4(227323), // Rule ID 3504 //
85754 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF16F16orSMEF8F16),
85755 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mopa),
85756 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
85757 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
85758 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
85759 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
85760 // MIs[0] tile
85761 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
85762 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
85763 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85764 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85765 // (intrinsic_void 814:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm) => (FMOPA_MPPZZ_H_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
85766 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPA_MPPZZ_H_PSEUDO),
85767 GIR_RootToRootCopy, /*OpIdx*/1, // tile
85768 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
85769 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
85770 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
85771 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
85772 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85773 GIR_RootConstrainSelectedInstOperands,
85774 // GIR_Coverage, 3504,
85775 GIR_EraseRootFromParent_Done,
85776 // Label 4811: @227323
85777 GIM_Try, /*On fail goto*//*Label 4812*/ GIMT_Encode4(227383), // Rule ID 3505 //
85778 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
85779 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smopa_wide),
85780 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
85781 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
85782 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
85783 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
85784 // MIs[0] tile
85785 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
85786 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
85787 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85788 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85789 // (intrinsic_void 901:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm) => (SMOPA_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
85790 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOPA_MPPZZ_S_PSEUDO),
85791 GIR_RootToRootCopy, /*OpIdx*/1, // tile
85792 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
85793 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
85794 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
85795 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
85796 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85797 GIR_RootConstrainSelectedInstOperands,
85798 // GIR_Coverage, 3505,
85799 GIR_EraseRootFromParent_Done,
85800 // Label 4812: @227383
85801 GIM_Try, /*On fail goto*//*Label 4813*/ GIMT_Encode4(227443), // Rule ID 3506 //
85802 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
85803 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smopa_wide),
85804 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
85805 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
85806 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
85807 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
85808 // MIs[0] tile
85809 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
85810 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
85811 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85812 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85813 // (intrinsic_void 901:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm) => (SMOPA_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
85814 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOPA_MPPZZ_D_PSEUDO),
85815 GIR_RootToRootCopy, /*OpIdx*/1, // tile
85816 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
85817 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
85818 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
85819 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
85820 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85821 GIR_RootConstrainSelectedInstOperands,
85822 // GIR_Coverage, 3506,
85823 GIR_EraseRootFromParent_Done,
85824 // Label 4813: @227443
85825 GIM_Try, /*On fail goto*//*Label 4814*/ GIMT_Encode4(227503), // Rule ID 3507 //
85826 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
85827 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mopa_wide),
85828 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
85829 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
85830 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
85831 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
85832 // MIs[0] tile
85833 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
85834 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
85835 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85836 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85837 // (intrinsic_void 816:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8bf16:{ *:[nxv8bf16] }:$Zn, nxv8bf16:{ *:[nxv8bf16] }:$Zm) => (BFMOPA_MPPZZ_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8bf16] }:$Zn, ?:{ *:[nxv8bf16] }:$Zm)
85838 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMOPA_MPPZZ_PSEUDO),
85839 GIR_RootToRootCopy, /*OpIdx*/1, // tile
85840 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
85841 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
85842 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
85843 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
85844 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85845 GIR_RootConstrainSelectedInstOperands,
85846 // GIR_Coverage, 3507,
85847 GIR_EraseRootFromParent_Done,
85848 // Label 4814: @227503
85849 GIM_Try, /*On fail goto*//*Label 4815*/ GIMT_Encode4(227563), // Rule ID 3508 //
85850 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
85851 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mopa_wide),
85852 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
85853 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
85854 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
85855 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
85856 // MIs[0] tile
85857 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
85858 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
85859 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85860 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85861 // (intrinsic_void 816:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm) => (FMOPAL_MPPZZ_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
85862 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPAL_MPPZZ_PSEUDO),
85863 GIR_RootToRootCopy, /*OpIdx*/1, // tile
85864 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
85865 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
85866 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
85867 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
85868 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85869 GIR_RootConstrainSelectedInstOperands,
85870 // GIR_Coverage, 3508,
85871 GIR_EraseRootFromParent_Done,
85872 // Label 4815: @227563
85873 GIM_Try, /*On fail goto*//*Label 4816*/ GIMT_Encode4(227623), // Rule ID 3585 //
85874 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME2),
85875 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smopa_za32),
85876 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
85877 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
85878 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
85879 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
85880 // MIs[0] tile
85881 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
85882 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
85883 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85884 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85885 // (intrinsic_void 902:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm) => (SMOPA_MPPZZ_HtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
85886 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOPA_MPPZZ_HtoS_PSEUDO),
85887 GIR_RootToRootCopy, /*OpIdx*/1, // tile
85888 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
85889 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
85890 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
85891 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
85892 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85893 GIR_RootConstrainSelectedInstOperands,
85894 // GIR_Coverage, 3585,
85895 GIR_EraseRootFromParent_Done,
85896 // Label 4816: @227623
85897 GIM_Try, /*On fail goto*//*Label 4817*/ GIMT_Encode4(227683), // Rule ID 3586 //
85898 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME2),
85899 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_bmopa_za32),
85900 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
85901 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
85902 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
85903 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
85904 // MIs[0] tile
85905 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
85906 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
85907 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85908 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85909 // (intrinsic_void 754:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv4i1] }:$Pn, PPR3bAny:{ *:[nxv4i1] }:$Pm, nxv4i32:{ *:[nxv4i32] }:$Zn, nxv4i32:{ *:[nxv4i32] }:$Zm) => (BMOPA_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv4i1] }:$Pn, ?:{ *:[nxv4i1] }:$Pm, ?:{ *:[nxv4i32] }:$Zn, ?:{ *:[nxv4i32] }:$Zm)
85910 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BMOPA_MPPZZ_S_PSEUDO),
85911 GIR_RootToRootCopy, /*OpIdx*/1, // tile
85912 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
85913 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
85914 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
85915 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
85916 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85917 GIR_RootConstrainSelectedInstOperands,
85918 // GIR_Coverage, 3586,
85919 GIR_EraseRootFromParent_Done,
85920 // Label 4817: @227683
85921 GIM_Try, /*On fail goto*//*Label 4818*/ GIMT_Encode4(227743), // Rule ID 11866 //
85922 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
85923 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mops_wide),
85924 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
85925 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
85926 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
85927 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
85928 // MIs[0] tile
85929 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
85930 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
85931 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85932 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85933 // (intrinsic_void 819:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8bf16:{ *:[nxv8bf16] }:$Zn, nxv8bf16:{ *:[nxv8bf16] }:$Zm) => (BFMOPS_MPPZZ_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8bf16] }:$Zn, ?:{ *:[nxv8bf16] }:$Zm)
85934 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMOPS_MPPZZ_PSEUDO),
85935 GIR_RootToRootCopy, /*OpIdx*/1, // tile
85936 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
85937 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
85938 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
85939 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
85940 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85941 GIR_RootConstrainSelectedInstOperands,
85942 // GIR_Coverage, 11866,
85943 GIR_EraseRootFromParent_Done,
85944 // Label 4818: @227743
85945 GIM_Try, /*On fail goto*//*Label 4819*/ GIMT_Encode4(227803), // Rule ID 11867 //
85946 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
85947 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mops),
85948 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
85949 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
85950 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
85951 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
85952 // MIs[0] tile
85953 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
85954 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
85955 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85956 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85957 // (intrinsic_void 817:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv4i1] }:$Pn, PPR3bAny:{ *:[nxv4i1] }:$Pm, nxv4f32:{ *:[nxv4f32] }:$Zn, nxv4f32:{ *:[nxv4f32] }:$Zm) => (FMOPS_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv4i1] }:$Pn, ?:{ *:[nxv4i1] }:$Pm, ?:{ *:[nxv4f32] }:$Zn, ?:{ *:[nxv4f32] }:$Zm)
85958 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPS_MPPZZ_S_PSEUDO),
85959 GIR_RootToRootCopy, /*OpIdx*/1, // tile
85960 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
85961 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
85962 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
85963 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
85964 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85965 GIR_RootConstrainSelectedInstOperands,
85966 // GIR_Coverage, 11867,
85967 GIR_EraseRootFromParent_Done,
85968 // Label 4819: @227803
85969 GIM_Try, /*On fail goto*//*Label 4820*/ GIMT_Encode4(227863), // Rule ID 11868 //
85970 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF64F64),
85971 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mops),
85972 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
85973 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
85974 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
85975 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
85976 // MIs[0] tile
85977 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
85978 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
85979 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85980 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
85981 // (intrinsic_void 817:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv2i1] }:$Pn, PPR3bAny:{ *:[nxv2i1] }:$Pm, nxv2f64:{ *:[nxv2f64] }:$Zn, nxv2f64:{ *:[nxv2f64] }:$Zm) => (FMOPS_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv2i1] }:$Pn, ?:{ *:[nxv2i1] }:$Pm, ?:{ *:[nxv2f64] }:$Zn, ?:{ *:[nxv2f64] }:$Zm)
85982 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPS_MPPZZ_D_PSEUDO),
85983 GIR_RootToRootCopy, /*OpIdx*/1, // tile
85984 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
85985 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
85986 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
85987 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
85988 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
85989 GIR_RootConstrainSelectedInstOperands,
85990 // GIR_Coverage, 11868,
85991 GIR_EraseRootFromParent_Done,
85992 // Label 4820: @227863
85993 GIM_Try, /*On fail goto*//*Label 4821*/ GIMT_Encode4(227923), // Rule ID 11869 //
85994 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
85995 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mops_wide),
85996 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
85997 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
85998 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
85999 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
86000 // MIs[0] tile
86001 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86002 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
86003 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86004 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86005 // (intrinsic_void 819:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm) => (FMOPSL_MPPZZ_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
86006 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPSL_MPPZZ_PSEUDO),
86007 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86008 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86009 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86010 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86011 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86012 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86013 GIR_RootConstrainSelectedInstOperands,
86014 // GIR_Coverage, 11869,
86015 GIR_EraseRootFromParent_Done,
86016 // Label 4821: @227923
86017 GIM_Try, /*On fail goto*//*Label 4822*/ GIMT_Encode4(227983), // Rule ID 11870 //
86018 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
86019 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smops_wide),
86020 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
86021 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
86022 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
86023 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
86024 // MIs[0] tile
86025 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86026 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
86027 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86028 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86029 // (intrinsic_void 903:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm) => (SMOPS_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
86030 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOPS_MPPZZ_S_PSEUDO),
86031 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86032 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86033 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86034 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86035 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86036 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86037 GIR_RootConstrainSelectedInstOperands,
86038 // GIR_Coverage, 11870,
86039 GIR_EraseRootFromParent_Done,
86040 // Label 4822: @227983
86041 GIM_Try, /*On fail goto*//*Label 4823*/ GIMT_Encode4(228043), // Rule ID 11871 //
86042 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
86043 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umopa_wide),
86044 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
86045 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
86046 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
86047 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
86048 // MIs[0] tile
86049 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86050 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
86051 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86052 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86053 // (intrinsic_void 1002:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm) => (UMOPA_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
86054 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOPA_MPPZZ_S_PSEUDO),
86055 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86056 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86057 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86058 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86059 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86060 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86061 GIR_RootConstrainSelectedInstOperands,
86062 // GIR_Coverage, 11871,
86063 GIR_EraseRootFromParent_Done,
86064 // Label 4823: @228043
86065 GIM_Try, /*On fail goto*//*Label 4824*/ GIMT_Encode4(228103), // Rule ID 11872 //
86066 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
86067 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umops_wide),
86068 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
86069 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
86070 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
86071 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
86072 // MIs[0] tile
86073 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86074 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
86075 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86076 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86077 // (intrinsic_void 1004:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm) => (UMOPS_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
86078 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOPS_MPPZZ_S_PSEUDO),
86079 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86080 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86081 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86082 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86083 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86084 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86085 GIR_RootConstrainSelectedInstOperands,
86086 // GIR_Coverage, 11872,
86087 GIR_EraseRootFromParent_Done,
86088 // Label 4824: @228103
86089 GIM_Try, /*On fail goto*//*Label 4825*/ GIMT_Encode4(228163), // Rule ID 11873 //
86090 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
86091 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumopa_wide),
86092 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
86093 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
86094 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
86095 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
86096 // MIs[0] tile
86097 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86098 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
86099 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86100 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86101 // (intrinsic_void 936:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm) => (SUMOPA_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
86102 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOPA_MPPZZ_S_PSEUDO),
86103 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86104 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86105 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86106 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86107 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86108 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86109 GIR_RootConstrainSelectedInstOperands,
86110 // GIR_Coverage, 11873,
86111 GIR_EraseRootFromParent_Done,
86112 // Label 4825: @228163
86113 GIM_Try, /*On fail goto*//*Label 4826*/ GIMT_Encode4(228223), // Rule ID 11874 //
86114 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
86115 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumops_wide),
86116 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
86117 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
86118 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
86119 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
86120 // MIs[0] tile
86121 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86122 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
86123 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86124 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86125 // (intrinsic_void 937:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm) => (SUMOPS_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
86126 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOPS_MPPZZ_S_PSEUDO),
86127 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86128 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86129 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86130 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86131 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86132 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86133 GIR_RootConstrainSelectedInstOperands,
86134 // GIR_Coverage, 11874,
86135 GIR_EraseRootFromParent_Done,
86136 // Label 4826: @228223
86137 GIM_Try, /*On fail goto*//*Label 4827*/ GIMT_Encode4(228283), // Rule ID 11875 //
86138 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
86139 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmopa_wide),
86140 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
86141 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
86142 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
86143 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
86144 // MIs[0] tile
86145 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86146 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
86147 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86148 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86149 // (intrinsic_void 1020:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm) => (USMOPA_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
86150 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOPA_MPPZZ_S_PSEUDO),
86151 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86152 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86153 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86154 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86155 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86156 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86157 GIR_RootConstrainSelectedInstOperands,
86158 // GIR_Coverage, 11875,
86159 GIR_EraseRootFromParent_Done,
86160 // Label 4827: @228283
86161 GIM_Try, /*On fail goto*//*Label 4828*/ GIMT_Encode4(228343), // Rule ID 11876 //
86162 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
86163 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmops_wide),
86164 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
86165 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
86166 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
86167 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
86168 // MIs[0] tile
86169 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86170 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
86171 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86172 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86173 // (intrinsic_void 1021:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm) => (USMOPS_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
86174 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOPS_MPPZZ_S_PSEUDO),
86175 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86176 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86177 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86178 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86179 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86180 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86181 GIR_RootConstrainSelectedInstOperands,
86182 // GIR_Coverage, 11876,
86183 GIR_EraseRootFromParent_Done,
86184 // Label 4828: @228343
86185 GIM_Try, /*On fail goto*//*Label 4829*/ GIMT_Encode4(228403), // Rule ID 11877 //
86186 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
86187 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smops_wide),
86188 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
86189 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
86190 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
86191 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
86192 // MIs[0] tile
86193 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86194 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
86195 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86196 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86197 // (intrinsic_void 903:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm) => (SMOPS_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
86198 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOPS_MPPZZ_D_PSEUDO),
86199 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86200 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86201 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86202 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86203 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86204 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86205 GIR_RootConstrainSelectedInstOperands,
86206 // GIR_Coverage, 11877,
86207 GIR_EraseRootFromParent_Done,
86208 // Label 4829: @228403
86209 GIM_Try, /*On fail goto*//*Label 4830*/ GIMT_Encode4(228463), // Rule ID 11878 //
86210 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
86211 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umopa_wide),
86212 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
86213 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
86214 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
86215 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
86216 // MIs[0] tile
86217 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86218 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
86219 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86220 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86221 // (intrinsic_void 1002:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm) => (UMOPA_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
86222 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOPA_MPPZZ_D_PSEUDO),
86223 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86224 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86225 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86226 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86227 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86228 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86229 GIR_RootConstrainSelectedInstOperands,
86230 // GIR_Coverage, 11878,
86231 GIR_EraseRootFromParent_Done,
86232 // Label 4830: @228463
86233 GIM_Try, /*On fail goto*//*Label 4831*/ GIMT_Encode4(228523), // Rule ID 11879 //
86234 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
86235 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umops_wide),
86236 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
86237 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
86238 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
86239 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
86240 // MIs[0] tile
86241 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86242 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
86243 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86244 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86245 // (intrinsic_void 1004:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm) => (UMOPS_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
86246 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOPS_MPPZZ_D_PSEUDO),
86247 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86248 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86249 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86250 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86251 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86252 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86253 GIR_RootConstrainSelectedInstOperands,
86254 // GIR_Coverage, 11879,
86255 GIR_EraseRootFromParent_Done,
86256 // Label 4831: @228523
86257 GIM_Try, /*On fail goto*//*Label 4832*/ GIMT_Encode4(228583), // Rule ID 11880 //
86258 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
86259 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumopa_wide),
86260 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
86261 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
86262 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
86263 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
86264 // MIs[0] tile
86265 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86266 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
86267 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86268 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86269 // (intrinsic_void 936:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm) => (SUMOPA_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
86270 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOPA_MPPZZ_D_PSEUDO),
86271 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86272 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86273 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86274 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86275 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86276 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86277 GIR_RootConstrainSelectedInstOperands,
86278 // GIR_Coverage, 11880,
86279 GIR_EraseRootFromParent_Done,
86280 // Label 4832: @228583
86281 GIM_Try, /*On fail goto*//*Label 4833*/ GIMT_Encode4(228643), // Rule ID 11881 //
86282 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
86283 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumops_wide),
86284 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
86285 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
86286 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
86287 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
86288 // MIs[0] tile
86289 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86290 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
86291 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86292 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86293 // (intrinsic_void 937:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm) => (SUMOPS_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
86294 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOPS_MPPZZ_D_PSEUDO),
86295 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86296 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86297 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86298 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86299 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86300 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86301 GIR_RootConstrainSelectedInstOperands,
86302 // GIR_Coverage, 11881,
86303 GIR_EraseRootFromParent_Done,
86304 // Label 4833: @228643
86305 GIM_Try, /*On fail goto*//*Label 4834*/ GIMT_Encode4(228703), // Rule ID 11882 //
86306 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
86307 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmopa_wide),
86308 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
86309 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
86310 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
86311 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
86312 // MIs[0] tile
86313 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86314 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
86315 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86316 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86317 // (intrinsic_void 1020:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm) => (USMOPA_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
86318 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOPA_MPPZZ_D_PSEUDO),
86319 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86320 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86321 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86322 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86323 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86324 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86325 GIR_RootConstrainSelectedInstOperands,
86326 // GIR_Coverage, 11882,
86327 GIR_EraseRootFromParent_Done,
86328 // Label 4834: @228703
86329 GIM_Try, /*On fail goto*//*Label 4835*/ GIMT_Encode4(228763), // Rule ID 11883 //
86330 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
86331 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmops_wide),
86332 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
86333 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
86334 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
86335 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
86336 // MIs[0] tile
86337 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86338 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
86339 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86340 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86341 // (intrinsic_void 1021:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm) => (USMOPS_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
86342 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOPS_MPPZZ_D_PSEUDO),
86343 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86344 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86345 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86346 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86347 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86348 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86349 GIR_RootConstrainSelectedInstOperands,
86350 // GIR_Coverage, 11883,
86351 GIR_EraseRootFromParent_Done,
86352 // Label 4835: @228763
86353 GIM_Try, /*On fail goto*//*Label 4836*/ GIMT_Encode4(228823), // Rule ID 12220 //
86354 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME2),
86355 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_bmops_za32),
86356 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
86357 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
86358 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
86359 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
86360 // MIs[0] tile
86361 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86362 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
86363 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86364 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86365 // (intrinsic_void 755:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv4i1] }:$Pn, PPR3bAny:{ *:[nxv4i1] }:$Pm, nxv4i32:{ *:[nxv4i32] }:$Zn, nxv4i32:{ *:[nxv4i32] }:$Zm) => (BMOPS_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv4i1] }:$Pn, ?:{ *:[nxv4i1] }:$Pm, ?:{ *:[nxv4i32] }:$Zn, ?:{ *:[nxv4i32] }:$Zm)
86366 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BMOPS_MPPZZ_S_PSEUDO),
86367 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86368 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86369 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86370 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86371 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86372 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86373 GIR_RootConstrainSelectedInstOperands,
86374 // GIR_Coverage, 12220,
86375 GIR_EraseRootFromParent_Done,
86376 // Label 4836: @228823
86377 GIM_Try, /*On fail goto*//*Label 4837*/ GIMT_Encode4(228883), // Rule ID 12221 //
86378 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME2),
86379 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smops_za32),
86380 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
86381 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
86382 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
86383 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
86384 // MIs[0] tile
86385 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86386 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
86387 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86388 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86389 // (intrinsic_void 904:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm) => (SMOPS_MPPZZ_HtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
86390 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOPS_MPPZZ_HtoS_PSEUDO),
86391 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86392 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86393 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86394 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86395 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86396 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86397 GIR_RootConstrainSelectedInstOperands,
86398 // GIR_Coverage, 12221,
86399 GIR_EraseRootFromParent_Done,
86400 // Label 4837: @228883
86401 GIM_Try, /*On fail goto*//*Label 4838*/ GIMT_Encode4(228943), // Rule ID 12222 //
86402 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME2),
86403 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umopa_za32),
86404 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
86405 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
86406 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
86407 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
86408 // MIs[0] tile
86409 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86410 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
86411 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86412 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86413 // (intrinsic_void 1003:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm) => (UMOPA_MPPZZ_HtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
86414 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOPA_MPPZZ_HtoS_PSEUDO),
86415 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86416 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86417 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86418 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86419 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86420 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86421 GIR_RootConstrainSelectedInstOperands,
86422 // GIR_Coverage, 12222,
86423 GIR_EraseRootFromParent_Done,
86424 // Label 4838: @228943
86425 GIM_Try, /*On fail goto*//*Label 4839*/ GIMT_Encode4(229003), // Rule ID 12223 //
86426 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME2),
86427 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umops_za32),
86428 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
86429 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
86430 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
86431 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
86432 // MIs[0] tile
86433 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86434 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
86435 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86436 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86437 // (intrinsic_void 1005:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm) => (UMOPS_MPPZZ_HtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
86438 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOPS_MPPZZ_HtoS_PSEUDO),
86439 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86440 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86441 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86442 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86443 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86444 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86445 GIR_RootConstrainSelectedInstOperands,
86446 // GIR_Coverage, 12223,
86447 GIR_EraseRootFromParent_Done,
86448 // Label 4839: @229003
86449 GIM_Try, /*On fail goto*//*Label 4840*/ GIMT_Encode4(229063), // Rule ID 12336 //
86450 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF16F16orSMEF8F16),
86451 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mops),
86452 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
86453 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
86454 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
86455 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
86456 // MIs[0] tile
86457 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86458 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
86459 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86460 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86461 // (intrinsic_void 817:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm) => (FMOPS_MPPZZ_H_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
86462 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPS_MPPZZ_H_PSEUDO),
86463 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86464 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86465 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86466 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86467 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86468 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86469 GIR_RootConstrainSelectedInstOperands,
86470 // GIR_Coverage, 12336,
86471 GIR_EraseRootFromParent_Done,
86472 // Label 4840: @229063
86473 GIM_Try, /*On fail goto*//*Label 4841*/ GIMT_Encode4(229123), // Rule ID 12353 //
86474 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasB16B16_HasSME2),
86475 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mopa),
86476 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
86477 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
86478 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
86479 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
86480 // MIs[0] tile
86481 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86482 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
86483 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86484 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86485 // (intrinsic_void 814:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8bf16:{ *:[nxv8bf16] }:$Zn, nxv8bf16:{ *:[nxv8bf16] }:$Zm) => (BFMOPA_MPPZZ_H_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8bf16] }:$Zn, ?:{ *:[nxv8bf16] }:$Zm)
86486 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMOPA_MPPZZ_H_PSEUDO),
86487 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86488 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86489 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86490 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86491 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86492 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86493 GIR_RootConstrainSelectedInstOperands,
86494 // GIR_Coverage, 12353,
86495 GIR_EraseRootFromParent_Done,
86496 // Label 4841: @229123
86497 GIM_Try, /*On fail goto*//*Label 4842*/ GIMT_Encode4(229183), // Rule ID 12354 //
86498 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasB16B16_HasSME2),
86499 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mops),
86500 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
86501 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
86502 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
86503 GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
86504 // MIs[0] tile
86505 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
86506 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
86507 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86508 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
86509 // (intrinsic_void 817:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8bf16:{ *:[nxv8bf16] }:$Zn, nxv8bf16:{ *:[nxv8bf16] }:$Zm) => (BFMOPS_MPPZZ_H_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8bf16] }:$Zn, ?:{ *:[nxv8bf16] }:$Zm)
86510 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMOPS_MPPZZ_H_PSEUDO),
86511 GIR_RootToRootCopy, /*OpIdx*/1, // tile
86512 GIR_RootToRootCopy, /*OpIdx*/2, // Pn
86513 GIR_RootToRootCopy, /*OpIdx*/3, // Pm
86514 GIR_RootToRootCopy, /*OpIdx*/4, // Zn
86515 GIR_RootToRootCopy, /*OpIdx*/5, // Zm
86516 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
86517 GIR_RootConstrainSelectedInstOperands,
86518 // GIR_Coverage, 12354,
86519 GIR_EraseRootFromParent_Done,
86520 // Label 4842: @229183
86521 GIM_Reject,
86522 // Label 4808: @229184
86523 GIM_Reject,
86524 // Label 34: @229185
86525 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(11), /*)*//*default:*//*Label 4847*/ GIMT_Encode4(229474),
86526 /*GILLT_s64*//*Label 4843*/ GIMT_Encode4(229228), GIMT_Encode4(0), GIMT_Encode4(0),
86527 /*GILLT_v2s64*//*Label 4844*/ GIMT_Encode4(229288), GIMT_Encode4(0),
86528 /*GILLT_v4s32*//*Label 4845*/ GIMT_Encode4(229350), GIMT_Encode4(0),
86529 /*GILLT_v8s16*//*Label 4846*/ GIMT_Encode4(229412),
86530 // Label 4843: @229228
86531 GIM_Try, /*On fail goto*//*Label 4848*/ GIMT_Encode4(229287), // Rule ID 6100 //
86532 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
86533 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
86534 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
86535 // (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] })
86536 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
86537 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
86538 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
86539 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
86540 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
86541 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
86542 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
86543 GIR_RootToRootCopy, /*OpIdx*/1, // src
86544 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
86545 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
86546 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
86547 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
86548 // GIR_Coverage, 6100,
86549 GIR_EraseRootFromParent_Done,
86550 // Label 4848: @229287
86551 GIM_Reject,
86552 // Label 4844: @229288
86553 GIM_Try, /*On fail goto*//*Label 4849*/ GIMT_Encode4(229349),
86554 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
86555 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86556 GIM_Try, /*On fail goto*//*Label 4850*/ GIMT_Encode4(229327), // Rule ID 5959 //
86557 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
86558 // (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)) => (USHLLv4i32_shift:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i32] })
86559 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv4i32_shift),
86560 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
86561 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
86562 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
86563 GIR_RootConstrainSelectedInstOperands,
86564 // GIR_Coverage, 5959,
86565 GIR_EraseRootFromParent_Done,
86566 // Label 4850: @229327
86567 GIM_Try, /*On fail goto*//*Label 4851*/ GIMT_Encode4(229348), // Rule ID 5950 //
86568 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
86569 // (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn) => (USHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] })
86570 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv2i32_shift),
86571 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
86572 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
86573 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
86574 GIR_RootConstrainSelectedInstOperands,
86575 // GIR_Coverage, 5950,
86576 GIR_EraseRootFromParent_Done,
86577 // Label 4851: @229348
86578 GIM_Reject,
86579 // Label 4849: @229349
86580 GIM_Reject,
86581 // Label 4845: @229350
86582 GIM_Try, /*On fail goto*//*Label 4852*/ GIMT_Encode4(229411),
86583 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
86584 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86585 GIM_Try, /*On fail goto*//*Label 4853*/ GIMT_Encode4(229389), // Rule ID 5956 //
86586 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
86587 // (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)) => (USHLLv8i16_shift:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, 0:{ *:[i32] })
86588 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv8i16_shift),
86589 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
86590 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
86591 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
86592 GIR_RootConstrainSelectedInstOperands,
86593 // GIR_Coverage, 5956,
86594 GIR_EraseRootFromParent_Done,
86595 // Label 4853: @229389
86596 GIM_Try, /*On fail goto*//*Label 4854*/ GIMT_Encode4(229410), // Rule ID 5947 //
86597 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
86598 // (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn) => (USHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] })
86599 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv4i16_shift),
86600 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
86601 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
86602 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
86603 GIR_RootConstrainSelectedInstOperands,
86604 // GIR_Coverage, 5947,
86605 GIR_EraseRootFromParent_Done,
86606 // Label 4854: @229410
86607 GIM_Reject,
86608 // Label 4852: @229411
86609 GIM_Reject,
86610 // Label 4846: @229412
86611 GIM_Try, /*On fail goto*//*Label 4855*/ GIMT_Encode4(229473),
86612 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
86613 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86614 GIM_Try, /*On fail goto*//*Label 4856*/ GIMT_Encode4(229451), // Rule ID 5953 //
86615 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
86616 // (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)) => (USHLLv16i8_shift:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, 0:{ *:[i32] })
86617 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv16i8_shift),
86618 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
86619 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
86620 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
86621 GIR_RootConstrainSelectedInstOperands,
86622 // GIR_Coverage, 5953,
86623 GIR_EraseRootFromParent_Done,
86624 // Label 4856: @229451
86625 GIM_Try, /*On fail goto*//*Label 4857*/ GIMT_Encode4(229472), // Rule ID 5944 //
86626 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
86627 // (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn) => (USHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] })
86628 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv8i8_shift),
86629 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
86630 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
86631 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
86632 GIR_RootConstrainSelectedInstOperands,
86633 // GIR_Coverage, 5944,
86634 GIR_EraseRootFromParent_Done,
86635 // Label 4857: @229472
86636 GIM_Reject,
86637 // Label 4855: @229473
86638 GIM_Reject,
86639 // Label 4847: @229474
86640 GIM_Reject,
86641 // Label 35: @229475
86642 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(10), /*)*//*default:*//*Label 4862*/ GIMT_Encode4(230677),
86643 /*GILLT_s32*//*Label 4858*/ GIMT_Encode4(229518), GIMT_Encode4(0), GIMT_Encode4(0),
86644 /*GILLT_v2s32*//*Label 4859*/ GIMT_Encode4(229557), GIMT_Encode4(0),
86645 /*GILLT_v4s16*//*Label 4860*/ GIMT_Encode4(229835), GIMT_Encode4(0),
86646 /*GILLT_v8s8*//*Label 4861*/ GIMT_Encode4(230256),
86647 // Label 4858: @229518
86648 GIM_Try, /*On fail goto*//*Label 4863*/ GIMT_Encode4(229556), // Rule ID 6121 //
86649 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
86650 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
86651 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
86652 // (trunc:{ *:[i32] } GPR64sp:{ *:[i64] }:$src) => (EXTRACT_SUBREG:{ *:[i32] } GPR64sp:{ *:[i64] }:$src, sub_32:{ *:[i32] })
86653 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
86654 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
86655 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(16), // src
86656 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32spRegClassID),
86657 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64spRegClassID),
86658 // GIR_Coverage, 6121,
86659 GIR_EraseRootFromParent_Done,
86660 // Label 4863: @229556
86661 GIM_Reject,
86662 // Label 4859: @229557
86663 GIM_Try, /*On fail goto*//*Label 4864*/ GIMT_Encode4(229834),
86664 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
86665 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
86666 GIM_Try, /*On fail goto*//*Label 4865*/ GIMT_Encode4(229640), // Rule ID 5065 //
86667 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
86668 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
86669 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
86670 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
86671 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ADD),
86672 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
86673 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
86674 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86675 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86676 // MIs[1] Operand 2
86677 GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(32),
86678 GIM_CheckIsSafeToFold, /*NumInsns*/2,
86679 // (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] })) => (ADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
86680 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv2i64_v2i32),
86681 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
86682 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
86683 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
86684 GIR_RootConstrainSelectedInstOperands,
86685 // GIR_Coverage, 5065,
86686 GIR_EraseRootFromParent_Done,
86687 // Label 4865: @229640
86688 GIM_Try, /*On fail goto*//*Label 4866*/ GIMT_Encode4(229711), // Rule ID 5071 //
86689 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
86690 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
86691 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
86692 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
86693 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB),
86694 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
86695 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
86696 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86697 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86698 // MIs[1] Operand 2
86699 GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(32),
86700 GIM_CheckIsSafeToFold, /*NumInsns*/2,
86701 // (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] })) => (SUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
86702 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv2i64_v2i32),
86703 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
86704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
86705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
86706 GIR_RootConstrainSelectedInstOperands,
86707 // GIR_Coverage, 5071,
86708 GIR_EraseRootFromParent_Done,
86709 // Label 4866: @229711
86710 GIM_Try, /*On fail goto*//*Label 4867*/ GIMT_Encode4(229764), // Rule ID 2147 //
86711 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
86712 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
86713 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
86714 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
86715 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86716 // MIs[1] imm
86717 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
86718 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
86719 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
86720 // MIs[2] Operand 1
86721 // No operand predicates
86722 GIM_CheckIsSafeToFold, /*NumInsns*/2,
86723 // (trunc:{ *:[v2i32] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)) => (SHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
86724 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv2i32_shift),
86725 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
86726 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
86727 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
86728 GIR_RootConstrainSelectedInstOperands,
86729 // GIR_Coverage, 2147,
86730 GIR_EraseRootFromParent_Done,
86731 // Label 4867: @229764
86732 GIM_Try, /*On fail goto*//*Label 4868*/ GIMT_Encode4(229814), // Rule ID 5938 //
86733 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
86734 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
86735 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
86736 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86737 // MIs[1] imm
86738 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
86739 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
86740 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
86741 // MIs[2] Operand 1
86742 // No operand predicates
86743 GIM_CheckIsSafeToFold, /*NumInsns*/2,
86744 // (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)) => (SHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
86745 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv2i32_shift),
86746 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
86747 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
86748 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
86749 GIR_RootConstrainSelectedInstOperands,
86750 // GIR_Coverage, 5938,
86751 GIR_EraseRootFromParent_Done,
86752 // Label 4868: @229814
86753 GIM_Try, /*On fail goto*//*Label 4869*/ GIMT_Encode4(229833), // Rule ID 1086 //
86754 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
86755 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86756 // (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn) => (XTNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn)
86757 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::XTNv2i32),
86758 GIR_RootConstrainSelectedInstOperands,
86759 // GIR_Coverage, 1086,
86760 GIR_Done,
86761 // Label 4869: @229833
86762 GIM_Reject,
86763 // Label 4864: @229834
86764 GIM_Reject,
86765 // Label 4860: @229835
86766 GIM_Try, /*On fail goto*//*Label 4870*/ GIMT_Encode4(230255),
86767 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
86768 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
86769 GIM_Try, /*On fail goto*//*Label 4871*/ GIMT_Encode4(229918), // Rule ID 5064 //
86770 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
86771 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
86772 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
86773 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
86774 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ADD),
86775 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
86776 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
86777 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86778 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86779 // MIs[1] Operand 2
86780 GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
86781 GIM_CheckIsSafeToFold, /*NumInsns*/2,
86782 // (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] })) => (ADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
86783 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv4i32_v4i16),
86784 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
86785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
86786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
86787 GIR_RootConstrainSelectedInstOperands,
86788 // GIR_Coverage, 5064,
86789 GIR_EraseRootFromParent_Done,
86790 // Label 4871: @229918
86791 GIM_Try, /*On fail goto*//*Label 4872*/ GIMT_Encode4(229989), // Rule ID 5070 //
86792 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
86793 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
86794 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
86795 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
86796 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB),
86797 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
86798 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
86799 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86800 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86801 // MIs[1] Operand 2
86802 GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
86803 GIM_CheckIsSafeToFold, /*NumInsns*/2,
86804 // (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] })) => (SUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
86805 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv4i32_v4i16),
86806 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
86807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
86808 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
86809 GIR_RootConstrainSelectedInstOperands,
86810 // GIR_Coverage, 5070,
86811 GIR_EraseRootFromParent_Done,
86812 // Label 4872: @229989
86813 GIM_Try, /*On fail goto*//*Label 4873*/ GIMT_Encode4(230081), // Rule ID 5204 //
86814 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
86815 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONCAT_VECTORS),
86816 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
86817 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
86818 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
86819 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
86820 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
86821 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
86822 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86823 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
86824 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC),
86825 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
86826 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86827 GIM_CheckIsSafeToFold, /*NumInsns*/3,
86828 // (trunc:{ *:[v4i16] } (concat_vectors:{ *:[v4i32] } (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Vn), (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Vm))) => (XTNv4i16:{ *:[v4i16] } (UZP1v4i32:{ *:[f128] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm))
86829 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
86830 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i32),
86831 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
86832 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Vn
86833 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, // Vm
86834 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
86835 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XTNv4i16),
86836 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
86837 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
86838 GIR_RootConstrainSelectedInstOperands,
86839 // GIR_Coverage, 5204,
86840 GIR_EraseRootFromParent_Done,
86841 // Label 4873: @230081
86842 GIM_Try, /*On fail goto*//*Label 4874*/ GIMT_Encode4(230134), // Rule ID 2146 //
86843 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
86844 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
86845 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
86846 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
86847 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86848 // MIs[1] imm
86849 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
86850 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
86851 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
86852 // MIs[2] Operand 1
86853 // No operand predicates
86854 GIM_CheckIsSafeToFold, /*NumInsns*/2,
86855 // (trunc:{ *:[v4i16] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)) => (SHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
86856 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv4i16_shift),
86857 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
86858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
86859 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
86860 GIR_RootConstrainSelectedInstOperands,
86861 // GIR_Coverage, 2146,
86862 GIR_EraseRootFromParent_Done,
86863 // Label 4874: @230134
86864 GIM_Try, /*On fail goto*//*Label 4875*/ GIMT_Encode4(230184), // Rule ID 5937 //
86865 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
86866 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
86867 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
86868 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86869 // MIs[1] imm
86870 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
86871 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
86872 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
86873 // MIs[2] Operand 1
86874 // No operand predicates
86875 GIM_CheckIsSafeToFold, /*NumInsns*/2,
86876 // (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)) => (SHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
86877 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv4i16_shift),
86878 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
86879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
86880 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
86881 GIR_RootConstrainSelectedInstOperands,
86882 // GIR_Coverage, 5937,
86883 GIR_EraseRootFromParent_Done,
86884 // Label 4875: @230184
86885 GIM_Try, /*On fail goto*//*Label 4876*/ GIMT_Encode4(230235), // Rule ID 5232 //
86886 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
86887 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONCAT_VECTORS),
86888 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
86889 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
86890 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
86891 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
86892 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
86893 GIM_CheckIsSafeToFold, /*NumInsns*/1,
86894 // (trunc:{ *:[v4i16] } (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Vn, V64:{ *:[v2i32] }:$Vm)) => (UZP1v4i16:{ *:[v4i16] } V64:{ *:[v2i32] }:$Vn, V64:{ *:[v2i32] }:$Vm)
86895 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i16),
86896 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
86897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
86898 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
86899 GIR_RootConstrainSelectedInstOperands,
86900 // GIR_Coverage, 5232,
86901 GIR_EraseRootFromParent_Done,
86902 // Label 4876: @230235
86903 GIM_Try, /*On fail goto*//*Label 4877*/ GIMT_Encode4(230254), // Rule ID 1085 //
86904 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
86905 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86906 // (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn) => (XTNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn)
86907 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::XTNv4i16),
86908 GIR_RootConstrainSelectedInstOperands,
86909 // GIR_Coverage, 1085,
86910 GIR_Done,
86911 // Label 4877: @230254
86912 GIM_Reject,
86913 // Label 4870: @230255
86914 GIM_Reject,
86915 // Label 4861: @230256
86916 GIM_Try, /*On fail goto*//*Label 4878*/ GIMT_Encode4(230676),
86917 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
86918 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
86919 GIM_Try, /*On fail goto*//*Label 4879*/ GIMT_Encode4(230339), // Rule ID 5063 //
86920 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
86921 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
86922 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
86923 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
86924 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ADD),
86925 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
86926 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
86927 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86928 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86929 // MIs[1] Operand 2
86930 GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
86931 GIM_CheckIsSafeToFold, /*NumInsns*/2,
86932 // (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] })) => (ADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
86933 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv8i16_v8i8),
86934 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
86935 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
86936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
86937 GIR_RootConstrainSelectedInstOperands,
86938 // GIR_Coverage, 5063,
86939 GIR_EraseRootFromParent_Done,
86940 // Label 4879: @230339
86941 GIM_Try, /*On fail goto*//*Label 4880*/ GIMT_Encode4(230410), // Rule ID 5069 //
86942 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
86943 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
86944 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
86945 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
86946 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB),
86947 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
86948 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
86949 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86950 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86951 // MIs[1] Operand 2
86952 GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
86953 GIM_CheckIsSafeToFold, /*NumInsns*/2,
86954 // (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] })) => (SUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
86955 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv8i16_v8i8),
86956 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
86957 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
86958 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
86959 GIR_RootConstrainSelectedInstOperands,
86960 // GIR_Coverage, 5069,
86961 GIR_EraseRootFromParent_Done,
86962 // Label 4880: @230410
86963 GIM_Try, /*On fail goto*//*Label 4881*/ GIMT_Encode4(230502), // Rule ID 5177 //
86964 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
86965 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONCAT_VECTORS),
86966 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
86967 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
86968 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
86969 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
86970 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
86971 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
86972 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86973 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
86974 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC),
86975 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
86976 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86977 GIM_CheckIsSafeToFold, /*NumInsns*/3,
86978 // (trunc:{ *:[v8i8] } (concat_vectors:{ *:[v8i16] } (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Vn), (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Vm))) => (XTNv8i8:{ *:[v8i8] } (UZP1v8i16:{ *:[f128] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm))
86979 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
86980 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UZP1v8i16),
86981 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
86982 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Vn
86983 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, // Vm
86984 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
86985 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XTNv8i8),
86986 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
86987 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
86988 GIR_RootConstrainSelectedInstOperands,
86989 // GIR_Coverage, 5177,
86990 GIR_EraseRootFromParent_Done,
86991 // Label 4881: @230502
86992 GIM_Try, /*On fail goto*//*Label 4882*/ GIMT_Encode4(230555), // Rule ID 2145 //
86993 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
86994 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
86995 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
86996 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
86997 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
86998 // MIs[1] imm
86999 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
87000 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
87001 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
87002 // MIs[2] Operand 1
87003 // No operand predicates
87004 GIM_CheckIsSafeToFold, /*NumInsns*/2,
87005 // (trunc:{ *:[v8i8] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)) => (SHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
87006 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv8i8_shift),
87007 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
87009 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
87010 GIR_RootConstrainSelectedInstOperands,
87011 // GIR_Coverage, 2145,
87012 GIR_EraseRootFromParent_Done,
87013 // Label 4882: @230555
87014 GIM_Try, /*On fail goto*//*Label 4883*/ GIMT_Encode4(230605), // Rule ID 5936 //
87015 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
87016 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
87017 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
87018 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
87019 // MIs[1] imm
87020 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
87021 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
87022 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
87023 // MIs[2] Operand 1
87024 // No operand predicates
87025 GIM_CheckIsSafeToFold, /*NumInsns*/2,
87026 // (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)) => (SHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
87027 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv8i8_shift),
87028 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
87030 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
87031 GIR_RootConstrainSelectedInstOperands,
87032 // GIR_Coverage, 5936,
87033 GIR_EraseRootFromParent_Done,
87034 // Label 4883: @230605
87035 GIM_Try, /*On fail goto*//*Label 4884*/ GIMT_Encode4(230656), // Rule ID 5231 //
87036 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
87037 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONCAT_VECTORS),
87038 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
87039 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
87040 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
87041 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
87042 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
87043 GIM_CheckIsSafeToFold, /*NumInsns*/1,
87044 // (trunc:{ *:[v8i8] } (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Vn, V64:{ *:[v4i16] }:$Vm)) => (UZP1v8i8:{ *:[v8i8] } V64:{ *:[v4i16] }:$Vn, V64:{ *:[v4i16] }:$Vm)
87045 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1v8i8),
87046 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
87048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
87049 GIR_RootConstrainSelectedInstOperands,
87050 // GIR_Coverage, 5231,
87051 GIR_EraseRootFromParent_Done,
87052 // Label 4884: @230656
87053 GIM_Try, /*On fail goto*//*Label 4885*/ GIMT_Encode4(230675), // Rule ID 1084 //
87054 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
87055 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
87056 // (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn) => (XTNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn)
87057 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::XTNv8i8),
87058 GIR_RootConstrainSelectedInstOperands,
87059 // GIR_Coverage, 1084,
87060 GIR_Done,
87061 // Label 4885: @230675
87062 GIM_Reject,
87063 // Label 4878: @230676
87064 GIM_Reject,
87065 // Label 4862: @230677
87066 GIM_Reject,
87067 // Label 36: @230678
87068 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 4888*/ GIMT_Encode4(230797),
87069 /*GILLT_s32*//*Label 4886*/ GIMT_Encode4(230697),
87070 /*GILLT_s64*//*Label 4887*/ GIMT_Encode4(230717),
87071 // Label 4886: @230697
87072 GIM_Try, /*On fail goto*//*Label 4889*/ GIMT_Encode4(230716), // Rule ID 92 //
87073 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
87074 // MIs[0] Operand 1
87075 // No operand predicates
87076 // (imm:{ *:[i32] }):$src => (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
87077 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
87078 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
87079 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
87080 GIR_RootConstrainSelectedInstOperands,
87081 // GIR_Coverage, 92,
87082 GIR_EraseRootFromParent_Done,
87083 // Label 4889: @230716
87084 GIM_Reject,
87085 // Label 4887: @230717
87086 GIM_Try, /*On fail goto*//*Label 4890*/ GIMT_Encode4(230777), // Rule ID 3774 //
87087 GIM_CheckFeatures, GIMT_Encode2(GIFBS_OptimizedGISelOrOtherSelector),
87088 GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i64imm_32bit),
87089 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
87090 // MIs[0] Operand 1
87091 // No operand predicates
87092 // (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$src => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$src)), sub_32:{ *:[i32] })
87093 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
87094 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
87095 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87096 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // src
87097 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
87098 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
87099 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
87100 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87101 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
87102 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
87103 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
87104 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
87105 // GIR_Coverage, 3774,
87106 GIR_EraseRootFromParent_Done,
87107 // Label 4890: @230777
87108 GIM_Try, /*On fail goto*//*Label 4891*/ GIMT_Encode4(230796), // Rule ID 93 //
87109 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
87110 // MIs[0] Operand 1
87111 // No operand predicates
87112 // (imm:{ *:[i64] }):$src => (MOVi64imm:{ *:[i64] } (imm:{ *:[i64] }):$src)
87113 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MOVi64imm),
87114 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
87115 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
87116 GIR_RootConstrainSelectedInstOperands,
87117 // GIR_Coverage, 93,
87118 GIR_EraseRootFromParent_Done,
87119 // Label 4891: @230796
87120 GIM_Reject,
87121 // Label 4888: @230797
87122 GIM_Reject,
87123 // Label 37: @230798
87124 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 4895*/ GIMT_Encode4(231086),
87125 /*GILLT_s16*//*Label 4892*/ GIMT_Encode4(230821),
87126 /*GILLT_s32*//*Label 4893*/ GIMT_Encode4(230921),
87127 /*GILLT_s64*//*Label 4894*/ GIMT_Encode4(231034),
87128 // Label 4892: @230821
87129 GIM_Try, /*On fail goto*//*Label 4896*/ GIMT_Encode4(230844), // Rule ID 500 //
87130 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
87131 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
87132 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
87133 // MIs[0] Operand 1
87134 // No operand predicates
87135 // (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>> => (FMOVH0:{ *:[f16] })
87136 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVH0),
87137 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87138 GIR_RootConstrainSelectedInstOperands,
87139 // GIR_Coverage, 500,
87140 GIR_EraseRootFromParent_Done,
87141 // Label 4896: @230844
87142 GIM_Try, /*On fail goto*//*Label 4897*/ GIMT_Encode4(230872), // Rule ID 682 //
87143 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
87144 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm16),
87145 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
87146 // MIs[0] Operand 1
87147 // No operand predicates
87148 // (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>><<X:fpimm16XForm>>:$imm => (FMOVHi:{ *:[f16] } (fpimm16XForm:{ *:[f16] } (fpimm:{ *:[f16] }):$imm))
87149 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVHi),
87150 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87151 GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFPImm16), // imm
87152 GIR_RootConstrainSelectedInstOperands,
87153 // GIR_Coverage, 682,
87154 GIR_EraseRootFromParent_Done,
87155 // Label 4897: @230872
87156 GIM_Try, /*On fail goto*//*Label 4898*/ GIMT_Encode4(230892), // Rule ID 4458 //
87157 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
87158 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
87159 // MIs[0] Operand 1
87160 // No operand predicates
87161 // (fpimm:{ *:[bf16] })<<P:Predicate_fpimm0>> => (FMOVH0:{ *:[bf16] })
87162 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVH0),
87163 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87164 GIR_RootConstrainSelectedInstOperands,
87165 // GIR_Coverage, 4458,
87166 GIR_EraseRootFromParent_Done,
87167 // Label 4898: @230892
87168 GIM_Try, /*On fail goto*//*Label 4899*/ GIMT_Encode4(230920), // Rule ID 4543 //
87169 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
87170 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimmbf16),
87171 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
87172 // MIs[0] Operand 1
87173 // No operand predicates
87174 // (fpimm:{ *:[bf16] })<<P:Predicate_fpimmbf16>><<X:fpimm16XForm>>:$in => (FMOVHi:{ *:[bf16] } (fpimm16XForm:{ *:[f16] } bf16:{ *:[bf16] }:$in))
87175 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVHi),
87176 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87177 GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFPImm16), // in
87178 GIR_RootConstrainSelectedInstOperands,
87179 // GIR_Coverage, 4543,
87180 GIR_EraseRootFromParent_Done,
87181 // Label 4899: @230920
87182 GIM_Reject,
87183 // Label 4893: @230921
87184 GIM_Try, /*On fail goto*//*Label 4900*/ GIMT_Encode4(230944), // Rule ID 501 //
87185 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
87186 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
87187 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
87188 // MIs[0] Operand 1
87189 // No operand predicates
87190 // (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>> => (FMOVS0:{ *:[f32] })
87191 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVS0),
87192 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87193 GIR_RootConstrainSelectedInstOperands,
87194 // GIR_Coverage, 501,
87195 GIR_EraseRootFromParent_Done,
87196 // Label 4900: @230944
87197 GIM_Try, /*On fail goto*//*Label 4901*/ GIMT_Encode4(230972), // Rule ID 683 //
87198 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
87199 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm32),
87200 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
87201 // MIs[0] Operand 1
87202 // No operand predicates
87203 // (fpimm:{ *:[f32] })<<P:Predicate_fpimm32>><<X:fpimm32XForm>>:$imm => (FMOVSi:{ *:[f32] } (fpimm32XForm:{ *:[f32] } (fpimm:{ *:[f32] }):$imm))
87204 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVSi),
87205 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87206 GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFPImm32), // imm
87207 GIR_RootConstrainSelectedInstOperands,
87208 // GIR_Coverage, 683,
87209 GIR_EraseRootFromParent_Done,
87210 // Label 4901: @230972
87211 GIM_Try, /*On fail goto*//*Label 4902*/ GIMT_Encode4(231033), // Rule ID 5647 //
87212 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
87213 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm32SIMDModImmType4),
87214 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
87215 // MIs[0] Operand 1
87216 // No operand predicates
87217 // (fpimm:{ *:[f32] })<<P:Predicate_fpimm32SIMDModImmType4>><<X:fpimm32SIMDModImmType4XForm>>:$in => (EXTRACT_SUBREG:{ *:[f32] } (MOVIv2i32:{ *:[i64] } (fpimm32SIMDModImmType4XForm:{ *:[i32] } f32:{ *:[f32] }:$in), 24:{ *:[i32] }), ssub:{ *:[i32] })
87218 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
87219 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2i32),
87220 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87221 GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFPImm32SIMDModImmType4), // in
87222 GIR_AddImm8, /*InsnID*/1, /*Imm*/24,
87223 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
87224 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
87225 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
87226 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
87227 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
87228 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
87229 // GIR_Coverage, 5647,
87230 GIR_EraseRootFromParent_Done,
87231 // Label 4902: @231033
87232 GIM_Reject,
87233 // Label 4894: @231034
87234 GIM_Try, /*On fail goto*//*Label 4903*/ GIMT_Encode4(231057), // Rule ID 502 //
87235 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
87236 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
87237 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
87238 // MIs[0] Operand 1
87239 // No operand predicates
87240 // (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>> => (FMOVD0:{ *:[f64] })
87241 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVD0),
87242 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87243 GIR_RootConstrainSelectedInstOperands,
87244 // GIR_Coverage, 502,
87245 GIR_EraseRootFromParent_Done,
87246 // Label 4903: @231057
87247 GIM_Try, /*On fail goto*//*Label 4904*/ GIMT_Encode4(231085), // Rule ID 684 //
87248 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
87249 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm64),
87250 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
87251 // MIs[0] Operand 1
87252 // No operand predicates
87253 // (fpimm:{ *:[f64] })<<P:Predicate_fpimm64>><<X:fpimm64XForm>>:$imm => (FMOVDi:{ *:[f64] } (fpimm64XForm:{ *:[f64] } (fpimm:{ *:[f64] }):$imm))
87254 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVDi),
87255 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87256 GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFPImm64), // imm
87257 GIR_RootConstrainSelectedInstOperands,
87258 // GIR_Coverage, 684,
87259 GIR_EraseRootFromParent_Done,
87260 // Label 4904: @231085
87261 GIM_Reject,
87262 // Label 4895: @231086
87263 GIM_Reject,
87264 // Label 38: @231087
87265 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 4910*/ GIMT_Encode4(232984),
87266 /*GILLT_s32*//*Label 4905*/ GIMT_Encode4(231134),
87267 /*GILLT_s64*//*Label 4906*/ GIMT_Encode4(232575), GIMT_Encode4(0), GIMT_Encode4(0),
87268 /*GILLT_v2s64*//*Label 4907*/ GIMT_Encode4(232798), GIMT_Encode4(0),
87269 /*GILLT_v4s32*//*Label 4908*/ GIMT_Encode4(232860), GIMT_Encode4(0),
87270 /*GILLT_v8s16*//*Label 4909*/ GIMT_Encode4(232922),
87271 // Label 4905: @231134
87272 GIM_Try, /*On fail goto*//*Label 4911*/ GIMT_Encode4(231254), // Rule ID 12370 //
87273 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
87274 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
87275 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
87276 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
87277 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
87278 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
87279 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
87280 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
87281 GIM_CheckIsSafeToFold, /*NumInsns*/1,
87282 // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 624:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)) => (SMOVvi8to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn), bsub:{ *:[i32] }), 0:{ *:[i64] })
87283 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
87284 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
87285 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
87286 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i8v),
87287 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87288 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
87289 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
87290 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
87291 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87292 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
87293 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
87294 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87295 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
87296 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
87297 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
87298 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
87299 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
87300 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
87301 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
87302 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87303 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
87304 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87305 GIR_RootConstrainSelectedInstOperands,
87306 // GIR_Coverage, 12370,
87307 GIR_EraseRootFromParent_Done,
87308 // Label 4911: @231254
87309 GIM_Try, /*On fail goto*//*Label 4912*/ GIMT_Encode4(231374), // Rule ID 12372 //
87310 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
87311 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
87312 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
87313 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
87314 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
87315 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
87316 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
87317 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
87318 GIM_CheckIsSafeToFold, /*NumInsns*/1,
87319 // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 624:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)) => (SMOVvi8to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn), bsub:{ *:[i32] }), 0:{ *:[i64] })
87320 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
87321 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
87322 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
87323 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDVv16i8v),
87324 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87325 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
87326 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
87327 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
87328 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87329 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
87330 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
87331 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87332 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
87333 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
87334 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
87335 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
87336 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
87337 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
87338 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
87339 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87340 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
87341 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87342 GIR_RootConstrainSelectedInstOperands,
87343 // GIR_Coverage, 12372,
87344 GIR_EraseRootFromParent_Done,
87345 // Label 4912: @231374
87346 GIM_Try, /*On fail goto*//*Label 4913*/ GIMT_Encode4(231494), // Rule ID 12374 //
87347 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
87348 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
87349 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
87350 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
87351 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
87352 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
87353 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
87354 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
87355 GIM_CheckIsSafeToFold, /*NumInsns*/1,
87356 // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 624:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)) => (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
87357 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
87358 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
87359 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
87360 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i16v),
87361 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87362 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
87363 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
87364 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
87365 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87366 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
87367 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
87368 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87369 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
87370 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
87371 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
87372 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
87373 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
87374 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
87375 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
87376 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87377 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
87378 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87379 GIR_RootConstrainSelectedInstOperands,
87380 // GIR_Coverage, 12374,
87381 GIR_EraseRootFromParent_Done,
87382 // Label 4913: @231494
87383 GIM_Try, /*On fail goto*//*Label 4914*/ GIMT_Encode4(231614), // Rule ID 12376 //
87384 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
87385 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
87386 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
87387 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
87388 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
87389 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
87390 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
87391 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
87392 GIM_CheckIsSafeToFold, /*NumInsns*/1,
87393 // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 624:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
87394 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
87395 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
87396 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
87397 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i16v),
87398 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87399 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
87400 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
87401 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
87402 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87403 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
87404 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
87405 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87406 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
87407 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
87408 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
87409 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
87410 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
87411 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
87412 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
87413 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87414 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
87415 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87416 GIR_RootConstrainSelectedInstOperands,
87417 // GIR_Coverage, 12376,
87418 GIR_EraseRootFromParent_Done,
87419 // Label 4914: @231614
87420 GIM_Try, /*On fail goto*//*Label 4915*/ GIMT_Encode4(231734), // Rule ID 12392 //
87421 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
87422 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
87423 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
87424 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
87425 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
87426 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
87427 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
87428 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
87429 GIM_CheckIsSafeToFold, /*NumInsns*/1,
87430 // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 634:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)) => (SMOVvi8to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMAXVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn), bsub:{ *:[i32] }), 0:{ *:[i64] })
87431 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
87432 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
87433 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
87434 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv8i8v),
87435 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87436 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
87437 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
87438 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
87439 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87440 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
87441 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
87442 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87443 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
87444 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
87445 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
87446 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
87447 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
87448 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
87449 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
87450 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87451 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
87452 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87453 GIR_RootConstrainSelectedInstOperands,
87454 // GIR_Coverage, 12392,
87455 GIR_EraseRootFromParent_Done,
87456 // Label 4915: @231734
87457 GIM_Try, /*On fail goto*//*Label 4916*/ GIMT_Encode4(231854), // Rule ID 12394 //
87458 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
87459 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
87460 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
87461 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
87462 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
87463 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
87464 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
87465 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
87466 GIM_CheckIsSafeToFold, /*NumInsns*/1,
87467 // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 634:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)) => (SMOVvi8to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMAXVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn), bsub:{ *:[i32] }), 0:{ *:[i64] })
87468 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
87469 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
87470 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
87471 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv16i8v),
87472 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87473 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
87474 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
87475 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
87476 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87477 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
87478 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
87479 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87480 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
87481 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
87482 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
87483 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
87484 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
87485 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
87486 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
87487 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87488 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
87489 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87490 GIR_RootConstrainSelectedInstOperands,
87491 // GIR_Coverage, 12394,
87492 GIR_EraseRootFromParent_Done,
87493 // Label 4916: @231854
87494 GIM_Try, /*On fail goto*//*Label 4917*/ GIMT_Encode4(231974), // Rule ID 12396 //
87495 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
87496 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
87497 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
87498 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
87499 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
87500 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
87501 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
87502 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
87503 GIM_CheckIsSafeToFold, /*NumInsns*/1,
87504 // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 634:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)) => (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMAXVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
87505 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
87506 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
87507 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
87508 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv4i16v),
87509 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87510 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
87511 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
87512 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
87513 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87514 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
87515 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
87516 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87517 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
87518 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
87519 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
87520 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
87521 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
87522 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
87523 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
87524 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87525 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
87526 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87527 GIR_RootConstrainSelectedInstOperands,
87528 // GIR_Coverage, 12396,
87529 GIR_EraseRootFromParent_Done,
87530 // Label 4917: @231974
87531 GIM_Try, /*On fail goto*//*Label 4918*/ GIMT_Encode4(232094), // Rule ID 12398 //
87532 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
87533 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
87534 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
87535 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
87536 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
87537 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
87538 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
87539 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
87540 GIM_CheckIsSafeToFold, /*NumInsns*/1,
87541 // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 634:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMAXVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
87542 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
87543 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
87544 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
87545 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv8i16v),
87546 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87547 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
87548 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
87549 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
87550 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87551 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
87552 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
87553 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87554 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
87555 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
87556 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
87557 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
87558 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
87559 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
87560 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
87561 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87562 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
87563 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87564 GIR_RootConstrainSelectedInstOperands,
87565 // GIR_Coverage, 12398,
87566 GIR_EraseRootFromParent_Done,
87567 // Label 4918: @232094
87568 GIM_Try, /*On fail goto*//*Label 4919*/ GIMT_Encode4(232214), // Rule ID 12402 //
87569 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
87570 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
87571 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
87572 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
87573 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
87574 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
87575 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
87576 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
87577 GIM_CheckIsSafeToFold, /*NumInsns*/1,
87578 // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 637:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)) => (SMOVvi8to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMINVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn), bsub:{ *:[i32] }), 0:{ *:[i64] })
87579 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
87580 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
87581 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
87582 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMINVv8i8v),
87583 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87584 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
87585 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
87586 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
87587 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87588 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
87589 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
87590 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87591 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
87592 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
87593 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
87594 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
87595 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
87596 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
87597 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
87598 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87599 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
87600 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87601 GIR_RootConstrainSelectedInstOperands,
87602 // GIR_Coverage, 12402,
87603 GIR_EraseRootFromParent_Done,
87604 // Label 4919: @232214
87605 GIM_Try, /*On fail goto*//*Label 4920*/ GIMT_Encode4(232334), // Rule ID 12404 //
87606 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
87607 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
87608 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
87609 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
87610 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
87611 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
87612 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
87613 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
87614 GIM_CheckIsSafeToFold, /*NumInsns*/1,
87615 // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 637:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)) => (SMOVvi8to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMINVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn), bsub:{ *:[i32] }), 0:{ *:[i64] })
87616 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
87617 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
87618 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
87619 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMINVv16i8v),
87620 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87621 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
87622 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
87623 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
87624 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87625 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
87626 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
87627 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87628 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
87629 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
87630 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
87631 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
87632 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
87633 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
87634 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
87635 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87636 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
87637 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87638 GIR_RootConstrainSelectedInstOperands,
87639 // GIR_Coverage, 12404,
87640 GIR_EraseRootFromParent_Done,
87641 // Label 4920: @232334
87642 GIM_Try, /*On fail goto*//*Label 4921*/ GIMT_Encode4(232454), // Rule ID 12406 //
87643 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
87644 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
87645 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
87646 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
87647 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
87648 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
87649 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
87650 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
87651 GIM_CheckIsSafeToFold, /*NumInsns*/1,
87652 // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 637:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)) => (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMINVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
87653 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
87654 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
87655 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
87656 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMINVv4i16v),
87657 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87658 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
87659 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
87660 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
87661 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87662 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
87663 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
87664 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87665 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
87666 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
87667 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
87668 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
87669 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
87670 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
87671 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
87672 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87673 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
87674 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87675 GIR_RootConstrainSelectedInstOperands,
87676 // GIR_Coverage, 12406,
87677 GIR_EraseRootFromParent_Done,
87678 // Label 4921: @232454
87679 GIM_Try, /*On fail goto*//*Label 4922*/ GIMT_Encode4(232574), // Rule ID 12408 //
87680 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
87681 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
87682 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
87683 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
87684 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
87685 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
87686 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
87687 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
87688 GIM_CheckIsSafeToFold, /*NumInsns*/1,
87689 // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 637:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMINVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
87690 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
87691 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
87692 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
87693 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMINVv8i16v),
87694 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87695 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
87696 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
87697 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
87698 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87699 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
87700 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
87701 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87702 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
87703 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
87704 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
87705 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
87706 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
87707 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
87708 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
87709 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87710 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
87711 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87712 GIR_RootConstrainSelectedInstOperands,
87713 // GIR_Coverage, 12408,
87714 GIR_EraseRootFromParent_Done,
87715 // Label 4922: @232574
87716 GIM_Reject,
87717 // Label 4906: @232575
87718 GIM_Try, /*On fail goto*//*Label 4923*/ GIMT_Encode4(232797),
87719 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
87720 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
87721 GIM_Try, /*On fail goto*//*Label 4924*/ GIMT_Encode4(232641), // Rule ID 5311 //
87722 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
87723 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
87724 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
87725 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
87726 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
87727 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
87728 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
87729 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
87730 // MIs[2] Operand 1
87731 // No operand predicates
87732 GIM_CheckIsSafeToFold, /*NumInsns*/2,
87733 // (sext:{ *:[i64] } (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SMOVvi32to64:{ *:[i64] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
87734 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi32to64),
87735 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87736 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
87737 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
87738 GIR_RootConstrainSelectedInstOperands,
87739 // GIR_Coverage, 5311,
87740 GIR_EraseRootFromParent_Done,
87741 // Label 4924: @232641
87742 GIM_Try, /*On fail goto*//*Label 4925*/ GIMT_Encode4(232720), // Rule ID 10891 //
87743 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
87744 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
87745 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
87746 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
87747 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
87748 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
87749 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
87750 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
87751 // MIs[2] Operand 1
87752 // No operand predicates
87753 GIM_CheckIsSafeToFold, /*NumInsns*/2,
87754 // (sext:{ *:[i64] } (vector_extract:{ *:[i32] } nxv4i32:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$index)) => (SMOVvi32to64:{ *:[i64] } (EXTRACT_SUBREG:{ *:[v4i32] } ZPR:{ *:[nxv4i32] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$index)
87755 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
87756 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
87757 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87758 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(38), // vec
87759 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
87760 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
87761 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi32to64),
87762 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87763 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
87764 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
87765 GIR_RootConstrainSelectedInstOperands,
87766 // GIR_Coverage, 10891,
87767 GIR_EraseRootFromParent_Done,
87768 // Label 4925: @232720
87769 GIM_Try, /*On fail goto*//*Label 4926*/ GIMT_Encode4(232796), // Rule ID 6102 //
87770 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
87771 // (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (SBFMXri:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i64] }, 31:{ *:[i64] })
87772 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
87773 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
87774 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
87775 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87776 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
87777 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
87778 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87779 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
87780 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
87781 GIR_AddImm8, /*InsnID*/1, /*Imm*/16,
87782 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
87783 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
87784 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
87785 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
87786 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87787 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
87788 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87789 GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
87790 GIR_RootConstrainSelectedInstOperands,
87791 // GIR_Coverage, 6102,
87792 GIR_EraseRootFromParent_Done,
87793 // Label 4926: @232796
87794 GIM_Reject,
87795 // Label 4923: @232797
87796 GIM_Reject,
87797 // Label 4907: @232798
87798 GIM_Try, /*On fail goto*//*Label 4927*/ GIMT_Encode4(232859),
87799 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
87800 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
87801 GIM_Try, /*On fail goto*//*Label 4928*/ GIMT_Encode4(232837), // Rule ID 5961 //
87802 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
87803 // (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)) => (SSHLLv4i32_shift:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i32] })
87804 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i32_shift),
87805 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87806 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
87807 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87808 GIR_RootConstrainSelectedInstOperands,
87809 // GIR_Coverage, 5961,
87810 GIR_EraseRootFromParent_Done,
87811 // Label 4928: @232837
87812 GIM_Try, /*On fail goto*//*Label 4929*/ GIMT_Encode4(232858), // Rule ID 5948 //
87813 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
87814 // (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn) => (SSHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] })
87815 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
87816 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87817 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
87818 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87819 GIR_RootConstrainSelectedInstOperands,
87820 // GIR_Coverage, 5948,
87821 GIR_EraseRootFromParent_Done,
87822 // Label 4929: @232858
87823 GIM_Reject,
87824 // Label 4927: @232859
87825 GIM_Reject,
87826 // Label 4908: @232860
87827 GIM_Try, /*On fail goto*//*Label 4930*/ GIMT_Encode4(232921),
87828 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
87829 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
87830 GIM_Try, /*On fail goto*//*Label 4931*/ GIMT_Encode4(232899), // Rule ID 5958 //
87831 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
87832 // (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)) => (SSHLLv8i16_shift:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, 0:{ *:[i32] })
87833 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i16_shift),
87834 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87835 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
87836 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87837 GIR_RootConstrainSelectedInstOperands,
87838 // GIR_Coverage, 5958,
87839 GIR_EraseRootFromParent_Done,
87840 // Label 4931: @232899
87841 GIM_Try, /*On fail goto*//*Label 4932*/ GIMT_Encode4(232920), // Rule ID 5945 //
87842 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
87843 // (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn) => (SSHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] })
87844 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
87845 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87846 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
87847 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87848 GIR_RootConstrainSelectedInstOperands,
87849 // GIR_Coverage, 5945,
87850 GIR_EraseRootFromParent_Done,
87851 // Label 4932: @232920
87852 GIM_Reject,
87853 // Label 4930: @232921
87854 GIM_Reject,
87855 // Label 4909: @232922
87856 GIM_Try, /*On fail goto*//*Label 4933*/ GIMT_Encode4(232983),
87857 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
87858 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
87859 GIM_Try, /*On fail goto*//*Label 4934*/ GIMT_Encode4(232961), // Rule ID 5955 //
87860 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
87861 // (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)) => (SSHLLv16i8_shift:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, 0:{ *:[i32] })
87862 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv16i8_shift),
87863 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87864 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
87865 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87866 GIR_RootConstrainSelectedInstOperands,
87867 // GIR_Coverage, 5955,
87868 GIR_EraseRootFromParent_Done,
87869 // Label 4934: @232961
87870 GIM_Try, /*On fail goto*//*Label 4935*/ GIMT_Encode4(232982), // Rule ID 5942 //
87871 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
87872 // (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn) => (SSHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] })
87873 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i8_shift),
87874 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
87875 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
87876 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
87877 GIR_RootConstrainSelectedInstOperands,
87878 // GIR_Coverage, 5942,
87879 GIR_EraseRootFromParent_Done,
87880 // Label 4935: @232982
87881 GIM_Reject,
87882 // Label 4933: @232983
87883 GIM_Reject,
87884 // Label 4910: @232984
87885 GIM_Reject,
87886 // Label 39: @232985
87887 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 4940*/ GIMT_Encode4(235763),
87888 /*GILLT_s32*//*Label 4936*/ GIMT_Encode4(233032), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
87889 /*GILLT_v2s64*//*Label 4937*/ GIMT_Encode4(234833), GIMT_Encode4(0),
87890 /*GILLT_v4s32*//*Label 4938*/ GIMT_Encode4(235143), GIMT_Encode4(0),
87891 /*GILLT_v8s16*//*Label 4939*/ GIMT_Encode4(235453),
87892 // Label 4936: @233032
87893 GIM_Try, /*On fail goto*//*Label 4941*/ GIMT_Encode4(233182), // Rule ID 12379 //
87894 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
87895 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
87896 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
87897 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
87898 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
87899 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
87900 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
87901 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
87902 GIM_CheckIsSafeToFold, /*NumInsns*/1,
87903 // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 689:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn), bsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
87904 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
87905 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
87906 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
87907 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s8,
87908 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i8v),
87909 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87910 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
87911 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
87912 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
87913 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87914 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
87915 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
87916 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87917 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
87918 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
87919 GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
87920 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
87921 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
87922 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
87923 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
87924 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87925 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
87926 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
87927 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
87928 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
87929 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
87930 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
87931 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
87932 // GIR_Coverage, 12379,
87933 GIR_EraseRootFromParent_Done,
87934 // Label 4941: @233182
87935 GIM_Try, /*On fail goto*//*Label 4942*/ GIMT_Encode4(233332), // Rule ID 12381 //
87936 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
87937 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
87938 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
87939 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
87940 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
87941 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
87942 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
87943 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
87944 GIM_CheckIsSafeToFold, /*NumInsns*/1,
87945 // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 689:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn), bsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
87946 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
87947 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
87948 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
87949 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s8,
87950 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::ADDVv16i8v),
87951 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87952 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
87953 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
87954 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
87955 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87956 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
87957 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
87958 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87959 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
87960 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
87961 GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
87962 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
87963 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
87964 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
87965 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
87966 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87967 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
87968 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
87969 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
87970 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
87971 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
87972 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
87973 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
87974 // GIR_Coverage, 12381,
87975 GIR_EraseRootFromParent_Done,
87976 // Label 4942: @233332
87977 GIM_Try, /*On fail goto*//*Label 4943*/ GIMT_Encode4(233482), // Rule ID 12383 //
87978 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
87979 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
87980 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
87981 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
87982 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
87983 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
87984 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
87985 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
87986 GIM_CheckIsSafeToFold, /*NumInsns*/1,
87987 // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 689:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
87988 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
87989 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
87990 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
87991 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
87992 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i16v),
87993 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87994 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
87995 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
87996 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
87997 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
87998 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
87999 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
88000 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88001 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
88002 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
88003 GIR_AddImm8, /*InsnID*/2, /*Imm*/7,
88004 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
88005 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88006 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
88007 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88008 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88009 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
88010 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
88011 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88012 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88013 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
88014 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
88015 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
88016 // GIR_Coverage, 12383,
88017 GIR_EraseRootFromParent_Done,
88018 // Label 4943: @233482
88019 GIM_Try, /*On fail goto*//*Label 4944*/ GIMT_Encode4(233632), // Rule ID 12385 //
88020 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
88021 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88022 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88023 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88024 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
88025 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
88026 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
88027 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
88028 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88029 // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 689:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
88030 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
88031 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
88032 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
88033 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
88034 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i16v),
88035 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88036 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
88037 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
88038 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
88039 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88040 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
88041 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
88042 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88043 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
88044 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
88045 GIR_AddImm8, /*InsnID*/2, /*Imm*/7,
88046 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
88047 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88048 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
88049 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88050 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88051 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
88052 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
88053 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88054 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88055 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
88056 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
88057 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
88058 // GIR_Coverage, 12385,
88059 GIR_EraseRootFromParent_Done,
88060 // Label 4944: @233632
88061 GIM_Try, /*On fail goto*//*Label 4945*/ GIMT_Encode4(233782), // Rule ID 12412 //
88062 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
88063 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88064 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88065 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88066 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
88067 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
88068 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
88069 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
88070 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88071 // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 695:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMAXVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn), bsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
88072 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
88073 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
88074 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
88075 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s8,
88076 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv8i8v),
88077 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88078 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
88079 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
88080 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
88081 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88082 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
88083 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
88084 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88085 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
88086 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
88087 GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
88088 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
88089 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88090 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
88091 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88092 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88093 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
88094 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
88095 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88096 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88097 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
88098 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
88099 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
88100 // GIR_Coverage, 12412,
88101 GIR_EraseRootFromParent_Done,
88102 // Label 4945: @233782
88103 GIM_Try, /*On fail goto*//*Label 4946*/ GIMT_Encode4(233932), // Rule ID 12414 //
88104 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
88105 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88106 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88107 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88108 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
88109 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
88110 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
88111 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
88112 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88113 // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 695:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMAXVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn), bsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
88114 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
88115 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
88116 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
88117 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s8,
88118 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv16i8v),
88119 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88120 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
88121 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
88122 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
88123 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88124 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
88125 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
88126 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88127 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
88128 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
88129 GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
88130 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
88131 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88132 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
88133 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88134 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88135 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
88136 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
88137 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88138 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88139 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
88140 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
88141 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
88142 // GIR_Coverage, 12414,
88143 GIR_EraseRootFromParent_Done,
88144 // Label 4946: @233932
88145 GIM_Try, /*On fail goto*//*Label 4947*/ GIMT_Encode4(234082), // Rule ID 12416 //
88146 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
88147 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88148 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88149 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88150 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
88151 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
88152 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
88153 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
88154 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88155 // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 695:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMAXVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
88156 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
88157 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
88158 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
88159 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
88160 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv4i16v),
88161 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88162 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
88163 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
88164 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
88165 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88166 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
88167 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
88168 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88169 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
88170 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
88171 GIR_AddImm8, /*InsnID*/2, /*Imm*/7,
88172 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
88173 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88174 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
88175 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88176 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88177 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
88178 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
88179 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88180 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88181 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
88182 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
88183 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
88184 // GIR_Coverage, 12416,
88185 GIR_EraseRootFromParent_Done,
88186 // Label 4947: @234082
88187 GIM_Try, /*On fail goto*//*Label 4948*/ GIMT_Encode4(234232), // Rule ID 12418 //
88188 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
88189 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88190 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88191 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88192 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
88193 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
88194 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
88195 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
88196 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88197 // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 695:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMAXVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
88198 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
88199 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
88200 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
88201 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
88202 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv8i16v),
88203 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88204 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
88205 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
88206 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
88207 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88208 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
88209 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
88210 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88211 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
88212 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
88213 GIR_AddImm8, /*InsnID*/2, /*Imm*/7,
88214 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
88215 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88216 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
88217 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88218 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88219 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
88220 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
88221 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88222 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88223 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
88224 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
88225 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
88226 // GIR_Coverage, 12418,
88227 GIR_EraseRootFromParent_Done,
88228 // Label 4948: @234232
88229 GIM_Try, /*On fail goto*//*Label 4949*/ GIMT_Encode4(234382), // Rule ID 12422 //
88230 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
88231 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88232 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88233 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88234 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
88235 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
88236 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
88237 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
88238 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88239 // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 698:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMINVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn), bsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
88240 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
88241 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
88242 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
88243 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s8,
88244 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMINVv8i8v),
88245 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88246 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
88247 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
88248 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
88249 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88250 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
88251 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
88252 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88253 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
88254 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
88255 GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
88256 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
88257 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88258 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
88259 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88260 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88261 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
88262 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
88263 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88264 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88265 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
88266 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
88267 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
88268 // GIR_Coverage, 12422,
88269 GIR_EraseRootFromParent_Done,
88270 // Label 4949: @234382
88271 GIM_Try, /*On fail goto*//*Label 4950*/ GIMT_Encode4(234532), // Rule ID 12424 //
88272 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
88273 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88274 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88275 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88276 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
88277 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
88278 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
88279 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
88280 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88281 // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 698:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMINVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn), bsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
88282 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
88283 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
88284 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
88285 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s8,
88286 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMINVv16i8v),
88287 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88288 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
88289 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
88290 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
88291 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88292 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
88293 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
88294 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88295 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
88296 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
88297 GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
88298 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
88299 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88300 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
88301 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88302 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88303 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
88304 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
88305 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88306 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88307 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
88308 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
88309 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
88310 // GIR_Coverage, 12424,
88311 GIR_EraseRootFromParent_Done,
88312 // Label 4950: @234532
88313 GIM_Try, /*On fail goto*//*Label 4951*/ GIMT_Encode4(234682), // Rule ID 12426 //
88314 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
88315 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88316 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88317 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88318 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
88319 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
88320 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
88321 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
88322 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88323 // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 698:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMINVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
88324 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
88325 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
88326 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
88327 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
88328 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMINVv4i16v),
88329 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88330 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
88331 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
88332 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
88333 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88334 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
88335 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
88336 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88337 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
88338 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
88339 GIR_AddImm8, /*InsnID*/2, /*Imm*/7,
88340 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
88341 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88342 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
88343 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88344 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88345 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
88346 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
88347 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88348 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88349 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
88350 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
88351 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
88352 // GIR_Coverage, 12426,
88353 GIR_EraseRootFromParent_Done,
88354 // Label 4951: @234682
88355 GIM_Try, /*On fail goto*//*Label 4952*/ GIMT_Encode4(234832), // Rule ID 12428 //
88356 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
88357 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88358 GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88359 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88360 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
88361 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
88362 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
88363 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
88364 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88365 // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 698:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMINVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
88366 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
88367 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
88368 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
88369 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
88370 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMINVv8i16v),
88371 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88372 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
88373 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
88374 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
88375 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88376 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
88377 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
88378 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88379 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
88380 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
88381 GIR_AddImm8, /*InsnID*/2, /*Imm*/7,
88382 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
88383 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88384 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
88385 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88386 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88387 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
88388 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
88389 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
88390 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
88391 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
88392 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
88393 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
88394 // GIR_Coverage, 12428,
88395 GIR_EraseRootFromParent_Done,
88396 // Label 4952: @234832
88397 GIM_Reject,
88398 // Label 4937: @234833
88399 GIM_Try, /*On fail goto*//*Label 4953*/ GIMT_Encode4(235142),
88400 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
88401 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
88402 GIM_Try, /*On fail goto*//*Label 4954*/ GIMT_Encode4(234910), // Rule ID 696 //
88403 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
88404 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88405 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88406 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
88407 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
88408 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
88409 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
88410 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88411 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
88412 GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
88413 // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 686:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (UABDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
88414 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv4i32_v2i64),
88415 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88416 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
88417 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
88418 GIR_RootConstrainSelectedInstOperands,
88419 // GIR_Coverage, 696,
88420 GIR_EraseRootFromParent_Done,
88421 // Label 4954: @234910
88422 GIM_Try, /*On fail goto*//*Label 4955*/ GIMT_Encode4(234975), // Rule ID 1698 //
88423 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
88424 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88425 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88426 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
88427 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
88428 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
88429 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
88430 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88431 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
88432 GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
88433 // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 621:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))) => (SABDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
88434 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLv4i32_v2i64),
88435 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88436 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
88437 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
88438 GIR_RootConstrainSelectedInstOperands,
88439 // GIR_Coverage, 1698,
88440 GIR_EraseRootFromParent_Done,
88441 // Label 4955: @234975
88442 GIM_Try, /*On fail goto*//*Label 4956*/ GIMT_Encode4(235034), // Rule ID 694 //
88443 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
88444 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88445 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88446 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
88447 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
88448 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
88449 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
88450 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
88451 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
88452 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88453 // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 686:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (UABDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
88454 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv2i32_v2i64),
88455 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88456 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
88457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
88458 GIR_RootConstrainSelectedInstOperands,
88459 // GIR_Coverage, 694,
88460 GIR_EraseRootFromParent_Done,
88461 // Label 4956: @235034
88462 GIM_Try, /*On fail goto*//*Label 4957*/ GIMT_Encode4(235093), // Rule ID 1696 //
88463 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
88464 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88465 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88466 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
88467 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
88468 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
88469 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
88470 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
88471 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
88472 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88473 // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 621:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)) => (SABDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
88474 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLv2i32_v2i64),
88475 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88476 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
88477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
88478 GIR_RootConstrainSelectedInstOperands,
88479 // GIR_Coverage, 1696,
88480 GIR_EraseRootFromParent_Done,
88481 // Label 4957: @235093
88482 GIM_Try, /*On fail goto*//*Label 4958*/ GIMT_Encode4(235120), // Rule ID 5960 //
88483 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
88484 // (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)) => (USHLLv4i32_shift:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i32] })
88485 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv4i32_shift),
88486 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88487 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
88488 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
88489 GIR_RootConstrainSelectedInstOperands,
88490 // GIR_Coverage, 5960,
88491 GIR_EraseRootFromParent_Done,
88492 // Label 4958: @235120
88493 GIM_Try, /*On fail goto*//*Label 4959*/ GIMT_Encode4(235141), // Rule ID 5949 //
88494 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
88495 // (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn) => (USHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] })
88496 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv2i32_shift),
88497 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88498 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
88499 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
88500 GIR_RootConstrainSelectedInstOperands,
88501 // GIR_Coverage, 5949,
88502 GIR_EraseRootFromParent_Done,
88503 // Label 4959: @235141
88504 GIM_Reject,
88505 // Label 4953: @235142
88506 GIM_Reject,
88507 // Label 4938: @235143
88508 GIM_Try, /*On fail goto*//*Label 4960*/ GIMT_Encode4(235452),
88509 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
88510 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
88511 GIM_Try, /*On fail goto*//*Label 4961*/ GIMT_Encode4(235220), // Rule ID 692 //
88512 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
88513 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88514 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88515 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
88516 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
88517 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
88518 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
88519 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88520 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
88521 GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
88522 // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 686:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (UABDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
88523 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv8i16_v4i32),
88524 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88525 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
88526 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
88527 GIR_RootConstrainSelectedInstOperands,
88528 // GIR_Coverage, 692,
88529 GIR_EraseRootFromParent_Done,
88530 // Label 4961: @235220
88531 GIM_Try, /*On fail goto*//*Label 4962*/ GIMT_Encode4(235285), // Rule ID 1694 //
88532 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
88533 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88534 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88535 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
88536 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
88537 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
88538 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
88539 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88540 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
88541 GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
88542 // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 621:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))) => (SABDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
88543 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLv8i16_v4i32),
88544 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88545 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
88546 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
88547 GIR_RootConstrainSelectedInstOperands,
88548 // GIR_Coverage, 1694,
88549 GIR_EraseRootFromParent_Done,
88550 // Label 4962: @235285
88551 GIM_Try, /*On fail goto*//*Label 4963*/ GIMT_Encode4(235344), // Rule ID 690 //
88552 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
88553 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88554 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88555 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
88556 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
88557 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
88558 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
88559 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
88560 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
88561 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88562 // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 686:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (UABDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
88563 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv4i16_v4i32),
88564 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88565 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
88566 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
88567 GIR_RootConstrainSelectedInstOperands,
88568 // GIR_Coverage, 690,
88569 GIR_EraseRootFromParent_Done,
88570 // Label 4963: @235344
88571 GIM_Try, /*On fail goto*//*Label 4964*/ GIMT_Encode4(235403), // Rule ID 1692 //
88572 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
88573 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88574 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88575 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
88576 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
88577 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
88578 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
88579 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
88580 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
88581 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88582 // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 621:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)) => (SABDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
88583 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLv4i16_v4i32),
88584 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88585 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
88586 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
88587 GIR_RootConstrainSelectedInstOperands,
88588 // GIR_Coverage, 1692,
88589 GIR_EraseRootFromParent_Done,
88590 // Label 4964: @235403
88591 GIM_Try, /*On fail goto*//*Label 4965*/ GIMT_Encode4(235430), // Rule ID 5957 //
88592 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
88593 // (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)) => (USHLLv8i16_shift:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, 0:{ *:[i32] })
88594 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv8i16_shift),
88595 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88596 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
88597 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
88598 GIR_RootConstrainSelectedInstOperands,
88599 // GIR_Coverage, 5957,
88600 GIR_EraseRootFromParent_Done,
88601 // Label 4965: @235430
88602 GIM_Try, /*On fail goto*//*Label 4966*/ GIMT_Encode4(235451), // Rule ID 5946 //
88603 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
88604 // (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn) => (USHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] })
88605 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv4i16_shift),
88606 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88607 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
88608 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
88609 GIR_RootConstrainSelectedInstOperands,
88610 // GIR_Coverage, 5946,
88611 GIR_EraseRootFromParent_Done,
88612 // Label 4966: @235451
88613 GIM_Reject,
88614 // Label 4960: @235452
88615 GIM_Reject,
88616 // Label 4939: @235453
88617 GIM_Try, /*On fail goto*//*Label 4967*/ GIMT_Encode4(235762),
88618 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
88619 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
88620 GIM_Try, /*On fail goto*//*Label 4968*/ GIMT_Encode4(235530), // Rule ID 688 //
88621 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
88622 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88623 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88624 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
88625 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
88626 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
88627 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
88628 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88629 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
88630 GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
88631 // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 686:{ *:[iPTR] }, (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (UABDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
88632 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv16i8_v8i16),
88633 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88634 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
88635 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
88636 GIR_RootConstrainSelectedInstOperands,
88637 // GIR_Coverage, 688,
88638 GIR_EraseRootFromParent_Done,
88639 // Label 4968: @235530
88640 GIM_Try, /*On fail goto*//*Label 4969*/ GIMT_Encode4(235595), // Rule ID 1690 //
88641 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
88642 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88643 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88644 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
88645 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
88646 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
88647 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
88648 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88649 GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
88650 GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
88651 // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 621:{ *:[iPTR] }, (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))) => (SABDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
88652 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLv16i8_v8i16),
88653 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88654 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
88655 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
88656 GIR_RootConstrainSelectedInstOperands,
88657 // GIR_Coverage, 1690,
88658 GIR_EraseRootFromParent_Done,
88659 // Label 4969: @235595
88660 GIM_Try, /*On fail goto*//*Label 4970*/ GIMT_Encode4(235654), // Rule ID 686 //
88661 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
88662 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88663 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88664 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
88665 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uabd),
88666 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
88667 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
88668 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
88669 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
88670 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88671 // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 686:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (UABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
88672 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv8i8_v8i16),
88673 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
88675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
88676 GIR_RootConstrainSelectedInstOperands,
88677 // GIR_Coverage, 686,
88678 GIR_EraseRootFromParent_Done,
88679 // Label 4970: @235654
88680 GIM_Try, /*On fail goto*//*Label 4971*/ GIMT_Encode4(235713), // Rule ID 1688 //
88681 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
88682 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
88683 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
88684 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
88685 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sabd),
88686 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
88687 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
88688 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
88689 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
88690 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88691 // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 621:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)) => (SABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
88692 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLv8i8_v8i16),
88693 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88694 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
88695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
88696 GIR_RootConstrainSelectedInstOperands,
88697 // GIR_Coverage, 1688,
88698 GIR_EraseRootFromParent_Done,
88699 // Label 4971: @235713
88700 GIM_Try, /*On fail goto*//*Label 4972*/ GIMT_Encode4(235740), // Rule ID 5954 //
88701 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
88702 // (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)) => (USHLLv16i8_shift:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, 0:{ *:[i32] })
88703 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv16i8_shift),
88704 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88705 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
88706 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
88707 GIR_RootConstrainSelectedInstOperands,
88708 // GIR_Coverage, 5954,
88709 GIR_EraseRootFromParent_Done,
88710 // Label 4972: @235740
88711 GIM_Try, /*On fail goto*//*Label 4973*/ GIMT_Encode4(235761), // Rule ID 5943 //
88712 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
88713 // (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn) => (USHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] })
88714 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv8i8_shift),
88715 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88716 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
88717 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
88718 GIR_RootConstrainSelectedInstOperands,
88719 // GIR_Coverage, 5943,
88720 GIR_EraseRootFromParent_Done,
88721 // Label 4973: @235761
88722 GIM_Reject,
88723 // Label 4967: @235762
88724 GIM_Reject,
88725 // Label 4940: @235763
88726 GIM_Reject,
88727 // Label 40: @235764
88728 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 4976*/ GIMT_Encode4(236088),
88729 /*GILLT_s32*//*Label 4974*/ GIMT_Encode4(235783),
88730 /*GILLT_s64*//*Label 4975*/ GIMT_Encode4(235915),
88731 // Label 4974: @235783
88732 GIM_Try, /*On fail goto*//*Label 4977*/ GIMT_Encode4(235914),
88733 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
88734 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
88735 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88736 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88737 GIM_Try, /*On fail goto*//*Label 4978*/ GIMT_Encode4(235839), // Rule ID 3804 //
88738 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
88739 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
88740 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
88741 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88742 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88743 // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
88744 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSLVWr),
88745 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88746 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
88747 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
88748 GIR_RootConstrainSelectedInstOperands,
88749 // GIR_Coverage, 3804,
88750 GIR_EraseRootFromParent_Done,
88751 // Label 4978: @235839
88752 GIM_Try, /*On fail goto*//*Label 4979*/ GIMT_Encode4(235876), // Rule ID 3805 //
88753 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
88754 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
88755 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
88756 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88757 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88758 // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
88759 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSLVWr),
88760 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88761 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
88762 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
88763 GIR_RootConstrainSelectedInstOperands,
88764 // GIR_Coverage, 3805,
88765 GIR_EraseRootFromParent_Done,
88766 // Label 4979: @235876
88767 GIM_Try, /*On fail goto*//*Label 4980*/ GIMT_Encode4(235913), // Rule ID 3803 //
88768 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
88769 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
88770 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
88771 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88772 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88773 // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
88774 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSLVWr),
88775 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88776 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
88777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
88778 GIR_RootConstrainSelectedInstOperands,
88779 // GIR_Coverage, 3803,
88780 GIR_EraseRootFromParent_Done,
88781 // Label 4980: @235913
88782 GIM_Reject,
88783 // Label 4977: @235914
88784 GIM_Reject,
88785 // Label 4975: @235915
88786 GIM_Try, /*On fail goto*//*Label 4981*/ GIMT_Encode4(236087),
88787 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
88788 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
88789 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
88790 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
88791 GIM_Try, /*On fail goto*//*Label 4982*/ GIMT_Encode4(236002), // Rule ID 3806 //
88792 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
88793 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
88794 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
88795 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88796 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88797 // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
88798 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
88799 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
88800 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88801 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
88802 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
88803 GIR_AddImm8, /*InsnID*/1, /*Imm*/16,
88804 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
88805 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
88806 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSLVXr),
88807 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88808 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
88809 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
88810 GIR_RootConstrainSelectedInstOperands,
88811 // GIR_Coverage, 3806,
88812 GIR_EraseRootFromParent_Done,
88813 // Label 4982: @236002
88814 GIM_Try, /*On fail goto*//*Label 4983*/ GIMT_Encode4(236070), // Rule ID 3807 //
88815 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
88816 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
88817 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
88818 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88819 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88820 // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSLVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
88821 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
88822 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
88823 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88824 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
88825 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
88826 GIR_AddImm8, /*InsnID*/1, /*Imm*/16,
88827 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
88828 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
88829 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSLVXr),
88830 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88831 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
88832 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
88833 GIR_RootConstrainSelectedInstOperands,
88834 // GIR_Coverage, 3807,
88835 GIR_EraseRootFromParent_Done,
88836 // Label 4983: @236070
88837 GIM_Try, /*On fail goto*//*Label 4984*/ GIMT_Encode4(236086), // Rule ID 131 //
88838 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
88839 // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (LSLVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
88840 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LSLVXr),
88841 GIR_RootConstrainSelectedInstOperands,
88842 // GIR_Coverage, 131,
88843 GIR_Done,
88844 // Label 4984: @236086
88845 GIM_Reject,
88846 // Label 4981: @236087
88847 GIM_Reject,
88848 // Label 4976: @236088
88849 GIM_Reject,
88850 // Label 41: @236089
88851 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 4987*/ GIMT_Encode4(236481),
88852 /*GILLT_s32*//*Label 4985*/ GIMT_Encode4(236108),
88853 /*GILLT_s64*//*Label 4986*/ GIMT_Encode4(236274),
88854 // Label 4985: @236108
88855 GIM_Try, /*On fail goto*//*Label 4988*/ GIMT_Encode4(236273),
88856 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
88857 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
88858 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88859 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88860 GIM_Try, /*On fail goto*//*Label 4989*/ GIMT_Encode4(236161), // Rule ID 3891 //
88861 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
88862 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
88863 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
88864 // MIs[1] Operand 1
88865 // No operand predicates
88866 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88867 // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm) => (UBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, 31:{ *:[i64] })
88868 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UBFMWri),
88869 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88870 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
88871 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
88872 GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
88873 GIR_RootConstrainSelectedInstOperands,
88874 // GIR_Coverage, 3891,
88875 GIR_EraseRootFromParent_Done,
88876 // Label 4989: @236161
88877 GIM_Try, /*On fail goto*//*Label 4990*/ GIMT_Encode4(236198), // Rule ID 3810 //
88878 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
88879 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
88880 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
88881 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88882 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88883 // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
88884 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSRVWr),
88885 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88886 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
88887 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
88888 GIR_RootConstrainSelectedInstOperands,
88889 // GIR_Coverage, 3810,
88890 GIR_EraseRootFromParent_Done,
88891 // Label 4990: @236198
88892 GIM_Try, /*On fail goto*//*Label 4991*/ GIMT_Encode4(236235), // Rule ID 3811 //
88893 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
88894 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
88895 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
88896 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88897 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88898 // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
88899 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSRVWr),
88900 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88901 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
88902 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
88903 GIR_RootConstrainSelectedInstOperands,
88904 // GIR_Coverage, 3811,
88905 GIR_EraseRootFromParent_Done,
88906 // Label 4991: @236235
88907 GIM_Try, /*On fail goto*//*Label 4992*/ GIMT_Encode4(236272), // Rule ID 3809 //
88908 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
88909 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
88910 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
88911 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88912 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88913 // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
88914 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSRVWr),
88915 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88916 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
88917 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
88918 GIR_RootConstrainSelectedInstOperands,
88919 // GIR_Coverage, 3809,
88920 GIR_EraseRootFromParent_Done,
88921 // Label 4992: @236272
88922 GIM_Reject,
88923 // Label 4988: @236273
88924 GIM_Reject,
88925 // Label 4986: @236274
88926 GIM_Try, /*On fail goto*//*Label 4993*/ GIMT_Encode4(236480),
88927 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
88928 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
88929 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
88930 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
88931 GIM_Try, /*On fail goto*//*Label 4994*/ GIMT_Encode4(236327), // Rule ID 3892 //
88932 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
88933 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
88934 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_63),
88935 // MIs[1] Operand 1
88936 // No operand predicates
88937 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88938 // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm) => (UBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm, 63:{ *:[i64] })
88939 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UBFMXri),
88940 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88941 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
88942 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
88943 GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
88944 GIR_RootConstrainSelectedInstOperands,
88945 // GIR_Coverage, 3892,
88946 GIR_EraseRootFromParent_Done,
88947 // Label 4994: @236327
88948 GIM_Try, /*On fail goto*//*Label 4995*/ GIMT_Encode4(236395), // Rule ID 3812 //
88949 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
88950 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
88951 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
88952 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88953 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88954 // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
88955 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
88956 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
88957 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88958 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
88959 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
88960 GIR_AddImm8, /*InsnID*/1, /*Imm*/16,
88961 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
88962 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
88963 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSRVXr),
88964 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88965 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
88966 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
88967 GIR_RootConstrainSelectedInstOperands,
88968 // GIR_Coverage, 3812,
88969 GIR_EraseRootFromParent_Done,
88970 // Label 4995: @236395
88971 GIM_Try, /*On fail goto*//*Label 4996*/ GIMT_Encode4(236463), // Rule ID 3813 //
88972 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
88973 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
88974 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
88975 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
88976 GIM_CheckIsSafeToFold, /*NumInsns*/1,
88977 // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (LSRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
88978 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
88979 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
88980 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
88981 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
88982 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
88983 GIR_AddImm8, /*InsnID*/1, /*Imm*/16,
88984 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
88985 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
88986 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSRVXr),
88987 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
88988 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
88989 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
88990 GIR_RootConstrainSelectedInstOperands,
88991 // GIR_Coverage, 3813,
88992 GIR_EraseRootFromParent_Done,
88993 // Label 4996: @236463
88994 GIM_Try, /*On fail goto*//*Label 4997*/ GIMT_Encode4(236479), // Rule ID 132 //
88995 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
88996 // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (LSRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
88997 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LSRVXr),
88998 GIR_RootConstrainSelectedInstOperands,
88999 // GIR_Coverage, 132,
89000 GIR_Done,
89001 // Label 4997: @236479
89002 GIM_Reject,
89003 // Label 4993: @236480
89004 GIM_Reject,
89005 // Label 4987: @236481
89006 GIM_Reject,
89007 // Label 42: @236482
89008 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 5000*/ GIMT_Encode4(236989),
89009 /*GILLT_s32*//*Label 4998*/ GIMT_Encode4(236501),
89010 /*GILLT_s64*//*Label 4999*/ GIMT_Encode4(236667),
89011 // Label 4998: @236501
89012 GIM_Try, /*On fail goto*//*Label 5001*/ GIMT_Encode4(236666),
89013 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
89014 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
89015 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89016 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89017 GIM_Try, /*On fail goto*//*Label 5002*/ GIMT_Encode4(236554), // Rule ID 3889 //
89018 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89019 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
89020 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
89021 // MIs[1] Operand 1
89022 // No operand predicates
89023 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89024 // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm) => (SBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, 31:{ *:[i64] })
89025 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMWri),
89026 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89027 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
89028 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
89029 GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
89030 GIR_RootConstrainSelectedInstOperands,
89031 // GIR_Coverage, 3889,
89032 GIR_EraseRootFromParent_Done,
89033 // Label 5002: @236554
89034 GIM_Try, /*On fail goto*//*Label 5003*/ GIMT_Encode4(236591), // Rule ID 2375 //
89035 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89036 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
89037 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
89038 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89039 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89040 // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
89041 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASRVWr),
89042 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89043 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
89044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
89045 GIR_RootConstrainSelectedInstOperands,
89046 // GIR_Coverage, 2375,
89047 GIR_EraseRootFromParent_Done,
89048 // Label 5003: @236591
89049 GIM_Try, /*On fail goto*//*Label 5004*/ GIMT_Encode4(236628), // Rule ID 2376 //
89050 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89051 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
89052 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
89053 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89054 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89055 // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
89056 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASRVWr),
89057 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89058 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
89059 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
89060 GIR_RootConstrainSelectedInstOperands,
89061 // GIR_Coverage, 2376,
89062 GIR_EraseRootFromParent_Done,
89063 // Label 5004: @236628
89064 GIM_Try, /*On fail goto*//*Label 5005*/ GIMT_Encode4(236665), // Rule ID 2374 //
89065 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89066 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
89067 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
89068 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89069 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89070 // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
89071 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASRVWr),
89072 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89073 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
89074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
89075 GIR_RootConstrainSelectedInstOperands,
89076 // GIR_Coverage, 2374,
89077 GIR_EraseRootFromParent_Done,
89078 // Label 5005: @236665
89079 GIM_Reject,
89080 // Label 5001: @236666
89081 GIM_Reject,
89082 // Label 4999: @236667
89083 GIM_Try, /*On fail goto*//*Label 5006*/ GIMT_Encode4(236988),
89084 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
89085 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
89086 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
89087 GIM_Try, /*On fail goto*//*Label 5007*/ GIMT_Encode4(236785), // Rule ID 6120 //
89088 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
89089 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
89090 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
89091 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89092 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
89093 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
89094 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
89095 // MIs[2] Operand 1
89096 // No operand predicates
89097 GIM_CheckIsSafeToFold, /*NumInsns*/2,
89098 // (sra:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm) => (SBFMXri:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, 31:{ *:[i64] })
89099 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
89100 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
89101 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
89102 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
89103 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
89104 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
89105 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
89106 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
89107 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
89108 GIR_AddImm8, /*InsnID*/1, /*Imm*/16,
89109 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
89110 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
89111 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
89112 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
89113 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89114 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
89115 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
89116 GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
89117 GIR_RootConstrainSelectedInstOperands,
89118 // GIR_Coverage, 6120,
89119 GIR_EraseRootFromParent_Done,
89120 // Label 5007: @236785
89121 GIM_Try, /*On fail goto*//*Label 5008*/ GIMT_Encode4(236823), // Rule ID 3890 //
89122 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
89123 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89124 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
89125 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_63),
89126 // MIs[1] Operand 1
89127 // No operand predicates
89128 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89129 // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm) => (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm, 63:{ *:[i64] })
89130 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
89131 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89132 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
89133 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
89134 GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
89135 GIR_RootConstrainSelectedInstOperands,
89136 // GIR_Coverage, 3890,
89137 GIR_EraseRootFromParent_Done,
89138 // Label 5008: @236823
89139 GIM_Try, /*On fail goto*//*Label 5009*/ GIMT_Encode4(236895), // Rule ID 2377 //
89140 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
89141 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89142 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
89143 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
89144 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89145 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89146 // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
89147 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
89148 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
89149 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
89150 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
89151 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
89152 GIR_AddImm8, /*InsnID*/1, /*Imm*/16,
89153 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
89154 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
89155 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASRVXr),
89156 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89157 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
89158 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
89159 GIR_RootConstrainSelectedInstOperands,
89160 // GIR_Coverage, 2377,
89161 GIR_EraseRootFromParent_Done,
89162 // Label 5009: @236895
89163 GIM_Try, /*On fail goto*//*Label 5010*/ GIMT_Encode4(236967), // Rule ID 2378 //
89164 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
89165 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89166 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
89167 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
89168 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89169 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89170 // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (ASRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
89171 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
89172 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
89173 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
89174 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
89175 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
89176 GIR_AddImm8, /*InsnID*/1, /*Imm*/16,
89177 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
89178 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
89179 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASRVXr),
89180 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89181 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
89182 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
89183 GIR_RootConstrainSelectedInstOperands,
89184 // GIR_Coverage, 2378,
89185 GIR_EraseRootFromParent_Done,
89186 // Label 5010: @236967
89187 GIM_Try, /*On fail goto*//*Label 5011*/ GIMT_Encode4(236987), // Rule ID 130 //
89188 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
89189 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
89190 // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (ASRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
89191 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ASRVXr),
89192 GIR_RootConstrainSelectedInstOperands,
89193 // GIR_Coverage, 130,
89194 GIR_Done,
89195 // Label 5011: @236987
89196 GIM_Reject,
89197 // Label 5006: @236988
89198 GIM_Reject,
89199 // Label 5000: @236989
89200 GIM_Reject,
89201 // Label 43: @236990
89202 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 5014*/ GIMT_Encode4(237119),
89203 /*GILLT_s32*//*Label 5012*/ GIMT_Encode4(237009),
89204 /*GILLT_s64*//*Label 5013*/ GIMT_Encode4(237064),
89205 // Label 5012: @237009
89206 GIM_Try, /*On fail goto*//*Label 5015*/ GIMT_Encode4(237063), // Rule ID 199 //
89207 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
89208 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
89209 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
89210 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89211 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89212 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89213 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
89214 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
89215 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
89216 // MIs[1] Operand 1
89217 // No operand predicates
89218 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89219 // (fshr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm) => (EXTRWrri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, (imm:{ *:[i64] }):$imm)
89220 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTRWrri),
89221 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89222 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
89223 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
89224 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
89225 GIR_RootConstrainSelectedInstOperands,
89226 // GIR_Coverage, 199,
89227 GIR_EraseRootFromParent_Done,
89228 // Label 5015: @237063
89229 GIM_Reject,
89230 // Label 5013: @237064
89231 GIM_Try, /*On fail goto*//*Label 5016*/ GIMT_Encode4(237118), // Rule ID 200 //
89232 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
89233 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
89234 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
89235 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
89236 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
89237 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
89238 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
89239 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
89240 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_63),
89241 // MIs[1] Operand 1
89242 // No operand predicates
89243 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89244 // (fshr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm) => (EXTRXrri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, (imm:{ *:[i64] }):$imm)
89245 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTRXrri),
89246 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89247 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
89248 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
89249 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
89250 GIR_RootConstrainSelectedInstOperands,
89251 // GIR_Coverage, 200,
89252 GIR_EraseRootFromParent_Done,
89253 // Label 5016: @237118
89254 GIM_Reject,
89255 // Label 5014: @237119
89256 GIM_Reject,
89257 // Label 44: @237120
89258 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 5019*/ GIMT_Encode4(237612),
89259 /*GILLT_s32*//*Label 5017*/ GIMT_Encode4(237139),
89260 /*GILLT_s64*//*Label 5018*/ GIMT_Encode4(237355),
89261 // Label 5017: @237139
89262 GIM_Try, /*On fail goto*//*Label 5020*/ GIMT_Encode4(237354),
89263 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
89264 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
89265 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89266 GIM_Try, /*On fail goto*//*Label 5021*/ GIMT_Encode4(237193), // Rule ID 195 //
89267 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
89268 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
89269 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
89270 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89271 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
89272 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89273 // (rotr:{ *:[i32] } (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$Rn), 16:{ *:[i64] }) => (REV16Wr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
89274 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV16Wr),
89275 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89276 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
89277 GIR_RootConstrainSelectedInstOperands,
89278 // GIR_Coverage, 195,
89279 GIR_EraseRootFromParent_Done,
89280 // Label 5021: @237193
89281 GIM_Try, /*On fail goto*//*Label 5022*/ GIMT_Encode4(237230), // Rule ID 3885 //
89282 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89283 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89284 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
89285 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
89286 // MIs[1] Operand 1
89287 // No operand predicates
89288 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89289 // (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm) => (EXTRWrri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)
89290 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTRWrri),
89291 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89292 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
89293 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
89294 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
89295 GIR_RootConstrainSelectedInstOperands,
89296 // GIR_Coverage, 3885,
89297 GIR_EraseRootFromParent_Done,
89298 // Label 5022: @237230
89299 GIM_Try, /*On fail goto*//*Label 5023*/ GIMT_Encode4(237271), // Rule ID 3816 //
89300 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89301 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89302 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
89303 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
89304 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89305 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89306 // (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (RORVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
89307 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RORVWr),
89308 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89309 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
89310 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
89311 GIR_RootConstrainSelectedInstOperands,
89312 // GIR_Coverage, 3816,
89313 GIR_EraseRootFromParent_Done,
89314 // Label 5023: @237271
89315 GIM_Try, /*On fail goto*//*Label 5024*/ GIMT_Encode4(237312), // Rule ID 3817 //
89316 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89317 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89318 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
89319 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
89320 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89321 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89322 // (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (RORVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
89323 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RORVWr),
89324 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89325 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
89326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
89327 GIR_RootConstrainSelectedInstOperands,
89328 // GIR_Coverage, 3817,
89329 GIR_EraseRootFromParent_Done,
89330 // Label 5024: @237312
89331 GIM_Try, /*On fail goto*//*Label 5025*/ GIMT_Encode4(237353), // Rule ID 3815 //
89332 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89333 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89334 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
89335 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
89336 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89337 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89338 // (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (RORVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
89339 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RORVWr),
89340 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89341 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
89342 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
89343 GIR_RootConstrainSelectedInstOperands,
89344 // GIR_Coverage, 3815,
89345 GIR_EraseRootFromParent_Done,
89346 // Label 5025: @237353
89347 GIM_Reject,
89348 // Label 5020: @237354
89349 GIM_Reject,
89350 // Label 5018: @237355
89351 GIM_Try, /*On fail goto*//*Label 5026*/ GIMT_Encode4(237611),
89352 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
89353 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
89354 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
89355 GIM_Try, /*On fail goto*//*Label 5027*/ GIMT_Encode4(237409), // Rule ID 198 //
89356 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
89357 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
89358 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
89359 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
89360 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 32,
89361 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89362 // (rotr:{ *:[i64] } (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$Rn), 32:{ *:[i64] }) => (REV32Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
89363 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV32Xr),
89364 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
89366 GIR_RootConstrainSelectedInstOperands,
89367 // GIR_Coverage, 198,
89368 GIR_EraseRootFromParent_Done,
89369 // Label 5027: @237409
89370 GIM_Try, /*On fail goto*//*Label 5028*/ GIMT_Encode4(237446), // Rule ID 3886 //
89371 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
89372 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89373 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
89374 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_63),
89375 // MIs[1] Operand 1
89376 // No operand predicates
89377 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89378 // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm) => (EXTRXrri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm)
89379 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTRXrri),
89380 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89381 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
89382 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
89383 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
89384 GIR_RootConstrainSelectedInstOperands,
89385 // GIR_Coverage, 3886,
89386 GIR_EraseRootFromParent_Done,
89387 // Label 5028: @237446
89388 GIM_Try, /*On fail goto*//*Label 5029*/ GIMT_Encode4(237518), // Rule ID 3818 //
89389 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
89390 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89391 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
89392 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
89393 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89394 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89395 // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (RORVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
89396 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
89397 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
89398 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
89399 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
89400 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
89401 GIR_AddImm8, /*InsnID*/1, /*Imm*/16,
89402 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
89403 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
89404 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RORVXr),
89405 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89406 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
89407 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
89408 GIR_RootConstrainSelectedInstOperands,
89409 // GIR_Coverage, 3818,
89410 GIR_EraseRootFromParent_Done,
89411 // Label 5029: @237518
89412 GIM_Try, /*On fail goto*//*Label 5030*/ GIMT_Encode4(237590), // Rule ID 3819 //
89413 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
89414 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89415 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
89416 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
89417 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
89418 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89419 // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)) => (RORVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
89420 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
89421 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
89422 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
89423 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
89424 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
89425 GIR_AddImm8, /*InsnID*/1, /*Imm*/16,
89426 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
89427 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
89428 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RORVXr),
89429 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89430 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
89431 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
89432 GIR_RootConstrainSelectedInstOperands,
89433 // GIR_Coverage, 3819,
89434 GIR_EraseRootFromParent_Done,
89435 // Label 5030: @237590
89436 GIM_Try, /*On fail goto*//*Label 5031*/ GIMT_Encode4(237610), // Rule ID 133 //
89437 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
89438 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
89439 // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (RORVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
89440 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::RORVXr),
89441 GIR_RootConstrainSelectedInstOperands,
89442 // GIR_Coverage, 133,
89443 GIR_Done,
89444 // Label 5031: @237610
89445 GIM_Reject,
89446 // Label 5026: @237611
89447 GIM_Reject,
89448 // Label 5019: @237612
89449 GIM_Reject,
89450 // Label 45: @237613
89451 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(12), /*)*//*default:*//*Label 5039*/ GIMT_Encode4(242188),
89452 /*GILLT_v2s32*//*Label 5032*/ GIMT_Encode4(237652),
89453 /*GILLT_v2s64*//*Label 5033*/ GIMT_Encode4(238300),
89454 /*GILLT_v4s16*//*Label 5034*/ GIMT_Encode4(238948),
89455 /*GILLT_v4s32*//*Label 5035*/ GIMT_Encode4(239596),
89456 /*GILLT_v8s8*//*Label 5036*/ GIMT_Encode4(240244),
89457 /*GILLT_v8s16*//*Label 5037*/ GIMT_Encode4(240892),
89458 /*GILLT_v16s8*//*Label 5038*/ GIMT_Encode4(241540),
89459 // Label 5032: @237652
89460 GIM_Try, /*On fail goto*//*Label 5040*/ GIMT_Encode4(238299),
89461 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
89462 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
89463 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89464 GIM_Try, /*On fail goto*//*Label 5041*/ GIMT_Encode4(237704), // Rule ID 4824 //
89465 // MIs[0] Operand 1
89466 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
89467 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89468 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89469 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89470 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89471 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89472 // (setcc:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn, SETEQ:{ *:[Other] }) => (CMEQv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
89473 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i32rz),
89474 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89475 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
89476 GIR_RootConstrainSelectedInstOperands,
89477 // GIR_Coverage, 4824,
89478 GIR_EraseRootFromParent_Done,
89479 // Label 5041: @237704
89480 GIM_Try, /*On fail goto*//*Label 5042*/ GIMT_Encode4(237741), // Rule ID 4831 //
89481 // MIs[0] Operand 1
89482 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
89483 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89484 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89485 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89486 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89487 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89488 // (setcc:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn, SETGT:{ *:[Other] }) => (CMLTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
89489 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i32rz),
89490 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89491 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
89492 GIR_RootConstrainSelectedInstOperands,
89493 // GIR_Coverage, 4831,
89494 GIR_EraseRootFromParent_Done,
89495 // Label 5042: @237741
89496 GIM_Try, /*On fail goto*//*Label 5043*/ GIMT_Encode4(237778), // Rule ID 4838 //
89497 // MIs[0] Operand 1
89498 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
89499 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89500 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89501 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89502 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89503 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89504 // (setcc:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn, SETGE:{ *:[Other] }) => (CMLEv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
89505 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv2i32rz),
89506 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89507 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
89508 GIR_RootConstrainSelectedInstOperands,
89509 // GIR_Coverage, 4838,
89510 GIR_EraseRootFromParent_Done,
89511 // Label 5043: @237778
89512 GIM_Try, /*On fail goto*//*Label 5044*/ GIMT_Encode4(237815), // Rule ID 4845 //
89513 // MIs[0] Operand 1
89514 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
89515 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89516 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89517 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89518 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89519 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89520 // (setcc:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn, SETLT:{ *:[Other] }) => (CMGTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
89521 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i32rz),
89522 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89523 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
89524 GIR_RootConstrainSelectedInstOperands,
89525 // GIR_Coverage, 4845,
89526 GIR_EraseRootFromParent_Done,
89527 // Label 5044: @237815
89528 GIM_Try, /*On fail goto*//*Label 5045*/ GIMT_Encode4(237852), // Rule ID 4852 //
89529 // MIs[0] Operand 1
89530 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
89531 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89532 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89533 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89534 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89535 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89536 // (setcc:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn, SETLE:{ *:[Other] }) => (CMGEv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
89537 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i32rz),
89538 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89539 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
89540 GIR_RootConstrainSelectedInstOperands,
89541 // GIR_Coverage, 4852,
89542 GIR_EraseRootFromParent_Done,
89543 // Label 5045: @237852
89544 GIM_Try, /*On fail goto*//*Label 5046*/ GIMT_Encode4(237889), // Rule ID 4789 //
89545 // MIs[0] Operand 1
89546 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
89547 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89548 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
89549 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89550 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89551 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89552 // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETEQ:{ *:[Other] }) => (CMEQv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
89553 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i32rz),
89554 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89555 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89556 GIR_RootConstrainSelectedInstOperands,
89557 // GIR_Coverage, 4789,
89558 GIR_EraseRootFromParent_Done,
89559 // Label 5046: @237889
89560 GIM_Try, /*On fail goto*//*Label 5047*/ GIMT_Encode4(237926), // Rule ID 4796 //
89561 // MIs[0] Operand 1
89562 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
89563 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89564 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
89565 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89566 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89567 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89568 // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETGT:{ *:[Other] }) => (CMGTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
89569 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i32rz),
89570 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89571 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89572 GIR_RootConstrainSelectedInstOperands,
89573 // GIR_Coverage, 4796,
89574 GIR_EraseRootFromParent_Done,
89575 // Label 5047: @237926
89576 GIM_Try, /*On fail goto*//*Label 5048*/ GIMT_Encode4(237963), // Rule ID 4803 //
89577 // MIs[0] Operand 1
89578 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
89579 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89580 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
89581 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89582 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89583 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89584 // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETGE:{ *:[Other] }) => (CMGEv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
89585 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i32rz),
89586 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89587 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89588 GIR_RootConstrainSelectedInstOperands,
89589 // GIR_Coverage, 4803,
89590 GIR_EraseRootFromParent_Done,
89591 // Label 5048: @237963
89592 GIM_Try, /*On fail goto*//*Label 5049*/ GIMT_Encode4(238000), // Rule ID 4810 //
89593 // MIs[0] Operand 1
89594 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
89595 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89596 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
89597 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89598 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89599 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89600 // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETLT:{ *:[Other] }) => (CMLTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
89601 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i32rz),
89602 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89603 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89604 GIR_RootConstrainSelectedInstOperands,
89605 // GIR_Coverage, 4810,
89606 GIR_EraseRootFromParent_Done,
89607 // Label 5049: @238000
89608 GIM_Try, /*On fail goto*//*Label 5050*/ GIMT_Encode4(238037), // Rule ID 4817 //
89609 // MIs[0] Operand 1
89610 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
89611 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89612 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
89613 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89614 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89615 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89616 // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETLE:{ *:[Other] }) => (CMLEv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
89617 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv2i32rz),
89618 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89619 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89620 GIR_RootConstrainSelectedInstOperands,
89621 // GIR_Coverage, 4817,
89622 GIR_EraseRootFromParent_Done,
89623 // Label 5050: @238037
89624 GIM_Try, /*On fail goto*//*Label 5051*/ GIMT_Encode4(238066), // Rule ID 4726 //
89625 // MIs[0] Operand 1
89626 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
89627 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89628 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89629 // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETEQ:{ *:[Other] }) => (CMEQv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
89630 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i32),
89631 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89632 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89633 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
89634 GIR_RootConstrainSelectedInstOperands,
89635 // GIR_Coverage, 4726,
89636 GIR_EraseRootFromParent_Done,
89637 // Label 5051: @238066
89638 GIM_Try, /*On fail goto*//*Label 5052*/ GIMT_Encode4(238095), // Rule ID 4733 //
89639 // MIs[0] Operand 1
89640 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
89641 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89642 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89643 // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETGT:{ *:[Other] }) => (CMGTv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
89644 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i32),
89645 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89646 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89647 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
89648 GIR_RootConstrainSelectedInstOperands,
89649 // GIR_Coverage, 4733,
89650 GIR_EraseRootFromParent_Done,
89651 // Label 5052: @238095
89652 GIM_Try, /*On fail goto*//*Label 5053*/ GIMT_Encode4(238124), // Rule ID 4740 //
89653 // MIs[0] Operand 1
89654 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
89655 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89656 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89657 // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETGE:{ *:[Other] }) => (CMGEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
89658 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i32),
89659 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89660 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89661 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
89662 GIR_RootConstrainSelectedInstOperands,
89663 // GIR_Coverage, 4740,
89664 GIR_EraseRootFromParent_Done,
89665 // Label 5053: @238124
89666 GIM_Try, /*On fail goto*//*Label 5054*/ GIMT_Encode4(238153), // Rule ID 4747 //
89667 // MIs[0] Operand 1
89668 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
89669 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89670 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89671 // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETUGT:{ *:[Other] }) => (CMHIv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
89672 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv2i32),
89673 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89674 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89675 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
89676 GIR_RootConstrainSelectedInstOperands,
89677 // GIR_Coverage, 4747,
89678 GIR_EraseRootFromParent_Done,
89679 // Label 5054: @238153
89680 GIM_Try, /*On fail goto*//*Label 5055*/ GIMT_Encode4(238182), // Rule ID 4754 //
89681 // MIs[0] Operand 1
89682 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
89683 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89684 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89685 // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETUGE:{ *:[Other] }) => (CMHSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
89686 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv2i32),
89687 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89688 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89689 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
89690 GIR_RootConstrainSelectedInstOperands,
89691 // GIR_Coverage, 4754,
89692 GIR_EraseRootFromParent_Done,
89693 // Label 5055: @238182
89694 GIM_Try, /*On fail goto*//*Label 5056*/ GIMT_Encode4(238211), // Rule ID 4761 //
89695 // MIs[0] Operand 1
89696 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
89697 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89698 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89699 // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETLT:{ *:[Other] }) => (CMGTv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rm, V64:{ *:[v2i32] }:$Rn)
89700 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i32),
89701 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89702 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
89703 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89704 GIR_RootConstrainSelectedInstOperands,
89705 // GIR_Coverage, 4761,
89706 GIR_EraseRootFromParent_Done,
89707 // Label 5056: @238211
89708 GIM_Try, /*On fail goto*//*Label 5057*/ GIMT_Encode4(238240), // Rule ID 4768 //
89709 // MIs[0] Operand 1
89710 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
89711 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89712 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89713 // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETLE:{ *:[Other] }) => (CMGEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rm, V64:{ *:[v2i32] }:$Rn)
89714 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i32),
89715 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89716 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
89717 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89718 GIR_RootConstrainSelectedInstOperands,
89719 // GIR_Coverage, 4768,
89720 GIR_EraseRootFromParent_Done,
89721 // Label 5057: @238240
89722 GIM_Try, /*On fail goto*//*Label 5058*/ GIMT_Encode4(238269), // Rule ID 4775 //
89723 // MIs[0] Operand 1
89724 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
89725 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89726 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89727 // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETULT:{ *:[Other] }) => (CMHIv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rm, V64:{ *:[v2i32] }:$Rn)
89728 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv2i32),
89729 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89730 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
89731 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89732 GIR_RootConstrainSelectedInstOperands,
89733 // GIR_Coverage, 4775,
89734 GIR_EraseRootFromParent_Done,
89735 // Label 5058: @238269
89736 GIM_Try, /*On fail goto*//*Label 5059*/ GIMT_Encode4(238298), // Rule ID 4782 //
89737 // MIs[0] Operand 1
89738 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
89739 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89740 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
89741 // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETULE:{ *:[Other] }) => (CMHSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rm, V64:{ *:[v2i32] }:$Rn)
89742 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv2i32),
89743 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89744 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
89745 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89746 GIR_RootConstrainSelectedInstOperands,
89747 // GIR_Coverage, 4782,
89748 GIR_EraseRootFromParent_Done,
89749 // Label 5059: @238298
89750 GIM_Reject,
89751 // Label 5040: @238299
89752 GIM_Reject,
89753 // Label 5033: @238300
89754 GIM_Try, /*On fail goto*//*Label 5060*/ GIMT_Encode4(238947),
89755 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
89756 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
89757 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89758 GIM_Try, /*On fail goto*//*Label 5061*/ GIMT_Encode4(238352), // Rule ID 4826 //
89759 // MIs[0] Operand 1
89760 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
89761 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89762 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89763 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89764 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89765 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89766 // (setcc:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn, SETEQ:{ *:[Other] }) => (CMEQv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
89767 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i64rz),
89768 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89769 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
89770 GIR_RootConstrainSelectedInstOperands,
89771 // GIR_Coverage, 4826,
89772 GIR_EraseRootFromParent_Done,
89773 // Label 5061: @238352
89774 GIM_Try, /*On fail goto*//*Label 5062*/ GIMT_Encode4(238389), // Rule ID 4833 //
89775 // MIs[0] Operand 1
89776 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
89777 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89778 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89779 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89780 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89781 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89782 // (setcc:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn, SETGT:{ *:[Other] }) => (CMLTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
89783 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i64rz),
89784 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89785 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
89786 GIR_RootConstrainSelectedInstOperands,
89787 // GIR_Coverage, 4833,
89788 GIR_EraseRootFromParent_Done,
89789 // Label 5062: @238389
89790 GIM_Try, /*On fail goto*//*Label 5063*/ GIMT_Encode4(238426), // Rule ID 4840 //
89791 // MIs[0] Operand 1
89792 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
89793 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89794 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89795 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89796 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89797 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89798 // (setcc:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn, SETGE:{ *:[Other] }) => (CMLEv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
89799 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv2i64rz),
89800 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89801 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
89802 GIR_RootConstrainSelectedInstOperands,
89803 // GIR_Coverage, 4840,
89804 GIR_EraseRootFromParent_Done,
89805 // Label 5063: @238426
89806 GIM_Try, /*On fail goto*//*Label 5064*/ GIMT_Encode4(238463), // Rule ID 4847 //
89807 // MIs[0] Operand 1
89808 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
89809 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89810 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89811 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89812 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89813 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89814 // (setcc:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn, SETLT:{ *:[Other] }) => (CMGTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
89815 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i64rz),
89816 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89817 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
89818 GIR_RootConstrainSelectedInstOperands,
89819 // GIR_Coverage, 4847,
89820 GIR_EraseRootFromParent_Done,
89821 // Label 5064: @238463
89822 GIM_Try, /*On fail goto*//*Label 5065*/ GIMT_Encode4(238500), // Rule ID 4854 //
89823 // MIs[0] Operand 1
89824 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
89825 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
89826 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89827 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89828 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89829 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89830 // (setcc:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn, SETLE:{ *:[Other] }) => (CMGEv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
89831 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i64rz),
89832 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89833 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
89834 GIR_RootConstrainSelectedInstOperands,
89835 // GIR_Coverage, 4854,
89836 GIR_EraseRootFromParent_Done,
89837 // Label 5065: @238500
89838 GIM_Try, /*On fail goto*//*Label 5066*/ GIMT_Encode4(238537), // Rule ID 4791 //
89839 // MIs[0] Operand 1
89840 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
89841 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89842 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
89843 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89844 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89845 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89846 // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETEQ:{ *:[Other] }) => (CMEQv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
89847 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i64rz),
89848 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89849 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89850 GIR_RootConstrainSelectedInstOperands,
89851 // GIR_Coverage, 4791,
89852 GIR_EraseRootFromParent_Done,
89853 // Label 5066: @238537
89854 GIM_Try, /*On fail goto*//*Label 5067*/ GIMT_Encode4(238574), // Rule ID 4798 //
89855 // MIs[0] Operand 1
89856 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
89857 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89858 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
89859 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89860 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89861 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89862 // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETGT:{ *:[Other] }) => (CMGTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
89863 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i64rz),
89864 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89865 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89866 GIR_RootConstrainSelectedInstOperands,
89867 // GIR_Coverage, 4798,
89868 GIR_EraseRootFromParent_Done,
89869 // Label 5067: @238574
89870 GIM_Try, /*On fail goto*//*Label 5068*/ GIMT_Encode4(238611), // Rule ID 4805 //
89871 // MIs[0] Operand 1
89872 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
89873 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89874 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
89875 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89876 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89877 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89878 // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETGE:{ *:[Other] }) => (CMGEv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
89879 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i64rz),
89880 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89881 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89882 GIR_RootConstrainSelectedInstOperands,
89883 // GIR_Coverage, 4805,
89884 GIR_EraseRootFromParent_Done,
89885 // Label 5068: @238611
89886 GIM_Try, /*On fail goto*//*Label 5069*/ GIMT_Encode4(238648), // Rule ID 4812 //
89887 // MIs[0] Operand 1
89888 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
89889 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89890 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
89891 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89892 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89893 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89894 // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETLT:{ *:[Other] }) => (CMLTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
89895 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i64rz),
89896 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89897 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89898 GIR_RootConstrainSelectedInstOperands,
89899 // GIR_Coverage, 4812,
89900 GIR_EraseRootFromParent_Done,
89901 // Label 5069: @238648
89902 GIM_Try, /*On fail goto*//*Label 5070*/ GIMT_Encode4(238685), // Rule ID 4819 //
89903 // MIs[0] Operand 1
89904 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
89905 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89906 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
89907 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
89908 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
89909 GIM_CheckIsSafeToFold, /*NumInsns*/1,
89910 // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETLE:{ *:[Other] }) => (CMLEv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
89911 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv2i64rz),
89912 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89913 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89914 GIR_RootConstrainSelectedInstOperands,
89915 // GIR_Coverage, 4819,
89916 GIR_EraseRootFromParent_Done,
89917 // Label 5070: @238685
89918 GIM_Try, /*On fail goto*//*Label 5071*/ GIMT_Encode4(238714), // Rule ID 4728 //
89919 // MIs[0] Operand 1
89920 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
89921 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89922 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89923 // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETEQ:{ *:[Other] }) => (CMEQv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
89924 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i64),
89925 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89926 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89927 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
89928 GIR_RootConstrainSelectedInstOperands,
89929 // GIR_Coverage, 4728,
89930 GIR_EraseRootFromParent_Done,
89931 // Label 5071: @238714
89932 GIM_Try, /*On fail goto*//*Label 5072*/ GIMT_Encode4(238743), // Rule ID 4735 //
89933 // MIs[0] Operand 1
89934 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
89935 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89936 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89937 // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETGT:{ *:[Other] }) => (CMGTv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
89938 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i64),
89939 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89940 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89941 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
89942 GIR_RootConstrainSelectedInstOperands,
89943 // GIR_Coverage, 4735,
89944 GIR_EraseRootFromParent_Done,
89945 // Label 5072: @238743
89946 GIM_Try, /*On fail goto*//*Label 5073*/ GIMT_Encode4(238772), // Rule ID 4742 //
89947 // MIs[0] Operand 1
89948 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
89949 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89950 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89951 // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETGE:{ *:[Other] }) => (CMGEv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
89952 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i64),
89953 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89954 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89955 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
89956 GIR_RootConstrainSelectedInstOperands,
89957 // GIR_Coverage, 4742,
89958 GIR_EraseRootFromParent_Done,
89959 // Label 5073: @238772
89960 GIM_Try, /*On fail goto*//*Label 5074*/ GIMT_Encode4(238801), // Rule ID 4749 //
89961 // MIs[0] Operand 1
89962 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
89963 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89964 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89965 // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETUGT:{ *:[Other] }) => (CMHIv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
89966 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv2i64),
89967 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89968 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89969 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
89970 GIR_RootConstrainSelectedInstOperands,
89971 // GIR_Coverage, 4749,
89972 GIR_EraseRootFromParent_Done,
89973 // Label 5074: @238801
89974 GIM_Try, /*On fail goto*//*Label 5075*/ GIMT_Encode4(238830), // Rule ID 4756 //
89975 // MIs[0] Operand 1
89976 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
89977 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89978 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89979 // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETUGE:{ *:[Other] }) => (CMHSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
89980 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv2i64),
89981 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89982 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89983 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
89984 GIR_RootConstrainSelectedInstOperands,
89985 // GIR_Coverage, 4756,
89986 GIR_EraseRootFromParent_Done,
89987 // Label 5075: @238830
89988 GIM_Try, /*On fail goto*//*Label 5076*/ GIMT_Encode4(238859), // Rule ID 4763 //
89989 // MIs[0] Operand 1
89990 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
89991 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89992 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
89993 // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETLT:{ *:[Other] }) => (CMGTv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, V128:{ *:[v2i64] }:$Rn)
89994 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i64),
89995 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
89996 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
89997 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
89998 GIR_RootConstrainSelectedInstOperands,
89999 // GIR_Coverage, 4763,
90000 GIR_EraseRootFromParent_Done,
90001 // Label 5076: @238859
90002 GIM_Try, /*On fail goto*//*Label 5077*/ GIMT_Encode4(238888), // Rule ID 4770 //
90003 // MIs[0] Operand 1
90004 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
90005 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90006 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90007 // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETLE:{ *:[Other] }) => (CMGEv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, V128:{ *:[v2i64] }:$Rn)
90008 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i64),
90009 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90010 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90011 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90012 GIR_RootConstrainSelectedInstOperands,
90013 // GIR_Coverage, 4770,
90014 GIR_EraseRootFromParent_Done,
90015 // Label 5077: @238888
90016 GIM_Try, /*On fail goto*//*Label 5078*/ GIMT_Encode4(238917), // Rule ID 4777 //
90017 // MIs[0] Operand 1
90018 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
90019 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90020 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90021 // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETULT:{ *:[Other] }) => (CMHIv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, V128:{ *:[v2i64] }:$Rn)
90022 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv2i64),
90023 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90024 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90025 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90026 GIR_RootConstrainSelectedInstOperands,
90027 // GIR_Coverage, 4777,
90028 GIR_EraseRootFromParent_Done,
90029 // Label 5078: @238917
90030 GIM_Try, /*On fail goto*//*Label 5079*/ GIMT_Encode4(238946), // Rule ID 4784 //
90031 // MIs[0] Operand 1
90032 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
90033 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90034 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90035 // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETULE:{ *:[Other] }) => (CMHSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, V128:{ *:[v2i64] }:$Rn)
90036 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv2i64),
90037 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90038 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90039 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90040 GIR_RootConstrainSelectedInstOperands,
90041 // GIR_Coverage, 4784,
90042 GIR_EraseRootFromParent_Done,
90043 // Label 5079: @238946
90044 GIM_Reject,
90045 // Label 5060: @238947
90046 GIM_Reject,
90047 // Label 5034: @238948
90048 GIM_Try, /*On fail goto*//*Label 5080*/ GIMT_Encode4(239595),
90049 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
90050 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
90051 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90052 GIM_Try, /*On fail goto*//*Label 5081*/ GIMT_Encode4(239000), // Rule ID 4822 //
90053 // MIs[0] Operand 1
90054 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
90055 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
90056 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90057 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90058 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90059 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90060 // (setcc:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn, SETEQ:{ *:[Other] }) => (CMEQv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
90061 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i16rz),
90062 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90063 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
90064 GIR_RootConstrainSelectedInstOperands,
90065 // GIR_Coverage, 4822,
90066 GIR_EraseRootFromParent_Done,
90067 // Label 5081: @239000
90068 GIM_Try, /*On fail goto*//*Label 5082*/ GIMT_Encode4(239037), // Rule ID 4829 //
90069 // MIs[0] Operand 1
90070 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
90071 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
90072 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90073 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90074 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90075 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90076 // (setcc:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn, SETGT:{ *:[Other] }) => (CMLTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
90077 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i16rz),
90078 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90079 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
90080 GIR_RootConstrainSelectedInstOperands,
90081 // GIR_Coverage, 4829,
90082 GIR_EraseRootFromParent_Done,
90083 // Label 5082: @239037
90084 GIM_Try, /*On fail goto*//*Label 5083*/ GIMT_Encode4(239074), // Rule ID 4836 //
90085 // MIs[0] Operand 1
90086 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
90087 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
90088 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90089 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90090 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90091 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90092 // (setcc:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn, SETGE:{ *:[Other] }) => (CMLEv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
90093 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv4i16rz),
90094 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90095 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
90096 GIR_RootConstrainSelectedInstOperands,
90097 // GIR_Coverage, 4836,
90098 GIR_EraseRootFromParent_Done,
90099 // Label 5083: @239074
90100 GIM_Try, /*On fail goto*//*Label 5084*/ GIMT_Encode4(239111), // Rule ID 4843 //
90101 // MIs[0] Operand 1
90102 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
90103 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
90104 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90105 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90106 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90107 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90108 // (setcc:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn, SETLT:{ *:[Other] }) => (CMGTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
90109 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i16rz),
90110 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90111 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
90112 GIR_RootConstrainSelectedInstOperands,
90113 // GIR_Coverage, 4843,
90114 GIR_EraseRootFromParent_Done,
90115 // Label 5084: @239111
90116 GIM_Try, /*On fail goto*//*Label 5085*/ GIMT_Encode4(239148), // Rule ID 4850 //
90117 // MIs[0] Operand 1
90118 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
90119 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
90120 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90121 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90122 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90123 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90124 // (setcc:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn, SETLE:{ *:[Other] }) => (CMGEv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
90125 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i16rz),
90126 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90127 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
90128 GIR_RootConstrainSelectedInstOperands,
90129 // GIR_Coverage, 4850,
90130 GIR_EraseRootFromParent_Done,
90131 // Label 5085: @239148
90132 GIM_Try, /*On fail goto*//*Label 5086*/ GIMT_Encode4(239185), // Rule ID 4787 //
90133 // MIs[0] Operand 1
90134 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
90135 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90136 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
90137 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90138 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90139 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90140 // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETEQ:{ *:[Other] }) => (CMEQv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
90141 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i16rz),
90142 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90143 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90144 GIR_RootConstrainSelectedInstOperands,
90145 // GIR_Coverage, 4787,
90146 GIR_EraseRootFromParent_Done,
90147 // Label 5086: @239185
90148 GIM_Try, /*On fail goto*//*Label 5087*/ GIMT_Encode4(239222), // Rule ID 4794 //
90149 // MIs[0] Operand 1
90150 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
90151 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90152 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
90153 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90154 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90155 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90156 // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETGT:{ *:[Other] }) => (CMGTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
90157 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i16rz),
90158 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90159 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90160 GIR_RootConstrainSelectedInstOperands,
90161 // GIR_Coverage, 4794,
90162 GIR_EraseRootFromParent_Done,
90163 // Label 5087: @239222
90164 GIM_Try, /*On fail goto*//*Label 5088*/ GIMT_Encode4(239259), // Rule ID 4801 //
90165 // MIs[0] Operand 1
90166 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
90167 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90168 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
90169 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90170 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90171 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90172 // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETGE:{ *:[Other] }) => (CMGEv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
90173 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i16rz),
90174 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90175 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90176 GIR_RootConstrainSelectedInstOperands,
90177 // GIR_Coverage, 4801,
90178 GIR_EraseRootFromParent_Done,
90179 // Label 5088: @239259
90180 GIM_Try, /*On fail goto*//*Label 5089*/ GIMT_Encode4(239296), // Rule ID 4808 //
90181 // MIs[0] Operand 1
90182 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
90183 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90184 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
90185 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90186 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90187 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90188 // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETLT:{ *:[Other] }) => (CMLTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
90189 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i16rz),
90190 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90191 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90192 GIR_RootConstrainSelectedInstOperands,
90193 // GIR_Coverage, 4808,
90194 GIR_EraseRootFromParent_Done,
90195 // Label 5089: @239296
90196 GIM_Try, /*On fail goto*//*Label 5090*/ GIMT_Encode4(239333), // Rule ID 4815 //
90197 // MIs[0] Operand 1
90198 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
90199 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90200 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
90201 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90202 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90203 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90204 // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETLE:{ *:[Other] }) => (CMLEv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
90205 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv4i16rz),
90206 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90207 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90208 GIR_RootConstrainSelectedInstOperands,
90209 // GIR_Coverage, 4815,
90210 GIR_EraseRootFromParent_Done,
90211 // Label 5090: @239333
90212 GIM_Try, /*On fail goto*//*Label 5091*/ GIMT_Encode4(239362), // Rule ID 4724 //
90213 // MIs[0] Operand 1
90214 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
90215 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90216 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90217 // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETEQ:{ *:[Other] }) => (CMEQv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
90218 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i16),
90219 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90220 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90221 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90222 GIR_RootConstrainSelectedInstOperands,
90223 // GIR_Coverage, 4724,
90224 GIR_EraseRootFromParent_Done,
90225 // Label 5091: @239362
90226 GIM_Try, /*On fail goto*//*Label 5092*/ GIMT_Encode4(239391), // Rule ID 4731 //
90227 // MIs[0] Operand 1
90228 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
90229 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90230 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90231 // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETGT:{ *:[Other] }) => (CMGTv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
90232 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i16),
90233 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90234 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90235 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90236 GIR_RootConstrainSelectedInstOperands,
90237 // GIR_Coverage, 4731,
90238 GIR_EraseRootFromParent_Done,
90239 // Label 5092: @239391
90240 GIM_Try, /*On fail goto*//*Label 5093*/ GIMT_Encode4(239420), // Rule ID 4738 //
90241 // MIs[0] Operand 1
90242 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
90243 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90244 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90245 // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETGE:{ *:[Other] }) => (CMGEv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
90246 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i16),
90247 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90248 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90249 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90250 GIR_RootConstrainSelectedInstOperands,
90251 // GIR_Coverage, 4738,
90252 GIR_EraseRootFromParent_Done,
90253 // Label 5093: @239420
90254 GIM_Try, /*On fail goto*//*Label 5094*/ GIMT_Encode4(239449), // Rule ID 4745 //
90255 // MIs[0] Operand 1
90256 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
90257 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90258 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90259 // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETUGT:{ *:[Other] }) => (CMHIv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
90260 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv4i16),
90261 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90262 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90263 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90264 GIR_RootConstrainSelectedInstOperands,
90265 // GIR_Coverage, 4745,
90266 GIR_EraseRootFromParent_Done,
90267 // Label 5094: @239449
90268 GIM_Try, /*On fail goto*//*Label 5095*/ GIMT_Encode4(239478), // Rule ID 4752 //
90269 // MIs[0] Operand 1
90270 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
90271 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90272 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90273 // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETUGE:{ *:[Other] }) => (CMHSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
90274 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv4i16),
90275 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90276 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90277 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90278 GIR_RootConstrainSelectedInstOperands,
90279 // GIR_Coverage, 4752,
90280 GIR_EraseRootFromParent_Done,
90281 // Label 5095: @239478
90282 GIM_Try, /*On fail goto*//*Label 5096*/ GIMT_Encode4(239507), // Rule ID 4759 //
90283 // MIs[0] Operand 1
90284 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
90285 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90286 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90287 // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETLT:{ *:[Other] }) => (CMGTv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rm, V64:{ *:[v4i16] }:$Rn)
90288 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i16),
90289 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90290 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90291 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90292 GIR_RootConstrainSelectedInstOperands,
90293 // GIR_Coverage, 4759,
90294 GIR_EraseRootFromParent_Done,
90295 // Label 5096: @239507
90296 GIM_Try, /*On fail goto*//*Label 5097*/ GIMT_Encode4(239536), // Rule ID 4766 //
90297 // MIs[0] Operand 1
90298 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
90299 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90300 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90301 // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETLE:{ *:[Other] }) => (CMGEv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rm, V64:{ *:[v4i16] }:$Rn)
90302 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i16),
90303 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90304 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90305 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90306 GIR_RootConstrainSelectedInstOperands,
90307 // GIR_Coverage, 4766,
90308 GIR_EraseRootFromParent_Done,
90309 // Label 5097: @239536
90310 GIM_Try, /*On fail goto*//*Label 5098*/ GIMT_Encode4(239565), // Rule ID 4773 //
90311 // MIs[0] Operand 1
90312 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
90313 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90314 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90315 // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETULT:{ *:[Other] }) => (CMHIv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rm, V64:{ *:[v4i16] }:$Rn)
90316 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv4i16),
90317 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90318 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90319 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90320 GIR_RootConstrainSelectedInstOperands,
90321 // GIR_Coverage, 4773,
90322 GIR_EraseRootFromParent_Done,
90323 // Label 5098: @239565
90324 GIM_Try, /*On fail goto*//*Label 5099*/ GIMT_Encode4(239594), // Rule ID 4780 //
90325 // MIs[0] Operand 1
90326 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
90327 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90328 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90329 // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETULE:{ *:[Other] }) => (CMHSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rm, V64:{ *:[v4i16] }:$Rn)
90330 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv4i16),
90331 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90332 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90333 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90334 GIR_RootConstrainSelectedInstOperands,
90335 // GIR_Coverage, 4780,
90336 GIR_EraseRootFromParent_Done,
90337 // Label 5099: @239594
90338 GIM_Reject,
90339 // Label 5080: @239595
90340 GIM_Reject,
90341 // Label 5035: @239596
90342 GIM_Try, /*On fail goto*//*Label 5100*/ GIMT_Encode4(240243),
90343 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
90344 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
90345 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90346 GIM_Try, /*On fail goto*//*Label 5101*/ GIMT_Encode4(239648), // Rule ID 4825 //
90347 // MIs[0] Operand 1
90348 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
90349 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
90350 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90351 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90352 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90353 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90354 // (setcc:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn, SETEQ:{ *:[Other] }) => (CMEQv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
90355 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i32rz),
90356 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90357 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
90358 GIR_RootConstrainSelectedInstOperands,
90359 // GIR_Coverage, 4825,
90360 GIR_EraseRootFromParent_Done,
90361 // Label 5101: @239648
90362 GIM_Try, /*On fail goto*//*Label 5102*/ GIMT_Encode4(239685), // Rule ID 4832 //
90363 // MIs[0] Operand 1
90364 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
90365 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
90366 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90367 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90368 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90369 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90370 // (setcc:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn, SETGT:{ *:[Other] }) => (CMLTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
90371 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i32rz),
90372 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90373 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
90374 GIR_RootConstrainSelectedInstOperands,
90375 // GIR_Coverage, 4832,
90376 GIR_EraseRootFromParent_Done,
90377 // Label 5102: @239685
90378 GIM_Try, /*On fail goto*//*Label 5103*/ GIMT_Encode4(239722), // Rule ID 4839 //
90379 // MIs[0] Operand 1
90380 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
90381 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
90382 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90383 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90384 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90385 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90386 // (setcc:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn, SETGE:{ *:[Other] }) => (CMLEv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
90387 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv4i32rz),
90388 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90389 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
90390 GIR_RootConstrainSelectedInstOperands,
90391 // GIR_Coverage, 4839,
90392 GIR_EraseRootFromParent_Done,
90393 // Label 5103: @239722
90394 GIM_Try, /*On fail goto*//*Label 5104*/ GIMT_Encode4(239759), // Rule ID 4846 //
90395 // MIs[0] Operand 1
90396 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
90397 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
90398 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90399 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90400 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90401 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90402 // (setcc:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn, SETLT:{ *:[Other] }) => (CMGTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
90403 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i32rz),
90404 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90405 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
90406 GIR_RootConstrainSelectedInstOperands,
90407 // GIR_Coverage, 4846,
90408 GIR_EraseRootFromParent_Done,
90409 // Label 5104: @239759
90410 GIM_Try, /*On fail goto*//*Label 5105*/ GIMT_Encode4(239796), // Rule ID 4853 //
90411 // MIs[0] Operand 1
90412 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
90413 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
90414 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90415 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90416 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90417 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90418 // (setcc:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn, SETLE:{ *:[Other] }) => (CMGEv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
90419 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i32rz),
90420 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90421 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
90422 GIR_RootConstrainSelectedInstOperands,
90423 // GIR_Coverage, 4853,
90424 GIR_EraseRootFromParent_Done,
90425 // Label 5105: @239796
90426 GIM_Try, /*On fail goto*//*Label 5106*/ GIMT_Encode4(239833), // Rule ID 4790 //
90427 // MIs[0] Operand 1
90428 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
90429 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90430 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
90431 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90432 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90433 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90434 // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETEQ:{ *:[Other] }) => (CMEQv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
90435 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i32rz),
90436 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90437 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90438 GIR_RootConstrainSelectedInstOperands,
90439 // GIR_Coverage, 4790,
90440 GIR_EraseRootFromParent_Done,
90441 // Label 5106: @239833
90442 GIM_Try, /*On fail goto*//*Label 5107*/ GIMT_Encode4(239870), // Rule ID 4797 //
90443 // MIs[0] Operand 1
90444 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
90445 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90446 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
90447 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90448 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90449 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90450 // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETGT:{ *:[Other] }) => (CMGTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
90451 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i32rz),
90452 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90453 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90454 GIR_RootConstrainSelectedInstOperands,
90455 // GIR_Coverage, 4797,
90456 GIR_EraseRootFromParent_Done,
90457 // Label 5107: @239870
90458 GIM_Try, /*On fail goto*//*Label 5108*/ GIMT_Encode4(239907), // Rule ID 4804 //
90459 // MIs[0] Operand 1
90460 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
90461 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90462 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
90463 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90464 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90465 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90466 // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETGE:{ *:[Other] }) => (CMGEv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
90467 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i32rz),
90468 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90469 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90470 GIR_RootConstrainSelectedInstOperands,
90471 // GIR_Coverage, 4804,
90472 GIR_EraseRootFromParent_Done,
90473 // Label 5108: @239907
90474 GIM_Try, /*On fail goto*//*Label 5109*/ GIMT_Encode4(239944), // Rule ID 4811 //
90475 // MIs[0] Operand 1
90476 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
90477 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90478 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
90479 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90480 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90481 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90482 // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETLT:{ *:[Other] }) => (CMLTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
90483 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i32rz),
90484 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90485 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90486 GIR_RootConstrainSelectedInstOperands,
90487 // GIR_Coverage, 4811,
90488 GIR_EraseRootFromParent_Done,
90489 // Label 5109: @239944
90490 GIM_Try, /*On fail goto*//*Label 5110*/ GIMT_Encode4(239981), // Rule ID 4818 //
90491 // MIs[0] Operand 1
90492 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
90493 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90494 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
90495 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90496 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90497 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90498 // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETLE:{ *:[Other] }) => (CMLEv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
90499 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv4i32rz),
90500 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90501 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90502 GIR_RootConstrainSelectedInstOperands,
90503 // GIR_Coverage, 4818,
90504 GIR_EraseRootFromParent_Done,
90505 // Label 5110: @239981
90506 GIM_Try, /*On fail goto*//*Label 5111*/ GIMT_Encode4(240010), // Rule ID 4727 //
90507 // MIs[0] Operand 1
90508 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
90509 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90510 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90511 // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETEQ:{ *:[Other] }) => (CMEQv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
90512 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i32),
90513 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90514 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90515 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90516 GIR_RootConstrainSelectedInstOperands,
90517 // GIR_Coverage, 4727,
90518 GIR_EraseRootFromParent_Done,
90519 // Label 5111: @240010
90520 GIM_Try, /*On fail goto*//*Label 5112*/ GIMT_Encode4(240039), // Rule ID 4734 //
90521 // MIs[0] Operand 1
90522 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
90523 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90524 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90525 // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETGT:{ *:[Other] }) => (CMGTv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
90526 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i32),
90527 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90528 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90529 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90530 GIR_RootConstrainSelectedInstOperands,
90531 // GIR_Coverage, 4734,
90532 GIR_EraseRootFromParent_Done,
90533 // Label 5112: @240039
90534 GIM_Try, /*On fail goto*//*Label 5113*/ GIMT_Encode4(240068), // Rule ID 4741 //
90535 // MIs[0] Operand 1
90536 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
90537 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90538 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90539 // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETGE:{ *:[Other] }) => (CMGEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
90540 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i32),
90541 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90542 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90543 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90544 GIR_RootConstrainSelectedInstOperands,
90545 // GIR_Coverage, 4741,
90546 GIR_EraseRootFromParent_Done,
90547 // Label 5113: @240068
90548 GIM_Try, /*On fail goto*//*Label 5114*/ GIMT_Encode4(240097), // Rule ID 4748 //
90549 // MIs[0] Operand 1
90550 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
90551 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90552 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90553 // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETUGT:{ *:[Other] }) => (CMHIv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
90554 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv4i32),
90555 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90556 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90557 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90558 GIR_RootConstrainSelectedInstOperands,
90559 // GIR_Coverage, 4748,
90560 GIR_EraseRootFromParent_Done,
90561 // Label 5114: @240097
90562 GIM_Try, /*On fail goto*//*Label 5115*/ GIMT_Encode4(240126), // Rule ID 4755 //
90563 // MIs[0] Operand 1
90564 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
90565 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90566 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90567 // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETUGE:{ *:[Other] }) => (CMHSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
90568 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv4i32),
90569 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90570 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90571 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90572 GIR_RootConstrainSelectedInstOperands,
90573 // GIR_Coverage, 4755,
90574 GIR_EraseRootFromParent_Done,
90575 // Label 5115: @240126
90576 GIM_Try, /*On fail goto*//*Label 5116*/ GIMT_Encode4(240155), // Rule ID 4762 //
90577 // MIs[0] Operand 1
90578 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
90579 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90580 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90581 // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETLT:{ *:[Other] }) => (CMGTv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, V128:{ *:[v4i32] }:$Rn)
90582 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i32),
90583 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90584 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90585 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90586 GIR_RootConstrainSelectedInstOperands,
90587 // GIR_Coverage, 4762,
90588 GIR_EraseRootFromParent_Done,
90589 // Label 5116: @240155
90590 GIM_Try, /*On fail goto*//*Label 5117*/ GIMT_Encode4(240184), // Rule ID 4769 //
90591 // MIs[0] Operand 1
90592 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
90593 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90594 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90595 // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETLE:{ *:[Other] }) => (CMGEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, V128:{ *:[v4i32] }:$Rn)
90596 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i32),
90597 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90598 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90599 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90600 GIR_RootConstrainSelectedInstOperands,
90601 // GIR_Coverage, 4769,
90602 GIR_EraseRootFromParent_Done,
90603 // Label 5117: @240184
90604 GIM_Try, /*On fail goto*//*Label 5118*/ GIMT_Encode4(240213), // Rule ID 4776 //
90605 // MIs[0] Operand 1
90606 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
90607 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90608 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90609 // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETULT:{ *:[Other] }) => (CMHIv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, V128:{ *:[v4i32] }:$Rn)
90610 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv4i32),
90611 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90612 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90613 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90614 GIR_RootConstrainSelectedInstOperands,
90615 // GIR_Coverage, 4776,
90616 GIR_EraseRootFromParent_Done,
90617 // Label 5118: @240213
90618 GIM_Try, /*On fail goto*//*Label 5119*/ GIMT_Encode4(240242), // Rule ID 4783 //
90619 // MIs[0] Operand 1
90620 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
90621 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90622 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90623 // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETULE:{ *:[Other] }) => (CMHSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, V128:{ *:[v4i32] }:$Rn)
90624 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv4i32),
90625 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90626 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90627 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90628 GIR_RootConstrainSelectedInstOperands,
90629 // GIR_Coverage, 4783,
90630 GIR_EraseRootFromParent_Done,
90631 // Label 5119: @240242
90632 GIM_Reject,
90633 // Label 5100: @240243
90634 GIM_Reject,
90635 // Label 5036: @240244
90636 GIM_Try, /*On fail goto*//*Label 5120*/ GIMT_Encode4(240891),
90637 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
90638 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
90639 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90640 GIM_Try, /*On fail goto*//*Label 5121*/ GIMT_Encode4(240296), // Rule ID 4820 //
90641 // MIs[0] Operand 1
90642 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
90643 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
90644 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90645 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90646 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90647 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90648 // (setcc:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn, SETEQ:{ *:[Other] }) => (CMEQv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
90649 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i8rz),
90650 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90651 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
90652 GIR_RootConstrainSelectedInstOperands,
90653 // GIR_Coverage, 4820,
90654 GIR_EraseRootFromParent_Done,
90655 // Label 5121: @240296
90656 GIM_Try, /*On fail goto*//*Label 5122*/ GIMT_Encode4(240333), // Rule ID 4827 //
90657 // MIs[0] Operand 1
90658 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
90659 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
90660 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90661 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90662 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90663 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90664 // (setcc:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn, SETGT:{ *:[Other] }) => (CMLTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
90665 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i8rz),
90666 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90667 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
90668 GIR_RootConstrainSelectedInstOperands,
90669 // GIR_Coverage, 4827,
90670 GIR_EraseRootFromParent_Done,
90671 // Label 5122: @240333
90672 GIM_Try, /*On fail goto*//*Label 5123*/ GIMT_Encode4(240370), // Rule ID 4834 //
90673 // MIs[0] Operand 1
90674 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
90675 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
90676 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90677 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90678 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90679 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90680 // (setcc:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn, SETGE:{ *:[Other] }) => (CMLEv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
90681 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv8i8rz),
90682 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90683 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
90684 GIR_RootConstrainSelectedInstOperands,
90685 // GIR_Coverage, 4834,
90686 GIR_EraseRootFromParent_Done,
90687 // Label 5123: @240370
90688 GIM_Try, /*On fail goto*//*Label 5124*/ GIMT_Encode4(240407), // Rule ID 4841 //
90689 // MIs[0] Operand 1
90690 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
90691 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
90692 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90693 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90694 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90695 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90696 // (setcc:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn, SETLT:{ *:[Other] }) => (CMGTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
90697 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i8rz),
90698 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90699 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
90700 GIR_RootConstrainSelectedInstOperands,
90701 // GIR_Coverage, 4841,
90702 GIR_EraseRootFromParent_Done,
90703 // Label 5124: @240407
90704 GIM_Try, /*On fail goto*//*Label 5125*/ GIMT_Encode4(240444), // Rule ID 4848 //
90705 // MIs[0] Operand 1
90706 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
90707 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
90708 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90709 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90710 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90711 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90712 // (setcc:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn, SETLE:{ *:[Other] }) => (CMGEv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
90713 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i8rz),
90714 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90715 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
90716 GIR_RootConstrainSelectedInstOperands,
90717 // GIR_Coverage, 4848,
90718 GIR_EraseRootFromParent_Done,
90719 // Label 5125: @240444
90720 GIM_Try, /*On fail goto*//*Label 5126*/ GIMT_Encode4(240481), // Rule ID 4785 //
90721 // MIs[0] Operand 1
90722 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
90723 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90724 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
90725 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90726 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90727 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90728 // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETEQ:{ *:[Other] }) => (CMEQv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
90729 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i8rz),
90730 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90731 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90732 GIR_RootConstrainSelectedInstOperands,
90733 // GIR_Coverage, 4785,
90734 GIR_EraseRootFromParent_Done,
90735 // Label 5126: @240481
90736 GIM_Try, /*On fail goto*//*Label 5127*/ GIMT_Encode4(240518), // Rule ID 4792 //
90737 // MIs[0] Operand 1
90738 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
90739 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90740 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
90741 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90742 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90743 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90744 // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETGT:{ *:[Other] }) => (CMGTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
90745 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i8rz),
90746 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90747 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90748 GIR_RootConstrainSelectedInstOperands,
90749 // GIR_Coverage, 4792,
90750 GIR_EraseRootFromParent_Done,
90751 // Label 5127: @240518
90752 GIM_Try, /*On fail goto*//*Label 5128*/ GIMT_Encode4(240555), // Rule ID 4799 //
90753 // MIs[0] Operand 1
90754 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
90755 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90756 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
90757 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90758 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90759 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90760 // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETGE:{ *:[Other] }) => (CMGEv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
90761 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i8rz),
90762 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90763 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90764 GIR_RootConstrainSelectedInstOperands,
90765 // GIR_Coverage, 4799,
90766 GIR_EraseRootFromParent_Done,
90767 // Label 5128: @240555
90768 GIM_Try, /*On fail goto*//*Label 5129*/ GIMT_Encode4(240592), // Rule ID 4806 //
90769 // MIs[0] Operand 1
90770 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
90771 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90772 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
90773 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90774 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90775 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90776 // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETLT:{ *:[Other] }) => (CMLTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
90777 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i8rz),
90778 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90779 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90780 GIR_RootConstrainSelectedInstOperands,
90781 // GIR_Coverage, 4806,
90782 GIR_EraseRootFromParent_Done,
90783 // Label 5129: @240592
90784 GIM_Try, /*On fail goto*//*Label 5130*/ GIMT_Encode4(240629), // Rule ID 4813 //
90785 // MIs[0] Operand 1
90786 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
90787 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90788 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
90789 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90790 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90791 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90792 // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETLE:{ *:[Other] }) => (CMLEv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
90793 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv8i8rz),
90794 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90795 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90796 GIR_RootConstrainSelectedInstOperands,
90797 // GIR_Coverage, 4813,
90798 GIR_EraseRootFromParent_Done,
90799 // Label 5130: @240629
90800 GIM_Try, /*On fail goto*//*Label 5131*/ GIMT_Encode4(240658), // Rule ID 4722 //
90801 // MIs[0] Operand 1
90802 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
90803 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90804 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90805 // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETEQ:{ *:[Other] }) => (CMEQv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
90806 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i8),
90807 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90808 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90809 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90810 GIR_RootConstrainSelectedInstOperands,
90811 // GIR_Coverage, 4722,
90812 GIR_EraseRootFromParent_Done,
90813 // Label 5131: @240658
90814 GIM_Try, /*On fail goto*//*Label 5132*/ GIMT_Encode4(240687), // Rule ID 4729 //
90815 // MIs[0] Operand 1
90816 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
90817 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90818 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90819 // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETGT:{ *:[Other] }) => (CMGTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
90820 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i8),
90821 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90822 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90823 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90824 GIR_RootConstrainSelectedInstOperands,
90825 // GIR_Coverage, 4729,
90826 GIR_EraseRootFromParent_Done,
90827 // Label 5132: @240687
90828 GIM_Try, /*On fail goto*//*Label 5133*/ GIMT_Encode4(240716), // Rule ID 4736 //
90829 // MIs[0] Operand 1
90830 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
90831 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90832 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90833 // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETGE:{ *:[Other] }) => (CMGEv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
90834 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i8),
90835 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90836 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90837 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90838 GIR_RootConstrainSelectedInstOperands,
90839 // GIR_Coverage, 4736,
90840 GIR_EraseRootFromParent_Done,
90841 // Label 5133: @240716
90842 GIM_Try, /*On fail goto*//*Label 5134*/ GIMT_Encode4(240745), // Rule ID 4743 //
90843 // MIs[0] Operand 1
90844 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
90845 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90846 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90847 // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETUGT:{ *:[Other] }) => (CMHIv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
90848 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv8i8),
90849 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90850 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90851 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90852 GIR_RootConstrainSelectedInstOperands,
90853 // GIR_Coverage, 4743,
90854 GIR_EraseRootFromParent_Done,
90855 // Label 5134: @240745
90856 GIM_Try, /*On fail goto*//*Label 5135*/ GIMT_Encode4(240774), // Rule ID 4750 //
90857 // MIs[0] Operand 1
90858 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
90859 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90860 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90861 // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETUGE:{ *:[Other] }) => (CMHSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
90862 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv8i8),
90863 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90864 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90865 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90866 GIR_RootConstrainSelectedInstOperands,
90867 // GIR_Coverage, 4750,
90868 GIR_EraseRootFromParent_Done,
90869 // Label 5135: @240774
90870 GIM_Try, /*On fail goto*//*Label 5136*/ GIMT_Encode4(240803), // Rule ID 4757 //
90871 // MIs[0] Operand 1
90872 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
90873 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90874 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90875 // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETLT:{ *:[Other] }) => (CMGTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, V64:{ *:[v8i8] }:$Rn)
90876 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i8),
90877 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90878 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90879 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90880 GIR_RootConstrainSelectedInstOperands,
90881 // GIR_Coverage, 4757,
90882 GIR_EraseRootFromParent_Done,
90883 // Label 5136: @240803
90884 GIM_Try, /*On fail goto*//*Label 5137*/ GIMT_Encode4(240832), // Rule ID 4764 //
90885 // MIs[0] Operand 1
90886 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
90887 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90888 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90889 // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETLE:{ *:[Other] }) => (CMGEv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, V64:{ *:[v8i8] }:$Rn)
90890 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i8),
90891 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90892 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90893 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90894 GIR_RootConstrainSelectedInstOperands,
90895 // GIR_Coverage, 4764,
90896 GIR_EraseRootFromParent_Done,
90897 // Label 5137: @240832
90898 GIM_Try, /*On fail goto*//*Label 5138*/ GIMT_Encode4(240861), // Rule ID 4771 //
90899 // MIs[0] Operand 1
90900 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
90901 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90902 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90903 // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETULT:{ *:[Other] }) => (CMHIv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, V64:{ *:[v8i8] }:$Rn)
90904 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv8i8),
90905 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90906 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90907 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90908 GIR_RootConstrainSelectedInstOperands,
90909 // GIR_Coverage, 4771,
90910 GIR_EraseRootFromParent_Done,
90911 // Label 5138: @240861
90912 GIM_Try, /*On fail goto*//*Label 5139*/ GIMT_Encode4(240890), // Rule ID 4778 //
90913 // MIs[0] Operand 1
90914 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
90915 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90916 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
90917 // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETULE:{ *:[Other] }) => (CMHSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, V64:{ *:[v8i8] }:$Rn)
90918 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv8i8),
90919 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90920 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
90921 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
90922 GIR_RootConstrainSelectedInstOperands,
90923 // GIR_Coverage, 4778,
90924 GIR_EraseRootFromParent_Done,
90925 // Label 5139: @240890
90926 GIM_Reject,
90927 // Label 5120: @240891
90928 GIM_Reject,
90929 // Label 5037: @240892
90930 GIM_Try, /*On fail goto*//*Label 5140*/ GIMT_Encode4(241539),
90931 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
90932 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
90933 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90934 GIM_Try, /*On fail goto*//*Label 5141*/ GIMT_Encode4(240944), // Rule ID 4823 //
90935 // MIs[0] Operand 1
90936 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
90937 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
90938 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90939 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90940 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90941 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90942 // (setcc:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn, SETEQ:{ *:[Other] }) => (CMEQv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
90943 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i16rz),
90944 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90945 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
90946 GIR_RootConstrainSelectedInstOperands,
90947 // GIR_Coverage, 4823,
90948 GIR_EraseRootFromParent_Done,
90949 // Label 5141: @240944
90950 GIM_Try, /*On fail goto*//*Label 5142*/ GIMT_Encode4(240981), // Rule ID 4830 //
90951 // MIs[0] Operand 1
90952 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
90953 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
90954 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90955 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90956 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90957 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90958 // (setcc:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn, SETGT:{ *:[Other] }) => (CMLTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
90959 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i16rz),
90960 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90961 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
90962 GIR_RootConstrainSelectedInstOperands,
90963 // GIR_Coverage, 4830,
90964 GIR_EraseRootFromParent_Done,
90965 // Label 5142: @240981
90966 GIM_Try, /*On fail goto*//*Label 5143*/ GIMT_Encode4(241018), // Rule ID 4837 //
90967 // MIs[0] Operand 1
90968 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
90969 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
90970 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90971 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90972 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90973 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90974 // (setcc:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn, SETGE:{ *:[Other] }) => (CMLEv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
90975 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv8i16rz),
90976 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90977 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
90978 GIR_RootConstrainSelectedInstOperands,
90979 // GIR_Coverage, 4837,
90980 GIR_EraseRootFromParent_Done,
90981 // Label 5143: @241018
90982 GIM_Try, /*On fail goto*//*Label 5144*/ GIMT_Encode4(241055), // Rule ID 4844 //
90983 // MIs[0] Operand 1
90984 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
90985 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
90986 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
90987 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
90988 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
90989 GIM_CheckIsSafeToFold, /*NumInsns*/1,
90990 // (setcc:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn, SETLT:{ *:[Other] }) => (CMGTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
90991 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i16rz),
90992 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
90993 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
90994 GIR_RootConstrainSelectedInstOperands,
90995 // GIR_Coverage, 4844,
90996 GIR_EraseRootFromParent_Done,
90997 // Label 5144: @241055
90998 GIM_Try, /*On fail goto*//*Label 5145*/ GIMT_Encode4(241092), // Rule ID 4851 //
90999 // MIs[0] Operand 1
91000 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
91001 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
91002 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
91003 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
91004 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91005 GIM_CheckIsSafeToFold, /*NumInsns*/1,
91006 // (setcc:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn, SETLE:{ *:[Other] }) => (CMGEv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
91007 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i16rz),
91008 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91009 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
91010 GIR_RootConstrainSelectedInstOperands,
91011 // GIR_Coverage, 4851,
91012 GIR_EraseRootFromParent_Done,
91013 // Label 5145: @241092
91014 GIM_Try, /*On fail goto*//*Label 5146*/ GIMT_Encode4(241129), // Rule ID 4788 //
91015 // MIs[0] Operand 1
91016 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
91017 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91018 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
91019 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
91020 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
91021 GIM_CheckIsSafeToFold, /*NumInsns*/1,
91022 // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETEQ:{ *:[Other] }) => (CMEQv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
91023 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i16rz),
91024 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91025 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91026 GIR_RootConstrainSelectedInstOperands,
91027 // GIR_Coverage, 4788,
91028 GIR_EraseRootFromParent_Done,
91029 // Label 5146: @241129
91030 GIM_Try, /*On fail goto*//*Label 5147*/ GIMT_Encode4(241166), // Rule ID 4795 //
91031 // MIs[0] Operand 1
91032 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
91033 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91034 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
91035 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
91036 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
91037 GIM_CheckIsSafeToFold, /*NumInsns*/1,
91038 // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETGT:{ *:[Other] }) => (CMGTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
91039 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i16rz),
91040 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91041 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91042 GIR_RootConstrainSelectedInstOperands,
91043 // GIR_Coverage, 4795,
91044 GIR_EraseRootFromParent_Done,
91045 // Label 5147: @241166
91046 GIM_Try, /*On fail goto*//*Label 5148*/ GIMT_Encode4(241203), // Rule ID 4802 //
91047 // MIs[0] Operand 1
91048 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
91049 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91050 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
91051 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
91052 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
91053 GIM_CheckIsSafeToFold, /*NumInsns*/1,
91054 // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETGE:{ *:[Other] }) => (CMGEv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
91055 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i16rz),
91056 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91057 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91058 GIR_RootConstrainSelectedInstOperands,
91059 // GIR_Coverage, 4802,
91060 GIR_EraseRootFromParent_Done,
91061 // Label 5148: @241203
91062 GIM_Try, /*On fail goto*//*Label 5149*/ GIMT_Encode4(241240), // Rule ID 4809 //
91063 // MIs[0] Operand 1
91064 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
91065 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91066 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
91067 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
91068 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
91069 GIM_CheckIsSafeToFold, /*NumInsns*/1,
91070 // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETLT:{ *:[Other] }) => (CMLTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
91071 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i16rz),
91072 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91073 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91074 GIR_RootConstrainSelectedInstOperands,
91075 // GIR_Coverage, 4809,
91076 GIR_EraseRootFromParent_Done,
91077 // Label 5149: @241240
91078 GIM_Try, /*On fail goto*//*Label 5150*/ GIMT_Encode4(241277), // Rule ID 4816 //
91079 // MIs[0] Operand 1
91080 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
91081 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91082 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
91083 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
91084 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
91085 GIM_CheckIsSafeToFold, /*NumInsns*/1,
91086 // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETLE:{ *:[Other] }) => (CMLEv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
91087 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv8i16rz),
91088 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91089 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91090 GIR_RootConstrainSelectedInstOperands,
91091 // GIR_Coverage, 4816,
91092 GIR_EraseRootFromParent_Done,
91093 // Label 5150: @241277
91094 GIM_Try, /*On fail goto*//*Label 5151*/ GIMT_Encode4(241306), // Rule ID 4725 //
91095 // MIs[0] Operand 1
91096 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
91097 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91098 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91099 // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETEQ:{ *:[Other] }) => (CMEQv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
91100 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i16),
91101 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91102 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91103 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
91104 GIR_RootConstrainSelectedInstOperands,
91105 // GIR_Coverage, 4725,
91106 GIR_EraseRootFromParent_Done,
91107 // Label 5151: @241306
91108 GIM_Try, /*On fail goto*//*Label 5152*/ GIMT_Encode4(241335), // Rule ID 4732 //
91109 // MIs[0] Operand 1
91110 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
91111 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91112 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91113 // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETGT:{ *:[Other] }) => (CMGTv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
91114 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i16),
91115 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91116 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91117 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
91118 GIR_RootConstrainSelectedInstOperands,
91119 // GIR_Coverage, 4732,
91120 GIR_EraseRootFromParent_Done,
91121 // Label 5152: @241335
91122 GIM_Try, /*On fail goto*//*Label 5153*/ GIMT_Encode4(241364), // Rule ID 4739 //
91123 // MIs[0] Operand 1
91124 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
91125 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91126 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91127 // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETGE:{ *:[Other] }) => (CMGEv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
91128 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i16),
91129 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91130 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91131 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
91132 GIR_RootConstrainSelectedInstOperands,
91133 // GIR_Coverage, 4739,
91134 GIR_EraseRootFromParent_Done,
91135 // Label 5153: @241364
91136 GIM_Try, /*On fail goto*//*Label 5154*/ GIMT_Encode4(241393), // Rule ID 4746 //
91137 // MIs[0] Operand 1
91138 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
91139 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91140 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91141 // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETUGT:{ *:[Other] }) => (CMHIv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
91142 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv8i16),
91143 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91144 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91145 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
91146 GIR_RootConstrainSelectedInstOperands,
91147 // GIR_Coverage, 4746,
91148 GIR_EraseRootFromParent_Done,
91149 // Label 5154: @241393
91150 GIM_Try, /*On fail goto*//*Label 5155*/ GIMT_Encode4(241422), // Rule ID 4753 //
91151 // MIs[0] Operand 1
91152 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
91153 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91154 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91155 // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETUGE:{ *:[Other] }) => (CMHSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
91156 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv8i16),
91157 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91158 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91159 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
91160 GIR_RootConstrainSelectedInstOperands,
91161 // GIR_Coverage, 4753,
91162 GIR_EraseRootFromParent_Done,
91163 // Label 5155: @241422
91164 GIM_Try, /*On fail goto*//*Label 5156*/ GIMT_Encode4(241451), // Rule ID 4760 //
91165 // MIs[0] Operand 1
91166 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
91167 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91168 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91169 // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETLT:{ *:[Other] }) => (CMGTv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rm, V128:{ *:[v8i16] }:$Rn)
91170 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i16),
91171 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91172 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
91173 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91174 GIR_RootConstrainSelectedInstOperands,
91175 // GIR_Coverage, 4760,
91176 GIR_EraseRootFromParent_Done,
91177 // Label 5156: @241451
91178 GIM_Try, /*On fail goto*//*Label 5157*/ GIMT_Encode4(241480), // Rule ID 4767 //
91179 // MIs[0] Operand 1
91180 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
91181 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91182 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91183 // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETLE:{ *:[Other] }) => (CMGEv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rm, V128:{ *:[v8i16] }:$Rn)
91184 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i16),
91185 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91186 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
91187 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91188 GIR_RootConstrainSelectedInstOperands,
91189 // GIR_Coverage, 4767,
91190 GIR_EraseRootFromParent_Done,
91191 // Label 5157: @241480
91192 GIM_Try, /*On fail goto*//*Label 5158*/ GIMT_Encode4(241509), // Rule ID 4774 //
91193 // MIs[0] Operand 1
91194 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
91195 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91196 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91197 // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETULT:{ *:[Other] }) => (CMHIv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rm, V128:{ *:[v8i16] }:$Rn)
91198 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv8i16),
91199 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91200 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
91201 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91202 GIR_RootConstrainSelectedInstOperands,
91203 // GIR_Coverage, 4774,
91204 GIR_EraseRootFromParent_Done,
91205 // Label 5158: @241509
91206 GIM_Try, /*On fail goto*//*Label 5159*/ GIMT_Encode4(241538), // Rule ID 4781 //
91207 // MIs[0] Operand 1
91208 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
91209 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91210 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91211 // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETULE:{ *:[Other] }) => (CMHSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rm, V128:{ *:[v8i16] }:$Rn)
91212 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv8i16),
91213 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91214 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
91215 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91216 GIR_RootConstrainSelectedInstOperands,
91217 // GIR_Coverage, 4781,
91218 GIR_EraseRootFromParent_Done,
91219 // Label 5159: @241538
91220 GIM_Reject,
91221 // Label 5140: @241539
91222 GIM_Reject,
91223 // Label 5038: @241540
91224 GIM_Try, /*On fail goto*//*Label 5160*/ GIMT_Encode4(242187),
91225 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
91226 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
91227 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91228 GIM_Try, /*On fail goto*//*Label 5161*/ GIMT_Encode4(241592), // Rule ID 4821 //
91229 // MIs[0] Operand 1
91230 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
91231 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
91232 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
91233 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
91234 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91235 GIM_CheckIsSafeToFold, /*NumInsns*/1,
91236 // (setcc:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn, SETEQ:{ *:[Other] }) => (CMEQv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
91237 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv16i8rz),
91238 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91239 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
91240 GIR_RootConstrainSelectedInstOperands,
91241 // GIR_Coverage, 4821,
91242 GIR_EraseRootFromParent_Done,
91243 // Label 5161: @241592
91244 GIM_Try, /*On fail goto*//*Label 5162*/ GIMT_Encode4(241629), // Rule ID 4828 //
91245 // MIs[0] Operand 1
91246 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
91247 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
91248 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
91249 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
91250 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91251 GIM_CheckIsSafeToFold, /*NumInsns*/1,
91252 // (setcc:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn, SETGT:{ *:[Other] }) => (CMLTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
91253 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv16i8rz),
91254 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91255 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
91256 GIR_RootConstrainSelectedInstOperands,
91257 // GIR_Coverage, 4828,
91258 GIR_EraseRootFromParent_Done,
91259 // Label 5162: @241629
91260 GIM_Try, /*On fail goto*//*Label 5163*/ GIMT_Encode4(241666), // Rule ID 4835 //
91261 // MIs[0] Operand 1
91262 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
91263 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
91264 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
91265 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
91266 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91267 GIM_CheckIsSafeToFold, /*NumInsns*/1,
91268 // (setcc:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn, SETGE:{ *:[Other] }) => (CMLEv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
91269 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv16i8rz),
91270 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91271 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
91272 GIR_RootConstrainSelectedInstOperands,
91273 // GIR_Coverage, 4835,
91274 GIR_EraseRootFromParent_Done,
91275 // Label 5163: @241666
91276 GIM_Try, /*On fail goto*//*Label 5164*/ GIMT_Encode4(241703), // Rule ID 4842 //
91277 // MIs[0] Operand 1
91278 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
91279 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
91280 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
91281 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
91282 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91283 GIM_CheckIsSafeToFold, /*NumInsns*/1,
91284 // (setcc:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn, SETLT:{ *:[Other] }) => (CMGTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
91285 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv16i8rz),
91286 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91287 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
91288 GIR_RootConstrainSelectedInstOperands,
91289 // GIR_Coverage, 4842,
91290 GIR_EraseRootFromParent_Done,
91291 // Label 5164: @241703
91292 GIM_Try, /*On fail goto*//*Label 5165*/ GIMT_Encode4(241740), // Rule ID 4849 //
91293 // MIs[0] Operand 1
91294 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
91295 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
91296 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
91297 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
91298 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91299 GIM_CheckIsSafeToFold, /*NumInsns*/1,
91300 // (setcc:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn, SETLE:{ *:[Other] }) => (CMGEv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
91301 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv16i8rz),
91302 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91303 GIR_RootToRootCopy, /*OpIdx*/3, // Rn
91304 GIR_RootConstrainSelectedInstOperands,
91305 // GIR_Coverage, 4849,
91306 GIR_EraseRootFromParent_Done,
91307 // Label 5165: @241740
91308 GIM_Try, /*On fail goto*//*Label 5166*/ GIMT_Encode4(241777), // Rule ID 4786 //
91309 // MIs[0] Operand 1
91310 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
91311 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91312 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
91313 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
91314 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
91315 GIM_CheckIsSafeToFold, /*NumInsns*/1,
91316 // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETEQ:{ *:[Other] }) => (CMEQv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
91317 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv16i8rz),
91318 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91319 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91320 GIR_RootConstrainSelectedInstOperands,
91321 // GIR_Coverage, 4786,
91322 GIR_EraseRootFromParent_Done,
91323 // Label 5166: @241777
91324 GIM_Try, /*On fail goto*//*Label 5167*/ GIMT_Encode4(241814), // Rule ID 4793 //
91325 // MIs[0] Operand 1
91326 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
91327 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91328 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
91329 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
91330 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
91331 GIM_CheckIsSafeToFold, /*NumInsns*/1,
91332 // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETGT:{ *:[Other] }) => (CMGTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
91333 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv16i8rz),
91334 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91335 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91336 GIR_RootConstrainSelectedInstOperands,
91337 // GIR_Coverage, 4793,
91338 GIR_EraseRootFromParent_Done,
91339 // Label 5167: @241814
91340 GIM_Try, /*On fail goto*//*Label 5168*/ GIMT_Encode4(241851), // Rule ID 4800 //
91341 // MIs[0] Operand 1
91342 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
91343 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91344 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
91345 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
91346 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
91347 GIM_CheckIsSafeToFold, /*NumInsns*/1,
91348 // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETGE:{ *:[Other] }) => (CMGEv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
91349 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv16i8rz),
91350 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91351 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91352 GIR_RootConstrainSelectedInstOperands,
91353 // GIR_Coverage, 4800,
91354 GIR_EraseRootFromParent_Done,
91355 // Label 5168: @241851
91356 GIM_Try, /*On fail goto*//*Label 5169*/ GIMT_Encode4(241888), // Rule ID 4807 //
91357 // MIs[0] Operand 1
91358 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
91359 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91360 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
91361 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
91362 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
91363 GIM_CheckIsSafeToFold, /*NumInsns*/1,
91364 // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETLT:{ *:[Other] }) => (CMLTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
91365 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv16i8rz),
91366 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91367 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91368 GIR_RootConstrainSelectedInstOperands,
91369 // GIR_Coverage, 4807,
91370 GIR_EraseRootFromParent_Done,
91371 // Label 5169: @241888
91372 GIM_Try, /*On fail goto*//*Label 5170*/ GIMT_Encode4(241925), // Rule ID 4814 //
91373 // MIs[0] Operand 1
91374 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
91375 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91376 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
91377 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
91378 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
91379 GIM_CheckIsSafeToFold, /*NumInsns*/1,
91380 // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETLE:{ *:[Other] }) => (CMLEv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
91381 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv16i8rz),
91382 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91383 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91384 GIR_RootConstrainSelectedInstOperands,
91385 // GIR_Coverage, 4814,
91386 GIR_EraseRootFromParent_Done,
91387 // Label 5170: @241925
91388 GIM_Try, /*On fail goto*//*Label 5171*/ GIMT_Encode4(241954), // Rule ID 4723 //
91389 // MIs[0] Operand 1
91390 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
91391 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91392 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91393 // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETEQ:{ *:[Other] }) => (CMEQv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
91394 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv16i8),
91395 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91396 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91397 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
91398 GIR_RootConstrainSelectedInstOperands,
91399 // GIR_Coverage, 4723,
91400 GIR_EraseRootFromParent_Done,
91401 // Label 5171: @241954
91402 GIM_Try, /*On fail goto*//*Label 5172*/ GIMT_Encode4(241983), // Rule ID 4730 //
91403 // MIs[0] Operand 1
91404 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
91405 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91406 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91407 // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETGT:{ *:[Other] }) => (CMGTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
91408 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv16i8),
91409 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91410 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91411 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
91412 GIR_RootConstrainSelectedInstOperands,
91413 // GIR_Coverage, 4730,
91414 GIR_EraseRootFromParent_Done,
91415 // Label 5172: @241983
91416 GIM_Try, /*On fail goto*//*Label 5173*/ GIMT_Encode4(242012), // Rule ID 4737 //
91417 // MIs[0] Operand 1
91418 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
91419 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91420 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91421 // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETGE:{ *:[Other] }) => (CMGEv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
91422 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv16i8),
91423 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91424 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91425 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
91426 GIR_RootConstrainSelectedInstOperands,
91427 // GIR_Coverage, 4737,
91428 GIR_EraseRootFromParent_Done,
91429 // Label 5173: @242012
91430 GIM_Try, /*On fail goto*//*Label 5174*/ GIMT_Encode4(242041), // Rule ID 4744 //
91431 // MIs[0] Operand 1
91432 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
91433 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91434 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91435 // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETUGT:{ *:[Other] }) => (CMHIv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
91436 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv16i8),
91437 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91438 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91439 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
91440 GIR_RootConstrainSelectedInstOperands,
91441 // GIR_Coverage, 4744,
91442 GIR_EraseRootFromParent_Done,
91443 // Label 5174: @242041
91444 GIM_Try, /*On fail goto*//*Label 5175*/ GIMT_Encode4(242070), // Rule ID 4751 //
91445 // MIs[0] Operand 1
91446 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
91447 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91448 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91449 // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETUGE:{ *:[Other] }) => (CMHSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
91450 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv16i8),
91451 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91452 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91453 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
91454 GIR_RootConstrainSelectedInstOperands,
91455 // GIR_Coverage, 4751,
91456 GIR_EraseRootFromParent_Done,
91457 // Label 5175: @242070
91458 GIM_Try, /*On fail goto*//*Label 5176*/ GIMT_Encode4(242099), // Rule ID 4758 //
91459 // MIs[0] Operand 1
91460 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
91461 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91462 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91463 // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETLT:{ *:[Other] }) => (CMGTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, V128:{ *:[v16i8] }:$Rn)
91464 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv16i8),
91465 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91466 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
91467 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91468 GIR_RootConstrainSelectedInstOperands,
91469 // GIR_Coverage, 4758,
91470 GIR_EraseRootFromParent_Done,
91471 // Label 5176: @242099
91472 GIM_Try, /*On fail goto*//*Label 5177*/ GIMT_Encode4(242128), // Rule ID 4765 //
91473 // MIs[0] Operand 1
91474 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
91475 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91476 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91477 // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETLE:{ *:[Other] }) => (CMGEv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, V128:{ *:[v16i8] }:$Rn)
91478 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv16i8),
91479 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91480 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
91481 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91482 GIR_RootConstrainSelectedInstOperands,
91483 // GIR_Coverage, 4765,
91484 GIR_EraseRootFromParent_Done,
91485 // Label 5177: @242128
91486 GIM_Try, /*On fail goto*//*Label 5178*/ GIMT_Encode4(242157), // Rule ID 4772 //
91487 // MIs[0] Operand 1
91488 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
91489 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91490 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91491 // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETULT:{ *:[Other] }) => (CMHIv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, V128:{ *:[v16i8] }:$Rn)
91492 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv16i8),
91493 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91494 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
91495 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91496 GIR_RootConstrainSelectedInstOperands,
91497 // GIR_Coverage, 4772,
91498 GIR_EraseRootFromParent_Done,
91499 // Label 5178: @242157
91500 GIM_Try, /*On fail goto*//*Label 5179*/ GIMT_Encode4(242186), // Rule ID 4779 //
91501 // MIs[0] Operand 1
91502 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
91503 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91504 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91505 // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETULE:{ *:[Other] }) => (CMHSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, V128:{ *:[v16i8] }:$Rn)
91506 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv16i8),
91507 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91508 GIR_RootToRootCopy, /*OpIdx*/3, // Rm
91509 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
91510 GIR_RootConstrainSelectedInstOperands,
91511 // GIR_Coverage, 4779,
91512 GIR_EraseRootFromParent_Done,
91513 // Label 5179: @242186
91514 GIM_Reject,
91515 // Label 5160: @242187
91516 GIM_Reject,
91517 // Label 5039: @242188
91518 GIM_Reject,
91519 // Label 46: @242189
91520 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(24), /*)*//*default:*//*Label 5192*/ GIMT_Encode4(242674),
91521 /*GILLT_nxv1s1*//*Label 5180*/ GIMT_Encode4(242248),
91522 /*GILLT_nxv2s1*//*Label 5181*/ GIMT_Encode4(242277),
91523 /*GILLT_nxv2s16*//*Label 5182*/ GIMT_Encode4(242306),
91524 /*GILLT_nxv2s32*//*Label 5183*/ GIMT_Encode4(242335),
91525 /*GILLT_nxv2s64*//*Label 5184*/ GIMT_Encode4(242364),
91526 /*GILLT_nxv4s1*//*Label 5185*/ GIMT_Encode4(242414),
91527 /*GILLT_nxv4s16*//*Label 5186*/ GIMT_Encode4(242443),
91528 /*GILLT_nxv4s32*//*Label 5187*/ GIMT_Encode4(242472),
91529 /*GILLT_nxv8s1*//*Label 5188*/ GIMT_Encode4(242522),
91530 /*GILLT_nxv8s16*//*Label 5189*/ GIMT_Encode4(242551),
91531 /*GILLT_nxv16s1*//*Label 5190*/ GIMT_Encode4(242616),
91532 /*GILLT_nxv16s8*//*Label 5191*/ GIMT_Encode4(242645),
91533 // Label 5180: @242248
91534 GIM_Try, /*On fail goto*//*Label 5193*/ GIMT_Encode4(242276), // Rule ID 8098 //
91535 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
91536 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1,
91537 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
91538 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
91539 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
91540 // (vselect:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3) => (SEL_PPPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
91541 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
91542 GIR_RootConstrainSelectedInstOperands,
91543 // GIR_Coverage, 8098,
91544 GIR_Done,
91545 // Label 5193: @242276
91546 GIM_Reject,
91547 // Label 5181: @242277
91548 GIM_Try, /*On fail goto*//*Label 5194*/ GIMT_Encode4(242305), // Rule ID 8097 //
91549 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
91550 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
91551 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
91552 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
91553 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
91554 // (vselect:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3) => (SEL_PPPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
91555 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
91556 GIR_RootConstrainSelectedInstOperands,
91557 // GIR_Coverage, 8097,
91558 GIR_Done,
91559 // Label 5194: @242305
91560 GIM_Reject,
91561 // Label 5182: @242306
91562 GIM_Try, /*On fail goto*//*Label 5195*/ GIMT_Encode4(242334), // Rule ID 2644 //
91563 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
91564 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
91565 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
91566 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
91567 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
91568 // (vselect:{ *:[nxv2f16] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3) => (SEL_ZPZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3)
91569 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_D),
91570 GIR_RootConstrainSelectedInstOperands,
91571 // GIR_Coverage, 2644,
91572 GIR_Done,
91573 // Label 5195: @242334
91574 GIM_Reject,
91575 // Label 5183: @242335
91576 GIM_Try, /*On fail goto*//*Label 5196*/ GIMT_Encode4(242363), // Rule ID 2645 //
91577 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
91578 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
91579 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
91580 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
91581 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
91582 // (vselect:{ *:[nxv2f32] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3) => (SEL_ZPZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3)
91583 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_D),
91584 GIR_RootConstrainSelectedInstOperands,
91585 // GIR_Coverage, 2645,
91586 GIR_Done,
91587 // Label 5196: @242363
91588 GIM_Reject,
91589 // Label 5184: @242364
91590 GIM_Try, /*On fail goto*//*Label 5197*/ GIMT_Encode4(242413),
91591 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
91592 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
91593 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
91594 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
91595 GIM_Try, /*On fail goto*//*Label 5198*/ GIMT_Encode4(242397), // Rule ID 2640 //
91596 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
91597 // (vselect:{ *:[nxv2i64] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3) => (SEL_ZPZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
91598 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_D),
91599 GIR_RootConstrainSelectedInstOperands,
91600 // GIR_Coverage, 2640,
91601 GIR_Done,
91602 // Label 5198: @242397
91603 GIM_Try, /*On fail goto*//*Label 5199*/ GIMT_Encode4(242412), // Rule ID 2646 //
91604 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
91605 // (vselect:{ *:[nxv2f64] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3) => (SEL_ZPZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
91606 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_D),
91607 GIR_RootConstrainSelectedInstOperands,
91608 // GIR_Coverage, 2646,
91609 GIR_Done,
91610 // Label 5199: @242412
91611 GIM_Reject,
91612 // Label 5197: @242413
91613 GIM_Reject,
91614 // Label 5185: @242414
91615 GIM_Try, /*On fail goto*//*Label 5200*/ GIMT_Encode4(242442), // Rule ID 8096 //
91616 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
91617 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
91618 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
91619 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
91620 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
91621 // (vselect:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3) => (SEL_PPPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
91622 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
91623 GIR_RootConstrainSelectedInstOperands,
91624 // GIR_Coverage, 8096,
91625 GIR_Done,
91626 // Label 5200: @242442
91627 GIM_Reject,
91628 // Label 5186: @242443
91629 GIM_Try, /*On fail goto*//*Label 5201*/ GIMT_Encode4(242471), // Rule ID 2642 //
91630 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
91631 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
91632 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
91633 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
91634 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
91635 // (vselect:{ *:[nxv4f16] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3) => (SEL_ZPZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3)
91636 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_S),
91637 GIR_RootConstrainSelectedInstOperands,
91638 // GIR_Coverage, 2642,
91639 GIR_Done,
91640 // Label 5201: @242471
91641 GIM_Reject,
91642 // Label 5187: @242472
91643 GIM_Try, /*On fail goto*//*Label 5202*/ GIMT_Encode4(242521),
91644 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
91645 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
91646 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
91647 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
91648 GIM_Try, /*On fail goto*//*Label 5203*/ GIMT_Encode4(242505), // Rule ID 2639 //
91649 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
91650 // (vselect:{ *:[nxv4i32] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3) => (SEL_ZPZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
91651 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_S),
91652 GIR_RootConstrainSelectedInstOperands,
91653 // GIR_Coverage, 2639,
91654 GIR_Done,
91655 // Label 5203: @242505
91656 GIM_Try, /*On fail goto*//*Label 5204*/ GIMT_Encode4(242520), // Rule ID 2643 //
91657 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
91658 // (vselect:{ *:[nxv4f32] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3) => (SEL_ZPZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
91659 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_S),
91660 GIR_RootConstrainSelectedInstOperands,
91661 // GIR_Coverage, 2643,
91662 GIR_Done,
91663 // Label 5204: @242520
91664 GIM_Reject,
91665 // Label 5202: @242521
91666 GIM_Reject,
91667 // Label 5188: @242522
91668 GIM_Try, /*On fail goto*//*Label 5205*/ GIMT_Encode4(242550), // Rule ID 8095 //
91669 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
91670 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
91671 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
91672 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
91673 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
91674 // (vselect:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3) => (SEL_PPPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
91675 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
91676 GIR_RootConstrainSelectedInstOperands,
91677 // GIR_Coverage, 8095,
91678 GIR_Done,
91679 // Label 5205: @242550
91680 GIM_Reject,
91681 // Label 5189: @242551
91682 GIM_Try, /*On fail goto*//*Label 5206*/ GIMT_Encode4(242615),
91683 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
91684 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
91685 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
91686 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
91687 GIM_Try, /*On fail goto*//*Label 5207*/ GIMT_Encode4(242584), // Rule ID 2638 //
91688 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
91689 // (vselect:{ *:[nxv8i16] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SEL_ZPZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
91690 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_H),
91691 GIR_RootConstrainSelectedInstOperands,
91692 // GIR_Coverage, 2638,
91693 GIR_Done,
91694 // Label 5207: @242584
91695 GIM_Try, /*On fail goto*//*Label 5208*/ GIMT_Encode4(242599), // Rule ID 2641 //
91696 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
91697 // (vselect:{ *:[nxv8f16] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3) => (SEL_ZPZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
91698 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_H),
91699 GIR_RootConstrainSelectedInstOperands,
91700 // GIR_Coverage, 2641,
91701 GIR_Done,
91702 // Label 5208: @242599
91703 GIM_Try, /*On fail goto*//*Label 5209*/ GIMT_Encode4(242614), // Rule ID 2647 //
91704 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
91705 // (vselect:{ *:[nxv8bf16] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2, nxv8bf16:{ *:[nxv8bf16] }:$Op3) => (SEL_ZPZZ_H:{ *:[nxv8bf16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2, ?:{ *:[nxv8bf16] }:$Op3)
91706 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_H),
91707 GIR_RootConstrainSelectedInstOperands,
91708 // GIR_Coverage, 2647,
91709 GIR_Done,
91710 // Label 5209: @242614
91711 GIM_Reject,
91712 // Label 5206: @242615
91713 GIM_Reject,
91714 // Label 5190: @242616
91715 GIM_Try, /*On fail goto*//*Label 5210*/ GIMT_Encode4(242644), // Rule ID 8094 //
91716 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
91717 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
91718 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
91719 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
91720 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
91721 // (vselect:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3) => (SEL_PPPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
91722 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
91723 GIR_RootConstrainSelectedInstOperands,
91724 // GIR_Coverage, 8094,
91725 GIR_Done,
91726 // Label 5210: @242644
91727 GIM_Reject,
91728 // Label 5191: @242645
91729 GIM_Try, /*On fail goto*//*Label 5211*/ GIMT_Encode4(242673), // Rule ID 2637 //
91730 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
91731 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
91732 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
91733 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
91734 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
91735 // (vselect:{ *:[nxv16i8] } nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SEL_ZPZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
91736 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_B),
91737 GIR_RootConstrainSelectedInstOperands,
91738 // GIR_Coverage, 2637,
91739 GIR_Done,
91740 // Label 5211: @242673
91741 GIM_Reject,
91742 // Label 5192: @242674
91743 GIM_Reject,
91744 // Label 47: @242675
91745 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(12), /*)*//*default:*//*Label 5216*/ GIMT_Encode4(243158),
91746 /*GILLT_s64*//*Label 5212*/ GIMT_Encode4(242722), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
91747 /*GILLT_v4s32*//*Label 5213*/ GIMT_Encode4(242753), GIMT_Encode4(0),
91748 /*GILLT_v8s16*//*Label 5214*/ GIMT_Encode4(242888),
91749 /*GILLT_v16s8*//*Label 5215*/ GIMT_Encode4(243023),
91750 // Label 5212: @242722
91751 GIM_Try, /*On fail goto*//*Label 5217*/ GIMT_Encode4(242752), // Rule ID 139 //
91752 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
91753 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
91754 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
91755 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
91756 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
91757 // (mulhu:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (UMULHrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
91758 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMULHrr),
91759 GIR_RootConstrainSelectedInstOperands,
91760 // GIR_Coverage, 139,
91761 GIR_Done,
91762 // Label 5217: @242752
91763 GIM_Reject,
91764 // Label 5213: @242753
91765 GIM_Try, /*On fail goto*//*Label 5218*/ GIMT_Encode4(242887), // Rule ID 6130 //
91766 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
91767 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
91768 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91769 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91770 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91771 // (mulhu:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UZP2v4i32:{ *:[v4i32] } (UMULLv2i32_v2i64:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rm, dsub:{ *:[i32] })), (UMULLv4i32_v2i64:{ *:[f128] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))
91772 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
91773 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
91774 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
91775 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
91776 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i32_v2i64),
91777 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91778 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
91779 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
91780 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
91781 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
91782 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91783 GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
91784 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
91785 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
91786 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
91787 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91788 GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
91789 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
91790 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
91791 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMULLv2i32_v2i64),
91792 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91793 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
91794 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
91795 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
91796 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i32),
91797 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91798 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
91799 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
91800 GIR_RootConstrainSelectedInstOperands,
91801 // GIR_Coverage, 6130,
91802 GIR_EraseRootFromParent_Done,
91803 // Label 5218: @242887
91804 GIM_Reject,
91805 // Label 5214: @242888
91806 GIM_Try, /*On fail goto*//*Label 5219*/ GIMT_Encode4(243022), // Rule ID 6129 //
91807 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
91808 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
91809 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91810 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91811 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91812 // (mulhu:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UZP2v8i16:{ *:[v8i16] } (UMULLv4i16_v4i32:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rm, dsub:{ *:[i32] })), (UMULLv8i16_v4i32:{ *:[f128] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))
91813 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
91814 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
91815 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
91816 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
91817 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMULLv8i16_v4i32),
91818 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91819 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
91820 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
91821 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
91822 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
91823 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91824 GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
91825 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
91826 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
91827 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
91828 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91829 GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
91830 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
91831 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
91832 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i16_v4i32),
91833 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91834 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
91835 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
91836 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
91837 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
91838 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91839 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
91840 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
91841 GIR_RootConstrainSelectedInstOperands,
91842 // GIR_Coverage, 6129,
91843 GIR_EraseRootFromParent_Done,
91844 // Label 5219: @243022
91845 GIM_Reject,
91846 // Label 5215: @243023
91847 GIM_Try, /*On fail goto*//*Label 5220*/ GIMT_Encode4(243157), // Rule ID 6128 //
91848 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
91849 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
91850 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91851 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91852 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91853 // (mulhu:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UZP2v16i8:{ *:[v16i8] } (UMULLv8i8_v8i16:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rm, dsub:{ *:[i32] })), (UMULLv16i8_v8i16:{ *:[f128] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))
91854 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
91855 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
91856 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
91857 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
91858 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMULLv16i8_v8i16),
91859 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91860 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
91861 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
91862 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
91863 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
91864 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91865 GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
91866 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
91867 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
91868 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
91869 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91870 GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
91871 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
91872 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
91873 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMULLv8i8_v8i16),
91874 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91875 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
91876 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
91877 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
91878 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v16i8),
91879 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91880 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
91881 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
91882 GIR_RootConstrainSelectedInstOperands,
91883 // GIR_Coverage, 6128,
91884 GIR_EraseRootFromParent_Done,
91885 // Label 5220: @243157
91886 GIM_Reject,
91887 // Label 5216: @243158
91888 GIM_Reject,
91889 // Label 48: @243159
91890 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(12), /*)*//*default:*//*Label 5225*/ GIMT_Encode4(243642),
91891 /*GILLT_s64*//*Label 5221*/ GIMT_Encode4(243206), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
91892 /*GILLT_v4s32*//*Label 5222*/ GIMT_Encode4(243237), GIMT_Encode4(0),
91893 /*GILLT_v8s16*//*Label 5223*/ GIMT_Encode4(243372),
91894 /*GILLT_v16s8*//*Label 5224*/ GIMT_Encode4(243507),
91895 // Label 5221: @243206
91896 GIM_Try, /*On fail goto*//*Label 5226*/ GIMT_Encode4(243236), // Rule ID 138 //
91897 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
91898 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
91899 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
91900 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
91901 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
91902 // (mulhs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SMULHrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
91903 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMULHrr),
91904 GIR_RootConstrainSelectedInstOperands,
91905 // GIR_Coverage, 138,
91906 GIR_Done,
91907 // Label 5226: @243236
91908 GIM_Reject,
91909 // Label 5222: @243237
91910 GIM_Try, /*On fail goto*//*Label 5227*/ GIMT_Encode4(243371), // Rule ID 6127 //
91911 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
91912 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
91913 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91914 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91915 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91916 // (mulhs:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UZP2v4i32:{ *:[v4i32] } (SMULLv2i32_v2i64:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rm, dsub:{ *:[i32] })), (SMULLv4i32_v2i64:{ *:[f128] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))
91917 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
91918 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
91919 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
91920 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
91921 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i32_v2i64),
91922 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91923 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
91924 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
91925 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
91926 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
91927 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91928 GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
91929 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
91930 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
91931 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
91932 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91933 GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
91934 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
91935 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
91936 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMULLv2i32_v2i64),
91937 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91938 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
91939 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
91940 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
91941 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i32),
91942 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91943 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
91944 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
91945 GIR_RootConstrainSelectedInstOperands,
91946 // GIR_Coverage, 6127,
91947 GIR_EraseRootFromParent_Done,
91948 // Label 5227: @243371
91949 GIM_Reject,
91950 // Label 5223: @243372
91951 GIM_Try, /*On fail goto*//*Label 5228*/ GIMT_Encode4(243506), // Rule ID 6126 //
91952 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
91953 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
91954 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91955 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91956 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91957 // (mulhs:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UZP2v8i16:{ *:[v8i16] } (SMULLv4i16_v4i32:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rm, dsub:{ *:[i32] })), (SMULLv8i16_v4i32:{ *:[f128] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))
91958 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
91959 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
91960 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
91961 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
91962 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SMULLv8i16_v4i32),
91963 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91964 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
91965 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
91966 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
91967 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
91968 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91969 GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
91970 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
91971 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
91972 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
91973 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91974 GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
91975 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
91976 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
91977 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i16_v4i32),
91978 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
91979 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
91980 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
91981 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
91982 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
91983 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
91984 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
91985 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
91986 GIR_RootConstrainSelectedInstOperands,
91987 // GIR_Coverage, 6126,
91988 GIR_EraseRootFromParent_Done,
91989 // Label 5228: @243506
91990 GIM_Reject,
91991 // Label 5224: @243507
91992 GIM_Try, /*On fail goto*//*Label 5229*/ GIMT_Encode4(243641), // Rule ID 6125 //
91993 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
91994 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
91995 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91996 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91997 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
91998 // (mulhs:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UZP2v16i8:{ *:[v16i8] } (SMULLv8i8_v8i16:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rm, dsub:{ *:[i32] })), (SMULLv16i8_v8i16:{ *:[f128] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))
91999 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
92000 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
92001 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
92002 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
92003 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SMULLv16i8_v8i16),
92004 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
92005 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
92006 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
92007 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
92008 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
92009 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
92010 GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
92011 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
92012 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
92013 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
92014 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
92015 GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
92016 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
92017 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
92018 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMULLv8i8_v8i16),
92019 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
92020 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
92021 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
92022 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
92023 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v16i8),
92024 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
92025 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
92026 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
92027 GIR_RootConstrainSelectedInstOperands,
92028 // GIR_Coverage, 6125,
92029 GIR_EraseRootFromParent_Done,
92030 // Label 5229: @243641
92031 GIM_Reject,
92032 // Label 5225: @243642
92033 GIM_Reject,
92034 // Label 49: @243643
92035 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 5241*/ GIMT_Encode4(244072),
92036 /*GILLT_v2s32*//*Label 5230*/ GIMT_Encode4(243730),
92037 /*GILLT_v2s64*//*Label 5231*/ GIMT_Encode4(243764),
92038 /*GILLT_v4s16*//*Label 5232*/ GIMT_Encode4(243798),
92039 /*GILLT_v4s32*//*Label 5233*/ GIMT_Encode4(243832),
92040 /*GILLT_v8s8*//*Label 5234*/ GIMT_Encode4(243866),
92041 /*GILLT_v8s16*//*Label 5235*/ GIMT_Encode4(243900),
92042 /*GILLT_v16s8*//*Label 5236*/ GIMT_Encode4(243934), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
92043 /*GILLT_nxv2s64*//*Label 5237*/ GIMT_Encode4(243968), GIMT_Encode4(0), GIMT_Encode4(0),
92044 /*GILLT_nxv4s32*//*Label 5238*/ GIMT_Encode4(243994), GIMT_Encode4(0),
92045 /*GILLT_nxv8s16*//*Label 5239*/ GIMT_Encode4(244020), GIMT_Encode4(0),
92046 /*GILLT_nxv16s8*//*Label 5240*/ GIMT_Encode4(244046),
92047 // Label 5230: @243730
92048 GIM_Try, /*On fail goto*//*Label 5242*/ GIMT_Encode4(243763), // Rule ID 4671 //
92049 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92050 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
92051 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
92052 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92053 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92054 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92055 // (uaddsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (UQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
92056 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv2i32),
92057 GIR_RootConstrainSelectedInstOperands,
92058 // GIR_Coverage, 4671,
92059 GIR_Done,
92060 // Label 5242: @243763
92061 GIM_Reject,
92062 // Label 5231: @243764
92063 GIM_Try, /*On fail goto*//*Label 5243*/ GIMT_Encode4(243797), // Rule ID 4675 //
92064 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92065 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
92066 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
92067 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92068 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92069 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92070 // (uaddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (UQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
92071 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv2i64),
92072 GIR_RootConstrainSelectedInstOperands,
92073 // GIR_Coverage, 4675,
92074 GIR_Done,
92075 // Label 5243: @243797
92076 GIM_Reject,
92077 // Label 5232: @243798
92078 GIM_Try, /*On fail goto*//*Label 5244*/ GIMT_Encode4(243831), // Rule ID 4670 //
92079 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92080 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
92081 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
92082 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92083 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92084 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92085 // (uaddsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (UQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
92086 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv4i16),
92087 GIR_RootConstrainSelectedInstOperands,
92088 // GIR_Coverage, 4670,
92089 GIR_Done,
92090 // Label 5244: @243831
92091 GIM_Reject,
92092 // Label 5233: @243832
92093 GIM_Try, /*On fail goto*//*Label 5245*/ GIMT_Encode4(243865), // Rule ID 4674 //
92094 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92095 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
92096 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
92097 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92098 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92099 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92100 // (uaddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (UQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
92101 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv4i32),
92102 GIR_RootConstrainSelectedInstOperands,
92103 // GIR_Coverage, 4674,
92104 GIR_Done,
92105 // Label 5245: @243865
92106 GIM_Reject,
92107 // Label 5234: @243866
92108 GIM_Try, /*On fail goto*//*Label 5246*/ GIMT_Encode4(243899), // Rule ID 4669 //
92109 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92110 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
92111 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
92112 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92113 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92114 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92115 // (uaddsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) => (UQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS)
92116 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv8i8),
92117 GIR_RootConstrainSelectedInstOperands,
92118 // GIR_Coverage, 4669,
92119 GIR_Done,
92120 // Label 5246: @243899
92121 GIM_Reject,
92122 // Label 5235: @243900
92123 GIM_Try, /*On fail goto*//*Label 5247*/ GIMT_Encode4(243933), // Rule ID 4673 //
92124 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92125 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
92126 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
92127 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92128 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92129 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92130 // (uaddsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (UQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
92131 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv8i16),
92132 GIR_RootConstrainSelectedInstOperands,
92133 // GIR_Coverage, 4673,
92134 GIR_Done,
92135 // Label 5247: @243933
92136 GIM_Reject,
92137 // Label 5236: @243934
92138 GIM_Try, /*On fail goto*//*Label 5248*/ GIMT_Encode4(243967), // Rule ID 4672 //
92139 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92140 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
92141 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
92142 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92143 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92144 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92145 // (uaddsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) => (UQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS)
92146 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv16i8),
92147 GIR_RootConstrainSelectedInstOperands,
92148 // GIR_Coverage, 4672,
92149 GIR_Done,
92150 // Label 5248: @243967
92151 GIM_Reject,
92152 // Label 5237: @243968
92153 GIM_Try, /*On fail goto*//*Label 5249*/ GIMT_Encode4(243993), // Rule ID 7111 //
92154 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
92155 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
92156 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
92157 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
92158 // (uaddsat:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (UQADD_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
92159 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZZZ_D),
92160 GIR_RootConstrainSelectedInstOperands,
92161 // GIR_Coverage, 7111,
92162 GIR_Done,
92163 // Label 5249: @243993
92164 GIM_Reject,
92165 // Label 5238: @243994
92166 GIM_Try, /*On fail goto*//*Label 5250*/ GIMT_Encode4(244019), // Rule ID 7110 //
92167 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
92168 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
92169 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
92170 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
92171 // (uaddsat:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (UQADD_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
92172 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZZZ_S),
92173 GIR_RootConstrainSelectedInstOperands,
92174 // GIR_Coverage, 7110,
92175 GIR_Done,
92176 // Label 5250: @244019
92177 GIM_Reject,
92178 // Label 5239: @244020
92179 GIM_Try, /*On fail goto*//*Label 5251*/ GIMT_Encode4(244045), // Rule ID 7109 //
92180 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
92181 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
92182 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
92183 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
92184 // (uaddsat:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (UQADD_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
92185 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZZZ_H),
92186 GIR_RootConstrainSelectedInstOperands,
92187 // GIR_Coverage, 7109,
92188 GIR_Done,
92189 // Label 5251: @244045
92190 GIM_Reject,
92191 // Label 5240: @244046
92192 GIM_Try, /*On fail goto*//*Label 5252*/ GIMT_Encode4(244071), // Rule ID 7108 //
92193 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
92194 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
92195 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
92196 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
92197 // (uaddsat:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (UQADD_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
92198 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZZZ_B),
92199 GIR_RootConstrainSelectedInstOperands,
92200 // GIR_Coverage, 7108,
92201 GIR_Done,
92202 // Label 5252: @244071
92203 GIM_Reject,
92204 // Label 5241: @244072
92205 GIM_Reject,
92206 // Label 50: @244073
92207 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 5264*/ GIMT_Encode4(244502),
92208 /*GILLT_v2s32*//*Label 5253*/ GIMT_Encode4(244160),
92209 /*GILLT_v2s64*//*Label 5254*/ GIMT_Encode4(244194),
92210 /*GILLT_v4s16*//*Label 5255*/ GIMT_Encode4(244228),
92211 /*GILLT_v4s32*//*Label 5256*/ GIMT_Encode4(244262),
92212 /*GILLT_v8s8*//*Label 5257*/ GIMT_Encode4(244296),
92213 /*GILLT_v8s16*//*Label 5258*/ GIMT_Encode4(244330),
92214 /*GILLT_v16s8*//*Label 5259*/ GIMT_Encode4(244364), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
92215 /*GILLT_nxv2s64*//*Label 5260*/ GIMT_Encode4(244398), GIMT_Encode4(0), GIMT_Encode4(0),
92216 /*GILLT_nxv4s32*//*Label 5261*/ GIMT_Encode4(244424), GIMT_Encode4(0),
92217 /*GILLT_nxv8s16*//*Label 5262*/ GIMT_Encode4(244450), GIMT_Encode4(0),
92218 /*GILLT_nxv16s8*//*Label 5263*/ GIMT_Encode4(244476),
92219 // Label 5253: @244160
92220 GIM_Try, /*On fail goto*//*Label 5265*/ GIMT_Encode4(244193), // Rule ID 2403 //
92221 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92222 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
92223 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
92224 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92225 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92226 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92227 // (saddsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (SQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
92228 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv2i32),
92229 GIR_RootConstrainSelectedInstOperands,
92230 // GIR_Coverage, 2403,
92231 GIR_Done,
92232 // Label 5265: @244193
92233 GIM_Reject,
92234 // Label 5254: @244194
92235 GIM_Try, /*On fail goto*//*Label 5266*/ GIMT_Encode4(244227), // Rule ID 2407 //
92236 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92237 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
92238 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
92239 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92240 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92241 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92242 // (saddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (SQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
92243 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv2i64),
92244 GIR_RootConstrainSelectedInstOperands,
92245 // GIR_Coverage, 2407,
92246 GIR_Done,
92247 // Label 5266: @244227
92248 GIM_Reject,
92249 // Label 5255: @244228
92250 GIM_Try, /*On fail goto*//*Label 5267*/ GIMT_Encode4(244261), // Rule ID 2402 //
92251 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92252 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
92253 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
92254 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92255 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92256 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92257 // (saddsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (SQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
92258 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv4i16),
92259 GIR_RootConstrainSelectedInstOperands,
92260 // GIR_Coverage, 2402,
92261 GIR_Done,
92262 // Label 5267: @244261
92263 GIM_Reject,
92264 // Label 5256: @244262
92265 GIM_Try, /*On fail goto*//*Label 5268*/ GIMT_Encode4(244295), // Rule ID 2406 //
92266 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92267 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
92268 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
92269 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92270 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92271 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92272 // (saddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (SQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
92273 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv4i32),
92274 GIR_RootConstrainSelectedInstOperands,
92275 // GIR_Coverage, 2406,
92276 GIR_Done,
92277 // Label 5268: @244295
92278 GIM_Reject,
92279 // Label 5257: @244296
92280 GIM_Try, /*On fail goto*//*Label 5269*/ GIMT_Encode4(244329), // Rule ID 2401 //
92281 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92282 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
92283 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
92284 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92285 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92286 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92287 // (saddsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) => (SQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS)
92288 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv8i8),
92289 GIR_RootConstrainSelectedInstOperands,
92290 // GIR_Coverage, 2401,
92291 GIR_Done,
92292 // Label 5269: @244329
92293 GIM_Reject,
92294 // Label 5258: @244330
92295 GIM_Try, /*On fail goto*//*Label 5270*/ GIMT_Encode4(244363), // Rule ID 2405 //
92296 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92297 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
92298 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
92299 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92300 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92301 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92302 // (saddsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (SQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
92303 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv8i16),
92304 GIR_RootConstrainSelectedInstOperands,
92305 // GIR_Coverage, 2405,
92306 GIR_Done,
92307 // Label 5270: @244363
92308 GIM_Reject,
92309 // Label 5259: @244364
92310 GIM_Try, /*On fail goto*//*Label 5271*/ GIMT_Encode4(244397), // Rule ID 2404 //
92311 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92312 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
92313 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
92314 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92315 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92316 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92317 // (saddsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) => (SQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS)
92318 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv16i8),
92319 GIR_RootConstrainSelectedInstOperands,
92320 // GIR_Coverage, 2404,
92321 GIR_Done,
92322 // Label 5271: @244397
92323 GIM_Reject,
92324 // Label 5260: @244398
92325 GIM_Try, /*On fail goto*//*Label 5272*/ GIMT_Encode4(244423), // Rule ID 7107 //
92326 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
92327 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
92328 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
92329 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
92330 // (saddsat:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (SQADD_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
92331 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZZZ_D),
92332 GIR_RootConstrainSelectedInstOperands,
92333 // GIR_Coverage, 7107,
92334 GIR_Done,
92335 // Label 5272: @244423
92336 GIM_Reject,
92337 // Label 5261: @244424
92338 GIM_Try, /*On fail goto*//*Label 5273*/ GIMT_Encode4(244449), // Rule ID 7106 //
92339 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
92340 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
92341 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
92342 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
92343 // (saddsat:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SQADD_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
92344 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZZZ_S),
92345 GIR_RootConstrainSelectedInstOperands,
92346 // GIR_Coverage, 7106,
92347 GIR_Done,
92348 // Label 5273: @244449
92349 GIM_Reject,
92350 // Label 5262: @244450
92351 GIM_Try, /*On fail goto*//*Label 5274*/ GIMT_Encode4(244475), // Rule ID 7105 //
92352 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
92353 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
92354 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
92355 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
92356 // (saddsat:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SQADD_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
92357 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZZZ_H),
92358 GIR_RootConstrainSelectedInstOperands,
92359 // GIR_Coverage, 7105,
92360 GIR_Done,
92361 // Label 5274: @244475
92362 GIM_Reject,
92363 // Label 5263: @244476
92364 GIM_Try, /*On fail goto*//*Label 5275*/ GIMT_Encode4(244501), // Rule ID 7104 //
92365 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
92366 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
92367 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
92368 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
92369 // (saddsat:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SQADD_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
92370 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZZZ_B),
92371 GIR_RootConstrainSelectedInstOperands,
92372 // GIR_Coverage, 7104,
92373 GIR_Done,
92374 // Label 5275: @244501
92375 GIM_Reject,
92376 // Label 5264: @244502
92377 GIM_Reject,
92378 // Label 51: @244503
92379 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 5287*/ GIMT_Encode4(244932),
92380 /*GILLT_v2s32*//*Label 5276*/ GIMT_Encode4(244590),
92381 /*GILLT_v2s64*//*Label 5277*/ GIMT_Encode4(244624),
92382 /*GILLT_v4s16*//*Label 5278*/ GIMT_Encode4(244658),
92383 /*GILLT_v4s32*//*Label 5279*/ GIMT_Encode4(244692),
92384 /*GILLT_v8s8*//*Label 5280*/ GIMT_Encode4(244726),
92385 /*GILLT_v8s16*//*Label 5281*/ GIMT_Encode4(244760),
92386 /*GILLT_v16s8*//*Label 5282*/ GIMT_Encode4(244794), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
92387 /*GILLT_nxv2s64*//*Label 5283*/ GIMT_Encode4(244828), GIMT_Encode4(0), GIMT_Encode4(0),
92388 /*GILLT_nxv4s32*//*Label 5284*/ GIMT_Encode4(244854), GIMT_Encode4(0),
92389 /*GILLT_nxv8s16*//*Label 5285*/ GIMT_Encode4(244880), GIMT_Encode4(0),
92390 /*GILLT_nxv16s8*//*Label 5286*/ GIMT_Encode4(244906),
92391 // Label 5276: @244590
92392 GIM_Try, /*On fail goto*//*Label 5288*/ GIMT_Encode4(244623), // Rule ID 4685 //
92393 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92394 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
92395 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
92396 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92397 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92398 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92399 // (usubsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (UQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
92400 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv2i32),
92401 GIR_RootConstrainSelectedInstOperands,
92402 // GIR_Coverage, 4685,
92403 GIR_Done,
92404 // Label 5288: @244623
92405 GIM_Reject,
92406 // Label 5277: @244624
92407 GIM_Try, /*On fail goto*//*Label 5289*/ GIMT_Encode4(244657), // Rule ID 4689 //
92408 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92409 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
92410 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
92411 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92412 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92413 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92414 // (usubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (UQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
92415 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv2i64),
92416 GIR_RootConstrainSelectedInstOperands,
92417 // GIR_Coverage, 4689,
92418 GIR_Done,
92419 // Label 5289: @244657
92420 GIM_Reject,
92421 // Label 5278: @244658
92422 GIM_Try, /*On fail goto*//*Label 5290*/ GIMT_Encode4(244691), // Rule ID 4684 //
92423 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92424 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
92425 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
92426 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92427 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92428 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92429 // (usubsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (UQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
92430 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv4i16),
92431 GIR_RootConstrainSelectedInstOperands,
92432 // GIR_Coverage, 4684,
92433 GIR_Done,
92434 // Label 5290: @244691
92435 GIM_Reject,
92436 // Label 5279: @244692
92437 GIM_Try, /*On fail goto*//*Label 5291*/ GIMT_Encode4(244725), // Rule ID 4688 //
92438 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92439 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
92440 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
92441 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92442 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92443 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92444 // (usubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (UQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
92445 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv4i32),
92446 GIR_RootConstrainSelectedInstOperands,
92447 // GIR_Coverage, 4688,
92448 GIR_Done,
92449 // Label 5291: @244725
92450 GIM_Reject,
92451 // Label 5280: @244726
92452 GIM_Try, /*On fail goto*//*Label 5292*/ GIMT_Encode4(244759), // Rule ID 4683 //
92453 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92454 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
92455 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
92456 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92457 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92458 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92459 // (usubsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) => (UQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS)
92460 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv8i8),
92461 GIR_RootConstrainSelectedInstOperands,
92462 // GIR_Coverage, 4683,
92463 GIR_Done,
92464 // Label 5292: @244759
92465 GIM_Reject,
92466 // Label 5281: @244760
92467 GIM_Try, /*On fail goto*//*Label 5293*/ GIMT_Encode4(244793), // Rule ID 4687 //
92468 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92469 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
92470 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
92471 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92472 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92473 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92474 // (usubsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (UQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
92475 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv8i16),
92476 GIR_RootConstrainSelectedInstOperands,
92477 // GIR_Coverage, 4687,
92478 GIR_Done,
92479 // Label 5293: @244793
92480 GIM_Reject,
92481 // Label 5282: @244794
92482 GIM_Try, /*On fail goto*//*Label 5294*/ GIMT_Encode4(244827), // Rule ID 4686 //
92483 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92484 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
92485 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
92486 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92487 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92488 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92489 // (usubsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) => (UQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS)
92490 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv16i8),
92491 GIR_RootConstrainSelectedInstOperands,
92492 // GIR_Coverage, 4686,
92493 GIR_Done,
92494 // Label 5294: @244827
92495 GIM_Reject,
92496 // Label 5283: @244828
92497 GIM_Try, /*On fail goto*//*Label 5295*/ GIMT_Encode4(244853), // Rule ID 7119 //
92498 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
92499 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
92500 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
92501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
92502 // (usubsat:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (UQSUB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
92503 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZZZ_D),
92504 GIR_RootConstrainSelectedInstOperands,
92505 // GIR_Coverage, 7119,
92506 GIR_Done,
92507 // Label 5295: @244853
92508 GIM_Reject,
92509 // Label 5284: @244854
92510 GIM_Try, /*On fail goto*//*Label 5296*/ GIMT_Encode4(244879), // Rule ID 7118 //
92511 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
92512 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
92513 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
92514 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
92515 // (usubsat:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (UQSUB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
92516 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZZZ_S),
92517 GIR_RootConstrainSelectedInstOperands,
92518 // GIR_Coverage, 7118,
92519 GIR_Done,
92520 // Label 5296: @244879
92521 GIM_Reject,
92522 // Label 5285: @244880
92523 GIM_Try, /*On fail goto*//*Label 5297*/ GIMT_Encode4(244905), // Rule ID 7117 //
92524 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
92525 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
92526 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
92527 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
92528 // (usubsat:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (UQSUB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
92529 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZZZ_H),
92530 GIR_RootConstrainSelectedInstOperands,
92531 // GIR_Coverage, 7117,
92532 GIR_Done,
92533 // Label 5297: @244905
92534 GIM_Reject,
92535 // Label 5286: @244906
92536 GIM_Try, /*On fail goto*//*Label 5298*/ GIMT_Encode4(244931), // Rule ID 7116 //
92537 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
92538 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
92539 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
92540 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
92541 // (usubsat:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (UQSUB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
92542 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZZZ_B),
92543 GIR_RootConstrainSelectedInstOperands,
92544 // GIR_Coverage, 7116,
92545 GIR_Done,
92546 // Label 5298: @244931
92547 GIM_Reject,
92548 // Label 5287: @244932
92549 GIM_Reject,
92550 // Label 52: @244933
92551 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 5310*/ GIMT_Encode4(245362),
92552 /*GILLT_v2s32*//*Label 5299*/ GIMT_Encode4(245020),
92553 /*GILLT_v2s64*//*Label 5300*/ GIMT_Encode4(245054),
92554 /*GILLT_v4s16*//*Label 5301*/ GIMT_Encode4(245088),
92555 /*GILLT_v4s32*//*Label 5302*/ GIMT_Encode4(245122),
92556 /*GILLT_v8s8*//*Label 5303*/ GIMT_Encode4(245156),
92557 /*GILLT_v8s16*//*Label 5304*/ GIMT_Encode4(245190),
92558 /*GILLT_v16s8*//*Label 5305*/ GIMT_Encode4(245224), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
92559 /*GILLT_nxv2s64*//*Label 5306*/ GIMT_Encode4(245258), GIMT_Encode4(0), GIMT_Encode4(0),
92560 /*GILLT_nxv4s32*//*Label 5307*/ GIMT_Encode4(245284), GIMT_Encode4(0),
92561 /*GILLT_nxv8s16*//*Label 5308*/ GIMT_Encode4(245310), GIMT_Encode4(0),
92562 /*GILLT_nxv16s8*//*Label 5309*/ GIMT_Encode4(245336),
92563 // Label 5299: @245020
92564 GIM_Try, /*On fail goto*//*Label 5311*/ GIMT_Encode4(245053), // Rule ID 4678 //
92565 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92566 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
92567 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
92568 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92569 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92570 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92571 // (ssubsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS) => (SQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
92572 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv2i32),
92573 GIR_RootConstrainSelectedInstOperands,
92574 // GIR_Coverage, 4678,
92575 GIR_Done,
92576 // Label 5311: @245053
92577 GIM_Reject,
92578 // Label 5300: @245054
92579 GIM_Try, /*On fail goto*//*Label 5312*/ GIMT_Encode4(245087), // Rule ID 4682 //
92580 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92581 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
92582 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
92583 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92584 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92585 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92586 // (ssubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS) => (SQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
92587 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv2i64),
92588 GIR_RootConstrainSelectedInstOperands,
92589 // GIR_Coverage, 4682,
92590 GIR_Done,
92591 // Label 5312: @245087
92592 GIM_Reject,
92593 // Label 5301: @245088
92594 GIM_Try, /*On fail goto*//*Label 5313*/ GIMT_Encode4(245121), // Rule ID 4677 //
92595 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92596 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
92597 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
92598 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92599 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92600 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92601 // (ssubsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS) => (SQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
92602 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv4i16),
92603 GIR_RootConstrainSelectedInstOperands,
92604 // GIR_Coverage, 4677,
92605 GIR_Done,
92606 // Label 5313: @245121
92607 GIM_Reject,
92608 // Label 5302: @245122
92609 GIM_Try, /*On fail goto*//*Label 5314*/ GIMT_Encode4(245155), // Rule ID 4681 //
92610 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92611 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
92612 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
92613 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92614 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92615 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92616 // (ssubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS) => (SQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
92617 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv4i32),
92618 GIR_RootConstrainSelectedInstOperands,
92619 // GIR_Coverage, 4681,
92620 GIR_Done,
92621 // Label 5314: @245155
92622 GIM_Reject,
92623 // Label 5303: @245156
92624 GIM_Try, /*On fail goto*//*Label 5315*/ GIMT_Encode4(245189), // Rule ID 4676 //
92625 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92626 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
92627 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
92628 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92629 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92630 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92631 // (ssubsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS) => (SQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$LHS, V64:{ *:[v8i8] }:$RHS)
92632 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv8i8),
92633 GIR_RootConstrainSelectedInstOperands,
92634 // GIR_Coverage, 4676,
92635 GIR_Done,
92636 // Label 5315: @245189
92637 GIM_Reject,
92638 // Label 5304: @245190
92639 GIM_Try, /*On fail goto*//*Label 5316*/ GIMT_Encode4(245223), // Rule ID 4680 //
92640 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92641 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
92642 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
92643 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92644 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92645 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92646 // (ssubsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS) => (SQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
92647 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv8i16),
92648 GIR_RootConstrainSelectedInstOperands,
92649 // GIR_Coverage, 4680,
92650 GIR_Done,
92651 // Label 5316: @245223
92652 GIM_Reject,
92653 // Label 5305: @245224
92654 GIM_Try, /*On fail goto*//*Label 5317*/ GIMT_Encode4(245257), // Rule ID 4679 //
92655 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92656 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
92657 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
92658 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92659 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92660 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92661 // (ssubsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS) => (SQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$LHS, V128:{ *:[v16i8] }:$RHS)
92662 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv16i8),
92663 GIR_RootConstrainSelectedInstOperands,
92664 // GIR_Coverage, 4679,
92665 GIR_Done,
92666 // Label 5317: @245257
92667 GIM_Reject,
92668 // Label 5306: @245258
92669 GIM_Try, /*On fail goto*//*Label 5318*/ GIMT_Encode4(245283), // Rule ID 7115 //
92670 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
92671 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
92672 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
92673 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
92674 // (ssubsat:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (SQSUB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
92675 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZZZ_D),
92676 GIR_RootConstrainSelectedInstOperands,
92677 // GIR_Coverage, 7115,
92678 GIR_Done,
92679 // Label 5318: @245283
92680 GIM_Reject,
92681 // Label 5307: @245284
92682 GIM_Try, /*On fail goto*//*Label 5319*/ GIMT_Encode4(245309), // Rule ID 7114 //
92683 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
92684 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
92685 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
92686 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
92687 // (ssubsat:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (SQSUB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
92688 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZZZ_S),
92689 GIR_RootConstrainSelectedInstOperands,
92690 // GIR_Coverage, 7114,
92691 GIR_Done,
92692 // Label 5319: @245309
92693 GIM_Reject,
92694 // Label 5308: @245310
92695 GIM_Try, /*On fail goto*//*Label 5320*/ GIMT_Encode4(245335), // Rule ID 7113 //
92696 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
92697 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
92698 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
92699 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
92700 // (ssubsat:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (SQSUB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
92701 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZZZ_H),
92702 GIR_RootConstrainSelectedInstOperands,
92703 // GIR_Coverage, 7113,
92704 GIR_Done,
92705 // Label 5320: @245335
92706 GIM_Reject,
92707 // Label 5309: @245336
92708 GIM_Try, /*On fail goto*//*Label 5321*/ GIMT_Encode4(245361), // Rule ID 7112 //
92709 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
92710 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
92711 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
92712 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
92713 // (ssubsat:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (SQSUB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
92714 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZZZ_B),
92715 GIR_RootConstrainSelectedInstOperands,
92716 // GIR_Coverage, 7112,
92717 GIR_Done,
92718 // Label 5321: @245361
92719 GIM_Reject,
92720 // Label 5310: @245362
92721 GIM_Reject,
92722 // Label 53: @245363
92723 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(22), /*)*//*default:*//*Label 5333*/ GIMT_Encode4(248036),
92724 /*GILLT_s16*//*Label 5322*/ GIMT_Encode4(245458),
92725 /*GILLT_s32*//*Label 5323*/ GIMT_Encode4(245684),
92726 /*GILLT_s64*//*Label 5324*/ GIMT_Encode4(246038), GIMT_Encode4(0),
92727 /*GILLT_v2s32*//*Label 5325*/ GIMT_Encode4(246210),
92728 /*GILLT_v2s64*//*Label 5326*/ GIMT_Encode4(246248),
92729 /*GILLT_v4s16*//*Label 5327*/ GIMT_Encode4(246286),
92730 /*GILLT_v4s32*//*Label 5328*/ GIMT_Encode4(246324), GIMT_Encode4(0),
92731 /*GILLT_v8s16*//*Label 5329*/ GIMT_Encode4(246362), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
92732 /*GILLT_nxv2s64*//*Label 5330*/ GIMT_Encode4(247937), GIMT_Encode4(0), GIMT_Encode4(0),
92733 /*GILLT_nxv4s32*//*Label 5331*/ GIMT_Encode4(247963), GIMT_Encode4(0),
92734 /*GILLT_nxv8s16*//*Label 5332*/ GIMT_Encode4(247989),
92735 // Label 5322: @245458
92736 GIM_Try, /*On fail goto*//*Label 5334*/ GIMT_Encode4(245683),
92737 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
92738 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
92739 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
92740 GIM_Try, /*On fail goto*//*Label 5335*/ GIMT_Encode4(245564), // Rule ID 6608 //
92741 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
92742 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
92743 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
92744 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
92745 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92746 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
92747 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
92748 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
92749 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
92750 // MIs[2] Rn
92751 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
92752 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
92753 GIM_CheckIsSafeToFold, /*NumInsns*/2,
92754 // (fadd:{ *:[f16] } (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] }))
92755 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
92756 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
92757 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
92758 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
92759 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
92760 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
92761 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i16p),
92762 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
92763 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
92764 GIR_RootConstrainSelectedInstOperands,
92765 // GIR_Coverage, 6608,
92766 GIR_EraseRootFromParent_Done,
92767 // Label 5335: @245564
92768 GIM_Try, /*On fail goto*//*Label 5336*/ GIMT_Encode4(245655), // Rule ID 13194 //
92769 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
92770 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
92771 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
92772 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
92773 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92774 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
92775 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
92776 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
92777 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
92778 // MIs[2] Rn
92779 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
92780 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
92781 GIM_CheckIsSafeToFold, /*NumInsns*/2,
92782 // (fadd:{ *:[f16] } (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] }))
92783 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
92784 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
92785 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
92786 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
92787 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
92788 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
92789 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i16p),
92790 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
92791 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
92792 GIR_RootConstrainSelectedInstOperands,
92793 // GIR_Coverage, 13194,
92794 GIR_EraseRootFromParent_Done,
92795 // Label 5336: @245655
92796 GIM_Try, /*On fail goto*//*Label 5337*/ GIMT_Encode4(245682), // Rule ID 578 //
92797 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
92798 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
92799 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
92800 // (fadd:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FADDHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
92801 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDHrr),
92802 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
92803 GIR_RootConstrainSelectedInstOperands,
92804 // GIR_Coverage, 578,
92805 GIR_Done,
92806 // Label 5337: @245682
92807 GIM_Reject,
92808 // Label 5334: @245683
92809 GIM_Reject,
92810 // Label 5323: @245684
92811 GIM_Try, /*On fail goto*//*Label 5338*/ GIMT_Encode4(246037),
92812 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
92813 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
92814 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
92815 GIM_Try, /*On fail goto*//*Label 5339*/ GIMT_Encode4(245790), // Rule ID 6606 //
92816 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
92817 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
92818 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
92819 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
92820 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92821 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
92822 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
92823 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
92824 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
92825 // MIs[2] Rn
92826 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
92827 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
92828 GIM_CheckIsSafeToFold, /*NumInsns*/2,
92829 // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] }))
92830 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
92831 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
92832 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
92833 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
92834 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
92835 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
92836 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
92837 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
92838 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
92839 GIR_RootConstrainSelectedInstOperands,
92840 // GIR_Coverage, 6606,
92841 GIR_EraseRootFromParent_Done,
92842 // Label 5339: @245790
92843 GIM_Try, /*On fail goto*//*Label 5340*/ GIMT_Encode4(245854), // Rule ID 12355 //
92844 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
92845 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
92846 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
92847 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
92848 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92849 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
92850 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
92851 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
92852 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
92853 // MIs[2] Rn
92854 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
92855 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
92856 GIM_CheckIsSafeToFold, /*NumInsns*/2,
92857 // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i32p:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn)
92858 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
92859 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
92860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
92861 GIR_RootConstrainSelectedInstOperands,
92862 // GIR_Coverage, 12355,
92863 GIR_EraseRootFromParent_Done,
92864 // Label 5340: @245854
92865 GIM_Try, /*On fail goto*//*Label 5341*/ GIMT_Encode4(245945), // Rule ID 13192 //
92866 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
92867 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
92868 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
92869 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
92870 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92871 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
92872 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
92873 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
92874 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
92875 // MIs[2] Rn
92876 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
92877 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
92878 GIM_CheckIsSafeToFold, /*NumInsns*/2,
92879 // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] }))
92880 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
92881 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
92882 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
92883 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
92884 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
92885 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
92886 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
92887 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
92888 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
92889 GIR_RootConstrainSelectedInstOperands,
92890 // GIR_Coverage, 13192,
92891 GIR_EraseRootFromParent_Done,
92892 // Label 5341: @245945
92893 GIM_Try, /*On fail goto*//*Label 5342*/ GIMT_Encode4(246009), // Rule ID 14868 //
92894 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
92895 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
92896 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
92897 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
92898 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92899 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
92900 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
92901 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
92902 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
92903 // MIs[2] Rn
92904 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
92905 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
92906 GIM_CheckIsSafeToFold, /*NumInsns*/2,
92907 // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i32p:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn)
92908 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
92909 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
92910 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
92911 GIR_RootConstrainSelectedInstOperands,
92912 // GIR_Coverage, 14868,
92913 GIR_EraseRootFromParent_Done,
92914 // Label 5342: @246009
92915 GIM_Try, /*On fail goto*//*Label 5343*/ GIMT_Encode4(246036), // Rule ID 580 //
92916 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
92917 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
92918 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
92919 // (fadd:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FADDSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
92920 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDSrr),
92921 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
92922 GIR_RootConstrainSelectedInstOperands,
92923 // GIR_Coverage, 580,
92924 GIR_Done,
92925 // Label 5343: @246036
92926 GIM_Reject,
92927 // Label 5338: @246037
92928 GIM_Reject,
92929 // Label 5324: @246038
92930 GIM_Try, /*On fail goto*//*Label 5344*/ GIMT_Encode4(246209),
92931 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
92932 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
92933 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92934 GIM_Try, /*On fail goto*//*Label 5345*/ GIMT_Encode4(246117), // Rule ID 6604 //
92935 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
92936 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
92937 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
92938 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
92939 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92940 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
92941 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
92942 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
92943 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
92944 // MIs[2] Rn
92945 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
92946 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
92947 GIM_CheckIsSafeToFold, /*NumInsns*/2,
92948 // (fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn)
92949 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i64p),
92950 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
92951 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
92952 GIR_RootConstrainSelectedInstOperands,
92953 // GIR_Coverage, 6604,
92954 GIR_EraseRootFromParent_Done,
92955 // Label 5345: @246117
92956 GIM_Try, /*On fail goto*//*Label 5346*/ GIMT_Encode4(246181), // Rule ID 13190 //
92957 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
92958 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
92959 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
92960 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
92961 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
92962 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
92963 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
92964 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
92965 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
92966 // MIs[2] Rn
92967 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
92968 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
92969 GIM_CheckIsSafeToFold, /*NumInsns*/2,
92970 // (fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn)
92971 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i64p),
92972 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
92973 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
92974 GIR_RootConstrainSelectedInstOperands,
92975 // GIR_Coverage, 13190,
92976 GIR_EraseRootFromParent_Done,
92977 // Label 5346: @246181
92978 GIM_Try, /*On fail goto*//*Label 5347*/ GIMT_Encode4(246208), // Rule ID 582 //
92979 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
92980 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92981 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92982 // (fadd:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FADDDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
92983 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDDrr),
92984 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
92985 GIR_RootConstrainSelectedInstOperands,
92986 // GIR_Coverage, 582,
92987 GIR_Done,
92988 // Label 5347: @246208
92989 GIM_Reject,
92990 // Label 5344: @246209
92991 GIM_Reject,
92992 // Label 5325: @246210
92993 GIM_Try, /*On fail goto*//*Label 5348*/ GIMT_Encode4(246247), // Rule ID 1190 //
92994 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
92995 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
92996 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
92997 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92998 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
92999 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
93000 // (fadd:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
93001 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv2f32),
93002 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
93003 GIR_RootConstrainSelectedInstOperands,
93004 // GIR_Coverage, 1190,
93005 GIR_Done,
93006 // Label 5348: @246247
93007 GIM_Reject,
93008 // Label 5326: @246248
93009 GIM_Try, /*On fail goto*//*Label 5349*/ GIMT_Encode4(246285), // Rule ID 1194 //
93010 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
93011 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
93012 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
93013 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
93014 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
93015 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
93016 // (fadd:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
93017 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv2f64),
93018 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
93019 GIR_RootConstrainSelectedInstOperands,
93020 // GIR_Coverage, 1194,
93021 GIR_Done,
93022 // Label 5349: @246285
93023 GIM_Reject,
93024 // Label 5327: @246286
93025 GIM_Try, /*On fail goto*//*Label 5350*/ GIMT_Encode4(246323), // Rule ID 1186 //
93026 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
93027 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
93028 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
93029 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
93030 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
93031 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
93032 // (fadd:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
93033 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f16),
93034 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
93035 GIR_RootConstrainSelectedInstOperands,
93036 // GIR_Coverage, 1186,
93037 GIR_Done,
93038 // Label 5350: @246323
93039 GIM_Reject,
93040 // Label 5328: @246324
93041 GIM_Try, /*On fail goto*//*Label 5351*/ GIMT_Encode4(246361), // Rule ID 1192 //
93042 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
93043 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
93044 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
93045 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
93046 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
93047 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
93048 // (fadd:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
93049 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
93050 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
93051 GIR_RootConstrainSelectedInstOperands,
93052 // GIR_Coverage, 1192,
93053 GIR_Done,
93054 // Label 5351: @246361
93055 GIM_Reject,
93056 // Label 5329: @246362
93057 GIM_Try, /*On fail goto*//*Label 5352*/ GIMT_Encode4(247936),
93058 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
93059 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
93060 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
93061 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
93062 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
93063 GIM_Try, /*On fail goto*//*Label 5353*/ GIMT_Encode4(246404), // Rule ID 1188 //
93064 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
93065 // (fadd:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
93066 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv8f16),
93067 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
93068 GIR_RootConstrainSelectedInstOperands,
93069 // GIR_Coverage, 1188,
93070 GIR_Done,
93071 // Label 5353: @246404
93072 GIM_Try, /*On fail goto*//*Label 5354*/ GIMT_Encode4(246658), // Rule ID 6716 //
93073 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
93074 // (fadd:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FADDv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FADDv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
93075 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
93076 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
93077 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
93078 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
93079 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
93080 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
93081 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
93082 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
93083 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
93084 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
93085 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
93086 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
93087 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93088 GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
93089 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
93090 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
93091 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93092 GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
93093 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
93094 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
93095 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93096 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
93097 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
93098 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
93099 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
93100 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93101 GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
93102 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
93103 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93104 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
93105 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93106 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
93107 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
93108 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
93109 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93110 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
93111 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
93112 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93113 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
93114 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93115 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
93116 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
93117 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
93118 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93119 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
93120 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
93121 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
93122 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
93123 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93124 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
93125 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
93126 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
93127 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93128 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
93129 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
93130 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93131 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
93132 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
93133 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
93134 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
93135 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93136 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
93137 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
93138 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
93139 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
93140 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
93141 GIR_RootConstrainSelectedInstOperands,
93142 // GIR_Coverage, 6716,
93143 GIR_EraseRootFromParent_Done,
93144 // Label 5354: @246658
93145 GIM_Try, /*On fail goto*//*Label 5355*/ GIMT_Encode4(246862), // Rule ID 6718 //
93146 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16),
93147 // (fadd:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFCVTN2:{ *:[v8bf16] } (BFCVTN:{ *:[v8bf16] } (FADDv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] })))), (FADDv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)))
93148 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
93149 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
93150 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
93151 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
93152 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
93153 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
93154 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
93155 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
93156 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
93157 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93158 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93159 GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/0, /*OpIdx*/2, // Rm
93160 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
93161 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93162 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93163 GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
93164 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
93165 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
93166 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93167 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
93168 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/8,
93169 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
93170 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
93171 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93172 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
93173 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
93174 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93175 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
93176 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93177 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
93178 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
93179 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
93180 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93181 GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
93182 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
93183 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93184 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
93185 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93186 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
93187 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
93188 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
93189 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93190 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
93191 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/4,
93192 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
93193 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN),
93194 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93195 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
93196 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
93197 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN2),
93198 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
93199 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
93200 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
93201 GIR_RootConstrainSelectedInstOperands,
93202 // GIR_Coverage, 6718,
93203 GIR_EraseRootFromParent_Done,
93204 // Label 5355: @246862
93205 GIM_Try, /*On fail goto*//*Label 5356*/ GIMT_Encode4(247935), // Rule ID 6720 //
93206 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoBF16),
93207 // (fadd:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (UZP2v8i16:{ *:[v8bf16] } (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FADDv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), (FADDv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] })))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FADDv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FADDv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), 64:{ *:[i32] }, 16:{ *:[i32] })), (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FADDv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), (FADDv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FADDv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FADDv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), 64:{ *:[i32] }, 16:{ *:[i32] })))
93208 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
93209 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
93210 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
93211 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
93212 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
93213 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
93214 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
93215 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
93216 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
93217 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s16,
93218 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
93219 GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_v4s16,
93220 GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_s128,
93221 GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s128,
93222 GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_v4s32,
93223 GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_v4s32,
93224 GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_v4s16,
93225 GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_v4s32,
93226 GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_v4s16,
93227 GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_s128,
93228 GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_s128,
93229 GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s128,
93230 GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s128,
93231 GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_s128,
93232 GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_v4s32,
93233 GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_v4s32,
93234 GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_v4s16,
93235 GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_v4s32,
93236 GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_v4s16,
93237 GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_s128,
93238 GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_s128,
93239 GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_v4s32,
93240 GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_v4s32,
93241 GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_v4s32,
93242 GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_v4s32,
93243 GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_v4s32,
93244 GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_v4s32,
93245 GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_s128,
93246 GIR_MakeTempReg, /*TempRegID*/38, /*TypeID*/GILLT_s128,
93247 GIR_MakeTempReg, /*TempRegID*/39, /*TypeID*/GILLT_v4s32,
93248 GIR_MakeTempReg, /*TempRegID*/40, /*TypeID*/GILLT_v4s32,
93249 GIR_MakeTempReg, /*TempRegID*/41, /*TypeID*/GILLT_v4s32,
93250 GIR_MakeTempReg, /*TempRegID*/42, /*TypeID*/GILLT_s128,
93251 GIR_MakeTempReg, /*TempRegID*/43, /*TypeID*/GILLT_s128,
93252 GIR_MakeTempReg, /*TempRegID*/44, /*TypeID*/GILLT_s128,
93253 GIR_MakeTempReg, /*TempRegID*/45, /*TypeID*/GILLT_s128,
93254 GIR_MakeTempReg, /*TempRegID*/46, /*TypeID*/GILLT_s128,
93255 GIR_MakeTempReg, /*TempRegID*/47, /*TypeID*/GILLT_v4s32,
93256 GIR_MakeTempReg, /*TempRegID*/48, /*TypeID*/GILLT_v4s32,
93257 GIR_MakeTempReg, /*TempRegID*/49, /*TypeID*/GILLT_v4s32,
93258 GIR_BuildMI, /*InsnID*/50, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93259 GIR_AddTempRegister, /*InsnID*/50, /*TempRegID*/49, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93260 GIR_Copy, /*NewInsnID*/50, /*OldInsnID*/0, /*OpIdx*/2, // Rm
93261 GIR_ConstrainSelectedInstOperands, /*InsnID*/50,
93262 GIR_BuildMI, /*InsnID*/49, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93263 GIR_AddTempRegister, /*InsnID*/49, /*TempRegID*/48, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93264 GIR_Copy, /*NewInsnID*/49, /*OldInsnID*/0, /*OpIdx*/1, // Rn
93265 GIR_ConstrainSelectedInstOperands, /*InsnID*/49,
93266 GIR_BuildMI, /*InsnID*/48, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
93267 GIR_AddTempRegister, /*InsnID*/48, /*TempRegID*/47, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93268 GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/48,
93269 GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/49,
93270 GIR_ConstrainSelectedInstOperands, /*InsnID*/48,
93271 GIR_BuildMI, /*InsnID*/47, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
93272 GIR_AddTempRegister, /*InsnID*/47, /*TempRegID*/46, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93273 GIR_AddSimpleTempRegister, /*InsnID*/47, /*TempRegID*/47,
93274 GIR_AddImm8, /*InsnID*/47, /*Imm*/64,
93275 GIR_AddImm8, /*InsnID*/47, /*Imm*/16,
93276 GIR_ConstrainSelectedInstOperands, /*InsnID*/47,
93277 GIR_BuildMI, /*InsnID*/46, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
93278 GIR_AddTempRegister, /*InsnID*/46, /*TempRegID*/45, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93279 GIR_AddImm8, /*InsnID*/46, /*Imm*/127,
93280 GIR_AddImm, /*InsnID*/46, /*Imm*/GIMT_Encode8(264),
93281 GIR_ConstrainSelectedInstOperands, /*InsnID*/46,
93282 GIR_BuildMI, /*InsnID*/45, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
93283 GIR_AddTempRegister, /*InsnID*/45, /*TempRegID*/44, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93284 GIR_AddImm8, /*InsnID*/45, /*Imm*/1,
93285 GIR_AddImm8, /*InsnID*/45, /*Imm*/0,
93286 GIR_ConstrainSelectedInstOperands, /*InsnID*/45,
93287 GIR_BuildMI, /*InsnID*/44, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
93288 GIR_AddTempRegister, /*InsnID*/44, /*TempRegID*/43, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93289 GIR_Copy, /*NewInsnID*/44, /*OldInsnID*/0, /*OpIdx*/1, // Rn
93290 GIR_AddImm8, /*InsnID*/44, /*Imm*/16,
93291 GIR_ConstrainSelectedInstOperands, /*InsnID*/44,
93292 GIR_BuildMI, /*InsnID*/43, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
93293 GIR_AddTempRegister, /*InsnID*/43, /*TempRegID*/42, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93294 GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/43,
93295 GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/44,
93296 GIR_ConstrainSelectedInstOperands, /*InsnID*/43,
93297 GIR_BuildMI, /*InsnID*/42, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93298 GIR_AddTempRegister, /*InsnID*/42, /*TempRegID*/41, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93299 GIR_Copy, /*NewInsnID*/42, /*OldInsnID*/0, /*OpIdx*/2, // Rm
93300 GIR_ConstrainSelectedInstOperands, /*InsnID*/42,
93301 GIR_BuildMI, /*InsnID*/41, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93302 GIR_AddTempRegister, /*InsnID*/41, /*TempRegID*/40, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93303 GIR_Copy, /*NewInsnID*/41, /*OldInsnID*/0, /*OpIdx*/1, // Rn
93304 GIR_ConstrainSelectedInstOperands, /*InsnID*/41,
93305 GIR_BuildMI, /*InsnID*/40, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
93306 GIR_AddTempRegister, /*InsnID*/40, /*TempRegID*/39, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93307 GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/40,
93308 GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/41,
93309 GIR_ConstrainSelectedInstOperands, /*InsnID*/40,
93310 GIR_BuildMI, /*InsnID*/39, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
93311 GIR_AddTempRegister, /*InsnID*/39, /*TempRegID*/38, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93312 GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/39,
93313 GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/42,
93314 GIR_ConstrainSelectedInstOperands, /*InsnID*/39,
93315 GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
93316 GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93317 GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/38,
93318 GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/45,
93319 GIR_ConstrainSelectedInstOperands, /*InsnID*/38,
93320 GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93321 GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93322 GIR_Copy, /*NewInsnID*/37, /*OldInsnID*/0, /*OpIdx*/2, // Rm
93323 GIR_ConstrainSelectedInstOperands, /*InsnID*/37,
93324 GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93325 GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93326 GIR_Copy, /*NewInsnID*/36, /*OldInsnID*/0, /*OpIdx*/1, // Rn
93327 GIR_ConstrainSelectedInstOperands, /*InsnID*/36,
93328 GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
93329 GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93330 GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/35,
93331 GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/36,
93332 GIR_ConstrainSelectedInstOperands, /*InsnID*/35,
93333 GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93334 GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93335 GIR_Copy, /*NewInsnID*/34, /*OldInsnID*/0, /*OpIdx*/2, // Rm
93336 GIR_ConstrainSelectedInstOperands, /*InsnID*/34,
93337 GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93338 GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93339 GIR_Copy, /*NewInsnID*/33, /*OldInsnID*/0, /*OpIdx*/1, // Rn
93340 GIR_ConstrainSelectedInstOperands, /*InsnID*/33,
93341 GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
93342 GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93343 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/32,
93344 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/33,
93345 GIR_ConstrainSelectedInstOperands, /*InsnID*/32,
93346 GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
93347 GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93348 GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/31,
93349 GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/34,
93350 GIR_ConstrainSelectedInstOperands, /*InsnID*/31,
93351 GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
93352 GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93353 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/30,
93354 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/37,
93355 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/46,
93356 GIR_ConstrainSelectedInstOperands, /*InsnID*/30,
93357 GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
93358 GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93359 GIR_CopySubReg, /*NewInsnID*/29, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
93360 GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
93361 GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93362 GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
93363 GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93364 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/28,
93365 GIR_ConstrainSelectedInstOperands, /*InsnID*/28,
93366 GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
93367 GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93368 GIR_CopySubReg, /*NewInsnID*/27, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
93369 GIR_ConstrainOperandRC, /*InsnID*/27, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
93370 GIR_ConstrainOperandRC, /*InsnID*/27, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93371 GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
93372 GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93373 GIR_AddSimpleTempRegister, /*InsnID*/26, /*TempRegID*/26,
93374 GIR_ConstrainSelectedInstOperands, /*InsnID*/26,
93375 GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
93376 GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93377 GIR_AddSimpleTempRegister, /*InsnID*/25, /*TempRegID*/25,
93378 GIR_AddSimpleTempRegister, /*InsnID*/25, /*TempRegID*/27,
93379 GIR_ConstrainSelectedInstOperands, /*InsnID*/25,
93380 GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
93381 GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93382 GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/24,
93383 GIR_AddImm8, /*InsnID*/24, /*Imm*/64,
93384 GIR_AddImm8, /*InsnID*/24, /*Imm*/16,
93385 GIR_ConstrainSelectedInstOperands, /*InsnID*/24,
93386 GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
93387 GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93388 GIR_AddImm8, /*InsnID*/23, /*Imm*/127,
93389 GIR_AddImm, /*InsnID*/23, /*Imm*/GIMT_Encode8(264),
93390 GIR_ConstrainSelectedInstOperands, /*InsnID*/23,
93391 GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
93392 GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93393 GIR_AddImm8, /*InsnID*/22, /*Imm*/1,
93394 GIR_AddImm8, /*InsnID*/22, /*Imm*/0,
93395 GIR_ConstrainSelectedInstOperands, /*InsnID*/22,
93396 GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
93397 GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93398 GIR_Copy, /*NewInsnID*/21, /*OldInsnID*/0, /*OpIdx*/1, // Rn
93399 GIR_AddImm8, /*InsnID*/21, /*Imm*/16,
93400 GIR_ConstrainSelectedInstOperands, /*InsnID*/21,
93401 GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
93402 GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93403 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/20,
93404 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/21,
93405 GIR_ConstrainSelectedInstOperands, /*InsnID*/20,
93406 GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
93407 GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93408 GIR_CopySubReg, /*NewInsnID*/19, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
93409 GIR_ConstrainOperandRC, /*InsnID*/19, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
93410 GIR_ConstrainOperandRC, /*InsnID*/19, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93411 GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
93412 GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93413 GIR_AddSimpleTempRegister, /*InsnID*/18, /*TempRegID*/18,
93414 GIR_ConstrainSelectedInstOperands, /*InsnID*/18,
93415 GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
93416 GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93417 GIR_CopySubReg, /*NewInsnID*/17, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
93418 GIR_ConstrainOperandRC, /*InsnID*/17, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
93419 GIR_ConstrainOperandRC, /*InsnID*/17, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93420 GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
93421 GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93422 GIR_AddSimpleTempRegister, /*InsnID*/16, /*TempRegID*/16,
93423 GIR_ConstrainSelectedInstOperands, /*InsnID*/16,
93424 GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
93425 GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93426 GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/15,
93427 GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/17,
93428 GIR_ConstrainSelectedInstOperands, /*InsnID*/15,
93429 GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
93430 GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93431 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14,
93432 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/19,
93433 GIR_ConstrainSelectedInstOperands, /*InsnID*/14,
93434 GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
93435 GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93436 GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/13,
93437 GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/22,
93438 GIR_ConstrainSelectedInstOperands, /*InsnID*/13,
93439 GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
93440 GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93441 GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
93442 GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
93443 GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93444 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
93445 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93446 GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11,
93447 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
93448 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
93449 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93450 GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
93451 GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
93452 GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93453 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
93454 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93455 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
93456 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
93457 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
93458 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93459 GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
93460 GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/10,
93461 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
93462 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
93463 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93464 GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
93465 GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
93466 GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93467 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
93468 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93469 GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
93470 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
93471 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
93472 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93473 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
93474 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
93475 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93476 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
93477 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93478 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
93479 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
93480 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
93481 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93482 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
93483 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/5,
93484 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
93485 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
93486 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93487 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
93488 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/7,
93489 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
93490 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
93491 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93492 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
93493 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/12,
93494 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/23,
93495 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
93496 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
93497 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
93498 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
93499 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/29,
93500 GIR_RootConstrainSelectedInstOperands,
93501 // GIR_Coverage, 6720,
93502 GIR_EraseRootFromParent_Done,
93503 // Label 5356: @247935
93504 GIM_Reject,
93505 // Label 5352: @247936
93506 GIM_Reject,
93507 // Label 5330: @247937
93508 GIM_Try, /*On fail goto*//*Label 5357*/ GIMT_Encode4(247962), // Rule ID 2740 //
93509 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
93510 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
93511 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
93512 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
93513 // (fadd:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (FADD_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
93514 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZZZ_D),
93515 GIR_RootConstrainSelectedInstOperands,
93516 // GIR_Coverage, 2740,
93517 GIR_Done,
93518 // Label 5357: @247962
93519 GIM_Reject,
93520 // Label 5331: @247963
93521 GIM_Try, /*On fail goto*//*Label 5358*/ GIMT_Encode4(247988), // Rule ID 2738 //
93522 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
93523 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
93524 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
93525 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
93526 // (fadd:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (FADD_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
93527 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZZZ_S),
93528 GIR_RootConstrainSelectedInstOperands,
93529 // GIR_Coverage, 2738,
93530 GIR_Done,
93531 // Label 5358: @247988
93532 GIM_Reject,
93533 // Label 5332: @247989
93534 GIM_Try, /*On fail goto*//*Label 5359*/ GIMT_Encode4(248035),
93535 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
93536 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
93537 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
93538 GIM_Try, /*On fail goto*//*Label 5360*/ GIMT_Encode4(248019), // Rule ID 2736 //
93539 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
93540 // (fadd:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (FADD_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
93541 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZZZ_H),
93542 GIR_RootConstrainSelectedInstOperands,
93543 // GIR_Coverage, 2736,
93544 GIR_Done,
93545 // Label 5360: @248019
93546 GIM_Try, /*On fail goto*//*Label 5361*/ GIMT_Encode4(248034), // Rule ID 2742 //
93547 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasB16B16_HasSVE2orSME2),
93548 // (fadd:{ *:[nxv8bf16] } nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2) => (BFADD_ZZZ:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2)
93549 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BFADD_ZZZ),
93550 GIR_RootConstrainSelectedInstOperands,
93551 // GIR_Coverage, 2742,
93552 GIR_Done,
93553 // Label 5361: @248034
93554 GIM_Reject,
93555 // Label 5359: @248035
93556 GIM_Reject,
93557 // Label 5333: @248036
93558 GIM_Reject,
93559 // Label 54: @248037
93560 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(22), /*)*//*default:*//*Label 5373*/ GIMT_Encode4(250072),
93561 /*GILLT_s16*//*Label 5362*/ GIMT_Encode4(248132),
93562 /*GILLT_s32*//*Label 5363*/ GIMT_Encode4(248170),
93563 /*GILLT_s64*//*Label 5364*/ GIMT_Encode4(248208), GIMT_Encode4(0),
93564 /*GILLT_v2s32*//*Label 5365*/ GIMT_Encode4(248246),
93565 /*GILLT_v2s64*//*Label 5366*/ GIMT_Encode4(248284),
93566 /*GILLT_v4s16*//*Label 5367*/ GIMT_Encode4(248322),
93567 /*GILLT_v4s32*//*Label 5368*/ GIMT_Encode4(248360), GIMT_Encode4(0),
93568 /*GILLT_v8s16*//*Label 5369*/ GIMT_Encode4(248398), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
93569 /*GILLT_nxv2s64*//*Label 5370*/ GIMT_Encode4(249973), GIMT_Encode4(0), GIMT_Encode4(0),
93570 /*GILLT_nxv4s32*//*Label 5371*/ GIMT_Encode4(249999), GIMT_Encode4(0),
93571 /*GILLT_nxv8s16*//*Label 5372*/ GIMT_Encode4(250025),
93572 // Label 5362: @248132
93573 GIM_Try, /*On fail goto*//*Label 5374*/ GIMT_Encode4(248169), // Rule ID 626 //
93574 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
93575 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
93576 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
93577 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
93578 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
93579 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
93580 // (fsub:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FSUBHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
93581 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBHrr),
93582 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
93583 GIR_RootConstrainSelectedInstOperands,
93584 // GIR_Coverage, 626,
93585 GIR_Done,
93586 // Label 5374: @248169
93587 GIM_Reject,
93588 // Label 5363: @248170
93589 GIM_Try, /*On fail goto*//*Label 5375*/ GIMT_Encode4(248207), // Rule ID 628 //
93590 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
93591 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
93592 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
93593 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
93594 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
93595 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
93596 // (fsub:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FSUBSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
93597 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBSrr),
93598 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
93599 GIR_RootConstrainSelectedInstOperands,
93600 // GIR_Coverage, 628,
93601 GIR_Done,
93602 // Label 5375: @248207
93603 GIM_Reject,
93604 // Label 5364: @248208
93605 GIM_Try, /*On fail goto*//*Label 5376*/ GIMT_Encode4(248245), // Rule ID 630 //
93606 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
93607 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
93608 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
93609 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
93610 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
93611 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
93612 // (fsub:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FSUBDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
93613 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBDrr),
93614 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
93615 GIR_RootConstrainSelectedInstOperands,
93616 // GIR_Coverage, 630,
93617 GIR_Done,
93618 // Label 5376: @248245
93619 GIM_Reject,
93620 // Label 5365: @248246
93621 GIM_Try, /*On fail goto*//*Label 5377*/ GIMT_Encode4(248283), // Rule ID 1330 //
93622 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
93623 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
93624 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
93625 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
93626 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
93627 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
93628 // (fsub:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FSUBv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
93629 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv2f32),
93630 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
93631 GIR_RootConstrainSelectedInstOperands,
93632 // GIR_Coverage, 1330,
93633 GIR_Done,
93634 // Label 5377: @248283
93635 GIM_Reject,
93636 // Label 5366: @248284
93637 GIM_Try, /*On fail goto*//*Label 5378*/ GIMT_Encode4(248321), // Rule ID 1334 //
93638 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
93639 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
93640 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
93641 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
93642 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
93643 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
93644 // (fsub:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FSUBv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
93645 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv2f64),
93646 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
93647 GIR_RootConstrainSelectedInstOperands,
93648 // GIR_Coverage, 1334,
93649 GIR_Done,
93650 // Label 5378: @248321
93651 GIM_Reject,
93652 // Label 5367: @248322
93653 GIM_Try, /*On fail goto*//*Label 5379*/ GIMT_Encode4(248359), // Rule ID 1326 //
93654 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
93655 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
93656 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
93657 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
93658 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
93659 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
93660 // (fsub:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FSUBv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
93661 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f16),
93662 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
93663 GIR_RootConstrainSelectedInstOperands,
93664 // GIR_Coverage, 1326,
93665 GIR_Done,
93666 // Label 5379: @248359
93667 GIM_Reject,
93668 // Label 5368: @248360
93669 GIM_Try, /*On fail goto*//*Label 5380*/ GIMT_Encode4(248397), // Rule ID 1332 //
93670 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
93671 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
93672 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
93673 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
93674 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
93675 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
93676 // (fsub:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FSUBv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
93677 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
93678 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
93679 GIR_RootConstrainSelectedInstOperands,
93680 // GIR_Coverage, 1332,
93681 GIR_Done,
93682 // Label 5380: @248397
93683 GIM_Reject,
93684 // Label 5369: @248398
93685 GIM_Try, /*On fail goto*//*Label 5381*/ GIMT_Encode4(249972),
93686 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
93687 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
93688 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
93689 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
93690 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
93691 GIM_Try, /*On fail goto*//*Label 5382*/ GIMT_Encode4(248440), // Rule ID 1328 //
93692 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
93693 // (fsub:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FSUBv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
93694 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv8f16),
93695 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
93696 GIR_RootConstrainSelectedInstOperands,
93697 // GIR_Coverage, 1328,
93698 GIR_Done,
93699 // Label 5382: @248440
93700 GIM_Try, /*On fail goto*//*Label 5383*/ GIMT_Encode4(248694), // Rule ID 6734 //
93701 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
93702 // (fsub:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FSUBv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FSUBv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
93703 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
93704 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
93705 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
93706 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
93707 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
93708 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
93709 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
93710 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
93711 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
93712 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
93713 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
93714 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
93715 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93716 GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
93717 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
93718 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
93719 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93720 GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
93721 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
93722 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
93723 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93724 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
93725 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
93726 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
93727 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
93728 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93729 GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
93730 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
93731 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93732 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
93733 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93734 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
93735 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
93736 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
93737 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93738 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
93739 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
93740 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93741 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
93742 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93743 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
93744 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
93745 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
93746 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93747 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
93748 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
93749 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
93750 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
93751 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93752 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
93753 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
93754 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
93755 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93756 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
93757 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
93758 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93759 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
93760 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
93761 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
93762 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
93763 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93764 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
93765 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
93766 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
93767 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
93768 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
93769 GIR_RootConstrainSelectedInstOperands,
93770 // GIR_Coverage, 6734,
93771 GIR_EraseRootFromParent_Done,
93772 // Label 5383: @248694
93773 GIM_Try, /*On fail goto*//*Label 5384*/ GIMT_Encode4(248898), // Rule ID 6736 //
93774 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16),
93775 // (fsub:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFCVTN2:{ *:[v8bf16] } (BFCVTN:{ *:[v8bf16] } (FSUBv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] })))), (FSUBv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)))
93776 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
93777 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
93778 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
93779 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
93780 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
93781 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
93782 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
93783 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
93784 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
93785 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93786 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93787 GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/0, /*OpIdx*/2, // Rm
93788 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
93789 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93790 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93791 GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
93792 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
93793 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
93794 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93795 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
93796 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/8,
93797 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
93798 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
93799 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93800 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
93801 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
93802 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93803 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
93804 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93805 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
93806 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
93807 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
93808 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93809 GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
93810 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
93811 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93812 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
93813 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93814 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
93815 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
93816 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
93817 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93818 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
93819 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/4,
93820 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
93821 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN),
93822 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93823 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
93824 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
93825 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN2),
93826 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
93827 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
93828 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
93829 GIR_RootConstrainSelectedInstOperands,
93830 // GIR_Coverage, 6736,
93831 GIR_EraseRootFromParent_Done,
93832 // Label 5384: @248898
93833 GIM_Try, /*On fail goto*//*Label 5385*/ GIMT_Encode4(249971), // Rule ID 6738 //
93834 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoBF16),
93835 // (fsub:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (UZP2v8i16:{ *:[v8bf16] } (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FSUBv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), (FSUBv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] })))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FSUBv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FSUBv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), 64:{ *:[i32] }, 16:{ *:[i32] })), (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FSUBv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), (FSUBv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FSUBv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FSUBv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), 64:{ *:[i32] }, 16:{ *:[i32] })))
93836 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
93837 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
93838 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
93839 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
93840 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
93841 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
93842 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
93843 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
93844 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
93845 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s16,
93846 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
93847 GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_v4s16,
93848 GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_s128,
93849 GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s128,
93850 GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_v4s32,
93851 GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_v4s32,
93852 GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_v4s16,
93853 GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_v4s32,
93854 GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_v4s16,
93855 GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_s128,
93856 GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_s128,
93857 GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s128,
93858 GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s128,
93859 GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_s128,
93860 GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_v4s32,
93861 GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_v4s32,
93862 GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_v4s16,
93863 GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_v4s32,
93864 GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_v4s16,
93865 GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_s128,
93866 GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_s128,
93867 GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_v4s32,
93868 GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_v4s32,
93869 GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_v4s32,
93870 GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_v4s32,
93871 GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_v4s32,
93872 GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_v4s32,
93873 GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_s128,
93874 GIR_MakeTempReg, /*TempRegID*/38, /*TypeID*/GILLT_s128,
93875 GIR_MakeTempReg, /*TempRegID*/39, /*TypeID*/GILLT_v4s32,
93876 GIR_MakeTempReg, /*TempRegID*/40, /*TypeID*/GILLT_v4s32,
93877 GIR_MakeTempReg, /*TempRegID*/41, /*TypeID*/GILLT_v4s32,
93878 GIR_MakeTempReg, /*TempRegID*/42, /*TypeID*/GILLT_s128,
93879 GIR_MakeTempReg, /*TempRegID*/43, /*TypeID*/GILLT_s128,
93880 GIR_MakeTempReg, /*TempRegID*/44, /*TypeID*/GILLT_s128,
93881 GIR_MakeTempReg, /*TempRegID*/45, /*TypeID*/GILLT_s128,
93882 GIR_MakeTempReg, /*TempRegID*/46, /*TypeID*/GILLT_s128,
93883 GIR_MakeTempReg, /*TempRegID*/47, /*TypeID*/GILLT_v4s32,
93884 GIR_MakeTempReg, /*TempRegID*/48, /*TypeID*/GILLT_v4s32,
93885 GIR_MakeTempReg, /*TempRegID*/49, /*TypeID*/GILLT_v4s32,
93886 GIR_BuildMI, /*InsnID*/50, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93887 GIR_AddTempRegister, /*InsnID*/50, /*TempRegID*/49, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93888 GIR_Copy, /*NewInsnID*/50, /*OldInsnID*/0, /*OpIdx*/2, // Rm
93889 GIR_ConstrainSelectedInstOperands, /*InsnID*/50,
93890 GIR_BuildMI, /*InsnID*/49, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93891 GIR_AddTempRegister, /*InsnID*/49, /*TempRegID*/48, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93892 GIR_Copy, /*NewInsnID*/49, /*OldInsnID*/0, /*OpIdx*/1, // Rn
93893 GIR_ConstrainSelectedInstOperands, /*InsnID*/49,
93894 GIR_BuildMI, /*InsnID*/48, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
93895 GIR_AddTempRegister, /*InsnID*/48, /*TempRegID*/47, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93896 GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/48,
93897 GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/49,
93898 GIR_ConstrainSelectedInstOperands, /*InsnID*/48,
93899 GIR_BuildMI, /*InsnID*/47, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
93900 GIR_AddTempRegister, /*InsnID*/47, /*TempRegID*/46, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93901 GIR_AddSimpleTempRegister, /*InsnID*/47, /*TempRegID*/47,
93902 GIR_AddImm8, /*InsnID*/47, /*Imm*/64,
93903 GIR_AddImm8, /*InsnID*/47, /*Imm*/16,
93904 GIR_ConstrainSelectedInstOperands, /*InsnID*/47,
93905 GIR_BuildMI, /*InsnID*/46, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
93906 GIR_AddTempRegister, /*InsnID*/46, /*TempRegID*/45, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93907 GIR_AddImm8, /*InsnID*/46, /*Imm*/127,
93908 GIR_AddImm, /*InsnID*/46, /*Imm*/GIMT_Encode8(264),
93909 GIR_ConstrainSelectedInstOperands, /*InsnID*/46,
93910 GIR_BuildMI, /*InsnID*/45, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
93911 GIR_AddTempRegister, /*InsnID*/45, /*TempRegID*/44, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93912 GIR_AddImm8, /*InsnID*/45, /*Imm*/1,
93913 GIR_AddImm8, /*InsnID*/45, /*Imm*/0,
93914 GIR_ConstrainSelectedInstOperands, /*InsnID*/45,
93915 GIR_BuildMI, /*InsnID*/44, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
93916 GIR_AddTempRegister, /*InsnID*/44, /*TempRegID*/43, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93917 GIR_Copy, /*NewInsnID*/44, /*OldInsnID*/0, /*OpIdx*/1, // Rn
93918 GIR_AddImm8, /*InsnID*/44, /*Imm*/16,
93919 GIR_ConstrainSelectedInstOperands, /*InsnID*/44,
93920 GIR_BuildMI, /*InsnID*/43, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
93921 GIR_AddTempRegister, /*InsnID*/43, /*TempRegID*/42, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93922 GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/43,
93923 GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/44,
93924 GIR_ConstrainSelectedInstOperands, /*InsnID*/43,
93925 GIR_BuildMI, /*InsnID*/42, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93926 GIR_AddTempRegister, /*InsnID*/42, /*TempRegID*/41, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93927 GIR_Copy, /*NewInsnID*/42, /*OldInsnID*/0, /*OpIdx*/2, // Rm
93928 GIR_ConstrainSelectedInstOperands, /*InsnID*/42,
93929 GIR_BuildMI, /*InsnID*/41, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93930 GIR_AddTempRegister, /*InsnID*/41, /*TempRegID*/40, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93931 GIR_Copy, /*NewInsnID*/41, /*OldInsnID*/0, /*OpIdx*/1, // Rn
93932 GIR_ConstrainSelectedInstOperands, /*InsnID*/41,
93933 GIR_BuildMI, /*InsnID*/40, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
93934 GIR_AddTempRegister, /*InsnID*/40, /*TempRegID*/39, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93935 GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/40,
93936 GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/41,
93937 GIR_ConstrainSelectedInstOperands, /*InsnID*/40,
93938 GIR_BuildMI, /*InsnID*/39, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
93939 GIR_AddTempRegister, /*InsnID*/39, /*TempRegID*/38, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93940 GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/39,
93941 GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/42,
93942 GIR_ConstrainSelectedInstOperands, /*InsnID*/39,
93943 GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
93944 GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93945 GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/38,
93946 GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/45,
93947 GIR_ConstrainSelectedInstOperands, /*InsnID*/38,
93948 GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93949 GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93950 GIR_Copy, /*NewInsnID*/37, /*OldInsnID*/0, /*OpIdx*/2, // Rm
93951 GIR_ConstrainSelectedInstOperands, /*InsnID*/37,
93952 GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93953 GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93954 GIR_Copy, /*NewInsnID*/36, /*OldInsnID*/0, /*OpIdx*/1, // Rn
93955 GIR_ConstrainSelectedInstOperands, /*InsnID*/36,
93956 GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
93957 GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93958 GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/35,
93959 GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/36,
93960 GIR_ConstrainSelectedInstOperands, /*InsnID*/35,
93961 GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93962 GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93963 GIR_Copy, /*NewInsnID*/34, /*OldInsnID*/0, /*OpIdx*/2, // Rm
93964 GIR_ConstrainSelectedInstOperands, /*InsnID*/34,
93965 GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
93966 GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93967 GIR_Copy, /*NewInsnID*/33, /*OldInsnID*/0, /*OpIdx*/1, // Rn
93968 GIR_ConstrainSelectedInstOperands, /*InsnID*/33,
93969 GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
93970 GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93971 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/32,
93972 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/33,
93973 GIR_ConstrainSelectedInstOperands, /*InsnID*/32,
93974 GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
93975 GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93976 GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/31,
93977 GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/34,
93978 GIR_ConstrainSelectedInstOperands, /*InsnID*/31,
93979 GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
93980 GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93981 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/30,
93982 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/37,
93983 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/46,
93984 GIR_ConstrainSelectedInstOperands, /*InsnID*/30,
93985 GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
93986 GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93987 GIR_CopySubReg, /*NewInsnID*/29, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
93988 GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
93989 GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93990 GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
93991 GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93992 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/28,
93993 GIR_ConstrainSelectedInstOperands, /*InsnID*/28,
93994 GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
93995 GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
93996 GIR_CopySubReg, /*NewInsnID*/27, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
93997 GIR_ConstrainOperandRC, /*InsnID*/27, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
93998 GIR_ConstrainOperandRC, /*InsnID*/27, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
93999 GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
94000 GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94001 GIR_AddSimpleTempRegister, /*InsnID*/26, /*TempRegID*/26,
94002 GIR_ConstrainSelectedInstOperands, /*InsnID*/26,
94003 GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
94004 GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94005 GIR_AddSimpleTempRegister, /*InsnID*/25, /*TempRegID*/25,
94006 GIR_AddSimpleTempRegister, /*InsnID*/25, /*TempRegID*/27,
94007 GIR_ConstrainSelectedInstOperands, /*InsnID*/25,
94008 GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
94009 GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94010 GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/24,
94011 GIR_AddImm8, /*InsnID*/24, /*Imm*/64,
94012 GIR_AddImm8, /*InsnID*/24, /*Imm*/16,
94013 GIR_ConstrainSelectedInstOperands, /*InsnID*/24,
94014 GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
94015 GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94016 GIR_AddImm8, /*InsnID*/23, /*Imm*/127,
94017 GIR_AddImm, /*InsnID*/23, /*Imm*/GIMT_Encode8(264),
94018 GIR_ConstrainSelectedInstOperands, /*InsnID*/23,
94019 GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
94020 GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94021 GIR_AddImm8, /*InsnID*/22, /*Imm*/1,
94022 GIR_AddImm8, /*InsnID*/22, /*Imm*/0,
94023 GIR_ConstrainSelectedInstOperands, /*InsnID*/22,
94024 GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
94025 GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94026 GIR_Copy, /*NewInsnID*/21, /*OldInsnID*/0, /*OpIdx*/1, // Rn
94027 GIR_AddImm8, /*InsnID*/21, /*Imm*/16,
94028 GIR_ConstrainSelectedInstOperands, /*InsnID*/21,
94029 GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
94030 GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94031 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/20,
94032 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/21,
94033 GIR_ConstrainSelectedInstOperands, /*InsnID*/20,
94034 GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
94035 GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94036 GIR_CopySubReg, /*NewInsnID*/19, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
94037 GIR_ConstrainOperandRC, /*InsnID*/19, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
94038 GIR_ConstrainOperandRC, /*InsnID*/19, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94039 GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
94040 GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94041 GIR_AddSimpleTempRegister, /*InsnID*/18, /*TempRegID*/18,
94042 GIR_ConstrainSelectedInstOperands, /*InsnID*/18,
94043 GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
94044 GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94045 GIR_CopySubReg, /*NewInsnID*/17, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
94046 GIR_ConstrainOperandRC, /*InsnID*/17, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
94047 GIR_ConstrainOperandRC, /*InsnID*/17, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94048 GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
94049 GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94050 GIR_AddSimpleTempRegister, /*InsnID*/16, /*TempRegID*/16,
94051 GIR_ConstrainSelectedInstOperands, /*InsnID*/16,
94052 GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
94053 GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94054 GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/15,
94055 GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/17,
94056 GIR_ConstrainSelectedInstOperands, /*InsnID*/15,
94057 GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
94058 GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94059 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14,
94060 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/19,
94061 GIR_ConstrainSelectedInstOperands, /*InsnID*/14,
94062 GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
94063 GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94064 GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/13,
94065 GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/22,
94066 GIR_ConstrainSelectedInstOperands, /*InsnID*/13,
94067 GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
94068 GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94069 GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
94070 GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
94071 GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94072 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
94073 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94074 GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11,
94075 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
94076 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
94077 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94078 GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
94079 GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
94080 GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94081 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
94082 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94083 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
94084 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
94085 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
94086 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94087 GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
94088 GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/10,
94089 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
94090 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
94091 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94092 GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
94093 GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
94094 GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94095 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
94096 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94097 GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
94098 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
94099 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
94100 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94101 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
94102 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
94103 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94104 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
94105 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94106 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
94107 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
94108 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
94109 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94110 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
94111 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/5,
94112 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
94113 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
94114 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94115 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
94116 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/7,
94117 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
94118 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
94119 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94120 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
94121 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/12,
94122 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/23,
94123 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
94124 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
94125 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94126 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
94127 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/29,
94128 GIR_RootConstrainSelectedInstOperands,
94129 // GIR_Coverage, 6738,
94130 GIR_EraseRootFromParent_Done,
94131 // Label 5385: @249971
94132 GIM_Reject,
94133 // Label 5381: @249972
94134 GIM_Reject,
94135 // Label 5370: @249973
94136 GIM_Try, /*On fail goto*//*Label 5386*/ GIMT_Encode4(249998), // Rule ID 7857 //
94137 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
94138 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
94139 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
94140 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
94141 // (fsub:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (FSUB_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
94142 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZZZ_D),
94143 GIR_RootConstrainSelectedInstOperands,
94144 // GIR_Coverage, 7857,
94145 GIR_Done,
94146 // Label 5386: @249998
94147 GIM_Reject,
94148 // Label 5371: @249999
94149 GIM_Try, /*On fail goto*//*Label 5387*/ GIMT_Encode4(250024), // Rule ID 7855 //
94150 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
94151 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
94152 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
94153 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
94154 // (fsub:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (FSUB_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
94155 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZZZ_S),
94156 GIR_RootConstrainSelectedInstOperands,
94157 // GIR_Coverage, 7855,
94158 GIR_Done,
94159 // Label 5387: @250024
94160 GIM_Reject,
94161 // Label 5372: @250025
94162 GIM_Try, /*On fail goto*//*Label 5388*/ GIMT_Encode4(250071),
94163 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
94164 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
94165 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
94166 GIM_Try, /*On fail goto*//*Label 5389*/ GIMT_Encode4(250055), // Rule ID 7853 //
94167 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
94168 // (fsub:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (FSUB_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
94169 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZZZ_H),
94170 GIR_RootConstrainSelectedInstOperands,
94171 // GIR_Coverage, 7853,
94172 GIR_Done,
94173 // Label 5389: @250055
94174 GIM_Try, /*On fail goto*//*Label 5390*/ GIMT_Encode4(250070), // Rule ID 11776 //
94175 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasB16B16_HasSVE2orSME2),
94176 // (fsub:{ *:[nxv8bf16] } nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2) => (BFSUB_ZZZ:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2)
94177 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BFSUB_ZZZ),
94178 GIR_RootConstrainSelectedInstOperands,
94179 // GIR_Coverage, 11776,
94180 GIR_Done,
94181 // Label 5390: @250070
94182 GIM_Reject,
94183 // Label 5388: @250071
94184 GIM_Reject,
94185 // Label 5373: @250072
94186 GIM_Reject,
94187 // Label 55: @250073
94188 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(22), /*)*//*default:*//*Label 5402*/ GIMT_Encode4(255138),
94189 /*GILLT_s16*//*Label 5391*/ GIMT_Encode4(250168),
94190 /*GILLT_s32*//*Label 5392*/ GIMT_Encode4(250810),
94191 /*GILLT_s64*//*Label 5393*/ GIMT_Encode4(251440), GIMT_Encode4(0),
94192 /*GILLT_v2s32*//*Label 5394*/ GIMT_Encode4(252070),
94193 /*GILLT_v2s64*//*Label 5395*/ GIMT_Encode4(252428),
94194 /*GILLT_v4s16*//*Label 5396*/ GIMT_Encode4(252786),
94195 /*GILLT_v4s32*//*Label 5397*/ GIMT_Encode4(252956), GIMT_Encode4(0),
94196 /*GILLT_v8s16*//*Label 5398*/ GIMT_Encode4(253314), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
94197 /*GILLT_nxv2s64*//*Label 5399*/ GIMT_Encode4(255039), GIMT_Encode4(0), GIMT_Encode4(0),
94198 /*GILLT_nxv4s32*//*Label 5400*/ GIMT_Encode4(255065), GIMT_Encode4(0),
94199 /*GILLT_nxv8s16*//*Label 5401*/ GIMT_Encode4(255091),
94200 // Label 5391: @250168
94201 GIM_Try, /*On fail goto*//*Label 5403*/ GIMT_Encode4(250809),
94202 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
94203 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
94204 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
94205 GIM_Try, /*On fail goto*//*Label 5404*/ GIMT_Encode4(250296), // Rule ID 5831 //
94206 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
94207 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
94208 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94209 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
94210 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94211 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94212 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
94213 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
94214 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94215 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
94216 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
94217 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94218 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
94219 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
94220 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
94221 // MIs[3] Operand 1
94222 // No operand predicates
94223 GIM_CheckIsSafeToFold, /*NumInsns*/3,
94224 // (fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMULv1i16_indexed:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
94225 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
94226 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
94227 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94228 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
94229 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
94230 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94231 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
94232 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94233 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
94234 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
94235 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
94236 GIR_RootConstrainSelectedInstOperands,
94237 // GIR_Coverage, 5831,
94238 GIR_EraseRootFromParent_Done,
94239 // Label 5404: @250296
94240 GIM_Try, /*On fail goto*//*Label 5405*/ GIMT_Encode4(250409), // Rule ID 13165 //
94241 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
94242 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
94243 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94244 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
94245 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94246 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94247 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
94248 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
94249 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
94250 // MIs[2] Operand 1
94251 // No operand predicates
94252 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
94253 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94254 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
94255 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
94256 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94257 GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
94258 GIM_CheckIsSafeToFold, /*NumInsns*/3,
94259 // (fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })) => (FMULv1i16_indexed:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
94260 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
94261 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
94262 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94263 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
94264 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
94265 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94266 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
94267 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94268 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
94269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
94270 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
94271 GIR_RootConstrainSelectedInstOperands,
94272 // GIR_Coverage, 13165,
94273 GIR_EraseRootFromParent_Done,
94274 // Label 5405: @250409
94275 GIM_Try, /*On fail goto*//*Label 5406*/ GIMT_Encode4(250488), // Rule ID 13080 //
94276 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
94277 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
94278 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94279 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
94280 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94281 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94282 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
94283 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
94284 GIM_CheckIsSafeToFold, /*NumInsns*/1,
94285 // (fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rn) => (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }))
94286 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
94287 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
94288 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94289 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rm
94290 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
94291 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94292 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULHrr),
94293 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94294 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
94295 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
94296 GIR_RootConstrainSelectedInstOperands,
94297 // GIR_Coverage, 13080,
94298 GIR_EraseRootFromParent_Done,
94299 // Label 5406: @250488
94300 GIM_Try, /*On fail goto*//*Label 5407*/ GIMT_Encode4(250567), // Rule ID 4488 //
94301 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
94302 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
94303 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
94304 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94305 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
94306 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94307 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94308 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
94309 GIM_CheckIsSafeToFold, /*NumInsns*/1,
94310 // (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })) => (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }))
94311 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
94312 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
94313 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94314 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rm
94315 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
94316 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94317 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULHrr),
94318 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94319 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
94320 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
94321 GIR_RootConstrainSelectedInstOperands,
94322 // GIR_Coverage, 4488,
94323 GIR_EraseRootFromParent_Done,
94324 // Label 5407: @250567
94325 GIM_Try, /*On fail goto*//*Label 5408*/ GIMT_Encode4(250630), // Rule ID 12707 //
94326 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
94327 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
94328 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94329 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
94330 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94331 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
94332 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
94333 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
94334 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
94335 // MIs[2] Operand 1
94336 // No operand predicates
94337 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
94338 GIM_CheckIsSafeToFold, /*NumInsns*/2,
94339 // (fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16Op:{ *:[f16] }:$Rn) => (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
94340 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
94341 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94342 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
94343 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
94344 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
94345 GIR_RootConstrainSelectedInstOperands,
94346 // GIR_Coverage, 12707,
94347 GIR_EraseRootFromParent_Done,
94348 // Label 5408: @250630
94349 GIM_Try, /*On fail goto*//*Label 5409*/ GIMT_Encode4(250693), // Rule ID 1999 //
94350 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
94351 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
94352 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
94353 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94354 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
94355 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94356 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
94357 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
94358 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
94359 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
94360 // MIs[2] Operand 1
94361 // No operand predicates
94362 GIM_CheckIsSafeToFold, /*NumInsns*/2,
94363 // (fmul:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
94364 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
94365 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94366 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
94367 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
94368 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
94369 GIR_RootConstrainSelectedInstOperands,
94370 // GIR_Coverage, 1999,
94371 GIR_EraseRootFromParent_Done,
94372 // Label 5409: @250693
94373 GIM_Try, /*On fail goto*//*Label 5410*/ GIMT_Encode4(250737), // Rule ID 4493 //
94374 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
94375 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
94376 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
94377 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
94378 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
94379 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
94380 GIM_CheckIsSafeToFold, /*NumInsns*/1,
94381 // (fmul:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$a), FPR16:{ *:[f16] }:$b) => (FNMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$a, FPR16:{ *:[f16] }:$b)
94382 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULHrr),
94383 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
94385 GIR_RootToRootCopy, /*OpIdx*/2, // b
94386 GIR_RootConstrainSelectedInstOperands,
94387 // GIR_Coverage, 4493,
94388 GIR_EraseRootFromParent_Done,
94389 // Label 5410: @250737
94390 GIM_Try, /*On fail goto*//*Label 5411*/ GIMT_Encode4(250781), // Rule ID 13085 //
94391 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
94392 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
94393 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
94394 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
94395 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
94396 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
94397 GIM_CheckIsSafeToFold, /*NumInsns*/1,
94398 // (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$b, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$a)) => (FNMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$a, FPR16:{ *:[f16] }:$b)
94399 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULHrr),
94400 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
94402 GIR_RootToRootCopy, /*OpIdx*/1, // b
94403 GIR_RootConstrainSelectedInstOperands,
94404 // GIR_Coverage, 13085,
94405 GIR_EraseRootFromParent_Done,
94406 // Label 5411: @250781
94407 GIM_Try, /*On fail goto*//*Label 5412*/ GIMT_Encode4(250808), // Rule ID 614 //
94408 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
94409 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
94410 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
94411 // (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
94412 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULHrr),
94413 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
94414 GIR_RootConstrainSelectedInstOperands,
94415 // GIR_Coverage, 614,
94416 GIR_Done,
94417 // Label 5412: @250808
94418 GIM_Reject,
94419 // Label 5403: @250809
94420 GIM_Reject,
94421 // Label 5392: @250810
94422 GIM_Try, /*On fail goto*//*Label 5413*/ GIMT_Encode4(251439),
94423 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
94424 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
94425 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
94426 GIM_Try, /*On fail goto*//*Label 5414*/ GIMT_Encode4(250938), // Rule ID 5833 //
94427 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
94428 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
94429 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94430 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
94431 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94432 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94433 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
94434 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
94435 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94436 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
94437 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
94438 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94439 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
94440 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
94441 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
94442 // MIs[3] Operand 1
94443 // No operand predicates
94444 GIM_CheckIsSafeToFold, /*NumInsns*/3,
94445 // (fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (FMULv1i32_indexed:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
94446 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
94447 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
94448 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94449 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rn
94450 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
94451 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94452 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
94453 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94454 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
94455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
94456 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
94457 GIR_RootConstrainSelectedInstOperands,
94458 // GIR_Coverage, 5833,
94459 GIR_EraseRootFromParent_Done,
94460 // Label 5414: @250938
94461 GIM_Try, /*On fail goto*//*Label 5415*/ GIMT_Encode4(251051), // Rule ID 13167 //
94462 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
94463 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
94464 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94465 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
94466 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94467 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94468 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
94469 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
94470 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
94471 // MIs[2] Operand 1
94472 // No operand predicates
94473 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
94474 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94475 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
94476 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
94477 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94478 GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
94479 GIM_CheckIsSafeToFold, /*NumInsns*/3,
94480 // (fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })) => (FMULv1i32_indexed:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
94481 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
94482 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
94483 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94484 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rn
94485 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
94486 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94487 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
94488 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94489 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
94490 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
94491 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
94492 GIR_RootConstrainSelectedInstOperands,
94493 // GIR_Coverage, 13167,
94494 GIR_EraseRootFromParent_Done,
94495 // Label 5415: @251051
94496 GIM_Try, /*On fail goto*//*Label 5416*/ GIMT_Encode4(251127), // Rule ID 13082 //
94497 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
94498 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94499 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
94500 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94501 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94502 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
94503 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
94504 GIM_CheckIsSafeToFold, /*NumInsns*/1,
94505 // (fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rn) => (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }))
94506 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
94507 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
94508 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94509 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rm
94510 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
94511 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94512 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULSrr),
94513 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94514 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
94515 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
94516 GIR_RootConstrainSelectedInstOperands,
94517 // GIR_Coverage, 13082,
94518 GIR_EraseRootFromParent_Done,
94519 // Label 5416: @251127
94520 GIM_Try, /*On fail goto*//*Label 5417*/ GIMT_Encode4(251203), // Rule ID 4490 //
94521 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
94522 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
94523 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94524 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
94525 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94526 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94527 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
94528 GIM_CheckIsSafeToFold, /*NumInsns*/1,
94529 // (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })) => (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }))
94530 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
94531 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
94532 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94533 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rm
94534 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
94535 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94536 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULSrr),
94537 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94538 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
94539 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
94540 GIR_RootConstrainSelectedInstOperands,
94541 // GIR_Coverage, 4490,
94542 GIR_EraseRootFromParent_Done,
94543 // Label 5417: @251203
94544 GIM_Try, /*On fail goto*//*Label 5418*/ GIMT_Encode4(251266), // Rule ID 12709 //
94545 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
94546 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
94547 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94548 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
94549 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94550 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94551 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
94552 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
94553 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
94554 // MIs[2] Operand 1
94555 // No operand predicates
94556 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
94557 GIM_CheckIsSafeToFold, /*NumInsns*/2,
94558 // (fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32Op:{ *:[f32] }:$Rn) => (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
94559 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
94560 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94561 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
94562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
94563 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
94564 GIR_RootConstrainSelectedInstOperands,
94565 // GIR_Coverage, 12709,
94566 GIR_EraseRootFromParent_Done,
94567 // Label 5418: @251266
94568 GIM_Try, /*On fail goto*//*Label 5419*/ GIMT_Encode4(251329), // Rule ID 2001 //
94569 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
94570 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
94571 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
94572 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94573 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
94574 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94575 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94576 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
94577 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
94578 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
94579 // MIs[2] Operand 1
94580 // No operand predicates
94581 GIM_CheckIsSafeToFold, /*NumInsns*/2,
94582 // (fmul:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
94583 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
94584 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94585 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
94586 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
94587 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
94588 GIR_RootConstrainSelectedInstOperands,
94589 // GIR_Coverage, 2001,
94590 GIR_EraseRootFromParent_Done,
94591 // Label 5419: @251329
94592 GIM_Try, /*On fail goto*//*Label 5420*/ GIMT_Encode4(251370), // Rule ID 4494 //
94593 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
94594 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
94595 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
94596 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
94597 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
94598 GIM_CheckIsSafeToFold, /*NumInsns*/1,
94599 // (fmul:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$a), FPR32:{ *:[f32] }:$b) => (FNMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$a, FPR32:{ *:[f32] }:$b)
94600 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULSrr),
94601 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
94603 GIR_RootToRootCopy, /*OpIdx*/2, // b
94604 GIR_RootConstrainSelectedInstOperands,
94605 // GIR_Coverage, 4494,
94606 GIR_EraseRootFromParent_Done,
94607 // Label 5420: @251370
94608 GIM_Try, /*On fail goto*//*Label 5421*/ GIMT_Encode4(251411), // Rule ID 13086 //
94609 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
94610 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
94611 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
94612 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
94613 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
94614 GIM_CheckIsSafeToFold, /*NumInsns*/1,
94615 // (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$b, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$a)) => (FNMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$a, FPR32:{ *:[f32] }:$b)
94616 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULSrr),
94617 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
94619 GIR_RootToRootCopy, /*OpIdx*/1, // b
94620 GIR_RootConstrainSelectedInstOperands,
94621 // GIR_Coverage, 13086,
94622 GIR_EraseRootFromParent_Done,
94623 // Label 5421: @251411
94624 GIM_Try, /*On fail goto*//*Label 5422*/ GIMT_Encode4(251438), // Rule ID 616 //
94625 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
94626 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
94627 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
94628 // (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
94629 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULSrr),
94630 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
94631 GIR_RootConstrainSelectedInstOperands,
94632 // GIR_Coverage, 616,
94633 GIR_Done,
94634 // Label 5422: @251438
94635 GIM_Reject,
94636 // Label 5413: @251439
94637 GIM_Reject,
94638 // Label 5393: @251440
94639 GIM_Try, /*On fail goto*//*Label 5423*/ GIMT_Encode4(252069),
94640 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
94641 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
94642 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
94643 GIM_Try, /*On fail goto*//*Label 5424*/ GIMT_Encode4(251568), // Rule ID 5835 //
94644 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
94645 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
94646 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94647 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
94648 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94649 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94650 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
94651 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
94652 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94653 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
94654 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
94655 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94656 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
94657 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
94658 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
94659 // MIs[3] Operand 1
94660 // No operand predicates
94661 GIM_CheckIsSafeToFold, /*NumInsns*/3,
94662 // (fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)) => (FMULv1i64_indexed:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
94663 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
94664 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
94665 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94666 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
94667 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
94668 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94669 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
94670 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94671 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
94672 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
94673 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
94674 GIR_RootConstrainSelectedInstOperands,
94675 // GIR_Coverage, 5835,
94676 GIR_EraseRootFromParent_Done,
94677 // Label 5424: @251568
94678 GIM_Try, /*On fail goto*//*Label 5425*/ GIMT_Encode4(251681), // Rule ID 13169 //
94679 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
94680 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
94681 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94682 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
94683 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94684 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94685 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
94686 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
94687 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
94688 // MIs[2] Operand 1
94689 // No operand predicates
94690 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
94691 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94692 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
94693 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
94694 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94695 GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
94696 GIM_CheckIsSafeToFold, /*NumInsns*/3,
94697 // (fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })) => (FMULv1i64_indexed:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
94698 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
94699 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
94700 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94701 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
94702 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
94703 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94704 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
94705 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94706 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
94707 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
94708 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
94709 GIR_RootConstrainSelectedInstOperands,
94710 // GIR_Coverage, 13169,
94711 GIR_EraseRootFromParent_Done,
94712 // Label 5425: @251681
94713 GIM_Try, /*On fail goto*//*Label 5426*/ GIMT_Encode4(251757), // Rule ID 13084 //
94714 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
94715 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94716 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
94717 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94718 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94719 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
94720 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
94721 GIM_CheckIsSafeToFold, /*NumInsns*/1,
94722 // (fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rn) => (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }))
94723 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
94724 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
94725 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94726 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rm
94727 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
94728 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94729 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULDrr),
94730 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94731 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
94732 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
94733 GIR_RootConstrainSelectedInstOperands,
94734 // GIR_Coverage, 13084,
94735 GIR_EraseRootFromParent_Done,
94736 // Label 5426: @251757
94737 GIM_Try, /*On fail goto*//*Label 5427*/ GIMT_Encode4(251833), // Rule ID 4492 //
94738 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
94739 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
94740 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94741 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
94742 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94743 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94744 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
94745 GIM_CheckIsSafeToFold, /*NumInsns*/1,
94746 // (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })) => (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }))
94747 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
94748 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
94749 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94750 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rm
94751 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
94752 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94753 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULDrr),
94754 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94755 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
94756 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
94757 GIR_RootConstrainSelectedInstOperands,
94758 // GIR_Coverage, 4492,
94759 GIR_EraseRootFromParent_Done,
94760 // Label 5427: @251833
94761 GIM_Try, /*On fail goto*//*Label 5428*/ GIMT_Encode4(251896), // Rule ID 12711 //
94762 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
94763 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
94764 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94765 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
94766 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94767 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94768 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
94769 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
94770 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
94771 // MIs[2] Operand 1
94772 // No operand predicates
94773 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
94774 GIM_CheckIsSafeToFold, /*NumInsns*/2,
94775 // (fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64Op:{ *:[f64] }:$Rn) => (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
94776 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
94777 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94778 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
94779 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
94780 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
94781 GIR_RootConstrainSelectedInstOperands,
94782 // GIR_Coverage, 12711,
94783 GIR_EraseRootFromParent_Done,
94784 // Label 5428: @251896
94785 GIM_Try, /*On fail goto*//*Label 5429*/ GIMT_Encode4(251959), // Rule ID 2003 //
94786 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
94787 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
94788 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
94789 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
94790 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
94791 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94792 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94793 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
94794 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
94795 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
94796 // MIs[2] Operand 1
94797 // No operand predicates
94798 GIM_CheckIsSafeToFold, /*NumInsns*/2,
94799 // (fmul:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)) => (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
94800 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
94801 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94802 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
94803 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
94804 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
94805 GIR_RootConstrainSelectedInstOperands,
94806 // GIR_Coverage, 2003,
94807 GIR_EraseRootFromParent_Done,
94808 // Label 5429: @251959
94809 GIM_Try, /*On fail goto*//*Label 5430*/ GIMT_Encode4(252000), // Rule ID 4495 //
94810 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
94811 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
94812 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
94813 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
94814 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
94815 GIM_CheckIsSafeToFold, /*NumInsns*/1,
94816 // (fmul:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$a), FPR64:{ *:[f64] }:$b) => (FNMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$a, FPR64:{ *:[f64] }:$b)
94817 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULDrr),
94818 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94819 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
94820 GIR_RootToRootCopy, /*OpIdx*/2, // b
94821 GIR_RootConstrainSelectedInstOperands,
94822 // GIR_Coverage, 4495,
94823 GIR_EraseRootFromParent_Done,
94824 // Label 5430: @252000
94825 GIM_Try, /*On fail goto*//*Label 5431*/ GIMT_Encode4(252041), // Rule ID 13087 //
94826 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
94827 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
94828 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
94829 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
94830 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
94831 GIM_CheckIsSafeToFold, /*NumInsns*/1,
94832 // (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$b, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$a)) => (FNMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$a, FPR64:{ *:[f64] }:$b)
94833 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULDrr),
94834 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94835 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
94836 GIR_RootToRootCopy, /*OpIdx*/1, // b
94837 GIR_RootConstrainSelectedInstOperands,
94838 // GIR_Coverage, 13087,
94839 GIR_EraseRootFromParent_Done,
94840 // Label 5431: @252041
94841 GIM_Try, /*On fail goto*//*Label 5432*/ GIMT_Encode4(252068), // Rule ID 618 //
94842 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
94843 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
94844 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
94845 // (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
94846 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULDrr),
94847 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
94848 GIR_RootConstrainSelectedInstOperands,
94849 // GIR_Coverage, 618,
94850 GIR_Done,
94851 // Label 5432: @252068
94852 GIM_Reject,
94853 // Label 5423: @252069
94854 GIM_Reject,
94855 // Label 5394: @252070
94856 GIM_Try, /*On fail goto*//*Label 5433*/ GIMT_Encode4(252427),
94857 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
94858 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
94859 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
94860 GIM_Try, /*On fail goto*//*Label 5434*/ GIMT_Encode4(252148), // Rule ID 12701 //
94861 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
94862 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
94863 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
94864 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
94865 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94866 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94867 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
94868 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
94869 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
94870 // MIs[2] Operand 1
94871 // No operand predicates
94872 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
94873 GIM_CheckIsSafeToFold, /*NumInsns*/2,
94874 // (fmul:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
94875 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
94876 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94877 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
94878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
94879 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
94880 GIR_RootConstrainSelectedInstOperands,
94881 // GIR_Coverage, 12701,
94882 GIR_EraseRootFromParent_Done,
94883 // Label 5434: @252148
94884 GIM_Try, /*On fail goto*//*Label 5435*/ GIMT_Encode4(252211), // Rule ID 1993 //
94885 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
94886 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
94887 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
94888 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
94889 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
94890 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94891 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94892 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
94893 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
94894 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
94895 // MIs[2] Operand 1
94896 // No operand predicates
94897 GIM_CheckIsSafeToFold, /*NumInsns*/2,
94898 // (fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
94899 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
94900 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94901 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
94902 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
94903 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
94904 GIR_RootConstrainSelectedInstOperands,
94905 // GIR_Coverage, 1993,
94906 GIR_EraseRootFromParent_Done,
94907 // Label 5435: @252211
94908 GIM_Try, /*On fail goto*//*Label 5436*/ GIMT_Encode4(252305), // Rule ID 13171 //
94909 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
94910 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
94911 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
94912 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
94913 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
94914 GIM_CheckIsSafeToFold, /*NumInsns*/1,
94915 // (fmul:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rn) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
94916 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
94917 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
94918 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
94919 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94920 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
94921 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
94922 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94923 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
94924 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
94925 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
94926 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
94927 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94928 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
94929 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
94930 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94931 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
94932 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
94933 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
94934 GIR_RootConstrainSelectedInstOperands,
94935 // GIR_Coverage, 13171,
94936 GIR_EraseRootFromParent_Done,
94937 // Label 5436: @252305
94938 GIM_Try, /*On fail goto*//*Label 5437*/ GIMT_Encode4(252399), // Rule ID 5837 //
94939 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
94940 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
94941 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
94942 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
94943 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
94944 GIM_CheckIsSafeToFold, /*NumInsns*/1,
94945 // (fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rm)) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
94946 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
94947 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
94948 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
94949 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94950 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
94951 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
94952 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
94953 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
94954 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
94955 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
94956 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
94957 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
94958 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
94959 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
94960 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
94961 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
94962 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
94963 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
94964 GIR_RootConstrainSelectedInstOperands,
94965 // GIR_Coverage, 5837,
94966 GIR_EraseRootFromParent_Done,
94967 // Label 5437: @252399
94968 GIM_Try, /*On fail goto*//*Label 5438*/ GIMT_Encode4(252426), // Rule ID 1310 //
94969 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
94970 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
94971 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
94972 // (fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMULv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
94973 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv2f32),
94974 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
94975 GIR_RootConstrainSelectedInstOperands,
94976 // GIR_Coverage, 1310,
94977 GIR_Done,
94978 // Label 5438: @252426
94979 GIM_Reject,
94980 // Label 5433: @252427
94981 GIM_Reject,
94982 // Label 5395: @252428
94983 GIM_Try, /*On fail goto*//*Label 5439*/ GIMT_Encode4(252785),
94984 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
94985 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
94986 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94987 GIM_Try, /*On fail goto*//*Label 5440*/ GIMT_Encode4(252506), // Rule ID 12705 //
94988 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
94989 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
94990 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
94991 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
94992 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
94993 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
94994 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
94995 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
94996 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
94997 // MIs[2] Operand 1
94998 // No operand predicates
94999 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95000 GIM_CheckIsSafeToFold, /*NumInsns*/2,
95001 // (fmul:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
95002 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
95003 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
95004 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
95005 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
95006 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
95007 GIR_RootConstrainSelectedInstOperands,
95008 // GIR_Coverage, 12705,
95009 GIR_EraseRootFromParent_Done,
95010 // Label 5440: @252506
95011 GIM_Try, /*On fail goto*//*Label 5441*/ GIMT_Encode4(252569), // Rule ID 1997 //
95012 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
95013 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95014 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
95015 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
95016 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
95017 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
95018 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95019 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
95020 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
95021 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
95022 // MIs[2] Operand 1
95023 // No operand predicates
95024 GIM_CheckIsSafeToFold, /*NumInsns*/2,
95025 // (fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
95026 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
95027 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
95028 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
95029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
95030 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
95031 GIR_RootConstrainSelectedInstOperands,
95032 // GIR_Coverage, 1997,
95033 GIR_EraseRootFromParent_Done,
95034 // Label 5441: @252569
95035 GIM_Try, /*On fail goto*//*Label 5442*/ GIMT_Encode4(252663), // Rule ID 13175 //
95036 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
95037 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
95038 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
95039 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
95040 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95041 GIM_CheckIsSafeToFold, /*NumInsns*/1,
95042 // (fmul:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rn) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
95043 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
95044 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
95045 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
95046 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95047 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
95048 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
95049 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95050 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
95051 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
95052 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
95053 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
95054 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95055 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
95056 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
95057 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
95058 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
95059 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
95060 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
95061 GIR_RootConstrainSelectedInstOperands,
95062 // GIR_Coverage, 13175,
95063 GIR_EraseRootFromParent_Done,
95064 // Label 5442: @252663
95065 GIM_Try, /*On fail goto*//*Label 5443*/ GIMT_Encode4(252757), // Rule ID 5841 //
95066 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95067 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
95068 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
95069 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
95070 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
95071 GIM_CheckIsSafeToFold, /*NumInsns*/1,
95072 // (fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rm)) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
95073 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
95074 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
95075 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
95076 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95077 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
95078 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
95079 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95080 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
95081 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
95082 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
95083 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
95084 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95085 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
95086 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
95087 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
95088 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
95089 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
95090 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
95091 GIR_RootConstrainSelectedInstOperands,
95092 // GIR_Coverage, 5841,
95093 GIR_EraseRootFromParent_Done,
95094 // Label 5443: @252757
95095 GIM_Try, /*On fail goto*//*Label 5444*/ GIMT_Encode4(252784), // Rule ID 1314 //
95096 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
95097 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95098 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95099 // (fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMULv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
95100 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv2f64),
95101 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
95102 GIR_RootConstrainSelectedInstOperands,
95103 // GIR_Coverage, 1314,
95104 GIR_Done,
95105 // Label 5444: @252784
95106 GIM_Reject,
95107 // Label 5439: @252785
95108 GIM_Reject,
95109 // Label 5396: @252786
95110 GIM_Try, /*On fail goto*//*Label 5445*/ GIMT_Encode4(252955),
95111 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
95112 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
95113 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
95114 GIM_Try, /*On fail goto*//*Label 5446*/ GIMT_Encode4(252864), // Rule ID 12695 //
95115 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
95116 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
95117 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
95118 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
95119 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
95120 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
95121 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
95122 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
95123 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
95124 // MIs[2] Operand 1
95125 // No operand predicates
95126 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
95127 GIM_CheckIsSafeToFold, /*NumInsns*/2,
95128 // (fmul:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rn) => (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
95129 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
95130 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
95131 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
95132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
95133 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
95134 GIR_RootConstrainSelectedInstOperands,
95135 // GIR_Coverage, 12695,
95136 GIR_EraseRootFromParent_Done,
95137 // Label 5446: @252864
95138 GIM_Try, /*On fail goto*//*Label 5447*/ GIMT_Encode4(252927), // Rule ID 1987 //
95139 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
95140 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
95141 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
95142 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
95143 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
95144 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
95145 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
95146 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
95147 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
95148 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
95149 // MIs[2] Operand 1
95150 // No operand predicates
95151 GIM_CheckIsSafeToFold, /*NumInsns*/2,
95152 // (fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
95153 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
95154 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
95155 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
95156 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
95157 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
95158 GIR_RootConstrainSelectedInstOperands,
95159 // GIR_Coverage, 1987,
95160 GIR_EraseRootFromParent_Done,
95161 // Label 5447: @252927
95162 GIM_Try, /*On fail goto*//*Label 5448*/ GIMT_Encode4(252954), // Rule ID 1306 //
95163 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
95164 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
95165 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
95166 // (fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMULv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
95167 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f16),
95168 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
95169 GIR_RootConstrainSelectedInstOperands,
95170 // GIR_Coverage, 1306,
95171 GIR_Done,
95172 // Label 5448: @252954
95173 GIM_Reject,
95174 // Label 5445: @252955
95175 GIM_Reject,
95176 // Label 5397: @252956
95177 GIM_Try, /*On fail goto*//*Label 5449*/ GIMT_Encode4(253313),
95178 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
95179 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
95180 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95181 GIM_Try, /*On fail goto*//*Label 5450*/ GIMT_Encode4(253034), // Rule ID 12703 //
95182 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
95183 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
95184 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
95185 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
95186 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
95187 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95188 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
95189 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
95190 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
95191 // MIs[2] Operand 1
95192 // No operand predicates
95193 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95194 GIM_CheckIsSafeToFold, /*NumInsns*/2,
95195 // (fmul:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
95196 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
95197 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
95198 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
95199 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
95200 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
95201 GIR_RootConstrainSelectedInstOperands,
95202 // GIR_Coverage, 12703,
95203 GIR_EraseRootFromParent_Done,
95204 // Label 5450: @253034
95205 GIM_Try, /*On fail goto*//*Label 5451*/ GIMT_Encode4(253097), // Rule ID 1995 //
95206 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
95207 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95208 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
95209 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
95210 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
95211 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
95212 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95213 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
95214 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
95215 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
95216 // MIs[2] Operand 1
95217 // No operand predicates
95218 GIM_CheckIsSafeToFold, /*NumInsns*/2,
95219 // (fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
95220 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
95221 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
95222 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
95223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
95224 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
95225 GIR_RootConstrainSelectedInstOperands,
95226 // GIR_Coverage, 1995,
95227 GIR_EraseRootFromParent_Done,
95228 // Label 5451: @253097
95229 GIM_Try, /*On fail goto*//*Label 5452*/ GIMT_Encode4(253191), // Rule ID 13173 //
95230 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
95231 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
95232 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
95233 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
95234 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95235 GIM_CheckIsSafeToFold, /*NumInsns*/1,
95236 // (fmul:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rn) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
95237 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
95238 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
95239 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
95240 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95241 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
95242 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
95243 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95244 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
95245 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
95246 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
95247 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
95248 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95249 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
95250 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
95251 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
95252 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
95253 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
95254 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
95255 GIR_RootConstrainSelectedInstOperands,
95256 // GIR_Coverage, 13173,
95257 GIR_EraseRootFromParent_Done,
95258 // Label 5452: @253191
95259 GIM_Try, /*On fail goto*//*Label 5453*/ GIMT_Encode4(253285), // Rule ID 5839 //
95260 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95261 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
95262 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
95263 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
95264 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
95265 GIM_CheckIsSafeToFold, /*NumInsns*/1,
95266 // (fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rm)) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
95267 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
95268 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
95269 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
95270 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95271 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
95272 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
95273 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95274 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
95275 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
95276 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
95277 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
95278 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95279 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
95280 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
95281 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
95282 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
95283 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
95284 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
95285 GIR_RootConstrainSelectedInstOperands,
95286 // GIR_Coverage, 5839,
95287 GIR_EraseRootFromParent_Done,
95288 // Label 5453: @253285
95289 GIM_Try, /*On fail goto*//*Label 5454*/ GIMT_Encode4(253312), // Rule ID 1312 //
95290 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
95291 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95292 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95293 // (fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMULv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
95294 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
95295 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
95296 GIR_RootConstrainSelectedInstOperands,
95297 // GIR_Coverage, 1312,
95298 GIR_Done,
95299 // Label 5454: @253312
95300 GIM_Reject,
95301 // Label 5449: @253313
95302 GIM_Reject,
95303 // Label 5398: @253314
95304 GIM_Try, /*On fail goto*//*Label 5455*/ GIMT_Encode4(255038),
95305 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
95306 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
95307 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95308 GIM_Try, /*On fail goto*//*Label 5456*/ GIMT_Encode4(253392), // Rule ID 12697 //
95309 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
95310 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
95311 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
95312 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
95313 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
95314 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
95315 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
95316 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
95317 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
95318 // MIs[2] Operand 1
95319 // No operand predicates
95320 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95321 GIM_CheckIsSafeToFold, /*NumInsns*/2,
95322 // (fmul:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rn) => (FMULv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
95323 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv8i16_indexed),
95324 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
95325 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
95326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
95327 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
95328 GIR_RootConstrainSelectedInstOperands,
95329 // GIR_Coverage, 12697,
95330 GIR_EraseRootFromParent_Done,
95331 // Label 5456: @253392
95332 GIM_Try, /*On fail goto*//*Label 5457*/ GIMT_Encode4(253455), // Rule ID 1989 //
95333 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
95334 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95335 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
95336 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
95337 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
95338 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
95339 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
95340 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
95341 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
95342 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
95343 // MIs[2] Operand 1
95344 // No operand predicates
95345 GIM_CheckIsSafeToFold, /*NumInsns*/2,
95346 // (fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMULv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
95347 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv8i16_indexed),
95348 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
95349 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
95350 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
95351 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
95352 GIR_RootConstrainSelectedInstOperands,
95353 // GIR_Coverage, 1989,
95354 GIR_EraseRootFromParent_Done,
95355 // Label 5457: @253455
95356 GIM_Try, /*On fail goto*//*Label 5458*/ GIMT_Encode4(253482), // Rule ID 1308 //
95357 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
95358 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95359 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95360 // (fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMULv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
95361 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv8f16),
95362 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
95363 GIR_RootConstrainSelectedInstOperands,
95364 // GIR_Coverage, 1308,
95365 GIR_Done,
95366 // Label 5458: @253482
95367 GIM_Try, /*On fail goto*//*Label 5459*/ GIMT_Encode4(253744), // Rule ID 6728 //
95368 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
95369 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95370 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95371 // (fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FMULv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FMULv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
95372 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
95373 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
95374 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
95375 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
95376 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
95377 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
95378 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
95379 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
95380 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
95381 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
95382 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
95383 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
95384 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95385 GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
95386 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
95387 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
95388 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95389 GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
95390 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
95391 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
95392 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95393 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
95394 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
95395 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
95396 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
95397 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95398 GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
95399 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
95400 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95401 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
95402 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95403 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
95404 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
95405 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
95406 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95407 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
95408 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
95409 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95410 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
95411 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95412 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
95413 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
95414 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
95415 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95416 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
95417 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
95418 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
95419 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
95420 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95421 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
95422 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
95423 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
95424 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95425 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
95426 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
95427 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95428 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
95429 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
95430 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
95431 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
95432 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95433 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
95434 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
95435 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
95436 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
95437 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
95438 GIR_RootConstrainSelectedInstOperands,
95439 // GIR_Coverage, 6728,
95440 GIR_EraseRootFromParent_Done,
95441 // Label 5459: @253744
95442 GIM_Try, /*On fail goto*//*Label 5460*/ GIMT_Encode4(253956), // Rule ID 6730 //
95443 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16),
95444 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95445 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95446 // (fmul:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFCVTN2:{ *:[v8bf16] } (BFCVTN:{ *:[v8bf16] } (FMULv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] })))), (FMULv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)))
95447 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
95448 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
95449 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
95450 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
95451 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
95452 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
95453 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
95454 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
95455 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
95456 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
95457 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95458 GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/0, /*OpIdx*/2, // Rm
95459 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
95460 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
95461 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95462 GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
95463 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
95464 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
95465 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95466 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
95467 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/8,
95468 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
95469 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
95470 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95471 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
95472 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
95473 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95474 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
95475 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95476 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
95477 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
95478 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
95479 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95480 GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
95481 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
95482 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95483 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
95484 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95485 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
95486 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
95487 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
95488 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95489 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
95490 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/4,
95491 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
95492 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN),
95493 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95494 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
95495 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
95496 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN2),
95497 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
95498 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
95499 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
95500 GIR_RootConstrainSelectedInstOperands,
95501 // GIR_Coverage, 6730,
95502 GIR_EraseRootFromParent_Done,
95503 // Label 5460: @253956
95504 GIM_Try, /*On fail goto*//*Label 5461*/ GIMT_Encode4(255037), // Rule ID 6732 //
95505 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoBF16),
95506 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95507 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95508 // (fmul:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (UZP2v8i16:{ *:[v8bf16] } (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FMULv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), (FMULv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] })))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FMULv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FMULv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), 64:{ *:[i32] }, 16:{ *:[i32] })), (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FMULv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), (FMULv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FMULv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FMULv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), 64:{ *:[i32] }, 16:{ *:[i32] })))
95509 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
95510 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
95511 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
95512 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
95513 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
95514 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
95515 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
95516 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
95517 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
95518 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s16,
95519 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
95520 GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_v4s16,
95521 GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_s128,
95522 GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s128,
95523 GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_v4s32,
95524 GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_v4s32,
95525 GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_v4s16,
95526 GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_v4s32,
95527 GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_v4s16,
95528 GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_s128,
95529 GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_s128,
95530 GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s128,
95531 GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s128,
95532 GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_s128,
95533 GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_v4s32,
95534 GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_v4s32,
95535 GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_v4s16,
95536 GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_v4s32,
95537 GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_v4s16,
95538 GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_s128,
95539 GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_s128,
95540 GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_v4s32,
95541 GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_v4s32,
95542 GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_v4s32,
95543 GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_v4s32,
95544 GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_v4s32,
95545 GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_v4s32,
95546 GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_s128,
95547 GIR_MakeTempReg, /*TempRegID*/38, /*TypeID*/GILLT_s128,
95548 GIR_MakeTempReg, /*TempRegID*/39, /*TypeID*/GILLT_v4s32,
95549 GIR_MakeTempReg, /*TempRegID*/40, /*TypeID*/GILLT_v4s32,
95550 GIR_MakeTempReg, /*TempRegID*/41, /*TypeID*/GILLT_v4s32,
95551 GIR_MakeTempReg, /*TempRegID*/42, /*TypeID*/GILLT_s128,
95552 GIR_MakeTempReg, /*TempRegID*/43, /*TypeID*/GILLT_s128,
95553 GIR_MakeTempReg, /*TempRegID*/44, /*TypeID*/GILLT_s128,
95554 GIR_MakeTempReg, /*TempRegID*/45, /*TypeID*/GILLT_s128,
95555 GIR_MakeTempReg, /*TempRegID*/46, /*TypeID*/GILLT_s128,
95556 GIR_MakeTempReg, /*TempRegID*/47, /*TypeID*/GILLT_v4s32,
95557 GIR_MakeTempReg, /*TempRegID*/48, /*TypeID*/GILLT_v4s32,
95558 GIR_MakeTempReg, /*TempRegID*/49, /*TypeID*/GILLT_v4s32,
95559 GIR_BuildMI, /*InsnID*/50, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
95560 GIR_AddTempRegister, /*InsnID*/50, /*TempRegID*/49, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95561 GIR_Copy, /*NewInsnID*/50, /*OldInsnID*/0, /*OpIdx*/2, // Rm
95562 GIR_ConstrainSelectedInstOperands, /*InsnID*/50,
95563 GIR_BuildMI, /*InsnID*/49, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
95564 GIR_AddTempRegister, /*InsnID*/49, /*TempRegID*/48, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95565 GIR_Copy, /*NewInsnID*/49, /*OldInsnID*/0, /*OpIdx*/1, // Rn
95566 GIR_ConstrainSelectedInstOperands, /*InsnID*/49,
95567 GIR_BuildMI, /*InsnID*/48, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
95568 GIR_AddTempRegister, /*InsnID*/48, /*TempRegID*/47, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95569 GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/48,
95570 GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/49,
95571 GIR_ConstrainSelectedInstOperands, /*InsnID*/48,
95572 GIR_BuildMI, /*InsnID*/47, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
95573 GIR_AddTempRegister, /*InsnID*/47, /*TempRegID*/46, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95574 GIR_AddSimpleTempRegister, /*InsnID*/47, /*TempRegID*/47,
95575 GIR_AddImm8, /*InsnID*/47, /*Imm*/64,
95576 GIR_AddImm8, /*InsnID*/47, /*Imm*/16,
95577 GIR_ConstrainSelectedInstOperands, /*InsnID*/47,
95578 GIR_BuildMI, /*InsnID*/46, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
95579 GIR_AddTempRegister, /*InsnID*/46, /*TempRegID*/45, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95580 GIR_AddImm8, /*InsnID*/46, /*Imm*/127,
95581 GIR_AddImm, /*InsnID*/46, /*Imm*/GIMT_Encode8(264),
95582 GIR_ConstrainSelectedInstOperands, /*InsnID*/46,
95583 GIR_BuildMI, /*InsnID*/45, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
95584 GIR_AddTempRegister, /*InsnID*/45, /*TempRegID*/44, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95585 GIR_AddImm8, /*InsnID*/45, /*Imm*/1,
95586 GIR_AddImm8, /*InsnID*/45, /*Imm*/0,
95587 GIR_ConstrainSelectedInstOperands, /*InsnID*/45,
95588 GIR_BuildMI, /*InsnID*/44, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
95589 GIR_AddTempRegister, /*InsnID*/44, /*TempRegID*/43, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95590 GIR_Copy, /*NewInsnID*/44, /*OldInsnID*/0, /*OpIdx*/1, // Rn
95591 GIR_AddImm8, /*InsnID*/44, /*Imm*/16,
95592 GIR_ConstrainSelectedInstOperands, /*InsnID*/44,
95593 GIR_BuildMI, /*InsnID*/43, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
95594 GIR_AddTempRegister, /*InsnID*/43, /*TempRegID*/42, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95595 GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/43,
95596 GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/44,
95597 GIR_ConstrainSelectedInstOperands, /*InsnID*/43,
95598 GIR_BuildMI, /*InsnID*/42, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
95599 GIR_AddTempRegister, /*InsnID*/42, /*TempRegID*/41, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95600 GIR_Copy, /*NewInsnID*/42, /*OldInsnID*/0, /*OpIdx*/2, // Rm
95601 GIR_ConstrainSelectedInstOperands, /*InsnID*/42,
95602 GIR_BuildMI, /*InsnID*/41, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
95603 GIR_AddTempRegister, /*InsnID*/41, /*TempRegID*/40, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95604 GIR_Copy, /*NewInsnID*/41, /*OldInsnID*/0, /*OpIdx*/1, // Rn
95605 GIR_ConstrainSelectedInstOperands, /*InsnID*/41,
95606 GIR_BuildMI, /*InsnID*/40, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
95607 GIR_AddTempRegister, /*InsnID*/40, /*TempRegID*/39, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95608 GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/40,
95609 GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/41,
95610 GIR_ConstrainSelectedInstOperands, /*InsnID*/40,
95611 GIR_BuildMI, /*InsnID*/39, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
95612 GIR_AddTempRegister, /*InsnID*/39, /*TempRegID*/38, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95613 GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/39,
95614 GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/42,
95615 GIR_ConstrainSelectedInstOperands, /*InsnID*/39,
95616 GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
95617 GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95618 GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/38,
95619 GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/45,
95620 GIR_ConstrainSelectedInstOperands, /*InsnID*/38,
95621 GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
95622 GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95623 GIR_Copy, /*NewInsnID*/37, /*OldInsnID*/0, /*OpIdx*/2, // Rm
95624 GIR_ConstrainSelectedInstOperands, /*InsnID*/37,
95625 GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
95626 GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95627 GIR_Copy, /*NewInsnID*/36, /*OldInsnID*/0, /*OpIdx*/1, // Rn
95628 GIR_ConstrainSelectedInstOperands, /*InsnID*/36,
95629 GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
95630 GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95631 GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/35,
95632 GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/36,
95633 GIR_ConstrainSelectedInstOperands, /*InsnID*/35,
95634 GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
95635 GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95636 GIR_Copy, /*NewInsnID*/34, /*OldInsnID*/0, /*OpIdx*/2, // Rm
95637 GIR_ConstrainSelectedInstOperands, /*InsnID*/34,
95638 GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
95639 GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95640 GIR_Copy, /*NewInsnID*/33, /*OldInsnID*/0, /*OpIdx*/1, // Rn
95641 GIR_ConstrainSelectedInstOperands, /*InsnID*/33,
95642 GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
95643 GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95644 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/32,
95645 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/33,
95646 GIR_ConstrainSelectedInstOperands, /*InsnID*/32,
95647 GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
95648 GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95649 GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/31,
95650 GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/34,
95651 GIR_ConstrainSelectedInstOperands, /*InsnID*/31,
95652 GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
95653 GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95654 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/30,
95655 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/37,
95656 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/46,
95657 GIR_ConstrainSelectedInstOperands, /*InsnID*/30,
95658 GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
95659 GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95660 GIR_CopySubReg, /*NewInsnID*/29, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
95661 GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
95662 GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95663 GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
95664 GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95665 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/28,
95666 GIR_ConstrainSelectedInstOperands, /*InsnID*/28,
95667 GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
95668 GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95669 GIR_CopySubReg, /*NewInsnID*/27, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
95670 GIR_ConstrainOperandRC, /*InsnID*/27, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
95671 GIR_ConstrainOperandRC, /*InsnID*/27, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95672 GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
95673 GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95674 GIR_AddSimpleTempRegister, /*InsnID*/26, /*TempRegID*/26,
95675 GIR_ConstrainSelectedInstOperands, /*InsnID*/26,
95676 GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
95677 GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95678 GIR_AddSimpleTempRegister, /*InsnID*/25, /*TempRegID*/25,
95679 GIR_AddSimpleTempRegister, /*InsnID*/25, /*TempRegID*/27,
95680 GIR_ConstrainSelectedInstOperands, /*InsnID*/25,
95681 GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
95682 GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95683 GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/24,
95684 GIR_AddImm8, /*InsnID*/24, /*Imm*/64,
95685 GIR_AddImm8, /*InsnID*/24, /*Imm*/16,
95686 GIR_ConstrainSelectedInstOperands, /*InsnID*/24,
95687 GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
95688 GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95689 GIR_AddImm8, /*InsnID*/23, /*Imm*/127,
95690 GIR_AddImm, /*InsnID*/23, /*Imm*/GIMT_Encode8(264),
95691 GIR_ConstrainSelectedInstOperands, /*InsnID*/23,
95692 GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
95693 GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95694 GIR_AddImm8, /*InsnID*/22, /*Imm*/1,
95695 GIR_AddImm8, /*InsnID*/22, /*Imm*/0,
95696 GIR_ConstrainSelectedInstOperands, /*InsnID*/22,
95697 GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
95698 GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95699 GIR_Copy, /*NewInsnID*/21, /*OldInsnID*/0, /*OpIdx*/1, // Rn
95700 GIR_AddImm8, /*InsnID*/21, /*Imm*/16,
95701 GIR_ConstrainSelectedInstOperands, /*InsnID*/21,
95702 GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
95703 GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95704 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/20,
95705 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/21,
95706 GIR_ConstrainSelectedInstOperands, /*InsnID*/20,
95707 GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
95708 GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95709 GIR_CopySubReg, /*NewInsnID*/19, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
95710 GIR_ConstrainOperandRC, /*InsnID*/19, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
95711 GIR_ConstrainOperandRC, /*InsnID*/19, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95712 GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
95713 GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95714 GIR_AddSimpleTempRegister, /*InsnID*/18, /*TempRegID*/18,
95715 GIR_ConstrainSelectedInstOperands, /*InsnID*/18,
95716 GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
95717 GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95718 GIR_CopySubReg, /*NewInsnID*/17, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
95719 GIR_ConstrainOperandRC, /*InsnID*/17, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
95720 GIR_ConstrainOperandRC, /*InsnID*/17, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95721 GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
95722 GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95723 GIR_AddSimpleTempRegister, /*InsnID*/16, /*TempRegID*/16,
95724 GIR_ConstrainSelectedInstOperands, /*InsnID*/16,
95725 GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
95726 GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95727 GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/15,
95728 GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/17,
95729 GIR_ConstrainSelectedInstOperands, /*InsnID*/15,
95730 GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
95731 GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95732 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14,
95733 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/19,
95734 GIR_ConstrainSelectedInstOperands, /*InsnID*/14,
95735 GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
95736 GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95737 GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/13,
95738 GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/22,
95739 GIR_ConstrainSelectedInstOperands, /*InsnID*/13,
95740 GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
95741 GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95742 GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
95743 GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
95744 GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95745 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
95746 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95747 GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11,
95748 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
95749 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
95750 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95751 GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
95752 GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
95753 GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95754 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
95755 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95756 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
95757 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
95758 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
95759 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95760 GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
95761 GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/10,
95762 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
95763 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
95764 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95765 GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
95766 GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
95767 GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95768 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
95769 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95770 GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
95771 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
95772 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
95773 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95774 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
95775 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
95776 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95777 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
95778 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95779 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
95780 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
95781 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
95782 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95783 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
95784 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/5,
95785 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
95786 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
95787 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95788 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
95789 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/7,
95790 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
95791 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
95792 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95793 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
95794 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/12,
95795 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/23,
95796 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
95797 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
95798 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
95799 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
95800 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/29,
95801 GIR_RootConstrainSelectedInstOperands,
95802 // GIR_Coverage, 6732,
95803 GIR_EraseRootFromParent_Done,
95804 // Label 5461: @255037
95805 GIM_Reject,
95806 // Label 5455: @255038
95807 GIM_Reject,
95808 // Label 5399: @255039
95809 GIM_Try, /*On fail goto*//*Label 5462*/ GIMT_Encode4(255064), // Rule ID 7863 //
95810 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
95811 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
95812 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
95813 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
95814 // (fmul:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (FMUL_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
95815 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZ_D),
95816 GIR_RootConstrainSelectedInstOperands,
95817 // GIR_Coverage, 7863,
95818 GIR_Done,
95819 // Label 5462: @255064
95820 GIM_Reject,
95821 // Label 5400: @255065
95822 GIM_Try, /*On fail goto*//*Label 5463*/ GIMT_Encode4(255090), // Rule ID 7861 //
95823 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
95824 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
95825 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
95826 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
95827 // (fmul:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (FMUL_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
95828 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZ_S),
95829 GIR_RootConstrainSelectedInstOperands,
95830 // GIR_Coverage, 7861,
95831 GIR_Done,
95832 // Label 5463: @255090
95833 GIM_Reject,
95834 // Label 5401: @255091
95835 GIM_Try, /*On fail goto*//*Label 5464*/ GIMT_Encode4(255137),
95836 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
95837 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
95838 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
95839 GIM_Try, /*On fail goto*//*Label 5465*/ GIMT_Encode4(255121), // Rule ID 7859 //
95840 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
95841 // (fmul:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (FMUL_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
95842 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZ_H),
95843 GIR_RootConstrainSelectedInstOperands,
95844 // GIR_Coverage, 7859,
95845 GIR_Done,
95846 // Label 5465: @255121
95847 GIM_Try, /*On fail goto*//*Label 5466*/ GIMT_Encode4(255136), // Rule ID 11778 //
95848 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasB16B16_HasSVE2orSME2),
95849 // (fmul:{ *:[nxv8bf16] } nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2) => (BFMUL_ZZZ:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2)
95850 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BFMUL_ZZZ),
95851 GIR_RootConstrainSelectedInstOperands,
95852 // GIR_Coverage, 11778,
95853 GIR_Done,
95854 // Label 5466: @255136
95855 GIM_Reject,
95856 // Label 5464: @255137
95857 GIM_Reject,
95858 // Label 5402: @255138
95859 GIM_Reject,
95860 // Label 56: @255139
95861 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 5475*/ GIMT_Encode4(267388),
95862 /*GILLT_s16*//*Label 5467*/ GIMT_Encode4(255190),
95863 /*GILLT_s32*//*Label 5468*/ GIMT_Encode4(256853),
95864 /*GILLT_s64*//*Label 5469*/ GIMT_Encode4(258660), GIMT_Encode4(0),
95865 /*GILLT_v2s32*//*Label 5470*/ GIMT_Encode4(260467),
95866 /*GILLT_v2s64*//*Label 5471*/ GIMT_Encode4(261988),
95867 /*GILLT_v4s16*//*Label 5472*/ GIMT_Encode4(263509),
95868 /*GILLT_v4s32*//*Label 5473*/ GIMT_Encode4(264688), GIMT_Encode4(0),
95869 /*GILLT_v8s16*//*Label 5474*/ GIMT_Encode4(266209),
95870 // Label 5467: @255190
95871 GIM_Try, /*On fail goto*//*Label 5476*/ GIMT_Encode4(256852),
95872 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
95873 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
95874 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
95875 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
95876 GIM_Try, /*On fail goto*//*Label 5477*/ GIMT_Encode4(255308), // Rule ID 4503 //
95877 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
95878 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
95879 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
95880 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
95881 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
95882 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95883 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
95884 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
95885 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
95886 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
95887 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
95888 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
95889 GIM_CheckIsSafeToFold, /*NumInsns*/2,
95890 // (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
95891 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
95892 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
95893 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95894 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
95895 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
95896 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95897 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
95898 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
95899 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
95900 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
95901 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
95902 GIR_RootConstrainSelectedInstOperands,
95903 // GIR_Coverage, 4503,
95904 GIR_EraseRootFromParent_Done,
95905 // Label 5477: @255308
95906 GIM_Try, /*On fail goto*//*Label 5478*/ GIMT_Encode4(255408), // Rule ID 4527 //
95907 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
95908 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
95909 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
95910 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
95911 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
95912 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95913 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
95914 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
95915 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
95916 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
95917 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
95918 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
95919 GIM_CheckIsSafeToFold, /*NumInsns*/2,
95920 // (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra)) => (FNMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
95921 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
95922 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
95923 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95924 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
95925 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
95926 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95927 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
95928 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
95929 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
95930 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
95931 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
95932 GIR_RootConstrainSelectedInstOperands,
95933 // GIR_Coverage, 4527,
95934 GIR_EraseRootFromParent_Done,
95935 // Label 5478: @255408
95936 GIM_Try, /*On fail goto*//*Label 5479*/ GIMT_Encode4(255505), // Rule ID 13089 //
95937 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
95938 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
95939 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
95940 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
95941 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
95942 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
95943 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
95944 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
95945 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95946 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
95947 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
95948 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
95949 GIM_CheckIsSafeToFold, /*NumInsns*/2,
95950 // (fma:{ *:[f16] } (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
95951 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
95952 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
95953 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95954 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rm
95955 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
95956 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95957 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
95958 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
95959 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
95960 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
95961 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
95962 GIR_RootConstrainSelectedInstOperands,
95963 // GIR_Coverage, 13089,
95964 GIR_EraseRootFromParent_Done,
95965 // Label 5479: @255505
95966 GIM_Try, /*On fail goto*//*Label 5480*/ GIMT_Encode4(255605), // Rule ID 13091 //
95967 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
95968 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
95969 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
95970 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
95971 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
95972 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
95973 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
95974 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
95975 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
95976 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
95977 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
95978 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
95979 GIM_CheckIsSafeToFold, /*NumInsns*/2,
95980 // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
95981 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
95982 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
95983 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
95984 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
95985 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
95986 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
95987 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
95988 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
95989 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
95990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
95991 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
95992 GIR_RootConstrainSelectedInstOperands,
95993 // GIR_Coverage, 13091,
95994 GIR_EraseRootFromParent_Done,
95995 // Label 5480: @255605
95996 GIM_Try, /*On fail goto*//*Label 5481*/ GIMT_Encode4(255705), // Rule ID 4525 //
95997 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
95998 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
95999 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
96000 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96001 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
96002 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
96003 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96004 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
96005 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
96006 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
96007 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
96008 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96009 GIM_CheckIsSafeToFold, /*NumInsns*/2,
96010 // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra)) => (FNMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
96011 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
96012 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
96013 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
96014 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rm
96015 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
96016 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
96017 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
96018 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96019 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
96020 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
96021 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
96022 GIR_RootConstrainSelectedInstOperands,
96023 // GIR_Coverage, 4525,
96024 GIR_EraseRootFromParent_Done,
96025 // Label 5481: @255705
96026 GIM_Try, /*On fail goto*//*Label 5482*/ GIMT_Encode4(255802), // Rule ID 4501 //
96027 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
96028 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96029 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
96030 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96031 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
96032 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
96033 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96034 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
96035 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
96036 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96037 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
96038 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96039 GIM_CheckIsSafeToFold, /*NumInsns*/2,
96040 // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
96041 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
96042 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
96043 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
96044 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rm
96045 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
96046 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
96047 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
96048 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96049 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
96050 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
96051 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
96052 GIR_RootConstrainSelectedInstOperands,
96053 // GIR_Coverage, 4501,
96054 GIR_EraseRootFromParent_Done,
96055 // Label 5482: @255802
96056 GIM_Try, /*On fail goto*//*Label 5483*/ GIMT_Encode4(255886), // Rule ID 5717 //
96057 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
96058 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96059 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96060 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
96061 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
96062 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
96063 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
96064 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
96065 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
96066 // MIs[2] Operand 1
96067 // No operand predicates
96068 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
96069 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
96070 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s16,
96071 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96072 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96073 GIM_CheckIsSafeToFold, /*NumInsns*/3,
96074 // (fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
96075 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
96076 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
96077 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
96078 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
96079 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
96080 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
96081 GIR_RootConstrainSelectedInstOperands,
96082 // GIR_Coverage, 5717,
96083 GIR_EraseRootFromParent_Done,
96084 // Label 5483: @255886
96085 GIM_Try, /*On fail goto*//*Label 5484*/ GIMT_Encode4(255967), // Rule ID 5743 //
96086 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
96087 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96088 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96089 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
96090 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
96091 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96092 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
96093 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
96094 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
96095 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
96096 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
96097 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
96098 // MIs[3] Operand 1
96099 // No operand predicates
96100 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96101 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96102 GIM_CheckIsSafeToFold, /*NumInsns*/3,
96103 // (fma:{ *:[f16] } (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
96104 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
96105 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
96106 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
96107 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
96108 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
96109 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
96110 GIR_RootConstrainSelectedInstOperands,
96111 // GIR_Coverage, 5743,
96112 GIR_EraseRootFromParent_Done,
96113 // Label 5484: @255967
96114 GIM_Try, /*On fail goto*//*Label 5485*/ GIMT_Encode4(256051), // Rule ID 5769 //
96115 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
96116 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96117 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96118 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
96119 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96120 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
96121 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96122 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
96123 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
96124 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
96125 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
96126 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
96127 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
96128 // MIs[3] Operand 1
96129 // No operand predicates
96130 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96131 GIM_CheckIsSafeToFold, /*NumInsns*/3,
96132 // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
96133 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
96134 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
96135 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
96136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
96137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
96138 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
96139 GIR_RootConstrainSelectedInstOperands,
96140 // GIR_Coverage, 5769,
96141 GIR_EraseRootFromParent_Done,
96142 // Label 5485: @256051
96143 GIM_Try, /*On fail goto*//*Label 5486*/ GIMT_Encode4(256132), // Rule ID 5691 //
96144 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
96145 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96146 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
96147 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96148 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
96149 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
96150 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96151 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
96152 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
96153 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
96154 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
96155 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
96156 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
96157 // MIs[3] Operand 1
96158 // No operand predicates
96159 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96160 GIM_CheckIsSafeToFold, /*NumInsns*/3,
96161 // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
96162 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
96163 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
96164 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
96165 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
96166 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
96167 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
96168 GIR_RootConstrainSelectedInstOperands,
96169 // GIR_Coverage, 5691,
96170 GIR_EraseRootFromParent_Done,
96171 // Label 5486: @256132
96172 GIM_Try, /*On fail goto*//*Label 5487*/ GIMT_Encode4(256217), // Rule ID 2386 //
96173 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
96174 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96175 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96176 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
96177 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
96178 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96179 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
96180 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96181 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96182 GIM_CheckIsSafeToFold, /*NumInsns*/1,
96183 // (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) => (FMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
96184 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
96185 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
96186 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
96187 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
96188 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
96189 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
96190 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
96191 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96192 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
96193 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
96194 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
96195 GIR_RootConstrainSelectedInstOperands,
96196 // GIR_Coverage, 2386,
96197 GIR_EraseRootFromParent_Done,
96198 // Label 5487: @256217
96199 GIM_Try, /*On fail goto*//*Label 5488*/ GIMT_Encode4(256302), // Rule ID 2384 //
96200 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
96201 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96202 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
96203 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96204 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
96205 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
96206 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96207 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
96208 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96209 GIM_CheckIsSafeToFold, /*NumInsns*/1,
96210 // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra) => (FMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
96211 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
96212 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
96213 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
96214 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rm
96215 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
96216 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
96217 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
96218 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96219 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
96220 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
96221 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
96222 GIR_RootConstrainSelectedInstOperands,
96223 // GIR_Coverage, 2384,
96224 GIR_EraseRootFromParent_Done,
96225 // Label 5488: @256302
96226 GIM_Try, /*On fail goto*//*Label 5489*/ GIMT_Encode4(256371), // Rule ID 2452 //
96227 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
96228 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96229 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96230 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
96231 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
96232 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
96233 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
96234 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
96235 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
96236 // MIs[2] Operand 1
96237 // No operand predicates
96238 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96239 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96240 GIM_CheckIsSafeToFold, /*NumInsns*/2,
96241 // (fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rd) => (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
96242 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
96243 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
96244 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
96245 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
96246 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
96247 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
96248 GIR_RootConstrainSelectedInstOperands,
96249 // GIR_Coverage, 2452,
96250 GIR_EraseRootFromParent_Done,
96251 // Label 5489: @256371
96252 GIM_Try, /*On fail goto*//*Label 5490*/ GIMT_Encode4(256440), // Rule ID 5665 //
96253 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
96254 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96255 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
96256 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96257 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
96258 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
96259 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
96260 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
96261 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
96262 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
96263 // MIs[2] Operand 1
96264 // No operand predicates
96265 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96266 GIM_CheckIsSafeToFold, /*NumInsns*/2,
96267 // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd) => (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
96268 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
96269 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
96270 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
96271 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
96272 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
96273 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
96274 GIR_RootConstrainSelectedInstOperands,
96275 // GIR_Coverage, 5665,
96276 GIR_EraseRootFromParent_Done,
96277 // Label 5490: @256440
96278 GIM_Try, /*On fail goto*//*Label 5491*/ GIMT_Encode4(256505), // Rule ID 4539 //
96279 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
96280 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96281 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96282 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
96283 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96284 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96285 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
96286 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
96287 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
96288 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96289 GIM_CheckIsSafeToFold, /*NumInsns*/2,
96290 // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra)) => (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
96291 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
96292 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96293 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
96294 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
96295 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
96296 GIR_RootConstrainSelectedInstOperands,
96297 // GIR_Coverage, 4539,
96298 GIR_EraseRootFromParent_Done,
96299 // Label 5491: @256505
96300 GIM_Try, /*On fail goto*//*Label 5492*/ GIMT_Encode4(256570), // Rule ID 13103 //
96301 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
96302 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96303 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
96304 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96305 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
96306 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96307 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
96308 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
96309 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
96310 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96311 GIM_CheckIsSafeToFold, /*NumInsns*/2,
96312 // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra)) => (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
96313 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
96314 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96315 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
96316 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
96317 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
96318 GIR_RootConstrainSelectedInstOperands,
96319 // GIR_Coverage, 13103,
96320 GIR_EraseRootFromParent_Done,
96321 // Label 5492: @256570
96322 GIM_Try, /*On fail goto*//*Label 5493*/ GIMT_Encode4(256620), // Rule ID 4536 //
96323 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
96324 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96325 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96326 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
96327 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96328 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96329 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96330 GIM_CheckIsSafeToFold, /*NumInsns*/1,
96331 // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
96332 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
96333 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96334 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
96335 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
96336 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
96337 GIR_RootConstrainSelectedInstOperands,
96338 // GIR_Coverage, 4536,
96339 GIR_EraseRootFromParent_Done,
96340 // Label 5493: @256620
96341 GIM_Try, /*On fail goto*//*Label 5494*/ GIMT_Encode4(256670), // Rule ID 12547 //
96342 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
96343 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96344 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96345 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
96346 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96347 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96348 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96349 GIM_CheckIsSafeToFold, /*NumInsns*/1,
96350 // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
96351 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
96352 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96353 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
96354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
96355 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
96356 GIR_RootConstrainSelectedInstOperands,
96357 // GIR_Coverage, 12547,
96358 GIR_EraseRootFromParent_Done,
96359 // Label 5494: @256670
96360 GIM_Try, /*On fail goto*//*Label 5495*/ GIMT_Encode4(256720), // Rule ID 638 //
96361 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
96362 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96363 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
96364 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96365 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
96366 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96367 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96368 GIM_CheckIsSafeToFold, /*NumInsns*/1,
96369 // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
96370 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
96371 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96372 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
96373 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
96374 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
96375 GIR_RootConstrainSelectedInstOperands,
96376 // GIR_Coverage, 638,
96377 GIR_EraseRootFromParent_Done,
96378 // Label 5495: @256720
96379 GIM_Try, /*On fail goto*//*Label 5496*/ GIMT_Encode4(256770), // Rule ID 13100 //
96380 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
96381 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96382 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
96383 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96384 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
96385 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96386 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96387 GIM_CheckIsSafeToFold, /*NumInsns*/1,
96388 // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
96389 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
96390 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96391 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
96392 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
96393 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
96394 GIR_RootConstrainSelectedInstOperands,
96395 // GIR_Coverage, 13100,
96396 GIR_EraseRootFromParent_Done,
96397 // Label 5496: @256770
96398 GIM_Try, /*On fail goto*//*Label 5497*/ GIMT_Encode4(256820), // Rule ID 650 //
96399 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
96400 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96401 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96402 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
96403 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96404 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
96405 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96406 GIM_CheckIsSafeToFold, /*NumInsns*/1,
96407 // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra)) => (FNMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
96408 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
96409 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96410 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
96411 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
96412 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra
96413 GIR_RootConstrainSelectedInstOperands,
96414 // GIR_Coverage, 650,
96415 GIR_EraseRootFromParent_Done,
96416 // Label 5497: @256820
96417 GIM_Try, /*On fail goto*//*Label 5498*/ GIMT_Encode4(256851), // Rule ID 632 //
96418 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
96419 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96420 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96421 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
96422 // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) => (FMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
96423 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
96424 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
96425 GIR_RootConstrainSelectedInstOperands,
96426 // GIR_Coverage, 632,
96427 GIR_Done,
96428 // Label 5498: @256851
96429 GIM_Reject,
96430 // Label 5476: @256852
96431 GIM_Reject,
96432 // Label 5468: @256853
96433 GIM_Try, /*On fail goto*//*Label 5499*/ GIMT_Encode4(258659),
96434 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
96435 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
96436 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
96437 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96438 GIM_Try, /*On fail goto*//*Label 5500*/ GIMT_Encode4(256971), // Rule ID 4507 //
96439 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
96440 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96441 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96442 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
96443 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
96444 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96445 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
96446 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
96447 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
96448 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
96449 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96450 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96451 GIM_CheckIsSafeToFold, /*NumInsns*/2,
96452 // (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
96453 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
96454 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
96455 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
96456 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rn
96457 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
96458 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
96459 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
96460 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96461 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
96462 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
96463 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
96464 GIR_RootConstrainSelectedInstOperands,
96465 // GIR_Coverage, 4507,
96466 GIR_EraseRootFromParent_Done,
96467 // Label 5500: @256971
96468 GIM_Try, /*On fail goto*//*Label 5501*/ GIMT_Encode4(257071), // Rule ID 4531 //
96469 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
96470 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96471 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96472 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
96473 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
96474 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96475 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
96476 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96477 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
96478 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
96479 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
96480 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96481 GIM_CheckIsSafeToFold, /*NumInsns*/2,
96482 // (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
96483 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
96484 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
96485 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
96486 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rn
96487 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
96488 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
96489 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
96490 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96491 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
96492 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
96493 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
96494 GIR_RootConstrainSelectedInstOperands,
96495 // GIR_Coverage, 4531,
96496 GIR_EraseRootFromParent_Done,
96497 // Label 5501: @257071
96498 GIM_Try, /*On fail goto*//*Label 5502*/ GIMT_Encode4(257168), // Rule ID 13093 //
96499 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
96500 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96501 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96502 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
96503 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
96504 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96505 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
96506 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
96507 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96508 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
96509 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96510 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96511 GIM_CheckIsSafeToFold, /*NumInsns*/2,
96512 // (fma:{ *:[f32] } (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
96513 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
96514 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
96515 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
96516 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rm
96517 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
96518 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
96519 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
96520 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96521 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
96522 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
96523 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
96524 GIR_RootConstrainSelectedInstOperands,
96525 // GIR_Coverage, 13093,
96526 GIR_EraseRootFromParent_Done,
96527 // Label 5502: @257168
96528 GIM_Try, /*On fail goto*//*Label 5503*/ GIMT_Encode4(257268), // Rule ID 13095 //
96529 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
96530 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96531 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96532 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
96533 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96534 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
96535 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96536 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
96537 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
96538 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96539 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
96540 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96541 GIM_CheckIsSafeToFold, /*NumInsns*/2,
96542 // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
96543 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
96544 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
96545 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
96546 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rn
96547 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
96548 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
96549 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
96550 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96551 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
96552 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
96553 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
96554 GIR_RootConstrainSelectedInstOperands,
96555 // GIR_Coverage, 13095,
96556 GIR_EraseRootFromParent_Done,
96557 // Label 5503: @257268
96558 GIM_Try, /*On fail goto*//*Label 5504*/ GIMT_Encode4(257368), // Rule ID 4529 //
96559 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
96560 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96561 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
96562 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96563 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
96564 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
96565 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96566 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
96567 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
96568 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
96569 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
96570 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96571 GIM_CheckIsSafeToFold, /*NumInsns*/2,
96572 // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
96573 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
96574 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
96575 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
96576 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rm
96577 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
96578 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
96579 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
96580 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96581 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
96582 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
96583 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
96584 GIR_RootConstrainSelectedInstOperands,
96585 // GIR_Coverage, 4529,
96586 GIR_EraseRootFromParent_Done,
96587 // Label 5504: @257368
96588 GIM_Try, /*On fail goto*//*Label 5505*/ GIMT_Encode4(257465), // Rule ID 4505 //
96589 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
96590 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96591 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
96592 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96593 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
96594 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
96595 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96596 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
96597 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
96598 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96599 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
96600 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96601 GIM_CheckIsSafeToFold, /*NumInsns*/2,
96602 // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
96603 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
96604 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
96605 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
96606 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rm
96607 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
96608 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
96609 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
96610 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96611 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
96612 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
96613 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
96614 GIR_RootConstrainSelectedInstOperands,
96615 // GIR_Coverage, 4505,
96616 GIR_EraseRootFromParent_Done,
96617 // Label 5505: @257465
96618 GIM_Try, /*On fail goto*//*Label 5506*/ GIMT_Encode4(257543), // Rule ID 5803 //
96619 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96620 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96621 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
96622 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
96623 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
96624 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
96625 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
96626 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96627 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
96628 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
96629 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
96630 // MIs[3] Operand 1
96631 // No operand predicates
96632 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96633 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96634 GIM_CheckIsSafeToFold, /*NumInsns*/3,
96635 // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
96636 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
96637 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
96638 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
96639 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
96640 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
96641 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
96642 GIR_RootConstrainSelectedInstOperands,
96643 // GIR_Coverage, 5803,
96644 GIR_EraseRootFromParent_Done,
96645 // Label 5506: @257543
96646 GIM_Try, /*On fail goto*//*Label 5507*/ GIMT_Encode4(257627), // Rule ID 5731 //
96647 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
96648 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96649 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96650 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
96651 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
96652 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96653 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
96654 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
96655 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
96656 // MIs[2] Operand 1
96657 // No operand predicates
96658 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
96659 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
96660 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
96661 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96662 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96663 GIM_CheckIsSafeToFold, /*NumInsns*/3,
96664 // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
96665 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
96666 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
96667 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
96668 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
96669 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
96670 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
96671 GIR_RootConstrainSelectedInstOperands,
96672 // GIR_Coverage, 5731,
96673 GIR_EraseRootFromParent_Done,
96674 // Label 5507: @257627
96675 GIM_Try, /*On fail goto*//*Label 5508*/ GIMT_Encode4(257708), // Rule ID 5757 //
96676 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
96677 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96678 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96679 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
96680 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
96681 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96682 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
96683 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
96684 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96685 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
96686 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
96687 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
96688 // MIs[3] Operand 1
96689 // No operand predicates
96690 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96691 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96692 GIM_CheckIsSafeToFold, /*NumInsns*/3,
96693 // (fma:{ *:[f32] } (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
96694 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
96695 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
96696 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
96697 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
96698 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
96699 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
96700 GIR_RootConstrainSelectedInstOperands,
96701 // GIR_Coverage, 5757,
96702 GIR_EraseRootFromParent_Done,
96703 // Label 5508: @257708
96704 GIM_Try, /*On fail goto*//*Label 5509*/ GIMT_Encode4(257792), // Rule ID 5783 //
96705 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
96706 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96707 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96708 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
96709 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96710 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
96711 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96712 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
96713 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
96714 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96715 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
96716 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
96717 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
96718 // MIs[3] Operand 1
96719 // No operand predicates
96720 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96721 GIM_CheckIsSafeToFold, /*NumInsns*/3,
96722 // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
96723 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
96724 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
96725 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
96726 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
96727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
96728 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
96729 GIR_RootConstrainSelectedInstOperands,
96730 // GIR_Coverage, 5783,
96731 GIR_EraseRootFromParent_Done,
96732 // Label 5509: @257792
96733 GIM_Try, /*On fail goto*//*Label 5510*/ GIMT_Encode4(257870), // Rule ID 5825 //
96734 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96735 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
96736 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96737 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
96738 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
96739 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
96740 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
96741 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
96742 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96743 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
96744 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
96745 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
96746 // MIs[3] Operand 1
96747 // No operand predicates
96748 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96749 GIM_CheckIsSafeToFold, /*NumInsns*/3,
96750 // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
96751 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
96752 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
96753 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
96754 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
96755 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
96756 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
96757 GIR_RootConstrainSelectedInstOperands,
96758 // GIR_Coverage, 5825,
96759 GIR_EraseRootFromParent_Done,
96760 // Label 5510: @257870
96761 GIM_Try, /*On fail goto*//*Label 5511*/ GIMT_Encode4(257951), // Rule ID 5705 //
96762 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
96763 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96764 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
96765 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96766 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
96767 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
96768 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96769 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
96770 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
96771 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96772 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
96773 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
96774 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
96775 // MIs[3] Operand 1
96776 // No operand predicates
96777 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96778 GIM_CheckIsSafeToFold, /*NumInsns*/3,
96779 // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
96780 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
96781 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
96782 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
96783 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
96784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
96785 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
96786 GIR_RootConstrainSelectedInstOperands,
96787 // GIR_Coverage, 5705,
96788 GIR_EraseRootFromParent_Done,
96789 // Label 5511: @257951
96790 GIM_Try, /*On fail goto*//*Label 5512*/ GIMT_Encode4(258036), // Rule ID 2390 //
96791 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
96792 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96793 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96794 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
96795 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
96796 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96797 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
96798 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96799 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96800 GIM_CheckIsSafeToFold, /*NumInsns*/1,
96801 // (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) => (FMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
96802 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
96803 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
96804 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
96805 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rn
96806 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
96807 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
96808 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
96809 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96810 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
96811 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
96812 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
96813 GIR_RootConstrainSelectedInstOperands,
96814 // GIR_Coverage, 2390,
96815 GIR_EraseRootFromParent_Done,
96816 // Label 5512: @258036
96817 GIM_Try, /*On fail goto*//*Label 5513*/ GIMT_Encode4(258121), // Rule ID 2388 //
96818 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
96819 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96820 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
96821 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96822 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
96823 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
96824 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96825 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
96826 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96827 GIM_CheckIsSafeToFold, /*NumInsns*/1,
96828 // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra) => (FMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
96829 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
96830 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
96831 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
96832 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rm
96833 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
96834 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
96835 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
96836 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96837 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
96838 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
96839 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
96840 GIR_RootConstrainSelectedInstOperands,
96841 // GIR_Coverage, 2388,
96842 GIR_EraseRootFromParent_Done,
96843 // Label 5513: @258121
96844 GIM_Try, /*On fail goto*//*Label 5514*/ GIMT_Encode4(258190), // Rule ID 2466 //
96845 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
96846 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96847 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96848 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
96849 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
96850 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96851 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
96852 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
96853 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
96854 // MIs[2] Operand 1
96855 // No operand predicates
96856 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96857 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96858 GIM_CheckIsSafeToFold, /*NumInsns*/2,
96859 // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
96860 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
96861 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
96862 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
96863 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
96864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
96865 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
96866 GIR_RootConstrainSelectedInstOperands,
96867 // GIR_Coverage, 2466,
96868 GIR_EraseRootFromParent_Done,
96869 // Label 5514: @258190
96870 GIM_Try, /*On fail goto*//*Label 5515*/ GIMT_Encode4(258259), // Rule ID 5679 //
96871 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
96872 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96873 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
96874 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
96875 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
96876 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
96877 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
96878 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
96879 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
96880 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
96881 // MIs[2] Operand 1
96882 // No operand predicates
96883 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96884 GIM_CheckIsSafeToFold, /*NumInsns*/2,
96885 // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
96886 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
96887 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
96888 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
96889 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
96890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
96891 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
96892 GIR_RootConstrainSelectedInstOperands,
96893 // GIR_Coverage, 5679,
96894 GIR_EraseRootFromParent_Done,
96895 // Label 5515: @258259
96896 GIM_Try, /*On fail goto*//*Label 5516*/ GIMT_Encode4(258321), // Rule ID 4540 //
96897 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96898 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96899 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
96900 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96901 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96902 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
96903 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
96904 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
96905 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96906 GIM_CheckIsSafeToFold, /*NumInsns*/2,
96907 // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
96908 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
96909 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96910 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
96911 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
96912 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
96913 GIR_RootConstrainSelectedInstOperands,
96914 // GIR_Coverage, 4540,
96915 GIR_EraseRootFromParent_Done,
96916 // Label 5516: @258321
96917 GIM_Try, /*On fail goto*//*Label 5517*/ GIMT_Encode4(258383), // Rule ID 13104 //
96918 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96919 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
96920 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96921 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
96922 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96923 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
96924 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
96925 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
96926 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96927 GIM_CheckIsSafeToFold, /*NumInsns*/2,
96928 // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
96929 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
96930 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96931 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
96932 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
96933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
96934 GIR_RootConstrainSelectedInstOperands,
96935 // GIR_Coverage, 13104,
96936 GIR_EraseRootFromParent_Done,
96937 // Label 5517: @258383
96938 GIM_Try, /*On fail goto*//*Label 5518*/ GIMT_Encode4(258430), // Rule ID 4537 //
96939 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96940 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96941 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
96942 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96943 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96944 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96945 GIM_CheckIsSafeToFold, /*NumInsns*/1,
96946 // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
96947 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
96948 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
96950 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
96951 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
96952 GIR_RootConstrainSelectedInstOperands,
96953 // GIR_Coverage, 4537,
96954 GIR_EraseRootFromParent_Done,
96955 // Label 5518: @258430
96956 GIM_Try, /*On fail goto*//*Label 5519*/ GIMT_Encode4(258480), // Rule ID 12549 //
96957 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
96958 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
96959 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96960 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
96961 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96962 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96963 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96964 GIM_CheckIsSafeToFold, /*NumInsns*/1,
96965 // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
96966 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
96967 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96968 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
96969 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
96970 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
96971 GIR_RootConstrainSelectedInstOperands,
96972 // GIR_Coverage, 12549,
96973 GIR_EraseRootFromParent_Done,
96974 // Label 5519: @258480
96975 GIM_Try, /*On fail goto*//*Label 5520*/ GIMT_Encode4(258530), // Rule ID 640 //
96976 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
96977 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96978 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
96979 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96980 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
96981 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96982 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96983 GIM_CheckIsSafeToFold, /*NumInsns*/1,
96984 // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
96985 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
96986 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
96987 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
96988 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
96989 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
96990 GIR_RootConstrainSelectedInstOperands,
96991 // GIR_Coverage, 640,
96992 GIR_EraseRootFromParent_Done,
96993 // Label 5520: @258530
96994 GIM_Try, /*On fail goto*//*Label 5521*/ GIMT_Encode4(258577), // Rule ID 13101 //
96995 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
96996 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
96997 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
96998 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
96999 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
97000 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
97001 GIM_CheckIsSafeToFold, /*NumInsns*/1,
97002 // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
97003 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
97004 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
97005 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
97006 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
97007 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
97008 GIR_RootConstrainSelectedInstOperands,
97009 // GIR_Coverage, 13101,
97010 GIR_EraseRootFromParent_Done,
97011 // Label 5521: @258577
97012 GIM_Try, /*On fail goto*//*Label 5522*/ GIMT_Encode4(258627), // Rule ID 652 //
97013 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
97014 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
97015 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
97016 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
97017 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
97018 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
97019 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
97020 GIM_CheckIsSafeToFold, /*NumInsns*/1,
97021 // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
97022 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
97023 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
97024 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
97025 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
97026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra
97027 GIR_RootConstrainSelectedInstOperands,
97028 // GIR_Coverage, 652,
97029 GIR_EraseRootFromParent_Done,
97030 // Label 5522: @258627
97031 GIM_Try, /*On fail goto*//*Label 5523*/ GIMT_Encode4(258658), // Rule ID 634 //
97032 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
97033 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
97034 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
97035 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
97036 // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) => (FMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
97037 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
97038 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
97039 GIR_RootConstrainSelectedInstOperands,
97040 // GIR_Coverage, 634,
97041 GIR_Done,
97042 // Label 5523: @258658
97043 GIM_Reject,
97044 // Label 5499: @258659
97045 GIM_Reject,
97046 // Label 5469: @258660
97047 GIM_Try, /*On fail goto*//*Label 5524*/ GIMT_Encode4(260466),
97048 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
97049 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
97050 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
97051 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97052 GIM_Try, /*On fail goto*//*Label 5525*/ GIMT_Encode4(258778), // Rule ID 4511 //
97053 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
97054 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97055 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
97056 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
97057 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
97058 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97059 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
97060 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
97061 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
97062 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
97063 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97064 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97065 GIM_CheckIsSafeToFold, /*NumInsns*/2,
97066 // (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
97067 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
97068 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
97069 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
97070 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
97071 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
97072 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
97073 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
97074 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
97075 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
97076 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
97077 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
97078 GIR_RootConstrainSelectedInstOperands,
97079 // GIR_Coverage, 4511,
97080 GIR_EraseRootFromParent_Done,
97081 // Label 5525: @258778
97082 GIM_Try, /*On fail goto*//*Label 5526*/ GIMT_Encode4(258878), // Rule ID 4535 //
97083 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
97084 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97085 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
97086 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
97087 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
97088 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97089 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
97090 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97091 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
97092 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
97093 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
97094 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97095 GIM_CheckIsSafeToFold, /*NumInsns*/2,
97096 // (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
97097 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
97098 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
97099 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
97100 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
97101 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
97102 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
97103 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
97104 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
97105 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
97106 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
97107 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
97108 GIR_RootConstrainSelectedInstOperands,
97109 // GIR_Coverage, 4535,
97110 GIR_EraseRootFromParent_Done,
97111 // Label 5526: @258878
97112 GIM_Try, /*On fail goto*//*Label 5527*/ GIMT_Encode4(258975), // Rule ID 13097 //
97113 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
97114 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97115 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
97116 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
97117 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
97118 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
97119 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
97120 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
97121 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97122 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
97123 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97124 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97125 GIM_CheckIsSafeToFold, /*NumInsns*/2,
97126 // (fma:{ *:[f64] } (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
97127 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
97128 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
97129 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
97130 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rm
97131 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
97132 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
97133 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
97134 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
97135 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
97136 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
97137 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
97138 GIR_RootConstrainSelectedInstOperands,
97139 // GIR_Coverage, 13097,
97140 GIR_EraseRootFromParent_Done,
97141 // Label 5527: @258975
97142 GIM_Try, /*On fail goto*//*Label 5528*/ GIMT_Encode4(259075), // Rule ID 13099 //
97143 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
97144 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97145 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
97146 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
97147 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97148 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
97149 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
97150 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
97151 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
97152 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97153 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
97154 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97155 GIM_CheckIsSafeToFold, /*NumInsns*/2,
97156 // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
97157 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
97158 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
97159 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
97160 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
97161 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
97162 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
97163 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
97164 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
97165 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
97166 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
97167 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
97168 GIR_RootConstrainSelectedInstOperands,
97169 // GIR_Coverage, 13099,
97170 GIR_EraseRootFromParent_Done,
97171 // Label 5528: @259075
97172 GIM_Try, /*On fail goto*//*Label 5529*/ GIMT_Encode4(259175), // Rule ID 4533 //
97173 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
97174 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97175 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
97176 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
97177 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
97178 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
97179 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97180 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
97181 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
97182 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
97183 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
97184 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97185 GIM_CheckIsSafeToFold, /*NumInsns*/2,
97186 // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
97187 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
97188 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
97189 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
97190 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rm
97191 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
97192 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
97193 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
97194 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
97195 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
97196 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
97197 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
97198 GIR_RootConstrainSelectedInstOperands,
97199 // GIR_Coverage, 4533,
97200 GIR_EraseRootFromParent_Done,
97201 // Label 5529: @259175
97202 GIM_Try, /*On fail goto*//*Label 5530*/ GIMT_Encode4(259272), // Rule ID 4509 //
97203 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
97204 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97205 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
97206 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
97207 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
97208 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
97209 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
97210 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
97211 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
97212 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97213 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
97214 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97215 GIM_CheckIsSafeToFold, /*NumInsns*/2,
97216 // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
97217 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
97218 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
97219 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
97220 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rm
97221 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
97222 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
97223 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
97224 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
97225 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
97226 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
97227 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
97228 GIR_RootConstrainSelectedInstOperands,
97229 // GIR_Coverage, 4509,
97230 GIR_EraseRootFromParent_Done,
97231 // Label 5530: @259272
97232 GIM_Try, /*On fail goto*//*Label 5531*/ GIMT_Encode4(259350), // Rule ID 5807 //
97233 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97234 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
97235 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
97236 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
97237 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
97238 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
97239 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
97240 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97241 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
97242 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
97243 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
97244 // MIs[3] Operand 1
97245 // No operand predicates
97246 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97247 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97248 GIM_CheckIsSafeToFold, /*NumInsns*/3,
97249 // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
97250 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
97251 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
97252 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
97253 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
97254 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
97255 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
97256 GIR_RootConstrainSelectedInstOperands,
97257 // GIR_Coverage, 5807,
97258 GIR_EraseRootFromParent_Done,
97259 // Label 5531: @259350
97260 GIM_Try, /*On fail goto*//*Label 5532*/ GIMT_Encode4(259434), // Rule ID 5733 //
97261 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
97262 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97263 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
97264 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
97265 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
97266 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97267 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
97268 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
97269 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
97270 // MIs[2] Operand 1
97271 // No operand predicates
97272 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
97273 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
97274 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
97275 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97276 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97277 GIM_CheckIsSafeToFold, /*NumInsns*/3,
97278 // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
97279 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
97280 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
97281 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
97282 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
97283 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
97284 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
97285 GIR_RootConstrainSelectedInstOperands,
97286 // GIR_Coverage, 5733,
97287 GIR_EraseRootFromParent_Done,
97288 // Label 5532: @259434
97289 GIM_Try, /*On fail goto*//*Label 5533*/ GIMT_Encode4(259515), // Rule ID 5759 //
97290 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
97291 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97292 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
97293 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
97294 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
97295 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
97296 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
97297 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
97298 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97299 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
97300 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
97301 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
97302 // MIs[3] Operand 1
97303 // No operand predicates
97304 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97305 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97306 GIM_CheckIsSafeToFold, /*NumInsns*/3,
97307 // (fma:{ *:[f64] } (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
97308 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
97309 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
97310 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
97311 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
97312 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
97313 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
97314 GIR_RootConstrainSelectedInstOperands,
97315 // GIR_Coverage, 5759,
97316 GIR_EraseRootFromParent_Done,
97317 // Label 5533: @259515
97318 GIM_Try, /*On fail goto*//*Label 5534*/ GIMT_Encode4(259599), // Rule ID 5785 //
97319 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
97320 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97321 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
97322 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
97323 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97324 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
97325 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
97326 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
97327 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
97328 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97329 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
97330 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
97331 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
97332 // MIs[3] Operand 1
97333 // No operand predicates
97334 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97335 GIM_CheckIsSafeToFold, /*NumInsns*/3,
97336 // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
97337 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
97338 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
97339 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
97340 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
97341 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
97342 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
97343 GIR_RootConstrainSelectedInstOperands,
97344 // GIR_Coverage, 5785,
97345 GIR_EraseRootFromParent_Done,
97346 // Label 5534: @259599
97347 GIM_Try, /*On fail goto*//*Label 5535*/ GIMT_Encode4(259677), // Rule ID 5829 //
97348 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97349 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
97350 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
97351 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
97352 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
97353 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
97354 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
97355 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
97356 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97357 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
97358 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
97359 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
97360 // MIs[3] Operand 1
97361 // No operand predicates
97362 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97363 GIM_CheckIsSafeToFold, /*NumInsns*/3,
97364 // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
97365 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
97366 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
97367 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
97368 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
97369 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
97370 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
97371 GIR_RootConstrainSelectedInstOperands,
97372 // GIR_Coverage, 5829,
97373 GIR_EraseRootFromParent_Done,
97374 // Label 5535: @259677
97375 GIM_Try, /*On fail goto*//*Label 5536*/ GIMT_Encode4(259758), // Rule ID 5707 //
97376 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
97377 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97378 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
97379 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
97380 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
97381 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
97382 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
97383 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
97384 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
97385 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97386 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
97387 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
97388 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
97389 // MIs[3] Operand 1
97390 // No operand predicates
97391 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97392 GIM_CheckIsSafeToFold, /*NumInsns*/3,
97393 // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
97394 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
97395 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
97396 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
97397 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
97398 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
97399 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
97400 GIR_RootConstrainSelectedInstOperands,
97401 // GIR_Coverage, 5707,
97402 GIR_EraseRootFromParent_Done,
97403 // Label 5536: @259758
97404 GIM_Try, /*On fail goto*//*Label 5537*/ GIMT_Encode4(259843), // Rule ID 2394 //
97405 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
97406 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97407 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
97408 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
97409 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
97410 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97411 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
97412 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97413 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97414 GIM_CheckIsSafeToFold, /*NumInsns*/1,
97415 // (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) => (FMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
97416 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
97417 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
97418 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
97419 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
97420 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
97421 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
97422 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
97423 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
97424 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
97425 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
97426 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
97427 GIR_RootConstrainSelectedInstOperands,
97428 // GIR_Coverage, 2394,
97429 GIR_EraseRootFromParent_Done,
97430 // Label 5537: @259843
97431 GIM_Try, /*On fail goto*//*Label 5538*/ GIMT_Encode4(259928), // Rule ID 2392 //
97432 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
97433 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97434 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
97435 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
97436 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
97437 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
97438 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97439 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
97440 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97441 GIM_CheckIsSafeToFold, /*NumInsns*/1,
97442 // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra) => (FMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
97443 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
97444 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
97445 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
97446 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rm
97447 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
97448 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
97449 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
97450 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
97451 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
97452 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
97453 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
97454 GIR_RootConstrainSelectedInstOperands,
97455 // GIR_Coverage, 2392,
97456 GIR_EraseRootFromParent_Done,
97457 // Label 5538: @259928
97458 GIM_Try, /*On fail goto*//*Label 5539*/ GIMT_Encode4(259997), // Rule ID 2468 //
97459 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
97460 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97461 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
97462 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
97463 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
97464 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97465 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
97466 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
97467 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
97468 // MIs[2] Operand 1
97469 // No operand predicates
97470 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97471 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97472 GIM_CheckIsSafeToFold, /*NumInsns*/2,
97473 // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd) => (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
97474 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
97475 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
97476 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
97477 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
97478 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
97479 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
97480 GIR_RootConstrainSelectedInstOperands,
97481 // GIR_Coverage, 2468,
97482 GIR_EraseRootFromParent_Done,
97483 // Label 5539: @259997
97484 GIM_Try, /*On fail goto*//*Label 5540*/ GIMT_Encode4(260066), // Rule ID 5681 //
97485 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
97486 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97487 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
97488 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
97489 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
97490 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
97491 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97492 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
97493 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
97494 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
97495 // MIs[2] Operand 1
97496 // No operand predicates
97497 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97498 GIM_CheckIsSafeToFold, /*NumInsns*/2,
97499 // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd) => (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
97500 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
97501 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
97502 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
97503 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
97504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
97505 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
97506 GIR_RootConstrainSelectedInstOperands,
97507 // GIR_Coverage, 5681,
97508 GIR_EraseRootFromParent_Done,
97509 // Label 5540: @260066
97510 GIM_Try, /*On fail goto*//*Label 5541*/ GIMT_Encode4(260128), // Rule ID 4541 //
97511 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97512 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
97513 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
97514 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97515 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97516 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
97517 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
97518 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
97519 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97520 GIM_CheckIsSafeToFold, /*NumInsns*/2,
97521 // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
97522 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
97523 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
97524 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
97525 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
97526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
97527 GIR_RootConstrainSelectedInstOperands,
97528 // GIR_Coverage, 4541,
97529 GIR_EraseRootFromParent_Done,
97530 // Label 5541: @260128
97531 GIM_Try, /*On fail goto*//*Label 5542*/ GIMT_Encode4(260190), // Rule ID 13105 //
97532 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97533 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
97534 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
97535 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
97536 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97537 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
97538 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
97539 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
97540 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97541 GIM_CheckIsSafeToFold, /*NumInsns*/2,
97542 // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
97543 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
97544 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
97545 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
97546 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
97547 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
97548 GIR_RootConstrainSelectedInstOperands,
97549 // GIR_Coverage, 13105,
97550 GIR_EraseRootFromParent_Done,
97551 // Label 5542: @260190
97552 GIM_Try, /*On fail goto*//*Label 5543*/ GIMT_Encode4(260237), // Rule ID 4538 //
97553 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97554 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
97555 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
97556 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97557 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97558 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97559 GIM_CheckIsSafeToFold, /*NumInsns*/1,
97560 // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
97561 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
97562 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
97563 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
97564 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
97565 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
97566 GIR_RootConstrainSelectedInstOperands,
97567 // GIR_Coverage, 4538,
97568 GIR_EraseRootFromParent_Done,
97569 // Label 5543: @260237
97570 GIM_Try, /*On fail goto*//*Label 5544*/ GIMT_Encode4(260287), // Rule ID 12551 //
97571 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
97572 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97573 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
97574 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
97575 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97576 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97577 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97578 GIM_CheckIsSafeToFold, /*NumInsns*/1,
97579 // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
97580 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
97581 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
97582 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
97583 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
97584 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
97585 GIR_RootConstrainSelectedInstOperands,
97586 // GIR_Coverage, 12551,
97587 GIR_EraseRootFromParent_Done,
97588 // Label 5544: @260287
97589 GIM_Try, /*On fail goto*//*Label 5545*/ GIMT_Encode4(260337), // Rule ID 642 //
97590 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
97591 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97592 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
97593 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
97594 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
97595 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97596 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97597 GIM_CheckIsSafeToFold, /*NumInsns*/1,
97598 // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
97599 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
97600 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
97601 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
97602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
97603 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
97604 GIR_RootConstrainSelectedInstOperands,
97605 // GIR_Coverage, 642,
97606 GIR_EraseRootFromParent_Done,
97607 // Label 5545: @260337
97608 GIM_Try, /*On fail goto*//*Label 5546*/ GIMT_Encode4(260384), // Rule ID 13102 //
97609 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97610 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
97611 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
97612 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
97613 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97614 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97615 GIM_CheckIsSafeToFold, /*NumInsns*/1,
97616 // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
97617 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
97618 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
97619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
97620 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
97621 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
97622 GIR_RootConstrainSelectedInstOperands,
97623 // GIR_Coverage, 13102,
97624 GIR_EraseRootFromParent_Done,
97625 // Label 5546: @260384
97626 GIM_Try, /*On fail goto*//*Label 5547*/ GIMT_Encode4(260434), // Rule ID 654 //
97627 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
97628 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97629 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97630 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
97631 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
97632 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
97633 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97634 GIM_CheckIsSafeToFold, /*NumInsns*/1,
97635 // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
97636 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
97637 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
97638 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
97639 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
97640 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra
97641 GIR_RootConstrainSelectedInstOperands,
97642 // GIR_Coverage, 654,
97643 GIR_EraseRootFromParent_Done,
97644 // Label 5547: @260434
97645 GIM_Try, /*On fail goto*//*Label 5548*/ GIMT_Encode4(260465), // Rule ID 636 //
97646 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
97647 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97648 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97649 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97650 // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) => (FMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
97651 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
97652 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
97653 GIR_RootConstrainSelectedInstOperands,
97654 // GIR_Coverage, 636,
97655 GIR_Done,
97656 // Label 5548: @260465
97657 GIM_Reject,
97658 // Label 5524: @260466
97659 GIM_Reject,
97660 // Label 5470: @260467
97661 GIM_Try, /*On fail goto*//*Label 5549*/ GIMT_Encode4(261987),
97662 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
97663 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
97664 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
97665 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97666 GIM_Try, /*On fail goto*//*Label 5550*/ GIMT_Encode4(260563), // Rule ID 5787 //
97667 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97668 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
97669 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
97670 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
97671 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
97672 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
97673 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
97674 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97675 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
97676 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
97677 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
97678 // MIs[3] Operand 1
97679 // No operand predicates
97680 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97681 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97682 GIM_CheckIsSafeToFold, /*NumInsns*/3,
97683 // (fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
97684 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
97685 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
97686 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
97687 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
97688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
97689 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
97690 GIR_RootConstrainSelectedInstOperands,
97691 // GIR_Coverage, 5787,
97692 GIR_EraseRootFromParent_Done,
97693 // Label 5550: @260563
97694 GIM_Try, /*On fail goto*//*Label 5551*/ GIMT_Encode4(260647), // Rule ID 5719 //
97695 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
97696 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97697 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
97698 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
97699 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
97700 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97701 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
97702 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
97703 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
97704 // MIs[2] Operand 1
97705 // No operand predicates
97706 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
97707 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
97708 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s32,
97709 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97710 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97711 GIM_CheckIsSafeToFold, /*NumInsns*/3,
97712 // (fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
97713 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
97714 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
97715 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
97716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
97717 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
97718 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
97719 GIR_RootConstrainSelectedInstOperands,
97720 // GIR_Coverage, 5719,
97721 GIR_EraseRootFromParent_Done,
97722 // Label 5551: @260647
97723 GIM_Try, /*On fail goto*//*Label 5552*/ GIMT_Encode4(260728), // Rule ID 5745 //
97724 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
97725 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97726 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
97727 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
97728 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
97729 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
97730 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
97731 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
97732 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97733 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
97734 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
97735 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
97736 // MIs[3] Operand 1
97737 // No operand predicates
97738 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97739 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97740 GIM_CheckIsSafeToFold, /*NumInsns*/3,
97741 // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
97742 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
97743 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
97744 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
97745 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
97746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
97747 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
97748 GIR_RootConstrainSelectedInstOperands,
97749 // GIR_Coverage, 5745,
97750 GIR_EraseRootFromParent_Done,
97751 // Label 5552: @260728
97752 GIM_Try, /*On fail goto*//*Label 5553*/ GIMT_Encode4(260812), // Rule ID 5771 //
97753 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
97754 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97755 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
97756 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
97757 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97758 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
97759 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
97760 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
97761 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
97762 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97763 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
97764 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
97765 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
97766 // MIs[3] Operand 1
97767 // No operand predicates
97768 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97769 GIM_CheckIsSafeToFold, /*NumInsns*/3,
97770 // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
97771 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
97772 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
97773 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
97774 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
97775 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
97776 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
97777 GIR_RootConstrainSelectedInstOperands,
97778 // GIR_Coverage, 5771,
97779 GIR_EraseRootFromParent_Done,
97780 // Label 5553: @260812
97781 GIM_Try, /*On fail goto*//*Label 5554*/ GIMT_Encode4(260890), // Rule ID 5809 //
97782 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97783 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
97784 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
97785 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
97786 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
97787 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
97788 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
97789 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
97790 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97791 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
97792 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
97793 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
97794 // MIs[3] Operand 1
97795 // No operand predicates
97796 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97797 GIM_CheckIsSafeToFold, /*NumInsns*/3,
97798 // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
97799 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
97800 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
97801 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
97802 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
97803 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
97804 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
97805 GIR_RootConstrainSelectedInstOperands,
97806 // GIR_Coverage, 5809,
97807 GIR_EraseRootFromParent_Done,
97808 // Label 5554: @260890
97809 GIM_Try, /*On fail goto*//*Label 5555*/ GIMT_Encode4(260971), // Rule ID 5693 //
97810 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
97811 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97812 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
97813 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
97814 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
97815 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
97816 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
97817 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
97818 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
97819 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97820 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
97821 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
97822 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
97823 // MIs[3] Operand 1
97824 // No operand predicates
97825 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97826 GIM_CheckIsSafeToFold, /*NumInsns*/3,
97827 // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
97828 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
97829 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
97830 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
97831 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
97832 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
97833 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
97834 GIR_RootConstrainSelectedInstOperands,
97835 // GIR_Coverage, 5693,
97836 GIR_EraseRootFromParent_Done,
97837 // Label 5555: @260971
97838 GIM_Try, /*On fail goto*//*Label 5556*/ GIMT_Encode4(261040), // Rule ID 2454 //
97839 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
97840 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97841 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
97842 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
97843 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
97844 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97845 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
97846 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
97847 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
97848 // MIs[2] Operand 1
97849 // No operand predicates
97850 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97851 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97852 GIM_CheckIsSafeToFold, /*NumInsns*/2,
97853 // (fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
97854 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
97855 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
97856 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
97857 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
97858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
97859 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
97860 GIR_RootConstrainSelectedInstOperands,
97861 // GIR_Coverage, 2454,
97862 GIR_EraseRootFromParent_Done,
97863 // Label 5556: @261040
97864 GIM_Try, /*On fail goto*//*Label 5557*/ GIMT_Encode4(261109), // Rule ID 5667 //
97865 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
97866 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97867 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
97868 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
97869 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
97870 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
97871 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
97872 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
97873 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
97874 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
97875 // MIs[2] Operand 1
97876 // No operand predicates
97877 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97878 GIM_CheckIsSafeToFold, /*NumInsns*/2,
97879 // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
97880 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
97881 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
97882 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
97883 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
97884 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
97885 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
97886 GIR_RootConstrainSelectedInstOperands,
97887 // GIR_Coverage, 5667,
97888 GIR_EraseRootFromParent_Done,
97889 // Label 5557: @261109
97890 GIM_Try, /*On fail goto*//*Label 5558*/ GIMT_Encode4(261202), // Rule ID 5791 //
97891 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97892 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
97893 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
97894 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
97895 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
97896 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
97897 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
97898 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97899 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97900 GIM_CheckIsSafeToFold, /*NumInsns*/2,
97901 // (fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
97902 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
97903 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
97904 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
97905 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
97906 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
97907 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
97908 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
97909 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
97910 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
97911 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
97912 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
97913 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
97914 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
97915 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
97916 GIR_RootConstrainSelectedInstOperands,
97917 // GIR_Coverage, 5791,
97918 GIR_EraseRootFromParent_Done,
97919 // Label 5558: @261202
97920 GIM_Try, /*On fail goto*//*Label 5559*/ GIMT_Encode4(261301), // Rule ID 5721 //
97921 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
97922 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97923 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
97924 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
97925 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
97926 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
97927 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
97928 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
97929 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97930 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97931 GIM_CheckIsSafeToFold, /*NumInsns*/2,
97932 // (fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
97933 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
97934 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
97935 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
97936 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
97937 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
97938 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
97939 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
97940 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
97941 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
97942 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
97943 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
97944 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
97945 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
97946 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
97947 GIR_RootConstrainSelectedInstOperands,
97948 // GIR_Coverage, 5721,
97949 GIR_EraseRootFromParent_Done,
97950 // Label 5559: @261301
97951 GIM_Try, /*On fail goto*//*Label 5560*/ GIMT_Encode4(261397), // Rule ID 5747 //
97952 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
97953 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97954 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
97955 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
97956 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
97957 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
97958 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
97959 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
97960 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97961 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97962 GIM_CheckIsSafeToFold, /*NumInsns*/2,
97963 // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
97964 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
97965 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
97966 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
97967 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
97968 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
97969 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
97970 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
97971 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
97972 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
97973 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
97974 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
97975 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
97976 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
97977 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
97978 GIR_RootConstrainSelectedInstOperands,
97979 // GIR_Coverage, 5747,
97980 GIR_EraseRootFromParent_Done,
97981 // Label 5560: @261397
97982 GIM_Try, /*On fail goto*//*Label 5561*/ GIMT_Encode4(261496), // Rule ID 5773 //
97983 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
97984 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
97985 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
97986 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
97987 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97988 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
97989 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
97990 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
97991 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
97992 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
97993 GIM_CheckIsSafeToFold, /*NumInsns*/2,
97994 // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
97995 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
97996 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
97997 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
97998 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
97999 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
98000 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
98001 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
98002 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
98003 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
98004 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98005 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98006 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
98007 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
98008 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
98009 GIR_RootConstrainSelectedInstOperands,
98010 // GIR_Coverage, 5773,
98011 GIR_EraseRootFromParent_Done,
98012 // Label 5561: @261496
98013 GIM_Try, /*On fail goto*//*Label 5562*/ GIMT_Encode4(261589), // Rule ID 5813 //
98014 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98015 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
98016 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
98017 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
98018 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
98019 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
98020 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
98021 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
98022 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98023 GIM_CheckIsSafeToFold, /*NumInsns*/2,
98024 // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
98025 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
98026 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
98027 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
98028 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
98029 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
98030 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
98031 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
98032 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
98033 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
98034 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98035 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98036 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
98037 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
98038 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
98039 GIR_RootConstrainSelectedInstOperands,
98040 // GIR_Coverage, 5813,
98041 GIR_EraseRootFromParent_Done,
98042 // Label 5562: @261589
98043 GIM_Try, /*On fail goto*//*Label 5563*/ GIMT_Encode4(261685), // Rule ID 5695 //
98044 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98045 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98046 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
98047 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
98048 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
98049 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
98050 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
98051 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
98052 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
98053 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98054 GIM_CheckIsSafeToFold, /*NumInsns*/2,
98055 // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
98056 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
98057 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
98058 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
98059 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
98060 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
98061 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
98062 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
98063 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
98064 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
98065 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98066 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98067 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
98068 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
98069 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
98070 GIR_RootConstrainSelectedInstOperands,
98071 // GIR_Coverage, 5695,
98072 GIR_EraseRootFromParent_Done,
98073 // Label 5563: @261685
98074 GIM_Try, /*On fail goto*//*Label 5564*/ GIMT_Encode4(261769), // Rule ID 2456 //
98075 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98076 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98077 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
98078 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
98079 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
98080 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98081 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98082 GIM_CheckIsSafeToFold, /*NumInsns*/1,
98083 // (fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
98084 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
98085 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
98086 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
98087 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
98088 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
98089 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
98090 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
98091 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
98092 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
98093 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98094 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98095 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
98096 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
98097 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
98098 GIR_RootConstrainSelectedInstOperands,
98099 // GIR_Coverage, 2456,
98100 GIR_EraseRootFromParent_Done,
98101 // Label 5564: @261769
98102 GIM_Try, /*On fail goto*//*Label 5565*/ GIMT_Encode4(261819), // Rule ID 12581 //
98103 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98104 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98105 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
98106 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
98107 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98108 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98109 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98110 GIM_CheckIsSafeToFold, /*NumInsns*/1,
98111 // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
98112 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f32),
98113 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98114 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98115 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
98116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
98117 GIR_RootConstrainSelectedInstOperands,
98118 // GIR_Coverage, 12581,
98119 GIR_EraseRootFromParent_Done,
98120 // Label 5565: @261819
98121 GIM_Try, /*On fail goto*//*Label 5566*/ GIMT_Encode4(261903), // Rule ID 5669 //
98122 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98123 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98124 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
98125 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
98126 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
98127 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
98128 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98129 GIM_CheckIsSafeToFold, /*NumInsns*/1,
98130 // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
98131 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
98132 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
98133 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
98134 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
98135 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
98136 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
98137 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
98138 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
98139 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
98140 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98141 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98142 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
98143 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
98144 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
98145 GIR_RootConstrainSelectedInstOperands,
98146 // GIR_Coverage, 5669,
98147 GIR_EraseRootFromParent_Done,
98148 // Label 5566: @261903
98149 GIM_Try, /*On fail goto*//*Label 5567*/ GIMT_Encode4(261953), // Rule ID 1295 //
98150 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98151 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98152 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
98153 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
98154 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
98155 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98156 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98157 GIM_CheckIsSafeToFold, /*NumInsns*/1,
98158 // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rd) => (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
98159 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f32),
98160 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98161 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98162 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
98163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
98164 GIR_RootConstrainSelectedInstOperands,
98165 // GIR_Coverage, 1295,
98166 GIR_EraseRootFromParent_Done,
98167 // Label 5567: @261953
98168 GIM_Try, /*On fail goto*//*Label 5568*/ GIMT_Encode4(261986), // Rule ID 1285 //
98169 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98170 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98171 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98172 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98173 // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLAv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
98174 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2f32),
98175 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98176 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98177 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
98178 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
98179 GIR_RootConstrainSelectedInstOperands,
98180 // GIR_Coverage, 1285,
98181 GIR_EraseRootFromParent_Done,
98182 // Label 5568: @261986
98183 GIM_Reject,
98184 // Label 5549: @261987
98185 GIM_Reject,
98186 // Label 5471: @261988
98187 GIM_Try, /*On fail goto*//*Label 5569*/ GIMT_Encode4(263508),
98188 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
98189 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
98190 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
98191 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98192 GIM_Try, /*On fail goto*//*Label 5570*/ GIMT_Encode4(262084), // Rule ID 5799 //
98193 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98194 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
98195 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
98196 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
98197 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
98198 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
98199 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
98200 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98201 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
98202 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
98203 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
98204 // MIs[3] Operand 1
98205 // No operand predicates
98206 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98207 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98208 GIM_CheckIsSafeToFold, /*NumInsns*/3,
98209 // (fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
98210 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
98211 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98212 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98213 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
98214 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
98215 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
98216 GIR_RootConstrainSelectedInstOperands,
98217 // GIR_Coverage, 5799,
98218 GIR_EraseRootFromParent_Done,
98219 // Label 5570: @262084
98220 GIM_Try, /*On fail goto*//*Label 5571*/ GIMT_Encode4(262168), // Rule ID 5727 //
98221 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98222 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98223 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
98224 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
98225 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
98226 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98227 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
98228 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
98229 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
98230 // MIs[2] Operand 1
98231 // No operand predicates
98232 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
98233 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
98234 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
98235 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98236 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98237 GIM_CheckIsSafeToFold, /*NumInsns*/3,
98238 // (fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
98239 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
98240 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98241 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98242 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
98243 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
98244 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
98245 GIR_RootConstrainSelectedInstOperands,
98246 // GIR_Coverage, 5727,
98247 GIR_EraseRootFromParent_Done,
98248 // Label 5571: @262168
98249 GIM_Try, /*On fail goto*//*Label 5572*/ GIMT_Encode4(262249), // Rule ID 5753 //
98250 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98251 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98252 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
98253 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
98254 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
98255 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
98256 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
98257 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
98258 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98259 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
98260 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
98261 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
98262 // MIs[3] Operand 1
98263 // No operand predicates
98264 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98265 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98266 GIM_CheckIsSafeToFold, /*NumInsns*/3,
98267 // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
98268 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
98269 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98270 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98271 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
98272 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
98273 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
98274 GIR_RootConstrainSelectedInstOperands,
98275 // GIR_Coverage, 5753,
98276 GIR_EraseRootFromParent_Done,
98277 // Label 5572: @262249
98278 GIM_Try, /*On fail goto*//*Label 5573*/ GIMT_Encode4(262333), // Rule ID 5779 //
98279 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98280 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98281 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
98282 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
98283 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98284 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
98285 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
98286 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
98287 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
98288 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98289 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
98290 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
98291 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
98292 // MIs[3] Operand 1
98293 // No operand predicates
98294 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98295 GIM_CheckIsSafeToFold, /*NumInsns*/3,
98296 // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
98297 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
98298 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98299 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98300 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
98301 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
98302 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
98303 GIR_RootConstrainSelectedInstOperands,
98304 // GIR_Coverage, 5779,
98305 GIR_EraseRootFromParent_Done,
98306 // Label 5573: @262333
98307 GIM_Try, /*On fail goto*//*Label 5574*/ GIMT_Encode4(262411), // Rule ID 5821 //
98308 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98309 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
98310 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
98311 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
98312 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
98313 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
98314 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
98315 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
98316 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98317 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
98318 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
98319 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
98320 // MIs[3] Operand 1
98321 // No operand predicates
98322 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98323 GIM_CheckIsSafeToFold, /*NumInsns*/3,
98324 // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
98325 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
98326 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98327 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98328 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
98329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
98330 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
98331 GIR_RootConstrainSelectedInstOperands,
98332 // GIR_Coverage, 5821,
98333 GIR_EraseRootFromParent_Done,
98334 // Label 5574: @262411
98335 GIM_Try, /*On fail goto*//*Label 5575*/ GIMT_Encode4(262492), // Rule ID 5701 //
98336 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98337 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98338 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
98339 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
98340 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
98341 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
98342 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
98343 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
98344 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
98345 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98346 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
98347 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
98348 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
98349 // MIs[3] Operand 1
98350 // No operand predicates
98351 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98352 GIM_CheckIsSafeToFold, /*NumInsns*/3,
98353 // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
98354 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
98355 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98356 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98357 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
98358 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
98359 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
98360 GIR_RootConstrainSelectedInstOperands,
98361 // GIR_Coverage, 5701,
98362 GIR_EraseRootFromParent_Done,
98363 // Label 5575: @262492
98364 GIM_Try, /*On fail goto*//*Label 5576*/ GIMT_Encode4(262561), // Rule ID 2462 //
98365 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98366 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98367 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
98368 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
98369 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
98370 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98371 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
98372 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
98373 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
98374 // MIs[2] Operand 1
98375 // No operand predicates
98376 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98377 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98378 GIM_CheckIsSafeToFold, /*NumInsns*/2,
98379 // (fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
98380 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
98381 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98382 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98383 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
98384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
98385 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
98386 GIR_RootConstrainSelectedInstOperands,
98387 // GIR_Coverage, 2462,
98388 GIR_EraseRootFromParent_Done,
98389 // Label 5576: @262561
98390 GIM_Try, /*On fail goto*//*Label 5577*/ GIMT_Encode4(262630), // Rule ID 5675 //
98391 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98392 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98393 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
98394 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
98395 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
98396 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
98397 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98398 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
98399 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
98400 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
98401 // MIs[2] Operand 1
98402 // No operand predicates
98403 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98404 GIM_CheckIsSafeToFold, /*NumInsns*/2,
98405 // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
98406 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
98407 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98408 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98409 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
98410 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
98411 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
98412 GIR_RootConstrainSelectedInstOperands,
98413 // GIR_Coverage, 5675,
98414 GIR_EraseRootFromParent_Done,
98415 // Label 5577: @262630
98416 GIM_Try, /*On fail goto*//*Label 5578*/ GIMT_Encode4(262723), // Rule ID 5801 //
98417 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98418 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
98419 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
98420 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
98421 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
98422 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
98423 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98424 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98425 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98426 GIM_CheckIsSafeToFold, /*NumInsns*/2,
98427 // (fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } (fneg:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
98428 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
98429 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
98430 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
98431 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
98432 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
98433 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
98434 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
98435 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
98436 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
98437 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98438 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98439 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
98440 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
98441 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
98442 GIR_RootConstrainSelectedInstOperands,
98443 // GIR_Coverage, 5801,
98444 GIR_EraseRootFromParent_Done,
98445 // Label 5578: @262723
98446 GIM_Try, /*On fail goto*//*Label 5579*/ GIMT_Encode4(262822), // Rule ID 5729 //
98447 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98448 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98449 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
98450 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
98451 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98452 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
98453 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
98454 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
98455 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98456 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98457 GIM_CheckIsSafeToFold, /*NumInsns*/2,
98458 // (fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
98459 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
98460 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
98461 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
98462 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
98463 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
98464 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
98465 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
98466 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
98467 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
98468 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98469 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98470 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
98471 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
98472 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
98473 GIR_RootConstrainSelectedInstOperands,
98474 // GIR_Coverage, 5729,
98475 GIR_EraseRootFromParent_Done,
98476 // Label 5579: @262822
98477 GIM_Try, /*On fail goto*//*Label 5580*/ GIMT_Encode4(262918), // Rule ID 5755 //
98478 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98479 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98480 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
98481 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
98482 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
98483 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
98484 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
98485 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98486 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98487 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98488 GIM_CheckIsSafeToFold, /*NumInsns*/2,
98489 // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
98490 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
98491 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
98492 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
98493 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
98494 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
98495 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
98496 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
98497 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
98498 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
98499 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98500 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98501 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
98502 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
98503 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
98504 GIR_RootConstrainSelectedInstOperands,
98505 // GIR_Coverage, 5755,
98506 GIR_EraseRootFromParent_Done,
98507 // Label 5580: @262918
98508 GIM_Try, /*On fail goto*//*Label 5581*/ GIMT_Encode4(263017), // Rule ID 5781 //
98509 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98510 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98511 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
98512 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
98513 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98514 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
98515 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
98516 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
98517 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98518 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98519 GIM_CheckIsSafeToFold, /*NumInsns*/2,
98520 // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
98521 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
98522 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
98523 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
98524 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
98525 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
98526 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
98527 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
98528 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
98529 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
98530 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98531 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98532 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
98533 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
98534 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
98535 GIR_RootConstrainSelectedInstOperands,
98536 // GIR_Coverage, 5781,
98537 GIR_EraseRootFromParent_Done,
98538 // Label 5581: @263017
98539 GIM_Try, /*On fail goto*//*Label 5582*/ GIMT_Encode4(263110), // Rule ID 5823 //
98540 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98541 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
98542 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
98543 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
98544 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
98545 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
98546 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
98547 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98548 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98549 GIM_CheckIsSafeToFold, /*NumInsns*/2,
98550 // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } (fneg:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
98551 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
98552 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
98553 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
98554 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
98555 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
98556 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
98557 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
98558 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
98559 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
98560 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98561 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98562 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
98563 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
98564 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
98565 GIR_RootConstrainSelectedInstOperands,
98566 // GIR_Coverage, 5823,
98567 GIR_EraseRootFromParent_Done,
98568 // Label 5582: @263110
98569 GIM_Try, /*On fail goto*//*Label 5583*/ GIMT_Encode4(263206), // Rule ID 5703 //
98570 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98571 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98572 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
98573 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
98574 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
98575 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
98576 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
98577 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
98578 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98579 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98580 GIM_CheckIsSafeToFold, /*NumInsns*/2,
98581 // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
98582 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
98583 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
98584 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
98585 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
98586 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
98587 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
98588 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
98589 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
98590 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
98591 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98592 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98593 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
98594 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
98595 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
98596 GIR_RootConstrainSelectedInstOperands,
98597 // GIR_Coverage, 5703,
98598 GIR_EraseRootFromParent_Done,
98599 // Label 5583: @263206
98600 GIM_Try, /*On fail goto*//*Label 5584*/ GIMT_Encode4(263290), // Rule ID 2464 //
98601 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98602 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98603 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
98604 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
98605 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98606 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98607 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98608 GIM_CheckIsSafeToFold, /*NumInsns*/1,
98609 // (fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
98610 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
98611 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
98612 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
98613 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
98614 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
98615 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
98616 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
98617 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
98618 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
98619 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98620 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98621 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
98622 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
98623 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
98624 GIR_RootConstrainSelectedInstOperands,
98625 // GIR_Coverage, 2464,
98626 GIR_EraseRootFromParent_Done,
98627 // Label 5584: @263290
98628 GIM_Try, /*On fail goto*//*Label 5585*/ GIMT_Encode4(263340), // Rule ID 12585 //
98629 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98630 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98631 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
98632 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
98633 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98634 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98635 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98636 GIM_CheckIsSafeToFold, /*NumInsns*/1,
98637 // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
98638 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f64),
98639 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98640 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98641 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
98642 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
98643 GIR_RootConstrainSelectedInstOperands,
98644 // GIR_Coverage, 12585,
98645 GIR_EraseRootFromParent_Done,
98646 // Label 5585: @263340
98647 GIM_Try, /*On fail goto*//*Label 5586*/ GIMT_Encode4(263424), // Rule ID 5677 //
98648 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98649 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98650 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
98651 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
98652 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
98653 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98654 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98655 GIM_CheckIsSafeToFold, /*NumInsns*/1,
98656 // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
98657 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
98658 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
98659 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
98660 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
98661 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
98662 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
98663 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
98664 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
98665 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
98666 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98667 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98668 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
98669 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
98670 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
98671 GIR_RootConstrainSelectedInstOperands,
98672 // GIR_Coverage, 5677,
98673 GIR_EraseRootFromParent_Done,
98674 // Label 5586: @263424
98675 GIM_Try, /*On fail goto*//*Label 5587*/ GIMT_Encode4(263474), // Rule ID 1299 //
98676 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98677 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98678 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
98679 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
98680 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
98681 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98682 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98683 GIM_CheckIsSafeToFold, /*NumInsns*/1,
98684 // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rd) => (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
98685 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f64),
98686 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98687 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98688 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
98689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
98690 GIR_RootConstrainSelectedInstOperands,
98691 // GIR_Coverage, 1299,
98692 GIR_EraseRootFromParent_Done,
98693 // Label 5587: @263474
98694 GIM_Try, /*On fail goto*//*Label 5588*/ GIMT_Encode4(263507), // Rule ID 1289 //
98695 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
98696 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98697 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98698 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
98699 // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLAv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
98700 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2f64),
98701 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98702 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98703 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
98704 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
98705 GIR_RootConstrainSelectedInstOperands,
98706 // GIR_Coverage, 1289,
98707 GIR_EraseRootFromParent_Done,
98708 // Label 5588: @263507
98709 GIM_Reject,
98710 // Label 5569: @263508
98711 GIM_Reject,
98712 // Label 5472: @263509
98713 GIM_Try, /*On fail goto*//*Label 5589*/ GIMT_Encode4(264687),
98714 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
98715 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
98716 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
98717 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98718 GIM_Try, /*On fail goto*//*Label 5590*/ GIMT_Encode4(263611), // Rule ID 5713 //
98719 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
98720 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98721 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
98722 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
98723 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
98724 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
98725 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
98726 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
98727 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
98728 // MIs[2] Operand 1
98729 // No operand predicates
98730 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
98731 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
98732 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16,
98733 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98734 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98735 GIM_CheckIsSafeToFold, /*NumInsns*/3,
98736 // (fma:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
98737 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
98738 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98739 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98740 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
98741 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
98742 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
98743 GIR_RootConstrainSelectedInstOperands,
98744 // GIR_Coverage, 5713,
98745 GIR_EraseRootFromParent_Done,
98746 // Label 5590: @263611
98747 GIM_Try, /*On fail goto*//*Label 5591*/ GIMT_Encode4(263692), // Rule ID 5739 //
98748 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
98749 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98750 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
98751 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
98752 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
98753 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
98754 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
98755 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
98756 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
98757 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
98758 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
98759 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
98760 // MIs[3] Operand 1
98761 // No operand predicates
98762 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98763 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98764 GIM_CheckIsSafeToFold, /*NumInsns*/3,
98765 // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
98766 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
98767 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98768 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98769 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
98770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
98771 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
98772 GIR_RootConstrainSelectedInstOperands,
98773 // GIR_Coverage, 5739,
98774 GIR_EraseRootFromParent_Done,
98775 // Label 5591: @263692
98776 GIM_Try, /*On fail goto*//*Label 5592*/ GIMT_Encode4(263776), // Rule ID 5765 //
98777 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
98778 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98779 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
98780 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
98781 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98782 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
98783 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
98784 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
98785 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
98786 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
98787 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
98788 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
98789 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
98790 // MIs[3] Operand 1
98791 // No operand predicates
98792 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98793 GIM_CheckIsSafeToFold, /*NumInsns*/3,
98794 // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
98795 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
98796 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98797 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98798 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
98799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
98800 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
98801 GIR_RootConstrainSelectedInstOperands,
98802 // GIR_Coverage, 5765,
98803 GIR_EraseRootFromParent_Done,
98804 // Label 5592: @263776
98805 GIM_Try, /*On fail goto*//*Label 5593*/ GIMT_Encode4(263857), // Rule ID 5687 //
98806 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
98807 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98808 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
98809 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
98810 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
98811 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
98812 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
98813 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
98814 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
98815 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
98816 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
98817 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
98818 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
98819 // MIs[3] Operand 1
98820 // No operand predicates
98821 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98822 GIM_CheckIsSafeToFold, /*NumInsns*/3,
98823 // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
98824 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
98825 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98826 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98827 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
98828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
98829 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
98830 GIR_RootConstrainSelectedInstOperands,
98831 // GIR_Coverage, 5687,
98832 GIR_EraseRootFromParent_Done,
98833 // Label 5593: @263857
98834 GIM_Try, /*On fail goto*//*Label 5594*/ GIMT_Encode4(263926), // Rule ID 2448 //
98835 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
98836 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98837 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
98838 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
98839 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
98840 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
98841 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
98842 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
98843 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
98844 // MIs[2] Operand 1
98845 // No operand predicates
98846 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98847 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98848 GIM_CheckIsSafeToFold, /*NumInsns*/2,
98849 // (fma:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
98850 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
98851 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98852 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98853 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
98854 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
98855 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
98856 GIR_RootConstrainSelectedInstOperands,
98857 // GIR_Coverage, 2448,
98858 GIR_EraseRootFromParent_Done,
98859 // Label 5594: @263926
98860 GIM_Try, /*On fail goto*//*Label 5595*/ GIMT_Encode4(263995), // Rule ID 5661 //
98861 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
98862 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98863 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
98864 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
98865 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
98866 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
98867 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
98868 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
98869 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
98870 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
98871 // MIs[2] Operand 1
98872 // No operand predicates
98873 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98874 GIM_CheckIsSafeToFold, /*NumInsns*/2,
98875 // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
98876 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
98877 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98878 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98879 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
98880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
98881 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
98882 GIR_RootConstrainSelectedInstOperands,
98883 // GIR_Coverage, 5661,
98884 GIR_EraseRootFromParent_Done,
98885 // Label 5595: @263995
98886 GIM_Try, /*On fail goto*//*Label 5596*/ GIMT_Encode4(264094), // Rule ID 5715 //
98887 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
98888 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98889 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
98890 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
98891 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
98892 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
98893 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
98894 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
98895 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98896 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98897 GIM_CheckIsSafeToFold, /*NumInsns*/2,
98898 // (fma:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
98899 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
98900 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
98901 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
98902 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
98903 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
98904 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
98905 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
98906 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
98907 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
98908 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98909 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98910 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
98911 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
98912 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
98913 GIR_RootConstrainSelectedInstOperands,
98914 // GIR_Coverage, 5715,
98915 GIR_EraseRootFromParent_Done,
98916 // Label 5596: @264094
98917 GIM_Try, /*On fail goto*//*Label 5597*/ GIMT_Encode4(264190), // Rule ID 5741 //
98918 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
98919 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98920 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
98921 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
98922 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
98923 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
98924 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
98925 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
98926 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98927 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98928 GIM_CheckIsSafeToFold, /*NumInsns*/2,
98929 // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
98930 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
98931 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
98932 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
98933 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
98934 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
98935 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
98936 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
98937 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
98938 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
98939 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98940 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98941 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
98942 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
98943 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
98944 GIR_RootConstrainSelectedInstOperands,
98945 // GIR_Coverage, 5741,
98946 GIR_EraseRootFromParent_Done,
98947 // Label 5597: @264190
98948 GIM_Try, /*On fail goto*//*Label 5598*/ GIMT_Encode4(264289), // Rule ID 5767 //
98949 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
98950 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
98951 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
98952 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
98953 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98954 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
98955 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
98956 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
98957 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
98958 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98959 GIM_CheckIsSafeToFold, /*NumInsns*/2,
98960 // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
98961 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
98962 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
98963 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
98964 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
98965 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
98966 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
98967 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
98968 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
98969 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
98970 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
98971 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
98972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
98973 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
98974 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
98975 GIR_RootConstrainSelectedInstOperands,
98976 // GIR_Coverage, 5767,
98977 GIR_EraseRootFromParent_Done,
98978 // Label 5598: @264289
98979 GIM_Try, /*On fail goto*//*Label 5599*/ GIMT_Encode4(264385), // Rule ID 5689 //
98980 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
98981 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98982 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
98983 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
98984 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
98985 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
98986 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
98987 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
98988 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
98989 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
98990 GIM_CheckIsSafeToFold, /*NumInsns*/2,
98991 // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
98992 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
98993 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
98994 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
98995 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
98996 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
98997 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
98998 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
98999 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
99000 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
99001 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99002 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99003 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
99004 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
99005 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
99006 GIR_RootConstrainSelectedInstOperands,
99007 // GIR_Coverage, 5689,
99008 GIR_EraseRootFromParent_Done,
99009 // Label 5599: @264385
99010 GIM_Try, /*On fail goto*//*Label 5600*/ GIMT_Encode4(264469), // Rule ID 2450 //
99011 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
99012 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99013 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
99014 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
99015 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
99016 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
99017 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
99018 GIM_CheckIsSafeToFold, /*NumInsns*/1,
99019 // (fma:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
99020 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
99021 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
99022 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
99023 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
99024 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
99025 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
99026 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
99027 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
99028 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
99029 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99030 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99031 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
99032 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
99033 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
99034 GIR_RootConstrainSelectedInstOperands,
99035 // GIR_Coverage, 2450,
99036 GIR_EraseRootFromParent_Done,
99037 // Label 5600: @264469
99038 GIM_Try, /*On fail goto*//*Label 5601*/ GIMT_Encode4(264519), // Rule ID 12577 //
99039 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
99040 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99041 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
99042 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
99043 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
99044 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
99045 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
99046 GIM_CheckIsSafeToFold, /*NumInsns*/1,
99047 // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
99048 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f16),
99049 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99050 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99051 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
99052 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
99053 GIR_RootConstrainSelectedInstOperands,
99054 // GIR_Coverage, 12577,
99055 GIR_EraseRootFromParent_Done,
99056 // Label 5601: @264519
99057 GIM_Try, /*On fail goto*//*Label 5602*/ GIMT_Encode4(264603), // Rule ID 5663 //
99058 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
99059 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
99060 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
99061 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
99062 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
99063 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
99064 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
99065 GIM_CheckIsSafeToFold, /*NumInsns*/1,
99066 // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
99067 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
99068 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
99069 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
99070 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
99071 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
99072 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
99073 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
99074 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
99075 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
99076 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99077 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99078 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
99079 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
99080 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
99081 GIR_RootConstrainSelectedInstOperands,
99082 // GIR_Coverage, 5663,
99083 GIR_EraseRootFromParent_Done,
99084 // Label 5602: @264603
99085 GIM_Try, /*On fail goto*//*Label 5603*/ GIMT_Encode4(264653), // Rule ID 1291 //
99086 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
99087 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
99088 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
99089 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
99090 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
99091 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
99092 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
99093 GIM_CheckIsSafeToFold, /*NumInsns*/1,
99094 // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rd) => (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
99095 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f16),
99096 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99097 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99098 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
99099 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
99100 GIR_RootConstrainSelectedInstOperands,
99101 // GIR_Coverage, 1291,
99102 GIR_EraseRootFromParent_Done,
99103 // Label 5603: @264653
99104 GIM_Try, /*On fail goto*//*Label 5604*/ GIMT_Encode4(264686), // Rule ID 1281 //
99105 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
99106 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
99107 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
99108 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
99109 // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLAv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
99110 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4f16),
99111 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99112 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99113 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
99114 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
99115 GIR_RootConstrainSelectedInstOperands,
99116 // GIR_Coverage, 1281,
99117 GIR_EraseRootFromParent_Done,
99118 // Label 5604: @264686
99119 GIM_Reject,
99120 // Label 5589: @264687
99121 GIM_Reject,
99122 // Label 5473: @264688
99123 GIM_Try, /*On fail goto*//*Label 5605*/ GIMT_Encode4(266208),
99124 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
99125 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
99126 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
99127 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99128 GIM_Try, /*On fail goto*//*Label 5606*/ GIMT_Encode4(264784), // Rule ID 5793 //
99129 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99130 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
99131 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
99132 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
99133 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
99134 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
99135 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
99136 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99137 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
99138 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
99139 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
99140 // MIs[3] Operand 1
99141 // No operand predicates
99142 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99143 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99144 GIM_CheckIsSafeToFold, /*NumInsns*/3,
99145 // (fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
99146 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
99147 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99148 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99149 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
99150 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
99151 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
99152 GIR_RootConstrainSelectedInstOperands,
99153 // GIR_Coverage, 5793,
99154 GIR_EraseRootFromParent_Done,
99155 // Label 5606: @264784
99156 GIM_Try, /*On fail goto*//*Label 5607*/ GIMT_Encode4(264868), // Rule ID 5723 //
99157 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
99158 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99159 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
99160 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
99161 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
99162 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99163 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
99164 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
99165 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
99166 // MIs[2] Operand 1
99167 // No operand predicates
99168 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
99169 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
99170 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
99171 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99172 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99173 GIM_CheckIsSafeToFold, /*NumInsns*/3,
99174 // (fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
99175 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
99176 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99177 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99178 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
99179 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
99180 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
99181 GIR_RootConstrainSelectedInstOperands,
99182 // GIR_Coverage, 5723,
99183 GIR_EraseRootFromParent_Done,
99184 // Label 5607: @264868
99185 GIM_Try, /*On fail goto*//*Label 5608*/ GIMT_Encode4(264949), // Rule ID 5749 //
99186 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
99187 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99188 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
99189 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
99190 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
99191 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
99192 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
99193 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
99194 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99195 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
99196 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
99197 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
99198 // MIs[3] Operand 1
99199 // No operand predicates
99200 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99201 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99202 GIM_CheckIsSafeToFold, /*NumInsns*/3,
99203 // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
99204 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
99205 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99206 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99207 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
99208 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
99209 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
99210 GIR_RootConstrainSelectedInstOperands,
99211 // GIR_Coverage, 5749,
99212 GIR_EraseRootFromParent_Done,
99213 // Label 5608: @264949
99214 GIM_Try, /*On fail goto*//*Label 5609*/ GIMT_Encode4(265033), // Rule ID 5775 //
99215 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
99216 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99217 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
99218 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
99219 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99220 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
99221 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
99222 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
99223 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
99224 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99225 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
99226 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
99227 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
99228 // MIs[3] Operand 1
99229 // No operand predicates
99230 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99231 GIM_CheckIsSafeToFold, /*NumInsns*/3,
99232 // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
99233 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
99234 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99235 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
99237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
99238 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
99239 GIR_RootConstrainSelectedInstOperands,
99240 // GIR_Coverage, 5775,
99241 GIR_EraseRootFromParent_Done,
99242 // Label 5609: @265033
99243 GIM_Try, /*On fail goto*//*Label 5610*/ GIMT_Encode4(265111), // Rule ID 5815 //
99244 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99245 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
99246 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
99247 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
99248 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
99249 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
99250 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
99251 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
99252 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99253 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
99254 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
99255 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
99256 // MIs[3] Operand 1
99257 // No operand predicates
99258 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99259 GIM_CheckIsSafeToFold, /*NumInsns*/3,
99260 // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
99261 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
99262 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99263 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99264 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
99265 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
99266 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
99267 GIR_RootConstrainSelectedInstOperands,
99268 // GIR_Coverage, 5815,
99269 GIR_EraseRootFromParent_Done,
99270 // Label 5610: @265111
99271 GIM_Try, /*On fail goto*//*Label 5611*/ GIMT_Encode4(265192), // Rule ID 5697 //
99272 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
99273 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99274 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
99275 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
99276 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
99277 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
99278 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
99279 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
99280 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
99281 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99282 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
99283 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
99284 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
99285 // MIs[3] Operand 1
99286 // No operand predicates
99287 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99288 GIM_CheckIsSafeToFold, /*NumInsns*/3,
99289 // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
99290 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
99291 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99292 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99293 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
99294 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
99295 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
99296 GIR_RootConstrainSelectedInstOperands,
99297 // GIR_Coverage, 5697,
99298 GIR_EraseRootFromParent_Done,
99299 // Label 5611: @265192
99300 GIM_Try, /*On fail goto*//*Label 5612*/ GIMT_Encode4(265261), // Rule ID 2458 //
99301 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
99302 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99303 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
99304 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
99305 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
99306 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99307 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
99308 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
99309 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
99310 // MIs[2] Operand 1
99311 // No operand predicates
99312 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99313 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99314 GIM_CheckIsSafeToFold, /*NumInsns*/2,
99315 // (fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
99316 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
99317 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99318 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99319 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
99320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
99321 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
99322 GIR_RootConstrainSelectedInstOperands,
99323 // GIR_Coverage, 2458,
99324 GIR_EraseRootFromParent_Done,
99325 // Label 5612: @265261
99326 GIM_Try, /*On fail goto*//*Label 5613*/ GIMT_Encode4(265330), // Rule ID 5671 //
99327 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
99328 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99329 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
99330 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
99331 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
99332 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
99333 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99334 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
99335 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
99336 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
99337 // MIs[2] Operand 1
99338 // No operand predicates
99339 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99340 GIM_CheckIsSafeToFold, /*NumInsns*/2,
99341 // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
99342 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
99343 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99344 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99345 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
99346 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
99347 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
99348 GIR_RootConstrainSelectedInstOperands,
99349 // GIR_Coverage, 5671,
99350 GIR_EraseRootFromParent_Done,
99351 // Label 5613: @265330
99352 GIM_Try, /*On fail goto*//*Label 5614*/ GIMT_Encode4(265423), // Rule ID 5797 //
99353 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99354 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
99355 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
99356 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
99357 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
99358 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
99359 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
99360 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99361 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99362 GIM_CheckIsSafeToFold, /*NumInsns*/2,
99363 // (fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
99364 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
99365 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
99366 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
99367 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
99368 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
99369 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
99370 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
99371 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
99372 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
99373 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99374 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99375 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
99376 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
99377 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
99378 GIR_RootConstrainSelectedInstOperands,
99379 // GIR_Coverage, 5797,
99380 GIR_EraseRootFromParent_Done,
99381 // Label 5614: @265423
99382 GIM_Try, /*On fail goto*//*Label 5615*/ GIMT_Encode4(265522), // Rule ID 5725 //
99383 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
99384 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99385 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
99386 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
99387 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
99388 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
99389 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
99390 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
99391 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99392 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99393 GIM_CheckIsSafeToFold, /*NumInsns*/2,
99394 // (fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
99395 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
99396 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
99397 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
99398 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
99399 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
99400 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
99401 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
99402 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
99403 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
99404 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99405 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99406 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
99407 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
99408 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
99409 GIR_RootConstrainSelectedInstOperands,
99410 // GIR_Coverage, 5725,
99411 GIR_EraseRootFromParent_Done,
99412 // Label 5615: @265522
99413 GIM_Try, /*On fail goto*//*Label 5616*/ GIMT_Encode4(265618), // Rule ID 5751 //
99414 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
99415 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99416 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
99417 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
99418 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
99419 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
99420 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
99421 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
99422 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99423 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99424 GIM_CheckIsSafeToFold, /*NumInsns*/2,
99425 // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
99426 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
99427 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
99428 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
99429 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
99430 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
99431 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
99432 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
99433 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
99434 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
99435 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99436 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99437 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
99438 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
99439 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
99440 GIR_RootConstrainSelectedInstOperands,
99441 // GIR_Coverage, 5751,
99442 GIR_EraseRootFromParent_Done,
99443 // Label 5616: @265618
99444 GIM_Try, /*On fail goto*//*Label 5617*/ GIMT_Encode4(265717), // Rule ID 5777 //
99445 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
99446 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99447 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
99448 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
99449 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99450 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
99451 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
99452 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
99453 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
99454 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99455 GIM_CheckIsSafeToFold, /*NumInsns*/2,
99456 // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
99457 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
99458 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
99459 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
99460 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
99461 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
99462 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
99463 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
99464 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
99465 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
99466 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99467 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99468 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
99469 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
99470 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
99471 GIR_RootConstrainSelectedInstOperands,
99472 // GIR_Coverage, 5777,
99473 GIR_EraseRootFromParent_Done,
99474 // Label 5617: @265717
99475 GIM_Try, /*On fail goto*//*Label 5618*/ GIMT_Encode4(265810), // Rule ID 5819 //
99476 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99477 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
99478 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
99479 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
99480 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
99481 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
99482 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
99483 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
99484 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99485 GIM_CheckIsSafeToFold, /*NumInsns*/2,
99486 // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
99487 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
99488 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
99489 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
99490 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
99491 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
99492 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
99493 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
99494 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
99495 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
99496 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99497 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99498 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
99499 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
99500 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
99501 GIR_RootConstrainSelectedInstOperands,
99502 // GIR_Coverage, 5819,
99503 GIR_EraseRootFromParent_Done,
99504 // Label 5618: @265810
99505 GIM_Try, /*On fail goto*//*Label 5619*/ GIMT_Encode4(265906), // Rule ID 5699 //
99506 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
99507 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99508 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
99509 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
99510 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
99511 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
99512 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
99513 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
99514 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
99515 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99516 GIM_CheckIsSafeToFold, /*NumInsns*/2,
99517 // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
99518 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
99519 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
99520 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
99521 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
99522 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
99523 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
99524 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
99525 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
99526 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
99527 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99528 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99529 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
99530 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
99531 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
99532 GIR_RootConstrainSelectedInstOperands,
99533 // GIR_Coverage, 5699,
99534 GIR_EraseRootFromParent_Done,
99535 // Label 5619: @265906
99536 GIM_Try, /*On fail goto*//*Label 5620*/ GIMT_Encode4(265990), // Rule ID 2460 //
99537 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
99538 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99539 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
99540 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
99541 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
99542 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99543 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99544 GIM_CheckIsSafeToFold, /*NumInsns*/1,
99545 // (fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
99546 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
99547 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
99548 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
99549 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
99550 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
99551 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
99552 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
99553 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
99554 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
99555 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99556 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99557 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
99558 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
99559 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
99560 GIR_RootConstrainSelectedInstOperands,
99561 // GIR_Coverage, 2460,
99562 GIR_EraseRootFromParent_Done,
99563 // Label 5620: @265990
99564 GIM_Try, /*On fail goto*//*Label 5621*/ GIMT_Encode4(266040), // Rule ID 12583 //
99565 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
99566 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99567 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
99568 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
99569 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99570 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99571 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99572 GIM_CheckIsSafeToFold, /*NumInsns*/1,
99573 // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
99574 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f32),
99575 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99576 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99577 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
99578 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
99579 GIR_RootConstrainSelectedInstOperands,
99580 // GIR_Coverage, 12583,
99581 GIR_EraseRootFromParent_Done,
99582 // Label 5621: @266040
99583 GIM_Try, /*On fail goto*//*Label 5622*/ GIMT_Encode4(266124), // Rule ID 5673 //
99584 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
99585 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99586 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
99587 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
99588 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
99589 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
99590 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99591 GIM_CheckIsSafeToFold, /*NumInsns*/1,
99592 // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
99593 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
99594 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
99595 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
99596 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
99597 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
99598 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
99599 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
99600 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
99601 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
99602 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99603 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99604 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
99605 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
99606 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
99607 GIR_RootConstrainSelectedInstOperands,
99608 // GIR_Coverage, 5673,
99609 GIR_EraseRootFromParent_Done,
99610 // Label 5622: @266124
99611 GIM_Try, /*On fail goto*//*Label 5623*/ GIMT_Encode4(266174), // Rule ID 1297 //
99612 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
99613 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99614 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
99615 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
99616 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
99617 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99618 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99619 GIM_CheckIsSafeToFold, /*NumInsns*/1,
99620 // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rd) => (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
99621 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f32),
99622 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99623 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99624 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
99625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
99626 GIR_RootConstrainSelectedInstOperands,
99627 // GIR_Coverage, 1297,
99628 GIR_EraseRootFromParent_Done,
99629 // Label 5623: @266174
99630 GIM_Try, /*On fail goto*//*Label 5624*/ GIMT_Encode4(266207), // Rule ID 1287 //
99631 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
99632 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99633 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99634 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99635 // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLAv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
99636 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4f32),
99637 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99638 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99639 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
99640 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
99641 GIR_RootConstrainSelectedInstOperands,
99642 // GIR_Coverage, 1287,
99643 GIR_EraseRootFromParent_Done,
99644 // Label 5624: @266207
99645 GIM_Reject,
99646 // Label 5605: @266208
99647 GIM_Reject,
99648 // Label 5474: @266209
99649 GIM_Try, /*On fail goto*//*Label 5625*/ GIMT_Encode4(267387),
99650 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
99651 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
99652 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
99653 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99654 GIM_Try, /*On fail goto*//*Label 5626*/ GIMT_Encode4(266311), // Rule ID 5709 //
99655 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
99656 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99657 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
99658 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
99659 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
99660 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
99661 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
99662 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
99663 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
99664 // MIs[2] Operand 1
99665 // No operand predicates
99666 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
99667 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
99668 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
99669 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99670 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99671 GIM_CheckIsSafeToFold, /*NumInsns*/3,
99672 // (fma:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
99673 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
99674 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99675 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
99677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
99678 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
99679 GIR_RootConstrainSelectedInstOperands,
99680 // GIR_Coverage, 5709,
99681 GIR_EraseRootFromParent_Done,
99682 // Label 5626: @266311
99683 GIM_Try, /*On fail goto*//*Label 5627*/ GIMT_Encode4(266392), // Rule ID 5735 //
99684 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
99685 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99686 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
99687 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
99688 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
99689 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
99690 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
99691 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
99692 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
99693 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
99694 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
99695 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
99696 // MIs[3] Operand 1
99697 // No operand predicates
99698 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99699 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99700 GIM_CheckIsSafeToFold, /*NumInsns*/3,
99701 // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
99702 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
99703 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99704 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99705 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
99706 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
99707 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
99708 GIR_RootConstrainSelectedInstOperands,
99709 // GIR_Coverage, 5735,
99710 GIR_EraseRootFromParent_Done,
99711 // Label 5627: @266392
99712 GIM_Try, /*On fail goto*//*Label 5628*/ GIMT_Encode4(266476), // Rule ID 5761 //
99713 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
99714 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99715 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
99716 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
99717 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99718 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
99719 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
99720 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
99721 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
99722 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
99723 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
99724 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
99725 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
99726 // MIs[3] Operand 1
99727 // No operand predicates
99728 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99729 GIM_CheckIsSafeToFold, /*NumInsns*/3,
99730 // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
99731 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
99732 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99733 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
99735 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
99736 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
99737 GIR_RootConstrainSelectedInstOperands,
99738 // GIR_Coverage, 5761,
99739 GIR_EraseRootFromParent_Done,
99740 // Label 5628: @266476
99741 GIM_Try, /*On fail goto*//*Label 5629*/ GIMT_Encode4(266557), // Rule ID 5683 //
99742 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
99743 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99744 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
99745 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
99746 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
99747 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
99748 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
99749 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
99750 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
99751 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
99752 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
99753 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
99754 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
99755 // MIs[3] Operand 1
99756 // No operand predicates
99757 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99758 GIM_CheckIsSafeToFold, /*NumInsns*/3,
99759 // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
99760 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
99761 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99762 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99763 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
99764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
99765 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
99766 GIR_RootConstrainSelectedInstOperands,
99767 // GIR_Coverage, 5683,
99768 GIR_EraseRootFromParent_Done,
99769 // Label 5629: @266557
99770 GIM_Try, /*On fail goto*//*Label 5630*/ GIMT_Encode4(266626), // Rule ID 2444 //
99771 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
99772 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99773 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
99774 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
99775 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
99776 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
99777 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
99778 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
99779 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
99780 // MIs[2] Operand 1
99781 // No operand predicates
99782 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99783 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99784 GIM_CheckIsSafeToFold, /*NumInsns*/2,
99785 // (fma:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
99786 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
99787 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99788 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99789 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
99790 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
99791 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
99792 GIR_RootConstrainSelectedInstOperands,
99793 // GIR_Coverage, 2444,
99794 GIR_EraseRootFromParent_Done,
99795 // Label 5630: @266626
99796 GIM_Try, /*On fail goto*//*Label 5631*/ GIMT_Encode4(266695), // Rule ID 5657 //
99797 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
99798 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99799 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
99800 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
99801 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
99802 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
99803 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
99804 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
99805 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
99806 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
99807 // MIs[2] Operand 1
99808 // No operand predicates
99809 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99810 GIM_CheckIsSafeToFold, /*NumInsns*/2,
99811 // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
99812 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
99813 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99814 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99815 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
99816 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
99817 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
99818 GIR_RootConstrainSelectedInstOperands,
99819 // GIR_Coverage, 5657,
99820 GIR_EraseRootFromParent_Done,
99821 // Label 5631: @266695
99822 GIM_Try, /*On fail goto*//*Label 5632*/ GIMT_Encode4(266794), // Rule ID 5711 //
99823 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
99824 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99825 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
99826 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
99827 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
99828 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
99829 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
99830 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
99831 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99832 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99833 GIM_CheckIsSafeToFold, /*NumInsns*/2,
99834 // (fma:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
99835 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
99836 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
99837 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
99838 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
99839 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
99840 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
99841 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
99842 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
99843 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
99844 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99845 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99846 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
99847 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
99848 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
99849 GIR_RootConstrainSelectedInstOperands,
99850 // GIR_Coverage, 5711,
99851 GIR_EraseRootFromParent_Done,
99852 // Label 5632: @266794
99853 GIM_Try, /*On fail goto*//*Label 5633*/ GIMT_Encode4(266890), // Rule ID 5737 //
99854 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
99855 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99856 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
99857 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
99858 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
99859 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
99860 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
99861 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
99862 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99863 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99864 GIM_CheckIsSafeToFold, /*NumInsns*/2,
99865 // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
99866 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
99867 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
99868 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
99869 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
99870 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
99871 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
99872 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
99873 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
99874 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
99875 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99876 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99877 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
99878 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
99879 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
99880 GIR_RootConstrainSelectedInstOperands,
99881 // GIR_Coverage, 5737,
99882 GIR_EraseRootFromParent_Done,
99883 // Label 5633: @266890
99884 GIM_Try, /*On fail goto*//*Label 5634*/ GIMT_Encode4(266989), // Rule ID 5763 //
99885 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
99886 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99887 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
99888 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
99889 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99890 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
99891 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
99892 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
99893 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
99894 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99895 GIM_CheckIsSafeToFold, /*NumInsns*/2,
99896 // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
99897 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
99898 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
99899 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
99900 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
99901 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
99902 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
99903 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
99904 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
99905 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
99906 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99907 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
99909 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
99910 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
99911 GIR_RootConstrainSelectedInstOperands,
99912 // GIR_Coverage, 5763,
99913 GIR_EraseRootFromParent_Done,
99914 // Label 5634: @266989
99915 GIM_Try, /*On fail goto*//*Label 5635*/ GIMT_Encode4(267085), // Rule ID 5685 //
99916 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
99917 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99918 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
99919 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
99920 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
99921 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
99922 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
99923 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
99924 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
99925 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99926 GIM_CheckIsSafeToFold, /*NumInsns*/2,
99927 // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
99928 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
99929 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
99930 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
99931 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
99932 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
99933 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
99934 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
99935 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
99936 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
99937 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99938 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99939 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
99940 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
99941 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
99942 GIR_RootConstrainSelectedInstOperands,
99943 // GIR_Coverage, 5685,
99944 GIR_EraseRootFromParent_Done,
99945 // Label 5635: @267085
99946 GIM_Try, /*On fail goto*//*Label 5636*/ GIMT_Encode4(267169), // Rule ID 2446 //
99947 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
99948 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99949 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
99950 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
99951 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
99952 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99953 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99954 GIM_CheckIsSafeToFold, /*NumInsns*/1,
99955 // (fma:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
99956 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
99957 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
99958 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
99959 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
99960 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
99961 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
99962 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
99963 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
99964 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
99965 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99966 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99967 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
99968 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
99969 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
99970 GIR_RootConstrainSelectedInstOperands,
99971 // GIR_Coverage, 2446,
99972 GIR_EraseRootFromParent_Done,
99973 // Label 5636: @267169
99974 GIM_Try, /*On fail goto*//*Label 5637*/ GIMT_Encode4(267219), // Rule ID 12579 //
99975 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
99976 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
99977 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
99978 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
99979 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99980 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99981 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99982 GIM_CheckIsSafeToFold, /*NumInsns*/1,
99983 // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
99984 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8f16),
99985 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
99986 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
99987 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
99988 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
99989 GIR_RootConstrainSelectedInstOperands,
99990 // GIR_Coverage, 12579,
99991 GIR_EraseRootFromParent_Done,
99992 // Label 5637: @267219
99993 GIM_Try, /*On fail goto*//*Label 5638*/ GIMT_Encode4(267303), // Rule ID 5659 //
99994 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
99995 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
99996 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
99997 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
99998 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
99999 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
100000 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100001 GIM_CheckIsSafeToFold, /*NumInsns*/1,
100002 // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
100003 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
100004 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
100005 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100006 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
100007 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
100008 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
100009 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
100010 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
100011 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
100012 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
100013 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
100014 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
100015 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
100016 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
100017 GIR_RootConstrainSelectedInstOperands,
100018 // GIR_Coverage, 5659,
100019 GIR_EraseRootFromParent_Done,
100020 // Label 5638: @267303
100021 GIM_Try, /*On fail goto*//*Label 5639*/ GIMT_Encode4(267353), // Rule ID 1293 //
100022 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
100023 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100024 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
100025 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
100026 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
100027 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100028 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100029 GIM_CheckIsSafeToFold, /*NumInsns*/1,
100030 // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rd) => (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
100031 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8f16),
100032 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
100033 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
100034 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
100035 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
100036 GIR_RootConstrainSelectedInstOperands,
100037 // GIR_Coverage, 1293,
100038 GIR_EraseRootFromParent_Done,
100039 // Label 5639: @267353
100040 GIM_Try, /*On fail goto*//*Label 5640*/ GIMT_Encode4(267386), // Rule ID 1283 //
100041 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
100042 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100043 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100044 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100045 // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLAv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
100046 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8f16),
100047 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
100048 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
100049 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
100050 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
100051 GIR_RootConstrainSelectedInstOperands,
100052 // GIR_Coverage, 1283,
100053 GIR_EraseRootFromParent_Done,
100054 // Label 5640: @267386
100055 GIM_Reject,
100056 // Label 5625: @267387
100057 GIM_Reject,
100058 // Label 5475: @267388
100059 GIM_Reject,
100060 // Label 57: @267389
100061 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 5649*/ GIMT_Encode4(269281),
100062 /*GILLT_s16*//*Label 5641*/ GIMT_Encode4(267440),
100063 /*GILLT_s32*//*Label 5642*/ GIMT_Encode4(267478),
100064 /*GILLT_s64*//*Label 5643*/ GIMT_Encode4(267516), GIMT_Encode4(0),
100065 /*GILLT_v2s32*//*Label 5644*/ GIMT_Encode4(267554),
100066 /*GILLT_v2s64*//*Label 5645*/ GIMT_Encode4(267592),
100067 /*GILLT_v4s16*//*Label 5646*/ GIMT_Encode4(267630),
100068 /*GILLT_v4s32*//*Label 5647*/ GIMT_Encode4(267668), GIMT_Encode4(0),
100069 /*GILLT_v8s16*//*Label 5648*/ GIMT_Encode4(267706),
100070 // Label 5641: @267440
100071 GIM_Try, /*On fail goto*//*Label 5650*/ GIMT_Encode4(267477), // Rule ID 584 //
100072 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
100073 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
100074 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
100075 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100076 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100077 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100078 // (fdiv:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FDIVHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
100079 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVHrr),
100080 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
100081 GIR_RootConstrainSelectedInstOperands,
100082 // GIR_Coverage, 584,
100083 GIR_Done,
100084 // Label 5650: @267477
100085 GIM_Reject,
100086 // Label 5642: @267478
100087 GIM_Try, /*On fail goto*//*Label 5651*/ GIMT_Encode4(267515), // Rule ID 586 //
100088 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
100089 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
100090 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
100091 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
100092 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
100093 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
100094 // (fdiv:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FDIVSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
100095 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVSrr),
100096 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
100097 GIR_RootConstrainSelectedInstOperands,
100098 // GIR_Coverage, 586,
100099 GIR_Done,
100100 // Label 5651: @267515
100101 GIM_Reject,
100102 // Label 5643: @267516
100103 GIM_Try, /*On fail goto*//*Label 5652*/ GIMT_Encode4(267553), // Rule ID 588 //
100104 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
100105 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
100106 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
100107 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
100108 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
100109 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
100110 // (fdiv:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FDIVDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
100111 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVDrr),
100112 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
100113 GIR_RootConstrainSelectedInstOperands,
100114 // GIR_Coverage, 588,
100115 GIR_Done,
100116 // Label 5652: @267553
100117 GIM_Reject,
100118 // Label 5644: @267554
100119 GIM_Try, /*On fail goto*//*Label 5653*/ GIMT_Encode4(267591), // Rule ID 1215 //
100120 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
100121 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
100122 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
100123 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
100124 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
100125 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
100126 // (fdiv:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FDIVv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
100127 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv2f32),
100128 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
100129 GIR_RootConstrainSelectedInstOperands,
100130 // GIR_Coverage, 1215,
100131 GIR_Done,
100132 // Label 5653: @267591
100133 GIM_Reject,
100134 // Label 5645: @267592
100135 GIM_Try, /*On fail goto*//*Label 5654*/ GIMT_Encode4(267629), // Rule ID 1219 //
100136 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
100137 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
100138 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
100139 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100140 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100141 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100142 // (fdiv:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FDIVv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
100143 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv2f64),
100144 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
100145 GIR_RootConstrainSelectedInstOperands,
100146 // GIR_Coverage, 1219,
100147 GIR_Done,
100148 // Label 5654: @267629
100149 GIM_Reject,
100150 // Label 5646: @267630
100151 GIM_Try, /*On fail goto*//*Label 5655*/ GIMT_Encode4(267667), // Rule ID 1211 //
100152 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
100153 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
100154 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
100155 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
100156 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
100157 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
100158 // (fdiv:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FDIVv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
100159 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f16),
100160 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
100161 GIR_RootConstrainSelectedInstOperands,
100162 // GIR_Coverage, 1211,
100163 GIR_Done,
100164 // Label 5655: @267667
100165 GIM_Reject,
100166 // Label 5647: @267668
100167 GIM_Try, /*On fail goto*//*Label 5656*/ GIMT_Encode4(267705), // Rule ID 1217 //
100168 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
100169 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
100170 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
100171 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100172 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100173 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100174 // (fdiv:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FDIVv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
100175 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
100176 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
100177 GIR_RootConstrainSelectedInstOperands,
100178 // GIR_Coverage, 1217,
100179 GIR_Done,
100180 // Label 5656: @267705
100181 GIM_Reject,
100182 // Label 5648: @267706
100183 GIM_Try, /*On fail goto*//*Label 5657*/ GIMT_Encode4(269280),
100184 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
100185 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
100186 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100187 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100188 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100189 GIM_Try, /*On fail goto*//*Label 5658*/ GIMT_Encode4(267748), // Rule ID 1213 //
100190 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
100191 // (fdiv:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FDIVv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
100192 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv8f16),
100193 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
100194 GIR_RootConstrainSelectedInstOperands,
100195 // GIR_Coverage, 1213,
100196 GIR_Done,
100197 // Label 5658: @267748
100198 GIM_Try, /*On fail goto*//*Label 5659*/ GIMT_Encode4(268002), // Rule ID 6722 //
100199 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
100200 // (fdiv:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FDIVv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FDIVv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
100201 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
100202 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
100203 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
100204 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
100205 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
100206 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
100207 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
100208 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
100209 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
100210 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
100211 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
100212 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
100213 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100214 GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
100215 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
100216 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
100217 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100218 GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
100219 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
100220 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
100221 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100222 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
100223 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
100224 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
100225 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100226 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100227 GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
100228 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
100229 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
100230 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
100231 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100232 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
100233 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
100234 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100235 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100236 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
100237 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
100238 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
100239 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
100240 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100241 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
100242 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
100243 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
100244 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100245 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
100246 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
100247 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
100248 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
100249 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100250 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
100251 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
100252 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
100253 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100254 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
100255 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
100256 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100257 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
100258 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
100259 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
100260 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
100261 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
100262 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
100263 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
100264 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
100265 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
100266 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
100267 GIR_RootConstrainSelectedInstOperands,
100268 // GIR_Coverage, 6722,
100269 GIR_EraseRootFromParent_Done,
100270 // Label 5659: @268002
100271 GIM_Try, /*On fail goto*//*Label 5660*/ GIMT_Encode4(268206), // Rule ID 6724 //
100272 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16),
100273 // (fdiv:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFCVTN2:{ *:[v8bf16] } (BFCVTN:{ *:[v8bf16] } (FDIVv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] })))), (FDIVv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)))
100274 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
100275 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
100276 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
100277 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
100278 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
100279 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
100280 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
100281 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
100282 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
100283 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
100284 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100285 GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/0, /*OpIdx*/2, // Rm
100286 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
100287 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
100288 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100289 GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
100290 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
100291 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
100292 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100293 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
100294 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/8,
100295 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
100296 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100297 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100298 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
100299 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
100300 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
100301 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
100302 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100303 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
100304 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
100305 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100306 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100307 GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
100308 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
100309 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
100310 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
100311 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100312 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
100313 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
100314 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
100315 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100316 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
100317 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/4,
100318 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
100319 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN),
100320 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100321 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
100322 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
100323 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN2),
100324 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
100325 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
100326 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
100327 GIR_RootConstrainSelectedInstOperands,
100328 // GIR_Coverage, 6724,
100329 GIR_EraseRootFromParent_Done,
100330 // Label 5660: @268206
100331 GIM_Try, /*On fail goto*//*Label 5661*/ GIMT_Encode4(269279), // Rule ID 6726 //
100332 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoBF16),
100333 // (fdiv:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (UZP2v8i16:{ *:[v8bf16] } (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FDIVv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), (FDIVv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] })))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FDIVv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FDIVv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), 64:{ *:[i32] }, 16:{ *:[i32] })), (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FDIVv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), (FDIVv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FDIVv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FDIVv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), 64:{ *:[i32] }, 16:{ *:[i32] })))
100334 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
100335 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
100336 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
100337 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
100338 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
100339 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
100340 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
100341 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
100342 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
100343 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s16,
100344 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
100345 GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_v4s16,
100346 GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_s128,
100347 GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s128,
100348 GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_v4s32,
100349 GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_v4s32,
100350 GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_v4s16,
100351 GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_v4s32,
100352 GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_v4s16,
100353 GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_s128,
100354 GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_s128,
100355 GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s128,
100356 GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s128,
100357 GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_s128,
100358 GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_v4s32,
100359 GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_v4s32,
100360 GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_v4s16,
100361 GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_v4s32,
100362 GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_v4s16,
100363 GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_s128,
100364 GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_s128,
100365 GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_v4s32,
100366 GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_v4s32,
100367 GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_v4s32,
100368 GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_v4s32,
100369 GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_v4s32,
100370 GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_v4s32,
100371 GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_s128,
100372 GIR_MakeTempReg, /*TempRegID*/38, /*TypeID*/GILLT_s128,
100373 GIR_MakeTempReg, /*TempRegID*/39, /*TypeID*/GILLT_v4s32,
100374 GIR_MakeTempReg, /*TempRegID*/40, /*TypeID*/GILLT_v4s32,
100375 GIR_MakeTempReg, /*TempRegID*/41, /*TypeID*/GILLT_v4s32,
100376 GIR_MakeTempReg, /*TempRegID*/42, /*TypeID*/GILLT_s128,
100377 GIR_MakeTempReg, /*TempRegID*/43, /*TypeID*/GILLT_s128,
100378 GIR_MakeTempReg, /*TempRegID*/44, /*TypeID*/GILLT_s128,
100379 GIR_MakeTempReg, /*TempRegID*/45, /*TypeID*/GILLT_s128,
100380 GIR_MakeTempReg, /*TempRegID*/46, /*TypeID*/GILLT_s128,
100381 GIR_MakeTempReg, /*TempRegID*/47, /*TypeID*/GILLT_v4s32,
100382 GIR_MakeTempReg, /*TempRegID*/48, /*TypeID*/GILLT_v4s32,
100383 GIR_MakeTempReg, /*TempRegID*/49, /*TypeID*/GILLT_v4s32,
100384 GIR_BuildMI, /*InsnID*/50, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
100385 GIR_AddTempRegister, /*InsnID*/50, /*TempRegID*/49, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100386 GIR_Copy, /*NewInsnID*/50, /*OldInsnID*/0, /*OpIdx*/2, // Rm
100387 GIR_ConstrainSelectedInstOperands, /*InsnID*/50,
100388 GIR_BuildMI, /*InsnID*/49, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
100389 GIR_AddTempRegister, /*InsnID*/49, /*TempRegID*/48, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100390 GIR_Copy, /*NewInsnID*/49, /*OldInsnID*/0, /*OpIdx*/1, // Rn
100391 GIR_ConstrainSelectedInstOperands, /*InsnID*/49,
100392 GIR_BuildMI, /*InsnID*/48, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
100393 GIR_AddTempRegister, /*InsnID*/48, /*TempRegID*/47, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100394 GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/48,
100395 GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/49,
100396 GIR_ConstrainSelectedInstOperands, /*InsnID*/48,
100397 GIR_BuildMI, /*InsnID*/47, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
100398 GIR_AddTempRegister, /*InsnID*/47, /*TempRegID*/46, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100399 GIR_AddSimpleTempRegister, /*InsnID*/47, /*TempRegID*/47,
100400 GIR_AddImm8, /*InsnID*/47, /*Imm*/64,
100401 GIR_AddImm8, /*InsnID*/47, /*Imm*/16,
100402 GIR_ConstrainSelectedInstOperands, /*InsnID*/47,
100403 GIR_BuildMI, /*InsnID*/46, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
100404 GIR_AddTempRegister, /*InsnID*/46, /*TempRegID*/45, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100405 GIR_AddImm8, /*InsnID*/46, /*Imm*/127,
100406 GIR_AddImm, /*InsnID*/46, /*Imm*/GIMT_Encode8(264),
100407 GIR_ConstrainSelectedInstOperands, /*InsnID*/46,
100408 GIR_BuildMI, /*InsnID*/45, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
100409 GIR_AddTempRegister, /*InsnID*/45, /*TempRegID*/44, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100410 GIR_AddImm8, /*InsnID*/45, /*Imm*/1,
100411 GIR_AddImm8, /*InsnID*/45, /*Imm*/0,
100412 GIR_ConstrainSelectedInstOperands, /*InsnID*/45,
100413 GIR_BuildMI, /*InsnID*/44, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
100414 GIR_AddTempRegister, /*InsnID*/44, /*TempRegID*/43, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100415 GIR_Copy, /*NewInsnID*/44, /*OldInsnID*/0, /*OpIdx*/1, // Rn
100416 GIR_AddImm8, /*InsnID*/44, /*Imm*/16,
100417 GIR_ConstrainSelectedInstOperands, /*InsnID*/44,
100418 GIR_BuildMI, /*InsnID*/43, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
100419 GIR_AddTempRegister, /*InsnID*/43, /*TempRegID*/42, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100420 GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/43,
100421 GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/44,
100422 GIR_ConstrainSelectedInstOperands, /*InsnID*/43,
100423 GIR_BuildMI, /*InsnID*/42, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
100424 GIR_AddTempRegister, /*InsnID*/42, /*TempRegID*/41, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100425 GIR_Copy, /*NewInsnID*/42, /*OldInsnID*/0, /*OpIdx*/2, // Rm
100426 GIR_ConstrainSelectedInstOperands, /*InsnID*/42,
100427 GIR_BuildMI, /*InsnID*/41, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
100428 GIR_AddTempRegister, /*InsnID*/41, /*TempRegID*/40, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100429 GIR_Copy, /*NewInsnID*/41, /*OldInsnID*/0, /*OpIdx*/1, // Rn
100430 GIR_ConstrainSelectedInstOperands, /*InsnID*/41,
100431 GIR_BuildMI, /*InsnID*/40, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
100432 GIR_AddTempRegister, /*InsnID*/40, /*TempRegID*/39, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100433 GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/40,
100434 GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/41,
100435 GIR_ConstrainSelectedInstOperands, /*InsnID*/40,
100436 GIR_BuildMI, /*InsnID*/39, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
100437 GIR_AddTempRegister, /*InsnID*/39, /*TempRegID*/38, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100438 GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/39,
100439 GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/42,
100440 GIR_ConstrainSelectedInstOperands, /*InsnID*/39,
100441 GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
100442 GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100443 GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/38,
100444 GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/45,
100445 GIR_ConstrainSelectedInstOperands, /*InsnID*/38,
100446 GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
100447 GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100448 GIR_Copy, /*NewInsnID*/37, /*OldInsnID*/0, /*OpIdx*/2, // Rm
100449 GIR_ConstrainSelectedInstOperands, /*InsnID*/37,
100450 GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
100451 GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100452 GIR_Copy, /*NewInsnID*/36, /*OldInsnID*/0, /*OpIdx*/1, // Rn
100453 GIR_ConstrainSelectedInstOperands, /*InsnID*/36,
100454 GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
100455 GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100456 GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/35,
100457 GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/36,
100458 GIR_ConstrainSelectedInstOperands, /*InsnID*/35,
100459 GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
100460 GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100461 GIR_Copy, /*NewInsnID*/34, /*OldInsnID*/0, /*OpIdx*/2, // Rm
100462 GIR_ConstrainSelectedInstOperands, /*InsnID*/34,
100463 GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
100464 GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100465 GIR_Copy, /*NewInsnID*/33, /*OldInsnID*/0, /*OpIdx*/1, // Rn
100466 GIR_ConstrainSelectedInstOperands, /*InsnID*/33,
100467 GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
100468 GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100469 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/32,
100470 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/33,
100471 GIR_ConstrainSelectedInstOperands, /*InsnID*/32,
100472 GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
100473 GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100474 GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/31,
100475 GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/34,
100476 GIR_ConstrainSelectedInstOperands, /*InsnID*/31,
100477 GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
100478 GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100479 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/30,
100480 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/37,
100481 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/46,
100482 GIR_ConstrainSelectedInstOperands, /*InsnID*/30,
100483 GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100484 GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100485 GIR_CopySubReg, /*NewInsnID*/29, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
100486 GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
100487 GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
100488 GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
100489 GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100490 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/28,
100491 GIR_ConstrainSelectedInstOperands, /*InsnID*/28,
100492 GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100493 GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100494 GIR_CopySubReg, /*NewInsnID*/27, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
100495 GIR_ConstrainOperandRC, /*InsnID*/27, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
100496 GIR_ConstrainOperandRC, /*InsnID*/27, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
100497 GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
100498 GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100499 GIR_AddSimpleTempRegister, /*InsnID*/26, /*TempRegID*/26,
100500 GIR_ConstrainSelectedInstOperands, /*InsnID*/26,
100501 GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
100502 GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100503 GIR_AddSimpleTempRegister, /*InsnID*/25, /*TempRegID*/25,
100504 GIR_AddSimpleTempRegister, /*InsnID*/25, /*TempRegID*/27,
100505 GIR_ConstrainSelectedInstOperands, /*InsnID*/25,
100506 GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
100507 GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100508 GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/24,
100509 GIR_AddImm8, /*InsnID*/24, /*Imm*/64,
100510 GIR_AddImm8, /*InsnID*/24, /*Imm*/16,
100511 GIR_ConstrainSelectedInstOperands, /*InsnID*/24,
100512 GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
100513 GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100514 GIR_AddImm8, /*InsnID*/23, /*Imm*/127,
100515 GIR_AddImm, /*InsnID*/23, /*Imm*/GIMT_Encode8(264),
100516 GIR_ConstrainSelectedInstOperands, /*InsnID*/23,
100517 GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
100518 GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100519 GIR_AddImm8, /*InsnID*/22, /*Imm*/1,
100520 GIR_AddImm8, /*InsnID*/22, /*Imm*/0,
100521 GIR_ConstrainSelectedInstOperands, /*InsnID*/22,
100522 GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
100523 GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100524 GIR_Copy, /*NewInsnID*/21, /*OldInsnID*/0, /*OpIdx*/1, // Rn
100525 GIR_AddImm8, /*InsnID*/21, /*Imm*/16,
100526 GIR_ConstrainSelectedInstOperands, /*InsnID*/21,
100527 GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
100528 GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100529 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/20,
100530 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/21,
100531 GIR_ConstrainSelectedInstOperands, /*InsnID*/20,
100532 GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100533 GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100534 GIR_CopySubReg, /*NewInsnID*/19, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
100535 GIR_ConstrainOperandRC, /*InsnID*/19, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
100536 GIR_ConstrainOperandRC, /*InsnID*/19, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
100537 GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
100538 GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100539 GIR_AddSimpleTempRegister, /*InsnID*/18, /*TempRegID*/18,
100540 GIR_ConstrainSelectedInstOperands, /*InsnID*/18,
100541 GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100542 GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100543 GIR_CopySubReg, /*NewInsnID*/17, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
100544 GIR_ConstrainOperandRC, /*InsnID*/17, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
100545 GIR_ConstrainOperandRC, /*InsnID*/17, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
100546 GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
100547 GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100548 GIR_AddSimpleTempRegister, /*InsnID*/16, /*TempRegID*/16,
100549 GIR_ConstrainSelectedInstOperands, /*InsnID*/16,
100550 GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
100551 GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100552 GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/15,
100553 GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/17,
100554 GIR_ConstrainSelectedInstOperands, /*InsnID*/15,
100555 GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
100556 GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100557 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14,
100558 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/19,
100559 GIR_ConstrainSelectedInstOperands, /*InsnID*/14,
100560 GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
100561 GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100562 GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/13,
100563 GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/22,
100564 GIR_ConstrainSelectedInstOperands, /*InsnID*/13,
100565 GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100566 GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100567 GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
100568 GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
100569 GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
100570 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
100571 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100572 GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11,
100573 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
100574 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100575 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100576 GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
100577 GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
100578 GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
100579 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
100580 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100581 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
100582 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
100583 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
100584 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100585 GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
100586 GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/10,
100587 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
100588 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100589 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100590 GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
100591 GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
100592 GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
100593 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
100594 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100595 GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
100596 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
100597 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100598 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100599 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
100600 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
100601 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
100602 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
100603 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100604 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
100605 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
100606 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
100607 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100608 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
100609 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/5,
100610 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
100611 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
100612 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100613 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
100614 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/7,
100615 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
100616 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
100617 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100618 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
100619 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/12,
100620 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/23,
100621 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
100622 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
100623 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
100624 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
100625 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/29,
100626 GIR_RootConstrainSelectedInstOperands,
100627 // GIR_Coverage, 6726,
100628 GIR_EraseRootFromParent_Done,
100629 // Label 5661: @269279
100630 GIM_Reject,
100631 // Label 5657: @269280
100632 GIM_Reject,
100633 // Label 5649: @269281
100634 GIM_Reject,
100635 // Label 58: @269282
100636 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 5670*/ GIMT_Encode4(272107),
100637 /*GILLT_s16*//*Label 5662*/ GIMT_Encode4(269333),
100638 /*GILLT_s32*//*Label 5663*/ GIMT_Encode4(270358),
100639 /*GILLT_s64*//*Label 5664*/ GIMT_Encode4(271065), GIMT_Encode4(0),
100640 /*GILLT_v2s32*//*Label 5665*/ GIMT_Encode4(271772),
100641 /*GILLT_v2s64*//*Label 5666*/ GIMT_Encode4(271799),
100642 /*GILLT_v4s16*//*Label 5667*/ GIMT_Encode4(271826),
100643 /*GILLT_v4s32*//*Label 5668*/ GIMT_Encode4(271953), GIMT_Encode4(0),
100644 /*GILLT_v8s16*//*Label 5669*/ GIMT_Encode4(271980),
100645 // Label 5662: @269333
100646 GIM_Try, /*On fail goto*//*Label 5671*/ GIMT_Encode4(270357),
100647 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
100648 GIM_Try, /*On fail goto*//*Label 5672*/ GIMT_Encode4(269456), // Rule ID 4515 //
100649 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
100650 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100651 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
100652 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
100653 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
100654 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
100655 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
100656 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
100657 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
100658 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
100659 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
100660 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100661 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
100662 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100663 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100664 GIM_CheckIsSafeToFold, /*NumInsns*/2,
100665 // (fneg:{ *:[f16] } (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)) => (FNMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
100666 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
100667 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100668 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100669 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
100670 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
100671 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
100672 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
100673 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
100674 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
100675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
100676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
100677 GIR_RootConstrainSelectedInstOperands,
100678 // GIR_Coverage, 4515,
100679 GIR_EraseRootFromParent_Done,
100680 // Label 5672: @269456
100681 GIM_Try, /*On fail goto*//*Label 5673*/ GIMT_Encode4(269571), // Rule ID 4513 //
100682 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
100683 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100684 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
100685 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
100686 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
100687 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
100688 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
100689 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100690 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
100691 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
100692 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
100693 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
100694 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100695 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
100696 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100697 GIM_CheckIsSafeToFold, /*NumInsns*/2,
100698 // (fneg:{ *:[f16] } (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra)) => (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
100699 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
100700 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100701 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100702 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rm
100703 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
100704 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
100705 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
100706 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
100707 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
100708 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
100709 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
100710 GIR_RootConstrainSelectedInstOperands,
100711 // GIR_Coverage, 4513,
100712 GIR_EraseRootFromParent_Done,
100713 // Label 5673: @269571
100714 GIM_Try, /*On fail goto*//*Label 5674*/ GIMT_Encode4(269686), // Rule ID 4514 //
100715 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
100716 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100717 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
100718 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
100719 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
100720 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
100721 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
100722 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
100723 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
100724 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
100725 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
100726 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100727 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
100728 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100729 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100730 GIM_CheckIsSafeToFold, /*NumInsns*/2,
100731 // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)) => (FNMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
100732 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
100733 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100734 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100735 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
100736 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
100737 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
100738 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
100739 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
100740 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
100741 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
100742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
100743 GIR_RootConstrainSelectedInstOperands,
100744 // GIR_Coverage, 4514,
100745 GIR_EraseRootFromParent_Done,
100746 // Label 5674: @269686
100747 GIM_Try, /*On fail goto*//*Label 5675*/ GIMT_Encode4(269801), // Rule ID 4512 //
100748 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
100749 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100750 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
100751 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
100752 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
100753 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
100754 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
100755 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100756 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
100757 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
100758 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
100759 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
100760 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100761 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
100762 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100763 GIM_CheckIsSafeToFold, /*NumInsns*/2,
100764 // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra)) => (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
100765 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
100766 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100767 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100768 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rm
100769 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
100770 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
100771 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
100772 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
100773 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
100774 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
100775 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
100776 GIR_RootConstrainSelectedInstOperands,
100777 // GIR_Coverage, 4512,
100778 GIR_EraseRootFromParent_Done,
100779 // Label 5675: @269801
100780 GIM_Try, /*On fail goto*//*Label 5676*/ GIMT_Encode4(269869), // Rule ID 644 //
100781 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
100782 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100783 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
100784 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
100785 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
100786 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
100787 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
100788 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100789 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100790 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100791 GIM_CheckIsSafeToFold, /*NumInsns*/1,
100792 // (fneg:{ *:[f16] } (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)) => (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
100793 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
100794 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
100795 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
100796 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
100797 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
100798 GIR_RootConstrainSelectedInstOperands,
100799 // GIR_Coverage, 644,
100800 GIR_EraseRootFromParent_Done,
100801 // Label 5676: @269869
100802 GIM_Try, /*On fail goto*//*Label 5677*/ GIMT_Encode4(269937), // Rule ID 643 //
100803 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
100804 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100805 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
100806 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
100807 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
100808 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
100809 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
100810 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100811 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100812 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100813 GIM_CheckIsSafeToFold, /*NumInsns*/1,
100814 // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)) => (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
100815 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
100816 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
100817 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
100818 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
100819 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
100820 GIR_RootConstrainSelectedInstOperands,
100821 // GIR_Coverage, 643,
100822 GIR_EraseRootFromParent_Done,
100823 // Label 5677: @269937
100824 GIM_Try, /*On fail goto*//*Label 5678*/ GIMT_Encode4(269992), // Rule ID 620 //
100825 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
100826 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100827 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
100828 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
100829 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
100830 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
100831 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100832 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100833 GIM_CheckIsSafeToFold, /*NumInsns*/1,
100834 // (fneg:{ *:[f16] } (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)) => (FNMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
100835 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULHrr),
100836 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
100837 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
100838 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
100839 GIR_RootConstrainSelectedInstOperands,
100840 // GIR_Coverage, 620,
100841 GIR_EraseRootFromParent_Done,
100842 // Label 5678: @269992
100843 GIM_Try, /*On fail goto*//*Label 5679*/ GIMT_Encode4(270047), // Rule ID 619 //
100844 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
100845 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100846 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
100847 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
100848 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
100849 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
100850 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100851 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100852 GIM_CheckIsSafeToFold, /*NumInsns*/1,
100853 // (fneg:{ *:[f16] } (strict_fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)) => (FNMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
100854 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULHrr),
100855 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
100856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
100857 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
100858 GIR_RootConstrainSelectedInstOperands,
100859 // GIR_Coverage, 619,
100860 GIR_EraseRootFromParent_Done,
100861 // Label 5679: @270047
100862 GIM_Try, /*On fail goto*//*Label 5680*/ GIMT_Encode4(270070), // Rule ID 518 //
100863 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
100864 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100865 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100866 // (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FNEGHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
100867 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGHr),
100868 GIR_RootConstrainSelectedInstOperands,
100869 // GIR_Coverage, 518,
100870 GIR_Done,
100871 // Label 5680: @270070
100872 GIM_Try, /*On fail goto*//*Label 5681*/ GIMT_Encode4(270213), // Rule ID 5964 //
100873 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
100874 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100875 // (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } (EORWri:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] }), GPR32:{ *:[i32] }), (logical_imm32_XFORM:{ *:[i32] } 32768:{ *:[i32] })), FPR32:{ *:[i32] }), hsub:{ *:[i32] })
100876 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
100877 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
100878 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
100879 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
100880 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
100881 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
100882 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100883 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
100884 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
100885 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100886 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
100887 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
100888 GIR_AddImm8, /*InsnID*/4, /*Imm*/7,
100889 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
100890 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
100891 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
100892 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100893 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100894 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
100895 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
100896 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::EORWri),
100897 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100898 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
100899 GIR_CustomRenderer, /*InsnID*/2, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm32), //
100900 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
100901 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100902 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100903 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
100904 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
100905 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100906 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
100907 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
100908 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
100909 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
100910 // GIR_Coverage, 5964,
100911 GIR_EraseRootFromParent_Done,
100912 // Label 5681: @270213
100913 GIM_Try, /*On fail goto*//*Label 5682*/ GIMT_Encode4(270356), // Rule ID 5965 //
100914 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
100915 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
100916 // (fneg:{ *:[bf16] } FPR16:{ *:[bf16] }:$Rn) => (EXTRACT_SUBREG:{ *:[bf16] } (COPY_TO_REGCLASS:{ *:[f32] } (EORWri:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), FPR16:{ *:[bf16] }:$Rn, hsub:{ *:[i32] }), GPR32:{ *:[i32] }), (logical_imm32_XFORM:{ *:[i32] } 32768:{ *:[i32] })), FPR32:{ *:[i32] }), hsub:{ *:[i32] })
100917 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
100918 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
100919 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
100920 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
100921 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
100922 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
100923 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100924 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
100925 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
100926 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100927 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
100928 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
100929 GIR_AddImm8, /*InsnID*/4, /*Imm*/7,
100930 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
100931 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
100932 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
100933 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100934 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100935 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
100936 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
100937 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::EORWri),
100938 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100939 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
100940 GIR_CustomRenderer, /*InsnID*/2, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm32), //
100941 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
100942 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100943 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100944 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
100945 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
100946 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100947 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
100948 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
100949 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
100950 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
100951 // GIR_Coverage, 5965,
100952 GIR_EraseRootFromParent_Done,
100953 // Label 5682: @270356
100954 GIM_Reject,
100955 // Label 5671: @270357
100956 GIM_Reject,
100957 // Label 5663: @270358
100958 GIM_Try, /*On fail goto*//*Label 5683*/ GIMT_Encode4(271064),
100959 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
100960 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
100961 GIM_Try, /*On fail goto*//*Label 5684*/ GIMT_Encode4(270481), // Rule ID 4519 //
100962 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
100963 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
100964 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
100965 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
100966 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
100967 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
100968 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
100969 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
100970 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
100971 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
100972 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
100973 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
100974 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
100975 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
100976 GIM_CheckIsSafeToFold, /*NumInsns*/2,
100977 // (fneg:{ *:[f32] } (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
100978 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
100979 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
100980 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
100981 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rn
100982 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
100983 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
100984 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
100985 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
100986 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
100987 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
100988 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
100989 GIR_RootConstrainSelectedInstOperands,
100990 // GIR_Coverage, 4519,
100991 GIR_EraseRootFromParent_Done,
100992 // Label 5684: @270481
100993 GIM_Try, /*On fail goto*//*Label 5685*/ GIMT_Encode4(270592), // Rule ID 4517 //
100994 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
100995 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
100996 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
100997 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
100998 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
100999 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
101000 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101001 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
101002 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
101003 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
101004 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
101005 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
101006 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
101007 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101008 GIM_CheckIsSafeToFold, /*NumInsns*/2,
101009 // (fneg:{ *:[f32] } (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
101010 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
101011 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
101012 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
101013 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rm
101014 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
101015 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
101016 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
101017 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101018 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101019 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
101020 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
101021 GIR_RootConstrainSelectedInstOperands,
101022 // GIR_Coverage, 4517,
101023 GIR_EraseRootFromParent_Done,
101024 // Label 5685: @270592
101025 GIM_Try, /*On fail goto*//*Label 5686*/ GIMT_Encode4(270703), // Rule ID 4518 //
101026 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101027 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101028 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
101029 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
101030 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
101031 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
101032 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
101033 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
101034 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
101035 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
101036 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
101037 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
101038 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101039 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101040 GIM_CheckIsSafeToFold, /*NumInsns*/2,
101041 // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
101042 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
101043 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
101044 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
101045 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rn
101046 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
101047 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
101048 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
101049 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101050 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
101051 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
101052 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
101053 GIR_RootConstrainSelectedInstOperands,
101054 // GIR_Coverage, 4518,
101055 GIR_EraseRootFromParent_Done,
101056 // Label 5686: @270703
101057 GIM_Try, /*On fail goto*//*Label 5687*/ GIMT_Encode4(270814), // Rule ID 4516 //
101058 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101059 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101060 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
101061 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
101062 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
101063 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
101064 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101065 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
101066 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
101067 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
101068 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
101069 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
101070 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
101071 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101072 GIM_CheckIsSafeToFold, /*NumInsns*/2,
101073 // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
101074 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
101075 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
101076 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
101077 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rm
101078 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
101079 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
101080 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
101081 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101083 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
101084 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
101085 GIR_RootConstrainSelectedInstOperands,
101086 // GIR_Coverage, 4516,
101087 GIR_EraseRootFromParent_Done,
101088 // Label 5687: @270814
101089 GIM_Try, /*On fail goto*//*Label 5688*/ GIMT_Encode4(270878), // Rule ID 646 //
101090 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101091 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101092 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
101093 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
101094 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
101095 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
101096 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101097 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101098 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101099 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101100 // (fneg:{ *:[f32] } (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
101101 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
101102 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101103 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101104 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
101105 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
101106 GIR_RootConstrainSelectedInstOperands,
101107 // GIR_Coverage, 646,
101108 GIR_EraseRootFromParent_Done,
101109 // Label 5688: @270878
101110 GIM_Try, /*On fail goto*//*Label 5689*/ GIMT_Encode4(270942), // Rule ID 645 //
101111 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101112 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101113 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
101114 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
101115 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
101116 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
101117 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101118 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101119 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101120 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101121 // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)) => (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
101122 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
101123 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101124 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
101126 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
101127 GIR_RootConstrainSelectedInstOperands,
101128 // GIR_Coverage, 645,
101129 GIR_EraseRootFromParent_Done,
101130 // Label 5689: @270942
101131 GIM_Try, /*On fail goto*//*Label 5690*/ GIMT_Encode4(270993), // Rule ID 622 //
101132 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101133 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101134 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
101135 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
101136 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
101137 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101138 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101139 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101140 // (fneg:{ *:[f32] } (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)) => (FNMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
101141 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULSrr),
101142 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101144 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
101145 GIR_RootConstrainSelectedInstOperands,
101146 // GIR_Coverage, 622,
101147 GIR_EraseRootFromParent_Done,
101148 // Label 5690: @270993
101149 GIM_Try, /*On fail goto*//*Label 5691*/ GIMT_Encode4(271044), // Rule ID 621 //
101150 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101151 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101152 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
101153 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
101154 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
101155 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101156 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101157 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101158 // (fneg:{ *:[f32] } (strict_fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)) => (FNMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
101159 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULSrr),
101160 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101161 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
101163 GIR_RootConstrainSelectedInstOperands,
101164 // GIR_Coverage, 621,
101165 GIR_EraseRootFromParent_Done,
101166 // Label 5691: @271044
101167 GIM_Try, /*On fail goto*//*Label 5692*/ GIMT_Encode4(271063), // Rule ID 519 //
101168 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101169 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101170 // (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FNEGSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
101171 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGSr),
101172 GIR_RootConstrainSelectedInstOperands,
101173 // GIR_Coverage, 519,
101174 GIR_Done,
101175 // Label 5692: @271063
101176 GIM_Reject,
101177 // Label 5683: @271064
101178 GIM_Reject,
101179 // Label 5664: @271065
101180 GIM_Try, /*On fail goto*//*Label 5693*/ GIMT_Encode4(271771),
101181 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
101182 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101183 GIM_Try, /*On fail goto*//*Label 5694*/ GIMT_Encode4(271188), // Rule ID 4523 //
101184 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101185 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101186 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
101187 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
101188 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
101189 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
101190 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
101191 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
101192 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
101193 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
101194 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
101195 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
101196 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101197 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101198 GIM_CheckIsSafeToFold, /*NumInsns*/2,
101199 // (fneg:{ *:[f64] } (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
101200 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
101201 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
101202 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
101203 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
101204 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
101205 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
101206 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
101207 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101208 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
101209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
101210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
101211 GIR_RootConstrainSelectedInstOperands,
101212 // GIR_Coverage, 4523,
101213 GIR_EraseRootFromParent_Done,
101214 // Label 5694: @271188
101215 GIM_Try, /*On fail goto*//*Label 5695*/ GIMT_Encode4(271299), // Rule ID 4521 //
101216 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101217 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101218 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
101219 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
101220 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
101221 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
101222 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101223 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
101224 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
101225 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
101226 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
101227 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
101228 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
101229 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101230 GIM_CheckIsSafeToFold, /*NumInsns*/2,
101231 // (fneg:{ *:[f64] } (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
101232 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
101233 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
101234 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
101235 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rm
101236 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
101237 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
101238 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
101239 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101240 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101241 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
101242 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
101243 GIR_RootConstrainSelectedInstOperands,
101244 // GIR_Coverage, 4521,
101245 GIR_EraseRootFromParent_Done,
101246 // Label 5695: @271299
101247 GIM_Try, /*On fail goto*//*Label 5696*/ GIMT_Encode4(271410), // Rule ID 4522 //
101248 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101249 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101250 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
101251 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
101252 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
101253 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
101254 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
101255 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
101256 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
101257 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
101258 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
101259 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
101260 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101261 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101262 GIM_CheckIsSafeToFold, /*NumInsns*/2,
101263 // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
101264 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
101265 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
101266 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
101267 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
101268 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
101269 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
101270 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
101271 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101272 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
101273 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
101274 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
101275 GIR_RootConstrainSelectedInstOperands,
101276 // GIR_Coverage, 4522,
101277 GIR_EraseRootFromParent_Done,
101278 // Label 5696: @271410
101279 GIM_Try, /*On fail goto*//*Label 5697*/ GIMT_Encode4(271521), // Rule ID 4520 //
101280 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101281 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101282 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
101283 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
101284 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
101285 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
101286 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101287 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
101288 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
101289 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
101290 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
101291 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
101292 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
101293 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101294 GIM_CheckIsSafeToFold, /*NumInsns*/2,
101295 // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
101296 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
101297 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
101298 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
101299 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rm
101300 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
101301 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
101302 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
101303 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101304 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101305 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
101306 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
101307 GIR_RootConstrainSelectedInstOperands,
101308 // GIR_Coverage, 4520,
101309 GIR_EraseRootFromParent_Done,
101310 // Label 5697: @271521
101311 GIM_Try, /*On fail goto*//*Label 5698*/ GIMT_Encode4(271585), // Rule ID 648 //
101312 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101313 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101314 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
101315 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
101316 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
101317 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
101318 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101319 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101320 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101321 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101322 // (fneg:{ *:[f64] } (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
101323 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
101324 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
101327 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
101328 GIR_RootConstrainSelectedInstOperands,
101329 // GIR_Coverage, 648,
101330 GIR_EraseRootFromParent_Done,
101331 // Label 5698: @271585
101332 GIM_Try, /*On fail goto*//*Label 5699*/ GIMT_Encode4(271649), // Rule ID 647 //
101333 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101334 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101335 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
101336 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
101337 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
101338 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
101339 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101340 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101341 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101342 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101343 // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)) => (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
101344 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
101345 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101346 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101347 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
101348 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
101349 GIR_RootConstrainSelectedInstOperands,
101350 // GIR_Coverage, 647,
101351 GIR_EraseRootFromParent_Done,
101352 // Label 5699: @271649
101353 GIM_Try, /*On fail goto*//*Label 5700*/ GIMT_Encode4(271700), // Rule ID 624 //
101354 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101355 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101356 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
101357 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
101358 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
101359 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101360 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101361 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101362 // (fneg:{ *:[f64] } (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)) => (FNMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
101363 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULDrr),
101364 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
101367 GIR_RootConstrainSelectedInstOperands,
101368 // GIR_Coverage, 624,
101369 GIR_EraseRootFromParent_Done,
101370 // Label 5700: @271700
101371 GIM_Try, /*On fail goto*//*Label 5701*/ GIMT_Encode4(271751), // Rule ID 623 //
101372 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101373 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101374 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
101375 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
101376 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
101377 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101378 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101379 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101380 // (fneg:{ *:[f64] } (strict_fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)) => (FNMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
101381 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULDrr),
101382 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
101385 GIR_RootConstrainSelectedInstOperands,
101386 // GIR_Coverage, 623,
101387 GIR_EraseRootFromParent_Done,
101388 // Label 5701: @271751
101389 GIM_Try, /*On fail goto*//*Label 5702*/ GIMT_Encode4(271770), // Rule ID 520 //
101390 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101391 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101392 // (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FNEGDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
101393 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGDr),
101394 GIR_RootConstrainSelectedInstOperands,
101395 // GIR_Coverage, 520,
101396 GIR_Done,
101397 // Label 5702: @271770
101398 GIM_Reject,
101399 // Label 5693: @271771
101400 GIM_Reject,
101401 // Label 5665: @271772
101402 GIM_Try, /*On fail goto*//*Label 5703*/ GIMT_Encode4(271798), // Rule ID 847 //
101403 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
101404 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
101405 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101406 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101407 // (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FNEGv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
101408 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGv2f32),
101409 GIR_RootConstrainSelectedInstOperands,
101410 // GIR_Coverage, 847,
101411 GIR_Done,
101412 // Label 5703: @271798
101413 GIM_Reject,
101414 // Label 5666: @271799
101415 GIM_Try, /*On fail goto*//*Label 5704*/ GIMT_Encode4(271825), // Rule ID 849 //
101416 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
101417 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
101418 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
101419 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
101420 // (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FNEGv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
101421 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGv2f64),
101422 GIR_RootConstrainSelectedInstOperands,
101423 // GIR_Coverage, 849,
101424 GIR_Done,
101425 // Label 5704: @271825
101426 GIM_Reject,
101427 // Label 5667: @271826
101428 GIM_Try, /*On fail goto*//*Label 5705*/ GIMT_Encode4(271952),
101429 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
101430 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101431 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101432 GIM_Try, /*On fail goto*//*Label 5706*/ GIMT_Encode4(271857), // Rule ID 845 //
101433 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
101434 // (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FNEGv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
101435 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGv4f16),
101436 GIR_RootConstrainSelectedInstOperands,
101437 // GIR_Coverage, 845,
101438 GIR_Done,
101439 // Label 5706: @271857
101440 GIM_Try, /*On fail goto*//*Label 5707*/ GIMT_Encode4(271904), // Rule ID 5970 //
101441 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
101442 // (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (EORv8i8:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (MOVIv4i16:{ *:[i64] } 128:{ *:[i32] }, 8:{ *:[i32] }))
101443 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
101444 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i16),
101445 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
101446 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(128),
101447 GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
101448 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
101449 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORv8i8),
101450 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101451 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
101452 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
101453 GIR_RootConstrainSelectedInstOperands,
101454 // GIR_Coverage, 5970,
101455 GIR_EraseRootFromParent_Done,
101456 // Label 5707: @271904
101457 GIM_Try, /*On fail goto*//*Label 5708*/ GIMT_Encode4(271951), // Rule ID 5971 //
101458 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
101459 // (fneg:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn) => (EORv8i8:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, (MOVIv4i16:{ *:[v4i16] } 128:{ *:[i32] }, 8:{ *:[i32] }))
101460 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16,
101461 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i16),
101462 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
101463 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(128),
101464 GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
101465 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
101466 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORv8i8),
101467 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101468 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
101469 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
101470 GIR_RootConstrainSelectedInstOperands,
101471 // GIR_Coverage, 5971,
101472 GIR_EraseRootFromParent_Done,
101473 // Label 5708: @271951
101474 GIM_Reject,
101475 // Label 5705: @271952
101476 GIM_Reject,
101477 // Label 5668: @271953
101478 GIM_Try, /*On fail goto*//*Label 5709*/ GIMT_Encode4(271979), // Rule ID 848 //
101479 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
101480 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
101481 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
101482 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
101483 // (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FNEGv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
101484 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGv4f32),
101485 GIR_RootConstrainSelectedInstOperands,
101486 // GIR_Coverage, 848,
101487 GIR_Done,
101488 // Label 5709: @271979
101489 GIM_Reject,
101490 // Label 5669: @271980
101491 GIM_Try, /*On fail goto*//*Label 5710*/ GIMT_Encode4(272106),
101492 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
101493 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
101494 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
101495 GIM_Try, /*On fail goto*//*Label 5711*/ GIMT_Encode4(272011), // Rule ID 846 //
101496 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
101497 // (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FNEGv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
101498 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGv8f16),
101499 GIR_RootConstrainSelectedInstOperands,
101500 // GIR_Coverage, 846,
101501 GIR_Done,
101502 // Label 5711: @272011
101503 GIM_Try, /*On fail goto*//*Label 5712*/ GIMT_Encode4(272058), // Rule ID 5972 //
101504 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
101505 // (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (EORv16i8:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (MOVIv8i16:{ *:[f128] } 128:{ *:[i32] }, 8:{ *:[i32] }))
101506 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
101507 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv8i16),
101508 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
101509 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(128),
101510 GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
101511 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
101512 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORv16i8),
101513 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101514 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
101515 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
101516 GIR_RootConstrainSelectedInstOperands,
101517 // GIR_Coverage, 5972,
101518 GIR_EraseRootFromParent_Done,
101519 // Label 5712: @272058
101520 GIM_Try, /*On fail goto*//*Label 5713*/ GIMT_Encode4(272105), // Rule ID 5973 //
101521 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
101522 // (fneg:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (EORv16i8:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, (MOVIv8i16:{ *:[v8i16] } 128:{ *:[i32] }, 8:{ *:[i32] }))
101523 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
101524 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv8i16),
101525 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
101526 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(128),
101527 GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
101528 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
101529 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORv16i8),
101530 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101531 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
101532 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
101533 GIR_RootConstrainSelectedInstOperands,
101534 // GIR_Coverage, 5973,
101535 GIR_EraseRootFromParent_Done,
101536 // Label 5713: @272105
101537 GIM_Reject,
101538 // Label 5710: @272106
101539 GIM_Reject,
101540 // Label 5670: @272107
101541 GIM_Reject,
101542 // Label 59: @272108
101543 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(9), /*)*//*default:*//*Label 5718*/ GIMT_Encode4(272371),
101544 /*GILLT_s32*//*Label 5714*/ GIMT_Encode4(272147),
101545 /*GILLT_s64*//*Label 5715*/ GIMT_Encode4(272178), GIMT_Encode4(0), GIMT_Encode4(0),
101546 /*GILLT_v2s64*//*Label 5716*/ GIMT_Encode4(272239), GIMT_Encode4(0),
101547 /*GILLT_v4s32*//*Label 5717*/ GIMT_Encode4(272297),
101548 // Label 5714: @272147
101549 GIM_Try, /*On fail goto*//*Label 5719*/ GIMT_Encode4(272177), // Rule ID 510 //
101550 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101551 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
101552 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101553 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
101554 // (fpextend:{ *:[f32] } FPR16:{ *:[f16] }:$Rn) => (FCVTSHr:{ *:[f32] } FPR16:{ *:[f16] }:$Rn)
101555 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTSHr),
101556 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
101557 GIR_RootConstrainSelectedInstOperands,
101558 // GIR_Coverage, 510,
101559 GIR_Done,
101560 // Label 5719: @272177
101561 GIM_Reject,
101562 // Label 5715: @272178
101563 GIM_Try, /*On fail goto*//*Label 5720*/ GIMT_Encode4(272208), // Rule ID 508 //
101564 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101565 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
101566 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101567 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
101568 // (fpextend:{ *:[f64] } FPR16:{ *:[f16] }:$Rn) => (FCVTDHr:{ *:[f64] } FPR16:{ *:[f16] }:$Rn)
101569 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTDHr),
101570 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
101571 GIR_RootConstrainSelectedInstOperands,
101572 // GIR_Coverage, 508,
101573 GIR_Done,
101574 // Label 5720: @272208
101575 GIM_Try, /*On fail goto*//*Label 5721*/ GIMT_Encode4(272238), // Rule ID 512 //
101576 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101577 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
101578 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101579 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101580 // (fpextend:{ *:[f64] } FPR32:{ *:[f32] }:$Rn) => (FCVTDSr:{ *:[f64] } FPR32:{ *:[f32] }:$Rn)
101581 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTDSr),
101582 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
101583 GIR_RootConstrainSelectedInstOperands,
101584 // GIR_Coverage, 512,
101585 GIR_Done,
101586 // Label 5721: @272238
101587 GIM_Reject,
101588 // Label 5716: @272239
101589 GIM_Try, /*On fail goto*//*Label 5722*/ GIMT_Encode4(272296),
101590 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
101591 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
101592 GIM_Try, /*On fail goto*//*Label 5723*/ GIMT_Encode4(272275), // Rule ID 4562 //
101593 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4f32),
101594 // (fpextend:{ *:[v2f64] } (extract_high_v4f32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn)) => (FCVTLv4i32:{ *:[v2f64] } V128:{ *:[v4f32] }:$Rn)
101595 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i32),
101596 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101597 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
101598 GIR_RootConstrainSelectedInstOperands,
101599 // GIR_Coverage, 4562,
101600 GIR_EraseRootFromParent_Done,
101601 // Label 5723: @272275
101602 GIM_Try, /*On fail goto*//*Label 5724*/ GIMT_Encode4(272295), // Rule ID 4560 //
101603 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101604 // (fpextend:{ *:[v2f64] } V64:{ *:[v2f32] }:$Rn) => (FCVTLv2i32:{ *:[v2f64] } V64:{ *:[v2f32] }:$Rn)
101605 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv2i32),
101606 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
101607 GIR_RootConstrainSelectedInstOperands,
101608 // GIR_Coverage, 4560,
101609 GIR_Done,
101610 // Label 5724: @272295
101611 GIM_Reject,
101612 // Label 5722: @272296
101613 GIM_Reject,
101614 // Label 5717: @272297
101615 GIM_Try, /*On fail goto*//*Label 5725*/ GIMT_Encode4(272370),
101616 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
101617 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
101618 GIM_Try, /*On fail goto*//*Label 5726*/ GIMT_Encode4(272333), // Rule ID 4566 //
101619 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8f16),
101620 // (fpextend:{ *:[v4f32] } (extract_high_v8f16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn)) => (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)
101621 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
101622 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101623 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
101624 GIR_RootConstrainSelectedInstOperands,
101625 // GIR_Coverage, 4566,
101626 GIR_EraseRootFromParent_Done,
101627 // Label 5726: @272333
101628 GIM_Try, /*On fail goto*//*Label 5727*/ GIMT_Encode4(272353), // Rule ID 4564 //
101629 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101630 // (fpextend:{ *:[v4f32] } V64:{ *:[v4f16] }:$Rn) => (FCVTLv4i16:{ *:[v4f32] } V64:{ *:[v4f16] }:$Rn)
101631 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
101632 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
101633 GIR_RootConstrainSelectedInstOperands,
101634 // GIR_Coverage, 4564,
101635 GIR_Done,
101636 // Label 5727: @272353
101637 GIM_Try, /*On fail goto*//*Label 5728*/ GIMT_Encode4(272369), // Rule ID 5952 //
101638 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101639 // (fpextend:{ *:[v4f32] } V64:{ *:[v4bf16] }:$Rn) => (SHLLv4i16:{ *:[v4f32] } V64:{ *:[v4bf16] }:$Rn)
101640 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
101641 GIR_RootConstrainSelectedInstOperands,
101642 // GIR_Coverage, 5952,
101643 GIR_Done,
101644 // Label 5728: @272369
101645 GIM_Reject,
101646 // Label 5725: @272370
101647 GIM_Reject,
101648 // Label 5718: @272371
101649 GIM_Reject,
101650 // Label 60: @272372
101651 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 5733*/ GIMT_Encode4(272699),
101652 /*GILLT_s16*//*Label 5729*/ GIMT_Encode4(272411),
101653 /*GILLT_s32*//*Label 5730*/ GIMT_Encode4(272549), GIMT_Encode4(0), GIMT_Encode4(0),
101654 /*GILLT_v2s32*//*Label 5731*/ GIMT_Encode4(272580), GIMT_Encode4(0),
101655 /*GILLT_v4s16*//*Label 5732*/ GIMT_Encode4(272608),
101656 // Label 5729: @272411
101657 GIM_Try, /*On fail goto*//*Label 5734*/ GIMT_Encode4(272441), // Rule ID 504 //
101658 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101659 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
101660 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
101661 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101662 // (fpround:{ *:[f16] } FPR64:{ *:[f64] }:$Rn) => (FCVTHDr:{ *:[f16] } FPR64:{ *:[f64] }:$Rn)
101663 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTHDr),
101664 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
101665 GIR_RootConstrainSelectedInstOperands,
101666 // GIR_Coverage, 504,
101667 GIR_Done,
101668 // Label 5734: @272441
101669 GIM_Try, /*On fail goto*//*Label 5735*/ GIMT_Encode4(272471), // Rule ID 514 //
101670 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101671 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
101672 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
101673 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101674 // (fpround:{ *:[f16] } FPR32:{ *:[f32] }:$Rn) => (FCVTHSr:{ *:[f16] } FPR32:{ *:[f32] }:$Rn)
101675 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTHSr),
101676 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
101677 GIR_RootConstrainSelectedInstOperands,
101678 // GIR_Coverage, 514,
101679 GIR_Done,
101680 // Label 5735: @272471
101681 GIM_Try, /*On fail goto*//*Label 5736*/ GIMT_Encode4(272501), // Rule ID 3683 //
101682 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEONandIsStreamingSafe),
101683 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
101684 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
101685 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101686 // (fpround:{ *:[bf16] } FPR32:{ *:[f32] }:$Rn) => (BFCVT:{ *:[bf16] } ?:{ *:[f32] }:$Rn)
101687 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BFCVT),
101688 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
101689 GIR_RootConstrainSelectedInstOperands,
101690 // GIR_Coverage, 3683,
101691 GIR_Done,
101692 // Label 5736: @272501
101693 GIM_Try, /*On fail goto*//*Label 5737*/ GIMT_Encode4(272548), // Rule ID 4900 //
101694 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEONandIsStreamingSafe),
101695 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
101696 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
101697 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101698 // (fpround:{ *:[bf16] } FPR64:{ *:[f64] }:$Rn) => (BFCVT:{ *:[bf16] } (FCVTXNv1i64:{ *:[i32] } ?:{ *:[f64] }:$Rn))
101699 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
101700 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTXNv1i64),
101701 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
101702 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
101703 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
101704 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVT),
101705 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101706 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
101707 GIR_RootConstrainSelectedInstOperands,
101708 // GIR_Coverage, 4900,
101709 GIR_EraseRootFromParent_Done,
101710 // Label 5737: @272548
101711 GIM_Reject,
101712 // Label 5730: @272549
101713 GIM_Try, /*On fail goto*//*Label 5738*/ GIMT_Encode4(272579), // Rule ID 506 //
101714 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101715 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
101716 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101717 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101718 // (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$Rn) => (FCVTSDr:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
101719 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTSDr),
101720 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
101721 GIR_RootConstrainSelectedInstOperands,
101722 // GIR_Coverage, 506,
101723 GIR_Done,
101724 // Label 5738: @272579
101725 GIM_Reject,
101726 // Label 5731: @272580
101727 GIM_Try, /*On fail goto*//*Label 5739*/ GIMT_Encode4(272607), // Rule ID 4570 //
101728 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
101729 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101730 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
101731 // (fpround:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn) => (FCVTNv2i32:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn)
101732 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv2i32),
101733 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
101734 GIR_RootConstrainSelectedInstOperands,
101735 // GIR_Coverage, 4570,
101736 GIR_Done,
101737 // Label 5739: @272607
101738 GIM_Reject,
101739 // Label 5732: @272608
101740 GIM_Try, /*On fail goto*//*Label 5740*/ GIMT_Encode4(272698),
101741 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
101742 GIM_Try, /*On fail goto*//*Label 5741*/ GIMT_Encode4(272673), // Rule ID 3680 //
101743 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16_HasNEON),
101744 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
101745 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
101746 // (fpround:{ *:[v4bf16] } V128:{ *:[v4f32] }:$Rn) => (EXTRACT_SUBREG:{ *:[v4bf16] } (BFCVTN:{ *:[f128] } V128:{ *:[v4f32] }:$Rn), dsub:{ *:[i32] })
101747 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
101748 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN),
101749 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
101750 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
101751 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
101752 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
101753 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
101754 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
101755 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
101756 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
101757 // GIR_Coverage, 3680,
101758 GIR_EraseRootFromParent_Done,
101759 // Label 5741: @272673
101760 GIM_Try, /*On fail goto*//*Label 5742*/ GIMT_Encode4(272697), // Rule ID 4572 //
101761 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101762 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
101763 // (fpround:{ *:[v4f16] } V128:{ *:[v4f32] }:$Rn) => (FCVTNv4i16:{ *:[v4f16] } V128:{ *:[v4f32] }:$Rn)
101764 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
101765 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
101766 GIR_RootConstrainSelectedInstOperands,
101767 // GIR_Coverage, 4572,
101768 GIR_Done,
101769 // Label 5742: @272697
101770 GIM_Reject,
101771 // Label 5740: @272698
101772 GIM_Reject,
101773 // Label 5733: @272699
101774 GIM_Reject,
101775 // Label 61: @272700
101776 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 5750*/ GIMT_Encode4(273762),
101777 /*GILLT_s32*//*Label 5743*/ GIMT_Encode4(272747),
101778 /*GILLT_s64*//*Label 5744*/ GIMT_Encode4(273134), GIMT_Encode4(0),
101779 /*GILLT_v2s32*//*Label 5745*/ GIMT_Encode4(273521),
101780 /*GILLT_v2s64*//*Label 5746*/ GIMT_Encode4(273595),
101781 /*GILLT_v4s16*//*Label 5747*/ GIMT_Encode4(273669),
101782 /*GILLT_v4s32*//*Label 5748*/ GIMT_Encode4(273700), GIMT_Encode4(0),
101783 /*GILLT_v8s16*//*Label 5749*/ GIMT_Encode4(273731),
101784 // Label 5743: @272747
101785 GIM_Try, /*On fail goto*//*Label 5751*/ GIMT_Encode4(272784), // Rule ID 4336 //
101786 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
101787 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
101788 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101789 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
101790 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
101791 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101792 // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTPSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
101793 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUWSr),
101794 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101795 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101796 GIR_RootConstrainSelectedInstOperands,
101797 // GIR_Coverage, 4336,
101798 GIR_EraseRootFromParent_Done,
101799 // Label 5751: @272784
101800 GIM_Try, /*On fail goto*//*Label 5752*/ GIMT_Encode4(272821), // Rule ID 4338 //
101801 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
101802 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
101803 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101804 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
101805 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
101806 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101807 // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTPSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
101808 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUWDr),
101809 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101810 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101811 GIR_RootConstrainSelectedInstOperands,
101812 // GIR_Coverage, 4338,
101813 GIR_EraseRootFromParent_Done,
101814 // Label 5752: @272821
101815 GIM_Try, /*On fail goto*//*Label 5753*/ GIMT_Encode4(272858), // Rule ID 4356 //
101816 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
101817 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
101818 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101819 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
101820 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
101821 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101822 // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTMSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
101823 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUWSr),
101824 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101825 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101826 GIR_RootConstrainSelectedInstOperands,
101827 // GIR_Coverage, 4356,
101828 GIR_EraseRootFromParent_Done,
101829 // Label 5753: @272858
101830 GIM_Try, /*On fail goto*//*Label 5754*/ GIMT_Encode4(272895), // Rule ID 4358 //
101831 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
101832 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
101833 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101834 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
101835 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
101836 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101837 // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTMSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
101838 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUWDr),
101839 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101840 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101841 GIR_RootConstrainSelectedInstOperands,
101842 // GIR_Coverage, 4358,
101843 GIR_EraseRootFromParent_Done,
101844 // Label 5754: @272895
101845 GIM_Try, /*On fail goto*//*Label 5755*/ GIMT_Encode4(272932), // Rule ID 4396 //
101846 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
101847 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
101848 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101849 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
101850 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
101851 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101852 // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTASUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
101853 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWSr),
101854 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101855 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101856 GIR_RootConstrainSelectedInstOperands,
101857 // GIR_Coverage, 4396,
101858 GIR_EraseRootFromParent_Done,
101859 // Label 5755: @272932
101860 GIM_Try, /*On fail goto*//*Label 5756*/ GIMT_Encode4(272969), // Rule ID 4398 //
101861 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
101862 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
101863 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101864 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
101865 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
101866 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101867 // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTASUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
101868 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWDr),
101869 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101870 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101871 GIR_RootConstrainSelectedInstOperands,
101872 // GIR_Coverage, 4398,
101873 GIR_EraseRootFromParent_Done,
101874 // Label 5756: @272969
101875 GIM_Try, /*On fail goto*//*Label 5757*/ GIMT_Encode4(273006), // Rule ID 4376 //
101876 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
101877 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
101878 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101879 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
101880 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
101881 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101882 // (fp_to_sint:{ *:[i32] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTZSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
101883 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWSr),
101884 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101885 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101886 GIR_RootConstrainSelectedInstOperands,
101887 // GIR_Coverage, 4376,
101888 GIR_EraseRootFromParent_Done,
101889 // Label 5757: @273006
101890 GIM_Try, /*On fail goto*//*Label 5758*/ GIMT_Encode4(273043), // Rule ID 4378 //
101891 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
101892 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
101893 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101894 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
101895 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
101896 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101897 // (fp_to_sint:{ *:[i32] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTZSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
101898 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWDr),
101899 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101900 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101901 GIR_RootConstrainSelectedInstOperands,
101902 // GIR_Coverage, 4378,
101903 GIR_EraseRootFromParent_Done,
101904 // Label 5758: @273043
101905 GIM_Try, /*On fail goto*//*Label 5759*/ GIMT_Encode4(273073), // Rule ID 405 //
101906 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
101907 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
101908 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
101909 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
101910 // (fp_to_sint:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) => (FCVTZSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
101911 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWHr),
101912 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
101913 GIR_RootConstrainSelectedInstOperands,
101914 // GIR_Coverage, 405,
101915 GIR_Done,
101916 // Label 5759: @273073
101917 GIM_Try, /*On fail goto*//*Label 5760*/ GIMT_Encode4(273103), // Rule ID 409 //
101918 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101919 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
101920 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
101921 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
101922 // (fp_to_sint:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) => (FCVTZSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
101923 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWSr),
101924 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
101925 GIR_RootConstrainSelectedInstOperands,
101926 // GIR_Coverage, 409,
101927 GIR_Done,
101928 // Label 5760: @273103
101929 GIM_Try, /*On fail goto*//*Label 5761*/ GIMT_Encode4(273133), // Rule ID 413 //
101930 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
101931 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
101932 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
101933 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
101934 // (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) => (FCVTZSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
101935 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWDr),
101936 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
101937 GIR_RootConstrainSelectedInstOperands,
101938 // GIR_Coverage, 413,
101939 GIR_Done,
101940 // Label 5761: @273133
101941 GIM_Reject,
101942 // Label 5744: @273134
101943 GIM_Try, /*On fail goto*//*Label 5762*/ GIMT_Encode4(273171), // Rule ID 4337 //
101944 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
101945 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
101946 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101947 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
101948 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
101949 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101950 // (fp_to_sint:{ *:[i64] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTPSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
101951 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUXSr),
101952 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101954 GIR_RootConstrainSelectedInstOperands,
101955 // GIR_Coverage, 4337,
101956 GIR_EraseRootFromParent_Done,
101957 // Label 5762: @273171
101958 GIM_Try, /*On fail goto*//*Label 5763*/ GIMT_Encode4(273208), // Rule ID 4339 //
101959 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
101960 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
101961 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101962 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
101963 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
101964 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101965 // (fp_to_sint:{ *:[i64] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTPSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
101966 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUXDr),
101967 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101968 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101969 GIR_RootConstrainSelectedInstOperands,
101970 // GIR_Coverage, 4339,
101971 GIR_EraseRootFromParent_Done,
101972 // Label 5763: @273208
101973 GIM_Try, /*On fail goto*//*Label 5764*/ GIMT_Encode4(273245), // Rule ID 4357 //
101974 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
101975 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
101976 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101977 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
101978 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
101979 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101980 // (fp_to_sint:{ *:[i64] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTMSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
101981 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUXSr),
101982 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101983 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101984 GIR_RootConstrainSelectedInstOperands,
101985 // GIR_Coverage, 4357,
101986 GIR_EraseRootFromParent_Done,
101987 // Label 5764: @273245
101988 GIM_Try, /*On fail goto*//*Label 5765*/ GIMT_Encode4(273282), // Rule ID 4359 //
101989 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
101990 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
101991 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
101992 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
101993 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
101994 GIM_CheckIsSafeToFold, /*NumInsns*/1,
101995 // (fp_to_sint:{ *:[i64] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTMSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
101996 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUXDr),
101997 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
101998 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
101999 GIR_RootConstrainSelectedInstOperands,
102000 // GIR_Coverage, 4359,
102001 GIR_EraseRootFromParent_Done,
102002 // Label 5765: @273282
102003 GIM_Try, /*On fail goto*//*Label 5766*/ GIMT_Encode4(273319), // Rule ID 4397 //
102004 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102005 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
102006 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102007 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
102008 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
102009 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102010 // (fp_to_sint:{ *:[i64] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTASUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
102011 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXSr),
102012 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102014 GIR_RootConstrainSelectedInstOperands,
102015 // GIR_Coverage, 4397,
102016 GIR_EraseRootFromParent_Done,
102017 // Label 5766: @273319
102018 GIM_Try, /*On fail goto*//*Label 5767*/ GIMT_Encode4(273356), // Rule ID 4399 //
102019 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
102020 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
102021 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102022 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
102023 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
102024 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102025 // (fp_to_sint:{ *:[i64] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTASUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
102026 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXDr),
102027 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102028 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102029 GIR_RootConstrainSelectedInstOperands,
102030 // GIR_Coverage, 4399,
102031 GIR_EraseRootFromParent_Done,
102032 // Label 5767: @273356
102033 GIM_Try, /*On fail goto*//*Label 5768*/ GIMT_Encode4(273393), // Rule ID 4377 //
102034 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102035 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
102036 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102037 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
102038 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
102039 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102040 // (fp_to_sint:{ *:[i64] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTZSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
102041 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXSr),
102042 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102044 GIR_RootConstrainSelectedInstOperands,
102045 // GIR_Coverage, 4377,
102046 GIR_EraseRootFromParent_Done,
102047 // Label 5768: @273393
102048 GIM_Try, /*On fail goto*//*Label 5769*/ GIMT_Encode4(273430), // Rule ID 4379 //
102049 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
102050 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
102051 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102052 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
102053 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
102054 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102055 // (fp_to_sint:{ *:[i64] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTZSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
102056 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXDr),
102057 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102058 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102059 GIR_RootConstrainSelectedInstOperands,
102060 // GIR_Coverage, 4379,
102061 GIR_EraseRootFromParent_Done,
102062 // Label 5769: @273430
102063 GIM_Try, /*On fail goto*//*Label 5770*/ GIMT_Encode4(273460), // Rule ID 407 //
102064 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
102065 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
102066 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
102067 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
102068 // (fp_to_sint:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) => (FCVTZSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
102069 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXHr),
102070 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102071 GIR_RootConstrainSelectedInstOperands,
102072 // GIR_Coverage, 407,
102073 GIR_Done,
102074 // Label 5770: @273460
102075 GIM_Try, /*On fail goto*//*Label 5771*/ GIMT_Encode4(273490), // Rule ID 411 //
102076 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
102077 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102078 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
102079 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
102080 // (fp_to_sint:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) => (FCVTZSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
102081 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXSr),
102082 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102083 GIR_RootConstrainSelectedInstOperands,
102084 // GIR_Coverage, 411,
102085 GIR_Done,
102086 // Label 5771: @273490
102087 GIM_Try, /*On fail goto*//*Label 5772*/ GIMT_Encode4(273520), // Rule ID 415 //
102088 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
102089 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
102090 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
102091 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
102092 // (fp_to_sint:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) => (FCVTZSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
102093 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXDr),
102094 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102095 GIR_RootConstrainSelectedInstOperands,
102096 // GIR_Coverage, 415,
102097 GIR_Done,
102098 // Label 5772: @273520
102099 GIM_Reject,
102100 // Label 5745: @273521
102101 GIM_Try, /*On fail goto*//*Label 5773*/ GIMT_Encode4(273551), // Rule ID 830 //
102102 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
102103 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
102104 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
102105 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
102106 // (fp_to_sint:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCVTZSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
102107 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2f32),
102108 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102109 GIR_RootConstrainSelectedInstOperands,
102110 // GIR_Coverage, 830,
102111 GIR_Done,
102112 // Label 5773: @273551
102113 GIM_Try, /*On fail goto*//*Label 5774*/ GIMT_Encode4(273594), // Rule ID 12362 //
102114 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
102115 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
102116 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
102117 // (fp_to_sint:{ *:[v2i32] } v2f64:{ *:[v2f64] }:$src) => (XTNv2i32:{ *:[v2i32] } (FCVTZSv2f64:{ *:[f128] } V128:{ *:[v2f64] }:$src))
102118 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
102119 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2f64),
102120 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102121 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
102122 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
102123 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XTNv2i32),
102124 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102125 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
102126 GIR_RootConstrainSelectedInstOperands,
102127 // GIR_Coverage, 12362,
102128 GIR_EraseRootFromParent_Done,
102129 // Label 5774: @273594
102130 GIM_Reject,
102131 // Label 5746: @273595
102132 GIM_Try, /*On fail goto*//*Label 5775*/ GIMT_Encode4(273625), // Rule ID 834 //
102133 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
102134 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
102135 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
102136 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
102137 // (fp_to_sint:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCVTZSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
102138 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2f64),
102139 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102140 GIR_RootConstrainSelectedInstOperands,
102141 // GIR_Coverage, 834,
102142 GIR_Done,
102143 // Label 5775: @273625
102144 GIM_Try, /*On fail goto*//*Label 5776*/ GIMT_Encode4(273668), // Rule ID 12360 //
102145 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
102146 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
102147 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
102148 // (fp_to_sint:{ *:[v2i64] } v2f32:{ *:[v2f32] }:$src) => (FCVTZSv2f64:{ *:[v2i64] } (FCVTLv2i32:{ *:[f128] } V64:{ *:[v2f32] }:$src))
102149 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
102150 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv2i32),
102151 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102152 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
102153 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
102154 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2f64),
102155 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102156 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
102157 GIR_RootConstrainSelectedInstOperands,
102158 // GIR_Coverage, 12360,
102159 GIR_EraseRootFromParent_Done,
102160 // Label 5776: @273668
102161 GIM_Reject,
102162 // Label 5747: @273669
102163 GIM_Try, /*On fail goto*//*Label 5777*/ GIMT_Encode4(273699), // Rule ID 826 //
102164 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
102165 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
102166 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
102167 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
102168 // (fp_to_sint:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCVTZSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
102169 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4f16),
102170 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102171 GIR_RootConstrainSelectedInstOperands,
102172 // GIR_Coverage, 826,
102173 GIR_Done,
102174 // Label 5777: @273699
102175 GIM_Reject,
102176 // Label 5748: @273700
102177 GIM_Try, /*On fail goto*//*Label 5778*/ GIMT_Encode4(273730), // Rule ID 832 //
102178 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
102179 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
102180 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
102181 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
102182 // (fp_to_sint:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCVTZSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
102183 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4f32),
102184 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102185 GIR_RootConstrainSelectedInstOperands,
102186 // GIR_Coverage, 832,
102187 GIR_Done,
102188 // Label 5778: @273730
102189 GIM_Reject,
102190 // Label 5749: @273731
102191 GIM_Try, /*On fail goto*//*Label 5779*/ GIMT_Encode4(273761), // Rule ID 828 //
102192 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
102193 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
102194 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
102195 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
102196 // (fp_to_sint:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCVTZSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
102197 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv8f16),
102198 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102199 GIR_RootConstrainSelectedInstOperands,
102200 // GIR_Coverage, 828,
102201 GIR_Done,
102202 // Label 5779: @273761
102203 GIM_Reject,
102204 // Label 5750: @273762
102205 GIM_Reject,
102206 // Label 62: @273763
102207 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 5787*/ GIMT_Encode4(274825),
102208 /*GILLT_s32*//*Label 5780*/ GIMT_Encode4(273810),
102209 /*GILLT_s64*//*Label 5781*/ GIMT_Encode4(274197), GIMT_Encode4(0),
102210 /*GILLT_v2s32*//*Label 5782*/ GIMT_Encode4(274584),
102211 /*GILLT_v2s64*//*Label 5783*/ GIMT_Encode4(274658),
102212 /*GILLT_v4s16*//*Label 5784*/ GIMT_Encode4(274732),
102213 /*GILLT_v4s32*//*Label 5785*/ GIMT_Encode4(274763), GIMT_Encode4(0),
102214 /*GILLT_v8s16*//*Label 5786*/ GIMT_Encode4(274794),
102215 // Label 5780: @273810
102216 GIM_Try, /*On fail goto*//*Label 5788*/ GIMT_Encode4(273847), // Rule ID 4346 //
102217 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102218 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
102219 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102220 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
102221 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
102222 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102223 // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTPUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
102224 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUWSr),
102225 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102226 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102227 GIR_RootConstrainSelectedInstOperands,
102228 // GIR_Coverage, 4346,
102229 GIR_EraseRootFromParent_Done,
102230 // Label 5788: @273847
102231 GIM_Try, /*On fail goto*//*Label 5789*/ GIMT_Encode4(273884), // Rule ID 4348 //
102232 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
102233 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
102234 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102235 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
102236 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
102237 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102238 // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTPUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
102239 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUWDr),
102240 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102241 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102242 GIR_RootConstrainSelectedInstOperands,
102243 // GIR_Coverage, 4348,
102244 GIR_EraseRootFromParent_Done,
102245 // Label 5789: @273884
102246 GIM_Try, /*On fail goto*//*Label 5790*/ GIMT_Encode4(273921), // Rule ID 4366 //
102247 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102248 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
102249 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102250 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
102251 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
102252 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102253 // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTMUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
102254 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUWSr),
102255 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102256 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102257 GIR_RootConstrainSelectedInstOperands,
102258 // GIR_Coverage, 4366,
102259 GIR_EraseRootFromParent_Done,
102260 // Label 5790: @273921
102261 GIM_Try, /*On fail goto*//*Label 5791*/ GIMT_Encode4(273958), // Rule ID 4368 //
102262 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
102263 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
102264 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102265 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
102266 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
102267 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102268 // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTMUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
102269 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUWDr),
102270 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102271 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102272 GIR_RootConstrainSelectedInstOperands,
102273 // GIR_Coverage, 4368,
102274 GIR_EraseRootFromParent_Done,
102275 // Label 5791: @273958
102276 GIM_Try, /*On fail goto*//*Label 5792*/ GIMT_Encode4(273995), // Rule ID 4406 //
102277 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102278 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
102279 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102280 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
102281 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
102282 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102283 // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTAUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
102284 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUWSr),
102285 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102286 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102287 GIR_RootConstrainSelectedInstOperands,
102288 // GIR_Coverage, 4406,
102289 GIR_EraseRootFromParent_Done,
102290 // Label 5792: @273995
102291 GIM_Try, /*On fail goto*//*Label 5793*/ GIMT_Encode4(274032), // Rule ID 4408 //
102292 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
102293 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
102294 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102295 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
102296 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
102297 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102298 // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTAUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
102299 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUWDr),
102300 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102301 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102302 GIR_RootConstrainSelectedInstOperands,
102303 // GIR_Coverage, 4408,
102304 GIR_EraseRootFromParent_Done,
102305 // Label 5793: @274032
102306 GIM_Try, /*On fail goto*//*Label 5794*/ GIMT_Encode4(274069), // Rule ID 4386 //
102307 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102308 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
102309 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102310 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
102311 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
102312 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102313 // (fp_to_uint:{ *:[i32] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTZUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
102314 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWSr),
102315 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102316 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102317 GIR_RootConstrainSelectedInstOperands,
102318 // GIR_Coverage, 4386,
102319 GIR_EraseRootFromParent_Done,
102320 // Label 5794: @274069
102321 GIM_Try, /*On fail goto*//*Label 5795*/ GIMT_Encode4(274106), // Rule ID 4388 //
102322 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
102323 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
102324 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102325 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
102326 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
102327 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102328 // (fp_to_uint:{ *:[i32] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTZUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
102329 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWDr),
102330 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102331 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102332 GIR_RootConstrainSelectedInstOperands,
102333 // GIR_Coverage, 4388,
102334 GIR_EraseRootFromParent_Done,
102335 // Label 5795: @274106
102336 GIM_Try, /*On fail goto*//*Label 5796*/ GIMT_Encode4(274136), // Rule ID 417 //
102337 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
102338 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
102339 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
102340 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
102341 // (fp_to_uint:{ *:[i32] } FPR16:{ *:[f16] }:$Rn) => (FCVTZUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
102342 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWHr),
102343 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102344 GIR_RootConstrainSelectedInstOperands,
102345 // GIR_Coverage, 417,
102346 GIR_Done,
102347 // Label 5796: @274136
102348 GIM_Try, /*On fail goto*//*Label 5797*/ GIMT_Encode4(274166), // Rule ID 421 //
102349 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
102350 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102351 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
102352 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
102353 // (fp_to_uint:{ *:[i32] } FPR32:{ *:[f32] }:$Rn) => (FCVTZUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
102354 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWSr),
102355 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102356 GIR_RootConstrainSelectedInstOperands,
102357 // GIR_Coverage, 421,
102358 GIR_Done,
102359 // Label 5797: @274166
102360 GIM_Try, /*On fail goto*//*Label 5798*/ GIMT_Encode4(274196), // Rule ID 425 //
102361 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
102362 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
102363 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
102364 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
102365 // (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$Rn) => (FCVTZUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
102366 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWDr),
102367 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102368 GIR_RootConstrainSelectedInstOperands,
102369 // GIR_Coverage, 425,
102370 GIR_Done,
102371 // Label 5798: @274196
102372 GIM_Reject,
102373 // Label 5781: @274197
102374 GIM_Try, /*On fail goto*//*Label 5799*/ GIMT_Encode4(274234), // Rule ID 4347 //
102375 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102376 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
102377 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102378 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
102379 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
102380 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102381 // (fp_to_uint:{ *:[i64] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTPUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
102382 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUXSr),
102383 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102385 GIR_RootConstrainSelectedInstOperands,
102386 // GIR_Coverage, 4347,
102387 GIR_EraseRootFromParent_Done,
102388 // Label 5799: @274234
102389 GIM_Try, /*On fail goto*//*Label 5800*/ GIMT_Encode4(274271), // Rule ID 4349 //
102390 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
102391 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
102392 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102393 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
102394 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
102395 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102396 // (fp_to_uint:{ *:[i64] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTPUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
102397 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUXDr),
102398 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102399 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102400 GIR_RootConstrainSelectedInstOperands,
102401 // GIR_Coverage, 4349,
102402 GIR_EraseRootFromParent_Done,
102403 // Label 5800: @274271
102404 GIM_Try, /*On fail goto*//*Label 5801*/ GIMT_Encode4(274308), // Rule ID 4367 //
102405 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102406 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
102407 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102408 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
102409 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
102410 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102411 // (fp_to_uint:{ *:[i64] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTMUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
102412 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUXSr),
102413 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102414 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102415 GIR_RootConstrainSelectedInstOperands,
102416 // GIR_Coverage, 4367,
102417 GIR_EraseRootFromParent_Done,
102418 // Label 5801: @274308
102419 GIM_Try, /*On fail goto*//*Label 5802*/ GIMT_Encode4(274345), // Rule ID 4369 //
102420 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
102421 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
102422 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102423 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
102424 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
102425 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102426 // (fp_to_uint:{ *:[i64] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTMUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
102427 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUXDr),
102428 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102429 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102430 GIR_RootConstrainSelectedInstOperands,
102431 // GIR_Coverage, 4369,
102432 GIR_EraseRootFromParent_Done,
102433 // Label 5802: @274345
102434 GIM_Try, /*On fail goto*//*Label 5803*/ GIMT_Encode4(274382), // Rule ID 4407 //
102435 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102436 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
102437 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102438 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
102439 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
102440 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102441 // (fp_to_uint:{ *:[i64] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTAUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
102442 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUXSr),
102443 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102444 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102445 GIR_RootConstrainSelectedInstOperands,
102446 // GIR_Coverage, 4407,
102447 GIR_EraseRootFromParent_Done,
102448 // Label 5803: @274382
102449 GIM_Try, /*On fail goto*//*Label 5804*/ GIMT_Encode4(274419), // Rule ID 4409 //
102450 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
102451 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
102452 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102453 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
102454 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
102455 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102456 // (fp_to_uint:{ *:[i64] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTAUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
102457 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUXDr),
102458 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102459 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102460 GIR_RootConstrainSelectedInstOperands,
102461 // GIR_Coverage, 4409,
102462 GIR_EraseRootFromParent_Done,
102463 // Label 5804: @274419
102464 GIM_Try, /*On fail goto*//*Label 5805*/ GIMT_Encode4(274456), // Rule ID 4387 //
102465 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102466 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
102467 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102468 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
102469 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
102470 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102471 // (fp_to_uint:{ *:[i64] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)) => (FCVTZUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
102472 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXSr),
102473 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102475 GIR_RootConstrainSelectedInstOperands,
102476 // GIR_Coverage, 4387,
102477 GIR_EraseRootFromParent_Done,
102478 // Label 5805: @274456
102479 GIM_Try, /*On fail goto*//*Label 5806*/ GIMT_Encode4(274493), // Rule ID 4389 //
102480 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
102481 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
102482 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102483 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
102484 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
102485 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102486 // (fp_to_uint:{ *:[i64] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)) => (FCVTZUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
102487 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXDr),
102488 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102489 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102490 GIR_RootConstrainSelectedInstOperands,
102491 // GIR_Coverage, 4389,
102492 GIR_EraseRootFromParent_Done,
102493 // Label 5806: @274493
102494 GIM_Try, /*On fail goto*//*Label 5807*/ GIMT_Encode4(274523), // Rule ID 419 //
102495 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
102496 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
102497 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
102498 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
102499 // (fp_to_uint:{ *:[i64] } FPR16:{ *:[f16] }:$Rn) => (FCVTZUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
102500 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXHr),
102501 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102502 GIR_RootConstrainSelectedInstOperands,
102503 // GIR_Coverage, 419,
102504 GIR_Done,
102505 // Label 5807: @274523
102506 GIM_Try, /*On fail goto*//*Label 5808*/ GIMT_Encode4(274553), // Rule ID 423 //
102507 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
102508 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102509 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
102510 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
102511 // (fp_to_uint:{ *:[i64] } FPR32:{ *:[f32] }:$Rn) => (FCVTZUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
102512 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXSr),
102513 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102514 GIR_RootConstrainSelectedInstOperands,
102515 // GIR_Coverage, 423,
102516 GIR_Done,
102517 // Label 5808: @274553
102518 GIM_Try, /*On fail goto*//*Label 5809*/ GIMT_Encode4(274583), // Rule ID 427 //
102519 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
102520 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
102521 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
102522 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
102523 // (fp_to_uint:{ *:[i64] } FPR64:{ *:[f64] }:$Rn) => (FCVTZUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
102524 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXDr),
102525 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102526 GIR_RootConstrainSelectedInstOperands,
102527 // GIR_Coverage, 427,
102528 GIR_Done,
102529 // Label 5809: @274583
102530 GIM_Reject,
102531 // Label 5782: @274584
102532 GIM_Try, /*On fail goto*//*Label 5810*/ GIMT_Encode4(274614), // Rule ID 840 //
102533 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
102534 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
102535 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
102536 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
102537 // (fp_to_uint:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCVTZUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
102538 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2f32),
102539 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102540 GIR_RootConstrainSelectedInstOperands,
102541 // GIR_Coverage, 840,
102542 GIR_Done,
102543 // Label 5810: @274614
102544 GIM_Try, /*On fail goto*//*Label 5811*/ GIMT_Encode4(274657), // Rule ID 12363 //
102545 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
102546 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
102547 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
102548 // (fp_to_uint:{ *:[v2i32] } v2f64:{ *:[v2f64] }:$src) => (XTNv2i32:{ *:[v2i32] } (FCVTZUv2f64:{ *:[f128] } V128:{ *:[v2f64] }:$src))
102549 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
102550 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2f64),
102551 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102552 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
102553 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
102554 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XTNv2i32),
102555 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102556 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
102557 GIR_RootConstrainSelectedInstOperands,
102558 // GIR_Coverage, 12363,
102559 GIR_EraseRootFromParent_Done,
102560 // Label 5811: @274657
102561 GIM_Reject,
102562 // Label 5783: @274658
102563 GIM_Try, /*On fail goto*//*Label 5812*/ GIMT_Encode4(274688), // Rule ID 844 //
102564 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
102565 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
102566 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
102567 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
102568 // (fp_to_uint:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCVTZUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
102569 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2f64),
102570 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102571 GIR_RootConstrainSelectedInstOperands,
102572 // GIR_Coverage, 844,
102573 GIR_Done,
102574 // Label 5812: @274688
102575 GIM_Try, /*On fail goto*//*Label 5813*/ GIMT_Encode4(274731), // Rule ID 12361 //
102576 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
102577 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
102578 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
102579 // (fp_to_uint:{ *:[v2i64] } v2f32:{ *:[v2f32] }:$src) => (FCVTZUv2f64:{ *:[v2i64] } (FCVTLv2i32:{ *:[f128] } V64:{ *:[v2f32] }:$src))
102580 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
102581 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv2i32),
102582 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102583 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
102584 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
102585 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2f64),
102586 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102587 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
102588 GIR_RootConstrainSelectedInstOperands,
102589 // GIR_Coverage, 12361,
102590 GIR_EraseRootFromParent_Done,
102591 // Label 5813: @274731
102592 GIM_Reject,
102593 // Label 5784: @274732
102594 GIM_Try, /*On fail goto*//*Label 5814*/ GIMT_Encode4(274762), // Rule ID 836 //
102595 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
102596 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
102597 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
102598 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
102599 // (fp_to_uint:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCVTZUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
102600 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4f16),
102601 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102602 GIR_RootConstrainSelectedInstOperands,
102603 // GIR_Coverage, 836,
102604 GIR_Done,
102605 // Label 5814: @274762
102606 GIM_Reject,
102607 // Label 5785: @274763
102608 GIM_Try, /*On fail goto*//*Label 5815*/ GIMT_Encode4(274793), // Rule ID 842 //
102609 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
102610 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
102611 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
102612 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
102613 // (fp_to_uint:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCVTZUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
102614 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4f32),
102615 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102616 GIR_RootConstrainSelectedInstOperands,
102617 // GIR_Coverage, 842,
102618 GIR_Done,
102619 // Label 5815: @274793
102620 GIM_Reject,
102621 // Label 5786: @274794
102622 GIM_Try, /*On fail goto*//*Label 5816*/ GIMT_Encode4(274824), // Rule ID 838 //
102623 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
102624 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
102625 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
102626 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
102627 // (fp_to_uint:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCVTZUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
102628 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv8f16),
102629 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102630 GIR_RootConstrainSelectedInstOperands,
102631 // GIR_Coverage, 838,
102632 GIR_Done,
102633 // Label 5816: @274824
102634 GIM_Reject,
102635 // Label 5787: @274825
102636 GIM_Reject,
102637 // Label 63: @274826
102638 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 5825*/ GIMT_Encode4(278999),
102639 /*GILLT_s16*//*Label 5817*/ GIMT_Encode4(274877),
102640 /*GILLT_s32*//*Label 5818*/ GIMT_Encode4(274995),
102641 /*GILLT_s64*//*Label 5819*/ GIMT_Encode4(276881), GIMT_Encode4(0),
102642 /*GILLT_v2s32*//*Label 5820*/ GIMT_Encode4(278755),
102643 /*GILLT_v2s64*//*Label 5821*/ GIMT_Encode4(278829),
102644 /*GILLT_v4s16*//*Label 5822*/ GIMT_Encode4(278906),
102645 /*GILLT_v4s32*//*Label 5823*/ GIMT_Encode4(278937), GIMT_Encode4(0),
102646 /*GILLT_v8s16*//*Label 5824*/ GIMT_Encode4(278968),
102647 // Label 5817: @274877
102648 GIM_Try, /*On fail goto*//*Label 5826*/ GIMT_Encode4(274934), // Rule ID 4963 //
102649 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
102650 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102651 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
102652 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102653 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
102654 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
102655 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102656 // (sint_to_fp:{ *:[f16] } (fp_to_sint:{ *:[i32] } f16:{ *:[f16] }:$Rn)) => (SCVTFv1i16:{ *:[f16] } (FCVTZSv1f16:{ *:[f16] } f16:{ *:[f16] }:$Rn))
102657 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
102658 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1f16),
102659 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102660 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
102661 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
102662 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i16),
102663 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102664 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
102665 GIR_RootConstrainSelectedInstOperands,
102666 // GIR_Coverage, 4963,
102667 GIR_EraseRootFromParent_Done,
102668 // Label 5826: @274934
102669 GIM_Try, /*On fail goto*//*Label 5827*/ GIMT_Encode4(274964), // Rule ID 453 //
102670 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
102671 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102672 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
102673 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
102674 // (sint_to_fp:{ *:[f16] } GPR32:{ *:[i32] }:$Rn) => (SCVTFUWHri:{ *:[f16] } GPR32:{ *:[i32] }:$Rn)
102675 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFUWHri),
102676 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102677 GIR_RootConstrainSelectedInstOperands,
102678 // GIR_Coverage, 453,
102679 GIR_Done,
102680 // Label 5827: @274964
102681 GIM_Try, /*On fail goto*//*Label 5828*/ GIMT_Encode4(274994), // Rule ID 459 //
102682 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
102683 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
102684 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
102685 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
102686 // (sint_to_fp:{ *:[f16] } GPR64:{ *:[i64] }:$Rn) => (SCVTFUXHri:{ *:[f16] } GPR64:{ *:[i64] }:$Rn)
102687 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFUXHri),
102688 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
102689 GIR_RootConstrainSelectedInstOperands,
102690 // GIR_Coverage, 459,
102691 GIR_Done,
102692 // Label 5828: @274994
102693 GIM_Reject,
102694 // Label 5818: @274995
102695 GIM_Try, /*On fail goto*//*Label 5829*/ GIMT_Encode4(275233), // Rule ID 5974 //
102696 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
102697 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102698 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
102699 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102700 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
102701 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
102702 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
102703 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
102704 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102705 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
102706 // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>) => (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv8i8_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$ext), bsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
102707 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
102708 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
102709 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
102710 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
102711 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
102712 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
102713 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s8,
102714 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
102715 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102716 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
102717 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
102718 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
102719 GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
102720 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
102721 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
102722 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102723 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
102724 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
102725 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102726 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
102727 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
102728 GIR_AddImm8, /*InsnID*/5, /*Imm*/1,
102729 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
102730 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
102731 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
102732 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i8_shift),
102733 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102734 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
102735 GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
102736 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
102737 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
102738 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102739 GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
102740 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
102741 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
102742 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
102743 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102744 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
102745 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
102746 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
102747 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
102748 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102749 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
102750 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
102751 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
102752 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
102753 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102754 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
102755 GIR_RootConstrainSelectedInstOperands,
102756 // GIR_Coverage, 5974,
102757 GIR_EraseRootFromParent_Done,
102758 // Label 5829: @275233
102759 GIM_Try, /*On fail goto*//*Label 5830*/ GIMT_Encode4(275471), // Rule ID 5975 //
102760 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
102761 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102762 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
102763 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102764 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
102765 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
102766 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
102767 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
102768 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102769 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
102770 // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>) => (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv8i8_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$ext), bsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
102771 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
102772 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
102773 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
102774 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
102775 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
102776 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
102777 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s8,
102778 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
102779 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102780 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
102781 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
102782 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
102783 GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
102784 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
102785 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
102786 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102787 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
102788 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
102789 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102790 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
102791 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
102792 GIR_AddImm8, /*InsnID*/5, /*Imm*/1,
102793 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
102794 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
102795 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
102796 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i8_shift),
102797 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102798 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
102799 GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
102800 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
102801 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
102802 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102803 GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
102804 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
102805 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
102806 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
102807 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102808 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
102809 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
102810 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
102811 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
102812 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102813 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
102814 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
102815 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
102816 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
102817 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102818 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
102819 GIR_RootConstrainSelectedInstOperands,
102820 // GIR_Coverage, 5975,
102821 GIR_EraseRootFromParent_Done,
102822 // Label 5830: @275471
102823 GIM_Try, /*On fail goto*//*Label 5831*/ GIMT_Encode4(275660), // Rule ID 5978 //
102824 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
102825 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102826 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
102827 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102828 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
102829 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
102830 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
102831 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
102832 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102833 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
102834 // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>) => (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
102835 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
102836 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
102837 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
102838 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
102839 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
102840 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
102841 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102842 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
102843 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
102844 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
102845 GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
102846 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
102847 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
102848 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102849 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
102850 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
102851 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102852 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
102853 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
102854 GIR_AddImm8, /*InsnID*/3, /*Imm*/7,
102855 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
102856 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
102857 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
102858 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
102859 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102860 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
102861 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
102862 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
102863 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
102864 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102865 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
102866 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
102867 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
102868 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
102869 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102870 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
102871 GIR_RootConstrainSelectedInstOperands,
102872 // GIR_Coverage, 5978,
102873 GIR_EraseRootFromParent_Done,
102874 // Label 5831: @275660
102875 GIM_Try, /*On fail goto*//*Label 5832*/ GIMT_Encode4(275849), // Rule ID 5979 //
102876 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
102877 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102878 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
102879 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102880 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
102881 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
102882 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
102883 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
102884 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102885 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
102886 // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>) => (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
102887 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
102888 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
102889 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
102890 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
102891 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
102892 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
102893 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102894 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
102895 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
102896 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
102897 GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
102898 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
102899 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
102900 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102901 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
102902 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
102903 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102904 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
102905 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
102906 GIR_AddImm8, /*InsnID*/3, /*Imm*/7,
102907 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
102908 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
102909 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
102910 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
102911 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102912 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
102913 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
102914 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
102915 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
102916 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102917 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
102918 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
102919 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
102920 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
102921 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102922 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
102923 GIR_RootConstrainSelectedInstOperands,
102924 // GIR_Coverage, 5979,
102925 GIR_EraseRootFromParent_Done,
102926 // Label 5832: @275849
102927 GIM_Try, /*On fail goto*//*Label 5833*/ GIMT_Encode4(276082), // Rule ID 5976 //
102928 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
102929 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102930 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
102931 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102932 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
102933 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
102934 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
102935 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
102936 GIM_CheckIsSafeToFold, /*NumInsns*/1,
102937 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
102938 // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>) => (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv8i8_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
102939 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
102940 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
102941 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
102942 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
102943 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
102944 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
102945 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s8,
102946 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
102947 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102948 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
102949 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
102950 GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
102951 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
102952 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
102953 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102954 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
102955 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
102956 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102957 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
102958 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
102959 GIR_AddImm8, /*InsnID*/5, /*Imm*/1,
102960 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
102961 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
102962 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
102963 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i8_shift),
102964 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102965 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
102966 GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
102967 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
102968 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
102969 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102970 GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
102971 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
102972 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
102973 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
102974 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102975 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
102976 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
102977 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
102978 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
102979 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
102980 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
102981 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
102982 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
102983 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
102984 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
102985 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
102986 GIR_RootConstrainSelectedInstOperands,
102987 // GIR_Coverage, 5976,
102988 GIR_EraseRootFromParent_Done,
102989 // Label 5833: @276082
102990 GIM_Try, /*On fail goto*//*Label 5834*/ GIMT_Encode4(276315), // Rule ID 5977 //
102991 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
102992 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
102993 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
102994 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
102995 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
102996 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
102997 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
102998 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
102999 GIM_CheckIsSafeToFold, /*NumInsns*/1,
103000 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
103001 // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>) => (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv8i8_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
103002 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
103003 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
103004 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
103005 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
103006 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
103007 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
103008 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s8,
103009 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
103010 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103011 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
103012 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
103013 GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
103014 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
103015 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
103016 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103017 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
103018 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
103019 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103020 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
103021 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
103022 GIR_AddImm8, /*InsnID*/5, /*Imm*/1,
103023 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103024 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
103025 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
103026 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i8_shift),
103027 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103028 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
103029 GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
103030 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
103031 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
103032 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103033 GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
103034 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103035 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
103036 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
103037 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103038 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
103039 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
103040 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
103041 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
103042 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103043 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
103044 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
103045 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
103046 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
103047 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103048 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103049 GIR_RootConstrainSelectedInstOperands,
103050 // GIR_Coverage, 5977,
103051 GIR_EraseRootFromParent_Done,
103052 // Label 5834: @276315
103053 GIM_Try, /*On fail goto*//*Label 5835*/ GIMT_Encode4(276499), // Rule ID 5980 //
103054 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
103055 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
103056 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
103057 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
103058 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
103059 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
103060 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
103061 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
103062 GIM_CheckIsSafeToFold, /*NumInsns*/1,
103063 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
103064 // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>) => (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
103065 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
103066 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
103067 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
103068 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
103069 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
103070 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
103071 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103072 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
103073 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
103074 GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
103075 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
103076 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
103077 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103078 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
103079 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
103080 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103081 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
103082 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
103083 GIR_AddImm8, /*InsnID*/3, /*Imm*/7,
103084 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103085 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
103086 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
103087 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
103088 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103089 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
103090 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
103091 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
103092 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
103093 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103094 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
103095 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
103096 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
103097 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
103098 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103099 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103100 GIR_RootConstrainSelectedInstOperands,
103101 // GIR_Coverage, 5980,
103102 GIR_EraseRootFromParent_Done,
103103 // Label 5835: @276499
103104 GIM_Try, /*On fail goto*//*Label 5836*/ GIMT_Encode4(276683), // Rule ID 5981 //
103105 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
103106 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
103107 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
103108 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
103109 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
103110 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
103111 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
103112 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
103113 GIM_CheckIsSafeToFold, /*NumInsns*/1,
103114 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
103115 // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>) => (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
103116 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
103117 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
103118 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
103119 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
103120 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
103121 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
103122 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103123 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
103124 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
103125 GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
103126 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
103127 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
103128 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103129 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
103130 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
103131 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103132 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
103133 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
103134 GIR_AddImm8, /*InsnID*/3, /*Imm*/7,
103135 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103136 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
103137 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
103138 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
103139 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103140 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
103141 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
103142 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
103143 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
103144 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103145 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
103146 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
103147 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
103148 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
103149 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103150 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103151 GIR_RootConstrainSelectedInstOperands,
103152 // GIR_Coverage, 5981,
103153 GIR_EraseRootFromParent_Done,
103154 // Label 5836: @276683
103155 GIM_Try, /*On fail goto*//*Label 5837*/ GIMT_Encode4(276763), // Rule ID 4968 //
103156 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
103157 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
103158 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
103159 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
103160 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
103161 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
103162 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
103163 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
103164 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
103165 GIM_CheckIsSafeToFold, /*NumInsns*/1,
103166 // (sint_to_fp:{ *:[f32] } (vector_extract:{ *:[i32] } FPR128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] })) => (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } FPR128:{ *:[v4i32] }:$Rn, ssub:{ *:[i32] }))
103167 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
103168 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
103169 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103170 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rn
103171 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
103172 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
103173 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
103174 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103175 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103176 GIR_RootConstrainSelectedInstOperands,
103177 // GIR_Coverage, 4968,
103178 GIR_EraseRootFromParent_Done,
103179 // Label 5837: @276763
103180 GIM_Try, /*On fail goto*//*Label 5838*/ GIMT_Encode4(276820), // Rule ID 4951 //
103181 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
103182 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
103183 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
103184 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
103185 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
103186 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
103187 GIM_CheckIsSafeToFold, /*NumInsns*/1,
103188 // (sint_to_fp:{ *:[f32] } (fp_to_sint:{ *:[i32] } f32:{ *:[f32] }:$Rn)) => (SCVTFv1i32:{ *:[f32] } (FCVTZSv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn))
103189 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
103190 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i32),
103191 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103192 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
103193 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
103194 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
103195 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103196 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103197 GIR_RootConstrainSelectedInstOperands,
103198 // GIR_Coverage, 4951,
103199 GIR_EraseRootFromParent_Done,
103200 // Label 5838: @276820
103201 GIM_Try, /*On fail goto*//*Label 5839*/ GIMT_Encode4(276850), // Rule ID 455 //
103202 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
103203 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
103204 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
103205 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
103206 // (sint_to_fp:{ *:[f32] } GPR32:{ *:[i32] }:$Rn) => (SCVTFUWSri:{ *:[f32] } GPR32:{ *:[i32] }:$Rn)
103207 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFUWSri),
103208 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
103209 GIR_RootConstrainSelectedInstOperands,
103210 // GIR_Coverage, 455,
103211 GIR_Done,
103212 // Label 5839: @276850
103213 GIM_Try, /*On fail goto*//*Label 5840*/ GIMT_Encode4(276880), // Rule ID 461 //
103214 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
103215 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
103216 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
103217 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
103218 // (sint_to_fp:{ *:[f32] } GPR64:{ *:[i64] }:$Rn) => (SCVTFUXSri:{ *:[f32] } GPR64:{ *:[i64] }:$Rn)
103219 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFUXSri),
103220 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
103221 GIR_RootConstrainSelectedInstOperands,
103222 // GIR_Coverage, 461,
103223 GIR_Done,
103224 // Label 5840: @276880
103225 GIM_Reject,
103226 // Label 5819: @276881
103227 GIM_Try, /*On fail goto*//*Label 5841*/ GIMT_Encode4(277067), // Rule ID 5986 //
103228 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
103229 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
103230 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
103231 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
103232 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
103233 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
103234 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
103235 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
103236 GIM_CheckIsSafeToFold, /*NumInsns*/1,
103237 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
103238 // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$ext), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
103239 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
103240 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
103241 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
103242 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
103243 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
103244 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
103245 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103246 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
103247 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
103248 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
103249 GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
103250 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
103251 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
103252 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103253 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
103254 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
103255 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103256 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
103257 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
103258 GIR_AddImm8, /*InsnID*/3, /*Imm*/15,
103259 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103260 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
103261 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
103262 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
103263 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103264 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
103265 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
103266 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
103267 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
103268 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103269 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
103270 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103271 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
103272 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
103273 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103274 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103275 GIR_RootConstrainSelectedInstOperands,
103276 // GIR_Coverage, 5986,
103277 GIR_EraseRootFromParent_Done,
103278 // Label 5841: @277067
103279 GIM_Try, /*On fail goto*//*Label 5842*/ GIMT_Encode4(277253), // Rule ID 5987 //
103280 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
103281 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
103282 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
103283 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
103284 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
103285 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
103286 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
103287 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
103288 GIM_CheckIsSafeToFold, /*NumInsns*/1,
103289 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
103290 // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$ext), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
103291 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
103292 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
103293 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
103294 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
103295 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
103296 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
103297 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103298 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
103299 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
103300 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
103301 GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
103302 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
103303 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
103304 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103305 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
103306 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
103307 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103308 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
103309 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
103310 GIR_AddImm8, /*InsnID*/3, /*Imm*/15,
103311 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103312 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
103313 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
103314 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
103315 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103316 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
103317 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
103318 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
103319 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
103320 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103321 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
103322 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103323 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
103324 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
103325 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103326 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103327 GIR_RootConstrainSelectedInstOperands,
103328 // GIR_Coverage, 5987,
103329 GIR_EraseRootFromParent_Done,
103330 // Label 5842: @277253
103331 GIM_Try, /*On fail goto*//*Label 5843*/ GIMT_Encode4(277491), // Rule ID 5982 //
103332 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
103333 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
103334 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
103335 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
103336 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
103337 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
103338 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
103339 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
103340 GIM_CheckIsSafeToFold, /*NumInsns*/1,
103341 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
103342 // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
103343 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
103344 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
103345 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
103346 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
103347 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
103348 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
103349 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
103350 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
103351 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103352 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
103353 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
103354 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
103355 GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
103356 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
103357 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
103358 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103359 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
103360 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
103361 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103362 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
103363 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
103364 GIR_AddImm8, /*InsnID*/5, /*Imm*/7,
103365 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103366 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
103367 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
103368 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
103369 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103370 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
103371 GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
103372 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
103373 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
103374 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103375 GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
103376 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103377 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
103378 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
103379 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103380 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
103381 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
103382 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
103383 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
103384 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103385 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
103386 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103387 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
103388 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
103389 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103390 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103391 GIR_RootConstrainSelectedInstOperands,
103392 // GIR_Coverage, 5982,
103393 GIR_EraseRootFromParent_Done,
103394 // Label 5843: @277491
103395 GIM_Try, /*On fail goto*//*Label 5844*/ GIMT_Encode4(277729), // Rule ID 5983 //
103396 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
103397 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
103398 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
103399 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
103400 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
103401 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
103402 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
103403 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
103404 GIM_CheckIsSafeToFold, /*NumInsns*/1,
103405 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
103406 // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
103407 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
103408 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
103409 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
103410 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
103411 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
103412 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
103413 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
103414 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
103415 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103416 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
103417 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
103418 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
103419 GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
103420 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
103421 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
103422 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103423 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
103424 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
103425 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103426 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
103427 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
103428 GIR_AddImm8, /*InsnID*/5, /*Imm*/7,
103429 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103430 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
103431 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
103432 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
103433 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103434 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
103435 GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
103436 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
103437 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
103438 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103439 GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
103440 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103441 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
103442 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
103443 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103444 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
103445 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
103446 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
103447 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
103448 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103449 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
103450 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103451 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
103452 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
103453 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103454 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103455 GIR_RootConstrainSelectedInstOperands,
103456 // GIR_Coverage, 5983,
103457 GIR_EraseRootFromParent_Done,
103458 // Label 5844: @277729
103459 GIM_Try, /*On fail goto*//*Label 5845*/ GIMT_Encode4(277910), // Rule ID 5988 //
103460 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
103461 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
103462 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
103463 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
103464 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
103465 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
103466 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
103467 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
103468 GIM_CheckIsSafeToFold, /*NumInsns*/1,
103469 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
103470 // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
103471 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
103472 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
103473 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
103474 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
103475 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
103476 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
103477 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103478 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
103479 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
103480 GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
103481 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
103482 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
103483 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103484 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
103485 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
103486 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103487 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
103488 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
103489 GIR_AddImm8, /*InsnID*/3, /*Imm*/15,
103490 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103491 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
103492 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
103493 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
103494 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103495 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
103496 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
103497 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
103498 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
103499 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103500 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
103501 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103502 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
103503 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
103504 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103505 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103506 GIR_RootConstrainSelectedInstOperands,
103507 // GIR_Coverage, 5988,
103508 GIR_EraseRootFromParent_Done,
103509 // Label 5845: @277910
103510 GIM_Try, /*On fail goto*//*Label 5846*/ GIMT_Encode4(278091), // Rule ID 5989 //
103511 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
103512 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
103513 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
103514 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
103515 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
103516 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
103517 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
103518 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
103519 GIM_CheckIsSafeToFold, /*NumInsns*/1,
103520 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
103521 // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
103522 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
103523 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
103524 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
103525 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
103526 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
103527 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
103528 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103529 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
103530 GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
103531 GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
103532 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
103533 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
103534 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103535 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
103536 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
103537 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103538 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
103539 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
103540 GIR_AddImm8, /*InsnID*/3, /*Imm*/15,
103541 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103542 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
103543 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
103544 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
103545 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103546 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
103547 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
103548 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
103549 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
103550 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103551 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
103552 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103553 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
103554 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
103555 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103556 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103557 GIR_RootConstrainSelectedInstOperands,
103558 // GIR_Coverage, 5989,
103559 GIR_EraseRootFromParent_Done,
103560 // Label 5846: @278091
103561 GIM_Try, /*On fail goto*//*Label 5847*/ GIMT_Encode4(278324), // Rule ID 5984 //
103562 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
103563 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
103564 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
103565 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
103566 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
103567 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
103568 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
103569 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
103570 GIM_CheckIsSafeToFold, /*NumInsns*/1,
103571 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
103572 // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
103573 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
103574 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
103575 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
103576 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
103577 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
103578 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
103579 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
103580 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
103581 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103582 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
103583 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
103584 GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
103585 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
103586 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
103587 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103588 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
103589 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
103590 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103591 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
103592 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
103593 GIR_AddImm8, /*InsnID*/5, /*Imm*/7,
103594 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103595 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
103596 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
103597 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
103598 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103599 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
103600 GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
103601 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
103602 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
103603 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103604 GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
103605 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103606 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
103607 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
103608 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103609 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
103610 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
103611 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
103612 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
103613 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103614 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
103615 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103616 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
103617 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
103618 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103619 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103620 GIR_RootConstrainSelectedInstOperands,
103621 // GIR_Coverage, 5984,
103622 GIR_EraseRootFromParent_Done,
103623 // Label 5847: @278324
103624 GIM_Try, /*On fail goto*//*Label 5848*/ GIMT_Encode4(278557), // Rule ID 5985 //
103625 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
103626 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
103627 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
103628 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
103629 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
103630 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
103631 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
103632 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
103633 GIM_CheckIsSafeToFold, /*NumInsns*/1,
103634 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
103635 // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
103636 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
103637 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
103638 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
103639 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
103640 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
103641 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
103642 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
103643 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
103644 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103645 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
103646 GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
103647 GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
103648 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
103649 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
103650 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103651 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
103652 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
103653 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103654 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
103655 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
103656 GIR_AddImm8, /*InsnID*/5, /*Imm*/7,
103657 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103658 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
103659 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
103660 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
103661 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103662 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
103663 GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
103664 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
103665 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
103666 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103667 GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
103668 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103669 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
103670 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
103671 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103672 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
103673 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
103674 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
103675 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
103676 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103677 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
103678 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103679 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
103680 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
103681 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103682 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103683 GIR_RootConstrainSelectedInstOperands,
103684 // GIR_Coverage, 5985,
103685 GIR_EraseRootFromParent_Done,
103686 // Label 5848: @278557
103687 GIM_Try, /*On fail goto*//*Label 5849*/ GIMT_Encode4(278637), // Rule ID 4970 //
103688 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
103689 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
103690 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
103691 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
103692 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
103693 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
103694 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
103695 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
103696 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
103697 GIM_CheckIsSafeToFold, /*NumInsns*/1,
103698 // (sint_to_fp:{ *:[f64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] })) => (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, dsub:{ *:[i32] }))
103699 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
103700 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
103701 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103702 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
103703 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
103704 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
103705 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
103706 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103707 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103708 GIR_RootConstrainSelectedInstOperands,
103709 // GIR_Coverage, 4970,
103710 GIR_EraseRootFromParent_Done,
103711 // Label 5849: @278637
103712 GIM_Try, /*On fail goto*//*Label 5850*/ GIMT_Encode4(278694), // Rule ID 4947 //
103713 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
103714 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
103715 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
103716 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
103717 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
103718 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
103719 GIM_CheckIsSafeToFold, /*NumInsns*/1,
103720 // (sint_to_fp:{ *:[f64] } (fp_to_sint:{ *:[i64] } f64:{ *:[f64] }:$Rn)) => (SCVTFv1i64:{ *:[f64] } (FCVTZSv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn))
103721 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
103722 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i64),
103723 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103724 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
103725 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
103726 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
103727 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103728 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103729 GIR_RootConstrainSelectedInstOperands,
103730 // GIR_Coverage, 4947,
103731 GIR_EraseRootFromParent_Done,
103732 // Label 5850: @278694
103733 GIM_Try, /*On fail goto*//*Label 5851*/ GIMT_Encode4(278724), // Rule ID 457 //
103734 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
103735 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
103736 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
103737 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
103738 // (sint_to_fp:{ *:[f64] } GPR32:{ *:[i32] }:$Rn) => (SCVTFUWDri:{ *:[f64] } GPR32:{ *:[i32] }:$Rn)
103739 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFUWDri),
103740 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
103741 GIR_RootConstrainSelectedInstOperands,
103742 // GIR_Coverage, 457,
103743 GIR_Done,
103744 // Label 5851: @278724
103745 GIM_Try, /*On fail goto*//*Label 5852*/ GIMT_Encode4(278754), // Rule ID 463 //
103746 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
103747 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
103748 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
103749 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
103750 // (sint_to_fp:{ *:[f64] } GPR64:{ *:[i64] }:$Rn) => (SCVTFUXDri:{ *:[f64] } GPR64:{ *:[i64] }:$Rn)
103751 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFUXDri),
103752 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
103753 GIR_RootConstrainSelectedInstOperands,
103754 // GIR_Coverage, 463,
103755 GIR_Done,
103756 // Label 5852: @278754
103757 GIM_Reject,
103758 // Label 5820: @278755
103759 GIM_Try, /*On fail goto*//*Label 5853*/ GIMT_Encode4(278785), // Rule ID 1004 //
103760 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
103761 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
103762 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
103763 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
103764 // (sint_to_fp:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn) => (SCVTFv2f32:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn)
103765 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv2f32),
103766 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
103767 GIR_RootConstrainSelectedInstOperands,
103768 // GIR_Coverage, 1004,
103769 GIR_Done,
103770 // Label 5853: @278785
103771 GIM_Try, /*On fail goto*//*Label 5854*/ GIMT_Encode4(278828), // Rule ID 12358 //
103772 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
103773 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
103774 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
103775 // (sint_to_fp:{ *:[v2f32] } v2i64:{ *:[v2i64] }:$src) => (FCVTNv2i32:{ *:[v2f32] } (SCVTFv2f64:{ *:[f128] } V128:{ *:[v2i64] }:$src))
103776 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
103777 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv2f64),
103778 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103779 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
103780 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
103781 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv2i32),
103782 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103783 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103784 GIR_RootConstrainSelectedInstOperands,
103785 // GIR_Coverage, 12358,
103786 GIR_EraseRootFromParent_Done,
103787 // Label 5854: @278828
103788 GIM_Reject,
103789 // Label 5821: @278829
103790 GIM_Try, /*On fail goto*//*Label 5855*/ GIMT_Encode4(278859), // Rule ID 1008 //
103791 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
103792 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
103793 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
103794 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
103795 // (sint_to_fp:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn) => (SCVTFv2f64:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn)
103796 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv2f64),
103797 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
103798 GIR_RootConstrainSelectedInstOperands,
103799 // GIR_Coverage, 1008,
103800 GIR_Done,
103801 // Label 5855: @278859
103802 GIM_Try, /*On fail goto*//*Label 5856*/ GIMT_Encode4(278905), // Rule ID 12356 //
103803 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
103804 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
103805 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
103806 // (sint_to_fp:{ *:[v2f64] } v2i32:{ *:[v2i32] }:$src) => (SCVTFv2f64:{ *:[v2f64] } (SSHLLv2i32_shift:{ *:[f128] } V64:{ *:[v2i32] }:$src, 0:{ *:[i32] }))
103807 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
103808 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
103809 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103810 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
103811 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
103812 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
103813 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv2f64),
103814 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103815 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103816 GIR_RootConstrainSelectedInstOperands,
103817 // GIR_Coverage, 12356,
103818 GIR_EraseRootFromParent_Done,
103819 // Label 5856: @278905
103820 GIM_Reject,
103821 // Label 5822: @278906
103822 GIM_Try, /*On fail goto*//*Label 5857*/ GIMT_Encode4(278936), // Rule ID 1000 //
103823 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
103824 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
103825 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
103826 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
103827 // (sint_to_fp:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn) => (SCVTFv4f16:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn)
103828 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv4f16),
103829 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
103830 GIR_RootConstrainSelectedInstOperands,
103831 // GIR_Coverage, 1000,
103832 GIR_Done,
103833 // Label 5857: @278936
103834 GIM_Reject,
103835 // Label 5823: @278937
103836 GIM_Try, /*On fail goto*//*Label 5858*/ GIMT_Encode4(278967), // Rule ID 1006 //
103837 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
103838 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
103839 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
103840 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
103841 // (sint_to_fp:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn) => (SCVTFv4f32:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn)
103842 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv4f32),
103843 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
103844 GIR_RootConstrainSelectedInstOperands,
103845 // GIR_Coverage, 1006,
103846 GIR_Done,
103847 // Label 5858: @278967
103848 GIM_Reject,
103849 // Label 5824: @278968
103850 GIM_Try, /*On fail goto*//*Label 5859*/ GIMT_Encode4(278998), // Rule ID 1002 //
103851 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
103852 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
103853 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
103854 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
103855 // (sint_to_fp:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn) => (SCVTFv8f16:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn)
103856 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv8f16),
103857 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
103858 GIR_RootConstrainSelectedInstOperands,
103859 // GIR_Coverage, 1002,
103860 GIR_Done,
103861 // Label 5859: @278998
103862 GIM_Reject,
103863 // Label 5825: @278999
103864 GIM_Reject,
103865 // Label 64: @279000
103866 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 5868*/ GIMT_Encode4(282654),
103867 /*GILLT_s16*//*Label 5860*/ GIMT_Encode4(279051),
103868 /*GILLT_s32*//*Label 5861*/ GIMT_Encode4(279276),
103869 /*GILLT_s64*//*Label 5862*/ GIMT_Encode4(280574), GIMT_Encode4(0),
103870 /*GILLT_v2s32*//*Label 5863*/ GIMT_Encode4(282410),
103871 /*GILLT_v2s64*//*Label 5864*/ GIMT_Encode4(282484),
103872 /*GILLT_v4s16*//*Label 5865*/ GIMT_Encode4(282561),
103873 /*GILLT_v4s32*//*Label 5866*/ GIMT_Encode4(282592), GIMT_Encode4(0),
103874 /*GILLT_v8s16*//*Label 5867*/ GIMT_Encode4(282623),
103875 // Label 5860: @279051
103876 GIM_Try, /*On fail goto*//*Label 5869*/ GIMT_Encode4(279158), // Rule ID 4973 //
103877 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
103878 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
103879 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
103880 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
103881 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
103882 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
103883 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
103884 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
103885 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
103886 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
103887 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
103888 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
103889 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
103890 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
103891 GIM_CheckIsSafeToFold, /*NumInsns*/2,
103892 // (uint_to_fp:{ *:[f16] } (and:{ *:[i32] } (vector_extract:{ *:[i32] } FPR128:{ *:[v8i16] }:$Rn, 0:{ *:[i64] }), 65535:{ *:[i32] })) => (UCVTFv1i16:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR128:{ *:[v8i16] }:$Rn, hsub:{ *:[i32] }))
103893 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
103894 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
103895 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103896 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
103897 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
103898 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
103899 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i16),
103900 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103901 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103902 GIR_RootConstrainSelectedInstOperands,
103903 // GIR_Coverage, 4973,
103904 GIR_EraseRootFromParent_Done,
103905 // Label 5869: @279158
103906 GIM_Try, /*On fail goto*//*Label 5870*/ GIMT_Encode4(279215), // Rule ID 4967 //
103907 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
103908 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
103909 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
103910 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
103911 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
103912 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
103913 GIM_CheckIsSafeToFold, /*NumInsns*/1,
103914 // (uint_to_fp:{ *:[f16] } (fp_to_uint:{ *:[i32] } f16:{ *:[f16] }:$Rn)) => (UCVTFv1i16:{ *:[f16] } (FCVTZUv1f16:{ *:[f16] } f16:{ *:[f16] }:$Rn))
103915 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
103916 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1f16),
103917 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103918 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
103919 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
103920 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i16),
103921 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103922 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103923 GIR_RootConstrainSelectedInstOperands,
103924 // GIR_Coverage, 4967,
103925 GIR_EraseRootFromParent_Done,
103926 // Label 5870: @279215
103927 GIM_Try, /*On fail goto*//*Label 5871*/ GIMT_Encode4(279245), // Rule ID 477 //
103928 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
103929 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
103930 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
103931 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
103932 // (uint_to_fp:{ *:[f16] } GPR32:{ *:[i32] }:$Rn) => (UCVTFUWHri:{ *:[f16] } GPR32:{ *:[i32] }:$Rn)
103933 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFUWHri),
103934 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
103935 GIR_RootConstrainSelectedInstOperands,
103936 // GIR_Coverage, 477,
103937 GIR_Done,
103938 // Label 5871: @279245
103939 GIM_Try, /*On fail goto*//*Label 5872*/ GIMT_Encode4(279275), // Rule ID 483 //
103940 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
103941 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
103942 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
103943 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
103944 // (uint_to_fp:{ *:[f16] } GPR64:{ *:[i64] }:$Rn) => (UCVTFUXHri:{ *:[f16] } GPR64:{ *:[i64] }:$Rn)
103945 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFUXHri),
103946 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
103947 GIR_RootConstrainSelectedInstOperands,
103948 // GIR_Coverage, 483,
103949 GIR_Done,
103950 // Label 5872: @279275
103951 GIM_Reject,
103952 // Label 5861: @279276
103953 GIM_Try, /*On fail goto*//*Label 5873*/ GIMT_Encode4(279416), // Rule ID 4974 //
103954 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
103955 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
103956 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
103957 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
103958 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
103959 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
103960 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
103961 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
103962 GIM_CheckIsSafeToFold, /*NumInsns*/1,
103963 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
103964 // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] }))
103965 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
103966 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
103967 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
103968 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
103969 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103970 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
103971 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
103972 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
103973 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
103974 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
103975 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
103976 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103977 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
103978 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
103979 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
103980 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
103981 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
103982 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
103983 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
103984 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
103985 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
103986 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
103987 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
103988 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
103989 GIR_RootConstrainSelectedInstOperands,
103990 // GIR_Coverage, 4974,
103991 GIR_EraseRootFromParent_Done,
103992 // Label 5873: @279416
103993 GIM_Try, /*On fail goto*//*Label 5874*/ GIMT_Encode4(279556), // Rule ID 4975 //
103994 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
103995 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
103996 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
103997 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
103998 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
103999 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
104000 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
104001 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
104002 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104003 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
104004 // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] }))
104005 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
104006 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
104007 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
104008 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
104009 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104010 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
104011 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
104012 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
104013 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
104014 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
104015 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
104016 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104017 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
104018 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
104019 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104020 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
104021 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
104022 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
104023 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
104024 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
104025 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
104026 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
104027 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104028 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104029 GIR_RootConstrainSelectedInstOperands,
104030 // GIR_Coverage, 4975,
104031 GIR_EraseRootFromParent_Done,
104032 // Label 5874: @279556
104033 GIM_Try, /*On fail goto*//*Label 5875*/ GIMT_Encode4(279696), // Rule ID 4978 //
104034 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104035 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104036 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
104037 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104038 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
104039 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
104040 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
104041 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
104042 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104043 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
104044 // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] }))
104045 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
104046 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
104047 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
104048 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
104049 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104050 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
104051 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
104052 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
104053 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
104054 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
104055 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
104056 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104057 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
104058 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
104059 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104060 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
104061 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
104062 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
104063 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
104064 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
104065 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
104066 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
104067 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104068 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104069 GIR_RootConstrainSelectedInstOperands,
104070 // GIR_Coverage, 4978,
104071 GIR_EraseRootFromParent_Done,
104072 // Label 5875: @279696
104073 GIM_Try, /*On fail goto*//*Label 5876*/ GIMT_Encode4(279836), // Rule ID 4979 //
104074 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104075 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104076 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
104077 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104078 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
104079 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
104080 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
104081 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
104082 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104083 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
104084 // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] }))
104085 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
104086 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
104087 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
104088 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
104089 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104090 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
104091 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
104092 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
104093 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
104094 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
104095 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
104096 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104097 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
104098 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
104099 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104100 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
104101 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
104102 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
104103 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
104104 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
104105 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
104106 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
104107 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104108 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104109 GIR_RootConstrainSelectedInstOperands,
104110 // GIR_Coverage, 4979,
104111 GIR_EraseRootFromParent_Done,
104112 // Label 5876: @279836
104113 GIM_Try, /*On fail goto*//*Label 5877*/ GIMT_Encode4(279971), // Rule ID 4976 //
104114 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104115 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104116 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
104117 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104118 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
104119 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
104120 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
104121 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
104122 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104123 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
104124 // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] }))
104125 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
104126 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
104127 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
104128 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
104129 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104130 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
104131 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
104132 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
104133 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
104134 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
104135 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104136 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
104137 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
104138 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104139 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
104140 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
104141 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
104142 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
104143 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
104144 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
104145 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
104146 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104147 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104148 GIR_RootConstrainSelectedInstOperands,
104149 // GIR_Coverage, 4976,
104150 GIR_EraseRootFromParent_Done,
104151 // Label 5877: @279971
104152 GIM_Try, /*On fail goto*//*Label 5878*/ GIMT_Encode4(280106), // Rule ID 4977 //
104153 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104154 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104155 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
104156 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104157 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
104158 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
104159 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
104160 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
104161 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104162 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
104163 // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] }))
104164 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
104165 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
104166 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
104167 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
104168 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104169 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
104170 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
104171 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
104172 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
104173 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
104174 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104175 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
104176 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
104177 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104178 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
104179 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
104180 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
104181 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
104182 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
104183 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
104184 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
104185 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104186 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104187 GIR_RootConstrainSelectedInstOperands,
104188 // GIR_Coverage, 4977,
104189 GIR_EraseRootFromParent_Done,
104190 // Label 5878: @280106
104191 GIM_Try, /*On fail goto*//*Label 5879*/ GIMT_Encode4(280241), // Rule ID 4980 //
104192 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104193 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104194 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
104195 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104196 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
104197 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
104198 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
104199 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
104200 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104201 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
104202 // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] }))
104203 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
104204 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
104205 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
104206 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
104207 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104208 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
104209 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
104210 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
104211 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
104212 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
104213 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104214 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
104215 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
104216 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104217 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
104218 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
104219 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
104220 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
104221 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
104222 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
104223 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
104224 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104225 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104226 GIR_RootConstrainSelectedInstOperands,
104227 // GIR_Coverage, 4980,
104228 GIR_EraseRootFromParent_Done,
104229 // Label 5879: @280241
104230 GIM_Try, /*On fail goto*//*Label 5880*/ GIMT_Encode4(280376), // Rule ID 4981 //
104231 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104232 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104233 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
104234 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104235 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
104236 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
104237 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
104238 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
104239 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104240 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
104241 // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>) => (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] }))
104242 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
104243 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
104244 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
104245 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
104246 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104247 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
104248 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
104249 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
104250 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
104251 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
104252 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104253 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
104254 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
104255 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104256 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
104257 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
104258 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
104259 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
104260 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
104261 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
104262 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
104263 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104264 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104265 GIR_RootConstrainSelectedInstOperands,
104266 // GIR_Coverage, 4981,
104267 GIR_EraseRootFromParent_Done,
104268 // Label 5880: @280376
104269 GIM_Try, /*On fail goto*//*Label 5881*/ GIMT_Encode4(280456), // Rule ID 4969 //
104270 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104271 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104272 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
104273 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104274 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
104275 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
104276 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
104277 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
104278 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
104279 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104280 // (uint_to_fp:{ *:[f32] } (vector_extract:{ *:[i32] } FPR128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] })) => (UCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } FPR128:{ *:[v4i32] }:$Rn, ssub:{ *:[i32] }))
104281 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
104282 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
104283 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104284 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rn
104285 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
104286 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
104287 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
104288 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104289 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104290 GIR_RootConstrainSelectedInstOperands,
104291 // GIR_Coverage, 4969,
104292 GIR_EraseRootFromParent_Done,
104293 // Label 5881: @280456
104294 GIM_Try, /*On fail goto*//*Label 5882*/ GIMT_Encode4(280513), // Rule ID 4959 //
104295 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104296 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104297 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
104298 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104299 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
104300 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
104301 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104302 // (uint_to_fp:{ *:[f32] } (fp_to_uint:{ *:[i32] } f32:{ *:[f32] }:$Rn)) => (UCVTFv1i32:{ *:[f32] } (FCVTZUv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn))
104303 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
104304 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i32),
104305 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104306 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
104307 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
104308 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
104309 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104310 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104311 GIR_RootConstrainSelectedInstOperands,
104312 // GIR_Coverage, 4959,
104313 GIR_EraseRootFromParent_Done,
104314 // Label 5882: @280513
104315 GIM_Try, /*On fail goto*//*Label 5883*/ GIMT_Encode4(280543), // Rule ID 479 //
104316 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
104317 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104318 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
104319 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
104320 // (uint_to_fp:{ *:[f32] } GPR32:{ *:[i32] }:$Rn) => (UCVTFUWSri:{ *:[f32] } GPR32:{ *:[i32] }:$Rn)
104321 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFUWSri),
104322 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
104323 GIR_RootConstrainSelectedInstOperands,
104324 // GIR_Coverage, 479,
104325 GIR_Done,
104326 // Label 5883: @280543
104327 GIM_Try, /*On fail goto*//*Label 5884*/ GIMT_Encode4(280573), // Rule ID 485 //
104328 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
104329 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
104330 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
104331 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
104332 // (uint_to_fp:{ *:[f32] } GPR64:{ *:[i64] }:$Rn) => (UCVTFUXSri:{ *:[f32] } GPR64:{ *:[i64] }:$Rn)
104333 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFUXSri),
104334 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
104335 GIR_RootConstrainSelectedInstOperands,
104336 // GIR_Coverage, 485,
104337 GIR_Done,
104338 // Label 5884: @280573
104339 GIM_Reject,
104340 // Label 5862: @280574
104341 GIM_Try, /*On fail goto*//*Label 5885*/ GIMT_Encode4(280711), // Rule ID 4990 //
104342 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104343 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104344 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104345 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104346 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
104347 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
104348 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
104349 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
104350 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104351 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
104352 // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] }))
104353 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
104354 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
104355 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
104356 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
104357 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104358 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
104359 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
104360 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
104361 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
104362 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
104363 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
104364 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104365 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
104366 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
104367 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104368 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
104369 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
104370 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
104371 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
104372 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
104373 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
104374 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
104375 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104376 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104377 GIR_RootConstrainSelectedInstOperands,
104378 // GIR_Coverage, 4990,
104379 GIR_EraseRootFromParent_Done,
104380 // Label 5885: @280711
104381 GIM_Try, /*On fail goto*//*Label 5886*/ GIMT_Encode4(280848), // Rule ID 4991 //
104382 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104383 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104384 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104385 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104386 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
104387 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
104388 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
104389 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
104390 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104391 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
104392 // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] }))
104393 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
104394 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
104395 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
104396 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
104397 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104398 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
104399 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
104400 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
104401 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
104402 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
104403 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
104404 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104405 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
104406 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
104407 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104408 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
104409 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
104410 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
104411 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
104412 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
104413 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
104414 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
104415 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104416 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104417 GIR_RootConstrainSelectedInstOperands,
104418 // GIR_Coverage, 4991,
104419 GIR_EraseRootFromParent_Done,
104420 // Label 5886: @280848
104421 GIM_Try, /*On fail goto*//*Label 5887*/ GIMT_Encode4(280988), // Rule ID 4982 //
104422 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104423 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104424 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104425 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104426 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
104427 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
104428 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
104429 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
104430 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104431 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
104432 // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] }))
104433 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
104434 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
104435 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
104436 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
104437 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104438 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
104439 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
104440 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
104441 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
104442 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
104443 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
104444 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104445 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
104446 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
104447 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104448 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
104449 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
104450 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
104451 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
104452 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
104453 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
104454 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
104455 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104456 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104457 GIR_RootConstrainSelectedInstOperands,
104458 // GIR_Coverage, 4982,
104459 GIR_EraseRootFromParent_Done,
104460 // Label 5887: @280988
104461 GIM_Try, /*On fail goto*//*Label 5888*/ GIMT_Encode4(281128), // Rule ID 4983 //
104462 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104463 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104464 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104465 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104466 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
104467 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
104468 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
104469 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
104470 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104471 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
104472 // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] }))
104473 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
104474 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
104475 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
104476 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
104477 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104478 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
104479 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
104480 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
104481 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
104482 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
104483 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
104484 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104485 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
104486 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
104487 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104488 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
104489 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
104490 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
104491 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
104492 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
104493 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
104494 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
104495 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104496 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104497 GIR_RootConstrainSelectedInstOperands,
104498 // GIR_Coverage, 4983,
104499 GIR_EraseRootFromParent_Done,
104500 // Label 5888: @281128
104501 GIM_Try, /*On fail goto*//*Label 5889*/ GIMT_Encode4(281268), // Rule ID 4986 //
104502 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104503 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104504 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104505 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104506 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
104507 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
104508 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
104509 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
104510 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104511 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
104512 // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] }))
104513 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
104514 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
104515 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
104516 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
104517 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104518 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
104519 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
104520 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
104521 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
104522 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
104523 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
104524 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104525 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
104526 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
104527 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104528 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
104529 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
104530 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
104531 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
104532 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
104533 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
104534 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
104535 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104536 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104537 GIR_RootConstrainSelectedInstOperands,
104538 // GIR_Coverage, 4986,
104539 GIR_EraseRootFromParent_Done,
104540 // Label 5889: @281268
104541 GIM_Try, /*On fail goto*//*Label 5890*/ GIMT_Encode4(281408), // Rule ID 4987 //
104542 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104543 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104544 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104545 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104546 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
104547 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
104548 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
104549 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
104550 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104551 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
104552 // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] }))
104553 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
104554 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
104555 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
104556 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
104557 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104558 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
104559 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
104560 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
104561 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
104562 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
104563 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
104564 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104565 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
104566 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
104567 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104568 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
104569 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
104570 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
104571 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
104572 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
104573 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
104574 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
104575 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104576 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104577 GIR_RootConstrainSelectedInstOperands,
104578 // GIR_Coverage, 4987,
104579 GIR_EraseRootFromParent_Done,
104580 // Label 5890: @281408
104581 GIM_Try, /*On fail goto*//*Label 5891*/ GIMT_Encode4(281540), // Rule ID 4992 //
104582 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104583 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104584 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104585 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104586 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
104587 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
104588 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
104589 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
104590 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104591 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
104592 // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] }))
104593 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
104594 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
104595 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
104596 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
104597 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104598 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
104599 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
104600 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
104601 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
104602 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
104603 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104604 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
104605 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
104606 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104607 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
104608 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
104609 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
104610 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
104611 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
104612 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
104613 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
104614 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104615 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104616 GIR_RootConstrainSelectedInstOperands,
104617 // GIR_Coverage, 4992,
104618 GIR_EraseRootFromParent_Done,
104619 // Label 5891: @281540
104620 GIM_Try, /*On fail goto*//*Label 5892*/ GIMT_Encode4(281672), // Rule ID 4993 //
104621 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104622 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104623 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104624 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104625 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
104626 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
104627 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
104628 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
104629 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104630 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
104631 // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] }))
104632 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
104633 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
104634 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
104635 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
104636 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104637 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
104638 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
104639 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
104640 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
104641 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
104642 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104643 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
104644 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
104645 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104646 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
104647 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
104648 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
104649 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
104650 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
104651 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
104652 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
104653 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104654 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104655 GIR_RootConstrainSelectedInstOperands,
104656 // GIR_Coverage, 4993,
104657 GIR_EraseRootFromParent_Done,
104658 // Label 5892: @281672
104659 GIM_Try, /*On fail goto*//*Label 5893*/ GIMT_Encode4(281807), // Rule ID 4984 //
104660 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104661 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104662 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104663 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104664 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
104665 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
104666 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
104667 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
104668 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104669 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
104670 // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] }))
104671 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
104672 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
104673 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
104674 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
104675 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104676 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
104677 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
104678 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
104679 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
104680 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
104681 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104682 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
104683 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
104684 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104685 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
104686 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
104687 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
104688 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
104689 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
104690 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
104691 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
104692 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104693 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104694 GIR_RootConstrainSelectedInstOperands,
104695 // GIR_Coverage, 4984,
104696 GIR_EraseRootFromParent_Done,
104697 // Label 5893: @281807
104698 GIM_Try, /*On fail goto*//*Label 5894*/ GIMT_Encode4(281942), // Rule ID 4985 //
104699 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104700 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104701 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104702 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104703 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
104704 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
104705 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
104706 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
104707 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104708 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
104709 // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] }))
104710 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
104711 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
104712 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
104713 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
104714 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104715 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
104716 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
104717 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
104718 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
104719 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
104720 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104721 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
104722 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
104723 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104724 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
104725 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
104726 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
104727 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
104728 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
104729 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
104730 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
104731 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104732 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104733 GIR_RootConstrainSelectedInstOperands,
104734 // GIR_Coverage, 4985,
104735 GIR_EraseRootFromParent_Done,
104736 // Label 5894: @281942
104737 GIM_Try, /*On fail goto*//*Label 5895*/ GIMT_Encode4(282077), // Rule ID 4988 //
104738 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104739 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104740 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104741 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104742 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
104743 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
104744 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
104745 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
104746 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104747 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
104748 // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] }))
104749 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
104750 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
104751 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
104752 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
104753 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104754 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
104755 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
104756 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
104757 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
104758 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
104759 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104760 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
104761 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
104762 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104763 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
104764 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
104765 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
104766 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
104767 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
104768 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
104769 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
104770 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104771 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104772 GIR_RootConstrainSelectedInstOperands,
104773 // GIR_Coverage, 4988,
104774 GIR_EraseRootFromParent_Done,
104775 // Label 5895: @282077
104776 GIM_Try, /*On fail goto*//*Label 5896*/ GIMT_Encode4(282212), // Rule ID 4989 //
104777 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104778 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104779 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104780 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104781 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
104782 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
104783 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
104784 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
104785 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104786 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
104787 // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>) => (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] }))
104788 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
104789 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
104790 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
104791 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
104792 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104793 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
104794 GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
104795 GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
104796 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
104797 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
104798 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104799 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
104800 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
104801 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104802 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
104803 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
104804 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
104805 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
104806 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
104807 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
104808 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
104809 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104810 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104811 GIR_RootConstrainSelectedInstOperands,
104812 // GIR_Coverage, 4989,
104813 GIR_EraseRootFromParent_Done,
104814 // Label 5896: @282212
104815 GIM_Try, /*On fail goto*//*Label 5897*/ GIMT_Encode4(282292), // Rule ID 4971 //
104816 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104817 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
104818 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104819 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104820 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
104821 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
104822 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
104823 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
104824 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
104825 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104826 // (uint_to_fp:{ *:[f64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] })) => (UCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, dsub:{ *:[i32] }))
104827 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
104828 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
104829 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104830 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
104831 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
104832 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
104833 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
104834 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104835 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104836 GIR_RootConstrainSelectedInstOperands,
104837 // GIR_Coverage, 4971,
104838 GIR_EraseRootFromParent_Done,
104839 // Label 5897: @282292
104840 GIM_Try, /*On fail goto*//*Label 5898*/ GIMT_Encode4(282349), // Rule ID 4955 //
104841 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
104842 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
104843 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104844 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
104845 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
104846 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
104847 GIM_CheckIsSafeToFold, /*NumInsns*/1,
104848 // (uint_to_fp:{ *:[f64] } (fp_to_uint:{ *:[i64] } f64:{ *:[f64] }:$Rn)) => (UCVTFv1i64:{ *:[f64] } (FCVTZUv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn))
104849 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
104850 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i64),
104851 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104852 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
104853 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
104854 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
104855 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104856 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104857 GIR_RootConstrainSelectedInstOperands,
104858 // GIR_Coverage, 4955,
104859 GIR_EraseRootFromParent_Done,
104860 // Label 5898: @282349
104861 GIM_Try, /*On fail goto*//*Label 5899*/ GIMT_Encode4(282379), // Rule ID 481 //
104862 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
104863 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
104864 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104865 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
104866 // (uint_to_fp:{ *:[f64] } GPR32:{ *:[i32] }:$Rn) => (UCVTFUWDri:{ *:[f64] } GPR32:{ *:[i32] }:$Rn)
104867 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFUWDri),
104868 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
104869 GIR_RootConstrainSelectedInstOperands,
104870 // GIR_Coverage, 481,
104871 GIR_Done,
104872 // Label 5899: @282379
104873 GIM_Try, /*On fail goto*//*Label 5900*/ GIMT_Encode4(282409), // Rule ID 487 //
104874 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
104875 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
104876 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104877 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
104878 // (uint_to_fp:{ *:[f64] } GPR64:{ *:[i64] }:$Rn) => (UCVTFUXDri:{ *:[f64] } GPR64:{ *:[i64] }:$Rn)
104879 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFUXDri),
104880 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
104881 GIR_RootConstrainSelectedInstOperands,
104882 // GIR_Coverage, 487,
104883 GIR_Done,
104884 // Label 5900: @282409
104885 GIM_Reject,
104886 // Label 5863: @282410
104887 GIM_Try, /*On fail goto*//*Label 5901*/ GIMT_Encode4(282440), // Rule ID 1065 //
104888 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
104889 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
104890 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104891 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104892 // (uint_to_fp:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn) => (UCVTFv2f32:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn)
104893 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv2f32),
104894 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
104895 GIR_RootConstrainSelectedInstOperands,
104896 // GIR_Coverage, 1065,
104897 GIR_Done,
104898 // Label 5901: @282440
104899 GIM_Try, /*On fail goto*//*Label 5902*/ GIMT_Encode4(282483), // Rule ID 12359 //
104900 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
104901 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
104902 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104903 // (uint_to_fp:{ *:[v2f32] } v2i64:{ *:[v2i64] }:$src) => (FCVTNv2i32:{ *:[v2f32] } (UCVTFv2f64:{ *:[f128] } V128:{ *:[v2i64] }:$src))
104904 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
104905 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv2f64),
104906 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104907 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
104908 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
104909 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv2i32),
104910 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104911 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104912 GIR_RootConstrainSelectedInstOperands,
104913 // GIR_Coverage, 12359,
104914 GIR_EraseRootFromParent_Done,
104915 // Label 5902: @282483
104916 GIM_Reject,
104917 // Label 5864: @282484
104918 GIM_Try, /*On fail goto*//*Label 5903*/ GIMT_Encode4(282514), // Rule ID 1069 //
104919 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
104920 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
104921 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
104922 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
104923 // (uint_to_fp:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn) => (UCVTFv2f64:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn)
104924 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv2f64),
104925 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
104926 GIR_RootConstrainSelectedInstOperands,
104927 // GIR_Coverage, 1069,
104928 GIR_Done,
104929 // Label 5903: @282514
104930 GIM_Try, /*On fail goto*//*Label 5904*/ GIMT_Encode4(282560), // Rule ID 12357 //
104931 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
104932 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
104933 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
104934 // (uint_to_fp:{ *:[v2f64] } v2i32:{ *:[v2i32] }:$src) => (UCVTFv2f64:{ *:[v2f64] } (USHLLv2i32_shift:{ *:[f128] } V64:{ *:[v2i32] }:$src, 0:{ *:[i32] }))
104935 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
104936 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USHLLv2i32_shift),
104937 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
104938 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
104939 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
104940 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
104941 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv2f64),
104942 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
104943 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
104944 GIR_RootConstrainSelectedInstOperands,
104945 // GIR_Coverage, 12357,
104946 GIR_EraseRootFromParent_Done,
104947 // Label 5904: @282560
104948 GIM_Reject,
104949 // Label 5865: @282561
104950 GIM_Try, /*On fail goto*//*Label 5905*/ GIMT_Encode4(282591), // Rule ID 1061 //
104951 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
104952 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
104953 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104954 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
104955 // (uint_to_fp:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn) => (UCVTFv4f16:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn)
104956 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv4f16),
104957 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
104958 GIR_RootConstrainSelectedInstOperands,
104959 // GIR_Coverage, 1061,
104960 GIR_Done,
104961 // Label 5905: @282591
104962 GIM_Reject,
104963 // Label 5866: @282592
104964 GIM_Try, /*On fail goto*//*Label 5906*/ GIMT_Encode4(282622), // Rule ID 1067 //
104965 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
104966 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
104967 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
104968 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
104969 // (uint_to_fp:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn) => (UCVTFv4f32:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn)
104970 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv4f32),
104971 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
104972 GIR_RootConstrainSelectedInstOperands,
104973 // GIR_Coverage, 1067,
104974 GIR_Done,
104975 // Label 5906: @282622
104976 GIM_Reject,
104977 // Label 5867: @282623
104978 GIM_Try, /*On fail goto*//*Label 5907*/ GIMT_Encode4(282653), // Rule ID 1063 //
104979 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
104980 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
104981 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
104982 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
104983 // (uint_to_fp:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn) => (UCVTFv8f16:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn)
104984 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv8f16),
104985 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
104986 GIR_RootConstrainSelectedInstOperands,
104987 // GIR_Coverage, 1063,
104988 GIR_Done,
104989 // Label 5907: @282653
104990 GIM_Reject,
104991 // Label 5868: @282654
104992 GIM_Reject,
104993 // Label 65: @282655
104994 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 5916*/ GIMT_Encode4(283724),
104995 /*GILLT_s16*//*Label 5908*/ GIMT_Encode4(282706),
104996 /*GILLT_s32*//*Label 5909*/ GIMT_Encode4(283070),
104997 /*GILLT_s64*//*Label 5910*/ GIMT_Encode4(283144), GIMT_Encode4(0),
104998 /*GILLT_v2s32*//*Label 5911*/ GIMT_Encode4(283218),
104999 /*GILLT_v2s64*//*Label 5912*/ GIMT_Encode4(283292),
105000 /*GILLT_v4s16*//*Label 5913*/ GIMT_Encode4(283366),
105001 /*GILLT_v4s32*//*Label 5914*/ GIMT_Encode4(283508), GIMT_Encode4(0),
105002 /*GILLT_v8s16*//*Label 5915*/ GIMT_Encode4(283582),
105003 // Label 5908: @282706
105004 GIM_Try, /*On fail goto*//*Label 5917*/ GIMT_Encode4(283069),
105005 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
105006 GIM_Try, /*On fail goto*//*Label 5918*/ GIMT_Encode4(282759), // Rule ID 4856 //
105007 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
105008 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
105009 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
105010 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
105011 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
105012 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
105013 GIM_CheckIsSafeToFold, /*NumInsns*/1,
105014 // (fabs:{ *:[f16] } (fsub:{ *:[f16] } f16:{ *:[f16] }:$Rn, f16:{ *:[f16] }:$Rm)) => (FABD16:{ *:[f16] } f16:{ *:[f16] }:$Rn, f16:{ *:[f16] }:$Rm)
105015 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD16),
105016 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
105017 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
105018 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
105019 GIR_RootConstrainSelectedInstOperands,
105020 // GIR_Coverage, 4856,
105021 GIR_EraseRootFromParent_Done,
105022 // Label 5918: @282759
105023 GIM_Try, /*On fail goto*//*Label 5919*/ GIMT_Encode4(282782), // Rule ID 515 //
105024 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
105025 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
105026 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
105027 // (fabs:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FABSHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
105028 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSHr),
105029 GIR_RootConstrainSelectedInstOperands,
105030 // GIR_Coverage, 515,
105031 GIR_Done,
105032 // Label 5919: @282782
105033 GIM_Try, /*On fail goto*//*Label 5920*/ GIMT_Encode4(282925), // Rule ID 5962 //
105034 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
105035 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
105036 // (fabs:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } (ANDWri:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] }), GPR32:{ *:[i32] }), (logical_imm32_XFORM:{ *:[i32] } 32767:{ *:[i32] })), FPR32:{ *:[i32] }), hsub:{ *:[i32] })
105037 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
105038 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
105039 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
105040 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
105041 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
105042 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
105043 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
105044 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
105045 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
105046 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
105047 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
105048 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
105049 GIR_AddImm8, /*InsnID*/4, /*Imm*/7,
105050 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
105051 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
105052 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
105053 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
105054 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
105055 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
105056 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
105057 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::ANDWri),
105058 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
105059 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
105060 GIR_CustomRenderer, /*InsnID*/2, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm32), //
105061 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
105062 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
105063 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
105064 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
105065 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
105066 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
105067 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
105068 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
105069 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
105070 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
105071 // GIR_Coverage, 5962,
105072 GIR_EraseRootFromParent_Done,
105073 // Label 5920: @282925
105074 GIM_Try, /*On fail goto*//*Label 5921*/ GIMT_Encode4(283068), // Rule ID 5963 //
105075 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
105076 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
105077 // (fabs:{ *:[bf16] } FPR16:{ *:[bf16] }:$Rn) => (EXTRACT_SUBREG:{ *:[bf16] } (COPY_TO_REGCLASS:{ *:[f32] } (ANDWri:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), FPR16:{ *:[bf16] }:$Rn, hsub:{ *:[i32] }), GPR32:{ *:[i32] }), (logical_imm32_XFORM:{ *:[i32] } 32767:{ *:[i32] })), FPR32:{ *:[i32] }), hsub:{ *:[i32] })
105078 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
105079 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
105080 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
105081 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
105082 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
105083 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
105084 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
105085 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
105086 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
105087 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
105088 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
105089 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
105090 GIR_AddImm8, /*InsnID*/4, /*Imm*/7,
105091 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
105092 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
105093 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
105094 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
105095 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
105096 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
105097 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
105098 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::ANDWri),
105099 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
105100 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
105101 GIR_CustomRenderer, /*InsnID*/2, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm32), //
105102 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
105103 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
105104 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
105105 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
105106 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
105107 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
105108 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
105109 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
105110 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
105111 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
105112 // GIR_Coverage, 5963,
105113 GIR_EraseRootFromParent_Done,
105114 // Label 5921: @283068
105115 GIM_Reject,
105116 // Label 5917: @283069
105117 GIM_Reject,
105118 // Label 5909: @283070
105119 GIM_Try, /*On fail goto*//*Label 5922*/ GIMT_Encode4(283143),
105120 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
105121 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
105122 GIM_Try, /*On fail goto*//*Label 5923*/ GIMT_Encode4(283123), // Rule ID 4857 //
105123 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105124 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
105125 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
105126 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
105127 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
105128 GIM_CheckIsSafeToFold, /*NumInsns*/1,
105129 // (fabs:{ *:[f32] } (fsub:{ *:[f32] } f32:{ *:[f32] }:$Rn, f32:{ *:[f32] }:$Rm)) => (FABD32:{ *:[f32] } f32:{ *:[f32] }:$Rn, f32:{ *:[f32] }:$Rm)
105130 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD32),
105131 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
105132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
105133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
105134 GIR_RootConstrainSelectedInstOperands,
105135 // GIR_Coverage, 4857,
105136 GIR_EraseRootFromParent_Done,
105137 // Label 5923: @283123
105138 GIM_Try, /*On fail goto*//*Label 5924*/ GIMT_Encode4(283142), // Rule ID 516 //
105139 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
105140 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
105141 // (fabs:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FABSSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
105142 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSSr),
105143 GIR_RootConstrainSelectedInstOperands,
105144 // GIR_Coverage, 516,
105145 GIR_Done,
105146 // Label 5924: @283142
105147 GIM_Reject,
105148 // Label 5922: @283143
105149 GIM_Reject,
105150 // Label 5910: @283144
105151 GIM_Try, /*On fail goto*//*Label 5925*/ GIMT_Encode4(283217),
105152 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
105153 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105154 GIM_Try, /*On fail goto*//*Label 5926*/ GIMT_Encode4(283197), // Rule ID 4858 //
105155 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105156 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
105157 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
105158 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
105159 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
105160 GIM_CheckIsSafeToFold, /*NumInsns*/1,
105161 // (fabs:{ *:[f64] } (fsub:{ *:[f64] } f64:{ *:[f64] }:$Rn, f64:{ *:[f64] }:$Rm)) => (FABD64:{ *:[f64] } f64:{ *:[f64] }:$Rn, f64:{ *:[f64] }:$Rm)
105162 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD64),
105163 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
105164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
105165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
105166 GIR_RootConstrainSelectedInstOperands,
105167 // GIR_Coverage, 4858,
105168 GIR_EraseRootFromParent_Done,
105169 // Label 5926: @283197
105170 GIM_Try, /*On fail goto*//*Label 5927*/ GIMT_Encode4(283216), // Rule ID 517 //
105171 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
105172 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105173 // (fabs:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FABSDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
105174 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSDr),
105175 GIR_RootConstrainSelectedInstOperands,
105176 // GIR_Coverage, 517,
105177 GIR_Done,
105178 // Label 5927: @283216
105179 GIM_Reject,
105180 // Label 5925: @283217
105181 GIM_Reject,
105182 // Label 5911: @283218
105183 GIM_Try, /*On fail goto*//*Label 5928*/ GIMT_Encode4(283291),
105184 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
105185 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105186 GIM_Try, /*On fail goto*//*Label 5929*/ GIMT_Encode4(283271), // Rule ID 4664 //
105187 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105188 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
105189 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
105190 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
105191 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
105192 GIM_CheckIsSafeToFold, /*NumInsns*/1,
105193 // (fabs:{ *:[v2f32] } (fsub:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$Rn, v2f32:{ *:[v2f32] }:$Rm)) => (FABDv2f32:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$Rn, v2f32:{ *:[v2f32] }:$Rm)
105194 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv2f32),
105195 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
105196 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
105197 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
105198 GIR_RootConstrainSelectedInstOperands,
105199 // GIR_Coverage, 4664,
105200 GIR_EraseRootFromParent_Done,
105201 // Label 5929: @283271
105202 GIM_Try, /*On fail goto*//*Label 5930*/ GIMT_Encode4(283290), // Rule ID 755 //
105203 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105204 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105205 // (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FABSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
105206 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSv2f32),
105207 GIR_RootConstrainSelectedInstOperands,
105208 // GIR_Coverage, 755,
105209 GIR_Done,
105210 // Label 5930: @283290
105211 GIM_Reject,
105212 // Label 5928: @283291
105213 GIM_Reject,
105214 // Label 5912: @283292
105215 GIM_Try, /*On fail goto*//*Label 5931*/ GIMT_Encode4(283365),
105216 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
105217 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105218 GIM_Try, /*On fail goto*//*Label 5932*/ GIMT_Encode4(283345), // Rule ID 4666 //
105219 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105220 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
105221 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
105222 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
105223 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
105224 GIM_CheckIsSafeToFold, /*NumInsns*/1,
105225 // (fabs:{ *:[v2f64] } (fsub:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$Rn, v2f64:{ *:[v2f64] }:$Rm)) => (FABDv2f64:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$Rn, v2f64:{ *:[v2f64] }:$Rm)
105226 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv2f64),
105227 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
105228 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
105229 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
105230 GIR_RootConstrainSelectedInstOperands,
105231 // GIR_Coverage, 4666,
105232 GIR_EraseRootFromParent_Done,
105233 // Label 5932: @283345
105234 GIM_Try, /*On fail goto*//*Label 5933*/ GIMT_Encode4(283364), // Rule ID 757 //
105235 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105236 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105237 // (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FABSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
105238 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSv2f64),
105239 GIR_RootConstrainSelectedInstOperands,
105240 // GIR_Coverage, 757,
105241 GIR_Done,
105242 // Label 5933: @283364
105243 GIM_Reject,
105244 // Label 5931: @283365
105245 GIM_Reject,
105246 // Label 5913: @283366
105247 GIM_Try, /*On fail goto*//*Label 5934*/ GIMT_Encode4(283507),
105248 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
105249 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105250 GIM_Try, /*On fail goto*//*Label 5935*/ GIMT_Encode4(283419), // Rule ID 4667 //
105251 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
105252 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
105253 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
105254 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
105255 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
105256 GIM_CheckIsSafeToFold, /*NumInsns*/1,
105257 // (fabs:{ *:[v4f16] } (fsub:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$Rn, v4f16:{ *:[v4f16] }:$Rm)) => (FABDv4f16:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$Rn, v4f16:{ *:[v4f16] }:$Rm)
105258 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv4f16),
105259 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
105260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
105261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
105262 GIR_RootConstrainSelectedInstOperands,
105263 // GIR_Coverage, 4667,
105264 GIR_EraseRootFromParent_Done,
105265 // Label 5935: @283419
105266 GIM_Try, /*On fail goto*//*Label 5936*/ GIMT_Encode4(283438), // Rule ID 753 //
105267 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
105268 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105269 // (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FABSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
105270 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSv4f16),
105271 GIR_RootConstrainSelectedInstOperands,
105272 // GIR_Coverage, 753,
105273 GIR_Done,
105274 // Label 5936: @283438
105275 GIM_Try, /*On fail goto*//*Label 5937*/ GIMT_Encode4(283472), // Rule ID 5966 //
105276 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105277 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105278 // (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (BICv4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, 128:{ *:[i32] }, 8:{ *:[i32] })
105279 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv4i16),
105280 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
105281 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
105282 GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(128),
105283 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
105284 GIR_RootConstrainSelectedInstOperands,
105285 // GIR_Coverage, 5966,
105286 GIR_EraseRootFromParent_Done,
105287 // Label 5937: @283472
105288 GIM_Try, /*On fail goto*//*Label 5938*/ GIMT_Encode4(283506), // Rule ID 5967 //
105289 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105290 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105291 // (fabs:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn) => (BICv4i16:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, 128:{ *:[i32] }, 8:{ *:[i32] })
105292 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv4i16),
105293 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
105294 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
105295 GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(128),
105296 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
105297 GIR_RootConstrainSelectedInstOperands,
105298 // GIR_Coverage, 5967,
105299 GIR_EraseRootFromParent_Done,
105300 // Label 5938: @283506
105301 GIM_Reject,
105302 // Label 5934: @283507
105303 GIM_Reject,
105304 // Label 5914: @283508
105305 GIM_Try, /*On fail goto*//*Label 5939*/ GIMT_Encode4(283581),
105306 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
105307 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105308 GIM_Try, /*On fail goto*//*Label 5940*/ GIMT_Encode4(283561), // Rule ID 4665 //
105309 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105310 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
105311 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
105312 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
105313 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
105314 GIM_CheckIsSafeToFold, /*NumInsns*/1,
105315 // (fabs:{ *:[v4f32] } (fsub:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$Rn, v4f32:{ *:[v4f32] }:$Rm)) => (FABDv4f32:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$Rn, v4f32:{ *:[v4f32] }:$Rm)
105316 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv4f32),
105317 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
105318 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
105319 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
105320 GIR_RootConstrainSelectedInstOperands,
105321 // GIR_Coverage, 4665,
105322 GIR_EraseRootFromParent_Done,
105323 // Label 5940: @283561
105324 GIM_Try, /*On fail goto*//*Label 5941*/ GIMT_Encode4(283580), // Rule ID 756 //
105325 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105326 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105327 // (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FABSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
105328 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSv4f32),
105329 GIR_RootConstrainSelectedInstOperands,
105330 // GIR_Coverage, 756,
105331 GIR_Done,
105332 // Label 5941: @283580
105333 GIM_Reject,
105334 // Label 5939: @283581
105335 GIM_Reject,
105336 // Label 5915: @283582
105337 GIM_Try, /*On fail goto*//*Label 5942*/ GIMT_Encode4(283723),
105338 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
105339 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105340 GIM_Try, /*On fail goto*//*Label 5943*/ GIMT_Encode4(283635), // Rule ID 4668 //
105341 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
105342 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
105343 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
105344 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
105345 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
105346 GIM_CheckIsSafeToFold, /*NumInsns*/1,
105347 // (fabs:{ *:[v8f16] } (fsub:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$Rn, v8f16:{ *:[v8f16] }:$Rm)) => (FABDv8f16:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$Rn, v8f16:{ *:[v8f16] }:$Rm)
105348 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv8f16),
105349 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
105350 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
105351 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
105352 GIR_RootConstrainSelectedInstOperands,
105353 // GIR_Coverage, 4668,
105354 GIR_EraseRootFromParent_Done,
105355 // Label 5943: @283635
105356 GIM_Try, /*On fail goto*//*Label 5944*/ GIMT_Encode4(283654), // Rule ID 754 //
105357 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
105358 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105359 // (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FABSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
105360 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSv8f16),
105361 GIR_RootConstrainSelectedInstOperands,
105362 // GIR_Coverage, 754,
105363 GIR_Done,
105364 // Label 5944: @283654
105365 GIM_Try, /*On fail goto*//*Label 5945*/ GIMT_Encode4(283688), // Rule ID 5968 //
105366 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105367 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105368 // (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (BICv8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, 128:{ *:[i32] }, 8:{ *:[i32] })
105369 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i16),
105370 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
105371 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
105372 GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(128),
105373 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
105374 GIR_RootConstrainSelectedInstOperands,
105375 // GIR_Coverage, 5968,
105376 GIR_EraseRootFromParent_Done,
105377 // Label 5945: @283688
105378 GIM_Try, /*On fail goto*//*Label 5946*/ GIMT_Encode4(283722), // Rule ID 5969 //
105379 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105380 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105381 // (fabs:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (BICv8i16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, 128:{ *:[i32] }, 8:{ *:[i32] })
105382 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i16),
105383 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
105384 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
105385 GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(128),
105386 GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
105387 GIR_RootConstrainSelectedInstOperands,
105388 // GIR_Coverage, 5969,
105389 GIR_EraseRootFromParent_Done,
105390 // Label 5946: @283722
105391 GIM_Reject,
105392 // Label 5942: @283723
105393 GIM_Reject,
105394 // Label 5916: @283724
105395 GIM_Reject,
105396 // Label 66: @283725
105397 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 5955*/ GIMT_Encode4(284102),
105398 /*GILLT_s16*//*Label 5947*/ GIMT_Encode4(283776),
105399 /*GILLT_s32*//*Label 5948*/ GIMT_Encode4(283814),
105400 /*GILLT_s64*//*Label 5949*/ GIMT_Encode4(283852), GIMT_Encode4(0),
105401 /*GILLT_v2s32*//*Label 5950*/ GIMT_Encode4(283912),
105402 /*GILLT_v2s64*//*Label 5951*/ GIMT_Encode4(283950),
105403 /*GILLT_v4s16*//*Label 5952*/ GIMT_Encode4(283988),
105404 /*GILLT_v4s32*//*Label 5953*/ GIMT_Encode4(284026), GIMT_Encode4(0),
105405 /*GILLT_v8s16*//*Label 5954*/ GIMT_Encode4(284064),
105406 // Label 5947: @283776
105407 GIM_Try, /*On fail goto*//*Label 5956*/ GIMT_Encode4(283813), // Rule ID 602 //
105408 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
105409 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
105410 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
105411 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
105412 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
105413 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
105414 // (fminnum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMINNMHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
105415 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMHrr),
105416 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105417 GIR_RootConstrainSelectedInstOperands,
105418 // GIR_Coverage, 602,
105419 GIR_Done,
105420 // Label 5956: @283813
105421 GIM_Reject,
105422 // Label 5948: @283814
105423 GIM_Try, /*On fail goto*//*Label 5957*/ GIMT_Encode4(283851), // Rule ID 604 //
105424 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
105425 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
105426 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
105427 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
105428 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
105429 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
105430 // (fminnum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMINNMSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
105431 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMSrr),
105432 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105433 GIR_RootConstrainSelectedInstOperands,
105434 // GIR_Coverage, 604,
105435 GIR_Done,
105436 // Label 5957: @283851
105437 GIM_Reject,
105438 // Label 5949: @283852
105439 GIM_Try, /*On fail goto*//*Label 5958*/ GIMT_Encode4(283911),
105440 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
105441 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
105442 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105443 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105444 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105445 GIM_Try, /*On fail goto*//*Label 5959*/ GIMT_Encode4(283894), // Rule ID 606 //
105446 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
105447 // (fminnum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMINNMDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
105448 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMDrr),
105449 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105450 GIR_RootConstrainSelectedInstOperands,
105451 // GIR_Coverage, 606,
105452 GIR_Done,
105453 // Label 5959: @283894
105454 GIM_Try, /*On fail goto*//*Label 5960*/ GIMT_Encode4(283910), // Rule ID 4499 //
105455 // (fminnum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FMINNMDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
105456 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMDrr),
105457 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105458 GIR_RootConstrainSelectedInstOperands,
105459 // GIR_Coverage, 4499,
105460 GIR_Done,
105461 // Label 5960: @283910
105462 GIM_Reject,
105463 // Label 5958: @283911
105464 GIM_Reject,
105465 // Label 5950: @283912
105466 GIM_Try, /*On fail goto*//*Label 5961*/ GIMT_Encode4(283949), // Rule ID 1260 //
105467 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105468 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
105469 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
105470 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105471 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105472 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105473 // (fminnum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMINNMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
105474 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv2f32),
105475 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105476 GIR_RootConstrainSelectedInstOperands,
105477 // GIR_Coverage, 1260,
105478 GIR_Done,
105479 // Label 5961: @283949
105480 GIM_Reject,
105481 // Label 5951: @283950
105482 GIM_Try, /*On fail goto*//*Label 5962*/ GIMT_Encode4(283987), // Rule ID 1264 //
105483 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105484 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
105485 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
105486 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105487 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105488 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105489 // (fminnum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMINNMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
105490 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv2f64),
105491 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105492 GIR_RootConstrainSelectedInstOperands,
105493 // GIR_Coverage, 1264,
105494 GIR_Done,
105495 // Label 5962: @283987
105496 GIM_Reject,
105497 // Label 5952: @283988
105498 GIM_Try, /*On fail goto*//*Label 5963*/ GIMT_Encode4(284025), // Rule ID 1256 //
105499 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
105500 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
105501 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
105502 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105503 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105504 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105505 // (fminnum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMINNMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
105506 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv4f16),
105507 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105508 GIR_RootConstrainSelectedInstOperands,
105509 // GIR_Coverage, 1256,
105510 GIR_Done,
105511 // Label 5963: @284025
105512 GIM_Reject,
105513 // Label 5953: @284026
105514 GIM_Try, /*On fail goto*//*Label 5964*/ GIMT_Encode4(284063), // Rule ID 1262 //
105515 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105516 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
105517 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
105518 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105519 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105520 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105521 // (fminnum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMINNMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
105522 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv4f32),
105523 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105524 GIR_RootConstrainSelectedInstOperands,
105525 // GIR_Coverage, 1262,
105526 GIR_Done,
105527 // Label 5964: @284063
105528 GIM_Reject,
105529 // Label 5954: @284064
105530 GIM_Try, /*On fail goto*//*Label 5965*/ GIMT_Encode4(284101), // Rule ID 1258 //
105531 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
105532 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
105533 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
105534 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105535 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105536 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105537 // (fminnum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMINNMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
105538 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv8f16),
105539 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105540 GIR_RootConstrainSelectedInstOperands,
105541 // GIR_Coverage, 1258,
105542 GIR_Done,
105543 // Label 5965: @284101
105544 GIM_Reject,
105545 // Label 5955: @284102
105546 GIM_Reject,
105547 // Label 67: @284103
105548 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 5974*/ GIMT_Encode4(284480),
105549 /*GILLT_s16*//*Label 5966*/ GIMT_Encode4(284154),
105550 /*GILLT_s32*//*Label 5967*/ GIMT_Encode4(284192),
105551 /*GILLT_s64*//*Label 5968*/ GIMT_Encode4(284230), GIMT_Encode4(0),
105552 /*GILLT_v2s32*//*Label 5969*/ GIMT_Encode4(284290),
105553 /*GILLT_v2s64*//*Label 5970*/ GIMT_Encode4(284328),
105554 /*GILLT_v4s16*//*Label 5971*/ GIMT_Encode4(284366),
105555 /*GILLT_v4s32*//*Label 5972*/ GIMT_Encode4(284404), GIMT_Encode4(0),
105556 /*GILLT_v8s16*//*Label 5973*/ GIMT_Encode4(284442),
105557 // Label 5966: @284154
105558 GIM_Try, /*On fail goto*//*Label 5975*/ GIMT_Encode4(284191), // Rule ID 590 //
105559 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
105560 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
105561 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
105562 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
105563 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
105564 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
105565 // (fmaxnum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMAXNMHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
105566 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMHrr),
105567 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105568 GIR_RootConstrainSelectedInstOperands,
105569 // GIR_Coverage, 590,
105570 GIR_Done,
105571 // Label 5975: @284191
105572 GIM_Reject,
105573 // Label 5967: @284192
105574 GIM_Try, /*On fail goto*//*Label 5976*/ GIMT_Encode4(284229), // Rule ID 592 //
105575 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
105576 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
105577 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
105578 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
105579 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
105580 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
105581 // (fmaxnum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMAXNMSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
105582 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMSrr),
105583 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105584 GIR_RootConstrainSelectedInstOperands,
105585 // GIR_Coverage, 592,
105586 GIR_Done,
105587 // Label 5976: @284229
105588 GIM_Reject,
105589 // Label 5968: @284230
105590 GIM_Try, /*On fail goto*//*Label 5977*/ GIMT_Encode4(284289),
105591 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
105592 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
105593 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105594 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105595 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105596 GIM_Try, /*On fail goto*//*Label 5978*/ GIMT_Encode4(284272), // Rule ID 594 //
105597 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
105598 // (fmaxnum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMAXNMDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
105599 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMDrr),
105600 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105601 GIR_RootConstrainSelectedInstOperands,
105602 // GIR_Coverage, 594,
105603 GIR_Done,
105604 // Label 5978: @284272
105605 GIM_Try, /*On fail goto*//*Label 5979*/ GIMT_Encode4(284288), // Rule ID 4498 //
105606 // (fmaxnum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FMAXNMDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
105607 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMDrr),
105608 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105609 GIR_RootConstrainSelectedInstOperands,
105610 // GIR_Coverage, 4498,
105611 GIR_Done,
105612 // Label 5979: @284288
105613 GIM_Reject,
105614 // Label 5977: @284289
105615 GIM_Reject,
105616 // Label 5969: @284290
105617 GIM_Try, /*On fail goto*//*Label 5980*/ GIMT_Encode4(284327), // Rule ID 1230 //
105618 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105619 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
105620 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
105621 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105622 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105623 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105624 // (fmaxnum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMAXNMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
105625 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv2f32),
105626 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105627 GIR_RootConstrainSelectedInstOperands,
105628 // GIR_Coverage, 1230,
105629 GIR_Done,
105630 // Label 5980: @284327
105631 GIM_Reject,
105632 // Label 5970: @284328
105633 GIM_Try, /*On fail goto*//*Label 5981*/ GIMT_Encode4(284365), // Rule ID 1234 //
105634 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105635 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
105636 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
105637 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105638 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105639 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105640 // (fmaxnum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMAXNMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
105641 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv2f64),
105642 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105643 GIR_RootConstrainSelectedInstOperands,
105644 // GIR_Coverage, 1234,
105645 GIR_Done,
105646 // Label 5981: @284365
105647 GIM_Reject,
105648 // Label 5971: @284366
105649 GIM_Try, /*On fail goto*//*Label 5982*/ GIMT_Encode4(284403), // Rule ID 1226 //
105650 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
105651 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
105652 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
105653 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105654 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105655 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105656 // (fmaxnum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMAXNMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
105657 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv4f16),
105658 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105659 GIR_RootConstrainSelectedInstOperands,
105660 // GIR_Coverage, 1226,
105661 GIR_Done,
105662 // Label 5982: @284403
105663 GIM_Reject,
105664 // Label 5972: @284404
105665 GIM_Try, /*On fail goto*//*Label 5983*/ GIMT_Encode4(284441), // Rule ID 1232 //
105666 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105667 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
105668 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
105669 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105670 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105671 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105672 // (fmaxnum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMAXNMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
105673 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv4f32),
105674 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105675 GIR_RootConstrainSelectedInstOperands,
105676 // GIR_Coverage, 1232,
105677 GIR_Done,
105678 // Label 5983: @284441
105679 GIM_Reject,
105680 // Label 5973: @284442
105681 GIM_Try, /*On fail goto*//*Label 5984*/ GIMT_Encode4(284479), // Rule ID 1228 //
105682 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
105683 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
105684 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
105685 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105686 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105687 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105688 // (fmaxnum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMAXNMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
105689 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv8f16),
105690 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105691 GIR_RootConstrainSelectedInstOperands,
105692 // GIR_Coverage, 1228,
105693 GIR_Done,
105694 // Label 5984: @284479
105695 GIM_Reject,
105696 // Label 5974: @284480
105697 GIM_Reject,
105698 // Label 68: @284481
105699 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 5993*/ GIMT_Encode4(284858),
105700 /*GILLT_s16*//*Label 5985*/ GIMT_Encode4(284532),
105701 /*GILLT_s32*//*Label 5986*/ GIMT_Encode4(284570),
105702 /*GILLT_s64*//*Label 5987*/ GIMT_Encode4(284608), GIMT_Encode4(0),
105703 /*GILLT_v2s32*//*Label 5988*/ GIMT_Encode4(284668),
105704 /*GILLT_v2s64*//*Label 5989*/ GIMT_Encode4(284706),
105705 /*GILLT_v4s16*//*Label 5990*/ GIMT_Encode4(284744),
105706 /*GILLT_v4s32*//*Label 5991*/ GIMT_Encode4(284782), GIMT_Encode4(0),
105707 /*GILLT_v8s16*//*Label 5992*/ GIMT_Encode4(284820),
105708 // Label 5985: @284532
105709 GIM_Try, /*On fail goto*//*Label 5994*/ GIMT_Encode4(284569), // Rule ID 608 //
105710 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
105711 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
105712 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
105713 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
105714 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
105715 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
105716 // (fminimum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMINHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
105717 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINHrr),
105718 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105719 GIR_RootConstrainSelectedInstOperands,
105720 // GIR_Coverage, 608,
105721 GIR_Done,
105722 // Label 5994: @284569
105723 GIM_Reject,
105724 // Label 5986: @284570
105725 GIM_Try, /*On fail goto*//*Label 5995*/ GIMT_Encode4(284607), // Rule ID 610 //
105726 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
105727 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
105728 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
105729 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
105730 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
105731 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
105732 // (fminimum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMINSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
105733 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINSrr),
105734 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105735 GIR_RootConstrainSelectedInstOperands,
105736 // GIR_Coverage, 610,
105737 GIR_Done,
105738 // Label 5995: @284607
105739 GIM_Reject,
105740 // Label 5987: @284608
105741 GIM_Try, /*On fail goto*//*Label 5996*/ GIMT_Encode4(284667),
105742 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
105743 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
105744 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105745 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105746 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105747 GIM_Try, /*On fail goto*//*Label 5997*/ GIMT_Encode4(284650), // Rule ID 612 //
105748 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
105749 // (fminimum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMINDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
105750 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINDrr),
105751 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105752 GIR_RootConstrainSelectedInstOperands,
105753 // GIR_Coverage, 612,
105754 GIR_Done,
105755 // Label 5997: @284650
105756 GIM_Try, /*On fail goto*//*Label 5998*/ GIMT_Encode4(284666), // Rule ID 4497 //
105757 // (fminimum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FMINDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
105758 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINDrr),
105759 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105760 GIR_RootConstrainSelectedInstOperands,
105761 // GIR_Coverage, 4497,
105762 GIR_Done,
105763 // Label 5998: @284666
105764 GIM_Reject,
105765 // Label 5996: @284667
105766 GIM_Reject,
105767 // Label 5988: @284668
105768 GIM_Try, /*On fail goto*//*Label 5999*/ GIMT_Encode4(284705), // Rule ID 1275 //
105769 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105770 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
105771 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
105772 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105773 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105774 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105775 // (fminimum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMINv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
105776 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINv2f32),
105777 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105778 GIR_RootConstrainSelectedInstOperands,
105779 // GIR_Coverage, 1275,
105780 GIR_Done,
105781 // Label 5999: @284705
105782 GIM_Reject,
105783 // Label 5989: @284706
105784 GIM_Try, /*On fail goto*//*Label 6000*/ GIMT_Encode4(284743), // Rule ID 1279 //
105785 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105786 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
105787 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
105788 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105789 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105790 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105791 // (fminimum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMINv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
105792 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINv2f64),
105793 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105794 GIR_RootConstrainSelectedInstOperands,
105795 // GIR_Coverage, 1279,
105796 GIR_Done,
105797 // Label 6000: @284743
105798 GIM_Reject,
105799 // Label 5990: @284744
105800 GIM_Try, /*On fail goto*//*Label 6001*/ GIMT_Encode4(284781), // Rule ID 1271 //
105801 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
105802 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
105803 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
105804 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105805 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105806 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105807 // (fminimum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMINv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
105808 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINv4f16),
105809 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105810 GIR_RootConstrainSelectedInstOperands,
105811 // GIR_Coverage, 1271,
105812 GIR_Done,
105813 // Label 6001: @284781
105814 GIM_Reject,
105815 // Label 5991: @284782
105816 GIM_Try, /*On fail goto*//*Label 6002*/ GIMT_Encode4(284819), // Rule ID 1277 //
105817 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105818 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
105819 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
105820 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105821 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105822 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105823 // (fminimum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMINv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
105824 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINv4f32),
105825 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105826 GIR_RootConstrainSelectedInstOperands,
105827 // GIR_Coverage, 1277,
105828 GIR_Done,
105829 // Label 6002: @284819
105830 GIM_Reject,
105831 // Label 5992: @284820
105832 GIM_Try, /*On fail goto*//*Label 6003*/ GIMT_Encode4(284857), // Rule ID 1273 //
105833 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
105834 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
105835 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
105836 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105837 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105838 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105839 // (fminimum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMINv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
105840 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINv8f16),
105841 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105842 GIR_RootConstrainSelectedInstOperands,
105843 // GIR_Coverage, 1273,
105844 GIR_Done,
105845 // Label 6003: @284857
105846 GIM_Reject,
105847 // Label 5993: @284858
105848 GIM_Reject,
105849 // Label 69: @284859
105850 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6012*/ GIMT_Encode4(285236),
105851 /*GILLT_s16*//*Label 6004*/ GIMT_Encode4(284910),
105852 /*GILLT_s32*//*Label 6005*/ GIMT_Encode4(284948),
105853 /*GILLT_s64*//*Label 6006*/ GIMT_Encode4(284986), GIMT_Encode4(0),
105854 /*GILLT_v2s32*//*Label 6007*/ GIMT_Encode4(285046),
105855 /*GILLT_v2s64*//*Label 6008*/ GIMT_Encode4(285084),
105856 /*GILLT_v4s16*//*Label 6009*/ GIMT_Encode4(285122),
105857 /*GILLT_v4s32*//*Label 6010*/ GIMT_Encode4(285160), GIMT_Encode4(0),
105858 /*GILLT_v8s16*//*Label 6011*/ GIMT_Encode4(285198),
105859 // Label 6004: @284910
105860 GIM_Try, /*On fail goto*//*Label 6013*/ GIMT_Encode4(284947), // Rule ID 596 //
105861 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
105862 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
105863 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
105864 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
105865 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
105866 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
105867 // (fmaximum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMAXHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
105868 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXHrr),
105869 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105870 GIR_RootConstrainSelectedInstOperands,
105871 // GIR_Coverage, 596,
105872 GIR_Done,
105873 // Label 6013: @284947
105874 GIM_Reject,
105875 // Label 6005: @284948
105876 GIM_Try, /*On fail goto*//*Label 6014*/ GIMT_Encode4(284985), // Rule ID 598 //
105877 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
105878 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
105879 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
105880 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
105881 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
105882 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
105883 // (fmaximum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMAXSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
105884 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXSrr),
105885 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105886 GIR_RootConstrainSelectedInstOperands,
105887 // GIR_Coverage, 598,
105888 GIR_Done,
105889 // Label 6014: @284985
105890 GIM_Reject,
105891 // Label 6006: @284986
105892 GIM_Try, /*On fail goto*//*Label 6015*/ GIMT_Encode4(285045),
105893 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
105894 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
105895 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105896 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105897 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105898 GIM_Try, /*On fail goto*//*Label 6016*/ GIMT_Encode4(285028), // Rule ID 600 //
105899 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
105900 // (fmaximum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMAXDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
105901 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXDrr),
105902 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105903 GIR_RootConstrainSelectedInstOperands,
105904 // GIR_Coverage, 600,
105905 GIR_Done,
105906 // Label 6016: @285028
105907 GIM_Try, /*On fail goto*//*Label 6017*/ GIMT_Encode4(285044), // Rule ID 4496 //
105908 // (fmaximum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FMAXDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
105909 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXDrr),
105910 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105911 GIR_RootConstrainSelectedInstOperands,
105912 // GIR_Coverage, 4496,
105913 GIR_Done,
105914 // Label 6017: @285044
105915 GIM_Reject,
105916 // Label 6015: @285045
105917 GIM_Reject,
105918 // Label 6007: @285046
105919 GIM_Try, /*On fail goto*//*Label 6018*/ GIMT_Encode4(285083), // Rule ID 1245 //
105920 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105921 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
105922 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
105923 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105924 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105925 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105926 // (fmaximum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMAXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
105927 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXv2f32),
105928 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105929 GIR_RootConstrainSelectedInstOperands,
105930 // GIR_Coverage, 1245,
105931 GIR_Done,
105932 // Label 6018: @285083
105933 GIM_Reject,
105934 // Label 6008: @285084
105935 GIM_Try, /*On fail goto*//*Label 6019*/ GIMT_Encode4(285121), // Rule ID 1249 //
105936 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105937 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
105938 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
105939 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105940 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105941 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105942 // (fmaximum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMAXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
105943 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXv2f64),
105944 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105945 GIR_RootConstrainSelectedInstOperands,
105946 // GIR_Coverage, 1249,
105947 GIR_Done,
105948 // Label 6019: @285121
105949 GIM_Reject,
105950 // Label 6009: @285122
105951 GIM_Try, /*On fail goto*//*Label 6020*/ GIMT_Encode4(285159), // Rule ID 1241 //
105952 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
105953 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
105954 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
105955 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105956 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105957 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
105958 // (fmaximum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMAXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
105959 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXv4f16),
105960 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105961 GIR_RootConstrainSelectedInstOperands,
105962 // GIR_Coverage, 1241,
105963 GIR_Done,
105964 // Label 6020: @285159
105965 GIM_Reject,
105966 // Label 6010: @285160
105967 GIM_Try, /*On fail goto*//*Label 6021*/ GIMT_Encode4(285197), // Rule ID 1247 //
105968 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
105969 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
105970 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
105971 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105972 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105973 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105974 // (fmaximum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMAXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
105975 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXv4f32),
105976 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105977 GIR_RootConstrainSelectedInstOperands,
105978 // GIR_Coverage, 1247,
105979 GIR_Done,
105980 // Label 6021: @285197
105981 GIM_Reject,
105982 // Label 6011: @285198
105983 GIM_Try, /*On fail goto*//*Label 6022*/ GIMT_Encode4(285235), // Rule ID 1243 //
105984 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
105985 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
105986 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
105987 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105988 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105989 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
105990 // (fmaximum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMAXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
105991 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXv8f16),
105992 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
105993 GIR_RootConstrainSelectedInstOperands,
105994 // GIR_Coverage, 1243,
105995 GIR_Done,
105996 // Label 6022: @285235
105997 GIM_Reject,
105998 // Label 6012: @285236
105999 GIM_Reject,
106000 // Label 70: @285237
106001 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 6031*/ GIMT_Encode4(285640),
106002 /*GILLT_s32*//*Label 6023*/ GIMT_Encode4(285288),
106003 /*GILLT_s64*//*Label 6024*/ GIMT_Encode4(285362), GIMT_Encode4(0),
106004 /*GILLT_v2s32*//*Label 6025*/ GIMT_Encode4(285436), GIMT_Encode4(0),
106005 /*GILLT_v4s16*//*Label 6026*/ GIMT_Encode4(285470),
106006 /*GILLT_v4s32*//*Label 6027*/ GIMT_Encode4(285504),
106007 /*GILLT_v8s8*//*Label 6028*/ GIMT_Encode4(285538),
106008 /*GILLT_v8s16*//*Label 6029*/ GIMT_Encode4(285572),
106009 /*GILLT_v16s8*//*Label 6030*/ GIMT_Encode4(285606),
106010 // Label 6023: @285288
106011 GIM_Try, /*On fail goto*//*Label 6032*/ GIMT_Encode4(285361),
106012 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
106013 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
106014 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
106015 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
106016 GIM_Try, /*On fail goto*//*Label 6033*/ GIMT_Encode4(285341), // Rule ID 2313 //
106017 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
106018 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
106019 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
106020 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm8_32b),
106021 // MIs[1] Operand 1
106022 // No operand predicates
106023 GIM_CheckIsSafeToFold, /*NumInsns*/1,
106024 // (smin:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_simm8_32b>>:$imm) => (SMINWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
106025 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINWri),
106026 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
106027 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
106028 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
106029 GIR_RootConstrainSelectedInstOperands,
106030 // GIR_Coverage, 2313,
106031 GIR_EraseRootFromParent_Done,
106032 // Label 6033: @285341
106033 GIM_Try, /*On fail goto*//*Label 6034*/ GIMT_Encode4(285360), // Rule ID 2312 //
106034 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
106035 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
106036 // (smin:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (SMINWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
106037 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINWrr),
106038 GIR_RootConstrainSelectedInstOperands,
106039 // GIR_Coverage, 2312,
106040 GIR_Done,
106041 // Label 6034: @285360
106042 GIM_Reject,
106043 // Label 6032: @285361
106044 GIM_Reject,
106045 // Label 6024: @285362
106046 GIM_Try, /*On fail goto*//*Label 6035*/ GIMT_Encode4(285435),
106047 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
106048 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
106049 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
106050 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
106051 GIM_Try, /*On fail goto*//*Label 6036*/ GIMT_Encode4(285415), // Rule ID 2315 //
106052 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
106053 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
106054 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
106055 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm8_64b),
106056 // MIs[1] Operand 1
106057 // No operand predicates
106058 GIM_CheckIsSafeToFold, /*NumInsns*/1,
106059 // (smin:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm8_64b>>:$imm) => (SMINXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$imm)
106060 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINXri),
106061 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
106062 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
106063 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
106064 GIR_RootConstrainSelectedInstOperands,
106065 // GIR_Coverage, 2315,
106066 GIR_EraseRootFromParent_Done,
106067 // Label 6036: @285415
106068 GIM_Try, /*On fail goto*//*Label 6037*/ GIMT_Encode4(285434), // Rule ID 2314 //
106069 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
106070 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
106071 // (smin:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SMINXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
106072 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINXrr),
106073 GIR_RootConstrainSelectedInstOperands,
106074 // GIR_Coverage, 2314,
106075 GIR_Done,
106076 // Label 6037: @285434
106077 GIM_Reject,
106078 // Label 6035: @285435
106079 GIM_Reject,
106080 // Label 6025: @285436
106081 GIM_Try, /*On fail goto*//*Label 6038*/ GIMT_Encode4(285469), // Rule ID 1401 //
106082 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106083 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
106084 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
106085 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106086 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106087 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106088 // (smin:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMINv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
106089 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINv2i32),
106090 GIR_RootConstrainSelectedInstOperands,
106091 // GIR_Coverage, 1401,
106092 GIR_Done,
106093 // Label 6038: @285469
106094 GIM_Reject,
106095 // Label 6026: @285470
106096 GIM_Try, /*On fail goto*//*Label 6039*/ GIMT_Encode4(285503), // Rule ID 1399 //
106097 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106098 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
106099 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
106100 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106101 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106102 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106103 // (smin:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMINv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
106104 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINv4i16),
106105 GIR_RootConstrainSelectedInstOperands,
106106 // GIR_Coverage, 1399,
106107 GIR_Done,
106108 // Label 6039: @285503
106109 GIM_Reject,
106110 // Label 6027: @285504
106111 GIM_Try, /*On fail goto*//*Label 6040*/ GIMT_Encode4(285537), // Rule ID 1402 //
106112 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106113 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
106114 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
106115 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106116 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106117 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106118 // (smin:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SMINv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
106119 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINv4i32),
106120 GIR_RootConstrainSelectedInstOperands,
106121 // GIR_Coverage, 1402,
106122 GIR_Done,
106123 // Label 6040: @285537
106124 GIM_Reject,
106125 // Label 6028: @285538
106126 GIM_Try, /*On fail goto*//*Label 6041*/ GIMT_Encode4(285571), // Rule ID 1397 //
106127 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106128 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
106129 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
106130 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106131 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106132 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106133 // (smin:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMINv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
106134 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINv8i8),
106135 GIR_RootConstrainSelectedInstOperands,
106136 // GIR_Coverage, 1397,
106137 GIR_Done,
106138 // Label 6041: @285571
106139 GIM_Reject,
106140 // Label 6029: @285572
106141 GIM_Try, /*On fail goto*//*Label 6042*/ GIMT_Encode4(285605), // Rule ID 1400 //
106142 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106143 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
106144 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
106145 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106146 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106147 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106148 // (smin:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SMINv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
106149 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINv8i16),
106150 GIR_RootConstrainSelectedInstOperands,
106151 // GIR_Coverage, 1400,
106152 GIR_Done,
106153 // Label 6042: @285605
106154 GIM_Reject,
106155 // Label 6030: @285606
106156 GIM_Try, /*On fail goto*//*Label 6043*/ GIMT_Encode4(285639), // Rule ID 1398 //
106157 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106158 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
106159 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
106160 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106161 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106162 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106163 // (smin:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMINv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
106164 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINv16i8),
106165 GIR_RootConstrainSelectedInstOperands,
106166 // GIR_Coverage, 1398,
106167 GIR_Done,
106168 // Label 6043: @285639
106169 GIM_Reject,
106170 // Label 6031: @285640
106171 GIM_Reject,
106172 // Label 71: @285641
106173 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 6052*/ GIMT_Encode4(286044),
106174 /*GILLT_s32*//*Label 6044*/ GIMT_Encode4(285692),
106175 /*GILLT_s64*//*Label 6045*/ GIMT_Encode4(285766), GIMT_Encode4(0),
106176 /*GILLT_v2s32*//*Label 6046*/ GIMT_Encode4(285840), GIMT_Encode4(0),
106177 /*GILLT_v4s16*//*Label 6047*/ GIMT_Encode4(285874),
106178 /*GILLT_v4s32*//*Label 6048*/ GIMT_Encode4(285908),
106179 /*GILLT_v8s8*//*Label 6049*/ GIMT_Encode4(285942),
106180 /*GILLT_v8s16*//*Label 6050*/ GIMT_Encode4(285976),
106181 /*GILLT_v16s8*//*Label 6051*/ GIMT_Encode4(286010),
106182 // Label 6044: @285692
106183 GIM_Try, /*On fail goto*//*Label 6053*/ GIMT_Encode4(285765),
106184 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
106185 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
106186 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
106187 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
106188 GIM_Try, /*On fail goto*//*Label 6054*/ GIMT_Encode4(285745), // Rule ID 2309 //
106189 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
106190 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
106191 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
106192 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm8_32b),
106193 // MIs[1] Operand 1
106194 // No operand predicates
106195 GIM_CheckIsSafeToFold, /*NumInsns*/1,
106196 // (smax:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_simm8_32b>>:$imm) => (SMAXWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
106197 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXWri),
106198 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
106199 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
106200 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
106201 GIR_RootConstrainSelectedInstOperands,
106202 // GIR_Coverage, 2309,
106203 GIR_EraseRootFromParent_Done,
106204 // Label 6054: @285745
106205 GIM_Try, /*On fail goto*//*Label 6055*/ GIMT_Encode4(285764), // Rule ID 2308 //
106206 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
106207 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
106208 // (smax:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (SMAXWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
106209 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXWrr),
106210 GIR_RootConstrainSelectedInstOperands,
106211 // GIR_Coverage, 2308,
106212 GIR_Done,
106213 // Label 6055: @285764
106214 GIM_Reject,
106215 // Label 6053: @285765
106216 GIM_Reject,
106217 // Label 6045: @285766
106218 GIM_Try, /*On fail goto*//*Label 6056*/ GIMT_Encode4(285839),
106219 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
106220 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
106221 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
106222 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
106223 GIM_Try, /*On fail goto*//*Label 6057*/ GIMT_Encode4(285819), // Rule ID 2311 //
106224 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
106225 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
106226 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
106227 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm8_64b),
106228 // MIs[1] Operand 1
106229 // No operand predicates
106230 GIM_CheckIsSafeToFold, /*NumInsns*/1,
106231 // (smax:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm8_64b>>:$imm) => (SMAXXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$imm)
106232 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXXri),
106233 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
106234 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
106235 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
106236 GIR_RootConstrainSelectedInstOperands,
106237 // GIR_Coverage, 2311,
106238 GIR_EraseRootFromParent_Done,
106239 // Label 6057: @285819
106240 GIM_Try, /*On fail goto*//*Label 6058*/ GIMT_Encode4(285838), // Rule ID 2310 //
106241 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
106242 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
106243 // (smax:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (SMAXXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
106244 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXXrr),
106245 GIR_RootConstrainSelectedInstOperands,
106246 // GIR_Coverage, 2310,
106247 GIR_Done,
106248 // Label 6058: @285838
106249 GIM_Reject,
106250 // Label 6056: @285839
106251 GIM_Reject,
106252 // Label 6046: @285840
106253 GIM_Try, /*On fail goto*//*Label 6059*/ GIMT_Encode4(285873), // Rule ID 1389 //
106254 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106255 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
106256 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
106257 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106258 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106259 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106260 // (smax:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMAXv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
106261 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXv2i32),
106262 GIR_RootConstrainSelectedInstOperands,
106263 // GIR_Coverage, 1389,
106264 GIR_Done,
106265 // Label 6059: @285873
106266 GIM_Reject,
106267 // Label 6047: @285874
106268 GIM_Try, /*On fail goto*//*Label 6060*/ GIMT_Encode4(285907), // Rule ID 1387 //
106269 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106270 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
106271 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
106272 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106273 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106274 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106275 // (smax:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMAXv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
106276 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXv4i16),
106277 GIR_RootConstrainSelectedInstOperands,
106278 // GIR_Coverage, 1387,
106279 GIR_Done,
106280 // Label 6060: @285907
106281 GIM_Reject,
106282 // Label 6048: @285908
106283 GIM_Try, /*On fail goto*//*Label 6061*/ GIMT_Encode4(285941), // Rule ID 1390 //
106284 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106285 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
106286 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
106287 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106288 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106289 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106290 // (smax:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (SMAXv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
106291 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXv4i32),
106292 GIR_RootConstrainSelectedInstOperands,
106293 // GIR_Coverage, 1390,
106294 GIR_Done,
106295 // Label 6061: @285941
106296 GIM_Reject,
106297 // Label 6049: @285942
106298 GIM_Try, /*On fail goto*//*Label 6062*/ GIMT_Encode4(285975), // Rule ID 1385 //
106299 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106300 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
106301 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
106302 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106303 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106304 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106305 // (smax:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMAXv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
106306 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXv8i8),
106307 GIR_RootConstrainSelectedInstOperands,
106308 // GIR_Coverage, 1385,
106309 GIR_Done,
106310 // Label 6062: @285975
106311 GIM_Reject,
106312 // Label 6050: @285976
106313 GIM_Try, /*On fail goto*//*Label 6063*/ GIMT_Encode4(286009), // Rule ID 1388 //
106314 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106315 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
106316 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
106317 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106318 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106319 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106320 // (smax:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (SMAXv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
106321 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXv8i16),
106322 GIR_RootConstrainSelectedInstOperands,
106323 // GIR_Coverage, 1388,
106324 GIR_Done,
106325 // Label 6063: @286009
106326 GIM_Reject,
106327 // Label 6051: @286010
106328 GIM_Try, /*On fail goto*//*Label 6064*/ GIMT_Encode4(286043), // Rule ID 1386 //
106329 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106330 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
106331 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
106332 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106333 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106334 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106335 // (smax:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SMAXv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
106336 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXv16i8),
106337 GIR_RootConstrainSelectedInstOperands,
106338 // GIR_Coverage, 1386,
106339 GIR_Done,
106340 // Label 6064: @286043
106341 GIM_Reject,
106342 // Label 6052: @286044
106343 GIM_Reject,
106344 // Label 72: @286045
106345 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 6073*/ GIMT_Encode4(286448),
106346 /*GILLT_s32*//*Label 6065*/ GIMT_Encode4(286096),
106347 /*GILLT_s64*//*Label 6066*/ GIMT_Encode4(286170), GIMT_Encode4(0),
106348 /*GILLT_v2s32*//*Label 6067*/ GIMT_Encode4(286244), GIMT_Encode4(0),
106349 /*GILLT_v4s16*//*Label 6068*/ GIMT_Encode4(286278),
106350 /*GILLT_v4s32*//*Label 6069*/ GIMT_Encode4(286312),
106351 /*GILLT_v8s8*//*Label 6070*/ GIMT_Encode4(286346),
106352 /*GILLT_v8s16*//*Label 6071*/ GIMT_Encode4(286380),
106353 /*GILLT_v16s8*//*Label 6072*/ GIMT_Encode4(286414),
106354 // Label 6065: @286096
106355 GIM_Try, /*On fail goto*//*Label 6074*/ GIMT_Encode4(286169),
106356 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
106357 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
106358 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
106359 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
106360 GIM_Try, /*On fail goto*//*Label 6075*/ GIMT_Encode4(286149), // Rule ID 2321 //
106361 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
106362 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
106363 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
106364 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm8_32b),
106365 // MIs[1] Operand 1
106366 // No operand predicates
106367 GIM_CheckIsSafeToFold, /*NumInsns*/1,
106368 // (umin:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_uimm8_32b>>:$imm) => (UMINWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
106369 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINWri),
106370 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
106371 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
106372 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
106373 GIR_RootConstrainSelectedInstOperands,
106374 // GIR_Coverage, 2321,
106375 GIR_EraseRootFromParent_Done,
106376 // Label 6075: @286149
106377 GIM_Try, /*On fail goto*//*Label 6076*/ GIMT_Encode4(286168), // Rule ID 2320 //
106378 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
106379 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
106380 // (umin:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (UMINWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
106381 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINWrr),
106382 GIR_RootConstrainSelectedInstOperands,
106383 // GIR_Coverage, 2320,
106384 GIR_Done,
106385 // Label 6076: @286168
106386 GIM_Reject,
106387 // Label 6074: @286169
106388 GIM_Reject,
106389 // Label 6066: @286170
106390 GIM_Try, /*On fail goto*//*Label 6077*/ GIMT_Encode4(286243),
106391 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
106392 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
106393 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
106394 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
106395 GIM_Try, /*On fail goto*//*Label 6078*/ GIMT_Encode4(286223), // Rule ID 2323 //
106396 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
106397 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
106398 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
106399 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm8_64b),
106400 // MIs[1] Operand 1
106401 // No operand predicates
106402 GIM_CheckIsSafeToFold, /*NumInsns*/1,
106403 // (umin:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_uimm8_64b>>:$imm) => (UMINXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$imm)
106404 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINXri),
106405 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
106406 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
106407 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
106408 GIR_RootConstrainSelectedInstOperands,
106409 // GIR_Coverage, 2323,
106410 GIR_EraseRootFromParent_Done,
106411 // Label 6078: @286223
106412 GIM_Try, /*On fail goto*//*Label 6079*/ GIMT_Encode4(286242), // Rule ID 2322 //
106413 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
106414 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
106415 // (umin:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (UMINXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
106416 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINXrr),
106417 GIR_RootConstrainSelectedInstOperands,
106418 // GIR_Coverage, 2322,
106419 GIR_Done,
106420 // Label 6079: @286242
106421 GIM_Reject,
106422 // Label 6077: @286243
106423 GIM_Reject,
106424 // Label 6067: @286244
106425 GIM_Try, /*On fail goto*//*Label 6080*/ GIMT_Encode4(286277), // Rule ID 1524 //
106426 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106427 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
106428 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
106429 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106430 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106431 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106432 // (umin:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMINv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
106433 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINv2i32),
106434 GIR_RootConstrainSelectedInstOperands,
106435 // GIR_Coverage, 1524,
106436 GIR_Done,
106437 // Label 6080: @286277
106438 GIM_Reject,
106439 // Label 6068: @286278
106440 GIM_Try, /*On fail goto*//*Label 6081*/ GIMT_Encode4(286311), // Rule ID 1522 //
106441 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106442 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
106443 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
106444 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106445 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106446 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106447 // (umin:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMINv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
106448 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINv4i16),
106449 GIR_RootConstrainSelectedInstOperands,
106450 // GIR_Coverage, 1522,
106451 GIR_Done,
106452 // Label 6081: @286311
106453 GIM_Reject,
106454 // Label 6069: @286312
106455 GIM_Try, /*On fail goto*//*Label 6082*/ GIMT_Encode4(286345), // Rule ID 1525 //
106456 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106457 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
106458 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
106459 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106460 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106461 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106462 // (umin:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UMINv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
106463 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINv4i32),
106464 GIR_RootConstrainSelectedInstOperands,
106465 // GIR_Coverage, 1525,
106466 GIR_Done,
106467 // Label 6082: @286345
106468 GIM_Reject,
106469 // Label 6070: @286346
106470 GIM_Try, /*On fail goto*//*Label 6083*/ GIMT_Encode4(286379), // Rule ID 1520 //
106471 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106472 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
106473 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
106474 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106475 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106476 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106477 // (umin:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMINv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
106478 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINv8i8),
106479 GIR_RootConstrainSelectedInstOperands,
106480 // GIR_Coverage, 1520,
106481 GIR_Done,
106482 // Label 6083: @286379
106483 GIM_Reject,
106484 // Label 6071: @286380
106485 GIM_Try, /*On fail goto*//*Label 6084*/ GIMT_Encode4(286413), // Rule ID 1523 //
106486 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106487 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
106488 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
106489 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106490 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106491 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106492 // (umin:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UMINv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
106493 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINv8i16),
106494 GIR_RootConstrainSelectedInstOperands,
106495 // GIR_Coverage, 1523,
106496 GIR_Done,
106497 // Label 6084: @286413
106498 GIM_Reject,
106499 // Label 6072: @286414
106500 GIM_Try, /*On fail goto*//*Label 6085*/ GIMT_Encode4(286447), // Rule ID 1521 //
106501 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106502 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
106503 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
106504 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106505 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106506 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106507 // (umin:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMINv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
106508 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINv16i8),
106509 GIR_RootConstrainSelectedInstOperands,
106510 // GIR_Coverage, 1521,
106511 GIR_Done,
106512 // Label 6085: @286447
106513 GIM_Reject,
106514 // Label 6073: @286448
106515 GIM_Reject,
106516 // Label 73: @286449
106517 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 6094*/ GIMT_Encode4(286852),
106518 /*GILLT_s32*//*Label 6086*/ GIMT_Encode4(286500),
106519 /*GILLT_s64*//*Label 6087*/ GIMT_Encode4(286574), GIMT_Encode4(0),
106520 /*GILLT_v2s32*//*Label 6088*/ GIMT_Encode4(286648), GIMT_Encode4(0),
106521 /*GILLT_v4s16*//*Label 6089*/ GIMT_Encode4(286682),
106522 /*GILLT_v4s32*//*Label 6090*/ GIMT_Encode4(286716),
106523 /*GILLT_v8s8*//*Label 6091*/ GIMT_Encode4(286750),
106524 /*GILLT_v8s16*//*Label 6092*/ GIMT_Encode4(286784),
106525 /*GILLT_v16s8*//*Label 6093*/ GIMT_Encode4(286818),
106526 // Label 6086: @286500
106527 GIM_Try, /*On fail goto*//*Label 6095*/ GIMT_Encode4(286573),
106528 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
106529 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
106530 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
106531 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
106532 GIM_Try, /*On fail goto*//*Label 6096*/ GIMT_Encode4(286553), // Rule ID 2317 //
106533 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
106534 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
106535 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
106536 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm8_32b),
106537 // MIs[1] Operand 1
106538 // No operand predicates
106539 GIM_CheckIsSafeToFold, /*NumInsns*/1,
106540 // (umax:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_uimm8_32b>>:$imm) => (UMAXWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
106541 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXWri),
106542 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
106543 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
106544 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
106545 GIR_RootConstrainSelectedInstOperands,
106546 // GIR_Coverage, 2317,
106547 GIR_EraseRootFromParent_Done,
106548 // Label 6096: @286553
106549 GIM_Try, /*On fail goto*//*Label 6097*/ GIMT_Encode4(286572), // Rule ID 2316 //
106550 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
106551 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
106552 // (umax:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm) => (UMAXWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
106553 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXWrr),
106554 GIR_RootConstrainSelectedInstOperands,
106555 // GIR_Coverage, 2316,
106556 GIR_Done,
106557 // Label 6097: @286572
106558 GIM_Reject,
106559 // Label 6095: @286573
106560 GIM_Reject,
106561 // Label 6087: @286574
106562 GIM_Try, /*On fail goto*//*Label 6098*/ GIMT_Encode4(286647),
106563 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
106564 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
106565 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
106566 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
106567 GIM_Try, /*On fail goto*//*Label 6099*/ GIMT_Encode4(286627), // Rule ID 2319 //
106568 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
106569 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
106570 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
106571 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm8_64b),
106572 // MIs[1] Operand 1
106573 // No operand predicates
106574 GIM_CheckIsSafeToFold, /*NumInsns*/1,
106575 // (umax:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_uimm8_64b>>:$imm) => (UMAXXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$imm)
106576 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXXri),
106577 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
106578 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
106579 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
106580 GIR_RootConstrainSelectedInstOperands,
106581 // GIR_Coverage, 2319,
106582 GIR_EraseRootFromParent_Done,
106583 // Label 6099: @286627
106584 GIM_Try, /*On fail goto*//*Label 6100*/ GIMT_Encode4(286646), // Rule ID 2318 //
106585 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
106586 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
106587 // (umax:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm) => (UMAXXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
106588 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXXrr),
106589 GIR_RootConstrainSelectedInstOperands,
106590 // GIR_Coverage, 2318,
106591 GIR_Done,
106592 // Label 6100: @286646
106593 GIM_Reject,
106594 // Label 6098: @286647
106595 GIM_Reject,
106596 // Label 6088: @286648
106597 GIM_Try, /*On fail goto*//*Label 6101*/ GIMT_Encode4(286681), // Rule ID 1512 //
106598 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106599 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
106600 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
106601 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106602 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106603 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106604 // (umax:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMAXv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
106605 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXv2i32),
106606 GIR_RootConstrainSelectedInstOperands,
106607 // GIR_Coverage, 1512,
106608 GIR_Done,
106609 // Label 6101: @286681
106610 GIM_Reject,
106611 // Label 6089: @286682
106612 GIM_Try, /*On fail goto*//*Label 6102*/ GIMT_Encode4(286715), // Rule ID 1510 //
106613 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106614 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
106615 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
106616 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106617 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106618 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106619 // (umax:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMAXv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
106620 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXv4i16),
106621 GIR_RootConstrainSelectedInstOperands,
106622 // GIR_Coverage, 1510,
106623 GIR_Done,
106624 // Label 6102: @286715
106625 GIM_Reject,
106626 // Label 6090: @286716
106627 GIM_Try, /*On fail goto*//*Label 6103*/ GIMT_Encode4(286749), // Rule ID 1513 //
106628 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106629 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
106630 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
106631 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106632 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106633 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106634 // (umax:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UMAXv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
106635 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXv4i32),
106636 GIR_RootConstrainSelectedInstOperands,
106637 // GIR_Coverage, 1513,
106638 GIR_Done,
106639 // Label 6103: @286749
106640 GIM_Reject,
106641 // Label 6091: @286750
106642 GIM_Try, /*On fail goto*//*Label 6104*/ GIMT_Encode4(286783), // Rule ID 1508 //
106643 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106644 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
106645 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
106646 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106647 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106648 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106649 // (umax:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMAXv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
106650 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXv8i8),
106651 GIR_RootConstrainSelectedInstOperands,
106652 // GIR_Coverage, 1508,
106653 GIR_Done,
106654 // Label 6104: @286783
106655 GIM_Reject,
106656 // Label 6092: @286784
106657 GIM_Try, /*On fail goto*//*Label 6105*/ GIMT_Encode4(286817), // Rule ID 1511 //
106658 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106659 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
106660 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
106661 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106662 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106663 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106664 // (umax:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UMAXv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
106665 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXv8i16),
106666 GIR_RootConstrainSelectedInstOperands,
106667 // GIR_Coverage, 1511,
106668 GIR_Done,
106669 // Label 6105: @286817
106670 GIM_Reject,
106671 // Label 6093: @286818
106672 GIM_Try, /*On fail goto*//*Label 6106*/ GIMT_Encode4(286851), // Rule ID 1509 //
106673 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106674 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
106675 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
106676 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106677 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106678 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106679 // (umax:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UMAXv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
106680 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXv16i8),
106681 GIR_RootConstrainSelectedInstOperands,
106682 // GIR_Coverage, 1509,
106683 GIR_Done,
106684 // Label 6106: @286851
106685 GIM_Reject,
106686 // Label 6094: @286852
106687 GIM_Reject,
106688 // Label 74: @286853
106689 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 6116*/ GIMT_Encode4(287667),
106690 /*GILLT_s32*//*Label 6107*/ GIMT_Encode4(286904),
106691 /*GILLT_s64*//*Label 6108*/ GIMT_Encode4(286931), GIMT_Encode4(0),
106692 /*GILLT_v2s32*//*Label 6109*/ GIMT_Encode4(287010),
106693 /*GILLT_v2s64*//*Label 6110*/ GIMT_Encode4(287037),
106694 /*GILLT_v4s16*//*Label 6111*/ GIMT_Encode4(287220),
106695 /*GILLT_v4s32*//*Label 6112*/ GIMT_Encode4(287247),
106696 /*GILLT_v8s8*//*Label 6113*/ GIMT_Encode4(287430),
106697 /*GILLT_v8s16*//*Label 6114*/ GIMT_Encode4(287457),
106698 /*GILLT_v16s8*//*Label 6115*/ GIMT_Encode4(287640),
106699 // Label 6107: @286904
106700 GIM_Try, /*On fail goto*//*Label 6117*/ GIMT_Encode4(286930), // Rule ID 2302 //
106701 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
106702 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
106703 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
106704 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
106705 // (abs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (ABSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
106706 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSWr),
106707 GIR_RootConstrainSelectedInstOperands,
106708 // GIR_Coverage, 2302,
106709 GIR_Done,
106710 // Label 6117: @286930
106711 GIM_Reject,
106712 // Label 6108: @286931
106713 GIM_Try, /*On fail goto*//*Label 6118*/ GIMT_Encode4(287009),
106714 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
106715 GIM_Try, /*On fail goto*//*Label 6119*/ GIMT_Encode4(286962), // Rule ID 1639 //
106716 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106717 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106718 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106719 // (abs:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn) => (ABSv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
106720 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv1i64),
106721 GIR_RootConstrainSelectedInstOperands,
106722 // GIR_Coverage, 1639,
106723 GIR_Done,
106724 // Label 6119: @286962
106725 GIM_Try, /*On fail goto*//*Label 6120*/ GIMT_Encode4(286985), // Rule ID 2303 //
106726 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
106727 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
106728 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
106729 // (abs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (ABSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
106730 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSXr),
106731 GIR_RootConstrainSelectedInstOperands,
106732 // GIR_Coverage, 2303,
106733 GIR_Done,
106734 // Label 6120: @286985
106735 GIM_Try, /*On fail goto*//*Label 6121*/ GIMT_Encode4(287008), // Rule ID 2436 //
106736 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoCSSC),
106737 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106738 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106739 // (abs:{ *:[i64] } FPR64:{ *:[i64] }:$Rn) => (ABSv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn)
106740 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv1i64),
106741 GIR_RootConstrainSelectedInstOperands,
106742 // GIR_Coverage, 2436,
106743 GIR_Done,
106744 // Label 6121: @287008
106745 GIM_Reject,
106746 // Label 6118: @287009
106747 GIM_Reject,
106748 // Label 6109: @287010
106749 GIM_Try, /*On fail goto*//*Label 6122*/ GIMT_Encode4(287036), // Rule ID 701 //
106750 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106751 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
106752 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106753 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106754 // (abs:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) => (ABSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
106755 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv2i32),
106756 GIR_RootConstrainSelectedInstOperands,
106757 // GIR_Coverage, 701,
106758 GIR_Done,
106759 // Label 6122: @287036
106760 GIM_Reject,
106761 // Label 6110: @287037
106762 GIM_Try, /*On fail goto*//*Label 6123*/ GIMT_Encode4(287219),
106763 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
106764 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106765 GIM_Try, /*On fail goto*//*Label 6124*/ GIMT_Encode4(287127), // Rule ID 4549 //
106766 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
106767 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
106768 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
106769 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
106770 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
106771 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
106772 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
106773 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
106774 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
106775 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s32,
106776 GIM_CheckIsSafeToFold, /*NumInsns*/3,
106777 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
106778 GIM_CheckComplexPattern, /*MI*/3, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
106779 // (abs:{ *:[v2i64] } (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$opA)), (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$opB)))) => (UABDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$opA, V128:{ *:[v4i32] }:$opB)
106780 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv4i32_v2i64),
106781 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
106782 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // opA
106783 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // opB
106784 GIR_RootConstrainSelectedInstOperands,
106785 // GIR_Coverage, 4549,
106786 GIR_EraseRootFromParent_Done,
106787 // Label 6124: @287127
106788 GIM_Try, /*On fail goto*//*Label 6125*/ GIMT_Encode4(287199), // Rule ID 4548 //
106789 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
106790 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
106791 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
106792 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
106793 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
106794 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
106795 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
106796 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106797 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
106798 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
106799 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s32,
106800 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106801 GIM_CheckIsSafeToFold, /*NumInsns*/3,
106802 // (abs:{ *:[v2i64] } (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$opA), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$opB))) => (UABDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$opA, V64:{ *:[v2i32] }:$opB)
106803 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv2i32_v2i64),
106804 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
106805 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // opA
106806 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opB
106807 GIR_RootConstrainSelectedInstOperands,
106808 // GIR_Coverage, 4548,
106809 GIR_EraseRootFromParent_Done,
106810 // Label 6125: @287199
106811 GIM_Try, /*On fail goto*//*Label 6126*/ GIMT_Encode4(287218), // Rule ID 703 //
106812 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106813 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106814 // (abs:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) => (ABSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
106815 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv2i64),
106816 GIR_RootConstrainSelectedInstOperands,
106817 // GIR_Coverage, 703,
106818 GIR_Done,
106819 // Label 6126: @287218
106820 GIM_Reject,
106821 // Label 6123: @287219
106822 GIM_Reject,
106823 // Label 6111: @287220
106824 GIM_Try, /*On fail goto*//*Label 6127*/ GIMT_Encode4(287246), // Rule ID 699 //
106825 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106826 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
106827 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106828 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106829 // (abs:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) => (ABSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
106830 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv4i16),
106831 GIR_RootConstrainSelectedInstOperands,
106832 // GIR_Coverage, 699,
106833 GIR_Done,
106834 // Label 6127: @287246
106835 GIM_Reject,
106836 // Label 6112: @287247
106837 GIM_Try, /*On fail goto*//*Label 6128*/ GIMT_Encode4(287429),
106838 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
106839 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106840 GIM_Try, /*On fail goto*//*Label 6129*/ GIMT_Encode4(287337), // Rule ID 4547 //
106841 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
106842 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
106843 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
106844 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
106845 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
106846 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
106847 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
106848 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
106849 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
106850 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16,
106851 GIM_CheckIsSafeToFold, /*NumInsns*/3,
106852 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
106853 GIM_CheckComplexPattern, /*MI*/3, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
106854 // (abs:{ *:[v4i32] } (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$opA)), (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$opB)))) => (UABDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$opA, V128:{ *:[v8i16] }:$opB)
106855 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv8i16_v4i32),
106856 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
106857 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // opA
106858 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // opB
106859 GIR_RootConstrainSelectedInstOperands,
106860 // GIR_Coverage, 4547,
106861 GIR_EraseRootFromParent_Done,
106862 // Label 6129: @287337
106863 GIM_Try, /*On fail goto*//*Label 6130*/ GIMT_Encode4(287409), // Rule ID 4546 //
106864 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
106865 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
106866 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
106867 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
106868 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
106869 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
106870 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
106871 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106872 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
106873 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
106874 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16,
106875 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106876 GIM_CheckIsSafeToFold, /*NumInsns*/3,
106877 // (abs:{ *:[v4i32] } (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$opA), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$opB))) => (UABDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$opA, V64:{ *:[v4i16] }:$opB)
106878 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv4i16_v4i32),
106879 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
106880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // opA
106881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opB
106882 GIR_RootConstrainSelectedInstOperands,
106883 // GIR_Coverage, 4546,
106884 GIR_EraseRootFromParent_Done,
106885 // Label 6130: @287409
106886 GIM_Try, /*On fail goto*//*Label 6131*/ GIMT_Encode4(287428), // Rule ID 702 //
106887 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106888 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106889 // (abs:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) => (ABSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
106890 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv4i32),
106891 GIR_RootConstrainSelectedInstOperands,
106892 // GIR_Coverage, 702,
106893 GIR_Done,
106894 // Label 6131: @287428
106895 GIM_Reject,
106896 // Label 6128: @287429
106897 GIM_Reject,
106898 // Label 6113: @287430
106899 GIM_Try, /*On fail goto*//*Label 6132*/ GIMT_Encode4(287456), // Rule ID 697 //
106900 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106901 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
106902 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106903 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106904 // (abs:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (ABSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
106905 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv8i8),
106906 GIR_RootConstrainSelectedInstOperands,
106907 // GIR_Coverage, 697,
106908 GIR_Done,
106909 // Label 6132: @287456
106910 GIM_Reject,
106911 // Label 6114: @287457
106912 GIM_Try, /*On fail goto*//*Label 6133*/ GIMT_Encode4(287639),
106913 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
106914 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106915 GIM_Try, /*On fail goto*//*Label 6134*/ GIMT_Encode4(287547), // Rule ID 4545 //
106916 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
106917 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
106918 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
106919 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
106920 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
106921 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
106922 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
106923 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
106924 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
106925 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s8,
106926 GIM_CheckIsSafeToFold, /*NumInsns*/3,
106927 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
106928 GIM_CheckComplexPattern, /*MI*/3, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
106929 // (abs:{ *:[v8i16] } (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$opA)), (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$opB)))) => (UABDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$opA, V128:{ *:[v16i8] }:$opB)
106930 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv16i8_v8i16),
106931 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
106932 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // opA
106933 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // opB
106934 GIR_RootConstrainSelectedInstOperands,
106935 // GIR_Coverage, 4545,
106936 GIR_EraseRootFromParent_Done,
106937 // Label 6134: @287547
106938 GIM_Try, /*On fail goto*//*Label 6135*/ GIMT_Encode4(287619), // Rule ID 4544 //
106939 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
106940 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
106941 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
106942 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
106943 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
106944 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
106945 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
106946 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106947 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
106948 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
106949 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s8,
106950 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
106951 GIM_CheckIsSafeToFold, /*NumInsns*/3,
106952 // (abs:{ *:[v8i16] } (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$opB))) => (UABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$opA, V64:{ *:[v8i8] }:$opB)
106953 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv8i8_v8i16),
106954 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
106955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // opA
106956 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opB
106957 GIR_RootConstrainSelectedInstOperands,
106958 // GIR_Coverage, 4544,
106959 GIR_EraseRootFromParent_Done,
106960 // Label 6135: @287619
106961 GIM_Try, /*On fail goto*//*Label 6136*/ GIMT_Encode4(287638), // Rule ID 700 //
106962 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106963 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106964 // (abs:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) => (ABSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
106965 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv8i16),
106966 GIR_RootConstrainSelectedInstOperands,
106967 // GIR_Coverage, 700,
106968 GIR_Done,
106969 // Label 6136: @287638
106970 GIM_Reject,
106971 // Label 6133: @287639
106972 GIM_Reject,
106973 // Label 6115: @287640
106974 GIM_Try, /*On fail goto*//*Label 6137*/ GIMT_Encode4(287666), // Rule ID 698 //
106975 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
106976 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
106977 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106978 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
106979 // (abs:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (ABSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
106980 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv16i8),
106981 GIR_RootConstrainSelectedInstOperands,
106982 // GIR_Coverage, 698,
106983 GIR_Done,
106984 // Label 6137: @287666
106985 GIM_Reject,
106986 // Label 6116: @287667
106987 GIM_Reject,
106988 // Label 75: @287668
106989 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 6140*/ GIMT_Encode4(287833),
106990 /*GILLT_s32*//*Label 6138*/ GIMT_Encode4(287687),
106991 /*GILLT_s64*//*Label 6139*/ GIMT_Encode4(287760),
106992 // Label 6138: @287687
106993 GIM_Try, /*On fail goto*//*Label 6141*/ GIMT_Encode4(287713), // Rule ID 4417 //
106994 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
106995 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
106996 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
106997 // (lround:{ *:[i32] } f16:{ *:[f16] }:$Rn) => (FCVTASUWHr:{ *:[i32] } f16:{ *:[f16] }:$Rn)
106998 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWHr),
106999 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
107000 GIR_RootConstrainSelectedInstOperands,
107001 // GIR_Coverage, 4417,
107002 GIR_Done,
107003 // Label 6141: @287713
107004 GIM_Try, /*On fail goto*//*Label 6142*/ GIMT_Encode4(287736), // Rule ID 4423 //
107005 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
107006 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
107007 // (lround:{ *:[i32] } f32:{ *:[f32] }:$Rn) => (FCVTASUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
107008 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWSr),
107009 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
107010 GIR_RootConstrainSelectedInstOperands,
107011 // GIR_Coverage, 4423,
107012 GIR_Done,
107013 // Label 6142: @287736
107014 GIM_Try, /*On fail goto*//*Label 6143*/ GIMT_Encode4(287759), // Rule ID 4425 //
107015 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
107016 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
107017 // (lround:{ *:[i32] } f64:{ *:[f64] }:$Rn) => (FCVTASUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
107018 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWDr),
107019 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
107020 GIR_RootConstrainSelectedInstOperands,
107021 // GIR_Coverage, 4425,
107022 GIR_Done,
107023 // Label 6143: @287759
107024 GIM_Reject,
107025 // Label 6139: @287760
107026 GIM_Try, /*On fail goto*//*Label 6144*/ GIMT_Encode4(287786), // Rule ID 4419 //
107027 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
107028 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
107029 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
107030 // (lround:{ *:[i64] } f16:{ *:[f16] }:$Rn) => (FCVTASUXHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
107031 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXHr),
107032 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
107033 GIR_RootConstrainSelectedInstOperands,
107034 // GIR_Coverage, 4419,
107035 GIR_Done,
107036 // Label 6144: @287786
107037 GIM_Try, /*On fail goto*//*Label 6145*/ GIMT_Encode4(287809), // Rule ID 4427 //
107038 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
107039 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
107040 // (lround:{ *:[i64] } f32:{ *:[f32] }:$Rn) => (FCVTASUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
107041 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXSr),
107042 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
107043 GIR_RootConstrainSelectedInstOperands,
107044 // GIR_Coverage, 4427,
107045 GIR_Done,
107046 // Label 6145: @287809
107047 GIM_Try, /*On fail goto*//*Label 6146*/ GIMT_Encode4(287832), // Rule ID 4429 //
107048 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
107049 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
107050 // (lround:{ *:[i64] } f64:{ *:[f64] }:$Rn) => (FCVTASUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
107051 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXDr),
107052 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
107053 GIR_RootConstrainSelectedInstOperands,
107054 // GIR_Coverage, 4429,
107055 GIR_Done,
107056 // Label 6146: @287832
107057 GIM_Reject,
107058 // Label 6140: @287833
107059 GIM_Reject,
107060 // Label 76: @287834
107061 GIM_Try, /*On fail goto*//*Label 6147*/ GIMT_Encode4(287932),
107062 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
107063 GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 6151*/ GIMT_Encode4(287931),
107064 /*GILLT_s16*//*Label 6148*/ GIMT_Encode4(287865),
107065 /*GILLT_s32*//*Label 6149*/ GIMT_Encode4(287889),
107066 /*GILLT_s64*//*Label 6150*/ GIMT_Encode4(287910),
107067 // Label 6148: @287865
107068 GIM_Try, /*On fail goto*//*Label 6152*/ GIMT_Encode4(287888), // Rule ID 4421 //
107069 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
107070 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
107071 // (llround:{ *:[i64] } f16:{ *:[f16] }:$Rn) => (FCVTASUXHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
107072 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXHr),
107073 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
107074 GIR_RootConstrainSelectedInstOperands,
107075 // GIR_Coverage, 4421,
107076 GIR_Done,
107077 // Label 6152: @287888
107078 GIM_Reject,
107079 // Label 6149: @287889
107080 GIM_Try, /*On fail goto*//*Label 6153*/ GIMT_Encode4(287909), // Rule ID 4431 //
107081 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
107082 // (llround:{ *:[i64] } f32:{ *:[f32] }:$Rn) => (FCVTASUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
107083 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXSr),
107084 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
107085 GIR_RootConstrainSelectedInstOperands,
107086 // GIR_Coverage, 4431,
107087 GIR_Done,
107088 // Label 6153: @287909
107089 GIM_Reject,
107090 // Label 6150: @287910
107091 GIM_Try, /*On fail goto*//*Label 6154*/ GIMT_Encode4(287930), // Rule ID 4433 //
107092 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
107093 // (llround:{ *:[i64] } f64:{ *:[f64] }:$Rn) => (FCVTASUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
107094 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXDr),
107095 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
107096 GIR_RootConstrainSelectedInstOperands,
107097 // GIR_Coverage, 4433,
107098 GIR_Done,
107099 // Label 6154: @287930
107100 GIM_Reject,
107101 // Label 6151: @287931
107102 GIM_Reject,
107103 // Label 6147: @287932
107104 GIM_Reject,
107105 // Label 77: @287933
107106 GIM_Try, /*On fail goto*//*Label 6155*/ GIMT_Encode4(287948), // Rule ID 235 //
107107 // MIs[0] addr
107108 GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
107109 // (br (bb:{ *:[Other] }):$addr) => (B (bb:{ *:[Other] }):$addr)
107110 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::B),
107111 GIR_RootConstrainSelectedInstOperands,
107112 // GIR_Coverage, 235,
107113 GIR_Done,
107114 // Label 6155: @287948
107115 GIM_Reject,
107116 // Label 78: @287949
107117 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(24), /*)*//*default:*//*Label 6171*/ GIMT_Encode4(303315),
107118 /*GILLT_s64*//*Label 6156*/ GIMT_Encode4(288044), GIMT_Encode4(0),
107119 /*GILLT_v2s32*//*Label 6157*/ GIMT_Encode4(288634),
107120 /*GILLT_v2s64*//*Label 6158*/ GIMT_Encode4(290589),
107121 /*GILLT_v4s16*//*Label 6159*/ GIMT_Encode4(292030),
107122 /*GILLT_v4s32*//*Label 6160*/ GIMT_Encode4(294760),
107123 /*GILLT_v8s8*//*Label 6161*/ GIMT_Encode4(296036),
107124 /*GILLT_v8s16*//*Label 6162*/ GIMT_Encode4(297071),
107125 /*GILLT_v16s8*//*Label 6163*/ GIMT_Encode4(298995), GIMT_Encode4(0), GIMT_Encode4(0),
107126 /*GILLT_nxv2s16*//*Label 6164*/ GIMT_Encode4(299766),
107127 /*GILLT_nxv2s32*//*Label 6165*/ GIMT_Encode4(300000),
107128 /*GILLT_nxv2s64*//*Label 6166*/ GIMT_Encode4(300125), GIMT_Encode4(0),
107129 /*GILLT_nxv4s16*//*Label 6167*/ GIMT_Encode4(300783),
107130 /*GILLT_nxv4s32*//*Label 6168*/ GIMT_Encode4(301071), GIMT_Encode4(0),
107131 /*GILLT_nxv8s16*//*Label 6169*/ GIMT_Encode4(301783), GIMT_Encode4(0),
107132 /*GILLT_nxv16s8*//*Label 6170*/ GIMT_Encode4(302935),
107133 // Label 6156: @288044
107134 GIM_Try, /*On fail goto*//*Label 6172*/ GIMT_Encode4(288633),
107135 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
107136 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
107137 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
107138 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
107139 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
107140 GIM_Try, /*On fail goto*//*Label 6173*/ GIMT_Encode4(288192), // Rule ID 5372 //
107141 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
107142 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
107143 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
107144 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
107145 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
107146 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
107147 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107148 // MIs[2] Operand 1
107149 // No operand predicates
107150 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
107151 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107152 // MIs[3] Operand 1
107153 // No operand predicates
107154 GIM_CheckIsSafeToFold, /*NumInsns*/3,
107155 // (vector_insert:{ *:[v1f64] } V64:{ *:[v1f64] }:$src, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (EXTRACT_SUBREG:{ *:[v1f64] } (INSvi64lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v1f64] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
107156 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
107157 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
107158 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107159 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107160 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
107161 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
107162 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
107163 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107164 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107165 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
107166 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107167 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
107168 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
107169 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
107170 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
107171 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107172 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
107173 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107174 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
107175 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
107176 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107177 // GIR_Coverage, 5372,
107178 GIR_EraseRootFromParent_Done,
107179 // Label 6173: @288192
107180 GIM_Try, /*On fail goto*//*Label 6174*/ GIMT_Encode4(288349), // Rule ID 5373 //
107181 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
107182 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
107183 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
107184 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
107185 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
107186 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
107187 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107188 // MIs[2] Operand 1
107189 // No operand predicates
107190 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
107191 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107192 // MIs[3] Operand 1
107193 // No operand predicates
107194 GIM_CheckIsSafeToFold, /*NumInsns*/3,
107195 // (vector_insert:{ *:[v1f64] } V64:{ *:[v1f64] }:$src, (vector_extract:{ *:[f64] } V64:{ *:[v1f64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (EXTRACT_SUBREG:{ *:[v1f64] } (INSvi64lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v1f64] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v1f64] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
107196 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
107197 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
107198 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
107199 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107200 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107201 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
107202 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
107203 GIR_AddImm8, /*InsnID*/3, /*Imm*/2,
107204 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107205 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107206 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107207 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107208 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
107209 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
107210 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
107211 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107212 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107213 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
107214 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107215 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
107216 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
107217 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
107218 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
107219 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107220 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
107221 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107222 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
107223 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
107224 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107225 // GIR_Coverage, 5373,
107226 GIR_EraseRootFromParent_Done,
107227 // Label 6174: @288349
107228 GIM_Try, /*On fail goto*//*Label 6175*/ GIMT_Encode4(288475), // Rule ID 5388 //
107229 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
107230 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
107231 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
107232 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
107233 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
107234 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
107235 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107236 // MIs[2] Operand 1
107237 // No operand predicates
107238 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
107239 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107240 // MIs[3] Operand 1
107241 // No operand predicates
107242 GIM_CheckIsSafeToFold, /*NumInsns*/3,
107243 // (vector_insert:{ *:[v1i64] } V64:{ *:[v1i64] }:$src, (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (EXTRACT_SUBREG:{ *:[v1i64] } (INSvi64lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v1i64] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
107244 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
107245 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
107246 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107247 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107248 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
107249 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
107250 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
107251 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107252 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107253 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
107254 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107255 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
107256 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
107257 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
107258 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
107259 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107260 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
107261 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107262 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
107263 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
107264 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107265 // GIR_Coverage, 5388,
107266 GIR_EraseRootFromParent_Done,
107267 // Label 6175: @288475
107268 GIM_Try, /*On fail goto*//*Label 6176*/ GIMT_Encode4(288632), // Rule ID 5389 //
107269 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
107270 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
107271 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
107272 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
107273 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
107274 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
107275 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107276 // MIs[2] Operand 1
107277 // No operand predicates
107278 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
107279 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107280 // MIs[3] Operand 1
107281 // No operand predicates
107282 GIM_CheckIsSafeToFold, /*NumInsns*/3,
107283 // (vector_insert:{ *:[v1i64] } V64:{ *:[v1i64] }:$src, (vector_extract:{ *:[i64] } V64:{ *:[v1i64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (EXTRACT_SUBREG:{ *:[v1i64] } (INSvi64lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v1i64] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
107284 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
107285 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
107286 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
107287 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107288 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107289 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
107290 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
107291 GIR_AddImm8, /*InsnID*/3, /*Imm*/2,
107292 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107293 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107294 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107295 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107296 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
107297 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
107298 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
107299 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107300 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107301 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
107302 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107303 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
107304 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
107305 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
107306 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
107307 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107308 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
107309 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107310 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
107311 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
107312 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107313 // GIR_Coverage, 5389,
107314 GIR_EraseRootFromParent_Done,
107315 // Label 6176: @288632
107316 GIM_Reject,
107317 // Label 6172: @288633
107318 GIM_Reject,
107319 // Label 6157: @288634
107320 GIM_Try, /*On fail goto*//*Label 6177*/ GIMT_Encode4(290588),
107321 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
107322 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
107323 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
107324 GIM_Try, /*On fail goto*//*Label 6178*/ GIMT_Encode4(288756), // Rule ID 4108 //
107325 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
107326 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
107327 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
107328 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
107329 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
107330 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
107331 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
107332 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
107333 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
107334 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
107335 GIM_CheckIsSafeToFold, /*NumInsns*/2,
107336 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
107337 // (vector_insert:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v2i32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
107338 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
107339 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
107340 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107341 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
107342 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
107343 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
107344 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107345 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107346 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107347 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
107348 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
107349 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
107350 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
107351 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
107352 // GIR_Coverage, 4108,
107353 GIR_EraseRootFromParent_Done,
107354 // Label 6178: @288756
107355 GIM_Try, /*On fail goto*//*Label 6179*/ GIMT_Encode4(288864), // Rule ID 4109 //
107356 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
107357 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
107358 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
107359 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
107360 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
107361 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
107362 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
107363 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
107364 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
107365 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
107366 GIM_CheckIsSafeToFold, /*NumInsns*/2,
107367 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
107368 // (vector_insert:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v2i32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
107369 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
107370 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
107371 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107372 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
107373 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
107374 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
107375 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107376 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107377 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107378 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
107379 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
107380 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
107381 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
107382 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
107383 // GIR_Coverage, 4109,
107384 GIR_EraseRootFromParent_Done,
107385 // Label 6179: @288864
107386 GIM_Try, /*On fail goto*//*Label 6180*/ GIMT_Encode4(288972), // Rule ID 4132 //
107387 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
107388 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
107389 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
107390 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
107391 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
107392 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
107393 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
107394 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
107395 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
107396 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
107397 GIM_CheckIsSafeToFold, /*NumInsns*/2,
107398 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
107399 // (vector_insert:{ *:[v2f32] } immAllZerosV:{ *:[v2f32] }, (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v2f32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
107400 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
107401 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
107402 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107403 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
107404 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
107405 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
107406 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107407 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107408 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107409 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
107410 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
107411 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
107412 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
107413 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
107414 // GIR_Coverage, 4132,
107415 GIR_EraseRootFromParent_Done,
107416 // Label 6180: @288972
107417 GIM_Try, /*On fail goto*//*Label 6181*/ GIMT_Encode4(289080), // Rule ID 4133 //
107418 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
107419 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
107420 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
107421 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
107422 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
107423 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
107424 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
107425 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
107426 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
107427 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
107428 GIM_CheckIsSafeToFold, /*NumInsns*/2,
107429 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
107430 // (vector_insert:{ *:[v2f32] } immAllZerosV:{ *:[v2f32] }, (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v2f32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
107431 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
107432 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
107433 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107434 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
107435 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
107436 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
107437 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107438 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107439 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107440 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
107441 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
107442 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
107443 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
107444 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
107445 // GIR_Coverage, 4133,
107446 GIR_EraseRootFromParent_Done,
107447 // Label 6181: @289080
107448 GIM_Try, /*On fail goto*//*Label 6182*/ GIMT_Encode4(289214), // Rule ID 5368 //
107449 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
107450 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
107451 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
107452 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
107453 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
107454 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
107455 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
107456 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
107457 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107458 // MIs[2] Operand 1
107459 // No operand predicates
107460 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
107461 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107462 // MIs[3] Operand 1
107463 // No operand predicates
107464 GIM_CheckIsSafeToFold, /*NumInsns*/3,
107465 // (vector_insert:{ *:[v2f32] } V64:{ *:[v2f32] }:$src, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (EXTRACT_SUBREG:{ *:[v2f32] } (INSvi32lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v2f32] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
107466 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
107467 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
107468 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107469 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107470 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
107471 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
107472 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
107473 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107474 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107475 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
107476 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107477 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
107478 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
107479 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
107480 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
107481 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107482 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
107483 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107484 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
107485 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
107486 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107487 // GIR_Coverage, 5368,
107488 GIR_EraseRootFromParent_Done,
107489 // Label 6182: @289214
107490 GIM_Try, /*On fail goto*//*Label 6183*/ GIMT_Encode4(289379), // Rule ID 5369 //
107491 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
107492 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
107493 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
107494 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
107495 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
107496 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
107497 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
107498 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
107499 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107500 // MIs[2] Operand 1
107501 // No operand predicates
107502 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
107503 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107504 // MIs[3] Operand 1
107505 // No operand predicates
107506 GIM_CheckIsSafeToFold, /*NumInsns*/3,
107507 // (vector_insert:{ *:[v2f32] } V64:{ *:[v2f32] }:$src, (vector_extract:{ *:[f32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (EXTRACT_SUBREG:{ *:[v2f32] } (INSvi32lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v2f32] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
107508 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
107509 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
107510 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
107511 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107512 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107513 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
107514 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
107515 GIR_AddImm8, /*InsnID*/3, /*Imm*/2,
107516 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107517 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107518 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107519 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107520 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
107521 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
107522 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
107523 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107524 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107525 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
107526 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107527 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
107528 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
107529 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
107530 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
107531 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107532 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
107533 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107534 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
107535 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
107536 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107537 // GIR_Coverage, 5369,
107538 GIR_EraseRootFromParent_Done,
107539 // Label 6183: @289379
107540 GIM_Try, /*On fail goto*//*Label 6184*/ GIMT_Encode4(289513), // Rule ID 5384 //
107541 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
107542 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
107543 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
107544 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
107545 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
107546 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
107547 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
107548 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
107549 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107550 // MIs[2] Operand 1
107551 // No operand predicates
107552 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
107553 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107554 // MIs[3] Operand 1
107555 // No operand predicates
107556 GIM_CheckIsSafeToFold, /*NumInsns*/3,
107557 // (vector_insert:{ *:[v2i32] } V64:{ *:[v2i32] }:$src, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (EXTRACT_SUBREG:{ *:[v2i32] } (INSvi32lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v2i32] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
107558 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
107559 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
107560 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107561 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107562 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
107563 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
107564 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
107565 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107566 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107567 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
107568 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107569 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
107570 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
107571 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
107572 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
107573 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107574 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
107575 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107576 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
107577 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
107578 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107579 // GIR_Coverage, 5384,
107580 GIR_EraseRootFromParent_Done,
107581 // Label 6184: @289513
107582 GIM_Try, /*On fail goto*//*Label 6185*/ GIMT_Encode4(289678), // Rule ID 5385 //
107583 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
107584 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
107585 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
107586 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
107587 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
107588 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
107589 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
107590 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
107591 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107592 // MIs[2] Operand 1
107593 // No operand predicates
107594 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
107595 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107596 // MIs[3] Operand 1
107597 // No operand predicates
107598 GIM_CheckIsSafeToFold, /*NumInsns*/3,
107599 // (vector_insert:{ *:[v2i32] } V64:{ *:[v2i32] }:$src, (vector_extract:{ *:[i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (EXTRACT_SUBREG:{ *:[v2i32] } (INSvi32lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v2i32] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
107600 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
107601 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
107602 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
107603 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107604 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107605 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
107606 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
107607 GIR_AddImm8, /*InsnID*/3, /*Imm*/2,
107608 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107609 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107610 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107611 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107612 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
107613 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
107614 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
107615 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107616 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107617 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
107618 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107619 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
107620 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
107621 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
107622 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
107623 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107624 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
107625 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107626 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
107627 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
107628 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107629 // GIR_Coverage, 5385,
107630 GIR_EraseRootFromParent_Done,
107631 // Label 6185: @289678
107632 GIM_Try, /*On fail goto*//*Label 6186*/ GIMT_Encode4(289817), // Rule ID 5341 //
107633 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
107634 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
107635 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
107636 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
107637 GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
107638 // MIs[1] Operand 1
107639 // No operand predicates
107640 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
107641 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107642 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
107643 // MIs[2] Operand 1
107644 // No operand predicates
107645 GIM_CheckIsSafeToFold, /*NumInsns*/2,
107646 // (vector_insert:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm) => (EXTRACT_SUBREG:{ *:[v2f32] } (INSvi32gpr:{ *:[f128] } (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, WZR:{ *:[i32] }), dsub:{ *:[i32] })
107647 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
107648 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
107649 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
107650 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
107651 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107652 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
107653 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
107654 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107655 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
107656 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
107657 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
107658 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107659 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107660 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107661 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32gpr),
107662 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107663 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
107664 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // imm
107665 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
107666 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107667 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
107668 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107669 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
107670 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
107671 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107672 // GIR_Coverage, 5341,
107673 GIR_EraseRootFromParent_Done,
107674 // Label 6186: @289817
107675 GIM_Try, /*On fail goto*//*Label 6187*/ GIMT_Encode4(289953), // Rule ID 6048 //
107676 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
107677 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
107678 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
107679 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
107680 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
107681 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
107682 // MIs[1] Rn
107683 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
107684 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
107685 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
107686 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107687 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
107688 // MIs[2] Operand 1
107689 // No operand predicates
107690 GIM_CheckIsSafeToFold, /*NumInsns*/2,
107691 // (vector_insert:{ *:[v2i32] } VecListOne64:{ *:[v2i32] }:$Rd, (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) => (EXTRACT_SUBREG:{ *:[v2i32] } (LD1i32:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
107692 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
107693 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
107694 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107695 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107696 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
107697 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rd
107698 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
107699 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107700 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107701 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i32),
107702 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107703 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
107704 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // idx
107705 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
107706 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
107707 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107708 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
107709 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107710 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
107711 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
107712 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107713 // GIR_Coverage, 6048,
107714 GIR_EraseRootFromParent_Done,
107715 // Label 6187: @289953
107716 GIM_Try, /*On fail goto*//*Label 6188*/ GIMT_Encode4(290089), // Rule ID 6049 //
107717 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
107718 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
107719 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
107720 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
107721 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
107722 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
107723 // MIs[1] Rn
107724 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
107725 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
107726 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
107727 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107728 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
107729 // MIs[2] Operand 1
107730 // No operand predicates
107731 GIM_CheckIsSafeToFold, /*NumInsns*/2,
107732 // (vector_insert:{ *:[v2f32] } VecListOne64:{ *:[v2f32] }:$Rd, (ld:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) => (EXTRACT_SUBREG:{ *:[v2f32] } (LD1i32:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
107733 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
107734 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
107735 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107736 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107737 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
107738 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rd
107739 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
107740 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107741 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107742 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i32),
107743 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107744 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
107745 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // idx
107746 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
107747 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
107748 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107749 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
107750 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107751 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
107752 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
107753 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107754 // GIR_Coverage, 6049,
107755 GIR_EraseRootFromParent_Done,
107756 // Label 6188: @290089
107757 GIM_Try, /*On fail goto*//*Label 6189*/ GIMT_Encode4(290276), // Rule ID 5391 //
107758 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
107759 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
107760 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
107761 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
107762 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
107763 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
107764 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107765 // MIs[2] Operand 1
107766 // No operand predicates
107767 GIM_CheckIsSafeToFold, /*NumInsns*/2,
107768 // (vector_insert:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src, (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Sn), (imm:{ *:[i64] }):$Immd) => (EXTRACT_SUBREG:{ *:[v2i32] } (INSvi32lane:{ *:[f128] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), FPR32:{ *:[f32] }:$Sn, ssub:{ *:[i32] }), 0:{ *:[i64] }), dsub:{ *:[i32] })
107769 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
107770 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
107771 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
107772 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
107773 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s128,
107774 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
107775 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107776 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
107777 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
107778 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107779 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
107780 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, // Sn
107781 GIR_AddImm8, /*InsnID*/4, /*Imm*/15,
107782 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107783 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107784 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
107785 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
107786 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107787 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
107788 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
107789 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107790 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
107791 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
107792 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
107793 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107794 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107795 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107796 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
107797 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107798 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
107799 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immd
107800 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
107801 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
107802 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107803 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
107804 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107805 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
107806 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
107807 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107808 // GIR_Coverage, 5391,
107809 GIR_EraseRootFromParent_Done,
107810 // Label 6189: @290276
107811 GIM_Try, /*On fail goto*//*Label 6190*/ GIMT_Encode4(290458), // Rule ID 5346 //
107812 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
107813 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
107814 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
107815 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
107816 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107817 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
107818 // MIs[1] Operand 1
107819 // No operand predicates
107820 GIM_CheckIsSafeToFold, /*NumInsns*/1,
107821 // (vector_insert:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm) => (EXTRACT_SUBREG:{ *:[v2f32] } (INSvi32lane:{ *:[f128] } (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }), dsub:{ *:[i32] })
107822 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
107823 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
107824 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
107825 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
107826 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
107827 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
107828 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107829 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
107830 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
107831 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107832 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
107833 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
107834 GIR_AddImm8, /*InsnID*/4, /*Imm*/15,
107835 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107836 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107837 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
107838 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
107839 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107840 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
107841 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
107842 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107843 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
107844 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
107845 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
107846 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107847 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107848 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107849 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
107850 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107851 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
107852 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
107853 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
107854 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
107855 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107856 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
107857 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107858 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
107859 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
107860 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107861 // GIR_Coverage, 5346,
107862 GIR_EraseRootFromParent_Done,
107863 // Label 6190: @290458
107864 GIM_Try, /*On fail goto*//*Label 6191*/ GIMT_Encode4(290587), // Rule ID 5349 //
107865 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
107866 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
107867 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
107868 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
107869 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
107870 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
107871 // MIs[1] Operand 1
107872 // No operand predicates
107873 GIM_CheckIsSafeToFold, /*NumInsns*/1,
107874 // (vector_insert:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm) => (EXTRACT_SUBREG:{ *:[v2i32] } (INSvi32gpr:{ *:[f128] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, GPR32:{ *:[i32] }:$Rm), dsub:{ *:[i32] })
107875 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
107876 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
107877 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
107878 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
107879 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107880 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
107881 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
107882 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107883 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
107884 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
107885 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
107886 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107887 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107888 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107889 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32gpr),
107890 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107891 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
107892 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
107893 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
107894 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107895 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
107896 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107897 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
107898 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
107899 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
107900 // GIR_Coverage, 5349,
107901 GIR_EraseRootFromParent_Done,
107902 // Label 6191: @290587
107903 GIM_Reject,
107904 // Label 6177: @290588
107905 GIM_Reject,
107906 // Label 6158: @290589
107907 GIM_Try, /*On fail goto*//*Label 6192*/ GIMT_Encode4(292029),
107908 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
107909 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
107910 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
107911 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
107912 GIM_Try, /*On fail goto*//*Label 6193*/ GIMT_Encode4(290711), // Rule ID 4112 //
107913 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
107914 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
107915 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
107916 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
107917 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
107918 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
107919 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
107920 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
107921 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
107922 GIM_CheckIsSafeToFold, /*NumInsns*/2,
107923 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
107924 // (vector_insert:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, (ld:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
107925 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
107926 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
107927 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107928 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
107929 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
107930 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
107931 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107932 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107933 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107934 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
107935 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
107936 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
107937 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107938 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107939 // GIR_Coverage, 4112,
107940 GIR_EraseRootFromParent_Done,
107941 // Label 6193: @290711
107942 GIM_Try, /*On fail goto*//*Label 6194*/ GIMT_Encode4(290815), // Rule ID 4113 //
107943 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
107944 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
107945 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
107946 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
107947 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
107948 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
107949 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
107950 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
107951 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
107952 GIM_CheckIsSafeToFold, /*NumInsns*/2,
107953 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
107954 // (vector_insert:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, (ld:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
107955 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
107956 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
107957 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107958 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
107959 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
107960 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
107961 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107962 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107963 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107964 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
107965 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
107966 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
107967 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107968 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107969 // GIR_Coverage, 4113,
107970 GIR_EraseRootFromParent_Done,
107971 // Label 6194: @290815
107972 GIM_Try, /*On fail goto*//*Label 6195*/ GIMT_Encode4(290919), // Rule ID 4136 //
107973 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
107974 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
107975 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
107976 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
107977 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
107978 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
107979 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
107980 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
107981 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
107982 GIM_CheckIsSafeToFold, /*NumInsns*/2,
107983 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
107984 // (vector_insert:{ *:[v2f64] } immAllZerosV:{ *:[v2f64] }, (ld:{ *:[f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
107985 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
107986 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
107987 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
107988 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
107989 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
107990 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
107991 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
107992 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
107993 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
107994 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
107995 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
107996 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
107997 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
107998 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
107999 // GIR_Coverage, 4136,
108000 GIR_EraseRootFromParent_Done,
108001 // Label 6195: @290919
108002 GIM_Try, /*On fail goto*//*Label 6196*/ GIMT_Encode4(291023), // Rule ID 4137 //
108003 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
108004 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
108005 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
108006 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
108007 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
108008 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
108009 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
108010 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
108011 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
108012 GIM_CheckIsSafeToFold, /*NumInsns*/2,
108013 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
108014 // (vector_insert:{ *:[v2f64] } immAllZerosV:{ *:[v2f64] }, (ld:{ *:[f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
108015 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
108016 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
108017 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108018 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
108019 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
108020 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
108021 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
108022 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
108023 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108024 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
108025 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
108026 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
108027 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
108028 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
108029 // GIR_Coverage, 4137,
108030 GIR_EraseRootFromParent_Done,
108031 // Label 6196: @291023
108032 GIM_Try, /*On fail goto*//*Label 6197*/ GIMT_Encode4(291101), // Rule ID 1928 //
108033 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
108034 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108035 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108036 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
108037 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
108038 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
108039 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108040 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
108041 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108042 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
108043 // MIs[2] Operand 1
108044 // No operand predicates
108045 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
108046 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108047 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
108048 // MIs[3] Operand 1
108049 // No operand predicates
108050 GIM_CheckIsSafeToFold, /*NumInsns*/3,
108051 // (vector_insert:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx2), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx) => (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (imm:{ *:[i64] }):$idx, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$idx2)
108052 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
108053 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108054 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
108055 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
108056 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
108057 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
108058 GIR_RootConstrainSelectedInstOperands,
108059 // GIR_Coverage, 1928,
108060 GIR_EraseRootFromParent_Done,
108061 // Label 6197: @291101
108062 GIM_Try, /*On fail goto*//*Label 6198*/ GIMT_Encode4(291192), // Rule ID 7084 //
108063 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRCPC3),
108064 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108065 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108066 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
108067 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
108068 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
108069 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
108070 GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(8),
108071 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::Acquire,
108072 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::Unordered,
108073 // MIs[2] Rn
108074 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/64,
108075 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
108076 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
108077 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108078 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
108079 // MIs[3] Operand 1
108080 // No operand predicates
108081 GIM_CheckIsSafeToFold, /*NumInsns*/3,
108082 // (vector_insert:{ *:[v2f64] } VecListOne128:{ *:[v2f64] }:$Rd, (bitconvert:{ *:[f64] } (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_atomic_load_64>><<P:Predicate_anonymous_14569>>), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx) => (LDAP1:{ *:[v2f64] } VecListOne128:{ *:[v2f64] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
108083 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAP1),
108084 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108085 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
108086 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
108087 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
108088 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/4, /*MergeInsnID's*/0, 1, 2, 3,
108089 GIR_RootConstrainSelectedInstOperands,
108090 // GIR_Coverage, 7084,
108091 GIR_EraseRootFromParent_Done,
108092 // Label 6198: @291192
108093 GIM_Try, /*On fail goto*//*Label 6199*/ GIMT_Encode4(291259), // Rule ID 5370 //
108094 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108095 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108096 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
108097 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
108098 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
108099 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108100 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
108101 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108102 // MIs[2] Operand 1
108103 // No operand predicates
108104 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
108105 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108106 // MIs[3] Operand 1
108107 // No operand predicates
108108 GIM_CheckIsSafeToFold, /*NumInsns*/3,
108109 // (vector_insert:{ *:[v2f64] } V128:{ *:[v2f64] }:$src, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (INSvi64lane:{ *:[v2f64] } V128:{ *:[v2f64] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] }):$Immn)
108110 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
108111 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108112 GIR_RootToRootCopy, /*OpIdx*/1, // src
108113 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
108114 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
108115 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
108116 GIR_RootConstrainSelectedInstOperands,
108117 // GIR_Coverage, 5370,
108118 GIR_EraseRootFromParent_Done,
108119 // Label 6199: @291259
108120 GIM_Try, /*On fail goto*//*Label 6200*/ GIMT_Encode4(291357), // Rule ID 5371 //
108121 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108122 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108123 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
108124 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
108125 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
108126 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108127 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
108128 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108129 // MIs[2] Operand 1
108130 // No operand predicates
108131 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
108132 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108133 // MIs[3] Operand 1
108134 // No operand predicates
108135 GIM_CheckIsSafeToFold, /*NumInsns*/3,
108136 // (vector_insert:{ *:[v2f64] } V128:{ *:[v2f64] }:$src, (vector_extract:{ *:[f64] } V64:{ *:[v1f64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (INSvi64lane:{ *:[v2f64] } V128:{ *:[v2f64] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v1f64] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
108137 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
108138 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
108139 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108140 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
108141 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
108142 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
108143 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
108144 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
108145 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
108146 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108147 GIR_RootToRootCopy, /*OpIdx*/1, // src
108148 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
108149 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
108150 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
108151 GIR_RootConstrainSelectedInstOperands,
108152 // GIR_Coverage, 5371,
108153 GIR_EraseRootFromParent_Done,
108154 // Label 6200: @291357
108155 GIM_Try, /*On fail goto*//*Label 6201*/ GIMT_Encode4(291424), // Rule ID 5386 //
108156 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108157 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108158 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
108159 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
108160 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
108161 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108162 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
108163 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108164 // MIs[2] Operand 1
108165 // No operand predicates
108166 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
108167 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108168 // MIs[3] Operand 1
108169 // No operand predicates
108170 GIM_CheckIsSafeToFold, /*NumInsns*/3,
108171 // (vector_insert:{ *:[v2i64] } V128:{ *:[v2i64] }:$src, (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$Immn)
108172 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
108173 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108174 GIR_RootToRootCopy, /*OpIdx*/1, // src
108175 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
108176 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
108177 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
108178 GIR_RootConstrainSelectedInstOperands,
108179 // GIR_Coverage, 5386,
108180 GIR_EraseRootFromParent_Done,
108181 // Label 6201: @291424
108182 GIM_Try, /*On fail goto*//*Label 6202*/ GIMT_Encode4(291522), // Rule ID 5387 //
108183 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108184 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108185 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
108186 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
108187 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
108188 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108189 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
108190 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108191 // MIs[2] Operand 1
108192 // No operand predicates
108193 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
108194 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108195 // MIs[3] Operand 1
108196 // No operand predicates
108197 GIM_CheckIsSafeToFold, /*NumInsns*/3,
108198 // (vector_insert:{ *:[v2i64] } V128:{ *:[v2i64] }:$src, (vector_extract:{ *:[i64] } V64:{ *:[v1i64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
108199 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
108200 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
108201 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108202 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
108203 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
108204 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
108205 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
108206 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
108207 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
108208 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108209 GIR_RootToRootCopy, /*OpIdx*/1, // src
108210 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
108211 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
108212 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
108213 GIR_RootConstrainSelectedInstOperands,
108214 // GIR_Coverage, 5387,
108215 GIR_EraseRootFromParent_Done,
108216 // Label 6202: @291522
108217 GIM_Try, /*On fail goto*//*Label 6203*/ GIMT_Encode4(291600), // Rule ID 7083 //
108218 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRCPC3),
108219 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108220 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108221 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
108222 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(8),
108223 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
108224 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
108225 // MIs[1] Rn
108226 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
108227 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
108228 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
108229 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108230 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
108231 // MIs[2] Operand 1
108232 // No operand predicates
108233 GIM_CheckIsSafeToFold, /*NumInsns*/2,
108234 // (vector_insert:{ *:[v2i64] } VecListOne128:{ *:[v2i64] }:$Rd, (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_atomic_load_64>><<P:Predicate_anonymous_14569>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx) => (LDAP1:{ *:[v2i64] } VecListOne128:{ *:[v2i64] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
108235 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAP1),
108236 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108237 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
108238 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
108239 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
108240 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
108241 GIR_RootConstrainSelectedInstOperands,
108242 // GIR_Coverage, 7083,
108243 GIR_EraseRootFromParent_Done,
108244 // Label 6203: @291600
108245 GIM_Try, /*On fail goto*//*Label 6204*/ GIMT_Encode4(291669), // Rule ID 6033 //
108246 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108247 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108248 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
108249 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
108250 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
108251 // MIs[1] Rn
108252 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
108253 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
108254 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
108255 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108256 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
108257 // MIs[2] Operand 1
108258 // No operand predicates
108259 GIM_CheckIsSafeToFold, /*NumInsns*/2,
108260 // (vector_insert:{ *:[v2i64] } VecListOne128:{ *:[v2i64] }:$Rd, (ld:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx) => (LD1i64:{ *:[v2i64] } VecListOne128:{ *:[v2i64] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
108261 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i64),
108262 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108263 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
108264 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
108265 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
108266 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
108267 GIR_RootConstrainSelectedInstOperands,
108268 // GIR_Coverage, 6033,
108269 GIR_EraseRootFromParent_Done,
108270 // Label 6204: @291669
108271 GIM_Try, /*On fail goto*//*Label 6205*/ GIMT_Encode4(291738), // Rule ID 6034 //
108272 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108273 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108274 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
108275 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
108276 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
108277 // MIs[1] Rn
108278 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
108279 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
108280 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
108281 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108282 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
108283 // MIs[2] Operand 1
108284 // No operand predicates
108285 GIM_CheckIsSafeToFold, /*NumInsns*/2,
108286 // (vector_insert:{ *:[v2f64] } VecListOne128:{ *:[v2f64] }:$Rd, (ld:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx) => (LD1i64:{ *:[v2f64] } VecListOne128:{ *:[v2f64] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
108287 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i64),
108288 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108289 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
108290 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
108291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
108292 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
108293 GIR_RootConstrainSelectedInstOperands,
108294 // GIR_Coverage, 6034,
108295 GIR_EraseRootFromParent_Done,
108296 // Label 6205: @291738
108297 GIM_Try, /*On fail goto*//*Label 6206*/ GIMT_Encode4(291787), // Rule ID 5342 //
108298 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108299 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
108300 GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
108301 // MIs[1] Operand 1
108302 // No operand predicates
108303 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
108304 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108305 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
108306 // MIs[2] Operand 1
108307 // No operand predicates
108308 GIM_CheckIsSafeToFold, /*NumInsns*/2,
108309 // (vector_insert:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$Rn, (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$imm) => (INSvi64gpr:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, XZR:{ *:[i64] })
108310 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64gpr),
108311 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108312 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
108313 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
108314 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
108315 GIR_RootConstrainSelectedInstOperands,
108316 // GIR_Coverage, 5342,
108317 GIR_EraseRootFromParent_Done,
108318 // Label 6206: @291787
108319 GIM_Try, /*On fail goto*//*Label 6207*/ GIMT_Encode4(291888), // Rule ID 5392 //
108320 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108321 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
108322 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
108323 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108324 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
108325 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108326 // MIs[2] Operand 1
108327 // No operand predicates
108328 GIM_CheckIsSafeToFold, /*NumInsns*/2,
108329 // (vector_insert:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$src, (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$Sn), (imm:{ *:[i64] }):$Immd) => (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$src, (imm:{ *:[i64] }):$Immd, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), FPR64:{ *:[f64] }:$Sn, dsub:{ *:[i32] }), 0:{ *:[i64] })
108330 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
108331 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
108332 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
108333 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108334 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
108335 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
108336 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108337 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
108338 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Sn
108339 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
108340 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
108341 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
108342 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
108343 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
108344 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108345 GIR_RootToRootCopy, /*OpIdx*/1, // src
108346 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immd
108347 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
108348 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
108349 GIR_RootConstrainSelectedInstOperands,
108350 // GIR_Coverage, 5392,
108351 GIR_EraseRootFromParent_Done,
108352 // Label 6207: @291888
108353 GIM_Try, /*On fail goto*//*Label 6208*/ GIMT_Encode4(291932), // Rule ID 1924 //
108354 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
108355 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108356 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
108357 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
108358 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108359 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
108360 // MIs[1] Operand 1
108361 // No operand predicates
108362 GIM_CheckIsSafeToFold, /*NumInsns*/1,
108363 // (vector_insert:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx) => (INSvi64gpr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (imm:{ *:[i64] }):$idx, GPR64:{ *:[i64] }:$Rn)
108364 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64gpr),
108365 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108366 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
108367 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
108368 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
108369 GIR_RootConstrainSelectedInstOperands,
108370 // GIR_Coverage, 1924,
108371 GIR_EraseRootFromParent_Done,
108372 // Label 6208: @291932
108373 GIM_Try, /*On fail goto*//*Label 6209*/ GIMT_Encode4(292028), // Rule ID 5348 //
108374 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108375 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108376 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
108377 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108378 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
108379 // MIs[1] Operand 1
108380 // No operand predicates
108381 GIM_CheckIsSafeToFold, /*NumInsns*/1,
108382 // (vector_insert:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$imm) => (INSvi64lane:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$imm, (INSERT_SUBREG:{ *:[v2f64] } (IMPLICIT_DEF:{ *:[v2f64] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
108383 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
108384 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
108385 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
108386 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108387 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
108388 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
108389 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108390 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
108391 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
108392 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
108393 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
108394 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
108395 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
108396 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
108397 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108398 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
108399 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
108400 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
108401 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
108402 GIR_RootConstrainSelectedInstOperands,
108403 // GIR_Coverage, 5348,
108404 GIR_EraseRootFromParent_Done,
108405 // Label 6209: @292028
108406 GIM_Reject,
108407 // Label 6192: @292029
108408 GIM_Reject,
108409 // Label 6159: @292030
108410 GIM_Try, /*On fail goto*//*Label 6210*/ GIMT_Encode4(294759),
108411 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
108412 GIM_Try, /*On fail goto*//*Label 6211*/ GIMT_Encode4(292152), // Rule ID 4120 //
108413 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
108414 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
108415 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108416 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
108417 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
108418 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
108419 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
108420 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
108421 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
108422 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
108423 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
108424 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
108425 GIM_CheckIsSafeToFold, /*NumInsns*/2,
108426 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
108427 // (vector_insert:{ *:[v4f16] } immAllZerosV:{ *:[v4f16] }, (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v4f16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
108428 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
108429 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
108430 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108431 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
108432 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
108433 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
108434 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
108435 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
108436 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108437 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
108438 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
108439 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
108440 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
108441 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
108442 // GIR_Coverage, 4120,
108443 GIR_EraseRootFromParent_Done,
108444 // Label 6211: @292152
108445 GIM_Try, /*On fail goto*//*Label 6212*/ GIMT_Encode4(292266), // Rule ID 4121 //
108446 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
108447 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
108448 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108449 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
108450 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
108451 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
108452 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
108453 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
108454 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
108455 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
108456 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
108457 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
108458 GIM_CheckIsSafeToFold, /*NumInsns*/2,
108459 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
108460 // (vector_insert:{ *:[v4f16] } immAllZerosV:{ *:[v4f16] }, (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v4f16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
108461 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
108462 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
108463 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108464 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
108465 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
108466 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
108467 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
108468 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
108469 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108470 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
108471 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
108472 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
108473 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
108474 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
108475 // GIR_Coverage, 4121,
108476 GIR_EraseRootFromParent_Done,
108477 // Label 6212: @292266
108478 GIM_Try, /*On fail goto*//*Label 6213*/ GIMT_Encode4(292380), // Rule ID 4126 //
108479 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
108480 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
108481 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108482 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
108483 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
108484 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
108485 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
108486 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
108487 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
108488 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
108489 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
108490 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
108491 GIM_CheckIsSafeToFold, /*NumInsns*/2,
108492 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
108493 // (vector_insert:{ *:[v4bf16] } immAllZerosV:{ *:[v4bf16] }, (ld:{ *:[bf16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v4bf16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
108494 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
108495 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
108496 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108497 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
108498 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
108499 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
108500 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
108501 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
108502 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108503 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
108504 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
108505 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
108506 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
108507 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
108508 // GIR_Coverage, 4126,
108509 GIR_EraseRootFromParent_Done,
108510 // Label 6213: @292380
108511 GIM_Try, /*On fail goto*//*Label 6214*/ GIMT_Encode4(292494), // Rule ID 4127 //
108512 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
108513 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
108514 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108515 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
108516 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
108517 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
108518 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
108519 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
108520 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
108521 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
108522 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
108523 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
108524 GIM_CheckIsSafeToFold, /*NumInsns*/2,
108525 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
108526 // (vector_insert:{ *:[v4bf16] } immAllZerosV:{ *:[v4bf16] }, (ld:{ *:[bf16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v4bf16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
108527 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
108528 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
108529 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108530 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
108531 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
108532 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
108533 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
108534 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
108535 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108536 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
108537 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
108538 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
108539 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
108540 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
108541 // GIR_Coverage, 4127,
108542 GIR_EraseRootFromParent_Done,
108543 // Label 6214: @292494
108544 GIM_Try, /*On fail goto*//*Label 6215*/ GIMT_Encode4(292615), // Rule ID 4102 //
108545 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
108546 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
108547 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108548 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
108549 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
108550 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
108551 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
108552 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
108553 GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
108554 GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
108555 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
108556 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
108557 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
108558 GIM_CheckIsSafeToFold, /*NumInsns*/2,
108559 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
108560 // (vector_insert:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
108561 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
108562 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
108563 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108564 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
108565 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
108566 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
108567 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
108568 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
108569 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108570 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
108571 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
108572 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
108573 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
108574 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
108575 // GIR_Coverage, 4102,
108576 GIR_EraseRootFromParent_Done,
108577 // Label 6215: @292615
108578 GIM_Try, /*On fail goto*//*Label 6216*/ GIMT_Encode4(292736), // Rule ID 4103 //
108579 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
108580 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
108581 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108582 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
108583 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
108584 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
108585 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
108586 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
108587 GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
108588 GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
108589 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
108590 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
108591 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
108592 GIM_CheckIsSafeToFold, /*NumInsns*/2,
108593 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
108594 // (vector_insert:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
108595 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
108596 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
108597 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108598 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
108599 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
108600 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
108601 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
108602 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
108603 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108604 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
108605 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
108606 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
108607 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
108608 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
108609 // GIR_Coverage, 4103,
108610 GIR_EraseRootFromParent_Done,
108611 // Label 6216: @292736
108612 GIM_Try, /*On fail goto*//*Label 6217*/ GIMT_Encode4(292876), // Rule ID 5360 //
108613 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
108614 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
108615 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108616 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108617 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108618 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
108619 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
108620 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
108621 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108622 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
108623 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108624 // MIs[2] Operand 1
108625 // No operand predicates
108626 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
108627 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108628 // MIs[3] Operand 1
108629 // No operand predicates
108630 GIM_CheckIsSafeToFold, /*NumInsns*/3,
108631 // (vector_insert:{ *:[v4f16] } V64:{ *:[v4f16] }:$src, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (EXTRACT_SUBREG:{ *:[v4f16] } (INSvi16lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4f16] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
108632 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
108633 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
108634 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
108635 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108636 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
108637 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
108638 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
108639 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
108640 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
108641 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
108642 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108643 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
108644 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
108645 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
108646 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
108647 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
108648 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
108649 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108650 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
108651 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
108652 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
108653 // GIR_Coverage, 5360,
108654 GIR_EraseRootFromParent_Done,
108655 // Label 6217: @292876
108656 GIM_Try, /*On fail goto*//*Label 6218*/ GIMT_Encode4(293047), // Rule ID 5361 //
108657 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
108658 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
108659 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108660 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108661 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108662 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
108663 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
108664 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
108665 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108666 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
108667 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108668 // MIs[2] Operand 1
108669 // No operand predicates
108670 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
108671 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108672 // MIs[3] Operand 1
108673 // No operand predicates
108674 GIM_CheckIsSafeToFold, /*NumInsns*/3,
108675 // (vector_insert:{ *:[v4f16] } V64:{ *:[v4f16] }:$src, (vector_extract:{ *:[f16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (EXTRACT_SUBREG:{ *:[v4f16] } (INSvi16lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4f16] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
108676 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
108677 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
108678 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
108679 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
108680 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108681 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
108682 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
108683 GIR_AddImm8, /*InsnID*/3, /*Imm*/2,
108684 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
108685 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
108686 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
108687 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108688 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
108689 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
108690 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
108691 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
108692 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
108693 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
108694 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108695 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
108696 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
108697 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
108698 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
108699 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
108700 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
108701 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108702 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
108703 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
108704 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
108705 // GIR_Coverage, 5361,
108706 GIR_EraseRootFromParent_Done,
108707 // Label 6218: @293047
108708 GIM_Try, /*On fail goto*//*Label 6219*/ GIMT_Encode4(293187), // Rule ID 5364 //
108709 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
108710 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
108711 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108712 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108713 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108714 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
108715 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
108716 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
108717 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108718 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
108719 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108720 // MIs[2] Operand 1
108721 // No operand predicates
108722 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
108723 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108724 // MIs[3] Operand 1
108725 // No operand predicates
108726 GIM_CheckIsSafeToFold, /*NumInsns*/3,
108727 // (vector_insert:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$src, (vector_extract:{ *:[bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (EXTRACT_SUBREG:{ *:[v4bf16] } (INSvi16lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4bf16] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
108728 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
108729 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
108730 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
108731 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108732 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
108733 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
108734 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
108735 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
108736 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
108737 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
108738 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108739 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
108740 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
108741 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
108742 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
108743 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
108744 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
108745 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108746 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
108747 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
108748 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
108749 // GIR_Coverage, 5364,
108750 GIR_EraseRootFromParent_Done,
108751 // Label 6219: @293187
108752 GIM_Try, /*On fail goto*//*Label 6220*/ GIMT_Encode4(293358), // Rule ID 5365 //
108753 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
108754 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
108755 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108756 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108757 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108758 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
108759 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
108760 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
108761 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108762 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
108763 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108764 // MIs[2] Operand 1
108765 // No operand predicates
108766 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
108767 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108768 // MIs[3] Operand 1
108769 // No operand predicates
108770 GIM_CheckIsSafeToFold, /*NumInsns*/3,
108771 // (vector_insert:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$src, (vector_extract:{ *:[bf16] } V64:{ *:[v4bf16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (EXTRACT_SUBREG:{ *:[v4bf16] } (INSvi16lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4bf16] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4bf16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
108772 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
108773 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
108774 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
108775 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
108776 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108777 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
108778 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
108779 GIR_AddImm8, /*InsnID*/3, /*Imm*/2,
108780 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
108781 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
108782 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
108783 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108784 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
108785 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
108786 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
108787 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
108788 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
108789 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
108790 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108791 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
108792 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
108793 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
108794 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
108795 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
108796 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
108797 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108798 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
108799 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
108800 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
108801 // GIR_Coverage, 5365,
108802 GIR_EraseRootFromParent_Done,
108803 // Label 6220: @293358
108804 GIM_Try, /*On fail goto*//*Label 6221*/ GIMT_Encode4(293498), // Rule ID 5380 //
108805 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
108806 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
108807 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108808 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108809 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108810 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
108811 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
108812 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
108813 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108814 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
108815 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108816 // MIs[2] Operand 1
108817 // No operand predicates
108818 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
108819 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108820 // MIs[3] Operand 1
108821 // No operand predicates
108822 GIM_CheckIsSafeToFold, /*NumInsns*/3,
108823 // (vector_insert:{ *:[v4i16] } V64:{ *:[v4i16] }:$src, (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (EXTRACT_SUBREG:{ *:[v4i16] } (INSvi16lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4i16] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
108824 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
108825 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
108826 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
108827 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108828 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
108829 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
108830 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
108831 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
108832 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
108833 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
108834 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108835 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
108836 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
108837 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
108838 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
108839 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
108840 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
108841 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108842 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
108843 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
108844 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
108845 // GIR_Coverage, 5380,
108846 GIR_EraseRootFromParent_Done,
108847 // Label 6221: @293498
108848 GIM_Try, /*On fail goto*//*Label 6222*/ GIMT_Encode4(293669), // Rule ID 5381 //
108849 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
108850 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
108851 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108852 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108853 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108854 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
108855 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
108856 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
108857 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108858 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
108859 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108860 // MIs[2] Operand 1
108861 // No operand predicates
108862 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
108863 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108864 // MIs[3] Operand 1
108865 // No operand predicates
108866 GIM_CheckIsSafeToFold, /*NumInsns*/3,
108867 // (vector_insert:{ *:[v4i16] } V64:{ *:[v4i16] }:$src, (vector_extract:{ *:[i32] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (EXTRACT_SUBREG:{ *:[v4i16] } (INSvi16lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4i16] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
108868 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
108869 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
108870 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
108871 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
108872 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108873 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
108874 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
108875 GIR_AddImm8, /*InsnID*/3, /*Imm*/2,
108876 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
108877 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
108878 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
108879 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108880 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
108881 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
108882 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
108883 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
108884 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
108885 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
108886 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108887 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
108888 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
108889 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
108890 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
108891 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
108892 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
108893 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108894 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
108895 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
108896 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
108897 // GIR_Coverage, 5381,
108898 GIR_EraseRootFromParent_Done,
108899 // Label 6222: @293669
108900 GIM_Try, /*On fail goto*//*Label 6223*/ GIMT_Encode4(293814), // Rule ID 5339 //
108901 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
108902 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
108903 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108904 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108905 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108906 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
108907 GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
108908 // MIs[1] Operand 1
108909 // No operand predicates
108910 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
108911 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108912 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
108913 // MIs[2] Operand 1
108914 // No operand predicates
108915 GIM_CheckIsSafeToFold, /*NumInsns*/2,
108916 // (vector_insert:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm) => (EXTRACT_SUBREG:{ *:[v4f16] } (INSvi16gpr:{ *:[f128] } (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm, WZR:{ *:[i32] }), dsub:{ *:[i32] })
108917 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
108918 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
108919 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
108920 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
108921 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108922 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
108923 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
108924 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108925 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
108926 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
108927 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
108928 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
108929 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
108930 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
108931 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16gpr),
108932 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108933 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
108934 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // imm
108935 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
108936 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
108937 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
108938 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108939 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
108940 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
108941 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
108942 // GIR_Coverage, 5339,
108943 GIR_EraseRootFromParent_Done,
108944 // Label 6223: @293814
108945 GIM_Try, /*On fail goto*//*Label 6224*/ GIMT_Encode4(293956), // Rule ID 6050 //
108946 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
108947 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
108948 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108949 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108950 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108951 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
108952 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
108953 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
108954 // MIs[1] Rn
108955 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
108956 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
108957 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
108958 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
108959 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
108960 // MIs[2] Operand 1
108961 // No operand predicates
108962 GIM_CheckIsSafeToFold, /*NumInsns*/2,
108963 // (vector_insert:{ *:[v4f16] } VecListOne64:{ *:[v4f16] }:$Rd, (ld:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) => (EXTRACT_SUBREG:{ *:[v4f16] } (LD1i16:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4f16] }:$Rd, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
108964 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
108965 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
108966 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
108967 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108968 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
108969 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rd
108970 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
108971 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
108972 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
108973 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i16),
108974 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
108975 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
108976 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // idx
108977 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
108978 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
108979 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
108980 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
108981 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
108982 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
108983 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
108984 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
108985 // GIR_Coverage, 6050,
108986 GIR_EraseRootFromParent_Done,
108987 // Label 6224: @293956
108988 GIM_Try, /*On fail goto*//*Label 6225*/ GIMT_Encode4(294098), // Rule ID 6051 //
108989 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
108990 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
108991 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
108992 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
108993 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
108994 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
108995 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
108996 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
108997 // MIs[1] Rn
108998 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
108999 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
109000 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
109001 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109002 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
109003 // MIs[2] Operand 1
109004 // No operand predicates
109005 GIM_CheckIsSafeToFold, /*NumInsns*/2,
109006 // (vector_insert:{ *:[v4bf16] } VecListOne64:{ *:[v4bf16] }:$Rd, (ld:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) => (EXTRACT_SUBREG:{ *:[v4bf16] } (LD1i16:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4bf16] }:$Rd, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
109007 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
109008 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
109009 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
109010 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109011 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
109012 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rd
109013 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
109014 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109015 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
109016 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i16),
109017 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109018 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
109019 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // idx
109020 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
109021 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
109022 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
109023 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
109024 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109025 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
109026 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
109027 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109028 // GIR_Coverage, 6051,
109029 GIR_EraseRootFromParent_Done,
109030 // Label 6225: @294098
109031 GIM_Try, /*On fail goto*//*Label 6226*/ GIMT_Encode4(294247), // Rule ID 6047 //
109032 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
109033 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
109034 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109035 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
109036 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
109037 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
109038 GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
109039 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
109040 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
109041 // MIs[1] Rn
109042 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
109043 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
109044 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
109045 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109046 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
109047 // MIs[2] Operand 1
109048 // No operand predicates
109049 GIM_CheckIsSafeToFold, /*NumInsns*/2,
109050 // (vector_insert:{ *:[v4i16] } VecListOne64:{ *:[v4i16] }:$Rd, (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) => (EXTRACT_SUBREG:{ *:[v4i16] } (LD1i16:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
109051 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
109052 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
109053 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
109054 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109055 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
109056 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rd
109057 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
109058 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109059 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
109060 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i16),
109061 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109062 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
109063 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // idx
109064 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
109065 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
109066 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
109067 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
109068 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109069 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
109070 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
109071 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109072 // GIR_Coverage, 6047,
109073 GIR_EraseRootFromParent_Done,
109074 // Label 6226: @294247
109075 GIM_Try, /*On fail goto*//*Label 6227*/ GIMT_Encode4(294435), // Rule ID 5337 //
109076 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
109077 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
109078 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109079 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
109080 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
109081 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
109082 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109083 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
109084 // MIs[1] Operand 1
109085 // No operand predicates
109086 GIM_CheckIsSafeToFold, /*NumInsns*/1,
109087 // (vector_insert:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm) => (EXTRACT_SUBREG:{ *:[v4f16] } (INSvi16lane:{ *:[f128] } (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), FPR16:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }), dsub:{ *:[i32] })
109088 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
109089 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
109090 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
109091 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s16,
109092 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s16,
109093 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
109094 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109095 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
109096 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
109097 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109098 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
109099 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
109100 GIR_AddImm8, /*InsnID*/4, /*Imm*/7,
109101 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109102 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109103 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
109104 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
109105 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109106 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
109107 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
109108 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109109 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
109110 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
109111 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
109112 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109113 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109114 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
109115 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
109116 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109117 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
109118 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
109119 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
109120 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
109121 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
109122 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
109123 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109124 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
109125 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
109126 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109127 // GIR_Coverage, 5337,
109128 GIR_EraseRootFromParent_Done,
109129 // Label 6227: @294435
109130 GIM_Try, /*On fail goto*//*Label 6228*/ GIMT_Encode4(294623), // Rule ID 5344 //
109131 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
109132 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
109133 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109134 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
109135 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
109136 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
109137 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109138 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
109139 // MIs[1] Operand 1
109140 // No operand predicates
109141 GIM_CheckIsSafeToFold, /*NumInsns*/1,
109142 // (vector_insert:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, FPR16:{ *:[bf16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm) => (EXTRACT_SUBREG:{ *:[v4bf16] } (INSvi16lane:{ *:[f128] } (INSERT_SUBREG:{ *:[v8bf16] } (IMPLICIT_DEF:{ *:[v8bf16] }), V64:{ *:[v4bf16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, (INSERT_SUBREG:{ *:[v8bf16] } (IMPLICIT_DEF:{ *:[v8bf16] }), FPR16:{ *:[bf16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }), dsub:{ *:[i32] })
109143 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
109144 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
109145 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
109146 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s16,
109147 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s16,
109148 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
109149 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109150 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
109151 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
109152 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109153 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
109154 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
109155 GIR_AddImm8, /*InsnID*/4, /*Imm*/7,
109156 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109157 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109158 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
109159 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
109160 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109161 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
109162 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
109163 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109164 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
109165 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
109166 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
109167 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109168 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109169 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
109170 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
109171 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109172 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
109173 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
109174 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
109175 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
109176 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
109177 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
109178 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109179 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
109180 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
109181 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109182 // GIR_Coverage, 5344,
109183 GIR_EraseRootFromParent_Done,
109184 // Label 6228: @294623
109185 GIM_Try, /*On fail goto*//*Label 6229*/ GIMT_Encode4(294758), // Rule ID 5350 //
109186 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
109187 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
109188 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109189 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
109190 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
109191 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
109192 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109193 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
109194 // MIs[1] Operand 1
109195 // No operand predicates
109196 GIM_CheckIsSafeToFold, /*NumInsns*/1,
109197 // (vector_insert:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, GPR32:{ *:[i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm) => (EXTRACT_SUBREG:{ *:[v4i16] } (INSvi16gpr:{ *:[f128] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm, GPR32:{ *:[i32] }:$Rm), dsub:{ *:[i32] })
109198 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
109199 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
109200 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
109201 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
109202 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109203 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
109204 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
109205 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109206 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
109207 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
109208 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
109209 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109210 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109211 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
109212 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16gpr),
109213 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109214 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
109215 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
109216 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
109217 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
109218 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
109219 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109220 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
109221 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
109222 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109223 // GIR_Coverage, 5350,
109224 GIR_EraseRootFromParent_Done,
109225 // Label 6229: @294758
109226 GIM_Reject,
109227 // Label 6210: @294759
109228 GIM_Reject,
109229 // Label 6160: @294760
109230 GIM_Try, /*On fail goto*//*Label 6230*/ GIMT_Encode4(296035),
109231 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
109232 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
109233 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
109234 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109235 GIM_Try, /*On fail goto*//*Label 6231*/ GIMT_Encode4(294882), // Rule ID 4106 //
109236 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
109237 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
109238 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
109239 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
109240 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
109241 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
109242 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
109243 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
109244 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
109245 GIM_CheckIsSafeToFold, /*NumInsns*/2,
109246 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
109247 // (vector_insert:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
109248 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
109249 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
109250 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109251 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
109252 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
109253 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
109254 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
109255 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
109256 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109257 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
109258 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
109259 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
109260 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109261 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
109262 // GIR_Coverage, 4106,
109263 GIR_EraseRootFromParent_Done,
109264 // Label 6231: @294882
109265 GIM_Try, /*On fail goto*//*Label 6232*/ GIMT_Encode4(294986), // Rule ID 4107 //
109266 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
109267 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
109268 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
109269 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
109270 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
109271 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
109272 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
109273 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
109274 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
109275 GIM_CheckIsSafeToFold, /*NumInsns*/2,
109276 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
109277 // (vector_insert:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
109278 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
109279 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
109280 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109281 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
109282 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
109283 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
109284 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
109285 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
109286 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109287 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
109288 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
109289 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
109290 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109291 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
109292 // GIR_Coverage, 4107,
109293 GIR_EraseRootFromParent_Done,
109294 // Label 6232: @294986
109295 GIM_Try, /*On fail goto*//*Label 6233*/ GIMT_Encode4(295090), // Rule ID 4130 //
109296 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
109297 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
109298 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
109299 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
109300 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
109301 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
109302 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
109303 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
109304 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
109305 GIM_CheckIsSafeToFold, /*NumInsns*/2,
109306 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
109307 // (vector_insert:{ *:[v4f32] } immAllZerosV:{ *:[v4f32] }, (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
109308 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
109309 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
109310 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109311 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
109312 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
109313 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
109314 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
109315 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
109316 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109317 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
109318 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
109319 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
109320 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109321 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
109322 // GIR_Coverage, 4130,
109323 GIR_EraseRootFromParent_Done,
109324 // Label 6233: @295090
109325 GIM_Try, /*On fail goto*//*Label 6234*/ GIMT_Encode4(295194), // Rule ID 4131 //
109326 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
109327 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
109328 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
109329 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
109330 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
109331 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
109332 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
109333 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
109334 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
109335 GIM_CheckIsSafeToFold, /*NumInsns*/2,
109336 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
109337 // (vector_insert:{ *:[v4f32] } immAllZerosV:{ *:[v4f32] }, (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
109338 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
109339 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
109340 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109341 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
109342 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
109343 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
109344 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
109345 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
109346 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109347 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
109348 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
109349 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
109350 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109351 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
109352 // GIR_Coverage, 4131,
109353 GIR_EraseRootFromParent_Done,
109354 // Label 6234: @295194
109355 GIM_Try, /*On fail goto*//*Label 6235*/ GIMT_Encode4(295272), // Rule ID 1927 //
109356 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
109357 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109358 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
109359 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
109360 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
109361 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
109362 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109363 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
109364 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109365 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
109366 // MIs[2] Operand 1
109367 // No operand predicates
109368 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
109369 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109370 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
109371 // MIs[3] Operand 1
109372 // No operand predicates
109373 GIM_CheckIsSafeToFold, /*NumInsns*/3,
109374 // (vector_insert:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx2), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) => (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (imm:{ *:[i64] }):$idx, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx2)
109375 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
109376 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109377 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
109378 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
109379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
109380 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
109381 GIR_RootConstrainSelectedInstOperands,
109382 // GIR_Coverage, 1927,
109383 GIR_EraseRootFromParent_Done,
109384 // Label 6235: @295272
109385 GIM_Try, /*On fail goto*//*Label 6236*/ GIMT_Encode4(295339), // Rule ID 5366 //
109386 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109387 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
109388 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
109389 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
109390 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
109391 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109392 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
109393 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109394 // MIs[2] Operand 1
109395 // No operand predicates
109396 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
109397 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109398 // MIs[3] Operand 1
109399 // No operand predicates
109400 GIM_CheckIsSafeToFold, /*NumInsns*/3,
109401 // (vector_insert:{ *:[v4f32] } V128:{ *:[v4f32] }:$src, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (INSvi32lane:{ *:[v4f32] } V128:{ *:[v4f32] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] }):$Immn)
109402 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
109403 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109404 GIR_RootToRootCopy, /*OpIdx*/1, // src
109405 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
109406 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
109407 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
109408 GIR_RootConstrainSelectedInstOperands,
109409 // GIR_Coverage, 5366,
109410 GIR_EraseRootFromParent_Done,
109411 // Label 6236: @295339
109412 GIM_Try, /*On fail goto*//*Label 6237*/ GIMT_Encode4(295437), // Rule ID 5367 //
109413 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109414 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
109415 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
109416 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
109417 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
109418 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
109419 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
109420 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109421 // MIs[2] Operand 1
109422 // No operand predicates
109423 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
109424 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109425 // MIs[3] Operand 1
109426 // No operand predicates
109427 GIM_CheckIsSafeToFold, /*NumInsns*/3,
109428 // (vector_insert:{ *:[v4f32] } V128:{ *:[v4f32] }:$src, (vector_extract:{ *:[f32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (INSvi32lane:{ *:[v4f32] } V128:{ *:[v4f32] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
109429 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
109430 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
109431 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109432 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
109433 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
109434 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
109435 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109436 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
109437 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
109438 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109439 GIR_RootToRootCopy, /*OpIdx*/1, // src
109440 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
109441 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
109442 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
109443 GIR_RootConstrainSelectedInstOperands,
109444 // GIR_Coverage, 5367,
109445 GIR_EraseRootFromParent_Done,
109446 // Label 6237: @295437
109447 GIM_Try, /*On fail goto*//*Label 6238*/ GIMT_Encode4(295504), // Rule ID 5382 //
109448 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109449 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
109450 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
109451 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
109452 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
109453 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109454 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
109455 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109456 // MIs[2] Operand 1
109457 // No operand predicates
109458 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
109459 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109460 // MIs[3] Operand 1
109461 // No operand predicates
109462 GIM_CheckIsSafeToFold, /*NumInsns*/3,
109463 // (vector_insert:{ *:[v4i32] } V128:{ *:[v4i32] }:$src, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$Immn)
109464 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
109465 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109466 GIR_RootToRootCopy, /*OpIdx*/1, // src
109467 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
109468 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
109469 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
109470 GIR_RootConstrainSelectedInstOperands,
109471 // GIR_Coverage, 5382,
109472 GIR_EraseRootFromParent_Done,
109473 // Label 6238: @295504
109474 GIM_Try, /*On fail goto*//*Label 6239*/ GIMT_Encode4(295602), // Rule ID 5383 //
109475 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109476 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
109477 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
109478 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
109479 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
109480 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
109481 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
109482 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109483 // MIs[2] Operand 1
109484 // No operand predicates
109485 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
109486 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109487 // MIs[3] Operand 1
109488 // No operand predicates
109489 GIM_CheckIsSafeToFold, /*NumInsns*/3,
109490 // (vector_insert:{ *:[v4i32] } V128:{ *:[v4i32] }:$src, (vector_extract:{ *:[i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
109491 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
109492 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
109493 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109494 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
109495 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
109496 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
109497 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109498 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
109499 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
109500 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109501 GIR_RootToRootCopy, /*OpIdx*/1, // src
109502 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
109503 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
109504 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
109505 GIR_RootConstrainSelectedInstOperands,
109506 // GIR_Coverage, 5383,
109507 GIR_EraseRootFromParent_Done,
109508 // Label 6239: @295602
109509 GIM_Try, /*On fail goto*//*Label 6240*/ GIMT_Encode4(295655), // Rule ID 5340 //
109510 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109511 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
109512 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
109513 GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
109514 // MIs[1] Operand 1
109515 // No operand predicates
109516 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
109517 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109518 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
109519 // MIs[2] Operand 1
109520 // No operand predicates
109521 GIM_CheckIsSafeToFold, /*NumInsns*/2,
109522 // (vector_insert:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm) => (INSvi32gpr:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, WZR:{ *:[i32] })
109523 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32gpr),
109524 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109525 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
109526 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
109527 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
109528 GIR_RootConstrainSelectedInstOperands,
109529 // GIR_Coverage, 5340,
109530 GIR_EraseRootFromParent_Done,
109531 // Label 6240: @295655
109532 GIM_Try, /*On fail goto*//*Label 6241*/ GIMT_Encode4(295724), // Rule ID 6031 //
109533 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109534 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
109535 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
109536 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
109537 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
109538 // MIs[1] Rn
109539 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
109540 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
109541 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
109542 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109543 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
109544 // MIs[2] Operand 1
109545 // No operand predicates
109546 GIM_CheckIsSafeToFold, /*NumInsns*/2,
109547 // (vector_insert:{ *:[v4i32] } VecListOne128:{ *:[v4i32] }:$Rd, (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) => (LD1i32:{ *:[v4i32] } VecListOne128:{ *:[v4i32] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
109548 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i32),
109549 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109550 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
109551 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
109552 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
109553 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
109554 GIR_RootConstrainSelectedInstOperands,
109555 // GIR_Coverage, 6031,
109556 GIR_EraseRootFromParent_Done,
109557 // Label 6241: @295724
109558 GIM_Try, /*On fail goto*//*Label 6242*/ GIMT_Encode4(295793), // Rule ID 6032 //
109559 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109560 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
109561 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
109562 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
109563 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
109564 // MIs[1] Rn
109565 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
109566 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
109567 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
109568 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109569 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
109570 // MIs[2] Operand 1
109571 // No operand predicates
109572 GIM_CheckIsSafeToFold, /*NumInsns*/2,
109573 // (vector_insert:{ *:[v4f32] } VecListOne128:{ *:[v4f32] }:$Rd, (ld:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) => (LD1i32:{ *:[v4f32] } VecListOne128:{ *:[v4f32] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
109574 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i32),
109575 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109576 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
109577 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
109578 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
109579 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
109580 GIR_RootConstrainSelectedInstOperands,
109581 // GIR_Coverage, 6032,
109582 GIR_EraseRootFromParent_Done,
109583 // Label 6242: @295793
109584 GIM_Try, /*On fail goto*//*Label 6243*/ GIMT_Encode4(295894), // Rule ID 5390 //
109585 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
109586 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
109587 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
109588 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
109589 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
109590 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109591 // MIs[2] Operand 1
109592 // No operand predicates
109593 GIM_CheckIsSafeToFold, /*NumInsns*/2,
109594 // (vector_insert:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Sn), (imm:{ *:[i64] }):$Immd) => (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$src, (imm:{ *:[i64] }):$Immd, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), FPR32:{ *:[f32] }:$Sn, ssub:{ *:[i32] }), 0:{ *:[i64] })
109595 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
109596 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
109597 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
109598 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109599 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
109600 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
109601 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109602 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
109603 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Sn
109604 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
109605 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109606 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109607 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
109608 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
109609 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109610 GIR_RootToRootCopy, /*OpIdx*/1, // src
109611 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immd
109612 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
109613 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
109614 GIR_RootConstrainSelectedInstOperands,
109615 // GIR_Coverage, 5390,
109616 GIR_EraseRootFromParent_Done,
109617 // Label 6243: @295894
109618 GIM_Try, /*On fail goto*//*Label 6244*/ GIMT_Encode4(295938), // Rule ID 1923 //
109619 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
109620 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109621 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
109622 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
109623 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109624 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
109625 // MIs[1] Operand 1
109626 // No operand predicates
109627 GIM_CheckIsSafeToFold, /*NumInsns*/1,
109628 // (vector_insert:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) => (INSvi32gpr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (imm:{ *:[i64] }):$idx, GPR32:{ *:[i32] }:$Rn)
109629 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32gpr),
109630 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109631 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
109632 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
109633 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
109634 GIR_RootConstrainSelectedInstOperands,
109635 // GIR_Coverage, 1923,
109636 GIR_EraseRootFromParent_Done,
109637 // Label 6244: @295938
109638 GIM_Try, /*On fail goto*//*Label 6245*/ GIMT_Encode4(296034), // Rule ID 5347 //
109639 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109640 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
109641 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
109642 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109643 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
109644 // MIs[1] Operand 1
109645 // No operand predicates
109646 GIM_CheckIsSafeToFold, /*NumInsns*/1,
109647 // (vector_insert:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm) => (INSvi32lane:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
109648 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
109649 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
109650 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
109651 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109652 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
109653 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
109654 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109655 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
109656 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
109657 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
109658 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109659 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109660 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
109661 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
109662 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109663 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
109664 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
109665 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
109666 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
109667 GIR_RootConstrainSelectedInstOperands,
109668 // GIR_Coverage, 5347,
109669 GIR_EraseRootFromParent_Done,
109670 // Label 6245: @296034
109671 GIM_Reject,
109672 // Label 6230: @296035
109673 GIM_Reject,
109674 // Label 6161: @296036
109675 GIM_Try, /*On fail goto*//*Label 6246*/ GIMT_Encode4(297070),
109676 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
109677 GIM_Try, /*On fail goto*//*Label 6247*/ GIMT_Encode4(296165), // Rule ID 4096 //
109678 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
109679 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
109680 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
109681 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
109682 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
109683 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
109684 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
109685 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
109686 GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
109687 GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
109688 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
109689 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
109690 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
109691 GIM_CheckIsSafeToFold, /*NumInsns*/2,
109692 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
109693 // (vector_insert:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
109694 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
109695 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
109696 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109697 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
109698 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
109699 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
109700 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
109701 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
109702 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109703 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
109704 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
109705 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
109706 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
109707 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
109708 // GIR_Coverage, 4096,
109709 GIR_EraseRootFromParent_Done,
109710 // Label 6247: @296165
109711 GIM_Try, /*On fail goto*//*Label 6248*/ GIMT_Encode4(296286), // Rule ID 4097 //
109712 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
109713 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
109714 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
109715 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
109716 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
109717 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
109718 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
109719 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
109720 GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
109721 GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
109722 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
109723 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
109724 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
109725 GIM_CheckIsSafeToFold, /*NumInsns*/2,
109726 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
109727 // (vector_insert:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
109728 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
109729 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
109730 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109731 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
109732 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
109733 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
109734 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
109735 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
109736 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109737 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
109738 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
109739 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
109740 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
109741 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
109742 // GIR_Coverage, 4097,
109743 GIR_EraseRootFromParent_Done,
109744 // Label 6248: @296286
109745 GIM_Try, /*On fail goto*//*Label 6249*/ GIMT_Encode4(296426), // Rule ID 5376 //
109746 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
109747 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
109748 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109749 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
109750 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
109751 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
109752 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
109753 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
109754 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109755 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
109756 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109757 // MIs[2] Operand 1
109758 // No operand predicates
109759 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
109760 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109761 // MIs[3] Operand 1
109762 // No operand predicates
109763 GIM_CheckIsSafeToFold, /*NumInsns*/3,
109764 // (vector_insert:{ *:[v8i8] } V64:{ *:[v8i8] }:$src, (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (EXTRACT_SUBREG:{ *:[v8i8] } (INSvi8lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
109765 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
109766 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
109767 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
109768 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109769 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
109770 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
109771 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
109772 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109773 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
109774 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
109775 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109776 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
109777 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
109778 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
109779 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
109780 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
109781 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
109782 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109783 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
109784 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
109785 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109786 // GIR_Coverage, 5376,
109787 GIR_EraseRootFromParent_Done,
109788 // Label 6249: @296426
109789 GIM_Try, /*On fail goto*//*Label 6250*/ GIMT_Encode4(296597), // Rule ID 5377 //
109790 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
109791 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
109792 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109793 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
109794 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
109795 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
109796 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
109797 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
109798 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
109799 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
109800 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109801 // MIs[2] Operand 1
109802 // No operand predicates
109803 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
109804 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109805 // MIs[3] Operand 1
109806 // No operand predicates
109807 GIM_CheckIsSafeToFold, /*NumInsns*/3,
109808 // (vector_insert:{ *:[v8i8] } V64:{ *:[v8i8] }:$src, (vector_extract:{ *:[i32] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (EXTRACT_SUBREG:{ *:[v8i8] } (INSvi8lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
109809 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
109810 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
109811 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
109812 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
109813 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109814 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
109815 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
109816 GIR_AddImm8, /*InsnID*/3, /*Imm*/2,
109817 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109818 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
109819 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
109820 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109821 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
109822 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
109823 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
109824 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109825 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
109826 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
109827 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109828 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
109829 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
109830 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
109831 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
109832 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
109833 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
109834 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109835 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
109836 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
109837 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109838 // GIR_Coverage, 5377,
109839 GIR_EraseRootFromParent_Done,
109840 // Label 6250: @296597
109841 GIM_Try, /*On fail goto*//*Label 6251*/ GIMT_Encode4(296746), // Rule ID 6046 //
109842 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
109843 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
109844 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109845 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
109846 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
109847 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
109848 GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
109849 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
109850 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
109851 // MIs[1] Rn
109852 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
109853 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
109854 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
109855 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109856 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
109857 // MIs[2] Operand 1
109858 // No operand predicates
109859 GIM_CheckIsSafeToFold, /*NumInsns*/2,
109860 // (vector_insert:{ *:[v8i8] } VecListOne64:{ *:[v8i8] }:$Rd, (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx) => (EXTRACT_SUBREG:{ *:[v8i8] } (LD1i8:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
109861 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
109862 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
109863 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
109864 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109865 GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
109866 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rd
109867 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
109868 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109869 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
109870 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i8),
109871 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109872 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
109873 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // idx
109874 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
109875 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
109876 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
109877 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
109878 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109879 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
109880 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
109881 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109882 // GIR_Coverage, 6046,
109883 GIR_EraseRootFromParent_Done,
109884 // Label 6251: @296746
109885 GIM_Try, /*On fail goto*//*Label 6252*/ GIMT_Encode4(296881), // Rule ID 5351 //
109886 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
109887 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
109888 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109889 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
109890 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
109891 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
109892 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109893 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
109894 // MIs[1] Operand 1
109895 // No operand predicates
109896 GIM_CheckIsSafeToFold, /*NumInsns*/1,
109897 // (vector_insert:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, GPR32:{ *:[i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$imm) => (EXTRACT_SUBREG:{ *:[v8i8] } (INSvi8gpr:{ *:[f128] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$imm, GPR32:{ *:[i32] }:$Rm), dsub:{ *:[i32] })
109898 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
109899 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
109900 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
109901 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
109902 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109903 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
109904 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
109905 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109906 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
109907 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
109908 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
109909 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109910 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109911 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
109912 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi8gpr),
109913 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109914 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
109915 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
109916 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
109917 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
109918 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
109919 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109920 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
109921 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
109922 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109923 // GIR_Coverage, 5351,
109924 GIR_EraseRootFromParent_Done,
109925 // Label 6252: @296881
109926 GIM_Try, /*On fail goto*//*Label 6253*/ GIMT_Encode4(297069), // Rule ID 5352 //
109927 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
109928 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
109929 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109930 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
109931 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
109932 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
109933 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
109934 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
109935 // MIs[1] Operand 1
109936 // No operand predicates
109937 GIM_CheckIsSafeToFold, /*NumInsns*/1,
109938 // (vector_insert:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, FPR8:{ *:[i8] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$imm) => (EXTRACT_SUBREG:{ *:[v8i8] } (INSvi8lane:{ *:[f128] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$imm, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), FPR8:{ *:[i8] }:$Rm, bsub:{ *:[i32] }), 0:{ *:[i64] }), dsub:{ *:[i32] })
109939 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
109940 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
109941 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
109942 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
109943 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v16s8,
109944 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
109945 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109946 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
109947 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
109948 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109949 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
109950 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
109951 GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
109952 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109953 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109954 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
109955 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
109956 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109957 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
109958 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
109959 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109960 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
109961 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
109962 GIR_AddImm8, /*InsnID*/2, /*Imm*/2,
109963 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
109964 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109965 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
109966 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
109967 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
109968 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
109969 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
109970 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
109971 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
109972 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
109973 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
109974 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
109975 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
109976 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
109977 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
109978 // GIR_Coverage, 5352,
109979 GIR_EraseRootFromParent_Done,
109980 // Label 6253: @297069
109981 GIM_Reject,
109982 // Label 6246: @297070
109983 GIM_Reject,
109984 // Label 6162: @297071
109985 GIM_Try, /*On fail goto*//*Label 6254*/ GIMT_Encode4(298994),
109986 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
109987 GIM_Try, /*On fail goto*//*Label 6255*/ GIMT_Encode4(297193), // Rule ID 4118 //
109988 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
109989 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
109990 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
109991 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
109992 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
109993 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
109994 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
109995 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
109996 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
109997 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
109998 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
109999 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
110000 GIM_CheckIsSafeToFold, /*NumInsns*/2,
110001 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
110002 // (vector_insert:{ *:[v8f16] } immAllZerosV:{ *:[v8f16] }, (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
110003 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
110004 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
110005 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110006 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
110007 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
110008 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
110009 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
110010 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
110011 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110012 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
110013 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
110014 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
110015 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
110016 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
110017 // GIR_Coverage, 4118,
110018 GIR_EraseRootFromParent_Done,
110019 // Label 6255: @297193
110020 GIM_Try, /*On fail goto*//*Label 6256*/ GIMT_Encode4(297307), // Rule ID 4119 //
110021 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
110022 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110023 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110024 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
110025 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
110026 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
110027 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
110028 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
110029 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
110030 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
110031 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
110032 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
110033 GIM_CheckIsSafeToFold, /*NumInsns*/2,
110034 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
110035 // (vector_insert:{ *:[v8f16] } immAllZerosV:{ *:[v8f16] }, (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
110036 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
110037 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
110038 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110039 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
110040 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
110041 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
110042 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
110043 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
110044 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110045 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
110046 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
110047 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
110048 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
110049 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
110050 // GIR_Coverage, 4119,
110051 GIR_EraseRootFromParent_Done,
110052 // Label 6256: @297307
110053 GIM_Try, /*On fail goto*//*Label 6257*/ GIMT_Encode4(297421), // Rule ID 4124 //
110054 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
110055 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110056 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110057 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
110058 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
110059 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
110060 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
110061 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
110062 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
110063 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
110064 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
110065 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
110066 GIM_CheckIsSafeToFold, /*NumInsns*/2,
110067 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
110068 // (vector_insert:{ *:[v8bf16] } immAllZerosV:{ *:[v8bf16] }, (ld:{ *:[bf16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v8bf16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
110069 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
110070 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
110071 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110072 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
110073 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
110074 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
110075 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
110076 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
110077 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110078 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
110079 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
110080 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
110081 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
110082 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
110083 // GIR_Coverage, 4124,
110084 GIR_EraseRootFromParent_Done,
110085 // Label 6257: @297421
110086 GIM_Try, /*On fail goto*//*Label 6258*/ GIMT_Encode4(297535), // Rule ID 4125 //
110087 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
110088 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110089 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110090 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
110091 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
110092 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
110093 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
110094 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
110095 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
110096 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
110097 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
110098 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
110099 GIM_CheckIsSafeToFold, /*NumInsns*/2,
110100 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
110101 // (vector_insert:{ *:[v8bf16] } immAllZerosV:{ *:[v8bf16] }, (ld:{ *:[bf16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v8bf16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
110102 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
110103 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
110104 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110105 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
110106 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
110107 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
110108 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
110109 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
110110 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110111 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
110112 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
110113 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
110114 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
110115 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
110116 // GIR_Coverage, 4125,
110117 GIR_EraseRootFromParent_Done,
110118 // Label 6258: @297535
110119 GIM_Try, /*On fail goto*//*Label 6259*/ GIMT_Encode4(297656), // Rule ID 4100 //
110120 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
110121 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110122 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110123 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
110124 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
110125 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
110126 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
110127 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
110128 GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
110129 GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
110130 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
110131 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
110132 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
110133 GIM_CheckIsSafeToFold, /*NumInsns*/2,
110134 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
110135 // (vector_insert:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
110136 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
110137 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
110138 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110139 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
110140 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
110141 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
110142 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
110143 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
110144 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110145 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
110146 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
110147 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
110148 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
110149 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
110150 // GIR_Coverage, 4100,
110151 GIR_EraseRootFromParent_Done,
110152 // Label 6259: @297656
110153 GIM_Try, /*On fail goto*//*Label 6260*/ GIMT_Encode4(297777), // Rule ID 4101 //
110154 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
110155 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110156 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110157 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
110158 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
110159 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
110160 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
110161 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
110162 GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
110163 GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
110164 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
110165 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
110166 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
110167 GIM_CheckIsSafeToFold, /*NumInsns*/2,
110168 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
110169 // (vector_insert:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
110170 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
110171 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
110172 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110173 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
110174 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
110175 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
110176 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
110177 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
110178 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110179 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
110180 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
110181 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
110182 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
110183 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
110184 // GIR_Coverage, 4101,
110185 GIR_EraseRootFromParent_Done,
110186 // Label 6260: @297777
110187 GIM_Try, /*On fail goto*//*Label 6261*/ GIMT_Encode4(297865), // Rule ID 1926 //
110188 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
110189 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
110190 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110191 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110192 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110193 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
110194 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
110195 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
110196 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
110197 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110198 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
110199 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110200 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
110201 // MIs[2] Operand 1
110202 // No operand predicates
110203 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
110204 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110205 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
110206 // MIs[3] Operand 1
110207 // No operand predicates
110208 GIM_CheckIsSafeToFold, /*NumInsns*/3,
110209 // (vector_insert:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx2), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) => (INSvi16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (imm:{ *:[i64] }):$idx, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx2)
110210 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
110211 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110212 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
110213 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
110214 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
110215 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
110216 GIR_RootConstrainSelectedInstOperands,
110217 // GIR_Coverage, 1926,
110218 GIR_EraseRootFromParent_Done,
110219 // Label 6261: @297865
110220 GIM_Try, /*On fail goto*//*Label 6262*/ GIMT_Encode4(297942), // Rule ID 5358 //
110221 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
110222 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110223 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110224 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110225 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
110226 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
110227 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
110228 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
110229 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110230 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
110231 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110232 // MIs[2] Operand 1
110233 // No operand predicates
110234 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
110235 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110236 // MIs[3] Operand 1
110237 // No operand predicates
110238 GIM_CheckIsSafeToFold, /*NumInsns*/3,
110239 // (vector_insert:{ *:[v8f16] } V128:{ *:[v8f16] }:$src, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (INSvi16lane:{ *:[v8f16] } V128:{ *:[v8f16] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] }):$Immn)
110240 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
110241 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110242 GIR_RootToRootCopy, /*OpIdx*/1, // src
110243 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
110244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
110245 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
110246 GIR_RootConstrainSelectedInstOperands,
110247 // GIR_Coverage, 5358,
110248 GIR_EraseRootFromParent_Done,
110249 // Label 6262: @297942
110250 GIM_Try, /*On fail goto*//*Label 6263*/ GIMT_Encode4(298050), // Rule ID 5359 //
110251 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
110252 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110253 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110254 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110255 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
110256 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
110257 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
110258 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
110259 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
110260 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
110261 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110262 // MIs[2] Operand 1
110263 // No operand predicates
110264 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
110265 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110266 // MIs[3] Operand 1
110267 // No operand predicates
110268 GIM_CheckIsSafeToFold, /*NumInsns*/3,
110269 // (vector_insert:{ *:[v8f16] } V128:{ *:[v8f16] }:$src, (vector_extract:{ *:[f16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (INSvi16lane:{ *:[v8f16] } V128:{ *:[v8f16] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
110270 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
110271 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
110272 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110273 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
110274 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
110275 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
110276 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
110277 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
110278 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
110279 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110280 GIR_RootToRootCopy, /*OpIdx*/1, // src
110281 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
110282 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
110283 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
110284 GIR_RootConstrainSelectedInstOperands,
110285 // GIR_Coverage, 5359,
110286 GIR_EraseRootFromParent_Done,
110287 // Label 6263: @298050
110288 GIM_Try, /*On fail goto*//*Label 6264*/ GIMT_Encode4(298127), // Rule ID 5362 //
110289 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
110290 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110291 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110292 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110293 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
110294 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
110295 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
110296 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
110297 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110298 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
110299 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110300 // MIs[2] Operand 1
110301 // No operand predicates
110302 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
110303 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110304 // MIs[3] Operand 1
110305 // No operand predicates
110306 GIM_CheckIsSafeToFold, /*NumInsns*/3,
110307 // (vector_insert:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$src, (vector_extract:{ *:[bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (INSvi16lane:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] }):$Immn)
110308 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
110309 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110310 GIR_RootToRootCopy, /*OpIdx*/1, // src
110311 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
110312 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
110313 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
110314 GIR_RootConstrainSelectedInstOperands,
110315 // GIR_Coverage, 5362,
110316 GIR_EraseRootFromParent_Done,
110317 // Label 6264: @298127
110318 GIM_Try, /*On fail goto*//*Label 6265*/ GIMT_Encode4(298235), // Rule ID 5363 //
110319 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
110320 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110321 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110322 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110323 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
110324 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
110325 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
110326 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
110327 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
110328 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
110329 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110330 // MIs[2] Operand 1
110331 // No operand predicates
110332 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
110333 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110334 // MIs[3] Operand 1
110335 // No operand predicates
110336 GIM_CheckIsSafeToFold, /*NumInsns*/3,
110337 // (vector_insert:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$src, (vector_extract:{ *:[bf16] } V64:{ *:[v4bf16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (INSvi16lane:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4bf16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
110338 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
110339 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
110340 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110341 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
110342 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
110343 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
110344 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
110345 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
110346 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
110347 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110348 GIR_RootToRootCopy, /*OpIdx*/1, // src
110349 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
110350 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
110351 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
110352 GIR_RootConstrainSelectedInstOperands,
110353 // GIR_Coverage, 5363,
110354 GIR_EraseRootFromParent_Done,
110355 // Label 6265: @298235
110356 GIM_Try, /*On fail goto*//*Label 6266*/ GIMT_Encode4(298312), // Rule ID 5378 //
110357 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
110358 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110359 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110360 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110361 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
110362 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
110363 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
110364 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
110365 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110366 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
110367 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110368 // MIs[2] Operand 1
110369 // No operand predicates
110370 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
110371 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110372 // MIs[3] Operand 1
110373 // No operand predicates
110374 GIM_CheckIsSafeToFold, /*NumInsns*/3,
110375 // (vector_insert:{ *:[v8i16] } V128:{ *:[v8i16] }:$src, (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (INSvi16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$Immn)
110376 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
110377 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110378 GIR_RootToRootCopy, /*OpIdx*/1, // src
110379 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
110380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
110381 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
110382 GIR_RootConstrainSelectedInstOperands,
110383 // GIR_Coverage, 5378,
110384 GIR_EraseRootFromParent_Done,
110385 // Label 6266: @298312
110386 GIM_Try, /*On fail goto*//*Label 6267*/ GIMT_Encode4(298420), // Rule ID 5379 //
110387 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
110388 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110389 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110390 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110391 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
110392 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
110393 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
110394 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
110395 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
110396 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
110397 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110398 // MIs[2] Operand 1
110399 // No operand predicates
110400 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
110401 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110402 // MIs[3] Operand 1
110403 // No operand predicates
110404 GIM_CheckIsSafeToFold, /*NumInsns*/3,
110405 // (vector_insert:{ *:[v8i16] } V128:{ *:[v8i16] }:$src, (vector_extract:{ *:[i32] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (INSvi16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
110406 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
110407 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
110408 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110409 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
110410 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
110411 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
110412 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
110413 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
110414 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
110415 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110416 GIR_RootToRootCopy, /*OpIdx*/1, // src
110417 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
110418 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
110419 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
110420 GIR_RootConstrainSelectedInstOperands,
110421 // GIR_Coverage, 5379,
110422 GIR_EraseRootFromParent_Done,
110423 // Label 6267: @298420
110424 GIM_Try, /*On fail goto*//*Label 6268*/ GIMT_Encode4(298483), // Rule ID 5338 //
110425 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
110426 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110427 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110428 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110429 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
110430 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
110431 GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
110432 // MIs[1] Operand 1
110433 // No operand predicates
110434 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
110435 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110436 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
110437 // MIs[2] Operand 1
110438 // No operand predicates
110439 GIM_CheckIsSafeToFold, /*NumInsns*/2,
110440 // (vector_insert:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm) => (INSvi16gpr:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm, WZR:{ *:[i32] })
110441 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16gpr),
110442 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110443 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
110444 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
110445 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
110446 GIR_RootConstrainSelectedInstOperands,
110447 // GIR_Coverage, 5338,
110448 GIR_EraseRootFromParent_Done,
110449 // Label 6268: @298483
110450 GIM_Try, /*On fail goto*//*Label 6269*/ GIMT_Encode4(298562), // Rule ID 6035 //
110451 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
110452 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110453 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110454 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110455 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
110456 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
110457 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
110458 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
110459 // MIs[1] Rn
110460 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
110461 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
110462 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
110463 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110464 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
110465 // MIs[2] Operand 1
110466 // No operand predicates
110467 GIM_CheckIsSafeToFold, /*NumInsns*/2,
110468 // (vector_insert:{ *:[v8f16] } VecListOne128:{ *:[v8f16] }:$Rd, (ld:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) => (LD1i16:{ *:[v8f16] } VecListOne128:{ *:[v8f16] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
110469 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i16),
110470 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110471 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
110472 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
110473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
110474 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
110475 GIR_RootConstrainSelectedInstOperands,
110476 // GIR_Coverage, 6035,
110477 GIR_EraseRootFromParent_Done,
110478 // Label 6269: @298562
110479 GIM_Try, /*On fail goto*//*Label 6270*/ GIMT_Encode4(298641), // Rule ID 6036 //
110480 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
110481 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110482 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110483 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110484 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
110485 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
110486 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
110487 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
110488 // MIs[1] Rn
110489 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
110490 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
110491 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
110492 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110493 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
110494 // MIs[2] Operand 1
110495 // No operand predicates
110496 GIM_CheckIsSafeToFold, /*NumInsns*/2,
110497 // (vector_insert:{ *:[v8bf16] } VecListOne128:{ *:[v8bf16] }:$Rd, (ld:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) => (LD1i16:{ *:[v8bf16] } VecListOne128:{ *:[v8bf16] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
110498 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i16),
110499 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110500 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
110501 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
110502 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
110503 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
110504 GIR_RootConstrainSelectedInstOperands,
110505 // GIR_Coverage, 6036,
110506 GIR_EraseRootFromParent_Done,
110507 // Label 6270: @298641
110508 GIM_Try, /*On fail goto*//*Label 6271*/ GIMT_Encode4(298727), // Rule ID 6030 //
110509 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
110510 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110511 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110512 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110513 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
110514 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
110515 GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
110516 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
110517 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
110518 // MIs[1] Rn
110519 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
110520 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
110521 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
110522 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110523 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
110524 // MIs[2] Operand 1
110525 // No operand predicates
110526 GIM_CheckIsSafeToFold, /*NumInsns*/2,
110527 // (vector_insert:{ *:[v8i16] } VecListOne128:{ *:[v8i16] }:$Rd, (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) => (LD1i16:{ *:[v8i16] } VecListOne128:{ *:[v8i16] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
110528 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i16),
110529 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110530 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
110531 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
110532 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
110533 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
110534 GIR_RootConstrainSelectedInstOperands,
110535 // GIR_Coverage, 6030,
110536 GIR_EraseRootFromParent_Done,
110537 // Label 6271: @298727
110538 GIM_Try, /*On fail goto*//*Label 6272*/ GIMT_Encode4(298781), // Rule ID 1922 //
110539 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
110540 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
110541 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110542 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110543 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110544 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
110545 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
110546 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110547 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
110548 // MIs[1] Operand 1
110549 // No operand predicates
110550 GIM_CheckIsSafeToFold, /*NumInsns*/1,
110551 // (vector_insert:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) => (INSvi16gpr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (imm:{ *:[i64] }):$idx, GPR32:{ *:[i32] }:$Rn)
110552 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16gpr),
110553 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110554 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
110555 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
110556 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
110557 GIR_RootConstrainSelectedInstOperands,
110558 // GIR_Coverage, 1922,
110559 GIR_EraseRootFromParent_Done,
110560 // Label 6272: @298781
110561 GIM_Try, /*On fail goto*//*Label 6273*/ GIMT_Encode4(298887), // Rule ID 5343 //
110562 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
110563 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110564 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110565 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110566 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
110567 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
110568 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110569 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
110570 // MIs[1] Operand 1
110571 // No operand predicates
110572 GIM_CheckIsSafeToFold, /*NumInsns*/1,
110573 // (vector_insert:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm) => (INSvi16lane:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm, (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), FPR16:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
110574 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
110575 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
110576 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
110577 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110578 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
110579 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
110580 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110581 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
110582 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
110583 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
110584 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
110585 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
110586 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
110587 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
110588 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110589 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
110590 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
110591 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
110592 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
110593 GIR_RootConstrainSelectedInstOperands,
110594 // GIR_Coverage, 5343,
110595 GIR_EraseRootFromParent_Done,
110596 // Label 6273: @298887
110597 GIM_Try, /*On fail goto*//*Label 6274*/ GIMT_Encode4(298993), // Rule ID 5345 //
110598 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
110599 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110600 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110601 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110602 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
110603 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
110604 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110605 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
110606 // MIs[1] Operand 1
110607 // No operand predicates
110608 GIM_CheckIsSafeToFold, /*NumInsns*/1,
110609 // (vector_insert:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, FPR16:{ *:[bf16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm) => (INSvi16lane:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm, (INSERT_SUBREG:{ *:[v8bf16] } (IMPLICIT_DEF:{ *:[v8bf16] }), FPR16:{ *:[bf16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
110610 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
110611 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
110612 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
110613 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110614 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
110615 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
110616 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110617 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
110618 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
110619 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
110620 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
110621 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
110622 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
110623 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
110624 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110625 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
110626 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
110627 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
110628 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
110629 GIR_RootConstrainSelectedInstOperands,
110630 // GIR_Coverage, 5345,
110631 GIR_EraseRootFromParent_Done,
110632 // Label 6274: @298993
110633 GIM_Reject,
110634 // Label 6254: @298994
110635 GIM_Reject,
110636 // Label 6163: @298995
110637 GIM_Try, /*On fail goto*//*Label 6275*/ GIMT_Encode4(299765),
110638 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
110639 GIM_Try, /*On fail goto*//*Label 6276*/ GIMT_Encode4(299124), // Rule ID 4094 //
110640 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
110641 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110642 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110643 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
110644 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
110645 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
110646 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
110647 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
110648 GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
110649 GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
110650 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
110651 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
110652 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
110653 GIM_CheckIsSafeToFold, /*NumInsns*/2,
110654 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
110655 // (vector_insert:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
110656 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
110657 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
110658 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110659 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
110660 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
110661 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
110662 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
110663 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
110664 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110665 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
110666 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
110667 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
110668 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
110669 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
110670 // GIR_Coverage, 4094,
110671 GIR_EraseRootFromParent_Done,
110672 // Label 6276: @299124
110673 GIM_Try, /*On fail goto*//*Label 6277*/ GIMT_Encode4(299245), // Rule ID 4095 //
110674 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
110675 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110676 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110677 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
110678 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
110679 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
110680 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
110681 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
110682 GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
110683 GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
110684 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
110685 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
110686 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
110687 GIM_CheckIsSafeToFold, /*NumInsns*/2,
110688 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
110689 // (vector_insert:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
110690 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
110691 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
110692 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110693 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
110694 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
110695 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
110696 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
110697 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
110698 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110699 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
110700 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
110701 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
110702 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
110703 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
110704 // GIR_Coverage, 4095,
110705 GIR_EraseRootFromParent_Done,
110706 // Label 6277: @299245
110707 GIM_Try, /*On fail goto*//*Label 6278*/ GIMT_Encode4(299333), // Rule ID 1925 //
110708 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
110709 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
110710 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110711 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110712 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110713 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
110714 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
110715 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
110716 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
110717 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110718 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
110719 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110720 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
110721 // MIs[2] Operand 1
110722 // No operand predicates
110723 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
110724 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110725 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
110726 // MIs[3] Operand 1
110727 // No operand predicates
110728 GIM_CheckIsSafeToFold, /*NumInsns*/3,
110729 // (vector_insert:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx2), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx) => (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (imm:{ *:[i64] }):$idx, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx2)
110730 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
110731 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110732 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
110733 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
110734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
110735 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
110736 GIR_RootConstrainSelectedInstOperands,
110737 // GIR_Coverage, 1925,
110738 GIR_EraseRootFromParent_Done,
110739 // Label 6278: @299333
110740 GIM_Try, /*On fail goto*//*Label 6279*/ GIMT_Encode4(299410), // Rule ID 5374 //
110741 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
110742 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110743 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110744 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110745 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
110746 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
110747 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
110748 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
110749 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110750 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
110751 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110752 // MIs[2] Operand 1
110753 // No operand predicates
110754 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
110755 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110756 // MIs[3] Operand 1
110757 // No operand predicates
110758 GIM_CheckIsSafeToFold, /*NumInsns*/3,
110759 // (vector_insert:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn)
110760 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
110761 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110762 GIR_RootToRootCopy, /*OpIdx*/1, // src
110763 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
110764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
110765 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
110766 GIR_RootConstrainSelectedInstOperands,
110767 // GIR_Coverage, 5374,
110768 GIR_EraseRootFromParent_Done,
110769 // Label 6279: @299410
110770 GIM_Try, /*On fail goto*//*Label 6280*/ GIMT_Encode4(299518), // Rule ID 5375 //
110771 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
110772 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110773 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110774 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110775 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
110776 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
110777 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
110778 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
110779 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
110780 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
110781 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110782 // MIs[2] Operand 1
110783 // No operand predicates
110784 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
110785 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110786 // MIs[3] Operand 1
110787 // No operand predicates
110788 GIM_CheckIsSafeToFold, /*NumInsns*/3,
110789 // (vector_insert:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (vector_extract:{ *:[i32] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd) => (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
110790 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
110791 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
110792 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110793 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
110794 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
110795 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
110796 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
110797 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
110798 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
110799 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110800 GIR_RootToRootCopy, /*OpIdx*/1, // src
110801 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
110802 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
110803 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
110804 GIR_RootConstrainSelectedInstOperands,
110805 // GIR_Coverage, 5375,
110806 GIR_EraseRootFromParent_Done,
110807 // Label 6280: @299518
110808 GIM_Try, /*On fail goto*//*Label 6281*/ GIMT_Encode4(299604), // Rule ID 6029 //
110809 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
110810 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110811 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110812 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110813 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
110814 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
110815 GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
110816 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
110817 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
110818 // MIs[1] Rn
110819 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
110820 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
110821 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
110822 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110823 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
110824 // MIs[2] Operand 1
110825 // No operand predicates
110826 GIM_CheckIsSafeToFold, /*NumInsns*/2,
110827 // (vector_insert:{ *:[v16i8] } VecListOne128:{ *:[v16i8] }:$Rd, (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx) => (LD1i8:{ *:[v16i8] } VecListOne128:{ *:[v16i8] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
110828 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i8),
110829 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110830 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
110831 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
110832 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
110833 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
110834 GIR_RootConstrainSelectedInstOperands,
110835 // GIR_Coverage, 6029,
110836 GIR_EraseRootFromParent_Done,
110837 // Label 6281: @299604
110838 GIM_Try, /*On fail goto*//*Label 6282*/ GIMT_Encode4(299658), // Rule ID 1921 //
110839 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
110840 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
110841 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110842 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110843 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110844 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
110845 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
110846 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110847 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
110848 // MIs[1] Operand 1
110849 // No operand predicates
110850 GIM_CheckIsSafeToFold, /*NumInsns*/1,
110851 // (vector_insert:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx) => (INSvi8gpr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (imm:{ *:[i64] }):$idx, GPR32:{ *:[i32] }:$Rn)
110852 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8gpr),
110853 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110854 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
110855 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
110856 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
110857 GIR_RootConstrainSelectedInstOperands,
110858 // GIR_Coverage, 1921,
110859 GIR_EraseRootFromParent_Done,
110860 // Label 6282: @299658
110861 GIM_Try, /*On fail goto*//*Label 6283*/ GIMT_Encode4(299764), // Rule ID 5353 //
110862 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
110863 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110864 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110865 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
110866 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
110867 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
110868 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
110869 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
110870 // MIs[1] Operand 1
110871 // No operand predicates
110872 GIM_CheckIsSafeToFold, /*NumInsns*/1,
110873 // (vector_insert:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, FPR8:{ *:[i8] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$imm) => (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$imm, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), FPR8:{ *:[i8] }:$Rm, bsub:{ *:[i32] }), 0:{ *:[i64] })
110874 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
110875 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
110876 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
110877 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110878 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
110879 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
110880 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110881 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
110882 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
110883 GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
110884 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
110885 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
110886 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
110887 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
110888 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
110889 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
110890 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
110891 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
110892 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
110893 GIR_RootConstrainSelectedInstOperands,
110894 // GIR_Coverage, 5353,
110895 GIR_EraseRootFromParent_Done,
110896 // Label 6283: @299764
110897 GIM_Reject,
110898 // Label 6275: @299765
110899 GIM_Reject,
110900 // Label 6164: @299766
110901 GIM_Try, /*On fail goto*//*Label 6284*/ GIMT_Encode4(299999),
110902 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
110903 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
110904 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110905 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
110906 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
110907 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
110908 GIM_Try, /*On fail goto*//*Label 6285*/ GIMT_Encode4(299895), // Rule ID 10848 //
110909 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
110910 // (vector_insert:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$vec, FPR16:{ *:[f16] }:$src, GPR64:{ *:[i64] }:$index) => (CPY_ZPmV_H:{ *:[nxv2f16] } ZPR:{ *:[nxv2f16] }:$vec, (CMPEQ_PPzZZ_D:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_D:{ *:[nxv16i8] } 0:{ *:[i64] }, 1:{ *:[i64] }), (DUP_ZR_D:{ *:[nxv16i8] } GPR64:{ *:[i64] }:$index)), ?:{ *:[f16] }:$src)
110911 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
110912 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
110913 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
110914 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
110915 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_D),
110916 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110917 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/3, // index
110918 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
110919 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_D),
110920 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110921 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
110922 GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
110923 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
110924 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
110925 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110926 GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
110927 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
110928 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_D),
110929 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110930 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
110931 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
110932 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
110933 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
110934 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
110935 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_H),
110936 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
110937 GIR_RootToRootCopy, /*OpIdx*/1, // vec
110938 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
110939 GIR_RootToRootCopy, /*OpIdx*/2, // src
110940 GIR_RootConstrainSelectedInstOperands,
110941 // GIR_Coverage, 10848,
110942 GIR_EraseRootFromParent_Done,
110943 // Label 6285: @299895
110944 GIM_Try, /*On fail goto*//*Label 6286*/ GIMT_Encode4(299998), // Rule ID 10851 //
110945 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
110946 // (vector_insert:{ *:[nxv2bf16] } nxv2bf16:{ *:[nxv2bf16] }:$vec, FPR16:{ *:[bf16] }:$src, GPR64:{ *:[i64] }:$index) => (CPY_ZPmV_H:{ *:[nxv2bf16] } ZPR:{ *:[nxv2bf16] }:$vec, (CMPEQ_PPzZZ_D:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_D:{ *:[nxv16i8] } 0:{ *:[i64] }, 1:{ *:[i64] }), (DUP_ZR_D:{ *:[nxv16i8] } GPR64:{ *:[i64] }:$index)), ?:{ *:[bf16] }:$src)
110947 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
110948 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
110949 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
110950 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
110951 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_D),
110952 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110953 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/3, // index
110954 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
110955 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_D),
110956 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110957 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
110958 GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
110959 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
110960 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
110961 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110962 GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
110963 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
110964 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_D),
110965 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110966 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
110967 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
110968 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
110969 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
110970 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
110971 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_H),
110972 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
110973 GIR_RootToRootCopy, /*OpIdx*/1, // vec
110974 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
110975 GIR_RootToRootCopy, /*OpIdx*/2, // src
110976 GIR_RootConstrainSelectedInstOperands,
110977 // GIR_Coverage, 10851,
110978 GIR_EraseRootFromParent_Done,
110979 // Label 6286: @299998
110980 GIM_Reject,
110981 // Label 6284: @299999
110982 GIM_Reject,
110983 // Label 6165: @300000
110984 GIM_Try, /*On fail goto*//*Label 6287*/ GIMT_Encode4(300124), // Rule ID 10854 //
110985 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
110986 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
110987 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
110988 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
110989 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
110990 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
110991 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
110992 // (vector_insert:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$vec, FPR32:{ *:[f32] }:$src, GPR64:{ *:[i64] }:$index) => (CPY_ZPmV_S:{ *:[nxv2f32] } ZPR:{ *:[nxv2f32] }:$vec, (CMPEQ_PPzZZ_D:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_D:{ *:[nxv16i8] } 0:{ *:[i64] }, 1:{ *:[i64] }), (DUP_ZR_D:{ *:[nxv16i8] } GPR64:{ *:[i64] }:$index)), ?:{ *:[f32] }:$src)
110993 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
110994 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
110995 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
110996 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
110997 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_D),
110998 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
110999 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/3, // index
111000 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
111001 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_D),
111002 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111003 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
111004 GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
111005 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
111006 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
111007 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111008 GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
111009 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
111010 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_D),
111011 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111012 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
111013 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
111014 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
111015 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
111016 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111017 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_S),
111018 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
111019 GIR_RootToRootCopy, /*OpIdx*/1, // vec
111020 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111021 GIR_RootToRootCopy, /*OpIdx*/2, // src
111022 GIR_RootConstrainSelectedInstOperands,
111023 // GIR_Coverage, 10854,
111024 GIR_EraseRootFromParent_Done,
111025 // Label 6287: @300124
111026 GIM_Reject,
111027 // Label 6166: @300125
111028 GIM_Try, /*On fail goto*//*Label 6288*/ GIMT_Encode4(300782),
111029 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
111030 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
111031 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
111032 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
111033 GIM_Try, /*On fail goto*//*Label 6289*/ GIMT_Encode4(300247), // Rule ID 4116 //
111034 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
111035 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
111036 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
111037 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
111038 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
111039 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
111040 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
111041 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
111042 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
111043 GIM_CheckIsSafeToFold, /*NumInsns*/2,
111044 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
111045 // (vector_insert:{ *:[nxv2i64] } immAllZerosV:{ *:[nxv2i64] }, (ld:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
111046 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
111047 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
111048 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111049 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
111050 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
111051 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
111052 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111053 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
111054 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
111055 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
111056 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111057 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
111058 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
111059 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
111060 // GIR_Coverage, 4116,
111061 GIR_EraseRootFromParent_Done,
111062 // Label 6289: @300247
111063 GIM_Try, /*On fail goto*//*Label 6290*/ GIMT_Encode4(300351), // Rule ID 4117 //
111064 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
111065 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
111066 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
111067 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
111068 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
111069 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
111070 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
111071 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
111072 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
111073 GIM_CheckIsSafeToFold, /*NumInsns*/2,
111074 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
111075 // (vector_insert:{ *:[nxv2i64] } immAllZerosV:{ *:[nxv2i64] }, (ld:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
111076 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
111077 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
111078 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111079 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
111080 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
111081 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
111082 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111083 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
111084 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
111085 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
111086 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111087 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
111088 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
111089 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
111090 // GIR_Coverage, 4117,
111091 GIR_EraseRootFromParent_Done,
111092 // Label 6290: @300351
111093 GIM_Try, /*On fail goto*//*Label 6291*/ GIMT_Encode4(300455), // Rule ID 4140 //
111094 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
111095 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
111096 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
111097 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
111098 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
111099 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
111100 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
111101 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
111102 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
111103 GIM_CheckIsSafeToFold, /*NumInsns*/2,
111104 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
111105 // (vector_insert:{ *:[nxv2f64] } immAllZerosV:{ *:[nxv2f64] }, (ld:{ *:[f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
111106 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
111107 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
111108 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111109 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
111110 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
111111 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
111112 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111113 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
111114 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
111115 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
111116 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111117 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
111118 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
111119 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
111120 // GIR_Coverage, 4140,
111121 GIR_EraseRootFromParent_Done,
111122 // Label 6291: @300455
111123 GIM_Try, /*On fail goto*//*Label 6292*/ GIMT_Encode4(300559), // Rule ID 4141 //
111124 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
111125 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
111126 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
111127 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
111128 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
111129 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
111130 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
111131 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
111132 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
111133 GIM_CheckIsSafeToFold, /*NumInsns*/2,
111134 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
111135 // (vector_insert:{ *:[nxv2f64] } immAllZerosV:{ *:[nxv2f64] }, (ld:{ *:[f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
111136 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
111137 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
111138 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111139 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
111140 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
111141 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
111142 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111143 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
111144 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
111145 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
111146 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111147 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
111148 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
111149 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
111150 // GIR_Coverage, 4141,
111151 GIR_EraseRootFromParent_Done,
111152 // Label 6292: @300559
111153 GIM_Try, /*On fail goto*//*Label 6293*/ GIMT_Encode4(300670), // Rule ID 10847 //
111154 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
111155 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
111156 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
111157 // (vector_insert:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$vec, GPR64:{ *:[i64] }:$src, GPR64:{ *:[i64] }:$index) => (CPY_ZPmR_D:{ *:[nxv2i64] } ZPR:{ *:[nxv2i64] }:$vec, (CMPEQ_PPzZZ_D:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_D:{ *:[nxv16i8] } 0:{ *:[i64] }, 1:{ *:[i64] }), (DUP_ZR_D:{ *:[nxv16i8] } GPR64:{ *:[i64] }:$index)), GPR64:{ *:[i64] }:$src)
111158 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
111159 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
111160 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
111161 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
111162 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_D),
111163 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111164 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/3, // index
111165 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
111166 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_D),
111167 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111168 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
111169 GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
111170 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
111171 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
111172 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111173 GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
111174 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
111175 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_D),
111176 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111177 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
111178 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
111179 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
111180 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
111181 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111182 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmR_D),
111183 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
111184 GIR_RootToRootCopy, /*OpIdx*/1, // vec
111185 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111186 GIR_RootToRootCopy, /*OpIdx*/2, // src
111187 GIR_RootConstrainSelectedInstOperands,
111188 // GIR_Coverage, 10847,
111189 GIR_EraseRootFromParent_Done,
111190 // Label 6293: @300670
111191 GIM_Try, /*On fail goto*//*Label 6294*/ GIMT_Encode4(300781), // Rule ID 10856 //
111192 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
111193 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
111194 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
111195 // (vector_insert:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$vec, FPR64:{ *:[f64] }:$src, GPR64:{ *:[i64] }:$index) => (CPY_ZPmV_D:{ *:[nxv2f64] } ZPR:{ *:[nxv2f64] }:$vec, (CMPEQ_PPzZZ_D:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_D:{ *:[nxv16i8] } 0:{ *:[i64] }, 1:{ *:[i64] }), (DUP_ZR_D:{ *:[nxv16i8] } ?:{ *:[i64] }:$index)), ?:{ *:[f64] }:$src)
111196 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
111197 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
111198 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
111199 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
111200 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_D),
111201 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111202 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/3, // index
111203 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
111204 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_D),
111205 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111206 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
111207 GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
111208 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
111209 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
111210 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111211 GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
111212 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
111213 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_D),
111214 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111215 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
111216 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
111217 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
111218 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
111219 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111220 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_D),
111221 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
111222 GIR_RootToRootCopy, /*OpIdx*/1, // vec
111223 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111224 GIR_RootToRootCopy, /*OpIdx*/2, // src
111225 GIR_RootConstrainSelectedInstOperands,
111226 // GIR_Coverage, 10856,
111227 GIR_EraseRootFromParent_Done,
111228 // Label 6294: @300781
111229 GIM_Reject,
111230 // Label 6288: @300782
111231 GIM_Reject,
111232 // Label 6167: @300783
111233 GIM_Try, /*On fail goto*//*Label 6295*/ GIMT_Encode4(301070),
111234 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
111235 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
111236 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
111237 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
111238 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
111239 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
111240 GIM_Try, /*On fail goto*//*Label 6296*/ GIMT_Encode4(300939), // Rule ID 10849 //
111241 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
111242 // (vector_insert:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$vec, FPR16:{ *:[f16] }:$src, GPR64:{ *:[i64] }:$index) => (CPY_ZPmV_H:{ *:[nxv4f16] } ZPR:{ *:[nxv4f16] }:$vec, (CMPEQ_PPzZZ_S:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_S:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_S:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), ?:{ *:[f16] }:$src)
111243 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
111244 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
111245 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
111246 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
111247 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
111248 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
111249 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111250 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(16), // index
111251 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
111252 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
111253 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_S),
111254 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111255 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
111256 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
111257 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_S),
111258 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111259 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
111260 GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
111261 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
111262 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
111263 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111264 GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
111265 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
111266 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_S),
111267 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111268 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
111269 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
111270 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
111271 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
111272 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111273 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_H),
111274 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
111275 GIR_RootToRootCopy, /*OpIdx*/1, // vec
111276 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111277 GIR_RootToRootCopy, /*OpIdx*/2, // src
111278 GIR_RootConstrainSelectedInstOperands,
111279 // GIR_Coverage, 10849,
111280 GIR_EraseRootFromParent_Done,
111281 // Label 6296: @300939
111282 GIM_Try, /*On fail goto*//*Label 6297*/ GIMT_Encode4(301069), // Rule ID 10852 //
111283 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
111284 // (vector_insert:{ *:[nxv4bf16] } nxv4bf16:{ *:[nxv4bf16] }:$vec, FPR16:{ *:[bf16] }:$src, GPR64:{ *:[i64] }:$index) => (CPY_ZPmV_H:{ *:[nxv4bf16] } ZPR:{ *:[nxv4bf16] }:$vec, (CMPEQ_PPzZZ_S:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_S:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_S:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), ?:{ *:[bf16] }:$src)
111285 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
111286 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
111287 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
111288 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
111289 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
111290 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
111291 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111292 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(16), // index
111293 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
111294 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
111295 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_S),
111296 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111297 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
111298 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
111299 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_S),
111300 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111301 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
111302 GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
111303 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
111304 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
111305 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111306 GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
111307 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
111308 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_S),
111309 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111310 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
111311 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
111312 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
111313 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
111314 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111315 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_H),
111316 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
111317 GIR_RootToRootCopy, /*OpIdx*/1, // vec
111318 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111319 GIR_RootToRootCopy, /*OpIdx*/2, // src
111320 GIR_RootConstrainSelectedInstOperands,
111321 // GIR_Coverage, 10852,
111322 GIR_EraseRootFromParent_Done,
111323 // Label 6297: @301069
111324 GIM_Reject,
111325 // Label 6295: @301070
111326 GIM_Reject,
111327 // Label 6168: @301071
111328 GIM_Try, /*On fail goto*//*Label 6298*/ GIMT_Encode4(301782),
111329 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
111330 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
111331 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
111332 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
111333 GIM_Try, /*On fail goto*//*Label 6299*/ GIMT_Encode4(301193), // Rule ID 4110 //
111334 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
111335 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
111336 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
111337 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
111338 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
111339 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
111340 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
111341 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
111342 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
111343 GIM_CheckIsSafeToFold, /*NumInsns*/2,
111344 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
111345 // (vector_insert:{ *:[nxv4i32] } immAllZerosV:{ *:[nxv4i32] }, (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
111346 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
111347 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
111348 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111349 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
111350 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
111351 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
111352 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111353 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
111354 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
111355 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
111356 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111357 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
111358 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
111359 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
111360 // GIR_Coverage, 4110,
111361 GIR_EraseRootFromParent_Done,
111362 // Label 6299: @301193
111363 GIM_Try, /*On fail goto*//*Label 6300*/ GIMT_Encode4(301297), // Rule ID 4111 //
111364 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
111365 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
111366 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
111367 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
111368 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
111369 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
111370 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
111371 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
111372 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
111373 GIM_CheckIsSafeToFold, /*NumInsns*/2,
111374 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
111375 // (vector_insert:{ *:[nxv4i32] } immAllZerosV:{ *:[nxv4i32] }, (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
111376 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
111377 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
111378 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111379 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
111380 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
111381 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
111382 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111383 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
111384 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
111385 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
111386 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111387 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
111388 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
111389 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
111390 // GIR_Coverage, 4111,
111391 GIR_EraseRootFromParent_Done,
111392 // Label 6300: @301297
111393 GIM_Try, /*On fail goto*//*Label 6301*/ GIMT_Encode4(301401), // Rule ID 4134 //
111394 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
111395 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
111396 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
111397 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
111398 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
111399 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
111400 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
111401 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
111402 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
111403 GIM_CheckIsSafeToFold, /*NumInsns*/2,
111404 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
111405 // (vector_insert:{ *:[nxv4f32] } immAllZerosV:{ *:[nxv4f32] }, (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
111406 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
111407 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
111408 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111409 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
111410 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
111411 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
111412 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111413 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
111414 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
111415 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
111416 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111417 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
111418 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
111419 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
111420 // GIR_Coverage, 4134,
111421 GIR_EraseRootFromParent_Done,
111422 // Label 6301: @301401
111423 GIM_Try, /*On fail goto*//*Label 6302*/ GIMT_Encode4(301505), // Rule ID 4135 //
111424 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
111425 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
111426 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
111427 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
111428 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
111429 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
111430 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
111431 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
111432 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
111433 GIM_CheckIsSafeToFold, /*NumInsns*/2,
111434 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
111435 // (vector_insert:{ *:[nxv4f32] } immAllZerosV:{ *:[nxv4f32] }, (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
111436 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
111437 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
111438 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111439 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
111440 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
111441 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
111442 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111443 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
111444 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
111445 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
111446 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111447 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
111448 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
111449 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
111450 // GIR_Coverage, 4135,
111451 GIR_EraseRootFromParent_Done,
111452 // Label 6302: @301505
111453 GIM_Try, /*On fail goto*//*Label 6303*/ GIMT_Encode4(301643), // Rule ID 10846 //
111454 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
111455 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
111456 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
111457 // (vector_insert:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$vec, GPR32:{ *:[i32] }:$src, GPR64:{ *:[i64] }:$index) => (CPY_ZPmR_S:{ *:[nxv4i32] } ZPR:{ *:[nxv4i32] }:$vec, (CMPEQ_PPzZZ_S:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_S:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_S:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), GPR32:{ *:[i32] }:$src)
111458 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
111459 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
111460 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
111461 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
111462 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
111463 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
111464 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111465 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(16), // index
111466 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
111467 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
111468 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_S),
111469 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111470 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
111471 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
111472 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_S),
111473 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111474 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
111475 GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
111476 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
111477 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
111478 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111479 GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
111480 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
111481 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_S),
111482 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111483 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
111484 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
111485 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
111486 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
111487 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111488 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmR_S),
111489 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
111490 GIR_RootToRootCopy, /*OpIdx*/1, // vec
111491 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111492 GIR_RootToRootCopy, /*OpIdx*/2, // src
111493 GIR_RootConstrainSelectedInstOperands,
111494 // GIR_Coverage, 10846,
111495 GIR_EraseRootFromParent_Done,
111496 // Label 6303: @301643
111497 GIM_Try, /*On fail goto*//*Label 6304*/ GIMT_Encode4(301781), // Rule ID 10855 //
111498 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
111499 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
111500 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
111501 // (vector_insert:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$vec, FPR32:{ *:[f32] }:$src, GPR64:{ *:[i64] }:$index) => (CPY_ZPmV_S:{ *:[nxv4f32] } ZPR:{ *:[nxv4f32] }:$vec, (CMPEQ_PPzZZ_S:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_S:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_S:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), ?:{ *:[f32] }:$src)
111502 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
111503 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
111504 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
111505 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
111506 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
111507 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
111508 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111509 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(16), // index
111510 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
111511 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
111512 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_S),
111513 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111514 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
111515 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
111516 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_S),
111517 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111518 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
111519 GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
111520 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
111521 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
111522 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111523 GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
111524 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
111525 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_S),
111526 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111527 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
111528 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
111529 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
111530 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
111531 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111532 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_S),
111533 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
111534 GIR_RootToRootCopy, /*OpIdx*/1, // vec
111535 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111536 GIR_RootToRootCopy, /*OpIdx*/2, // src
111537 GIR_RootConstrainSelectedInstOperands,
111538 // GIR_Coverage, 10855,
111539 GIR_EraseRootFromParent_Done,
111540 // Label 6304: @301781
111541 GIM_Reject,
111542 // Label 6298: @301782
111543 GIM_Reject,
111544 // Label 6169: @301783
111545 GIM_Try, /*On fail goto*//*Label 6305*/ GIMT_Encode4(302934),
111546 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
111547 GIM_Try, /*On fail goto*//*Label 6306*/ GIMT_Encode4(301905), // Rule ID 4122 //
111548 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
111549 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
111550 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
111551 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
111552 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
111553 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
111554 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
111555 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
111556 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
111557 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
111558 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
111559 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
111560 GIM_CheckIsSafeToFold, /*NumInsns*/2,
111561 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
111562 // (vector_insert:{ *:[nxv8f16] } immAllZerosV:{ *:[nxv8f16] }, (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
111563 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
111564 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
111565 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111566 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
111567 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
111568 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
111569 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111570 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
111571 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
111572 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
111573 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111574 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
111575 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
111576 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
111577 // GIR_Coverage, 4122,
111578 GIR_EraseRootFromParent_Done,
111579 // Label 6306: @301905
111580 GIM_Try, /*On fail goto*//*Label 6307*/ GIMT_Encode4(302019), // Rule ID 4123 //
111581 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
111582 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
111583 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
111584 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
111585 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
111586 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
111587 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
111588 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
111589 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
111590 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
111591 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
111592 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
111593 GIM_CheckIsSafeToFold, /*NumInsns*/2,
111594 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
111595 // (vector_insert:{ *:[nxv8f16] } immAllZerosV:{ *:[nxv8f16] }, (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
111596 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
111597 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
111598 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111599 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
111600 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
111601 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
111602 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111603 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
111604 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
111605 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
111606 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111607 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
111608 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
111609 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
111610 // GIR_Coverage, 4123,
111611 GIR_EraseRootFromParent_Done,
111612 // Label 6307: @302019
111613 GIM_Try, /*On fail goto*//*Label 6308*/ GIMT_Encode4(302133), // Rule ID 4128 //
111614 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
111615 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
111616 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
111617 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
111618 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
111619 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
111620 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
111621 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
111622 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
111623 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
111624 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
111625 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
111626 GIM_CheckIsSafeToFold, /*NumInsns*/2,
111627 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
111628 // (vector_insert:{ *:[nxv8bf16] } immAllZerosV:{ *:[nxv8bf16] }, (ld:{ *:[bf16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[nxv8bf16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
111629 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
111630 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
111631 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111632 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
111633 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
111634 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
111635 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111636 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
111637 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
111638 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
111639 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111640 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
111641 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
111642 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
111643 // GIR_Coverage, 4128,
111644 GIR_EraseRootFromParent_Done,
111645 // Label 6308: @302133
111646 GIM_Try, /*On fail goto*//*Label 6309*/ GIMT_Encode4(302247), // Rule ID 4129 //
111647 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
111648 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
111649 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
111650 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
111651 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
111652 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
111653 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
111654 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
111655 GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
111656 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
111657 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
111658 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
111659 GIM_CheckIsSafeToFold, /*NumInsns*/2,
111660 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
111661 // (vector_insert:{ *:[nxv8bf16] } immAllZerosV:{ *:[nxv8bf16] }, (ld:{ *:[bf16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[nxv8bf16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
111662 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
111663 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
111664 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111665 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
111666 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
111667 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
111668 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111669 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
111670 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
111671 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
111672 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111673 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
111674 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
111675 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
111676 // GIR_Coverage, 4129,
111677 GIR_EraseRootFromParent_Done,
111678 // Label 6309: @302247
111679 GIM_Try, /*On fail goto*//*Label 6310*/ GIMT_Encode4(302368), // Rule ID 4104 //
111680 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
111681 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
111682 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
111683 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
111684 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
111685 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
111686 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
111687 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
111688 GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
111689 GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
111690 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
111691 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
111692 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
111693 GIM_CheckIsSafeToFold, /*NumInsns*/2,
111694 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
111695 // (vector_insert:{ *:[nxv8i16] } immAllZerosV:{ *:[nxv8i16] }, (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
111696 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
111697 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
111698 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111699 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
111700 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
111701 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
111702 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111703 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
111704 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
111705 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
111706 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111707 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
111708 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
111709 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
111710 // GIR_Coverage, 4104,
111711 GIR_EraseRootFromParent_Done,
111712 // Label 6310: @302368
111713 GIM_Try, /*On fail goto*//*Label 6311*/ GIMT_Encode4(302489), // Rule ID 4105 //
111714 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
111715 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
111716 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
111717 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
111718 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
111719 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
111720 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
111721 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
111722 GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
111723 GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
111724 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
111725 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
111726 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
111727 GIM_CheckIsSafeToFold, /*NumInsns*/2,
111728 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
111729 // (vector_insert:{ *:[nxv8i16] } immAllZerosV:{ *:[nxv8i16] }, (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
111730 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
111731 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
111732 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111733 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
111734 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
111735 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
111736 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111737 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
111738 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
111739 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
111740 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111741 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
111742 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
111743 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
111744 // GIR_Coverage, 4105,
111745 GIR_EraseRootFromParent_Done,
111746 // Label 6311: @302489
111747 GIM_Try, /*On fail goto*//*Label 6312*/ GIMT_Encode4(302637), // Rule ID 10845 //
111748 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
111749 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
111750 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
111751 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
111752 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
111753 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
111754 // (vector_insert:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$vec, GPR32:{ *:[i32] }:$src, GPR64:{ *:[i64] }:$index) => (CPY_ZPmR_H:{ *:[nxv8i16] } ZPR:{ *:[nxv8i16] }:$vec, (CMPEQ_PPzZZ_H:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_H:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_H:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), GPR32:{ *:[i32] }:$src)
111755 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
111756 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
111757 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
111758 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
111759 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
111760 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
111761 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111762 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(16), // index
111763 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
111764 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
111765 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_H),
111766 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111767 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
111768 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
111769 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_H),
111770 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111771 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
111772 GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
111773 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
111774 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
111775 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111776 GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
111777 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
111778 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_H),
111779 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111780 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
111781 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
111782 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
111783 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
111784 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111785 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmR_H),
111786 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
111787 GIR_RootToRootCopy, /*OpIdx*/1, // vec
111788 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111789 GIR_RootToRootCopy, /*OpIdx*/2, // src
111790 GIR_RootConstrainSelectedInstOperands,
111791 // GIR_Coverage, 10845,
111792 GIR_EraseRootFromParent_Done,
111793 // Label 6312: @302637
111794 GIM_Try, /*On fail goto*//*Label 6313*/ GIMT_Encode4(302785), // Rule ID 10850 //
111795 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
111796 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
111797 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
111798 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
111799 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
111800 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
111801 // (vector_insert:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$vec, FPR16:{ *:[f16] }:$src, GPR64:{ *:[i64] }:$index) => (CPY_ZPmV_H:{ *:[nxv8f16] } ZPR:{ *:[nxv8f16] }:$vec, (CMPEQ_PPzZZ_H:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_H:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_H:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), ?:{ *:[f16] }:$src)
111802 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
111803 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
111804 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
111805 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
111806 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
111807 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
111808 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111809 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(16), // index
111810 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
111811 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
111812 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_H),
111813 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111814 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
111815 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
111816 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_H),
111817 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111818 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
111819 GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
111820 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
111821 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
111822 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111823 GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
111824 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
111825 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_H),
111826 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111827 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
111828 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
111829 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
111830 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
111831 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111832 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_H),
111833 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
111834 GIR_RootToRootCopy, /*OpIdx*/1, // vec
111835 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111836 GIR_RootToRootCopy, /*OpIdx*/2, // src
111837 GIR_RootConstrainSelectedInstOperands,
111838 // GIR_Coverage, 10850,
111839 GIR_EraseRootFromParent_Done,
111840 // Label 6313: @302785
111841 GIM_Try, /*On fail goto*//*Label 6314*/ GIMT_Encode4(302933), // Rule ID 10853 //
111842 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
111843 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
111844 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
111845 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
111846 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
111847 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
111848 // (vector_insert:{ *:[nxv8bf16] } nxv8bf16:{ *:[nxv8bf16] }:$vec, FPR16:{ *:[bf16] }:$src, GPR64:{ *:[i64] }:$index) => (CPY_ZPmV_H:{ *:[nxv8bf16] } ZPR:{ *:[nxv8bf16] }:$vec, (CMPEQ_PPzZZ_H:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_H:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_H:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), ?:{ *:[bf16] }:$src)
111849 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
111850 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
111851 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
111852 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
111853 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
111854 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
111855 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111856 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(16), // index
111857 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
111858 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
111859 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_H),
111860 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111861 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
111862 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
111863 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_H),
111864 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111865 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
111866 GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
111867 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
111868 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
111869 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111870 GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
111871 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
111872 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_H),
111873 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111874 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
111875 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
111876 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
111877 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
111878 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111879 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_H),
111880 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
111881 GIR_RootToRootCopy, /*OpIdx*/1, // vec
111882 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111883 GIR_RootToRootCopy, /*OpIdx*/2, // src
111884 GIR_RootConstrainSelectedInstOperands,
111885 // GIR_Coverage, 10853,
111886 GIR_EraseRootFromParent_Done,
111887 // Label 6314: @302933
111888 GIM_Reject,
111889 // Label 6305: @302934
111890 GIM_Reject,
111891 // Label 6170: @302935
111892 GIM_Try, /*On fail goto*//*Label 6315*/ GIMT_Encode4(303314),
111893 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
111894 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
111895 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
111896 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
111897 GIM_Try, /*On fail goto*//*Label 6316*/ GIMT_Encode4(303064), // Rule ID 4098 //
111898 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
111899 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
111900 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
111901 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
111902 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
111903 GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
111904 GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
111905 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
111906 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
111907 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
111908 GIM_CheckIsSafeToFold, /*NumInsns*/2,
111909 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
111910 // (vector_insert:{ *:[nxv16i8] } immAllZerosV:{ *:[nxv16i8] }, (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
111911 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
111912 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
111913 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111914 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
111915 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
111916 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
111917 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111918 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
111919 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
111920 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
111921 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111922 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
111923 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
111924 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
111925 // GIR_Coverage, 4098,
111926 GIR_EraseRootFromParent_Done,
111927 // Label 6316: @303064
111928 GIM_Try, /*On fail goto*//*Label 6317*/ GIMT_Encode4(303175), // Rule ID 4099 //
111929 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
111930 GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
111931 GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
111932 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
111933 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
111934 GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
111935 GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
111936 GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
111937 GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
111938 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
111939 GIM_CheckIsSafeToFold, /*NumInsns*/2,
111940 GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
111941 // (vector_insert:{ *:[nxv16i8] } immAllZerosV:{ *:[nxv16i8] }, (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] }) => (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
111942 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
111943 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
111944 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111945 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
111946 GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
111947 GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
111948 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111949 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
111950 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
111951 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
111952 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111953 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
111954 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
111955 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
111956 // GIR_Coverage, 4099,
111957 GIR_EraseRootFromParent_Done,
111958 // Label 6317: @303175
111959 GIM_Try, /*On fail goto*//*Label 6318*/ GIMT_Encode4(303313), // Rule ID 10844 //
111960 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
111961 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
111962 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
111963 // (vector_insert:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$vec, GPR32:{ *:[i32] }:$src, GPR64:{ *:[i64] }:$index) => (CPY_ZPmR_B:{ *:[nxv16i8] } ZPR:{ *:[nxv16i8] }:$vec, (CMPEQ_PPzZZ_B:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_B:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_B:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_B:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), GPR32:{ *:[i32] }:$src)
111964 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
111965 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
111966 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
111967 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
111968 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
111969 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
111970 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111971 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(16), // index
111972 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
111973 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
111974 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_B),
111975 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111976 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
111977 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
111978 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_B),
111979 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111980 GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
111981 GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
111982 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
111983 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_B),
111984 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111985 GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
111986 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
111987 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_B),
111988 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
111989 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
111990 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
111991 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
111992 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
111993 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
111994 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmR_B),
111995 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
111996 GIR_RootToRootCopy, /*OpIdx*/1, // vec
111997 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
111998 GIR_RootToRootCopy, /*OpIdx*/2, // src
111999 GIR_RootConstrainSelectedInstOperands,
112000 // GIR_Coverage, 10844,
112001 GIR_EraseRootFromParent_Done,
112002 // Label 6318: @303313
112003 GIM_Reject,
112004 // Label 6315: @303314
112005 GIM_Reject,
112006 // Label 6171: @303315
112007 GIM_Reject,
112008 // Label 79: @303316
112009 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 6322*/ GIMT_Encode4(306866),
112010 /*GILLT_s16*//*Label 6319*/ GIMT_Encode4(303339),
112011 /*GILLT_s32*//*Label 6320*/ GIMT_Encode4(304606),
112012 /*GILLT_s64*//*Label 6321*/ GIMT_Encode4(306199),
112013 // Label 6319: @303339
112014 GIM_Try, /*On fail goto*//*Label 6323*/ GIMT_Encode4(303383), // Rule ID 10896 //
112015 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112016 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
112017 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112018 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112019 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
112020 // (vector_extract:{ *:[f16] } nxv8f16:{ *:[nxv8f16] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[f16] } ZPR:{ *:[nxv8f16] }:$Zs, hsub:{ *:[i32] })
112021 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112022 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112023 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Zs
112024 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
112025 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112026 // GIR_Coverage, 10896,
112027 GIR_EraseRootFromParent_Done,
112028 // Label 6323: @303383
112029 GIM_Try, /*On fail goto*//*Label 6324*/ GIMT_Encode4(303427), // Rule ID 10897 //
112030 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112031 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
112032 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112033 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112034 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
112035 // (vector_extract:{ *:[f16] } nxv4f16:{ *:[nxv4f16] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[f16] } ZPR:{ *:[nxv4f16] }:$Zs, hsub:{ *:[i32] })
112036 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112037 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112038 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Zs
112039 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
112040 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112041 // GIR_Coverage, 10897,
112042 GIR_EraseRootFromParent_Done,
112043 // Label 6324: @303427
112044 GIM_Try, /*On fail goto*//*Label 6325*/ GIMT_Encode4(303471), // Rule ID 10898 //
112045 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112046 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
112047 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112048 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112049 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
112050 // (vector_extract:{ *:[f16] } nxv2f16:{ *:[nxv2f16] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[f16] } ZPR:{ *:[nxv2f16] }:$Zs, hsub:{ *:[i32] })
112051 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112052 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112053 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Zs
112054 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
112055 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112056 // GIR_Coverage, 10898,
112057 GIR_EraseRootFromParent_Done,
112058 // Label 6325: @303471
112059 GIM_Try, /*On fail goto*//*Label 6326*/ GIMT_Encode4(303515), // Rule ID 10899 //
112060 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112061 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
112062 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112063 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112064 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
112065 // (vector_extract:{ *:[bf16] } nxv8bf16:{ *:[nxv8bf16] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[bf16] } ZPR:{ *:[nxv8bf16] }:$Zs, hsub:{ *:[i32] })
112066 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112067 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112068 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Zs
112069 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
112070 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112071 // GIR_Coverage, 10899,
112072 GIR_EraseRootFromParent_Done,
112073 // Label 6326: @303515
112074 GIM_Try, /*On fail goto*//*Label 6327*/ GIMT_Encode4(303559), // Rule ID 10900 //
112075 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112076 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
112077 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112078 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112079 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
112080 // (vector_extract:{ *:[bf16] } nxv4bf16:{ *:[nxv4bf16] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[bf16] } ZPR:{ *:[nxv4bf16] }:$Zs, hsub:{ *:[i32] })
112081 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112082 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112083 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Zs
112084 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
112085 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112086 // GIR_Coverage, 10900,
112087 GIR_EraseRootFromParent_Done,
112088 // Label 6327: @303559
112089 GIM_Try, /*On fail goto*//*Label 6328*/ GIMT_Encode4(303603), // Rule ID 10901 //
112090 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112091 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
112092 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112093 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112094 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
112095 // (vector_extract:{ *:[bf16] } nxv2bf16:{ *:[nxv2bf16] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[bf16] } ZPR:{ *:[nxv2bf16] }:$Zs, hsub:{ *:[i32] })
112096 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112097 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112098 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Zs
112099 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
112100 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112101 // GIR_Coverage, 10901,
112102 GIR_EraseRootFromParent_Done,
112103 // Label 6328: @303603
112104 GIM_Try, /*On fail goto*//*Label 6329*/ GIMT_Encode4(303648), // Rule ID 5399 //
112105 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
112106 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112107 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
112108 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
112109 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
112110 // (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] })
112111 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112112 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112113 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
112114 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
112115 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
112116 // GIR_Coverage, 5399,
112117 GIR_EraseRootFromParent_Done,
112118 // Label 6329: @303648
112119 GIM_Try, /*On fail goto*//*Label 6330*/ GIMT_Encode4(303693), // Rule ID 5400 //
112120 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
112121 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112122 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
112123 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
112124 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
112125 // (vector_extract:{ *:[bf16] } V128:{ *:[v8bf16] }:$Rn, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[bf16] } V128:{ *:[v8bf16] }:$Rn, hsub:{ *:[i32] })
112126 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112127 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112128 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
112129 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
112130 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
112131 // GIR_Coverage, 5400,
112132 GIR_EraseRootFromParent_Done,
112133 // Label 6330: @303693
112134 GIM_Try, /*On fail goto*//*Label 6331*/ GIMT_Encode4(303738), // Rule ID 5403 //
112135 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
112136 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112137 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
112138 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
112139 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112140 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112141 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
112142 // MIs[1] Operand 1
112143 // No operand predicates
112144 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112145 // (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) => (DUPi16:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
112146 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPi16),
112147 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112148 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
112149 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
112150 GIR_RootConstrainSelectedInstOperands,
112151 // GIR_Coverage, 5403,
112152 GIR_EraseRootFromParent_Done,
112153 // Label 6331: @303738
112154 GIM_Try, /*On fail goto*//*Label 6332*/ GIMT_Encode4(303783), // Rule ID 5404 //
112155 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
112156 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112157 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
112158 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
112159 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112160 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112161 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
112162 // MIs[1] Operand 1
112163 // No operand predicates
112164 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112165 // (vector_extract:{ *:[bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) => (DUPi16:{ *:[bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
112166 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPi16),
112167 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112168 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
112169 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
112170 GIR_RootConstrainSelectedInstOperands,
112171 // GIR_Coverage, 5404,
112172 GIR_EraseRootFromParent_Done,
112173 // Label 6332: @303783
112174 GIM_Try, /*On fail goto*//*Label 6333*/ GIMT_Encode4(303859), // Rule ID 10874 //
112175 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112176 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
112177 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112178 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112179 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112180 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112181 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_h),
112182 // MIs[1] Operand 1
112183 // No operand predicates
112184 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112185 // (vector_extract:{ *:[f16] } nxv8f16:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index) => (EXTRACT_SUBREG:{ *:[f16] } (DUP_ZZI_H:{ *:[nxv16i8] } ZPR:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index), hsub:{ *:[i32] })
112186 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
112187 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
112188 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112189 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
112190 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
112191 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112192 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112193 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112194 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
112195 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
112196 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112197 // GIR_Coverage, 10874,
112198 GIR_EraseRootFromParent_Done,
112199 // Label 6333: @303859
112200 GIM_Try, /*On fail goto*//*Label 6334*/ GIMT_Encode4(303935), // Rule ID 10875 //
112201 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112202 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
112203 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112204 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112205 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112206 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112207 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
112208 // MIs[1] Operand 1
112209 // No operand predicates
112210 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112211 // (vector_extract:{ *:[f16] } nxv4f16:{ *:[nxv4f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index) => (EXTRACT_SUBREG:{ *:[f16] } (DUP_ZZI_S:{ *:[nxv16i8] } ZPR:{ *:[nxv4f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index), hsub:{ *:[i32] })
112212 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
112213 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
112214 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112215 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
112216 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
112217 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112218 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112219 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112220 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
112221 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
112222 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112223 // GIR_Coverage, 10875,
112224 GIR_EraseRootFromParent_Done,
112225 // Label 6334: @303935
112226 GIM_Try, /*On fail goto*//*Label 6335*/ GIMT_Encode4(304011), // Rule ID 10876 //
112227 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112228 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
112229 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112230 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112231 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112232 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112233 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
112234 // MIs[1] Operand 1
112235 // No operand predicates
112236 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112237 // (vector_extract:{ *:[f16] } nxv2f16:{ *:[nxv2f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index) => (EXTRACT_SUBREG:{ *:[f16] } (DUP_ZZI_D:{ *:[nxv16i8] } ZPR:{ *:[nxv2f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index), hsub:{ *:[i32] })
112238 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
112239 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
112240 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112241 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
112242 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
112243 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112244 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112245 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112246 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
112247 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
112248 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112249 // GIR_Coverage, 10876,
112250 GIR_EraseRootFromParent_Done,
112251 // Label 6335: @304011
112252 GIM_Try, /*On fail goto*//*Label 6336*/ GIMT_Encode4(304087), // Rule ID 10877 //
112253 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112254 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
112255 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112256 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112257 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112258 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112259 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_h),
112260 // MIs[1] Operand 1
112261 // No operand predicates
112262 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112263 // (vector_extract:{ *:[bf16] } nxv8bf16:{ *:[nxv8bf16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index) => (EXTRACT_SUBREG:{ *:[bf16] } (DUP_ZZI_H:{ *:[nxv16i8] } ZPR:{ *:[nxv8bf16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index), hsub:{ *:[i32] })
112264 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
112265 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
112266 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112267 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
112268 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
112269 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112270 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112271 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112272 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
112273 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
112274 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112275 // GIR_Coverage, 10877,
112276 GIR_EraseRootFromParent_Done,
112277 // Label 6336: @304087
112278 GIM_Try, /*On fail goto*//*Label 6337*/ GIMT_Encode4(304163), // Rule ID 10878 //
112279 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112280 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
112281 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112282 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112283 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112284 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112285 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
112286 // MIs[1] Operand 1
112287 // No operand predicates
112288 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112289 // (vector_extract:{ *:[bf16] } nxv4bf16:{ *:[nxv4bf16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index) => (EXTRACT_SUBREG:{ *:[bf16] } (DUP_ZZI_S:{ *:[nxv16i8] } ZPR:{ *:[nxv4bf16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index), hsub:{ *:[i32] })
112290 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
112291 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
112292 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112293 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
112294 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
112295 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112296 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112297 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112298 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
112299 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
112300 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112301 // GIR_Coverage, 10878,
112302 GIR_EraseRootFromParent_Done,
112303 // Label 6337: @304163
112304 GIM_Try, /*On fail goto*//*Label 6338*/ GIMT_Encode4(304239), // Rule ID 10879 //
112305 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112306 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
112307 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112308 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112309 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112310 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112311 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
112312 // MIs[1] Operand 1
112313 // No operand predicates
112314 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112315 // (vector_extract:{ *:[bf16] } nxv2bf16:{ *:[nxv2bf16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index) => (EXTRACT_SUBREG:{ *:[bf16] } (DUP_ZZI_D:{ *:[nxv16i8] } ZPR:{ *:[nxv2bf16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index), hsub:{ *:[i32] })
112316 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
112317 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
112318 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112319 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
112320 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
112321 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112322 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112323 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112324 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
112325 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
112326 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112327 // GIR_Coverage, 10879,
112328 GIR_EraseRootFromParent_Done,
112329 // Label 6338: @304239
112330 GIM_Try, /*On fail goto*//*Label 6339*/ GIMT_Encode4(304300), // Rule ID 10861 //
112331 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112332 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
112333 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112334 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
112335 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
112336 // (vector_extract:{ *:[f16] } nxv8f16:{ *:[nxv8f16] }:$vec, GPR64:{ *:[i64] }:$index) => (LASTB_VPZ_H:{ *:[f16] } (WHILELS_PXX_H:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv8f16] }:$vec)
112337 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
112338 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_H),
112339 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112340 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
112341 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
112342 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
112343 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112344 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_H),
112345 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
112346 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
112347 GIR_RootToRootCopy, /*OpIdx*/1, // vec
112348 GIR_RootConstrainSelectedInstOperands,
112349 // GIR_Coverage, 10861,
112350 GIR_EraseRootFromParent_Done,
112351 // Label 6339: @304300
112352 GIM_Try, /*On fail goto*//*Label 6340*/ GIMT_Encode4(304361), // Rule ID 10862 //
112353 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112354 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
112355 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112356 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
112357 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
112358 // (vector_extract:{ *:[f16] } nxv4f16:{ *:[nxv4f16] }:$vec, GPR64:{ *:[i64] }:$index) => (LASTB_VPZ_H:{ *:[f16] } (WHILELS_PXX_S:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv4f16] }:$vec)
112359 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
112360 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_S),
112361 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112362 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
112363 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
112364 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
112365 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112366 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_H),
112367 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
112368 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
112369 GIR_RootToRootCopy, /*OpIdx*/1, // vec
112370 GIR_RootConstrainSelectedInstOperands,
112371 // GIR_Coverage, 10862,
112372 GIR_EraseRootFromParent_Done,
112373 // Label 6340: @304361
112374 GIM_Try, /*On fail goto*//*Label 6341*/ GIMT_Encode4(304422), // Rule ID 10863 //
112375 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112376 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
112377 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112378 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
112379 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
112380 // (vector_extract:{ *:[f16] } nxv2f16:{ *:[nxv2f16] }:$vec, GPR64:{ *:[i64] }:$index) => (LASTB_VPZ_H:{ *:[f16] } (WHILELS_PXX_D:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv2f16] }:$vec)
112381 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
112382 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_D),
112383 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112384 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
112385 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
112386 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
112387 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112388 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_H),
112389 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
112390 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
112391 GIR_RootToRootCopy, /*OpIdx*/1, // vec
112392 GIR_RootConstrainSelectedInstOperands,
112393 // GIR_Coverage, 10863,
112394 GIR_EraseRootFromParent_Done,
112395 // Label 6341: @304422
112396 GIM_Try, /*On fail goto*//*Label 6342*/ GIMT_Encode4(304483), // Rule ID 10864 //
112397 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112398 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
112399 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112400 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
112401 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
112402 // (vector_extract:{ *:[bf16] } nxv8bf16:{ *:[nxv8bf16] }:$vec, GPR64:{ *:[i64] }:$index) => (LASTB_VPZ_H:{ *:[bf16] } (WHILELS_PXX_H:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv8bf16] }:$vec)
112403 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
112404 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_H),
112405 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112406 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
112407 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
112408 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
112409 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112410 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_H),
112411 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
112412 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
112413 GIR_RootToRootCopy, /*OpIdx*/1, // vec
112414 GIR_RootConstrainSelectedInstOperands,
112415 // GIR_Coverage, 10864,
112416 GIR_EraseRootFromParent_Done,
112417 // Label 6342: @304483
112418 GIM_Try, /*On fail goto*//*Label 6343*/ GIMT_Encode4(304544), // Rule ID 10865 //
112419 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112420 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
112421 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112422 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
112423 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
112424 // (vector_extract:{ *:[bf16] } nxv4bf16:{ *:[nxv4bf16] }:$vec, GPR64:{ *:[i64] }:$index) => (LASTB_VPZ_H:{ *:[bf16] } (WHILELS_PXX_S:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv4bf16] }:$vec)
112425 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
112426 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_S),
112427 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112428 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
112429 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
112430 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
112431 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112432 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_H),
112433 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
112434 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
112435 GIR_RootToRootCopy, /*OpIdx*/1, // vec
112436 GIR_RootConstrainSelectedInstOperands,
112437 // GIR_Coverage, 10865,
112438 GIR_EraseRootFromParent_Done,
112439 // Label 6343: @304544
112440 GIM_Try, /*On fail goto*//*Label 6344*/ GIMT_Encode4(304605), // Rule ID 10866 //
112441 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112442 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
112443 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112444 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
112445 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
112446 // (vector_extract:{ *:[bf16] } nxv2bf16:{ *:[nxv2bf16] }:$vec, GPR64:{ *:[i64] }:$index) => (LASTB_VPZ_H:{ *:[bf16] } (WHILELS_PXX_D:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv2bf16] }:$vec)
112447 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
112448 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_D),
112449 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112450 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
112451 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
112452 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
112453 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112454 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_H),
112455 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
112456 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
112457 GIR_RootToRootCopy, /*OpIdx*/1, // vec
112458 GIR_RootConstrainSelectedInstOperands,
112459 // GIR_Coverage, 10866,
112460 GIR_EraseRootFromParent_Done,
112461 // Label 6344: @304605
112462 GIM_Reject,
112463 // Label 6320: @304606
112464 GIM_Try, /*On fail goto*//*Label 6345*/ GIMT_Encode4(304651), // Rule ID 6648 //
112465 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
112466 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112467 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
112468 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
112469 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
112470 // (extractelt:{ *:[i32] } V128:{ *:[v4i32] }:$V, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4i32] }:$V, ssub:{ *:[i32] })
112471 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112472 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112473 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // V
112474 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
112475 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
112476 // GIR_Coverage, 6648,
112477 GIR_EraseRootFromParent_Done,
112478 // Label 6345: @304651
112479 GIM_Try, /*On fail goto*//*Label 6346*/ GIMT_Encode4(304696), // Rule ID 6649 //
112480 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
112481 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112482 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
112483 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
112484 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
112485 // (extractelt:{ *:[i32] } V64:{ *:[v2i32] }:$V, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[i32] } V64:{ *:[v2i32] }:$V, ssub:{ *:[i32] })
112486 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112487 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112488 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // V
112489 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
112490 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
112491 // GIR_Coverage, 6649,
112492 GIR_EraseRootFromParent_Done,
112493 // Label 6346: @304696
112494 GIM_Try, /*On fail goto*//*Label 6347*/ GIMT_Encode4(304740), // Rule ID 10892 //
112495 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112496 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
112497 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112498 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112499 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
112500 // (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[i32] } ZPR:{ *:[nxv16i8] }:$Zs, ssub:{ *:[i32] })
112501 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112502 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112503 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Zs
112504 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
112505 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112506 // GIR_Coverage, 10892,
112507 GIR_EraseRootFromParent_Done,
112508 // Label 6347: @304740
112509 GIM_Try, /*On fail goto*//*Label 6348*/ GIMT_Encode4(304784), // Rule ID 10893 //
112510 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112511 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
112512 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112513 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112514 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
112515 // (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[i32] } ZPR:{ *:[nxv8i16] }:$Zs, ssub:{ *:[i32] })
112516 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112517 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112518 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Zs
112519 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
112520 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112521 // GIR_Coverage, 10893,
112522 GIR_EraseRootFromParent_Done,
112523 // Label 6348: @304784
112524 GIM_Try, /*On fail goto*//*Label 6349*/ GIMT_Encode4(304828), // Rule ID 10894 //
112525 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112526 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
112527 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112528 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112529 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
112530 // (vector_extract:{ *:[i32] } nxv4i32:{ *:[nxv4i32] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[i32] } ZPR:{ *:[nxv4i32] }:$Zs, ssub:{ *:[i32] })
112531 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112532 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112533 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Zs
112534 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
112535 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112536 // GIR_Coverage, 10894,
112537 GIR_EraseRootFromParent_Done,
112538 // Label 6349: @304828
112539 GIM_Try, /*On fail goto*//*Label 6350*/ GIMT_Encode4(304872), // Rule ID 10902 //
112540 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112541 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
112542 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112543 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112544 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
112545 // (vector_extract:{ *:[f32] } nxv4f32:{ *:[nxv4f32] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[f32] } ZPR:{ *:[nxv4f32] }:$Zs, ssub:{ *:[i32] })
112546 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112547 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112548 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Zs
112549 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
112550 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112551 // GIR_Coverage, 10902,
112552 GIR_EraseRootFromParent_Done,
112553 // Label 6350: @304872
112554 GIM_Try, /*On fail goto*//*Label 6351*/ GIMT_Encode4(304916), // Rule ID 10903 //
112555 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112556 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
112557 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112558 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112559 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
112560 // (vector_extract:{ *:[f32] } nxv2f32:{ *:[nxv2f32] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[f32] } ZPR:{ *:[nxv2f32] }:$Zs, ssub:{ *:[i32] })
112561 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112562 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112563 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Zs
112564 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
112565 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112566 // GIR_Coverage, 10903,
112567 GIR_EraseRootFromParent_Done,
112568 // Label 6351: @304916
112569 GIM_Try, /*On fail goto*//*Label 6352*/ GIMT_Encode4(304961), // Rule ID 5398 //
112570 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
112571 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112572 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
112573 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
112574 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
112575 // (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] })
112576 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112577 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112578 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rn
112579 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
112580 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
112581 // GIR_Coverage, 5398,
112582 GIR_EraseRootFromParent_Done,
112583 // Label 6352: @304961
112584 GIM_Try, /*On fail goto*//*Label 6353*/ GIMT_Encode4(305034), // Rule ID 10883 //
112585 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
112586 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
112587 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112588 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
112589 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112590 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112591 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
112592 // MIs[1] Operand 1
112593 // No operand predicates
112594 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112595 // (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$index) => (UMOVvi8:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v16i8] } ZPR:{ *:[nxv16i8] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$index)
112596 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
112597 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112598 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112599 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(38), // vec
112600 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
112601 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112602 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi8),
112603 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
112604 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
112605 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // index
112606 GIR_RootConstrainSelectedInstOperands,
112607 // GIR_Coverage, 10883,
112608 GIR_EraseRootFromParent_Done,
112609 // Label 6353: @305034
112610 GIM_Try, /*On fail goto*//*Label 6354*/ GIMT_Encode4(305107), // Rule ID 10884 //
112611 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
112612 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
112613 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112614 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
112615 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112616 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112617 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
112618 // MIs[1] Operand 1
112619 // No operand predicates
112620 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112621 // (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$index) => (UMOVvi16:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v8i16] } ZPR:{ *:[nxv8i16] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$index)
112622 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
112623 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112624 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112625 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(38), // vec
112626 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
112627 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112628 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi16),
112629 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
112630 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
112631 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // index
112632 GIR_RootConstrainSelectedInstOperands,
112633 // GIR_Coverage, 10884,
112634 GIR_EraseRootFromParent_Done,
112635 // Label 6354: @305107
112636 GIM_Try, /*On fail goto*//*Label 6355*/ GIMT_Encode4(305180), // Rule ID 10885 //
112637 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
112638 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
112639 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112640 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
112641 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112642 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112643 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
112644 // MIs[1] Operand 1
112645 // No operand predicates
112646 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112647 // (vector_extract:{ *:[i32] } nxv4i32:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$index) => (UMOVvi32:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v4i32] } ZPR:{ *:[nxv4i32] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$index)
112648 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
112649 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112650 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112651 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(38), // vec
112652 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
112653 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112654 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi32),
112655 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
112656 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
112657 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // index
112658 GIR_RootConstrainSelectedInstOperands,
112659 // GIR_Coverage, 10885,
112660 GIR_EraseRootFromParent_Done,
112661 // Label 6355: @305180
112662 GIM_Try, /*On fail goto*//*Label 6356*/ GIMT_Encode4(305228), // Rule ID 1913 //
112663 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
112664 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
112665 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112666 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
112667 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
112668 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112669 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112670 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndex0),
112671 // MIs[1] Operand 1
112672 // No operand predicates
112673 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112674 // (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndex0>>:$idx) => (UMOVvi8_idx0:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx)
112675 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi8_idx0),
112676 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
112677 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
112678 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
112679 GIR_RootConstrainSelectedInstOperands,
112680 // GIR_Coverage, 1913,
112681 GIR_EraseRootFromParent_Done,
112682 // Label 6356: @305228
112683 GIM_Try, /*On fail goto*//*Label 6357*/ GIMT_Encode4(305276), // Rule ID 1914 //
112684 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
112685 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
112686 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112687 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
112688 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
112689 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112690 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112691 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndex0),
112692 // MIs[1] Operand 1
112693 // No operand predicates
112694 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112695 // (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndex0>>:$idx) => (UMOVvi16_idx0:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx)
112696 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi16_idx0),
112697 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
112698 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
112699 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
112700 GIR_RootConstrainSelectedInstOperands,
112701 // GIR_Coverage, 1914,
112702 GIR_EraseRootFromParent_Done,
112703 // Label 6357: @305276
112704 GIM_Try, /*On fail goto*//*Label 6358*/ GIMT_Encode4(305324), // Rule ID 1915 //
112705 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
112706 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
112707 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112708 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
112709 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
112710 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112711 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112712 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndex0),
112713 // MIs[1] Operand 1
112714 // No operand predicates
112715 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112716 // (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndex0>>:$idx) => (UMOVvi32_idx0:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx)
112717 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi32_idx0),
112718 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
112719 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
112720 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
112721 GIR_RootConstrainSelectedInstOperands,
112722 // GIR_Coverage, 1915,
112723 GIR_EraseRootFromParent_Done,
112724 // Label 6358: @305324
112725 GIM_Try, /*On fail goto*//*Label 6359*/ GIMT_Encode4(305372), // Rule ID 1917 //
112726 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
112727 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
112728 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112729 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
112730 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
112731 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112732 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112733 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
112734 // MIs[1] Operand 1
112735 // No operand predicates
112736 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112737 // (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx) => (UMOVvi8:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx)
112738 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi8),
112739 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
112740 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
112741 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
112742 GIR_RootConstrainSelectedInstOperands,
112743 // GIR_Coverage, 1917,
112744 GIR_EraseRootFromParent_Done,
112745 // Label 6359: @305372
112746 GIM_Try, /*On fail goto*//*Label 6360*/ GIMT_Encode4(305420), // Rule ID 1918 //
112747 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
112748 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
112749 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112750 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
112751 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
112752 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112753 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112754 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
112755 // MIs[1] Operand 1
112756 // No operand predicates
112757 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112758 // (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) => (UMOVvi16:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx)
112759 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi16),
112760 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
112761 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
112762 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
112763 GIR_RootConstrainSelectedInstOperands,
112764 // GIR_Coverage, 1918,
112765 GIR_EraseRootFromParent_Done,
112766 // Label 6360: @305420
112767 GIM_Try, /*On fail goto*//*Label 6361*/ GIMT_Encode4(305468), // Rule ID 1919 //
112768 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
112769 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
112770 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112771 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
112772 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
112773 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112774 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112775 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
112776 // MIs[1] Operand 1
112777 // No operand predicates
112778 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112779 // (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) => (UMOVvi32:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx)
112780 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi32),
112781 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
112782 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
112783 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
112784 GIR_RootConstrainSelectedInstOperands,
112785 // GIR_Coverage, 1919,
112786 GIR_EraseRootFromParent_Done,
112787 // Label 6361: @305468
112788 GIM_Try, /*On fail goto*//*Label 6362*/ GIMT_Encode4(305513), // Rule ID 5402 //
112789 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
112790 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112791 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
112792 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
112793 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112794 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112795 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
112796 // MIs[1] Operand 1
112797 // No operand predicates
112798 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112799 // (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) => (DUPi32:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
112800 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPi32),
112801 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112802 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
112803 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
112804 GIR_RootConstrainSelectedInstOperands,
112805 // GIR_Coverage, 5402,
112806 GIR_EraseRootFromParent_Done,
112807 // Label 6362: @305513
112808 GIM_Try, /*On fail goto*//*Label 6363*/ GIMT_Encode4(305589), // Rule ID 10870 //
112809 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112810 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
112811 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112812 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112813 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112814 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112815 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_b),
112816 // MIs[1] Operand 1
112817 // No operand predicates
112818 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112819 // (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_b>>:$index) => (EXTRACT_SUBREG:{ *:[i32] } (DUP_ZZI_B:{ *:[nxv16i8] } ZPR:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_b>>:$index), ssub:{ *:[i32] })
112820 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
112821 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_B),
112822 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112823 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
112824 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
112825 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112826 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112827 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112828 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
112829 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
112830 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112831 // GIR_Coverage, 10870,
112832 GIR_EraseRootFromParent_Done,
112833 // Label 6363: @305589
112834 GIM_Try, /*On fail goto*//*Label 6364*/ GIMT_Encode4(305665), // Rule ID 10871 //
112835 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112836 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
112837 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112838 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112839 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112840 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112841 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_h),
112842 // MIs[1] Operand 1
112843 // No operand predicates
112844 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112845 // (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index) => (EXTRACT_SUBREG:{ *:[i32] } (DUP_ZZI_H:{ *:[nxv16i8] } ZPR:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index), ssub:{ *:[i32] })
112846 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
112847 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
112848 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112849 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
112850 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
112851 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112852 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112853 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112854 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
112855 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
112856 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112857 // GIR_Coverage, 10871,
112858 GIR_EraseRootFromParent_Done,
112859 // Label 6364: @305665
112860 GIM_Try, /*On fail goto*//*Label 6365*/ GIMT_Encode4(305741), // Rule ID 10872 //
112861 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112862 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
112863 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112864 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112865 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112866 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112867 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
112868 // MIs[1] Operand 1
112869 // No operand predicates
112870 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112871 // (vector_extract:{ *:[i32] } nxv4i32:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index) => (EXTRACT_SUBREG:{ *:[i32] } (DUP_ZZI_S:{ *:[nxv16i8] } ZPR:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index), ssub:{ *:[i32] })
112872 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
112873 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
112874 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112875 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
112876 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
112877 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112878 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112879 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112880 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
112881 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
112882 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112883 // GIR_Coverage, 10872,
112884 GIR_EraseRootFromParent_Done,
112885 // Label 6365: @305741
112886 GIM_Try, /*On fail goto*//*Label 6366*/ GIMT_Encode4(305817), // Rule ID 10880 //
112887 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112888 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
112889 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112890 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112891 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112892 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112893 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
112894 // MIs[1] Operand 1
112895 // No operand predicates
112896 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112897 // (vector_extract:{ *:[f32] } nxv4f32:{ *:[nxv4f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index) => (EXTRACT_SUBREG:{ *:[f32] } (DUP_ZZI_S:{ *:[nxv16i8] } ZPR:{ *:[nxv4f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index), ssub:{ *:[i32] })
112898 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
112899 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
112900 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112901 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
112902 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
112903 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112904 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112905 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112906 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
112907 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
112908 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112909 // GIR_Coverage, 10880,
112910 GIR_EraseRootFromParent_Done,
112911 // Label 6366: @305817
112912 GIM_Try, /*On fail goto*//*Label 6367*/ GIMT_Encode4(305893), // Rule ID 10881 //
112913 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112914 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
112915 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112916 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
112917 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
112918 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
112919 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
112920 // MIs[1] Operand 1
112921 // No operand predicates
112922 GIM_CheckIsSafeToFold, /*NumInsns*/1,
112923 // (vector_extract:{ *:[f32] } nxv2f32:{ *:[nxv2f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index) => (EXTRACT_SUBREG:{ *:[f32] } (DUP_ZZI_D:{ *:[nxv16i8] } ZPR:{ *:[nxv2f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index), ssub:{ *:[i32] })
112924 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
112925 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
112926 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112927 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
112928 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
112929 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112930 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
112931 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
112932 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
112933 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
112934 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
112935 // GIR_Coverage, 10881,
112936 GIR_EraseRootFromParent_Done,
112937 // Label 6367: @305893
112938 GIM_Try, /*On fail goto*//*Label 6368*/ GIMT_Encode4(305954), // Rule ID 10857 //
112939 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112940 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
112941 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112942 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
112943 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
112944 // (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$vec, GPR64:{ *:[i64] }:$index) => (LASTB_RPZ_B:{ *:[i32] } (WHILELS_PXX_B:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv16i8] }:$vec)
112945 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
112946 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_B),
112947 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112948 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
112949 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
112950 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
112951 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112952 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_RPZ_B),
112953 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
112954 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
112955 GIR_RootToRootCopy, /*OpIdx*/1, // vec
112956 GIR_RootConstrainSelectedInstOperands,
112957 // GIR_Coverage, 10857,
112958 GIR_EraseRootFromParent_Done,
112959 // Label 6368: @305954
112960 GIM_Try, /*On fail goto*//*Label 6369*/ GIMT_Encode4(306015), // Rule ID 10858 //
112961 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112962 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
112963 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112964 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
112965 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
112966 // (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$vec, GPR64:{ *:[i64] }:$index) => (LASTB_RPZ_H:{ *:[i32] } (WHILELS_PXX_H:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv8i16] }:$vec)
112967 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
112968 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_H),
112969 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112970 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
112971 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
112972 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
112973 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112974 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_RPZ_H),
112975 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
112976 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
112977 GIR_RootToRootCopy, /*OpIdx*/1, // vec
112978 GIR_RootConstrainSelectedInstOperands,
112979 // GIR_Coverage, 10858,
112980 GIR_EraseRootFromParent_Done,
112981 // Label 6369: @306015
112982 GIM_Try, /*On fail goto*//*Label 6370*/ GIMT_Encode4(306076), // Rule ID 10859 //
112983 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
112984 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
112985 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
112986 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
112987 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
112988 // (vector_extract:{ *:[i32] } nxv4i32:{ *:[nxv4i32] }:$vec, GPR64:{ *:[i64] }:$index) => (LASTB_RPZ_S:{ *:[i32] } (WHILELS_PXX_S:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv4i32] }:$vec)
112989 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
112990 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_S),
112991 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
112992 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
112993 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
112994 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
112995 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
112996 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_RPZ_S),
112997 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
112998 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
112999 GIR_RootToRootCopy, /*OpIdx*/1, // vec
113000 GIR_RootConstrainSelectedInstOperands,
113001 // GIR_Coverage, 10859,
113002 GIR_EraseRootFromParent_Done,
113003 // Label 6370: @306076
113004 GIM_Try, /*On fail goto*//*Label 6371*/ GIMT_Encode4(306137), // Rule ID 10867 //
113005 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
113006 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
113007 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
113008 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
113009 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113010 // (vector_extract:{ *:[f32] } nxv4f32:{ *:[nxv4f32] }:$vec, GPR64:{ *:[i64] }:$index) => (LASTB_VPZ_S:{ *:[f32] } (WHILELS_PXX_S:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv4f32] }:$vec)
113011 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
113012 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_S),
113013 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
113014 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
113015 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
113016 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
113017 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
113018 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_S),
113019 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
113020 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
113021 GIR_RootToRootCopy, /*OpIdx*/1, // vec
113022 GIR_RootConstrainSelectedInstOperands,
113023 // GIR_Coverage, 10867,
113024 GIR_EraseRootFromParent_Done,
113025 // Label 6371: @306137
113026 GIM_Try, /*On fail goto*//*Label 6372*/ GIMT_Encode4(306198), // Rule ID 10868 //
113027 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
113028 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
113029 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
113030 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
113031 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113032 // (vector_extract:{ *:[f32] } nxv2f32:{ *:[nxv2f32] }:$vec, GPR64:{ *:[i64] }:$index) => (LASTB_VPZ_S:{ *:[f32] } (WHILELS_PXX_D:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv2f32] }:$vec)
113033 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
113034 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_D),
113035 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
113036 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
113037 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
113038 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
113039 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
113040 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_S),
113041 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
113042 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
113043 GIR_RootToRootCopy, /*OpIdx*/1, // vec
113044 GIR_RootConstrainSelectedInstOperands,
113045 // GIR_Coverage, 10868,
113046 GIR_EraseRootFromParent_Done,
113047 // Label 6372: @306198
113048 GIM_Reject,
113049 // Label 6321: @306199
113050 GIM_Try, /*On fail goto*//*Label 6373*/ GIMT_Encode4(306244), // Rule ID 6647 //
113051 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
113052 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
113053 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113054 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113055 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
113056 // (extractelt:{ *:[i64] } V128:{ *:[v2i64] }:$V, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2i64] }:$V, dsub:{ *:[i32] })
113057 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
113058 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
113059 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // V
113060 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
113061 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
113062 // GIR_Coverage, 6647,
113063 GIR_EraseRootFromParent_Done,
113064 // Label 6373: @306244
113065 GIM_Try, /*On fail goto*//*Label 6374*/ GIMT_Encode4(306288), // Rule ID 10895 //
113066 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
113067 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
113068 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
113069 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
113070 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
113071 // (vector_extract:{ *:[i64] } nxv2i64:{ *:[nxv2i64] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[i64] } ZPR:{ *:[nxv2i64] }:$Zs, dsub:{ *:[i32] })
113072 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
113073 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
113074 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Zs
113075 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
113076 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
113077 // GIR_Coverage, 10895,
113078 GIR_EraseRootFromParent_Done,
113079 // Label 6374: @306288
113080 GIM_Try, /*On fail goto*//*Label 6375*/ GIMT_Encode4(306332), // Rule ID 10904 //
113081 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
113082 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
113083 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
113084 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
113085 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
113086 // (vector_extract:{ *:[f64] } nxv2f64:{ *:[nxv2f64] }:$Zs, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[f64] } ZPR:{ *:[nxv2f64] }:$Zs, dsub:{ *:[i32] })
113087 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
113088 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
113089 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Zs
113090 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
113091 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
113092 // GIR_Coverage, 10904,
113093 GIR_EraseRootFromParent_Done,
113094 // Label 6375: @306332
113095 GIM_Try, /*On fail goto*//*Label 6376*/ GIMT_Encode4(306377), // Rule ID 5397 //
113096 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
113097 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
113098 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113099 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113100 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
113101 // (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }) => (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] })
113102 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
113103 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
113104 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
113105 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
113106 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
113107 // GIR_Coverage, 5397,
113108 GIR_EraseRootFromParent_Done,
113109 // Label 6376: @306377
113110 GIM_Try, /*On fail goto*//*Label 6377*/ GIMT_Encode4(306450), // Rule ID 10886 //
113111 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
113112 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
113113 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
113114 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113115 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
113116 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
113117 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
113118 // MIs[1] Operand 1
113119 // No operand predicates
113120 GIM_CheckIsSafeToFold, /*NumInsns*/1,
113121 // (vector_extract:{ *:[i64] } nxv2i64:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$index) => (UMOVvi64:{ *:[i64] } (EXTRACT_SUBREG:{ *:[v2i64] } ZPR:{ *:[nxv2i64] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$index)
113122 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
113123 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
113124 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
113125 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(38), // vec
113126 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
113127 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
113128 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi64),
113129 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
113130 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
113131 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // index
113132 GIR_RootConstrainSelectedInstOperands,
113133 // GIR_Coverage, 10886,
113134 GIR_EraseRootFromParent_Done,
113135 // Label 6377: @306450
113136 GIM_Try, /*On fail goto*//*Label 6378*/ GIMT_Encode4(306498), // Rule ID 1916 //
113137 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
113138 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
113139 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
113140 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113141 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113142 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
113143 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
113144 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndex0),
113145 // MIs[1] Operand 1
113146 // No operand predicates
113147 GIM_CheckIsSafeToFold, /*NumInsns*/1,
113148 // (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndex0>>:$idx) => (UMOVvi64_idx0:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$idx)
113149 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi64_idx0),
113150 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
113151 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
113152 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
113153 GIR_RootConstrainSelectedInstOperands,
113154 // GIR_Coverage, 1916,
113155 GIR_EraseRootFromParent_Done,
113156 // Label 6378: @306498
113157 GIM_Try, /*On fail goto*//*Label 6379*/ GIMT_Encode4(306546), // Rule ID 1920 //
113158 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
113159 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
113160 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
113161 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113162 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113163 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
113164 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
113165 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
113166 // MIs[1] Operand 1
113167 // No operand predicates
113168 GIM_CheckIsSafeToFold, /*NumInsns*/1,
113169 // (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx) => (UMOVvi64:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$idx)
113170 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi64),
113171 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
113172 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
113173 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
113174 GIR_RootConstrainSelectedInstOperands,
113175 // GIR_Coverage, 1920,
113176 GIR_EraseRootFromParent_Done,
113177 // Label 6379: @306546
113178 GIM_Try, /*On fail goto*//*Label 6380*/ GIMT_Encode4(306591), // Rule ID 5401 //
113179 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
113180 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
113181 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113182 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113183 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
113184 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
113185 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
113186 // MIs[1] Operand 1
113187 // No operand predicates
113188 GIM_CheckIsSafeToFold, /*NumInsns*/1,
113189 // (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx) => (DUPi64:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
113190 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPi64),
113191 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
113192 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
113193 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
113194 GIR_RootConstrainSelectedInstOperands,
113195 // GIR_Coverage, 5401,
113196 GIR_EraseRootFromParent_Done,
113197 // Label 6380: @306591
113198 GIM_Try, /*On fail goto*//*Label 6381*/ GIMT_Encode4(306667), // Rule ID 10873 //
113199 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
113200 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
113201 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
113202 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
113203 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
113204 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
113205 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
113206 // MIs[1] Operand 1
113207 // No operand predicates
113208 GIM_CheckIsSafeToFold, /*NumInsns*/1,
113209 // (vector_extract:{ *:[i64] } nxv2i64:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index) => (EXTRACT_SUBREG:{ *:[i64] } (DUP_ZZI_D:{ *:[nxv16i8] } ZPR:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index), dsub:{ *:[i32] })
113210 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
113211 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
113212 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
113213 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
113214 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
113215 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
113216 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
113217 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
113218 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
113219 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
113220 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
113221 // GIR_Coverage, 10873,
113222 GIR_EraseRootFromParent_Done,
113223 // Label 6381: @306667
113224 GIM_Try, /*On fail goto*//*Label 6382*/ GIMT_Encode4(306743), // Rule ID 10882 //
113225 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
113226 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
113227 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
113228 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
113229 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
113230 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
113231 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
113232 // MIs[1] Operand 1
113233 // No operand predicates
113234 GIM_CheckIsSafeToFold, /*NumInsns*/1,
113235 // (vector_extract:{ *:[f64] } nxv2f64:{ *:[nxv2f64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index) => (EXTRACT_SUBREG:{ *:[f64] } (DUP_ZZI_D:{ *:[nxv16i8] } ZPR:{ *:[nxv2f64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index), dsub:{ *:[i32] })
113236 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
113237 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
113238 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
113239 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
113240 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
113241 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
113242 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
113243 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
113244 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
113245 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
113246 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
113247 // GIR_Coverage, 10882,
113248 GIR_EraseRootFromParent_Done,
113249 // Label 6382: @306743
113250 GIM_Try, /*On fail goto*//*Label 6383*/ GIMT_Encode4(306804), // Rule ID 10860 //
113251 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
113252 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
113253 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
113254 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113255 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113256 // (vector_extract:{ *:[i64] } nxv2i64:{ *:[nxv2i64] }:$vec, GPR64:{ *:[i64] }:$index) => (LASTB_RPZ_D:{ *:[i64] } (WHILELS_PXX_D:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv2i64] }:$vec)
113257 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
113258 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_D),
113259 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
113260 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
113261 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
113262 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
113263 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
113264 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_RPZ_D),
113265 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
113266 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
113267 GIR_RootToRootCopy, /*OpIdx*/1, // vec
113268 GIR_RootConstrainSelectedInstOperands,
113269 // GIR_Coverage, 10860,
113270 GIR_EraseRootFromParent_Done,
113271 // Label 6383: @306804
113272 GIM_Try, /*On fail goto*//*Label 6384*/ GIMT_Encode4(306865), // Rule ID 10869 //
113273 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
113274 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
113275 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
113276 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113277 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113278 // (vector_extract:{ *:[f64] } nxv2f64:{ *:[nxv2f64] }:$vec, GPR64:{ *:[i64] }:$index) => (LASTB_VPZ_D:{ *:[f64] } (WHILELS_PXX_D:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv2f64] }:$vec)
113279 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
113280 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_D),
113281 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
113282 GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
113283 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
113284 GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
113285 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
113286 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_D),
113287 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
113288 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
113289 GIR_RootToRootCopy, /*OpIdx*/1, // vec
113290 GIR_RootConstrainSelectedInstOperands,
113291 // GIR_Coverage, 10869,
113292 GIR_EraseRootFromParent_Done,
113293 // Label 6384: @306865
113294 GIM_Reject,
113295 // Label 6322: @306866
113296 GIM_Reject,
113297 // Label 80: @306867
113298 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 6387*/ GIMT_Encode4(307018),
113299 /*GILLT_s32*//*Label 6385*/ GIMT_Encode4(306886),
113300 /*GILLT_s64*//*Label 6386*/ GIMT_Encode4(306952),
113301 // Label 6385: @306886
113302 GIM_Try, /*On fail goto*//*Label 6388*/ GIMT_Encode4(306951),
113303 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
113304 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
113305 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
113306 GIM_Try, /*On fail goto*//*Label 6389*/ GIMT_Encode4(306917), // Rule ID 2306 //
113307 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
113308 // (cttz:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (CTZWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
113309 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CTZWr),
113310 GIR_RootConstrainSelectedInstOperands,
113311 // GIR_Coverage, 2306,
113312 GIR_Done,
113313 // Label 6389: @306917
113314 GIM_Try, /*On fail goto*//*Label 6390*/ GIMT_Encode4(306950), // Rule ID 3874 //
113315 // (cttz:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (CLZWr:{ *:[i32] } (RBITWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn))
113316 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
113317 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::RBITWr),
113318 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
113319 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
113320 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
113321 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLZWr),
113322 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
113323 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
113324 GIR_RootConstrainSelectedInstOperands,
113325 // GIR_Coverage, 3874,
113326 GIR_EraseRootFromParent_Done,
113327 // Label 6390: @306950
113328 GIM_Reject,
113329 // Label 6388: @306951
113330 GIM_Reject,
113331 // Label 6386: @306952
113332 GIM_Try, /*On fail goto*//*Label 6391*/ GIMT_Encode4(307017),
113333 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
113334 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113335 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113336 GIM_Try, /*On fail goto*//*Label 6392*/ GIMT_Encode4(306983), // Rule ID 2307 //
113337 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
113338 // (cttz:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (CTZXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
113339 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CTZXr),
113340 GIR_RootConstrainSelectedInstOperands,
113341 // GIR_Coverage, 2307,
113342 GIR_Done,
113343 // Label 6392: @306983
113344 GIM_Try, /*On fail goto*//*Label 6393*/ GIMT_Encode4(307016), // Rule ID 3875 //
113345 // (cttz:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (CLZXr:{ *:[i64] } (RBITXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn))
113346 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
113347 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::RBITXr),
113348 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
113349 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
113350 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
113351 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLZXr),
113352 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
113353 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
113354 GIR_RootConstrainSelectedInstOperands,
113355 // GIR_Coverage, 3875,
113356 GIR_EraseRootFromParent_Done,
113357 // Label 6393: @307016
113358 GIM_Reject,
113359 // Label 6391: @307017
113360 GIM_Reject,
113361 // Label 6387: @307018
113362 GIM_Reject,
113363 // Label 81: @307019
113364 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 6402*/ GIMT_Encode4(307692),
113365 /*GILLT_s32*//*Label 6394*/ GIMT_Encode4(307070),
113366 /*GILLT_s64*//*Label 6395*/ GIMT_Encode4(307300), GIMT_Encode4(0),
113367 /*GILLT_v2s32*//*Label 6396*/ GIMT_Encode4(307530), GIMT_Encode4(0),
113368 /*GILLT_v4s16*//*Label 6397*/ GIMT_Encode4(307557),
113369 /*GILLT_v4s32*//*Label 6398*/ GIMT_Encode4(307584),
113370 /*GILLT_v8s8*//*Label 6399*/ GIMT_Encode4(307611),
113371 /*GILLT_v8s16*//*Label 6400*/ GIMT_Encode4(307638),
113372 /*GILLT_v16s8*//*Label 6401*/ GIMT_Encode4(307665),
113373 // Label 6394: @307070
113374 GIM_Try, /*On fail goto*//*Label 6403*/ GIMT_Encode4(307299),
113375 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
113376 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
113377 GIM_Try, /*On fail goto*//*Label 6404*/ GIMT_Encode4(307182), // Rule ID 3876 //
113378 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
113379 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
113380 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
113381 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
113382 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
113383 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
113384 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
113385 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
113386 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
113387 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
113388 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
113389 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
113390 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ASHR),
113391 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
113392 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
113393 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
113394 GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 31,
113395 // MIs[3] Rn
113396 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1,
113397 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
113398 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
113399 GIM_CheckIsSafeToFold, /*NumInsns*/4,
113400 // (ctlz:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } (xor:{ *:[i32] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, 31:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn), 1:{ *:[i64] }), 1:{ *:[i32] })) => (CLSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
113401 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSWr),
113402 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
113403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
113404 GIR_RootConstrainSelectedInstOperands,
113405 // GIR_Coverage, 3876,
113406 GIR_EraseRootFromParent_Done,
113407 // Label 6404: @307182
113408 GIM_Try, /*On fail goto*//*Label 6405*/ GIMT_Encode4(307282), // Rule ID 13042 //
113409 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
113410 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
113411 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
113412 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
113413 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
113414 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
113415 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
113416 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
113417 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
113418 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
113419 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
113420 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
113421 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
113422 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
113423 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ASHR),
113424 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
113425 // MIs[4] Rn
113426 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
113427 GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 31,
113428 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
113429 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
113430 GIM_CheckIsSafeToFold, /*NumInsns*/4,
113431 // (ctlz:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, 31:{ *:[i64] })), 1:{ *:[i64] }), 1:{ *:[i32] })) => (CLSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
113432 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSWr),
113433 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
113434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
113435 GIR_RootConstrainSelectedInstOperands,
113436 // GIR_Coverage, 13042,
113437 GIR_EraseRootFromParent_Done,
113438 // Label 6405: @307282
113439 GIM_Try, /*On fail goto*//*Label 6406*/ GIMT_Encode4(307298), // Rule ID 191 //
113440 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
113441 // (ctlz:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (CLZWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
113442 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZWr),
113443 GIR_RootConstrainSelectedInstOperands,
113444 // GIR_Coverage, 191,
113445 GIR_Done,
113446 // Label 6406: @307298
113447 GIM_Reject,
113448 // Label 6403: @307299
113449 GIM_Reject,
113450 // Label 6395: @307300
113451 GIM_Try, /*On fail goto*//*Label 6407*/ GIMT_Encode4(307529),
113452 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
113453 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113454 GIM_Try, /*On fail goto*//*Label 6408*/ GIMT_Encode4(307412), // Rule ID 3877 //
113455 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
113456 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
113457 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
113458 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
113459 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
113460 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
113461 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
113462 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
113463 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
113464 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
113465 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
113466 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
113467 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ASHR),
113468 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64,
113469 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
113470 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113471 GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 63,
113472 // MIs[3] Rn
113473 GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1,
113474 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
113475 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
113476 GIM_CheckIsSafeToFold, /*NumInsns*/4,
113477 // (ctlz:{ *:[i64] } (or:{ *:[i64] } (shl:{ *:[i64] } (xor:{ *:[i64] } (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 63:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn), 1:{ *:[i64] }), 1:{ *:[i64] })) => (CLSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
113478 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSXr),
113479 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
113480 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
113481 GIR_RootConstrainSelectedInstOperands,
113482 // GIR_Coverage, 3877,
113483 GIR_EraseRootFromParent_Done,
113484 // Label 6408: @307412
113485 GIM_Try, /*On fail goto*//*Label 6409*/ GIMT_Encode4(307512), // Rule ID 13043 //
113486 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
113487 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
113488 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
113489 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
113490 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
113491 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
113492 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
113493 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
113494 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
113495 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
113496 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
113497 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
113498 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113499 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
113500 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ASHR),
113501 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
113502 // MIs[4] Rn
113503 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
113504 GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 63,
113505 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
113506 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
113507 GIM_CheckIsSafeToFold, /*NumInsns*/4,
113508 // (ctlz:{ *:[i64] } (or:{ *:[i64] } (shl:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 63:{ *:[i64] })), 1:{ *:[i64] }), 1:{ *:[i64] })) => (CLSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
113509 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSXr),
113510 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
113511 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
113512 GIR_RootConstrainSelectedInstOperands,
113513 // GIR_Coverage, 13043,
113514 GIR_EraseRootFromParent_Done,
113515 // Label 6409: @307512
113516 GIM_Try, /*On fail goto*//*Label 6410*/ GIMT_Encode4(307528), // Rule ID 192 //
113517 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113518 // (ctlz:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (CLZXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
113519 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZXr),
113520 GIR_RootConstrainSelectedInstOperands,
113521 // GIR_Coverage, 192,
113522 GIR_Done,
113523 // Label 6410: @307528
113524 GIM_Reject,
113525 // Label 6407: @307529
113526 GIM_Reject,
113527 // Label 6396: @307530
113528 GIM_Try, /*On fail goto*//*Label 6411*/ GIMT_Encode4(307556), // Rule ID 714 //
113529 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
113530 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
113531 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113532 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113533 // (ctlz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) => (CLZv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
113534 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZv2i32),
113535 GIR_RootConstrainSelectedInstOperands,
113536 // GIR_Coverage, 714,
113537 GIR_Done,
113538 // Label 6411: @307556
113539 GIM_Reject,
113540 // Label 6397: @307557
113541 GIM_Try, /*On fail goto*//*Label 6412*/ GIMT_Encode4(307583), // Rule ID 712 //
113542 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
113543 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
113544 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113545 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113546 // (ctlz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) => (CLZv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
113547 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZv4i16),
113548 GIR_RootConstrainSelectedInstOperands,
113549 // GIR_Coverage, 712,
113550 GIR_Done,
113551 // Label 6412: @307583
113552 GIM_Reject,
113553 // Label 6398: @307584
113554 GIM_Try, /*On fail goto*//*Label 6413*/ GIMT_Encode4(307610), // Rule ID 715 //
113555 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
113556 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
113557 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113558 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113559 // (ctlz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) => (CLZv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
113560 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZv4i32),
113561 GIR_RootConstrainSelectedInstOperands,
113562 // GIR_Coverage, 715,
113563 GIR_Done,
113564 // Label 6413: @307610
113565 GIM_Reject,
113566 // Label 6399: @307611
113567 GIM_Try, /*On fail goto*//*Label 6414*/ GIMT_Encode4(307637), // Rule ID 710 //
113568 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
113569 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
113570 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113571 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113572 // (ctlz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (CLZv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
113573 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZv8i8),
113574 GIR_RootConstrainSelectedInstOperands,
113575 // GIR_Coverage, 710,
113576 GIR_Done,
113577 // Label 6414: @307637
113578 GIM_Reject,
113579 // Label 6400: @307638
113580 GIM_Try, /*On fail goto*//*Label 6415*/ GIMT_Encode4(307664), // Rule ID 713 //
113581 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
113582 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
113583 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113584 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113585 // (ctlz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) => (CLZv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
113586 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZv8i16),
113587 GIR_RootConstrainSelectedInstOperands,
113588 // GIR_Coverage, 713,
113589 GIR_Done,
113590 // Label 6415: @307664
113591 GIM_Reject,
113592 // Label 6401: @307665
113593 GIM_Try, /*On fail goto*//*Label 6416*/ GIMT_Encode4(307691), // Rule ID 711 //
113594 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
113595 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
113596 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113597 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113598 // (ctlz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (CLZv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
113599 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZv16i8),
113600 GIR_RootConstrainSelectedInstOperands,
113601 // GIR_Coverage, 711,
113602 GIR_Done,
113603 // Label 6416: @307691
113604 GIM_Reject,
113605 // Label 6402: @307692
113606 GIM_Reject,
113607 // Label 82: @307693
113608 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 6421*/ GIMT_Encode4(307852),
113609 /*GILLT_s32*//*Label 6417*/ GIMT_Encode4(307744),
113610 /*GILLT_s64*//*Label 6418*/ GIMT_Encode4(307771), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
113611 /*GILLT_v8s8*//*Label 6419*/ GIMT_Encode4(307798), GIMT_Encode4(0),
113612 /*GILLT_v16s8*//*Label 6420*/ GIMT_Encode4(307825),
113613 // Label 6417: @307744
113614 GIM_Try, /*On fail goto*//*Label 6422*/ GIMT_Encode4(307770), // Rule ID 2304 //
113615 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
113616 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
113617 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
113618 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
113619 // (ctpop:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (CNTWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
113620 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CNTWr),
113621 GIR_RootConstrainSelectedInstOperands,
113622 // GIR_Coverage, 2304,
113623 GIR_Done,
113624 // Label 6422: @307770
113625 GIM_Reject,
113626 // Label 6418: @307771
113627 GIM_Try, /*On fail goto*//*Label 6423*/ GIMT_Encode4(307797), // Rule ID 2305 //
113628 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
113629 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
113630 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113631 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113632 // (ctpop:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (CNTXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
113633 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CNTXr),
113634 GIR_RootConstrainSelectedInstOperands,
113635 // GIR_Coverage, 2305,
113636 GIR_Done,
113637 // Label 6423: @307797
113638 GIM_Reject,
113639 // Label 6419: @307798
113640 GIM_Try, /*On fail goto*//*Label 6424*/ GIMT_Encode4(307824), // Rule ID 751 //
113641 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
113642 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
113643 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113644 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113645 // (ctpop:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (CNTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
113646 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CNTv8i8),
113647 GIR_RootConstrainSelectedInstOperands,
113648 // GIR_Coverage, 751,
113649 GIR_Done,
113650 // Label 6424: @307824
113651 GIM_Reject,
113652 // Label 6420: @307825
113653 GIM_Try, /*On fail goto*//*Label 6425*/ GIMT_Encode4(307851), // Rule ID 752 //
113654 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
113655 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
113656 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113657 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113658 // (ctpop:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (CNTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
113659 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CNTv16i8),
113660 GIR_RootConstrainSelectedInstOperands,
113661 // GIR_Coverage, 752,
113662 GIR_Done,
113663 // Label 6425: @307851
113664 GIM_Reject,
113665 // Label 6421: @307852
113666 GIM_Reject,
113667 // Label 83: @307853
113668 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 6433*/ GIMT_Encode4(308166),
113669 /*GILLT_s32*//*Label 6426*/ GIMT_Encode4(307900),
113670 /*GILLT_s64*//*Label 6427*/ GIMT_Encode4(307973), GIMT_Encode4(0),
113671 /*GILLT_v2s32*//*Label 6428*/ GIMT_Encode4(308046),
113672 /*GILLT_v2s64*//*Label 6429*/ GIMT_Encode4(308070),
113673 /*GILLT_v4s16*//*Label 6430*/ GIMT_Encode4(308094),
113674 /*GILLT_v4s32*//*Label 6431*/ GIMT_Encode4(308118), GIMT_Encode4(0),
113675 /*GILLT_v8s16*//*Label 6432*/ GIMT_Encode4(308142),
113676 // Label 6426: @307900
113677 GIM_Try, /*On fail goto*//*Label 6434*/ GIMT_Encode4(307972),
113678 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
113679 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
113680 GIM_Try, /*On fail goto*//*Label 6435*/ GIMT_Encode4(307955), // Rule ID 3880 //
113681 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
113682 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ROTR),
113683 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
113684 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
113685 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
113686 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
113687 GIM_CheckIsSafeToFold, /*NumInsns*/1,
113688 // (bswap:{ *:[i32] } (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, 16:{ *:[i64] })) => (REV16Wr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
113689 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV16Wr),
113690 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
113691 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
113692 GIR_RootConstrainSelectedInstOperands,
113693 // GIR_Coverage, 3880,
113694 GIR_EraseRootFromParent_Done,
113695 // Label 6435: @307955
113696 GIM_Try, /*On fail goto*//*Label 6436*/ GIMT_Encode4(307971), // Rule ID 196 //
113697 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
113698 // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (REVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
113699 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REVWr),
113700 GIR_RootConstrainSelectedInstOperands,
113701 // GIR_Coverage, 196,
113702 GIR_Done,
113703 // Label 6436: @307971
113704 GIM_Reject,
113705 // Label 6434: @307972
113706 GIM_Reject,
113707 // Label 6427: @307973
113708 GIM_Try, /*On fail goto*//*Label 6437*/ GIMT_Encode4(308045),
113709 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
113710 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113711 GIM_Try, /*On fail goto*//*Label 6438*/ GIMT_Encode4(308028), // Rule ID 3881 //
113712 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
113713 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ROTR),
113714 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
113715 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
113716 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113717 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 32,
113718 GIM_CheckIsSafeToFold, /*NumInsns*/1,
113719 // (bswap:{ *:[i64] } (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 32:{ *:[i64] })) => (REV32Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
113720 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV32Xr),
113721 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
113722 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
113723 GIR_RootConstrainSelectedInstOperands,
113724 // GIR_Coverage, 3881,
113725 GIR_EraseRootFromParent_Done,
113726 // Label 6438: @308028
113727 GIM_Try, /*On fail goto*//*Label 6439*/ GIMT_Encode4(308044), // Rule ID 197 //
113728 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113729 // (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (REVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
113730 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REVXr),
113731 GIR_RootConstrainSelectedInstOperands,
113732 // GIR_Coverage, 197,
113733 GIR_Done,
113734 // Label 6439: @308044
113735 GIM_Reject,
113736 // Label 6437: @308045
113737 GIM_Reject,
113738 // Label 6428: @308046
113739 GIM_Try, /*On fail goto*//*Label 6440*/ GIMT_Encode4(308069), // Rule ID 4654 //
113740 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
113741 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113742 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113743 // (bswap:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) => (REV32v8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
113744 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i8),
113745 GIR_RootConstrainSelectedInstOperands,
113746 // GIR_Coverage, 4654,
113747 GIR_Done,
113748 // Label 6440: @308069
113749 GIM_Reject,
113750 // Label 6429: @308070
113751 GIM_Try, /*On fail goto*//*Label 6441*/ GIMT_Encode4(308093), // Rule ID 4656 //
113752 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
113753 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113754 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113755 // (bswap:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn) => (REV64v16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
113756 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
113757 GIR_RootConstrainSelectedInstOperands,
113758 // GIR_Coverage, 4656,
113759 GIR_Done,
113760 // Label 6441: @308093
113761 GIM_Reject,
113762 // Label 6430: @308094
113763 GIM_Try, /*On fail goto*//*Label 6442*/ GIMT_Encode4(308117), // Rule ID 4652 //
113764 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
113765 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113766 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113767 // (bswap:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) => (REV16v8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
113768 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
113769 GIR_RootConstrainSelectedInstOperands,
113770 // GIR_Coverage, 4652,
113771 GIR_Done,
113772 // Label 6442: @308117
113773 GIM_Reject,
113774 // Label 6431: @308118
113775 GIM_Try, /*On fail goto*//*Label 6443*/ GIMT_Encode4(308141), // Rule ID 4655 //
113776 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
113777 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113778 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113779 // (bswap:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) => (REV32v16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
113780 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v16i8),
113781 GIR_RootConstrainSelectedInstOperands,
113782 // GIR_Coverage, 4655,
113783 GIR_Done,
113784 // Label 6443: @308141
113785 GIM_Reject,
113786 // Label 6432: @308142
113787 GIM_Try, /*On fail goto*//*Label 6444*/ GIMT_Encode4(308165), // Rule ID 4653 //
113788 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
113789 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113790 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113791 // (bswap:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) => (REV16v16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
113792 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
113793 GIR_RootConstrainSelectedInstOperands,
113794 // GIR_Coverage, 4653,
113795 GIR_Done,
113796 // Label 6444: @308165
113797 GIM_Reject,
113798 // Label 6433: @308166
113799 GIM_Reject,
113800 // Label 84: @308167
113801 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 6449*/ GIMT_Encode4(308320),
113802 /*GILLT_s32*//*Label 6445*/ GIMT_Encode4(308218),
113803 /*GILLT_s64*//*Label 6446*/ GIMT_Encode4(308242), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
113804 /*GILLT_v8s8*//*Label 6447*/ GIMT_Encode4(308266), GIMT_Encode4(0),
113805 /*GILLT_v16s8*//*Label 6448*/ GIMT_Encode4(308293),
113806 // Label 6445: @308218
113807 GIM_Try, /*On fail goto*//*Label 6450*/ GIMT_Encode4(308241), // Rule ID 193 //
113808 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
113809 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
113810 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
113811 // (bitreverse:{ *:[i32] } GPR32:{ *:[i32] }:$Rn) => (RBITWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
113812 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::RBITWr),
113813 GIR_RootConstrainSelectedInstOperands,
113814 // GIR_Coverage, 193,
113815 GIR_Done,
113816 // Label 6450: @308241
113817 GIM_Reject,
113818 // Label 6446: @308242
113819 GIM_Try, /*On fail goto*//*Label 6451*/ GIMT_Encode4(308265), // Rule ID 194 //
113820 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
113821 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113822 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
113823 // (bitreverse:{ *:[i64] } GPR64:{ *:[i64] }:$Rn) => (RBITXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
113824 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::RBITXr),
113825 GIR_RootConstrainSelectedInstOperands,
113826 // GIR_Coverage, 194,
113827 GIR_Done,
113828 // Label 6451: @308265
113829 GIM_Reject,
113830 // Label 6447: @308266
113831 GIM_Try, /*On fail goto*//*Label 6452*/ GIMT_Encode4(308292), // Rule ID 961 //
113832 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
113833 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
113834 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113835 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113836 // (bitreverse:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (RBITv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
113837 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::RBITv8i8),
113838 GIR_RootConstrainSelectedInstOperands,
113839 // GIR_Coverage, 961,
113840 GIR_Done,
113841 // Label 6452: @308292
113842 GIM_Reject,
113843 // Label 6448: @308293
113844 GIM_Try, /*On fail goto*//*Label 6453*/ GIMT_Encode4(308319), // Rule ID 962 //
113845 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
113846 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
113847 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113848 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113849 // (bitreverse:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (RBITv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
113850 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::RBITv16i8),
113851 GIR_RootConstrainSelectedInstOperands,
113852 // GIR_Coverage, 962,
113853 GIR_Done,
113854 // Label 6453: @308319
113855 GIM_Reject,
113856 // Label 6449: @308320
113857 GIM_Reject,
113858 // Label 85: @308321
113859 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6462*/ GIMT_Encode4(309743),
113860 /*GILLT_s16*//*Label 6454*/ GIMT_Encode4(308372),
113861 /*GILLT_s32*//*Label 6455*/ GIMT_Encode4(308403),
113862 /*GILLT_s64*//*Label 6456*/ GIMT_Encode4(308434), GIMT_Encode4(0),
113863 /*GILLT_v2s32*//*Label 6457*/ GIMT_Encode4(308465),
113864 /*GILLT_v2s64*//*Label 6458*/ GIMT_Encode4(308496),
113865 /*GILLT_v4s16*//*Label 6459*/ GIMT_Encode4(308527),
113866 /*GILLT_v4s32*//*Label 6460*/ GIMT_Encode4(308558), GIMT_Encode4(0),
113867 /*GILLT_v8s16*//*Label 6461*/ GIMT_Encode4(308589),
113868 // Label 6454: @308372
113869 GIM_Try, /*On fail goto*//*Label 6463*/ GIMT_Encode4(308402), // Rule ID 546 //
113870 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
113871 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
113872 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
113873 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
113874 // (fceil:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTPHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
113875 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPHr),
113876 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
113877 GIR_RootConstrainSelectedInstOperands,
113878 // GIR_Coverage, 546,
113879 GIR_Done,
113880 // Label 6463: @308402
113881 GIM_Reject,
113882 // Label 6455: @308403
113883 GIM_Try, /*On fail goto*//*Label 6464*/ GIMT_Encode4(308433), // Rule ID 548 //
113884 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
113885 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
113886 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
113887 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
113888 // (fceil:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTPSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
113889 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPSr),
113890 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
113891 GIR_RootConstrainSelectedInstOperands,
113892 // GIR_Coverage, 548,
113893 GIR_Done,
113894 // Label 6464: @308433
113895 GIM_Reject,
113896 // Label 6456: @308434
113897 GIM_Try, /*On fail goto*//*Label 6465*/ GIMT_Encode4(308464), // Rule ID 550 //
113898 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
113899 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
113900 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113901 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113902 // (fceil:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTPDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
113903 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPDr),
113904 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
113905 GIR_RootConstrainSelectedInstOperands,
113906 // GIR_Coverage, 550,
113907 GIR_Done,
113908 // Label 6465: @308464
113909 GIM_Reject,
113910 // Label 6457: @308465
113911 GIM_Try, /*On fail goto*//*Label 6466*/ GIMT_Encode4(308495), // Rule ID 900 //
113912 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
113913 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
113914 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113915 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113916 // (fceil:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
113917 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv2f32),
113918 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
113919 GIR_RootConstrainSelectedInstOperands,
113920 // GIR_Coverage, 900,
113921 GIR_Done,
113922 // Label 6466: @308495
113923 GIM_Reject,
113924 // Label 6458: @308496
113925 GIM_Try, /*On fail goto*//*Label 6467*/ GIMT_Encode4(308526), // Rule ID 904 //
113926 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
113927 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
113928 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113929 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113930 // (fceil:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
113931 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv2f64),
113932 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
113933 GIR_RootConstrainSelectedInstOperands,
113934 // GIR_Coverage, 904,
113935 GIR_Done,
113936 // Label 6467: @308526
113937 GIM_Reject,
113938 // Label 6459: @308527
113939 GIM_Try, /*On fail goto*//*Label 6468*/ GIMT_Encode4(308557), // Rule ID 896 //
113940 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
113941 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
113942 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113943 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
113944 // (fceil:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
113945 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f16),
113946 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
113947 GIR_RootConstrainSelectedInstOperands,
113948 // GIR_Coverage, 896,
113949 GIR_Done,
113950 // Label 6468: @308557
113951 GIM_Reject,
113952 // Label 6460: @308558
113953 GIM_Try, /*On fail goto*//*Label 6469*/ GIMT_Encode4(308588), // Rule ID 902 //
113954 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
113955 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
113956 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113957 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113958 // (fceil:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
113959 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f32),
113960 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
113961 GIR_RootConstrainSelectedInstOperands,
113962 // GIR_Coverage, 902,
113963 GIR_Done,
113964 // Label 6469: @308588
113965 GIM_Reject,
113966 // Label 6461: @308589
113967 GIM_Try, /*On fail goto*//*Label 6470*/ GIMT_Encode4(309742),
113968 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
113969 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113970 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
113971 GIM_Try, /*On fail goto*//*Label 6471*/ GIMT_Encode4(308624), // Rule ID 898 //
113972 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
113973 // (fceil:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
113974 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv8f16),
113975 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
113976 GIR_RootConstrainSelectedInstOperands,
113977 // GIR_Coverage, 898,
113978 GIR_Done,
113979 // Label 6471: @308624
113980 GIM_Try, /*On fail goto*//*Label 6472*/ GIMT_Encode4(308809), // Rule ID 6674 //
113981 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
113982 // (fceil:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTPv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTPv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
113983 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
113984 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
113985 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
113986 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
113987 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
113988 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
113989 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
113990 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
113991 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
113992 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
113993 GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
113994 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
113995 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f32),
113996 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
113997 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
113998 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
113999 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
114000 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114001 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
114002 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
114003 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
114004 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
114005 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114006 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
114007 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
114008 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f32),
114009 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114010 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
114011 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
114012 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
114013 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114014 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
114015 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
114016 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
114017 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114018 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
114019 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
114020 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114021 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
114022 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
114023 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
114024 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
114025 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
114026 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
114027 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
114028 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
114029 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
114030 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
114031 GIR_RootConstrainSelectedInstOperands,
114032 // GIR_Coverage, 6674,
114033 GIR_EraseRootFromParent_Done,
114034 // Label 6472: @308809
114035 GIM_Try, /*On fail goto*//*Label 6473*/ GIMT_Encode4(308944), // Rule ID 6676 //
114036 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16),
114037 // (fceil:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (BFCVTN2:{ *:[v8bf16] } (BFCVTN:{ *:[v8bf16] } (FRINTPv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })))), (FRINTPv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)))
114038 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
114039 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
114040 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
114041 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
114042 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
114043 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
114044 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
114045 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114046 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, // Rn
114047 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
114048 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f32),
114049 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114050 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
114051 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
114052 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
114053 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114054 GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
114055 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
114056 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
114057 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
114058 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114059 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
114060 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
114061 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f32),
114062 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114063 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
114064 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
114065 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN),
114066 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114067 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
114068 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
114069 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN2),
114070 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
114071 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
114072 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
114073 GIR_RootConstrainSelectedInstOperands,
114074 // GIR_Coverage, 6676,
114075 GIR_EraseRootFromParent_Done,
114076 // Label 6473: @308944
114077 GIM_Try, /*On fail goto*//*Label 6474*/ GIMT_Encode4(309741), // Rule ID 6678 //
114078 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoBF16),
114079 // (fceil:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (UZP2v8i16:{ *:[v8bf16] } (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FRINTPv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), (FRINTPv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FRINTPv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FRINTPv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), 64:{ *:[i32] }, 16:{ *:[i32] })), (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FRINTPv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), (FRINTPv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FRINTPv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FRINTPv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), 64:{ *:[i32] }, 16:{ *:[i32] })))
114080 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
114081 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
114082 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
114083 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
114084 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
114085 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
114086 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
114087 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
114088 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s128,
114089 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s128,
114090 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
114091 GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_v4s32,
114092 GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_v4s16,
114093 GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s128,
114094 GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_s128,
114095 GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_s128,
114096 GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_s128,
114097 GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_s128,
114098 GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_v4s32,
114099 GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_v4s32,
114100 GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_v4s16,
114101 GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s128,
114102 GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s128,
114103 GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_v4s32,
114104 GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_v4s32,
114105 GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_v4s32,
114106 GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_v4s32,
114107 GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_s128,
114108 GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_s128,
114109 GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_v4s32,
114110 GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_v4s32,
114111 GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_s128,
114112 GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_s128,
114113 GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_s128,
114114 GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_s128,
114115 GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_s128,
114116 GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_v4s32,
114117 GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_v4s32,
114118 GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
114119 GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114120 GIR_Copy, /*NewInsnID*/38, /*OldInsnID*/0, /*OpIdx*/1, // Rn
114121 GIR_ConstrainSelectedInstOperands, /*InsnID*/38,
114122 GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f32),
114123 GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114124 GIR_AddSimpleTempRegister, /*InsnID*/37, /*TempRegID*/37,
114125 GIR_ConstrainSelectedInstOperands, /*InsnID*/37,
114126 GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
114127 GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114128 GIR_AddSimpleTempRegister, /*InsnID*/36, /*TempRegID*/36,
114129 GIR_AddImm8, /*InsnID*/36, /*Imm*/64,
114130 GIR_AddImm8, /*InsnID*/36, /*Imm*/16,
114131 GIR_ConstrainSelectedInstOperands, /*InsnID*/36,
114132 GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
114133 GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114134 GIR_AddImm8, /*InsnID*/35, /*Imm*/127,
114135 GIR_AddImm, /*InsnID*/35, /*Imm*/GIMT_Encode8(264),
114136 GIR_ConstrainSelectedInstOperands, /*InsnID*/35,
114137 GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
114138 GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114139 GIR_AddImm8, /*InsnID*/34, /*Imm*/1,
114140 GIR_AddImm8, /*InsnID*/34, /*Imm*/0,
114141 GIR_ConstrainSelectedInstOperands, /*InsnID*/34,
114142 GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
114143 GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114144 GIR_Copy, /*NewInsnID*/33, /*OldInsnID*/0, /*OpIdx*/1, // Rn
114145 GIR_AddImm8, /*InsnID*/33, /*Imm*/16,
114146 GIR_ConstrainSelectedInstOperands, /*InsnID*/33,
114147 GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
114148 GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114149 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/32,
114150 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/33,
114151 GIR_ConstrainSelectedInstOperands, /*InsnID*/32,
114152 GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
114153 GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114154 GIR_Copy, /*NewInsnID*/31, /*OldInsnID*/0, /*OpIdx*/1, // Rn
114155 GIR_ConstrainSelectedInstOperands, /*InsnID*/31,
114156 GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f32),
114157 GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114158 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/30,
114159 GIR_ConstrainSelectedInstOperands, /*InsnID*/30,
114160 GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
114161 GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114162 GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/29,
114163 GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/31,
114164 GIR_ConstrainSelectedInstOperands, /*InsnID*/29,
114165 GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
114166 GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114167 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/28,
114168 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/34,
114169 GIR_ConstrainSelectedInstOperands, /*InsnID*/28,
114170 GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
114171 GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114172 GIR_Copy, /*NewInsnID*/27, /*OldInsnID*/0, /*OpIdx*/1, // Rn
114173 GIR_ConstrainSelectedInstOperands, /*InsnID*/27,
114174 GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f32),
114175 GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114176 GIR_AddSimpleTempRegister, /*InsnID*/26, /*TempRegID*/26,
114177 GIR_ConstrainSelectedInstOperands, /*InsnID*/26,
114178 GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
114179 GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114180 GIR_Copy, /*NewInsnID*/25, /*OldInsnID*/0, /*OpIdx*/1, // Rn
114181 GIR_ConstrainSelectedInstOperands, /*InsnID*/25,
114182 GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f32),
114183 GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114184 GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/24,
114185 GIR_ConstrainSelectedInstOperands, /*InsnID*/24,
114186 GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
114187 GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114188 GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/23,
114189 GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/25,
114190 GIR_ConstrainSelectedInstOperands, /*InsnID*/23,
114191 GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
114192 GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114193 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/22,
114194 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/27,
114195 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/35,
114196 GIR_ConstrainSelectedInstOperands, /*InsnID*/22,
114197 GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
114198 GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114199 GIR_CopySubReg, /*NewInsnID*/21, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
114200 GIR_ConstrainOperandRC, /*InsnID*/21, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
114201 GIR_ConstrainOperandRC, /*InsnID*/21, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
114202 GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
114203 GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114204 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/20,
114205 GIR_ConstrainSelectedInstOperands, /*InsnID*/20,
114206 GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f32),
114207 GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114208 GIR_AddSimpleTempRegister, /*InsnID*/19, /*TempRegID*/19,
114209 GIR_ConstrainSelectedInstOperands, /*InsnID*/19,
114210 GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
114211 GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114212 GIR_AddSimpleTempRegister, /*InsnID*/18, /*TempRegID*/18,
114213 GIR_AddImm8, /*InsnID*/18, /*Imm*/64,
114214 GIR_AddImm8, /*InsnID*/18, /*Imm*/16,
114215 GIR_ConstrainSelectedInstOperands, /*InsnID*/18,
114216 GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
114217 GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114218 GIR_AddImm8, /*InsnID*/17, /*Imm*/127,
114219 GIR_AddImm, /*InsnID*/17, /*Imm*/GIMT_Encode8(264),
114220 GIR_ConstrainSelectedInstOperands, /*InsnID*/17,
114221 GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
114222 GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114223 GIR_AddImm8, /*InsnID*/16, /*Imm*/1,
114224 GIR_AddImm8, /*InsnID*/16, /*Imm*/0,
114225 GIR_ConstrainSelectedInstOperands, /*InsnID*/16,
114226 GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
114227 GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114228 GIR_Copy, /*NewInsnID*/15, /*OldInsnID*/0, /*OpIdx*/1, // Rn
114229 GIR_AddImm8, /*InsnID*/15, /*Imm*/16,
114230 GIR_ConstrainSelectedInstOperands, /*InsnID*/15,
114231 GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
114232 GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114233 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14,
114234 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/15,
114235 GIR_ConstrainSelectedInstOperands, /*InsnID*/14,
114236 GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
114237 GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114238 GIR_CopySubReg, /*NewInsnID*/13, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
114239 GIR_ConstrainOperandRC, /*InsnID*/13, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
114240 GIR_ConstrainOperandRC, /*InsnID*/13, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
114241 GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
114242 GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114243 GIR_AddSimpleTempRegister, /*InsnID*/12, /*TempRegID*/12,
114244 GIR_ConstrainSelectedInstOperands, /*InsnID*/12,
114245 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f32),
114246 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114247 GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11,
114248 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
114249 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
114250 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114251 GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
114252 GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/13,
114253 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
114254 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
114255 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114256 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
114257 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/16,
114258 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
114259 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
114260 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114261 GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
114262 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
114263 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
114264 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
114265 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114266 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
114267 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
114268 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f32),
114269 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114270 GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
114271 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
114272 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
114273 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114274 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
114275 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
114276 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
114277 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
114278 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114279 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
114280 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
114281 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f32),
114282 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114283 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
114284 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
114285 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
114286 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114287 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
114288 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
114289 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
114290 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
114291 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114292 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
114293 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/8,
114294 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/17,
114295 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
114296 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
114297 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
114298 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
114299 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/21,
114300 GIR_RootConstrainSelectedInstOperands,
114301 // GIR_Coverage, 6678,
114302 GIR_EraseRootFromParent_Done,
114303 // Label 6474: @309741
114304 GIM_Reject,
114305 // Label 6470: @309742
114306 GIM_Reject,
114307 // Label 6462: @309743
114308 GIM_Reject,
114309 // Label 86: @309744
114310 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6483*/ GIMT_Encode4(310043),
114311 /*GILLT_s16*//*Label 6475*/ GIMT_Encode4(309795),
114312 /*GILLT_s32*//*Label 6476*/ GIMT_Encode4(309826),
114313 /*GILLT_s64*//*Label 6477*/ GIMT_Encode4(309857), GIMT_Encode4(0),
114314 /*GILLT_v2s32*//*Label 6478*/ GIMT_Encode4(309888),
114315 /*GILLT_v2s64*//*Label 6479*/ GIMT_Encode4(309919),
114316 /*GILLT_v4s16*//*Label 6480*/ GIMT_Encode4(309950),
114317 /*GILLT_v4s32*//*Label 6481*/ GIMT_Encode4(309981), GIMT_Encode4(0),
114318 /*GILLT_v8s16*//*Label 6482*/ GIMT_Encode4(310012),
114319 // Label 6475: @309795
114320 GIM_Try, /*On fail goto*//*Label 6484*/ GIMT_Encode4(309825), // Rule ID 564 //
114321 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
114322 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
114323 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
114324 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
114325 // (fsqrt:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FSQRTHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
114326 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTHr),
114327 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114328 GIR_RootConstrainSelectedInstOperands,
114329 // GIR_Coverage, 564,
114330 GIR_Done,
114331 // Label 6484: @309825
114332 GIM_Reject,
114333 // Label 6476: @309826
114334 GIM_Try, /*On fail goto*//*Label 6485*/ GIMT_Encode4(309856), // Rule ID 566 //
114335 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
114336 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
114337 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
114338 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
114339 // (fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FSQRTSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
114340 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTSr),
114341 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114342 GIR_RootConstrainSelectedInstOperands,
114343 // GIR_Coverage, 566,
114344 GIR_Done,
114345 // Label 6485: @309856
114346 GIM_Reject,
114347 // Label 6477: @309857
114348 GIM_Try, /*On fail goto*//*Label 6486*/ GIMT_Encode4(309887), // Rule ID 568 //
114349 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
114350 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
114351 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
114352 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
114353 // (fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FSQRTDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
114354 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTDr),
114355 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114356 GIR_RootConstrainSelectedInstOperands,
114357 // GIR_Coverage, 568,
114358 GIR_Done,
114359 // Label 6486: @309887
114360 GIM_Reject,
114361 // Label 6478: @309888
114362 GIM_Try, /*On fail goto*//*Label 6487*/ GIMT_Encode4(309918), // Rule ID 947 //
114363 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
114364 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
114365 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
114366 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
114367 // (fsqrt:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FSQRTv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
114368 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv2f32),
114369 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114370 GIR_RootConstrainSelectedInstOperands,
114371 // GIR_Coverage, 947,
114372 GIR_Done,
114373 // Label 6487: @309918
114374 GIM_Reject,
114375 // Label 6479: @309919
114376 GIM_Try, /*On fail goto*//*Label 6488*/ GIMT_Encode4(309949), // Rule ID 951 //
114377 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
114378 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
114379 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
114380 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
114381 // (fsqrt:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FSQRTv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
114382 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv2f64),
114383 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114384 GIR_RootConstrainSelectedInstOperands,
114385 // GIR_Coverage, 951,
114386 GIR_Done,
114387 // Label 6488: @309949
114388 GIM_Reject,
114389 // Label 6480: @309950
114390 GIM_Try, /*On fail goto*//*Label 6489*/ GIMT_Encode4(309980), // Rule ID 943 //
114391 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
114392 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
114393 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
114394 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
114395 // (fsqrt:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FSQRTv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
114396 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv4f16),
114397 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114398 GIR_RootConstrainSelectedInstOperands,
114399 // GIR_Coverage, 943,
114400 GIR_Done,
114401 // Label 6489: @309980
114402 GIM_Reject,
114403 // Label 6481: @309981
114404 GIM_Try, /*On fail goto*//*Label 6490*/ GIMT_Encode4(310011), // Rule ID 949 //
114405 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
114406 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
114407 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
114408 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
114409 // (fsqrt:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FSQRTv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
114410 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv4f32),
114411 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114412 GIR_RootConstrainSelectedInstOperands,
114413 // GIR_Coverage, 949,
114414 GIR_Done,
114415 // Label 6490: @310011
114416 GIM_Reject,
114417 // Label 6482: @310012
114418 GIM_Try, /*On fail goto*//*Label 6491*/ GIMT_Encode4(310042), // Rule ID 945 //
114419 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
114420 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
114421 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
114422 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
114423 // (fsqrt:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FSQRTv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
114424 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv8f16),
114425 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114426 GIR_RootConstrainSelectedInstOperands,
114427 // GIR_Coverage, 945,
114428 GIR_Done,
114429 // Label 6491: @310042
114430 GIM_Reject,
114431 // Label 6483: @310043
114432 GIM_Reject,
114433 // Label 87: @310044
114434 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6500*/ GIMT_Encode4(311466),
114435 /*GILLT_s16*//*Label 6492*/ GIMT_Encode4(310095),
114436 /*GILLT_s32*//*Label 6493*/ GIMT_Encode4(310126),
114437 /*GILLT_s64*//*Label 6494*/ GIMT_Encode4(310157), GIMT_Encode4(0),
114438 /*GILLT_v2s32*//*Label 6495*/ GIMT_Encode4(310188),
114439 /*GILLT_v2s64*//*Label 6496*/ GIMT_Encode4(310219),
114440 /*GILLT_v4s16*//*Label 6497*/ GIMT_Encode4(310250),
114441 /*GILLT_v4s32*//*Label 6498*/ GIMT_Encode4(310281), GIMT_Encode4(0),
114442 /*GILLT_v8s16*//*Label 6499*/ GIMT_Encode4(310312),
114443 // Label 6492: @310095
114444 GIM_Try, /*On fail goto*//*Label 6501*/ GIMT_Encode4(310125), // Rule ID 534 //
114445 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
114446 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
114447 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
114448 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
114449 // (ffloor:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTMHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
114450 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMHr),
114451 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114452 GIR_RootConstrainSelectedInstOperands,
114453 // GIR_Coverage, 534,
114454 GIR_Done,
114455 // Label 6501: @310125
114456 GIM_Reject,
114457 // Label 6493: @310126
114458 GIM_Try, /*On fail goto*//*Label 6502*/ GIMT_Encode4(310156), // Rule ID 536 //
114459 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
114460 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
114461 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
114462 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
114463 // (ffloor:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTMSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
114464 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMSr),
114465 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114466 GIR_RootConstrainSelectedInstOperands,
114467 // GIR_Coverage, 536,
114468 GIR_Done,
114469 // Label 6502: @310156
114470 GIM_Reject,
114471 // Label 6494: @310157
114472 GIM_Try, /*On fail goto*//*Label 6503*/ GIMT_Encode4(310187), // Rule ID 538 //
114473 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
114474 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
114475 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
114476 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
114477 // (ffloor:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTMDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
114478 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMDr),
114479 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114480 GIR_RootConstrainSelectedInstOperands,
114481 // GIR_Coverage, 538,
114482 GIR_Done,
114483 // Label 6503: @310187
114484 GIM_Reject,
114485 // Label 6495: @310188
114486 GIM_Try, /*On fail goto*//*Label 6504*/ GIMT_Encode4(310218), // Rule ID 880 //
114487 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
114488 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
114489 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
114490 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
114491 // (ffloor:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
114492 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv2f32),
114493 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114494 GIR_RootConstrainSelectedInstOperands,
114495 // GIR_Coverage, 880,
114496 GIR_Done,
114497 // Label 6504: @310218
114498 GIM_Reject,
114499 // Label 6496: @310219
114500 GIM_Try, /*On fail goto*//*Label 6505*/ GIMT_Encode4(310249), // Rule ID 884 //
114501 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
114502 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
114503 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
114504 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
114505 // (ffloor:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
114506 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv2f64),
114507 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114508 GIR_RootConstrainSelectedInstOperands,
114509 // GIR_Coverage, 884,
114510 GIR_Done,
114511 // Label 6505: @310249
114512 GIM_Reject,
114513 // Label 6497: @310250
114514 GIM_Try, /*On fail goto*//*Label 6506*/ GIMT_Encode4(310280), // Rule ID 876 //
114515 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
114516 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
114517 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
114518 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
114519 // (ffloor:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
114520 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f16),
114521 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114522 GIR_RootConstrainSelectedInstOperands,
114523 // GIR_Coverage, 876,
114524 GIR_Done,
114525 // Label 6506: @310280
114526 GIM_Reject,
114527 // Label 6498: @310281
114528 GIM_Try, /*On fail goto*//*Label 6507*/ GIMT_Encode4(310311), // Rule ID 882 //
114529 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
114530 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
114531 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
114532 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
114533 // (ffloor:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
114534 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f32),
114535 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114536 GIR_RootConstrainSelectedInstOperands,
114537 // GIR_Coverage, 882,
114538 GIR_Done,
114539 // Label 6507: @310311
114540 GIM_Reject,
114541 // Label 6499: @310312
114542 GIM_Try, /*On fail goto*//*Label 6508*/ GIMT_Encode4(311465),
114543 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
114544 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
114545 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
114546 GIM_Try, /*On fail goto*//*Label 6509*/ GIMT_Encode4(310347), // Rule ID 878 //
114547 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
114548 // (ffloor:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
114549 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv8f16),
114550 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114551 GIR_RootConstrainSelectedInstOperands,
114552 // GIR_Coverage, 878,
114553 GIR_Done,
114554 // Label 6509: @310347
114555 GIM_Try, /*On fail goto*//*Label 6510*/ GIMT_Encode4(310532), // Rule ID 6680 //
114556 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
114557 // (ffloor:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTMv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTMv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
114558 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
114559 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
114560 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
114561 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
114562 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
114563 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
114564 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
114565 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
114566 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
114567 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114568 GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
114569 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
114570 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f32),
114571 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114572 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
114573 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
114574 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
114575 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114576 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
114577 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
114578 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
114579 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
114580 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114581 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
114582 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
114583 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f32),
114584 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114585 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
114586 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
114587 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
114588 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114589 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
114590 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
114591 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
114592 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114593 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
114594 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
114595 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114596 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
114597 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
114598 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
114599 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
114600 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
114601 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
114602 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
114603 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
114604 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
114605 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
114606 GIR_RootConstrainSelectedInstOperands,
114607 // GIR_Coverage, 6680,
114608 GIR_EraseRootFromParent_Done,
114609 // Label 6510: @310532
114610 GIM_Try, /*On fail goto*//*Label 6511*/ GIMT_Encode4(310667), // Rule ID 6682 //
114611 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16),
114612 // (ffloor:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (BFCVTN2:{ *:[v8bf16] } (BFCVTN:{ *:[v8bf16] } (FRINTMv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })))), (FRINTMv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)))
114613 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
114614 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
114615 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
114616 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
114617 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
114618 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
114619 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
114620 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114621 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, // Rn
114622 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
114623 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f32),
114624 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114625 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
114626 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
114627 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
114628 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114629 GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
114630 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
114631 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
114632 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
114633 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114634 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
114635 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
114636 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f32),
114637 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114638 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
114639 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
114640 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN),
114641 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114642 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
114643 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
114644 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN2),
114645 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
114646 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
114647 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
114648 GIR_RootConstrainSelectedInstOperands,
114649 // GIR_Coverage, 6682,
114650 GIR_EraseRootFromParent_Done,
114651 // Label 6511: @310667
114652 GIM_Try, /*On fail goto*//*Label 6512*/ GIMT_Encode4(311464), // Rule ID 6684 //
114653 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoBF16),
114654 // (ffloor:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (UZP2v8i16:{ *:[v8bf16] } (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FRINTMv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), (FRINTMv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FRINTMv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FRINTMv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), 64:{ *:[i32] }, 16:{ *:[i32] })), (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FRINTMv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), (FRINTMv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FRINTMv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FRINTMv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), 64:{ *:[i32] }, 16:{ *:[i32] })))
114655 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
114656 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
114657 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
114658 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
114659 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
114660 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
114661 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
114662 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
114663 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s128,
114664 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s128,
114665 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
114666 GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_v4s32,
114667 GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_v4s16,
114668 GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s128,
114669 GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_s128,
114670 GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_s128,
114671 GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_s128,
114672 GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_s128,
114673 GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_v4s32,
114674 GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_v4s32,
114675 GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_v4s16,
114676 GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s128,
114677 GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s128,
114678 GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_v4s32,
114679 GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_v4s32,
114680 GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_v4s32,
114681 GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_v4s32,
114682 GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_s128,
114683 GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_s128,
114684 GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_v4s32,
114685 GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_v4s32,
114686 GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_s128,
114687 GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_s128,
114688 GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_s128,
114689 GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_s128,
114690 GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_s128,
114691 GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_v4s32,
114692 GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_v4s32,
114693 GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
114694 GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114695 GIR_Copy, /*NewInsnID*/38, /*OldInsnID*/0, /*OpIdx*/1, // Rn
114696 GIR_ConstrainSelectedInstOperands, /*InsnID*/38,
114697 GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f32),
114698 GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114699 GIR_AddSimpleTempRegister, /*InsnID*/37, /*TempRegID*/37,
114700 GIR_ConstrainSelectedInstOperands, /*InsnID*/37,
114701 GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
114702 GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114703 GIR_AddSimpleTempRegister, /*InsnID*/36, /*TempRegID*/36,
114704 GIR_AddImm8, /*InsnID*/36, /*Imm*/64,
114705 GIR_AddImm8, /*InsnID*/36, /*Imm*/16,
114706 GIR_ConstrainSelectedInstOperands, /*InsnID*/36,
114707 GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
114708 GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114709 GIR_AddImm8, /*InsnID*/35, /*Imm*/127,
114710 GIR_AddImm, /*InsnID*/35, /*Imm*/GIMT_Encode8(264),
114711 GIR_ConstrainSelectedInstOperands, /*InsnID*/35,
114712 GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
114713 GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114714 GIR_AddImm8, /*InsnID*/34, /*Imm*/1,
114715 GIR_AddImm8, /*InsnID*/34, /*Imm*/0,
114716 GIR_ConstrainSelectedInstOperands, /*InsnID*/34,
114717 GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
114718 GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114719 GIR_Copy, /*NewInsnID*/33, /*OldInsnID*/0, /*OpIdx*/1, // Rn
114720 GIR_AddImm8, /*InsnID*/33, /*Imm*/16,
114721 GIR_ConstrainSelectedInstOperands, /*InsnID*/33,
114722 GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
114723 GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114724 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/32,
114725 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/33,
114726 GIR_ConstrainSelectedInstOperands, /*InsnID*/32,
114727 GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
114728 GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114729 GIR_Copy, /*NewInsnID*/31, /*OldInsnID*/0, /*OpIdx*/1, // Rn
114730 GIR_ConstrainSelectedInstOperands, /*InsnID*/31,
114731 GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f32),
114732 GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114733 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/30,
114734 GIR_ConstrainSelectedInstOperands, /*InsnID*/30,
114735 GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
114736 GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114737 GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/29,
114738 GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/31,
114739 GIR_ConstrainSelectedInstOperands, /*InsnID*/29,
114740 GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
114741 GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114742 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/28,
114743 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/34,
114744 GIR_ConstrainSelectedInstOperands, /*InsnID*/28,
114745 GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
114746 GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114747 GIR_Copy, /*NewInsnID*/27, /*OldInsnID*/0, /*OpIdx*/1, // Rn
114748 GIR_ConstrainSelectedInstOperands, /*InsnID*/27,
114749 GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f32),
114750 GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114751 GIR_AddSimpleTempRegister, /*InsnID*/26, /*TempRegID*/26,
114752 GIR_ConstrainSelectedInstOperands, /*InsnID*/26,
114753 GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
114754 GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114755 GIR_Copy, /*NewInsnID*/25, /*OldInsnID*/0, /*OpIdx*/1, // Rn
114756 GIR_ConstrainSelectedInstOperands, /*InsnID*/25,
114757 GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f32),
114758 GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114759 GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/24,
114760 GIR_ConstrainSelectedInstOperands, /*InsnID*/24,
114761 GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
114762 GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114763 GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/23,
114764 GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/25,
114765 GIR_ConstrainSelectedInstOperands, /*InsnID*/23,
114766 GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
114767 GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114768 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/22,
114769 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/27,
114770 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/35,
114771 GIR_ConstrainSelectedInstOperands, /*InsnID*/22,
114772 GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
114773 GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114774 GIR_CopySubReg, /*NewInsnID*/21, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
114775 GIR_ConstrainOperandRC, /*InsnID*/21, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
114776 GIR_ConstrainOperandRC, /*InsnID*/21, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
114777 GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
114778 GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114779 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/20,
114780 GIR_ConstrainSelectedInstOperands, /*InsnID*/20,
114781 GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f32),
114782 GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114783 GIR_AddSimpleTempRegister, /*InsnID*/19, /*TempRegID*/19,
114784 GIR_ConstrainSelectedInstOperands, /*InsnID*/19,
114785 GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
114786 GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114787 GIR_AddSimpleTempRegister, /*InsnID*/18, /*TempRegID*/18,
114788 GIR_AddImm8, /*InsnID*/18, /*Imm*/64,
114789 GIR_AddImm8, /*InsnID*/18, /*Imm*/16,
114790 GIR_ConstrainSelectedInstOperands, /*InsnID*/18,
114791 GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
114792 GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114793 GIR_AddImm8, /*InsnID*/17, /*Imm*/127,
114794 GIR_AddImm, /*InsnID*/17, /*Imm*/GIMT_Encode8(264),
114795 GIR_ConstrainSelectedInstOperands, /*InsnID*/17,
114796 GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
114797 GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114798 GIR_AddImm8, /*InsnID*/16, /*Imm*/1,
114799 GIR_AddImm8, /*InsnID*/16, /*Imm*/0,
114800 GIR_ConstrainSelectedInstOperands, /*InsnID*/16,
114801 GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
114802 GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114803 GIR_Copy, /*NewInsnID*/15, /*OldInsnID*/0, /*OpIdx*/1, // Rn
114804 GIR_AddImm8, /*InsnID*/15, /*Imm*/16,
114805 GIR_ConstrainSelectedInstOperands, /*InsnID*/15,
114806 GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
114807 GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114808 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14,
114809 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/15,
114810 GIR_ConstrainSelectedInstOperands, /*InsnID*/14,
114811 GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
114812 GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114813 GIR_CopySubReg, /*NewInsnID*/13, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
114814 GIR_ConstrainOperandRC, /*InsnID*/13, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
114815 GIR_ConstrainOperandRC, /*InsnID*/13, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
114816 GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
114817 GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114818 GIR_AddSimpleTempRegister, /*InsnID*/12, /*TempRegID*/12,
114819 GIR_ConstrainSelectedInstOperands, /*InsnID*/12,
114820 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f32),
114821 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114822 GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11,
114823 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
114824 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
114825 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114826 GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
114827 GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/13,
114828 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
114829 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
114830 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114831 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
114832 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/16,
114833 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
114834 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
114835 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114836 GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
114837 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
114838 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
114839 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
114840 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114841 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
114842 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
114843 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f32),
114844 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114845 GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
114846 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
114847 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
114848 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114849 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
114850 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
114851 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
114852 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
114853 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114854 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
114855 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
114856 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f32),
114857 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114858 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
114859 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
114860 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
114861 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114862 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
114863 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
114864 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
114865 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
114866 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
114867 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
114868 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/8,
114869 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/17,
114870 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
114871 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
114872 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
114873 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
114874 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/21,
114875 GIR_RootConstrainSelectedInstOperands,
114876 // GIR_Coverage, 6684,
114877 GIR_EraseRootFromParent_Done,
114878 // Label 6512: @311464
114879 GIM_Reject,
114880 // Label 6508: @311465
114881 GIM_Reject,
114882 // Label 6500: @311466
114883 GIM_Reject,
114884 // Label 88: @311467
114885 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6521*/ GIMT_Encode4(312889),
114886 /*GILLT_s16*//*Label 6513*/ GIMT_Encode4(311518),
114887 /*GILLT_s32*//*Label 6514*/ GIMT_Encode4(311549),
114888 /*GILLT_s64*//*Label 6515*/ GIMT_Encode4(311580), GIMT_Encode4(0),
114889 /*GILLT_v2s32*//*Label 6516*/ GIMT_Encode4(311611),
114890 /*GILLT_v2s64*//*Label 6517*/ GIMT_Encode4(311642),
114891 /*GILLT_v4s16*//*Label 6518*/ GIMT_Encode4(311673),
114892 /*GILLT_v4s32*//*Label 6519*/ GIMT_Encode4(311704), GIMT_Encode4(0),
114893 /*GILLT_v8s16*//*Label 6520*/ GIMT_Encode4(311735),
114894 // Label 6513: @311518
114895 GIM_Try, /*On fail goto*//*Label 6522*/ GIMT_Encode4(311548), // Rule ID 552 //
114896 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
114897 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
114898 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
114899 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
114900 // (frint:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTXHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
114901 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXHr),
114902 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114903 GIR_RootConstrainSelectedInstOperands,
114904 // GIR_Coverage, 552,
114905 GIR_Done,
114906 // Label 6522: @311548
114907 GIM_Reject,
114908 // Label 6514: @311549
114909 GIM_Try, /*On fail goto*//*Label 6523*/ GIMT_Encode4(311579), // Rule ID 554 //
114910 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
114911 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
114912 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
114913 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
114914 // (frint:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTXSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
114915 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXSr),
114916 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114917 GIR_RootConstrainSelectedInstOperands,
114918 // GIR_Coverage, 554,
114919 GIR_Done,
114920 // Label 6523: @311579
114921 GIM_Reject,
114922 // Label 6515: @311580
114923 GIM_Try, /*On fail goto*//*Label 6524*/ GIMT_Encode4(311610), // Rule ID 556 //
114924 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
114925 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
114926 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
114927 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
114928 // (frint:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTXDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
114929 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXDr),
114930 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114931 GIR_RootConstrainSelectedInstOperands,
114932 // GIR_Coverage, 556,
114933 GIR_Done,
114934 // Label 6524: @311610
114935 GIM_Reject,
114936 // Label 6516: @311611
114937 GIM_Try, /*On fail goto*//*Label 6525*/ GIMT_Encode4(311641), // Rule ID 910 //
114938 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
114939 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
114940 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
114941 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
114942 // (frint:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
114943 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv2f32),
114944 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114945 GIR_RootConstrainSelectedInstOperands,
114946 // GIR_Coverage, 910,
114947 GIR_Done,
114948 // Label 6525: @311641
114949 GIM_Reject,
114950 // Label 6517: @311642
114951 GIM_Try, /*On fail goto*//*Label 6526*/ GIMT_Encode4(311672), // Rule ID 914 //
114952 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
114953 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
114954 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
114955 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
114956 // (frint:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
114957 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv2f64),
114958 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114959 GIR_RootConstrainSelectedInstOperands,
114960 // GIR_Coverage, 914,
114961 GIR_Done,
114962 // Label 6526: @311672
114963 GIM_Reject,
114964 // Label 6518: @311673
114965 GIM_Try, /*On fail goto*//*Label 6527*/ GIMT_Encode4(311703), // Rule ID 906 //
114966 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
114967 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
114968 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
114969 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
114970 // (frint:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
114971 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f16),
114972 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114973 GIR_RootConstrainSelectedInstOperands,
114974 // GIR_Coverage, 906,
114975 GIR_Done,
114976 // Label 6527: @311703
114977 GIM_Reject,
114978 // Label 6519: @311704
114979 GIM_Try, /*On fail goto*//*Label 6528*/ GIMT_Encode4(311734), // Rule ID 912 //
114980 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
114981 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
114982 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
114983 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
114984 // (frint:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
114985 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f32),
114986 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
114987 GIR_RootConstrainSelectedInstOperands,
114988 // GIR_Coverage, 912,
114989 GIR_Done,
114990 // Label 6528: @311734
114991 GIM_Reject,
114992 // Label 6520: @311735
114993 GIM_Try, /*On fail goto*//*Label 6529*/ GIMT_Encode4(312888),
114994 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
114995 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
114996 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
114997 GIM_Try, /*On fail goto*//*Label 6530*/ GIMT_Encode4(311770), // Rule ID 908 //
114998 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
114999 // (frint:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
115000 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv8f16),
115001 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
115002 GIR_RootConstrainSelectedInstOperands,
115003 // GIR_Coverage, 908,
115004 GIR_Done,
115005 // Label 6530: @311770
115006 GIM_Try, /*On fail goto*//*Label 6531*/ GIMT_Encode4(311955), // Rule ID 6704 //
115007 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
115008 // (frint:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTXv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTXv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
115009 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
115010 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
115011 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
115012 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
115013 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
115014 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
115015 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
115016 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
115017 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
115018 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115019 GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
115020 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
115021 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f32),
115022 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115023 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
115024 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
115025 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
115026 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115027 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
115028 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
115029 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
115030 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
115031 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115032 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
115033 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
115034 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f32),
115035 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115036 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
115037 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
115038 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
115039 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115040 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
115041 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
115042 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
115043 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115044 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
115045 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
115046 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115047 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
115048 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
115049 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
115050 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
115051 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
115052 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
115053 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
115054 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
115055 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
115056 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
115057 GIR_RootConstrainSelectedInstOperands,
115058 // GIR_Coverage, 6704,
115059 GIR_EraseRootFromParent_Done,
115060 // Label 6531: @311955
115061 GIM_Try, /*On fail goto*//*Label 6532*/ GIMT_Encode4(312090), // Rule ID 6706 //
115062 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16),
115063 // (frint:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (BFCVTN2:{ *:[v8bf16] } (BFCVTN:{ *:[v8bf16] } (FRINTXv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })))), (FRINTXv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)))
115064 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
115065 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
115066 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
115067 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
115068 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
115069 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
115070 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
115071 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115072 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, // Rn
115073 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
115074 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f32),
115075 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115076 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
115077 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
115078 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
115079 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115080 GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
115081 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
115082 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
115083 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
115084 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115085 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
115086 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
115087 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f32),
115088 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115089 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
115090 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
115091 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN),
115092 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115093 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
115094 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
115095 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN2),
115096 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
115097 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
115098 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
115099 GIR_RootConstrainSelectedInstOperands,
115100 // GIR_Coverage, 6706,
115101 GIR_EraseRootFromParent_Done,
115102 // Label 6532: @312090
115103 GIM_Try, /*On fail goto*//*Label 6533*/ GIMT_Encode4(312887), // Rule ID 6708 //
115104 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoBF16),
115105 // (frint:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (UZP2v8i16:{ *:[v8bf16] } (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FRINTXv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), (FRINTXv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FRINTXv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FRINTXv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), 64:{ *:[i32] }, 16:{ *:[i32] })), (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FRINTXv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), (FRINTXv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FRINTXv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FRINTXv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), 64:{ *:[i32] }, 16:{ *:[i32] })))
115106 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
115107 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
115108 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
115109 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
115110 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
115111 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
115112 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
115113 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
115114 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s128,
115115 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s128,
115116 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
115117 GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_v4s32,
115118 GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_v4s16,
115119 GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s128,
115120 GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_s128,
115121 GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_s128,
115122 GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_s128,
115123 GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_s128,
115124 GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_v4s32,
115125 GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_v4s32,
115126 GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_v4s16,
115127 GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s128,
115128 GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s128,
115129 GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_v4s32,
115130 GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_v4s32,
115131 GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_v4s32,
115132 GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_v4s32,
115133 GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_s128,
115134 GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_s128,
115135 GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_v4s32,
115136 GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_v4s32,
115137 GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_s128,
115138 GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_s128,
115139 GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_s128,
115140 GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_s128,
115141 GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_s128,
115142 GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_v4s32,
115143 GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_v4s32,
115144 GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
115145 GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115146 GIR_Copy, /*NewInsnID*/38, /*OldInsnID*/0, /*OpIdx*/1, // Rn
115147 GIR_ConstrainSelectedInstOperands, /*InsnID*/38,
115148 GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f32),
115149 GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115150 GIR_AddSimpleTempRegister, /*InsnID*/37, /*TempRegID*/37,
115151 GIR_ConstrainSelectedInstOperands, /*InsnID*/37,
115152 GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
115153 GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115154 GIR_AddSimpleTempRegister, /*InsnID*/36, /*TempRegID*/36,
115155 GIR_AddImm8, /*InsnID*/36, /*Imm*/64,
115156 GIR_AddImm8, /*InsnID*/36, /*Imm*/16,
115157 GIR_ConstrainSelectedInstOperands, /*InsnID*/36,
115158 GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
115159 GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115160 GIR_AddImm8, /*InsnID*/35, /*Imm*/127,
115161 GIR_AddImm, /*InsnID*/35, /*Imm*/GIMT_Encode8(264),
115162 GIR_ConstrainSelectedInstOperands, /*InsnID*/35,
115163 GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
115164 GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115165 GIR_AddImm8, /*InsnID*/34, /*Imm*/1,
115166 GIR_AddImm8, /*InsnID*/34, /*Imm*/0,
115167 GIR_ConstrainSelectedInstOperands, /*InsnID*/34,
115168 GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
115169 GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115170 GIR_Copy, /*NewInsnID*/33, /*OldInsnID*/0, /*OpIdx*/1, // Rn
115171 GIR_AddImm8, /*InsnID*/33, /*Imm*/16,
115172 GIR_ConstrainSelectedInstOperands, /*InsnID*/33,
115173 GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
115174 GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115175 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/32,
115176 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/33,
115177 GIR_ConstrainSelectedInstOperands, /*InsnID*/32,
115178 GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
115179 GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115180 GIR_Copy, /*NewInsnID*/31, /*OldInsnID*/0, /*OpIdx*/1, // Rn
115181 GIR_ConstrainSelectedInstOperands, /*InsnID*/31,
115182 GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f32),
115183 GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115184 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/30,
115185 GIR_ConstrainSelectedInstOperands, /*InsnID*/30,
115186 GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
115187 GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115188 GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/29,
115189 GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/31,
115190 GIR_ConstrainSelectedInstOperands, /*InsnID*/29,
115191 GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
115192 GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115193 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/28,
115194 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/34,
115195 GIR_ConstrainSelectedInstOperands, /*InsnID*/28,
115196 GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
115197 GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115198 GIR_Copy, /*NewInsnID*/27, /*OldInsnID*/0, /*OpIdx*/1, // Rn
115199 GIR_ConstrainSelectedInstOperands, /*InsnID*/27,
115200 GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f32),
115201 GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115202 GIR_AddSimpleTempRegister, /*InsnID*/26, /*TempRegID*/26,
115203 GIR_ConstrainSelectedInstOperands, /*InsnID*/26,
115204 GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
115205 GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115206 GIR_Copy, /*NewInsnID*/25, /*OldInsnID*/0, /*OpIdx*/1, // Rn
115207 GIR_ConstrainSelectedInstOperands, /*InsnID*/25,
115208 GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f32),
115209 GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115210 GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/24,
115211 GIR_ConstrainSelectedInstOperands, /*InsnID*/24,
115212 GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
115213 GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115214 GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/23,
115215 GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/25,
115216 GIR_ConstrainSelectedInstOperands, /*InsnID*/23,
115217 GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
115218 GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115219 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/22,
115220 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/27,
115221 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/35,
115222 GIR_ConstrainSelectedInstOperands, /*InsnID*/22,
115223 GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
115224 GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115225 GIR_CopySubReg, /*NewInsnID*/21, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
115226 GIR_ConstrainOperandRC, /*InsnID*/21, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
115227 GIR_ConstrainOperandRC, /*InsnID*/21, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
115228 GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
115229 GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115230 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/20,
115231 GIR_ConstrainSelectedInstOperands, /*InsnID*/20,
115232 GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f32),
115233 GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115234 GIR_AddSimpleTempRegister, /*InsnID*/19, /*TempRegID*/19,
115235 GIR_ConstrainSelectedInstOperands, /*InsnID*/19,
115236 GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
115237 GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115238 GIR_AddSimpleTempRegister, /*InsnID*/18, /*TempRegID*/18,
115239 GIR_AddImm8, /*InsnID*/18, /*Imm*/64,
115240 GIR_AddImm8, /*InsnID*/18, /*Imm*/16,
115241 GIR_ConstrainSelectedInstOperands, /*InsnID*/18,
115242 GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
115243 GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115244 GIR_AddImm8, /*InsnID*/17, /*Imm*/127,
115245 GIR_AddImm, /*InsnID*/17, /*Imm*/GIMT_Encode8(264),
115246 GIR_ConstrainSelectedInstOperands, /*InsnID*/17,
115247 GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
115248 GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115249 GIR_AddImm8, /*InsnID*/16, /*Imm*/1,
115250 GIR_AddImm8, /*InsnID*/16, /*Imm*/0,
115251 GIR_ConstrainSelectedInstOperands, /*InsnID*/16,
115252 GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
115253 GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115254 GIR_Copy, /*NewInsnID*/15, /*OldInsnID*/0, /*OpIdx*/1, // Rn
115255 GIR_AddImm8, /*InsnID*/15, /*Imm*/16,
115256 GIR_ConstrainSelectedInstOperands, /*InsnID*/15,
115257 GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
115258 GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115259 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14,
115260 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/15,
115261 GIR_ConstrainSelectedInstOperands, /*InsnID*/14,
115262 GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
115263 GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115264 GIR_CopySubReg, /*NewInsnID*/13, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
115265 GIR_ConstrainOperandRC, /*InsnID*/13, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
115266 GIR_ConstrainOperandRC, /*InsnID*/13, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
115267 GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
115268 GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115269 GIR_AddSimpleTempRegister, /*InsnID*/12, /*TempRegID*/12,
115270 GIR_ConstrainSelectedInstOperands, /*InsnID*/12,
115271 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f32),
115272 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115273 GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11,
115274 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
115275 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
115276 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115277 GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
115278 GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/13,
115279 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
115280 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
115281 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115282 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
115283 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/16,
115284 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
115285 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
115286 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115287 GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
115288 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
115289 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
115290 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
115291 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115292 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
115293 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
115294 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f32),
115295 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115296 GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
115297 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
115298 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
115299 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115300 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
115301 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
115302 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
115303 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
115304 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115305 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
115306 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
115307 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f32),
115308 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115309 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
115310 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
115311 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
115312 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115313 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
115314 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
115315 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
115316 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
115317 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115318 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
115319 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/8,
115320 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/17,
115321 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
115322 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
115323 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
115324 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
115325 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/21,
115326 GIR_RootConstrainSelectedInstOperands,
115327 // GIR_Coverage, 6708,
115328 GIR_EraseRootFromParent_Done,
115329 // Label 6533: @312887
115330 GIM_Reject,
115331 // Label 6529: @312888
115332 GIM_Reject,
115333 // Label 6521: @312889
115334 GIM_Reject,
115335 // Label 89: @312890
115336 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6542*/ GIMT_Encode4(314312),
115337 /*GILLT_s16*//*Label 6534*/ GIMT_Encode4(312941),
115338 /*GILLT_s32*//*Label 6535*/ GIMT_Encode4(312972),
115339 /*GILLT_s64*//*Label 6536*/ GIMT_Encode4(313003), GIMT_Encode4(0),
115340 /*GILLT_v2s32*//*Label 6537*/ GIMT_Encode4(313034),
115341 /*GILLT_v2s64*//*Label 6538*/ GIMT_Encode4(313065),
115342 /*GILLT_v4s16*//*Label 6539*/ GIMT_Encode4(313096),
115343 /*GILLT_v4s32*//*Label 6540*/ GIMT_Encode4(313127), GIMT_Encode4(0),
115344 /*GILLT_v8s16*//*Label 6541*/ GIMT_Encode4(313158),
115345 // Label 6534: @312941
115346 GIM_Try, /*On fail goto*//*Label 6543*/ GIMT_Encode4(312971), // Rule ID 528 //
115347 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
115348 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
115349 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
115350 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
115351 // (fnearbyint:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FRINTIHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
115352 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIHr),
115353 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
115354 GIR_RootConstrainSelectedInstOperands,
115355 // GIR_Coverage, 528,
115356 GIR_Done,
115357 // Label 6543: @312971
115358 GIM_Reject,
115359 // Label 6535: @312972
115360 GIM_Try, /*On fail goto*//*Label 6544*/ GIMT_Encode4(313002), // Rule ID 530 //
115361 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
115362 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
115363 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
115364 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
115365 // (fnearbyint:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FRINTISr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
115366 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTISr),
115367 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
115368 GIR_RootConstrainSelectedInstOperands,
115369 // GIR_Coverage, 530,
115370 GIR_Done,
115371 // Label 6544: @313002
115372 GIM_Reject,
115373 // Label 6536: @313003
115374 GIM_Try, /*On fail goto*//*Label 6545*/ GIMT_Encode4(313033), // Rule ID 532 //
115375 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
115376 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
115377 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
115378 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
115379 // (fnearbyint:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FRINTIDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
115380 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIDr),
115381 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
115382 GIR_RootConstrainSelectedInstOperands,
115383 // GIR_Coverage, 532,
115384 GIR_Done,
115385 // Label 6545: @313033
115386 GIM_Reject,
115387 // Label 6537: @313034
115388 GIM_Try, /*On fail goto*//*Label 6546*/ GIMT_Encode4(313064), // Rule ID 870 //
115389 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
115390 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
115391 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
115392 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
115393 // (fnearbyint:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FRINTIv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
115394 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv2f32),
115395 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
115396 GIR_RootConstrainSelectedInstOperands,
115397 // GIR_Coverage, 870,
115398 GIR_Done,
115399 // Label 6546: @313064
115400 GIM_Reject,
115401 // Label 6538: @313065
115402 GIM_Try, /*On fail goto*//*Label 6547*/ GIMT_Encode4(313095), // Rule ID 874 //
115403 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
115404 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
115405 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
115406 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
115407 // (fnearbyint:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FRINTIv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
115408 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv2f64),
115409 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
115410 GIR_RootConstrainSelectedInstOperands,
115411 // GIR_Coverage, 874,
115412 GIR_Done,
115413 // Label 6547: @313095
115414 GIM_Reject,
115415 // Label 6539: @313096
115416 GIM_Try, /*On fail goto*//*Label 6548*/ GIMT_Encode4(313126), // Rule ID 866 //
115417 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
115418 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
115419 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
115420 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
115421 // (fnearbyint:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FRINTIv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
115422 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f16),
115423 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
115424 GIR_RootConstrainSelectedInstOperands,
115425 // GIR_Coverage, 866,
115426 GIR_Done,
115427 // Label 6548: @313126
115428 GIM_Reject,
115429 // Label 6540: @313127
115430 GIM_Try, /*On fail goto*//*Label 6549*/ GIMT_Encode4(313157), // Rule ID 872 //
115431 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
115432 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
115433 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
115434 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
115435 // (fnearbyint:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FRINTIv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
115436 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f32),
115437 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
115438 GIR_RootConstrainSelectedInstOperands,
115439 // GIR_Coverage, 872,
115440 GIR_Done,
115441 // Label 6549: @313157
115442 GIM_Reject,
115443 // Label 6541: @313158
115444 GIM_Try, /*On fail goto*//*Label 6550*/ GIMT_Encode4(314311),
115445 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
115446 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
115447 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
115448 GIM_Try, /*On fail goto*//*Label 6551*/ GIMT_Encode4(313193), // Rule ID 868 //
115449 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
115450 // (fnearbyint:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FRINTIv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
115451 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv8f16),
115452 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
115453 GIR_RootConstrainSelectedInstOperands,
115454 // GIR_Coverage, 868,
115455 GIR_Done,
115456 // Label 6551: @313193
115457 GIM_Try, /*On fail goto*//*Label 6552*/ GIMT_Encode4(313378), // Rule ID 6686 //
115458 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
115459 // (fnearbyint:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTIv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTIv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
115460 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
115461 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
115462 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
115463 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
115464 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
115465 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
115466 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
115467 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
115468 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
115469 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115470 GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
115471 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
115472 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f32),
115473 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115474 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
115475 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
115476 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
115477 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115478 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
115479 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
115480 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
115481 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
115482 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115483 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
115484 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
115485 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f32),
115486 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115487 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
115488 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
115489 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
115490 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115491 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
115492 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
115493 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
115494 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115495 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
115496 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
115497 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115498 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
115499 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
115500 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
115501 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
115502 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
115503 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
115504 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
115505 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
115506 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
115507 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
115508 GIR_RootConstrainSelectedInstOperands,
115509 // GIR_Coverage, 6686,
115510 GIR_EraseRootFromParent_Done,
115511 // Label 6552: @313378
115512 GIM_Try, /*On fail goto*//*Label 6553*/ GIMT_Encode4(313513), // Rule ID 6688 //
115513 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16),
115514 // (fnearbyint:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (BFCVTN2:{ *:[v8bf16] } (BFCVTN:{ *:[v8bf16] } (FRINTIv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })))), (FRINTIv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)))
115515 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
115516 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
115517 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
115518 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
115519 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
115520 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
115521 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
115522 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115523 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, // Rn
115524 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
115525 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f32),
115526 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115527 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
115528 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
115529 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
115530 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115531 GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
115532 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
115533 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
115534 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
115535 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115536 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
115537 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
115538 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f32),
115539 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115540 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
115541 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
115542 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN),
115543 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115544 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
115545 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
115546 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN2),
115547 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
115548 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
115549 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
115550 GIR_RootConstrainSelectedInstOperands,
115551 // GIR_Coverage, 6688,
115552 GIR_EraseRootFromParent_Done,
115553 // Label 6553: @313513
115554 GIM_Try, /*On fail goto*//*Label 6554*/ GIMT_Encode4(314310), // Rule ID 6690 //
115555 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoBF16),
115556 // (fnearbyint:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (UZP2v8i16:{ *:[v8bf16] } (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FRINTIv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), (FRINTIv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FRINTIv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FRINTIv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] }))), 64:{ *:[i32] }, 16:{ *:[i32] })), (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FRINTIv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), (FRINTIv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FRINTIv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FRINTIv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn)), 64:{ *:[i32] }, 16:{ *:[i32] })))
115557 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
115558 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
115559 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
115560 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
115561 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
115562 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
115563 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
115564 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
115565 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s128,
115566 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s128,
115567 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
115568 GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_v4s32,
115569 GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_v4s16,
115570 GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s128,
115571 GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_s128,
115572 GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_s128,
115573 GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_s128,
115574 GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_s128,
115575 GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_v4s32,
115576 GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_v4s32,
115577 GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_v4s16,
115578 GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s128,
115579 GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s128,
115580 GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_v4s32,
115581 GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_v4s32,
115582 GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_v4s32,
115583 GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_v4s32,
115584 GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_s128,
115585 GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_s128,
115586 GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_v4s32,
115587 GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_v4s32,
115588 GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_s128,
115589 GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_s128,
115590 GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_s128,
115591 GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_s128,
115592 GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_s128,
115593 GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_v4s32,
115594 GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_v4s32,
115595 GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
115596 GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115597 GIR_Copy, /*NewInsnID*/38, /*OldInsnID*/0, /*OpIdx*/1, // Rn
115598 GIR_ConstrainSelectedInstOperands, /*InsnID*/38,
115599 GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f32),
115600 GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115601 GIR_AddSimpleTempRegister, /*InsnID*/37, /*TempRegID*/37,
115602 GIR_ConstrainSelectedInstOperands, /*InsnID*/37,
115603 GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
115604 GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115605 GIR_AddSimpleTempRegister, /*InsnID*/36, /*TempRegID*/36,
115606 GIR_AddImm8, /*InsnID*/36, /*Imm*/64,
115607 GIR_AddImm8, /*InsnID*/36, /*Imm*/16,
115608 GIR_ConstrainSelectedInstOperands, /*InsnID*/36,
115609 GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
115610 GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115611 GIR_AddImm8, /*InsnID*/35, /*Imm*/127,
115612 GIR_AddImm, /*InsnID*/35, /*Imm*/GIMT_Encode8(264),
115613 GIR_ConstrainSelectedInstOperands, /*InsnID*/35,
115614 GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
115615 GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115616 GIR_AddImm8, /*InsnID*/34, /*Imm*/1,
115617 GIR_AddImm8, /*InsnID*/34, /*Imm*/0,
115618 GIR_ConstrainSelectedInstOperands, /*InsnID*/34,
115619 GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
115620 GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115621 GIR_Copy, /*NewInsnID*/33, /*OldInsnID*/0, /*OpIdx*/1, // Rn
115622 GIR_AddImm8, /*InsnID*/33, /*Imm*/16,
115623 GIR_ConstrainSelectedInstOperands, /*InsnID*/33,
115624 GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
115625 GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115626 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/32,
115627 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/33,
115628 GIR_ConstrainSelectedInstOperands, /*InsnID*/32,
115629 GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
115630 GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115631 GIR_Copy, /*NewInsnID*/31, /*OldInsnID*/0, /*OpIdx*/1, // Rn
115632 GIR_ConstrainSelectedInstOperands, /*InsnID*/31,
115633 GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f32),
115634 GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115635 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/30,
115636 GIR_ConstrainSelectedInstOperands, /*InsnID*/30,
115637 GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
115638 GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115639 GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/29,
115640 GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/31,
115641 GIR_ConstrainSelectedInstOperands, /*InsnID*/29,
115642 GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
115643 GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115644 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/28,
115645 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/34,
115646 GIR_ConstrainSelectedInstOperands, /*InsnID*/28,
115647 GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
115648 GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115649 GIR_Copy, /*NewInsnID*/27, /*OldInsnID*/0, /*OpIdx*/1, // Rn
115650 GIR_ConstrainSelectedInstOperands, /*InsnID*/27,
115651 GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f32),
115652 GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115653 GIR_AddSimpleTempRegister, /*InsnID*/26, /*TempRegID*/26,
115654 GIR_ConstrainSelectedInstOperands, /*InsnID*/26,
115655 GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
115656 GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115657 GIR_Copy, /*NewInsnID*/25, /*OldInsnID*/0, /*OpIdx*/1, // Rn
115658 GIR_ConstrainSelectedInstOperands, /*InsnID*/25,
115659 GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f32),
115660 GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115661 GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/24,
115662 GIR_ConstrainSelectedInstOperands, /*InsnID*/24,
115663 GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
115664 GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115665 GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/23,
115666 GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/25,
115667 GIR_ConstrainSelectedInstOperands, /*InsnID*/23,
115668 GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
115669 GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115670 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/22,
115671 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/27,
115672 GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/35,
115673 GIR_ConstrainSelectedInstOperands, /*InsnID*/22,
115674 GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
115675 GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115676 GIR_CopySubReg, /*NewInsnID*/21, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
115677 GIR_ConstrainOperandRC, /*InsnID*/21, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
115678 GIR_ConstrainOperandRC, /*InsnID*/21, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
115679 GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
115680 GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115681 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/20,
115682 GIR_ConstrainSelectedInstOperands, /*InsnID*/20,
115683 GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f32),
115684 GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115685 GIR_AddSimpleTempRegister, /*InsnID*/19, /*TempRegID*/19,
115686 GIR_ConstrainSelectedInstOperands, /*InsnID*/19,
115687 GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
115688 GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115689 GIR_AddSimpleTempRegister, /*InsnID*/18, /*TempRegID*/18,
115690 GIR_AddImm8, /*InsnID*/18, /*Imm*/64,
115691 GIR_AddImm8, /*InsnID*/18, /*Imm*/16,
115692 GIR_ConstrainSelectedInstOperands, /*InsnID*/18,
115693 GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
115694 GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115695 GIR_AddImm8, /*InsnID*/17, /*Imm*/127,
115696 GIR_AddImm, /*InsnID*/17, /*Imm*/GIMT_Encode8(264),
115697 GIR_ConstrainSelectedInstOperands, /*InsnID*/17,
115698 GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
115699 GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115700 GIR_AddImm8, /*InsnID*/16, /*Imm*/1,
115701 GIR_AddImm8, /*InsnID*/16, /*Imm*/0,
115702 GIR_ConstrainSelectedInstOperands, /*InsnID*/16,
115703 GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
115704 GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115705 GIR_Copy, /*NewInsnID*/15, /*OldInsnID*/0, /*OpIdx*/1, // Rn
115706 GIR_AddImm8, /*InsnID*/15, /*Imm*/16,
115707 GIR_ConstrainSelectedInstOperands, /*InsnID*/15,
115708 GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
115709 GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115710 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14,
115711 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/15,
115712 GIR_ConstrainSelectedInstOperands, /*InsnID*/14,
115713 GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
115714 GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115715 GIR_CopySubReg, /*NewInsnID*/13, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
115716 GIR_ConstrainOperandRC, /*InsnID*/13, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
115717 GIR_ConstrainOperandRC, /*InsnID*/13, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
115718 GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
115719 GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115720 GIR_AddSimpleTempRegister, /*InsnID*/12, /*TempRegID*/12,
115721 GIR_ConstrainSelectedInstOperands, /*InsnID*/12,
115722 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f32),
115723 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115724 GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11,
115725 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
115726 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
115727 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115728 GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
115729 GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/13,
115730 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
115731 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
115732 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115733 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
115734 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/16,
115735 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
115736 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
115737 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115738 GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
115739 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
115740 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
115741 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
115742 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115743 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
115744 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
115745 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f32),
115746 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115747 GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
115748 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
115749 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
115750 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115751 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
115752 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
115753 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
115754 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
115755 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115756 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
115757 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
115758 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f32),
115759 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115760 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
115761 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
115762 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
115763 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115764 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
115765 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
115766 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
115767 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
115768 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115769 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
115770 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/8,
115771 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/17,
115772 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
115773 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
115774 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
115775 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
115776 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/21,
115777 GIR_RootConstrainSelectedInstOperands,
115778 // GIR_Coverage, 6690,
115779 GIR_EraseRootFromParent_Done,
115780 // Label 6554: @314310
115781 GIM_Reject,
115782 // Label 6550: @314311
115783 GIM_Reject,
115784 // Label 6542: @314312
115785 GIM_Reject,
115786 // Label 90: @314313
115787 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6563*/ GIMT_Encode4(316715),
115788 /*GILLT_s16*//*Label 6555*/ GIMT_Encode4(314364),
115789 /*GILLT_s32*//*Label 6556*/ GIMT_Encode4(314590),
115790 /*GILLT_s64*//*Label 6557*/ GIMT_Encode4(314816), GIMT_Encode4(0),
115791 /*GILLT_v2s32*//*Label 6558*/ GIMT_Encode4(314988),
115792 /*GILLT_v2s64*//*Label 6559*/ GIMT_Encode4(315026),
115793 /*GILLT_v4s16*//*Label 6560*/ GIMT_Encode4(315064),
115794 /*GILLT_v4s32*//*Label 6561*/ GIMT_Encode4(315102), GIMT_Encode4(0),
115795 /*GILLT_v8s16*//*Label 6562*/ GIMT_Encode4(315140),
115796 // Label 6555: @314364
115797 GIM_Try, /*On fail goto*//*Label 6564*/ GIMT_Encode4(314589),
115798 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
115799 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
115800 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
115801 GIM_Try, /*On fail goto*//*Label 6565*/ GIMT_Encode4(314470), // Rule ID 6607 //
115802 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
115803 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
115804 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
115805 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
115806 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
115807 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
115808 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
115809 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
115810 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
115811 // MIs[2] Rn
115812 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
115813 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
115814 GIM_CheckIsSafeToFold, /*NumInsns*/2,
115815 // (strict_fadd:{ *:[f16] } (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] }))
115816 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
115817 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
115818 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115819 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
115820 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
115821 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
115822 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i16p),
115823 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
115824 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
115825 GIR_RootConstrainSelectedInstOperands,
115826 // GIR_Coverage, 6607,
115827 GIR_EraseRootFromParent_Done,
115828 // Label 6565: @314470
115829 GIM_Try, /*On fail goto*//*Label 6566*/ GIMT_Encode4(314561), // Rule ID 13193 //
115830 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
115831 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
115832 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
115833 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
115834 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
115835 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
115836 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
115837 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
115838 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
115839 // MIs[2] Rn
115840 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
115841 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
115842 GIM_CheckIsSafeToFold, /*NumInsns*/2,
115843 // (strict_fadd:{ *:[f16] } (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] }))
115844 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
115845 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
115846 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115847 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
115848 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
115849 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
115850 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i16p),
115851 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
115852 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
115853 GIR_RootConstrainSelectedInstOperands,
115854 // GIR_Coverage, 13193,
115855 GIR_EraseRootFromParent_Done,
115856 // Label 6566: @314561
115857 GIM_Try, /*On fail goto*//*Label 6567*/ GIMT_Encode4(314588), // Rule ID 577 //
115858 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
115859 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
115860 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
115861 // (strict_fadd:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FADDHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
115862 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDHrr),
115863 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
115864 GIR_RootConstrainSelectedInstOperands,
115865 // GIR_Coverage, 577,
115866 GIR_Done,
115867 // Label 6567: @314588
115868 GIM_Reject,
115869 // Label 6564: @314589
115870 GIM_Reject,
115871 // Label 6556: @314590
115872 GIM_Try, /*On fail goto*//*Label 6568*/ GIMT_Encode4(314815),
115873 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
115874 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
115875 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
115876 GIM_Try, /*On fail goto*//*Label 6569*/ GIMT_Encode4(314696), // Rule ID 6605 //
115877 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
115878 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
115879 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
115880 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
115881 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
115882 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
115883 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
115884 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
115885 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
115886 // MIs[2] Rn
115887 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
115888 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
115889 GIM_CheckIsSafeToFold, /*NumInsns*/2,
115890 // (strict_fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] }))
115891 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
115892 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
115893 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115894 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
115895 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
115896 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
115897 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
115898 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
115899 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
115900 GIR_RootConstrainSelectedInstOperands,
115901 // GIR_Coverage, 6605,
115902 GIR_EraseRootFromParent_Done,
115903 // Label 6569: @314696
115904 GIM_Try, /*On fail goto*//*Label 6570*/ GIMT_Encode4(314787), // Rule ID 13191 //
115905 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
115906 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
115907 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
115908 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
115909 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
115910 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
115911 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
115912 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
115913 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
115914 // MIs[2] Rn
115915 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
115916 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
115917 GIM_CheckIsSafeToFold, /*NumInsns*/2,
115918 // (strict_fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] }))
115919 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
115920 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
115921 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
115922 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
115923 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
115924 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
115925 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
115926 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
115927 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
115928 GIR_RootConstrainSelectedInstOperands,
115929 // GIR_Coverage, 13191,
115930 GIR_EraseRootFromParent_Done,
115931 // Label 6570: @314787
115932 GIM_Try, /*On fail goto*//*Label 6571*/ GIMT_Encode4(314814), // Rule ID 579 //
115933 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
115934 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
115935 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
115936 // (strict_fadd:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FADDSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
115937 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDSrr),
115938 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
115939 GIR_RootConstrainSelectedInstOperands,
115940 // GIR_Coverage, 579,
115941 GIR_Done,
115942 // Label 6571: @314814
115943 GIM_Reject,
115944 // Label 6568: @314815
115945 GIM_Reject,
115946 // Label 6557: @314816
115947 GIM_Try, /*On fail goto*//*Label 6572*/ GIMT_Encode4(314987),
115948 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
115949 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
115950 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
115951 GIM_Try, /*On fail goto*//*Label 6573*/ GIMT_Encode4(314895), // Rule ID 6603 //
115952 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
115953 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
115954 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
115955 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
115956 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
115957 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
115958 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
115959 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
115960 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
115961 // MIs[2] Rn
115962 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
115963 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
115964 GIM_CheckIsSafeToFold, /*NumInsns*/2,
115965 // (strict_fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] })) => (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn)
115966 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i64p),
115967 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
115968 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
115969 GIR_RootConstrainSelectedInstOperands,
115970 // GIR_Coverage, 6603,
115971 GIR_EraseRootFromParent_Done,
115972 // Label 6573: @314895
115973 GIM_Try, /*On fail goto*//*Label 6574*/ GIMT_Encode4(314959), // Rule ID 13189 //
115974 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
115975 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
115976 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
115977 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
115978 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
115979 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
115980 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
115981 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
115982 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
115983 // MIs[2] Rn
115984 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
115985 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
115986 GIM_CheckIsSafeToFold, /*NumInsns*/2,
115987 // (strict_fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })) => (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn)
115988 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i64p),
115989 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
115990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
115991 GIR_RootConstrainSelectedInstOperands,
115992 // GIR_Coverage, 13189,
115993 GIR_EraseRootFromParent_Done,
115994 // Label 6574: @314959
115995 GIM_Try, /*On fail goto*//*Label 6575*/ GIMT_Encode4(314986), // Rule ID 581 //
115996 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
115997 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
115998 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
115999 // (strict_fadd:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FADDDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
116000 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDDrr),
116001 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
116002 GIR_RootConstrainSelectedInstOperands,
116003 // GIR_Coverage, 581,
116004 GIR_Done,
116005 // Label 6575: @314986
116006 GIM_Reject,
116007 // Label 6572: @314987
116008 GIM_Reject,
116009 // Label 6558: @314988
116010 GIM_Try, /*On fail goto*//*Label 6576*/ GIMT_Encode4(315025), // Rule ID 1189 //
116011 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
116012 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
116013 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
116014 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
116015 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
116016 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
116017 // (strict_fadd:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
116018 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv2f32),
116019 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
116020 GIR_RootConstrainSelectedInstOperands,
116021 // GIR_Coverage, 1189,
116022 GIR_Done,
116023 // Label 6576: @315025
116024 GIM_Reject,
116025 // Label 6559: @315026
116026 GIM_Try, /*On fail goto*//*Label 6577*/ GIMT_Encode4(315063), // Rule ID 1193 //
116027 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
116028 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
116029 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
116030 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
116031 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
116032 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
116033 // (strict_fadd:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
116034 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv2f64),
116035 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
116036 GIR_RootConstrainSelectedInstOperands,
116037 // GIR_Coverage, 1193,
116038 GIR_Done,
116039 // Label 6577: @315063
116040 GIM_Reject,
116041 // Label 6560: @315064
116042 GIM_Try, /*On fail goto*//*Label 6578*/ GIMT_Encode4(315101), // Rule ID 1185 //
116043 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
116044 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
116045 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
116046 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
116047 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
116048 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
116049 // (strict_fadd:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
116050 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f16),
116051 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
116052 GIR_RootConstrainSelectedInstOperands,
116053 // GIR_Coverage, 1185,
116054 GIR_Done,
116055 // Label 6578: @315101
116056 GIM_Reject,
116057 // Label 6561: @315102
116058 GIM_Try, /*On fail goto*//*Label 6579*/ GIMT_Encode4(315139), // Rule ID 1191 //
116059 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
116060 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
116061 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
116062 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
116063 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
116064 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
116065 // (strict_fadd:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
116066 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
116067 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
116068 GIR_RootConstrainSelectedInstOperands,
116069 // GIR_Coverage, 1191,
116070 GIR_Done,
116071 // Label 6579: @315139
116072 GIM_Reject,
116073 // Label 6562: @315140
116074 GIM_Try, /*On fail goto*//*Label 6580*/ GIMT_Encode4(316714),
116075 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
116076 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
116077 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
116078 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
116079 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
116080 GIM_Try, /*On fail goto*//*Label 6581*/ GIMT_Encode4(315182), // Rule ID 1187 //
116081 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
116082 // (strict_fadd:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
116083 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv8f16),
116084 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
116085 GIR_RootConstrainSelectedInstOperands,
116086 // GIR_Coverage, 1187,
116087 GIR_Done,
116088 // Label 6581: @315182
116089 GIM_Try, /*On fail goto*//*Label 6582*/ GIMT_Encode4(315436), // Rule ID 6715 //
116090 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
116091 // (strict_fadd:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FADDv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FADDv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
116092 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
116093 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
116094 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
116095 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
116096 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
116097 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
116098 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
116099 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
116100 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
116101 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
116102 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
116103 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
116104 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116105 GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
116106 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
116107 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
116108 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116109 GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
116110 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
116111 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
116112 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116113 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
116114 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
116115 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
116116 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
116117 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116118 GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
116119 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
116120 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116121 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
116122 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116123 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
116124 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
116125 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
116126 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116127 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
116128 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
116129 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116130 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
116131 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116132 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
116133 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
116134 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
116135 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116136 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
116137 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
116138 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
116139 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
116140 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116141 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
116142 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
116143 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
116144 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116145 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
116146 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
116147 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116148 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
116149 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
116150 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
116151 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
116152 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116153 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
116154 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
116155 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
116156 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
116157 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
116158 GIR_RootConstrainSelectedInstOperands,
116159 // GIR_Coverage, 6715,
116160 GIR_EraseRootFromParent_Done,
116161 // Label 6582: @315436
116162 GIM_Try, /*On fail goto*//*Label 6583*/ GIMT_Encode4(315640), // Rule ID 6717 //
116163 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16),
116164 // (strict_fadd:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFCVTN2:{ *:[v8bf16] } (BFCVTN:{ *:[v8bf16] } (FADDv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] })))), (FADDv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)))
116165 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
116166 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
116167 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
116168 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
116169 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
116170 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
116171 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
116172 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
116173 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
116174 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116175 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116176 GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/0, /*OpIdx*/2, // Rm
116177 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
116178 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116179 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116180 GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
116181 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
116182 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
116183 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116184 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
116185 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/8,
116186 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
116187 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
116188 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116189 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
116190 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
116191 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116192 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
116193 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116194 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
116195 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
116196 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
116197 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116198 GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
116199 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
116200 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116201 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
116202 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116203 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
116204 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
116205 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
116206 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116207 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
116208 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/4,
116209 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
116210 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN),
116211 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116212 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
116213 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
116214 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN2),
116215 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
116216 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
116217 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
116218 GIR_RootConstrainSelectedInstOperands,
116219 // GIR_Coverage, 6717,
116220 GIR_EraseRootFromParent_Done,
116221 // Label 6583: @315640
116222 GIM_Try, /*On fail goto*//*Label 6584*/ GIMT_Encode4(316713), // Rule ID 6719 //
116223 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoBF16),
116224 // (strict_fadd:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (UZP2v8i16:{ *:[v8bf16] } (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FADDv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), (FADDv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] })))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FADDv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FADDv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), 64:{ *:[i32] }, 16:{ *:[i32] })), (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FADDv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), (FADDv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FADDv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FADDv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), 64:{ *:[i32] }, 16:{ *:[i32] })))
116225 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
116226 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
116227 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
116228 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
116229 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
116230 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
116231 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
116232 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
116233 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
116234 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s16,
116235 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
116236 GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_v4s16,
116237 GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_s128,
116238 GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s128,
116239 GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_v4s32,
116240 GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_v4s32,
116241 GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_v4s16,
116242 GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_v4s32,
116243 GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_v4s16,
116244 GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_s128,
116245 GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_s128,
116246 GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s128,
116247 GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s128,
116248 GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_s128,
116249 GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_v4s32,
116250 GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_v4s32,
116251 GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_v4s16,
116252 GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_v4s32,
116253 GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_v4s16,
116254 GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_s128,
116255 GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_s128,
116256 GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_v4s32,
116257 GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_v4s32,
116258 GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_v4s32,
116259 GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_v4s32,
116260 GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_v4s32,
116261 GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_v4s32,
116262 GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_s128,
116263 GIR_MakeTempReg, /*TempRegID*/38, /*TypeID*/GILLT_s128,
116264 GIR_MakeTempReg, /*TempRegID*/39, /*TypeID*/GILLT_v4s32,
116265 GIR_MakeTempReg, /*TempRegID*/40, /*TypeID*/GILLT_v4s32,
116266 GIR_MakeTempReg, /*TempRegID*/41, /*TypeID*/GILLT_v4s32,
116267 GIR_MakeTempReg, /*TempRegID*/42, /*TypeID*/GILLT_s128,
116268 GIR_MakeTempReg, /*TempRegID*/43, /*TypeID*/GILLT_s128,
116269 GIR_MakeTempReg, /*TempRegID*/44, /*TypeID*/GILLT_s128,
116270 GIR_MakeTempReg, /*TempRegID*/45, /*TypeID*/GILLT_s128,
116271 GIR_MakeTempReg, /*TempRegID*/46, /*TypeID*/GILLT_s128,
116272 GIR_MakeTempReg, /*TempRegID*/47, /*TypeID*/GILLT_v4s32,
116273 GIR_MakeTempReg, /*TempRegID*/48, /*TypeID*/GILLT_v4s32,
116274 GIR_MakeTempReg, /*TempRegID*/49, /*TypeID*/GILLT_v4s32,
116275 GIR_BuildMI, /*InsnID*/50, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116276 GIR_AddTempRegister, /*InsnID*/50, /*TempRegID*/49, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116277 GIR_Copy, /*NewInsnID*/50, /*OldInsnID*/0, /*OpIdx*/2, // Rm
116278 GIR_ConstrainSelectedInstOperands, /*InsnID*/50,
116279 GIR_BuildMI, /*InsnID*/49, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116280 GIR_AddTempRegister, /*InsnID*/49, /*TempRegID*/48, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116281 GIR_Copy, /*NewInsnID*/49, /*OldInsnID*/0, /*OpIdx*/1, // Rn
116282 GIR_ConstrainSelectedInstOperands, /*InsnID*/49,
116283 GIR_BuildMI, /*InsnID*/48, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
116284 GIR_AddTempRegister, /*InsnID*/48, /*TempRegID*/47, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116285 GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/48,
116286 GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/49,
116287 GIR_ConstrainSelectedInstOperands, /*InsnID*/48,
116288 GIR_BuildMI, /*InsnID*/47, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
116289 GIR_AddTempRegister, /*InsnID*/47, /*TempRegID*/46, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116290 GIR_AddSimpleTempRegister, /*InsnID*/47, /*TempRegID*/47,
116291 GIR_AddImm8, /*InsnID*/47, /*Imm*/64,
116292 GIR_AddImm8, /*InsnID*/47, /*Imm*/16,
116293 GIR_ConstrainSelectedInstOperands, /*InsnID*/47,
116294 GIR_BuildMI, /*InsnID*/46, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
116295 GIR_AddTempRegister, /*InsnID*/46, /*TempRegID*/45, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116296 GIR_AddImm8, /*InsnID*/46, /*Imm*/127,
116297 GIR_AddImm, /*InsnID*/46, /*Imm*/GIMT_Encode8(264),
116298 GIR_ConstrainSelectedInstOperands, /*InsnID*/46,
116299 GIR_BuildMI, /*InsnID*/45, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
116300 GIR_AddTempRegister, /*InsnID*/45, /*TempRegID*/44, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116301 GIR_AddImm8, /*InsnID*/45, /*Imm*/1,
116302 GIR_AddImm8, /*InsnID*/45, /*Imm*/0,
116303 GIR_ConstrainSelectedInstOperands, /*InsnID*/45,
116304 GIR_BuildMI, /*InsnID*/44, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
116305 GIR_AddTempRegister, /*InsnID*/44, /*TempRegID*/43, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116306 GIR_Copy, /*NewInsnID*/44, /*OldInsnID*/0, /*OpIdx*/1, // Rn
116307 GIR_AddImm8, /*InsnID*/44, /*Imm*/16,
116308 GIR_ConstrainSelectedInstOperands, /*InsnID*/44,
116309 GIR_BuildMI, /*InsnID*/43, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
116310 GIR_AddTempRegister, /*InsnID*/43, /*TempRegID*/42, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116311 GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/43,
116312 GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/44,
116313 GIR_ConstrainSelectedInstOperands, /*InsnID*/43,
116314 GIR_BuildMI, /*InsnID*/42, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116315 GIR_AddTempRegister, /*InsnID*/42, /*TempRegID*/41, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116316 GIR_Copy, /*NewInsnID*/42, /*OldInsnID*/0, /*OpIdx*/2, // Rm
116317 GIR_ConstrainSelectedInstOperands, /*InsnID*/42,
116318 GIR_BuildMI, /*InsnID*/41, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116319 GIR_AddTempRegister, /*InsnID*/41, /*TempRegID*/40, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116320 GIR_Copy, /*NewInsnID*/41, /*OldInsnID*/0, /*OpIdx*/1, // Rn
116321 GIR_ConstrainSelectedInstOperands, /*InsnID*/41,
116322 GIR_BuildMI, /*InsnID*/40, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
116323 GIR_AddTempRegister, /*InsnID*/40, /*TempRegID*/39, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116324 GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/40,
116325 GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/41,
116326 GIR_ConstrainSelectedInstOperands, /*InsnID*/40,
116327 GIR_BuildMI, /*InsnID*/39, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
116328 GIR_AddTempRegister, /*InsnID*/39, /*TempRegID*/38, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116329 GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/39,
116330 GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/42,
116331 GIR_ConstrainSelectedInstOperands, /*InsnID*/39,
116332 GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
116333 GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116334 GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/38,
116335 GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/45,
116336 GIR_ConstrainSelectedInstOperands, /*InsnID*/38,
116337 GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116338 GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116339 GIR_Copy, /*NewInsnID*/37, /*OldInsnID*/0, /*OpIdx*/2, // Rm
116340 GIR_ConstrainSelectedInstOperands, /*InsnID*/37,
116341 GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116342 GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116343 GIR_Copy, /*NewInsnID*/36, /*OldInsnID*/0, /*OpIdx*/1, // Rn
116344 GIR_ConstrainSelectedInstOperands, /*InsnID*/36,
116345 GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
116346 GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116347 GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/35,
116348 GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/36,
116349 GIR_ConstrainSelectedInstOperands, /*InsnID*/35,
116350 GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116351 GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116352 GIR_Copy, /*NewInsnID*/34, /*OldInsnID*/0, /*OpIdx*/2, // Rm
116353 GIR_ConstrainSelectedInstOperands, /*InsnID*/34,
116354 GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116355 GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116356 GIR_Copy, /*NewInsnID*/33, /*OldInsnID*/0, /*OpIdx*/1, // Rn
116357 GIR_ConstrainSelectedInstOperands, /*InsnID*/33,
116358 GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
116359 GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116360 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/32,
116361 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/33,
116362 GIR_ConstrainSelectedInstOperands, /*InsnID*/32,
116363 GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
116364 GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116365 GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/31,
116366 GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/34,
116367 GIR_ConstrainSelectedInstOperands, /*InsnID*/31,
116368 GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
116369 GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116370 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/30,
116371 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/37,
116372 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/46,
116373 GIR_ConstrainSelectedInstOperands, /*InsnID*/30,
116374 GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
116375 GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116376 GIR_CopySubReg, /*NewInsnID*/29, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
116377 GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
116378 GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116379 GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
116380 GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116381 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/28,
116382 GIR_ConstrainSelectedInstOperands, /*InsnID*/28,
116383 GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
116384 GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116385 GIR_CopySubReg, /*NewInsnID*/27, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
116386 GIR_ConstrainOperandRC, /*InsnID*/27, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
116387 GIR_ConstrainOperandRC, /*InsnID*/27, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116388 GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
116389 GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116390 GIR_AddSimpleTempRegister, /*InsnID*/26, /*TempRegID*/26,
116391 GIR_ConstrainSelectedInstOperands, /*InsnID*/26,
116392 GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
116393 GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116394 GIR_AddSimpleTempRegister, /*InsnID*/25, /*TempRegID*/25,
116395 GIR_AddSimpleTempRegister, /*InsnID*/25, /*TempRegID*/27,
116396 GIR_ConstrainSelectedInstOperands, /*InsnID*/25,
116397 GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
116398 GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116399 GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/24,
116400 GIR_AddImm8, /*InsnID*/24, /*Imm*/64,
116401 GIR_AddImm8, /*InsnID*/24, /*Imm*/16,
116402 GIR_ConstrainSelectedInstOperands, /*InsnID*/24,
116403 GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
116404 GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116405 GIR_AddImm8, /*InsnID*/23, /*Imm*/127,
116406 GIR_AddImm, /*InsnID*/23, /*Imm*/GIMT_Encode8(264),
116407 GIR_ConstrainSelectedInstOperands, /*InsnID*/23,
116408 GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
116409 GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116410 GIR_AddImm8, /*InsnID*/22, /*Imm*/1,
116411 GIR_AddImm8, /*InsnID*/22, /*Imm*/0,
116412 GIR_ConstrainSelectedInstOperands, /*InsnID*/22,
116413 GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
116414 GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116415 GIR_Copy, /*NewInsnID*/21, /*OldInsnID*/0, /*OpIdx*/1, // Rn
116416 GIR_AddImm8, /*InsnID*/21, /*Imm*/16,
116417 GIR_ConstrainSelectedInstOperands, /*InsnID*/21,
116418 GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
116419 GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116420 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/20,
116421 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/21,
116422 GIR_ConstrainSelectedInstOperands, /*InsnID*/20,
116423 GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
116424 GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116425 GIR_CopySubReg, /*NewInsnID*/19, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
116426 GIR_ConstrainOperandRC, /*InsnID*/19, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
116427 GIR_ConstrainOperandRC, /*InsnID*/19, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116428 GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
116429 GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116430 GIR_AddSimpleTempRegister, /*InsnID*/18, /*TempRegID*/18,
116431 GIR_ConstrainSelectedInstOperands, /*InsnID*/18,
116432 GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
116433 GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116434 GIR_CopySubReg, /*NewInsnID*/17, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
116435 GIR_ConstrainOperandRC, /*InsnID*/17, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
116436 GIR_ConstrainOperandRC, /*InsnID*/17, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116437 GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
116438 GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116439 GIR_AddSimpleTempRegister, /*InsnID*/16, /*TempRegID*/16,
116440 GIR_ConstrainSelectedInstOperands, /*InsnID*/16,
116441 GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
116442 GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116443 GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/15,
116444 GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/17,
116445 GIR_ConstrainSelectedInstOperands, /*InsnID*/15,
116446 GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
116447 GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116448 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14,
116449 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/19,
116450 GIR_ConstrainSelectedInstOperands, /*InsnID*/14,
116451 GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
116452 GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116453 GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/13,
116454 GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/22,
116455 GIR_ConstrainSelectedInstOperands, /*InsnID*/13,
116456 GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
116457 GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116458 GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
116459 GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
116460 GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116461 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
116462 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116463 GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11,
116464 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
116465 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
116466 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116467 GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
116468 GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
116469 GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116470 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
116471 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116472 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
116473 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
116474 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
116475 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116476 GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
116477 GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/10,
116478 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
116479 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
116480 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116481 GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
116482 GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
116483 GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116484 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
116485 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116486 GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
116487 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
116488 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
116489 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116490 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
116491 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
116492 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116493 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
116494 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116495 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
116496 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
116497 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
116498 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116499 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
116500 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/5,
116501 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
116502 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
116503 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116504 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
116505 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/7,
116506 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
116507 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
116508 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116509 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
116510 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/12,
116511 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/23,
116512 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
116513 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
116514 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
116515 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
116516 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/29,
116517 GIR_RootConstrainSelectedInstOperands,
116518 // GIR_Coverage, 6719,
116519 GIR_EraseRootFromParent_Done,
116520 // Label 6584: @316713
116521 GIM_Reject,
116522 // Label 6580: @316714
116523 GIM_Reject,
116524 // Label 6563: @316715
116525 GIM_Reject,
116526 // Label 91: @316716
116527 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6593*/ GIMT_Encode4(318608),
116528 /*GILLT_s16*//*Label 6585*/ GIMT_Encode4(316767),
116529 /*GILLT_s32*//*Label 6586*/ GIMT_Encode4(316805),
116530 /*GILLT_s64*//*Label 6587*/ GIMT_Encode4(316843), GIMT_Encode4(0),
116531 /*GILLT_v2s32*//*Label 6588*/ GIMT_Encode4(316881),
116532 /*GILLT_v2s64*//*Label 6589*/ GIMT_Encode4(316919),
116533 /*GILLT_v4s16*//*Label 6590*/ GIMT_Encode4(316957),
116534 /*GILLT_v4s32*//*Label 6591*/ GIMT_Encode4(316995), GIMT_Encode4(0),
116535 /*GILLT_v8s16*//*Label 6592*/ GIMT_Encode4(317033),
116536 // Label 6585: @316767
116537 GIM_Try, /*On fail goto*//*Label 6594*/ GIMT_Encode4(316804), // Rule ID 625 //
116538 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
116539 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
116540 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
116541 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
116542 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
116543 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
116544 // (strict_fsub:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FSUBHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
116545 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBHrr),
116546 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
116547 GIR_RootConstrainSelectedInstOperands,
116548 // GIR_Coverage, 625,
116549 GIR_Done,
116550 // Label 6594: @316804
116551 GIM_Reject,
116552 // Label 6586: @316805
116553 GIM_Try, /*On fail goto*//*Label 6595*/ GIMT_Encode4(316842), // Rule ID 627 //
116554 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
116555 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
116556 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
116557 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
116558 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
116559 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
116560 // (strict_fsub:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FSUBSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
116561 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBSrr),
116562 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
116563 GIR_RootConstrainSelectedInstOperands,
116564 // GIR_Coverage, 627,
116565 GIR_Done,
116566 // Label 6595: @316842
116567 GIM_Reject,
116568 // Label 6587: @316843
116569 GIM_Try, /*On fail goto*//*Label 6596*/ GIMT_Encode4(316880), // Rule ID 629 //
116570 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
116571 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
116572 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
116573 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
116574 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
116575 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
116576 // (strict_fsub:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FSUBDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
116577 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBDrr),
116578 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
116579 GIR_RootConstrainSelectedInstOperands,
116580 // GIR_Coverage, 629,
116581 GIR_Done,
116582 // Label 6596: @316880
116583 GIM_Reject,
116584 // Label 6588: @316881
116585 GIM_Try, /*On fail goto*//*Label 6597*/ GIMT_Encode4(316918), // Rule ID 1329 //
116586 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
116587 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
116588 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
116589 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
116590 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
116591 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
116592 // (strict_fsub:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FSUBv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
116593 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv2f32),
116594 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
116595 GIR_RootConstrainSelectedInstOperands,
116596 // GIR_Coverage, 1329,
116597 GIR_Done,
116598 // Label 6597: @316918
116599 GIM_Reject,
116600 // Label 6589: @316919
116601 GIM_Try, /*On fail goto*//*Label 6598*/ GIMT_Encode4(316956), // Rule ID 1333 //
116602 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
116603 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
116604 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
116605 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
116606 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
116607 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
116608 // (strict_fsub:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FSUBv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
116609 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv2f64),
116610 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
116611 GIR_RootConstrainSelectedInstOperands,
116612 // GIR_Coverage, 1333,
116613 GIR_Done,
116614 // Label 6598: @316956
116615 GIM_Reject,
116616 // Label 6590: @316957
116617 GIM_Try, /*On fail goto*//*Label 6599*/ GIMT_Encode4(316994), // Rule ID 1325 //
116618 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
116619 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
116620 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
116621 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
116622 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
116623 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
116624 // (strict_fsub:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FSUBv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
116625 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f16),
116626 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
116627 GIR_RootConstrainSelectedInstOperands,
116628 // GIR_Coverage, 1325,
116629 GIR_Done,
116630 // Label 6599: @316994
116631 GIM_Reject,
116632 // Label 6591: @316995
116633 GIM_Try, /*On fail goto*//*Label 6600*/ GIMT_Encode4(317032), // Rule ID 1331 //
116634 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
116635 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
116636 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
116637 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
116638 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
116639 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
116640 // (strict_fsub:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FSUBv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
116641 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
116642 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
116643 GIR_RootConstrainSelectedInstOperands,
116644 // GIR_Coverage, 1331,
116645 GIR_Done,
116646 // Label 6600: @317032
116647 GIM_Reject,
116648 // Label 6592: @317033
116649 GIM_Try, /*On fail goto*//*Label 6601*/ GIMT_Encode4(318607),
116650 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
116651 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
116652 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
116653 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
116654 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
116655 GIM_Try, /*On fail goto*//*Label 6602*/ GIMT_Encode4(317075), // Rule ID 1327 //
116656 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
116657 // (strict_fsub:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FSUBv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
116658 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv8f16),
116659 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
116660 GIR_RootConstrainSelectedInstOperands,
116661 // GIR_Coverage, 1327,
116662 GIR_Done,
116663 // Label 6602: @317075
116664 GIM_Try, /*On fail goto*//*Label 6603*/ GIMT_Encode4(317329), // Rule ID 6733 //
116665 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
116666 // (strict_fsub:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FSUBv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FSUBv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
116667 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
116668 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
116669 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
116670 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
116671 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
116672 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
116673 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
116674 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
116675 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
116676 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
116677 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
116678 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
116679 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116680 GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
116681 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
116682 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
116683 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116684 GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
116685 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
116686 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
116687 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116688 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
116689 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
116690 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
116691 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
116692 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116693 GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
116694 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
116695 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116696 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
116697 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116698 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
116699 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
116700 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
116701 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116702 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
116703 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
116704 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116705 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
116706 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116707 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
116708 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
116709 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
116710 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116711 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
116712 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
116713 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
116714 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
116715 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116716 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
116717 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
116718 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
116719 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116720 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
116721 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
116722 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116723 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
116724 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
116725 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
116726 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
116727 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116728 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
116729 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
116730 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
116731 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
116732 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
116733 GIR_RootConstrainSelectedInstOperands,
116734 // GIR_Coverage, 6733,
116735 GIR_EraseRootFromParent_Done,
116736 // Label 6603: @317329
116737 GIM_Try, /*On fail goto*//*Label 6604*/ GIMT_Encode4(317533), // Rule ID 6735 //
116738 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16),
116739 // (strict_fsub:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFCVTN2:{ *:[v8bf16] } (BFCVTN:{ *:[v8bf16] } (FSUBv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] })))), (FSUBv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)))
116740 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
116741 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
116742 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
116743 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
116744 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
116745 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
116746 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
116747 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
116748 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
116749 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116750 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116751 GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/0, /*OpIdx*/2, // Rm
116752 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
116753 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116754 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116755 GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
116756 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
116757 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
116758 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116759 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
116760 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/8,
116761 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
116762 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
116763 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116764 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
116765 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
116766 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116767 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
116768 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116769 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
116770 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
116771 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
116772 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116773 GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
116774 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
116775 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116776 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
116777 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116778 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
116779 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
116780 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
116781 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116782 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
116783 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/4,
116784 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
116785 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN),
116786 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116787 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
116788 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
116789 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN2),
116790 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
116791 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
116792 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
116793 GIR_RootConstrainSelectedInstOperands,
116794 // GIR_Coverage, 6735,
116795 GIR_EraseRootFromParent_Done,
116796 // Label 6604: @317533
116797 GIM_Try, /*On fail goto*//*Label 6605*/ GIMT_Encode4(318606), // Rule ID 6737 //
116798 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoBF16),
116799 // (strict_fsub:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (UZP2v8i16:{ *:[v8bf16] } (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FSUBv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), (FSUBv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] })))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FSUBv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FSUBv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), 64:{ *:[i32] }, 16:{ *:[i32] })), (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FSUBv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), (FSUBv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FSUBv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FSUBv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), 64:{ *:[i32] }, 16:{ *:[i32] })))
116800 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
116801 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
116802 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
116803 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
116804 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
116805 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
116806 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
116807 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
116808 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
116809 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s16,
116810 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
116811 GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_v4s16,
116812 GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_s128,
116813 GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s128,
116814 GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_v4s32,
116815 GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_v4s32,
116816 GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_v4s16,
116817 GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_v4s32,
116818 GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_v4s16,
116819 GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_s128,
116820 GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_s128,
116821 GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s128,
116822 GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s128,
116823 GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_s128,
116824 GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_v4s32,
116825 GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_v4s32,
116826 GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_v4s16,
116827 GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_v4s32,
116828 GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_v4s16,
116829 GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_s128,
116830 GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_s128,
116831 GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_v4s32,
116832 GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_v4s32,
116833 GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_v4s32,
116834 GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_v4s32,
116835 GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_v4s32,
116836 GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_v4s32,
116837 GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_s128,
116838 GIR_MakeTempReg, /*TempRegID*/38, /*TypeID*/GILLT_s128,
116839 GIR_MakeTempReg, /*TempRegID*/39, /*TypeID*/GILLT_v4s32,
116840 GIR_MakeTempReg, /*TempRegID*/40, /*TypeID*/GILLT_v4s32,
116841 GIR_MakeTempReg, /*TempRegID*/41, /*TypeID*/GILLT_v4s32,
116842 GIR_MakeTempReg, /*TempRegID*/42, /*TypeID*/GILLT_s128,
116843 GIR_MakeTempReg, /*TempRegID*/43, /*TypeID*/GILLT_s128,
116844 GIR_MakeTempReg, /*TempRegID*/44, /*TypeID*/GILLT_s128,
116845 GIR_MakeTempReg, /*TempRegID*/45, /*TypeID*/GILLT_s128,
116846 GIR_MakeTempReg, /*TempRegID*/46, /*TypeID*/GILLT_s128,
116847 GIR_MakeTempReg, /*TempRegID*/47, /*TypeID*/GILLT_v4s32,
116848 GIR_MakeTempReg, /*TempRegID*/48, /*TypeID*/GILLT_v4s32,
116849 GIR_MakeTempReg, /*TempRegID*/49, /*TypeID*/GILLT_v4s32,
116850 GIR_BuildMI, /*InsnID*/50, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116851 GIR_AddTempRegister, /*InsnID*/50, /*TempRegID*/49, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116852 GIR_Copy, /*NewInsnID*/50, /*OldInsnID*/0, /*OpIdx*/2, // Rm
116853 GIR_ConstrainSelectedInstOperands, /*InsnID*/50,
116854 GIR_BuildMI, /*InsnID*/49, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116855 GIR_AddTempRegister, /*InsnID*/49, /*TempRegID*/48, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116856 GIR_Copy, /*NewInsnID*/49, /*OldInsnID*/0, /*OpIdx*/1, // Rn
116857 GIR_ConstrainSelectedInstOperands, /*InsnID*/49,
116858 GIR_BuildMI, /*InsnID*/48, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
116859 GIR_AddTempRegister, /*InsnID*/48, /*TempRegID*/47, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116860 GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/48,
116861 GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/49,
116862 GIR_ConstrainSelectedInstOperands, /*InsnID*/48,
116863 GIR_BuildMI, /*InsnID*/47, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
116864 GIR_AddTempRegister, /*InsnID*/47, /*TempRegID*/46, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116865 GIR_AddSimpleTempRegister, /*InsnID*/47, /*TempRegID*/47,
116866 GIR_AddImm8, /*InsnID*/47, /*Imm*/64,
116867 GIR_AddImm8, /*InsnID*/47, /*Imm*/16,
116868 GIR_ConstrainSelectedInstOperands, /*InsnID*/47,
116869 GIR_BuildMI, /*InsnID*/46, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
116870 GIR_AddTempRegister, /*InsnID*/46, /*TempRegID*/45, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116871 GIR_AddImm8, /*InsnID*/46, /*Imm*/127,
116872 GIR_AddImm, /*InsnID*/46, /*Imm*/GIMT_Encode8(264),
116873 GIR_ConstrainSelectedInstOperands, /*InsnID*/46,
116874 GIR_BuildMI, /*InsnID*/45, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
116875 GIR_AddTempRegister, /*InsnID*/45, /*TempRegID*/44, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116876 GIR_AddImm8, /*InsnID*/45, /*Imm*/1,
116877 GIR_AddImm8, /*InsnID*/45, /*Imm*/0,
116878 GIR_ConstrainSelectedInstOperands, /*InsnID*/45,
116879 GIR_BuildMI, /*InsnID*/44, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
116880 GIR_AddTempRegister, /*InsnID*/44, /*TempRegID*/43, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116881 GIR_Copy, /*NewInsnID*/44, /*OldInsnID*/0, /*OpIdx*/1, // Rn
116882 GIR_AddImm8, /*InsnID*/44, /*Imm*/16,
116883 GIR_ConstrainSelectedInstOperands, /*InsnID*/44,
116884 GIR_BuildMI, /*InsnID*/43, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
116885 GIR_AddTempRegister, /*InsnID*/43, /*TempRegID*/42, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116886 GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/43,
116887 GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/44,
116888 GIR_ConstrainSelectedInstOperands, /*InsnID*/43,
116889 GIR_BuildMI, /*InsnID*/42, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116890 GIR_AddTempRegister, /*InsnID*/42, /*TempRegID*/41, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116891 GIR_Copy, /*NewInsnID*/42, /*OldInsnID*/0, /*OpIdx*/2, // Rm
116892 GIR_ConstrainSelectedInstOperands, /*InsnID*/42,
116893 GIR_BuildMI, /*InsnID*/41, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116894 GIR_AddTempRegister, /*InsnID*/41, /*TempRegID*/40, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116895 GIR_Copy, /*NewInsnID*/41, /*OldInsnID*/0, /*OpIdx*/1, // Rn
116896 GIR_ConstrainSelectedInstOperands, /*InsnID*/41,
116897 GIR_BuildMI, /*InsnID*/40, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
116898 GIR_AddTempRegister, /*InsnID*/40, /*TempRegID*/39, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116899 GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/40,
116900 GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/41,
116901 GIR_ConstrainSelectedInstOperands, /*InsnID*/40,
116902 GIR_BuildMI, /*InsnID*/39, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
116903 GIR_AddTempRegister, /*InsnID*/39, /*TempRegID*/38, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116904 GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/39,
116905 GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/42,
116906 GIR_ConstrainSelectedInstOperands, /*InsnID*/39,
116907 GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
116908 GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116909 GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/38,
116910 GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/45,
116911 GIR_ConstrainSelectedInstOperands, /*InsnID*/38,
116912 GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116913 GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116914 GIR_Copy, /*NewInsnID*/37, /*OldInsnID*/0, /*OpIdx*/2, // Rm
116915 GIR_ConstrainSelectedInstOperands, /*InsnID*/37,
116916 GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116917 GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116918 GIR_Copy, /*NewInsnID*/36, /*OldInsnID*/0, /*OpIdx*/1, // Rn
116919 GIR_ConstrainSelectedInstOperands, /*InsnID*/36,
116920 GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
116921 GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116922 GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/35,
116923 GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/36,
116924 GIR_ConstrainSelectedInstOperands, /*InsnID*/35,
116925 GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116926 GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116927 GIR_Copy, /*NewInsnID*/34, /*OldInsnID*/0, /*OpIdx*/2, // Rm
116928 GIR_ConstrainSelectedInstOperands, /*InsnID*/34,
116929 GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
116930 GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116931 GIR_Copy, /*NewInsnID*/33, /*OldInsnID*/0, /*OpIdx*/1, // Rn
116932 GIR_ConstrainSelectedInstOperands, /*InsnID*/33,
116933 GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
116934 GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116935 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/32,
116936 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/33,
116937 GIR_ConstrainSelectedInstOperands, /*InsnID*/32,
116938 GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
116939 GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116940 GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/31,
116941 GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/34,
116942 GIR_ConstrainSelectedInstOperands, /*InsnID*/31,
116943 GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
116944 GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116945 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/30,
116946 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/37,
116947 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/46,
116948 GIR_ConstrainSelectedInstOperands, /*InsnID*/30,
116949 GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
116950 GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116951 GIR_CopySubReg, /*NewInsnID*/29, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
116952 GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
116953 GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116954 GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
116955 GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116956 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/28,
116957 GIR_ConstrainSelectedInstOperands, /*InsnID*/28,
116958 GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
116959 GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116960 GIR_CopySubReg, /*NewInsnID*/27, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
116961 GIR_ConstrainOperandRC, /*InsnID*/27, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
116962 GIR_ConstrainOperandRC, /*InsnID*/27, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
116963 GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
116964 GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116965 GIR_AddSimpleTempRegister, /*InsnID*/26, /*TempRegID*/26,
116966 GIR_ConstrainSelectedInstOperands, /*InsnID*/26,
116967 GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
116968 GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116969 GIR_AddSimpleTempRegister, /*InsnID*/25, /*TempRegID*/25,
116970 GIR_AddSimpleTempRegister, /*InsnID*/25, /*TempRegID*/27,
116971 GIR_ConstrainSelectedInstOperands, /*InsnID*/25,
116972 GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
116973 GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116974 GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/24,
116975 GIR_AddImm8, /*InsnID*/24, /*Imm*/64,
116976 GIR_AddImm8, /*InsnID*/24, /*Imm*/16,
116977 GIR_ConstrainSelectedInstOperands, /*InsnID*/24,
116978 GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
116979 GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116980 GIR_AddImm8, /*InsnID*/23, /*Imm*/127,
116981 GIR_AddImm, /*InsnID*/23, /*Imm*/GIMT_Encode8(264),
116982 GIR_ConstrainSelectedInstOperands, /*InsnID*/23,
116983 GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
116984 GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116985 GIR_AddImm8, /*InsnID*/22, /*Imm*/1,
116986 GIR_AddImm8, /*InsnID*/22, /*Imm*/0,
116987 GIR_ConstrainSelectedInstOperands, /*InsnID*/22,
116988 GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
116989 GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116990 GIR_Copy, /*NewInsnID*/21, /*OldInsnID*/0, /*OpIdx*/1, // Rn
116991 GIR_AddImm8, /*InsnID*/21, /*Imm*/16,
116992 GIR_ConstrainSelectedInstOperands, /*InsnID*/21,
116993 GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
116994 GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
116995 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/20,
116996 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/21,
116997 GIR_ConstrainSelectedInstOperands, /*InsnID*/20,
116998 GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
116999 GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117000 GIR_CopySubReg, /*NewInsnID*/19, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
117001 GIR_ConstrainOperandRC, /*InsnID*/19, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
117002 GIR_ConstrainOperandRC, /*InsnID*/19, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117003 GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
117004 GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117005 GIR_AddSimpleTempRegister, /*InsnID*/18, /*TempRegID*/18,
117006 GIR_ConstrainSelectedInstOperands, /*InsnID*/18,
117007 GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
117008 GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117009 GIR_CopySubReg, /*NewInsnID*/17, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
117010 GIR_ConstrainOperandRC, /*InsnID*/17, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
117011 GIR_ConstrainOperandRC, /*InsnID*/17, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117012 GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
117013 GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117014 GIR_AddSimpleTempRegister, /*InsnID*/16, /*TempRegID*/16,
117015 GIR_ConstrainSelectedInstOperands, /*InsnID*/16,
117016 GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
117017 GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117018 GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/15,
117019 GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/17,
117020 GIR_ConstrainSelectedInstOperands, /*InsnID*/15,
117021 GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
117022 GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117023 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14,
117024 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/19,
117025 GIR_ConstrainSelectedInstOperands, /*InsnID*/14,
117026 GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
117027 GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117028 GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/13,
117029 GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/22,
117030 GIR_ConstrainSelectedInstOperands, /*InsnID*/13,
117031 GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
117032 GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117033 GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
117034 GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
117035 GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117036 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
117037 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117038 GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11,
117039 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
117040 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
117041 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117042 GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
117043 GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
117044 GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117045 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
117046 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117047 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
117048 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
117049 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
117050 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117051 GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
117052 GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/10,
117053 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
117054 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
117055 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117056 GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
117057 GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
117058 GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117059 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
117060 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117061 GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
117062 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
117063 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
117064 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117065 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
117066 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
117067 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117068 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
117069 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117070 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
117071 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
117072 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
117073 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117074 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
117075 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/5,
117076 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
117077 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
117078 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117079 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
117080 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/7,
117081 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
117082 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
117083 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117084 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
117085 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/12,
117086 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/23,
117087 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
117088 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
117089 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117090 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
117091 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/29,
117092 GIR_RootConstrainSelectedInstOperands,
117093 // GIR_Coverage, 6737,
117094 GIR_EraseRootFromParent_Done,
117095 // Label 6605: @318606
117096 GIM_Reject,
117097 // Label 6601: @318607
117098 GIM_Reject,
117099 // Label 6593: @318608
117100 GIM_Reject,
117101 // Label 92: @318609
117102 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6614*/ GIMT_Encode4(323279),
117103 /*GILLT_s16*//*Label 6606*/ GIMT_Encode4(318660),
117104 /*GILLT_s32*//*Label 6607*/ GIMT_Encode4(319214),
117105 /*GILLT_s64*//*Label 6608*/ GIMT_Encode4(319762), GIMT_Encode4(0),
117106 /*GILLT_v2s32*//*Label 6609*/ GIMT_Encode4(320310),
117107 /*GILLT_v2s64*//*Label 6610*/ GIMT_Encode4(320668),
117108 /*GILLT_v4s16*//*Label 6611*/ GIMT_Encode4(321026),
117109 /*GILLT_v4s32*//*Label 6612*/ GIMT_Encode4(321196), GIMT_Encode4(0),
117110 /*GILLT_v8s16*//*Label 6613*/ GIMT_Encode4(321554),
117111 // Label 6606: @318660
117112 GIM_Try, /*On fail goto*//*Label 6615*/ GIMT_Encode4(319213),
117113 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
117114 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
117115 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
117116 GIM_Try, /*On fail goto*//*Label 6616*/ GIMT_Encode4(318788), // Rule ID 5830 //
117117 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
117118 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
117119 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117120 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
117121 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117122 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117123 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
117124 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
117125 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117126 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
117127 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
117128 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117129 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
117130 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
117131 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
117132 // MIs[3] Operand 1
117133 // No operand predicates
117134 GIM_CheckIsSafeToFold, /*NumInsns*/3,
117135 // (strict_fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMULv1i16_indexed:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
117136 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
117137 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
117138 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117139 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
117140 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
117141 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117142 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
117143 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117144 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
117145 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
117146 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
117147 GIR_RootConstrainSelectedInstOperands,
117148 // GIR_Coverage, 5830,
117149 GIR_EraseRootFromParent_Done,
117150 // Label 6616: @318788
117151 GIM_Try, /*On fail goto*//*Label 6617*/ GIMT_Encode4(318901), // Rule ID 13164 //
117152 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
117153 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
117154 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117155 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
117156 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117157 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117158 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
117159 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
117160 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
117161 // MIs[2] Operand 1
117162 // No operand predicates
117163 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
117164 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117165 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
117166 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
117167 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117168 GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
117169 GIM_CheckIsSafeToFold, /*NumInsns*/3,
117170 // (strict_fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })) => (FMULv1i16_indexed:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
117171 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
117172 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
117173 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117174 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
117175 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
117176 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117177 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
117178 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117179 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
117180 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
117181 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
117182 GIR_RootConstrainSelectedInstOperands,
117183 // GIR_Coverage, 13164,
117184 GIR_EraseRootFromParent_Done,
117185 // Label 6617: @318901
117186 GIM_Try, /*On fail goto*//*Label 6618*/ GIMT_Encode4(318980), // Rule ID 13079 //
117187 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
117188 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
117189 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117190 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
117191 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117192 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117193 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
117194 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
117195 GIM_CheckIsSafeToFold, /*NumInsns*/1,
117196 // (strict_fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rn) => (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }))
117197 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
117198 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
117199 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117200 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rm
117201 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
117202 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117203 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULHrr),
117204 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117205 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
117206 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
117207 GIR_RootConstrainSelectedInstOperands,
117208 // GIR_Coverage, 13079,
117209 GIR_EraseRootFromParent_Done,
117210 // Label 6618: @318980
117211 GIM_Try, /*On fail goto*//*Label 6619*/ GIMT_Encode4(319059), // Rule ID 4487 //
117212 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
117213 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
117214 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
117215 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117216 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
117217 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117218 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117219 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
117220 GIM_CheckIsSafeToFold, /*NumInsns*/1,
117221 // (strict_fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })) => (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }))
117222 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
117223 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
117224 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117225 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rm
117226 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
117227 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117228 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULHrr),
117229 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117230 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
117231 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
117232 GIR_RootConstrainSelectedInstOperands,
117233 // GIR_Coverage, 4487,
117234 GIR_EraseRootFromParent_Done,
117235 // Label 6619: @319059
117236 GIM_Try, /*On fail goto*//*Label 6620*/ GIMT_Encode4(319122), // Rule ID 12706 //
117237 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
117238 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
117239 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117240 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
117241 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117242 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
117243 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
117244 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
117245 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
117246 // MIs[2] Operand 1
117247 // No operand predicates
117248 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
117249 GIM_CheckIsSafeToFold, /*NumInsns*/2,
117250 // (strict_fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16Op:{ *:[f16] }:$Rn) => (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
117251 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
117252 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117253 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
117254 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
117255 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
117256 GIR_RootConstrainSelectedInstOperands,
117257 // GIR_Coverage, 12706,
117258 GIR_EraseRootFromParent_Done,
117259 // Label 6620: @319122
117260 GIM_Try, /*On fail goto*//*Label 6621*/ GIMT_Encode4(319185), // Rule ID 1998 //
117261 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
117262 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
117263 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
117264 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117265 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
117266 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117267 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
117268 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
117269 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
117270 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
117271 // MIs[2] Operand 1
117272 // No operand predicates
117273 GIM_CheckIsSafeToFold, /*NumInsns*/2,
117274 // (strict_fmul:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
117275 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
117276 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117277 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
117278 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
117279 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
117280 GIR_RootConstrainSelectedInstOperands,
117281 // GIR_Coverage, 1998,
117282 GIR_EraseRootFromParent_Done,
117283 // Label 6621: @319185
117284 GIM_Try, /*On fail goto*//*Label 6622*/ GIMT_Encode4(319212), // Rule ID 613 //
117285 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
117286 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
117287 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
117288 // (strict_fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
117289 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULHrr),
117290 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
117291 GIR_RootConstrainSelectedInstOperands,
117292 // GIR_Coverage, 613,
117293 GIR_Done,
117294 // Label 6622: @319212
117295 GIM_Reject,
117296 // Label 6615: @319213
117297 GIM_Reject,
117298 // Label 6607: @319214
117299 GIM_Try, /*On fail goto*//*Label 6623*/ GIMT_Encode4(319761),
117300 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
117301 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
117302 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
117303 GIM_Try, /*On fail goto*//*Label 6624*/ GIMT_Encode4(319342), // Rule ID 5832 //
117304 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
117305 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
117306 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117307 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
117308 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117309 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117310 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
117311 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
117312 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117313 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
117314 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
117315 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117316 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
117317 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
117318 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
117319 // MIs[3] Operand 1
117320 // No operand predicates
117321 GIM_CheckIsSafeToFold, /*NumInsns*/3,
117322 // (strict_fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (FMULv1i32_indexed:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
117323 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
117324 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
117325 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117326 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rn
117327 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
117328 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117329 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
117330 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117331 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
117332 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
117333 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
117334 GIR_RootConstrainSelectedInstOperands,
117335 // GIR_Coverage, 5832,
117336 GIR_EraseRootFromParent_Done,
117337 // Label 6624: @319342
117338 GIM_Try, /*On fail goto*//*Label 6625*/ GIMT_Encode4(319455), // Rule ID 13166 //
117339 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
117340 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
117341 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117342 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
117343 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117344 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117345 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
117346 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
117347 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
117348 // MIs[2] Operand 1
117349 // No operand predicates
117350 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
117351 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117352 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
117353 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
117354 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117355 GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
117356 GIM_CheckIsSafeToFold, /*NumInsns*/3,
117357 // (strict_fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })) => (FMULv1i32_indexed:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
117358 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
117359 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
117360 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117361 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rn
117362 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
117363 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117364 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
117365 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117366 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
117367 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
117368 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
117369 GIR_RootConstrainSelectedInstOperands,
117370 // GIR_Coverage, 13166,
117371 GIR_EraseRootFromParent_Done,
117372 // Label 6625: @319455
117373 GIM_Try, /*On fail goto*//*Label 6626*/ GIMT_Encode4(319531), // Rule ID 13081 //
117374 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
117375 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117376 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
117377 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117378 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117379 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
117380 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
117381 GIM_CheckIsSafeToFold, /*NumInsns*/1,
117382 // (strict_fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rn) => (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }))
117383 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
117384 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
117385 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117386 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rm
117387 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
117388 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117389 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULSrr),
117390 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117391 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
117392 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
117393 GIR_RootConstrainSelectedInstOperands,
117394 // GIR_Coverage, 13081,
117395 GIR_EraseRootFromParent_Done,
117396 // Label 6626: @319531
117397 GIM_Try, /*On fail goto*//*Label 6627*/ GIMT_Encode4(319607), // Rule ID 4489 //
117398 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
117399 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
117400 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117401 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
117402 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117403 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117404 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
117405 GIM_CheckIsSafeToFold, /*NumInsns*/1,
117406 // (strict_fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })) => (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }))
117407 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
117408 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
117409 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117410 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rm
117411 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
117412 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117413 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULSrr),
117414 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117415 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
117416 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
117417 GIR_RootConstrainSelectedInstOperands,
117418 // GIR_Coverage, 4489,
117419 GIR_EraseRootFromParent_Done,
117420 // Label 6627: @319607
117421 GIM_Try, /*On fail goto*//*Label 6628*/ GIMT_Encode4(319670), // Rule ID 12708 //
117422 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
117423 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
117424 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117425 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
117426 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117427 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117428 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
117429 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
117430 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
117431 // MIs[2] Operand 1
117432 // No operand predicates
117433 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
117434 GIM_CheckIsSafeToFold, /*NumInsns*/2,
117435 // (strict_fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32Op:{ *:[f32] }:$Rn) => (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
117436 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
117437 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117438 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
117439 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
117440 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
117441 GIR_RootConstrainSelectedInstOperands,
117442 // GIR_Coverage, 12708,
117443 GIR_EraseRootFromParent_Done,
117444 // Label 6628: @319670
117445 GIM_Try, /*On fail goto*//*Label 6629*/ GIMT_Encode4(319733), // Rule ID 2000 //
117446 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
117447 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
117448 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
117449 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117450 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
117451 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117452 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117453 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
117454 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
117455 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
117456 // MIs[2] Operand 1
117457 // No operand predicates
117458 GIM_CheckIsSafeToFold, /*NumInsns*/2,
117459 // (strict_fmul:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
117460 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
117461 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117462 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
117463 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
117464 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
117465 GIR_RootConstrainSelectedInstOperands,
117466 // GIR_Coverage, 2000,
117467 GIR_EraseRootFromParent_Done,
117468 // Label 6629: @319733
117469 GIM_Try, /*On fail goto*//*Label 6630*/ GIMT_Encode4(319760), // Rule ID 615 //
117470 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
117471 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
117472 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
117473 // (strict_fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
117474 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULSrr),
117475 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
117476 GIR_RootConstrainSelectedInstOperands,
117477 // GIR_Coverage, 615,
117478 GIR_Done,
117479 // Label 6630: @319760
117480 GIM_Reject,
117481 // Label 6623: @319761
117482 GIM_Reject,
117483 // Label 6608: @319762
117484 GIM_Try, /*On fail goto*//*Label 6631*/ GIMT_Encode4(320309),
117485 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
117486 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
117487 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117488 GIM_Try, /*On fail goto*//*Label 6632*/ GIMT_Encode4(319890), // Rule ID 5834 //
117489 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
117490 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
117491 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117492 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
117493 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117494 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117495 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
117496 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
117497 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117498 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
117499 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
117500 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117501 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
117502 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
117503 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
117504 // MIs[3] Operand 1
117505 // No operand predicates
117506 GIM_CheckIsSafeToFold, /*NumInsns*/3,
117507 // (strict_fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)) => (FMULv1i64_indexed:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
117508 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
117509 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
117510 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117511 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
117512 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
117513 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117514 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
117515 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117516 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
117517 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
117518 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
117519 GIR_RootConstrainSelectedInstOperands,
117520 // GIR_Coverage, 5834,
117521 GIR_EraseRootFromParent_Done,
117522 // Label 6632: @319890
117523 GIM_Try, /*On fail goto*//*Label 6633*/ GIMT_Encode4(320003), // Rule ID 13168 //
117524 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
117525 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
117526 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117527 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
117528 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117529 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117530 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
117531 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
117532 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
117533 // MIs[2] Operand 1
117534 // No operand predicates
117535 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
117536 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117537 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
117538 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
117539 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117540 GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
117541 GIM_CheckIsSafeToFold, /*NumInsns*/3,
117542 // (strict_fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })) => (FMULv1i64_indexed:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
117543 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
117544 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
117545 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117546 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
117547 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
117548 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117549 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
117550 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117551 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
117552 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
117553 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
117554 GIR_RootConstrainSelectedInstOperands,
117555 // GIR_Coverage, 13168,
117556 GIR_EraseRootFromParent_Done,
117557 // Label 6633: @320003
117558 GIM_Try, /*On fail goto*//*Label 6634*/ GIMT_Encode4(320079), // Rule ID 13083 //
117559 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
117560 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117561 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
117562 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117563 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117564 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
117565 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117566 GIM_CheckIsSafeToFold, /*NumInsns*/1,
117567 // (strict_fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rn) => (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }))
117568 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
117569 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
117570 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117571 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rm
117572 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
117573 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117574 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULDrr),
117575 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117576 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
117577 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
117578 GIR_RootConstrainSelectedInstOperands,
117579 // GIR_Coverage, 13083,
117580 GIR_EraseRootFromParent_Done,
117581 // Label 6634: @320079
117582 GIM_Try, /*On fail goto*//*Label 6635*/ GIMT_Encode4(320155), // Rule ID 4491 //
117583 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117584 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
117585 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117586 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
117587 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117588 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117589 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
117590 GIM_CheckIsSafeToFold, /*NumInsns*/1,
117591 // (strict_fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })) => (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }))
117592 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
117593 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
117594 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117595 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rm
117596 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
117597 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117598 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULDrr),
117599 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117600 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
117601 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
117602 GIR_RootConstrainSelectedInstOperands,
117603 // GIR_Coverage, 4491,
117604 GIR_EraseRootFromParent_Done,
117605 // Label 6635: @320155
117606 GIM_Try, /*On fail goto*//*Label 6636*/ GIMT_Encode4(320218), // Rule ID 12710 //
117607 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
117608 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
117609 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117610 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
117611 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117612 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117613 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
117614 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
117615 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
117616 // MIs[2] Operand 1
117617 // No operand predicates
117618 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117619 GIM_CheckIsSafeToFold, /*NumInsns*/2,
117620 // (strict_fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64Op:{ *:[f64] }:$Rn) => (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
117621 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
117622 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117623 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
117624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
117625 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
117626 GIR_RootConstrainSelectedInstOperands,
117627 // GIR_Coverage, 12710,
117628 GIR_EraseRootFromParent_Done,
117629 // Label 6636: @320218
117630 GIM_Try, /*On fail goto*//*Label 6637*/ GIMT_Encode4(320281), // Rule ID 2002 //
117631 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
117632 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117633 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
117634 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
117635 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
117636 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117637 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117638 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
117639 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
117640 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
117641 // MIs[2] Operand 1
117642 // No operand predicates
117643 GIM_CheckIsSafeToFold, /*NumInsns*/2,
117644 // (strict_fmul:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)) => (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
117645 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
117646 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117647 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
117648 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
117649 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
117650 GIR_RootConstrainSelectedInstOperands,
117651 // GIR_Coverage, 2002,
117652 GIR_EraseRootFromParent_Done,
117653 // Label 6637: @320281
117654 GIM_Try, /*On fail goto*//*Label 6638*/ GIMT_Encode4(320308), // Rule ID 617 //
117655 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
117656 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117657 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117658 // (strict_fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
117659 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULDrr),
117660 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
117661 GIR_RootConstrainSelectedInstOperands,
117662 // GIR_Coverage, 617,
117663 GIR_Done,
117664 // Label 6638: @320308
117665 GIM_Reject,
117666 // Label 6631: @320309
117667 GIM_Reject,
117668 // Label 6609: @320310
117669 GIM_Try, /*On fail goto*//*Label 6639*/ GIMT_Encode4(320667),
117670 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
117671 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
117672 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117673 GIM_Try, /*On fail goto*//*Label 6640*/ GIMT_Encode4(320388), // Rule ID 12699 //
117674 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
117675 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
117676 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
117677 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
117678 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117679 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117680 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
117681 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
117682 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
117683 // MIs[2] Operand 1
117684 // No operand predicates
117685 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117686 GIM_CheckIsSafeToFold, /*NumInsns*/2,
117687 // (strict_fmul:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
117688 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
117689 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117690 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
117691 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
117692 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
117693 GIR_RootConstrainSelectedInstOperands,
117694 // GIR_Coverage, 12699,
117695 GIR_EraseRootFromParent_Done,
117696 // Label 6640: @320388
117697 GIM_Try, /*On fail goto*//*Label 6641*/ GIMT_Encode4(320451), // Rule ID 1991 //
117698 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
117699 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117700 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
117701 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
117702 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
117703 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117704 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117705 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
117706 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
117707 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
117708 // MIs[2] Operand 1
117709 // No operand predicates
117710 GIM_CheckIsSafeToFold, /*NumInsns*/2,
117711 // (strict_fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
117712 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
117713 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117714 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
117715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
117716 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
117717 GIR_RootConstrainSelectedInstOperands,
117718 // GIR_Coverage, 1991,
117719 GIR_EraseRootFromParent_Done,
117720 // Label 6641: @320451
117721 GIM_Try, /*On fail goto*//*Label 6642*/ GIMT_Encode4(320545), // Rule ID 13170 //
117722 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
117723 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
117724 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
117725 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
117726 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117727 GIM_CheckIsSafeToFold, /*NumInsns*/1,
117728 // (strict_fmul:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rn) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
117729 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
117730 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
117731 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
117732 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117733 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
117734 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
117735 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117736 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
117737 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
117738 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
117739 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
117740 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117741 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
117742 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
117743 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117744 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
117745 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
117746 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
117747 GIR_RootConstrainSelectedInstOperands,
117748 // GIR_Coverage, 13170,
117749 GIR_EraseRootFromParent_Done,
117750 // Label 6642: @320545
117751 GIM_Try, /*On fail goto*//*Label 6643*/ GIMT_Encode4(320639), // Rule ID 5836 //
117752 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117753 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
117754 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
117755 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
117756 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
117757 GIM_CheckIsSafeToFold, /*NumInsns*/1,
117758 // (strict_fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rm)) => (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
117759 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
117760 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
117761 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
117762 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117763 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
117764 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
117765 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117766 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
117767 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
117768 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
117769 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
117770 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117771 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
117772 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
117773 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117774 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
117775 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
117776 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
117777 GIR_RootConstrainSelectedInstOperands,
117778 // GIR_Coverage, 5836,
117779 GIR_EraseRootFromParent_Done,
117780 // Label 6643: @320639
117781 GIM_Try, /*On fail goto*//*Label 6644*/ GIMT_Encode4(320666), // Rule ID 1309 //
117782 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
117783 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117784 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117785 // (strict_fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FMULv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
117786 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv2f32),
117787 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
117788 GIR_RootConstrainSelectedInstOperands,
117789 // GIR_Coverage, 1309,
117790 GIR_Done,
117791 // Label 6644: @320666
117792 GIM_Reject,
117793 // Label 6639: @320667
117794 GIM_Reject,
117795 // Label 6610: @320668
117796 GIM_Try, /*On fail goto*//*Label 6645*/ GIMT_Encode4(321025),
117797 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
117798 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
117799 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117800 GIM_Try, /*On fail goto*//*Label 6646*/ GIMT_Encode4(320746), // Rule ID 12704 //
117801 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
117802 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
117803 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
117804 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
117805 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117806 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117807 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
117808 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
117809 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
117810 // MIs[2] Operand 1
117811 // No operand predicates
117812 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117813 GIM_CheckIsSafeToFold, /*NumInsns*/2,
117814 // (strict_fmul:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
117815 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
117816 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117817 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
117818 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
117819 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
117820 GIR_RootConstrainSelectedInstOperands,
117821 // GIR_Coverage, 12704,
117822 GIR_EraseRootFromParent_Done,
117823 // Label 6646: @320746
117824 GIM_Try, /*On fail goto*//*Label 6647*/ GIMT_Encode4(320809), // Rule ID 1996 //
117825 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
117826 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117827 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
117828 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
117829 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
117830 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117831 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117832 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
117833 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
117834 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
117835 // MIs[2] Operand 1
117836 // No operand predicates
117837 GIM_CheckIsSafeToFold, /*NumInsns*/2,
117838 // (strict_fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
117839 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
117840 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117841 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
117842 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
117843 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
117844 GIR_RootConstrainSelectedInstOperands,
117845 // GIR_Coverage, 1996,
117846 GIR_EraseRootFromParent_Done,
117847 // Label 6647: @320809
117848 GIM_Try, /*On fail goto*//*Label 6648*/ GIMT_Encode4(320903), // Rule ID 13174 //
117849 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
117850 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
117851 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
117852 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117853 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117854 GIM_CheckIsSafeToFold, /*NumInsns*/1,
117855 // (strict_fmul:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rn) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
117856 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
117857 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
117858 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
117859 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117860 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
117861 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
117862 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117863 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
117864 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
117865 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
117866 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
117867 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117868 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
117869 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
117870 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117871 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
117872 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
117873 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
117874 GIR_RootConstrainSelectedInstOperands,
117875 // GIR_Coverage, 13174,
117876 GIR_EraseRootFromParent_Done,
117877 // Label 6648: @320903
117878 GIM_Try, /*On fail goto*//*Label 6649*/ GIMT_Encode4(320997), // Rule ID 5840 //
117879 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117880 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
117881 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
117882 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
117883 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117884 GIM_CheckIsSafeToFold, /*NumInsns*/1,
117885 // (strict_fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rm)) => (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
117886 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
117887 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
117888 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
117889 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117890 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
117891 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
117892 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
117893 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
117894 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
117895 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
117896 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
117897 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
117898 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
117899 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
117900 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117901 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
117902 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
117903 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
117904 GIR_RootConstrainSelectedInstOperands,
117905 // GIR_Coverage, 5840,
117906 GIR_EraseRootFromParent_Done,
117907 // Label 6649: @320997
117908 GIM_Try, /*On fail goto*//*Label 6650*/ GIMT_Encode4(321024), // Rule ID 1313 //
117909 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
117910 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117911 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117912 // (strict_fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FMULv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
117913 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv2f64),
117914 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
117915 GIR_RootConstrainSelectedInstOperands,
117916 // GIR_Coverage, 1313,
117917 GIR_Done,
117918 // Label 6650: @321024
117919 GIM_Reject,
117920 // Label 6645: @321025
117921 GIM_Reject,
117922 // Label 6611: @321026
117923 GIM_Try, /*On fail goto*//*Label 6651*/ GIMT_Encode4(321195),
117924 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
117925 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
117926 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117927 GIM_Try, /*On fail goto*//*Label 6652*/ GIMT_Encode4(321104), // Rule ID 12693 //
117928 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
117929 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
117930 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
117931 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
117932 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117933 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
117934 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
117935 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
117936 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
117937 // MIs[2] Operand 1
117938 // No operand predicates
117939 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117940 GIM_CheckIsSafeToFold, /*NumInsns*/2,
117941 // (strict_fmul:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rn) => (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
117942 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
117943 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117944 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
117945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
117946 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
117947 GIR_RootConstrainSelectedInstOperands,
117948 // GIR_Coverage, 12693,
117949 GIR_EraseRootFromParent_Done,
117950 // Label 6652: @321104
117951 GIM_Try, /*On fail goto*//*Label 6653*/ GIMT_Encode4(321167), // Rule ID 1985 //
117952 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
117953 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117954 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
117955 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
117956 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
117957 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
117958 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
117959 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
117960 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
117961 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
117962 // MIs[2] Operand 1
117963 // No operand predicates
117964 GIM_CheckIsSafeToFold, /*NumInsns*/2,
117965 // (strict_fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
117966 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
117967 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
117968 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
117969 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
117970 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
117971 GIR_RootConstrainSelectedInstOperands,
117972 // GIR_Coverage, 1985,
117973 GIR_EraseRootFromParent_Done,
117974 // Label 6653: @321167
117975 GIM_Try, /*On fail goto*//*Label 6654*/ GIMT_Encode4(321194), // Rule ID 1305 //
117976 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
117977 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117978 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
117979 // (strict_fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FMULv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
117980 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f16),
117981 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
117982 GIR_RootConstrainSelectedInstOperands,
117983 // GIR_Coverage, 1305,
117984 GIR_Done,
117985 // Label 6654: @321194
117986 GIM_Reject,
117987 // Label 6651: @321195
117988 GIM_Reject,
117989 // Label 6612: @321196
117990 GIM_Try, /*On fail goto*//*Label 6655*/ GIMT_Encode4(321553),
117991 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
117992 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
117993 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
117994 GIM_Try, /*On fail goto*//*Label 6656*/ GIMT_Encode4(321274), // Rule ID 12702 //
117995 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
117996 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
117997 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
117998 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
117999 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
118000 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118001 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
118002 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
118003 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
118004 // MIs[2] Operand 1
118005 // No operand predicates
118006 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118007 GIM_CheckIsSafeToFold, /*NumInsns*/2,
118008 // (strict_fmul:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
118009 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
118010 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
118011 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
118012 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
118013 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
118014 GIR_RootConstrainSelectedInstOperands,
118015 // GIR_Coverage, 12702,
118016 GIR_EraseRootFromParent_Done,
118017 // Label 6656: @321274
118018 GIM_Try, /*On fail goto*//*Label 6657*/ GIMT_Encode4(321337), // Rule ID 1994 //
118019 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
118020 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118021 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
118022 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
118023 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
118024 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
118025 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118026 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
118027 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
118028 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
118029 // MIs[2] Operand 1
118030 // No operand predicates
118031 GIM_CheckIsSafeToFold, /*NumInsns*/2,
118032 // (strict_fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
118033 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
118034 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
118035 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
118036 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
118037 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
118038 GIR_RootConstrainSelectedInstOperands,
118039 // GIR_Coverage, 1994,
118040 GIR_EraseRootFromParent_Done,
118041 // Label 6657: @321337
118042 GIM_Try, /*On fail goto*//*Label 6658*/ GIMT_Encode4(321431), // Rule ID 13172 //
118043 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
118044 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
118045 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
118046 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
118047 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118048 GIM_CheckIsSafeToFold, /*NumInsns*/1,
118049 // (strict_fmul:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rn) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
118050 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
118051 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
118052 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
118053 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118054 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
118055 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
118056 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118057 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
118058 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
118059 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
118060 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
118061 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118062 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
118063 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
118064 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
118065 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
118066 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
118067 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
118068 GIR_RootConstrainSelectedInstOperands,
118069 // GIR_Coverage, 13172,
118070 GIR_EraseRootFromParent_Done,
118071 // Label 6658: @321431
118072 GIM_Try, /*On fail goto*//*Label 6659*/ GIMT_Encode4(321525), // Rule ID 5838 //
118073 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118074 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
118075 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
118076 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
118077 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
118078 GIM_CheckIsSafeToFold, /*NumInsns*/1,
118079 // (strict_fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rm)) => (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
118080 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
118081 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
118082 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
118083 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118084 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
118085 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
118086 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118087 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
118088 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
118089 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
118090 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
118091 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118092 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
118093 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
118094 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
118095 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
118096 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
118097 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
118098 GIR_RootConstrainSelectedInstOperands,
118099 // GIR_Coverage, 5838,
118100 GIR_EraseRootFromParent_Done,
118101 // Label 6659: @321525
118102 GIM_Try, /*On fail goto*//*Label 6660*/ GIMT_Encode4(321552), // Rule ID 1311 //
118103 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
118104 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118105 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118106 // (strict_fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FMULv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
118107 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
118108 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
118109 GIR_RootConstrainSelectedInstOperands,
118110 // GIR_Coverage, 1311,
118111 GIR_Done,
118112 // Label 6660: @321552
118113 GIM_Reject,
118114 // Label 6655: @321553
118115 GIM_Reject,
118116 // Label 6613: @321554
118117 GIM_Try, /*On fail goto*//*Label 6661*/ GIMT_Encode4(323278),
118118 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
118119 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
118120 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118121 GIM_Try, /*On fail goto*//*Label 6662*/ GIMT_Encode4(321632), // Rule ID 12696 //
118122 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
118123 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
118124 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
118125 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
118126 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
118127 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
118128 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
118129 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
118130 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
118131 // MIs[2] Operand 1
118132 // No operand predicates
118133 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118134 GIM_CheckIsSafeToFold, /*NumInsns*/2,
118135 // (strict_fmul:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rn) => (FMULv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
118136 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv8i16_indexed),
118137 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
118138 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
118139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
118140 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
118141 GIR_RootConstrainSelectedInstOperands,
118142 // GIR_Coverage, 12696,
118143 GIR_EraseRootFromParent_Done,
118144 // Label 6662: @321632
118145 GIM_Try, /*On fail goto*//*Label 6663*/ GIMT_Encode4(321695), // Rule ID 1988 //
118146 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
118147 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118148 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
118149 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
118150 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
118151 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
118152 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
118153 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
118154 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
118155 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
118156 // MIs[2] Operand 1
118157 // No operand predicates
118158 GIM_CheckIsSafeToFold, /*NumInsns*/2,
118159 // (strict_fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (FMULv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
118160 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv8i16_indexed),
118161 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
118162 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
118163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
118164 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
118165 GIR_RootConstrainSelectedInstOperands,
118166 // GIR_Coverage, 1988,
118167 GIR_EraseRootFromParent_Done,
118168 // Label 6663: @321695
118169 GIM_Try, /*On fail goto*//*Label 6664*/ GIMT_Encode4(321722), // Rule ID 1307 //
118170 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
118171 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118172 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118173 // (strict_fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FMULv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
118174 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv8f16),
118175 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
118176 GIR_RootConstrainSelectedInstOperands,
118177 // GIR_Coverage, 1307,
118178 GIR_Done,
118179 // Label 6664: @321722
118180 GIM_Try, /*On fail goto*//*Label 6665*/ GIMT_Encode4(321984), // Rule ID 6727 //
118181 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
118182 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118183 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118184 // (strict_fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FMULv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FMULv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
118185 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
118186 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
118187 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
118188 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
118189 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
118190 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
118191 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
118192 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
118193 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
118194 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
118195 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
118196 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
118197 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118198 GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
118199 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
118200 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
118201 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118202 GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
118203 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
118204 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
118205 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118206 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
118207 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
118208 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
118209 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
118210 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118211 GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
118212 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
118213 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118214 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
118215 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118216 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
118217 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
118218 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
118219 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118220 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
118221 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
118222 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118223 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
118224 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118225 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
118226 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
118227 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
118228 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118229 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
118230 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
118231 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
118232 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
118233 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118234 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
118235 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
118236 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
118237 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118238 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
118239 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
118240 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118241 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
118242 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
118243 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
118244 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
118245 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118246 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
118247 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
118248 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
118249 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
118250 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
118251 GIR_RootConstrainSelectedInstOperands,
118252 // GIR_Coverage, 6727,
118253 GIR_EraseRootFromParent_Done,
118254 // Label 6665: @321984
118255 GIM_Try, /*On fail goto*//*Label 6666*/ GIMT_Encode4(322196), // Rule ID 6729 //
118256 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16),
118257 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118258 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118259 // (strict_fmul:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFCVTN2:{ *:[v8bf16] } (BFCVTN:{ *:[v8bf16] } (FMULv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] })))), (FMULv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)))
118260 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
118261 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
118262 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
118263 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
118264 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
118265 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
118266 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
118267 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
118268 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
118269 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
118270 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118271 GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/0, /*OpIdx*/2, // Rm
118272 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
118273 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
118274 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118275 GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
118276 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
118277 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
118278 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118279 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
118280 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/8,
118281 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
118282 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
118283 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118284 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
118285 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
118286 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118287 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
118288 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118289 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
118290 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
118291 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
118292 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118293 GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
118294 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
118295 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118296 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
118297 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118298 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
118299 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
118300 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
118301 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118302 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
118303 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/4,
118304 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
118305 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN),
118306 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118307 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
118308 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
118309 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN2),
118310 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
118311 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
118312 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
118313 GIR_RootConstrainSelectedInstOperands,
118314 // GIR_Coverage, 6729,
118315 GIR_EraseRootFromParent_Done,
118316 // Label 6666: @322196
118317 GIM_Try, /*On fail goto*//*Label 6667*/ GIMT_Encode4(323277), // Rule ID 6731 //
118318 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoBF16),
118319 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118320 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118321 // (strict_fmul:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (UZP2v8i16:{ *:[v8bf16] } (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FMULv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), (FMULv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] })))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FMULv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FMULv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), 64:{ *:[i32] }, 16:{ *:[i32] })), (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FMULv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), (FMULv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FMULv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FMULv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), 64:{ *:[i32] }, 16:{ *:[i32] })))
118322 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
118323 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
118324 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
118325 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
118326 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
118327 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
118328 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
118329 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
118330 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
118331 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s16,
118332 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
118333 GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_v4s16,
118334 GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_s128,
118335 GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s128,
118336 GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_v4s32,
118337 GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_v4s32,
118338 GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_v4s16,
118339 GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_v4s32,
118340 GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_v4s16,
118341 GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_s128,
118342 GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_s128,
118343 GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s128,
118344 GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s128,
118345 GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_s128,
118346 GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_v4s32,
118347 GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_v4s32,
118348 GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_v4s16,
118349 GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_v4s32,
118350 GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_v4s16,
118351 GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_s128,
118352 GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_s128,
118353 GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_v4s32,
118354 GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_v4s32,
118355 GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_v4s32,
118356 GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_v4s32,
118357 GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_v4s32,
118358 GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_v4s32,
118359 GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_s128,
118360 GIR_MakeTempReg, /*TempRegID*/38, /*TypeID*/GILLT_s128,
118361 GIR_MakeTempReg, /*TempRegID*/39, /*TypeID*/GILLT_v4s32,
118362 GIR_MakeTempReg, /*TempRegID*/40, /*TypeID*/GILLT_v4s32,
118363 GIR_MakeTempReg, /*TempRegID*/41, /*TypeID*/GILLT_v4s32,
118364 GIR_MakeTempReg, /*TempRegID*/42, /*TypeID*/GILLT_s128,
118365 GIR_MakeTempReg, /*TempRegID*/43, /*TypeID*/GILLT_s128,
118366 GIR_MakeTempReg, /*TempRegID*/44, /*TypeID*/GILLT_s128,
118367 GIR_MakeTempReg, /*TempRegID*/45, /*TypeID*/GILLT_s128,
118368 GIR_MakeTempReg, /*TempRegID*/46, /*TypeID*/GILLT_s128,
118369 GIR_MakeTempReg, /*TempRegID*/47, /*TypeID*/GILLT_v4s32,
118370 GIR_MakeTempReg, /*TempRegID*/48, /*TypeID*/GILLT_v4s32,
118371 GIR_MakeTempReg, /*TempRegID*/49, /*TypeID*/GILLT_v4s32,
118372 GIR_BuildMI, /*InsnID*/50, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
118373 GIR_AddTempRegister, /*InsnID*/50, /*TempRegID*/49, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118374 GIR_Copy, /*NewInsnID*/50, /*OldInsnID*/0, /*OpIdx*/2, // Rm
118375 GIR_ConstrainSelectedInstOperands, /*InsnID*/50,
118376 GIR_BuildMI, /*InsnID*/49, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
118377 GIR_AddTempRegister, /*InsnID*/49, /*TempRegID*/48, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118378 GIR_Copy, /*NewInsnID*/49, /*OldInsnID*/0, /*OpIdx*/1, // Rn
118379 GIR_ConstrainSelectedInstOperands, /*InsnID*/49,
118380 GIR_BuildMI, /*InsnID*/48, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
118381 GIR_AddTempRegister, /*InsnID*/48, /*TempRegID*/47, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118382 GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/48,
118383 GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/49,
118384 GIR_ConstrainSelectedInstOperands, /*InsnID*/48,
118385 GIR_BuildMI, /*InsnID*/47, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
118386 GIR_AddTempRegister, /*InsnID*/47, /*TempRegID*/46, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118387 GIR_AddSimpleTempRegister, /*InsnID*/47, /*TempRegID*/47,
118388 GIR_AddImm8, /*InsnID*/47, /*Imm*/64,
118389 GIR_AddImm8, /*InsnID*/47, /*Imm*/16,
118390 GIR_ConstrainSelectedInstOperands, /*InsnID*/47,
118391 GIR_BuildMI, /*InsnID*/46, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
118392 GIR_AddTempRegister, /*InsnID*/46, /*TempRegID*/45, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118393 GIR_AddImm8, /*InsnID*/46, /*Imm*/127,
118394 GIR_AddImm, /*InsnID*/46, /*Imm*/GIMT_Encode8(264),
118395 GIR_ConstrainSelectedInstOperands, /*InsnID*/46,
118396 GIR_BuildMI, /*InsnID*/45, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
118397 GIR_AddTempRegister, /*InsnID*/45, /*TempRegID*/44, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118398 GIR_AddImm8, /*InsnID*/45, /*Imm*/1,
118399 GIR_AddImm8, /*InsnID*/45, /*Imm*/0,
118400 GIR_ConstrainSelectedInstOperands, /*InsnID*/45,
118401 GIR_BuildMI, /*InsnID*/44, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
118402 GIR_AddTempRegister, /*InsnID*/44, /*TempRegID*/43, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118403 GIR_Copy, /*NewInsnID*/44, /*OldInsnID*/0, /*OpIdx*/1, // Rn
118404 GIR_AddImm8, /*InsnID*/44, /*Imm*/16,
118405 GIR_ConstrainSelectedInstOperands, /*InsnID*/44,
118406 GIR_BuildMI, /*InsnID*/43, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
118407 GIR_AddTempRegister, /*InsnID*/43, /*TempRegID*/42, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118408 GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/43,
118409 GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/44,
118410 GIR_ConstrainSelectedInstOperands, /*InsnID*/43,
118411 GIR_BuildMI, /*InsnID*/42, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
118412 GIR_AddTempRegister, /*InsnID*/42, /*TempRegID*/41, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118413 GIR_Copy, /*NewInsnID*/42, /*OldInsnID*/0, /*OpIdx*/2, // Rm
118414 GIR_ConstrainSelectedInstOperands, /*InsnID*/42,
118415 GIR_BuildMI, /*InsnID*/41, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
118416 GIR_AddTempRegister, /*InsnID*/41, /*TempRegID*/40, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118417 GIR_Copy, /*NewInsnID*/41, /*OldInsnID*/0, /*OpIdx*/1, // Rn
118418 GIR_ConstrainSelectedInstOperands, /*InsnID*/41,
118419 GIR_BuildMI, /*InsnID*/40, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
118420 GIR_AddTempRegister, /*InsnID*/40, /*TempRegID*/39, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118421 GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/40,
118422 GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/41,
118423 GIR_ConstrainSelectedInstOperands, /*InsnID*/40,
118424 GIR_BuildMI, /*InsnID*/39, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
118425 GIR_AddTempRegister, /*InsnID*/39, /*TempRegID*/38, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118426 GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/39,
118427 GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/42,
118428 GIR_ConstrainSelectedInstOperands, /*InsnID*/39,
118429 GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
118430 GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118431 GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/38,
118432 GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/45,
118433 GIR_ConstrainSelectedInstOperands, /*InsnID*/38,
118434 GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
118435 GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118436 GIR_Copy, /*NewInsnID*/37, /*OldInsnID*/0, /*OpIdx*/2, // Rm
118437 GIR_ConstrainSelectedInstOperands, /*InsnID*/37,
118438 GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
118439 GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118440 GIR_Copy, /*NewInsnID*/36, /*OldInsnID*/0, /*OpIdx*/1, // Rn
118441 GIR_ConstrainSelectedInstOperands, /*InsnID*/36,
118442 GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
118443 GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118444 GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/35,
118445 GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/36,
118446 GIR_ConstrainSelectedInstOperands, /*InsnID*/35,
118447 GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
118448 GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118449 GIR_Copy, /*NewInsnID*/34, /*OldInsnID*/0, /*OpIdx*/2, // Rm
118450 GIR_ConstrainSelectedInstOperands, /*InsnID*/34,
118451 GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
118452 GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118453 GIR_Copy, /*NewInsnID*/33, /*OldInsnID*/0, /*OpIdx*/1, // Rn
118454 GIR_ConstrainSelectedInstOperands, /*InsnID*/33,
118455 GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
118456 GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118457 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/32,
118458 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/33,
118459 GIR_ConstrainSelectedInstOperands, /*InsnID*/32,
118460 GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
118461 GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118462 GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/31,
118463 GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/34,
118464 GIR_ConstrainSelectedInstOperands, /*InsnID*/31,
118465 GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
118466 GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118467 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/30,
118468 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/37,
118469 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/46,
118470 GIR_ConstrainSelectedInstOperands, /*InsnID*/30,
118471 GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
118472 GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118473 GIR_CopySubReg, /*NewInsnID*/29, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
118474 GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
118475 GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118476 GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
118477 GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118478 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/28,
118479 GIR_ConstrainSelectedInstOperands, /*InsnID*/28,
118480 GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
118481 GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118482 GIR_CopySubReg, /*NewInsnID*/27, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
118483 GIR_ConstrainOperandRC, /*InsnID*/27, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
118484 GIR_ConstrainOperandRC, /*InsnID*/27, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118485 GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
118486 GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118487 GIR_AddSimpleTempRegister, /*InsnID*/26, /*TempRegID*/26,
118488 GIR_ConstrainSelectedInstOperands, /*InsnID*/26,
118489 GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
118490 GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118491 GIR_AddSimpleTempRegister, /*InsnID*/25, /*TempRegID*/25,
118492 GIR_AddSimpleTempRegister, /*InsnID*/25, /*TempRegID*/27,
118493 GIR_ConstrainSelectedInstOperands, /*InsnID*/25,
118494 GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
118495 GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118496 GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/24,
118497 GIR_AddImm8, /*InsnID*/24, /*Imm*/64,
118498 GIR_AddImm8, /*InsnID*/24, /*Imm*/16,
118499 GIR_ConstrainSelectedInstOperands, /*InsnID*/24,
118500 GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
118501 GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118502 GIR_AddImm8, /*InsnID*/23, /*Imm*/127,
118503 GIR_AddImm, /*InsnID*/23, /*Imm*/GIMT_Encode8(264),
118504 GIR_ConstrainSelectedInstOperands, /*InsnID*/23,
118505 GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
118506 GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118507 GIR_AddImm8, /*InsnID*/22, /*Imm*/1,
118508 GIR_AddImm8, /*InsnID*/22, /*Imm*/0,
118509 GIR_ConstrainSelectedInstOperands, /*InsnID*/22,
118510 GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
118511 GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118512 GIR_Copy, /*NewInsnID*/21, /*OldInsnID*/0, /*OpIdx*/1, // Rn
118513 GIR_AddImm8, /*InsnID*/21, /*Imm*/16,
118514 GIR_ConstrainSelectedInstOperands, /*InsnID*/21,
118515 GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
118516 GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118517 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/20,
118518 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/21,
118519 GIR_ConstrainSelectedInstOperands, /*InsnID*/20,
118520 GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
118521 GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118522 GIR_CopySubReg, /*NewInsnID*/19, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
118523 GIR_ConstrainOperandRC, /*InsnID*/19, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
118524 GIR_ConstrainOperandRC, /*InsnID*/19, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118525 GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
118526 GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118527 GIR_AddSimpleTempRegister, /*InsnID*/18, /*TempRegID*/18,
118528 GIR_ConstrainSelectedInstOperands, /*InsnID*/18,
118529 GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
118530 GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118531 GIR_CopySubReg, /*NewInsnID*/17, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
118532 GIR_ConstrainOperandRC, /*InsnID*/17, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
118533 GIR_ConstrainOperandRC, /*InsnID*/17, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118534 GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
118535 GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118536 GIR_AddSimpleTempRegister, /*InsnID*/16, /*TempRegID*/16,
118537 GIR_ConstrainSelectedInstOperands, /*InsnID*/16,
118538 GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
118539 GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118540 GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/15,
118541 GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/17,
118542 GIR_ConstrainSelectedInstOperands, /*InsnID*/15,
118543 GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
118544 GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118545 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14,
118546 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/19,
118547 GIR_ConstrainSelectedInstOperands, /*InsnID*/14,
118548 GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
118549 GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118550 GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/13,
118551 GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/22,
118552 GIR_ConstrainSelectedInstOperands, /*InsnID*/13,
118553 GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
118554 GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118555 GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
118556 GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
118557 GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118558 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
118559 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118560 GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11,
118561 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
118562 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
118563 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118564 GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
118565 GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
118566 GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118567 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
118568 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118569 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
118570 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
118571 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
118572 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118573 GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
118574 GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/10,
118575 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
118576 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
118577 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118578 GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
118579 GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
118580 GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118581 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
118582 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118583 GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
118584 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
118585 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
118586 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118587 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
118588 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
118589 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118590 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
118591 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118592 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
118593 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
118594 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
118595 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118596 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
118597 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/5,
118598 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
118599 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
118600 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118601 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
118602 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/7,
118603 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
118604 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
118605 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118606 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
118607 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/12,
118608 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/23,
118609 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
118610 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
118611 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
118612 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
118613 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/29,
118614 GIR_RootConstrainSelectedInstOperands,
118615 // GIR_Coverage, 6731,
118616 GIR_EraseRootFromParent_Done,
118617 // Label 6667: @323277
118618 GIM_Reject,
118619 // Label 6661: @323278
118620 GIM_Reject,
118621 // Label 6614: @323279
118622 GIM_Reject,
118623 // Label 93: @323280
118624 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6676*/ GIMT_Encode4(325172),
118625 /*GILLT_s16*//*Label 6668*/ GIMT_Encode4(323331),
118626 /*GILLT_s32*//*Label 6669*/ GIMT_Encode4(323369),
118627 /*GILLT_s64*//*Label 6670*/ GIMT_Encode4(323407), GIMT_Encode4(0),
118628 /*GILLT_v2s32*//*Label 6671*/ GIMT_Encode4(323445),
118629 /*GILLT_v2s64*//*Label 6672*/ GIMT_Encode4(323483),
118630 /*GILLT_v4s16*//*Label 6673*/ GIMT_Encode4(323521),
118631 /*GILLT_v4s32*//*Label 6674*/ GIMT_Encode4(323559), GIMT_Encode4(0),
118632 /*GILLT_v8s16*//*Label 6675*/ GIMT_Encode4(323597),
118633 // Label 6668: @323331
118634 GIM_Try, /*On fail goto*//*Label 6677*/ GIMT_Encode4(323368), // Rule ID 583 //
118635 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
118636 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
118637 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
118638 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
118639 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
118640 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
118641 // (strict_fdiv:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm) => (FDIVHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
118642 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVHrr),
118643 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
118644 GIR_RootConstrainSelectedInstOperands,
118645 // GIR_Coverage, 583,
118646 GIR_Done,
118647 // Label 6677: @323368
118648 GIM_Reject,
118649 // Label 6669: @323369
118650 GIM_Try, /*On fail goto*//*Label 6678*/ GIMT_Encode4(323406), // Rule ID 585 //
118651 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
118652 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
118653 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
118654 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
118655 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
118656 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
118657 // (strict_fdiv:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FDIVSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
118658 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVSrr),
118659 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
118660 GIR_RootConstrainSelectedInstOperands,
118661 // GIR_Coverage, 585,
118662 GIR_Done,
118663 // Label 6678: @323406
118664 GIM_Reject,
118665 // Label 6670: @323407
118666 GIM_Try, /*On fail goto*//*Label 6679*/ GIMT_Encode4(323444), // Rule ID 587 //
118667 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
118668 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
118669 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
118670 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
118671 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
118672 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
118673 // (strict_fdiv:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FDIVDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
118674 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVDrr),
118675 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
118676 GIR_RootConstrainSelectedInstOperands,
118677 // GIR_Coverage, 587,
118678 GIR_Done,
118679 // Label 6679: @323444
118680 GIM_Reject,
118681 // Label 6671: @323445
118682 GIM_Try, /*On fail goto*//*Label 6680*/ GIMT_Encode4(323482), // Rule ID 1214 //
118683 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
118684 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
118685 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
118686 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
118687 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
118688 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
118689 // (strict_fdiv:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FDIVv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
118690 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv2f32),
118691 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
118692 GIR_RootConstrainSelectedInstOperands,
118693 // GIR_Coverage, 1214,
118694 GIR_Done,
118695 // Label 6680: @323482
118696 GIM_Reject,
118697 // Label 6672: @323483
118698 GIM_Try, /*On fail goto*//*Label 6681*/ GIMT_Encode4(323520), // Rule ID 1218 //
118699 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
118700 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
118701 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
118702 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118703 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118704 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118705 // (strict_fdiv:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FDIVv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
118706 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv2f64),
118707 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
118708 GIR_RootConstrainSelectedInstOperands,
118709 // GIR_Coverage, 1218,
118710 GIR_Done,
118711 // Label 6681: @323520
118712 GIM_Reject,
118713 // Label 6673: @323521
118714 GIM_Try, /*On fail goto*//*Label 6682*/ GIMT_Encode4(323558), // Rule ID 1210 //
118715 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
118716 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
118717 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
118718 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
118719 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
118720 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
118721 // (strict_fdiv:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FDIVv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
118722 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f16),
118723 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
118724 GIR_RootConstrainSelectedInstOperands,
118725 // GIR_Coverage, 1210,
118726 GIR_Done,
118727 // Label 6682: @323558
118728 GIM_Reject,
118729 // Label 6674: @323559
118730 GIM_Try, /*On fail goto*//*Label 6683*/ GIMT_Encode4(323596), // Rule ID 1216 //
118731 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
118732 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
118733 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
118734 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118735 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118736 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118737 // (strict_fdiv:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FDIVv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
118738 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
118739 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
118740 GIR_RootConstrainSelectedInstOperands,
118741 // GIR_Coverage, 1216,
118742 GIR_Done,
118743 // Label 6683: @323596
118744 GIM_Reject,
118745 // Label 6675: @323597
118746 GIM_Try, /*On fail goto*//*Label 6684*/ GIMT_Encode4(325171),
118747 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
118748 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
118749 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118750 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118751 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
118752 GIM_Try, /*On fail goto*//*Label 6685*/ GIMT_Encode4(323639), // Rule ID 1212 //
118753 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
118754 // (strict_fdiv:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FDIVv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
118755 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv8f16),
118756 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
118757 GIR_RootConstrainSelectedInstOperands,
118758 // GIR_Coverage, 1212,
118759 GIR_Done,
118760 // Label 6685: @323639
118761 GIM_Try, /*On fail goto*//*Label 6686*/ GIMT_Encode4(323893), // Rule ID 6721 //
118762 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
118763 // (strict_fdiv:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FDIVv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FDIVv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
118764 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
118765 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
118766 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
118767 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
118768 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
118769 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
118770 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
118771 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
118772 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
118773 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
118774 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
118775 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
118776 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118777 GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
118778 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
118779 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
118780 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118781 GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
118782 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
118783 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
118784 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118785 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
118786 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
118787 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
118788 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
118789 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118790 GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
118791 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
118792 GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118793 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
118794 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118795 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
118796 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
118797 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
118798 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118799 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
118800 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
118801 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118802 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
118803 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118804 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
118805 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
118806 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
118807 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118808 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
118809 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
118810 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
118811 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
118812 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118813 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
118814 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
118815 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
118816 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118817 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
118818 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
118819 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118820 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
118821 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
118822 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
118823 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
118824 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118825 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
118826 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
118827 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
118828 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
118829 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
118830 GIR_RootConstrainSelectedInstOperands,
118831 // GIR_Coverage, 6721,
118832 GIR_EraseRootFromParent_Done,
118833 // Label 6686: @323893
118834 GIM_Try, /*On fail goto*//*Label 6687*/ GIMT_Encode4(324097), // Rule ID 6723 //
118835 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBF16),
118836 // (strict_fdiv:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (BFCVTN2:{ *:[v8bf16] } (BFCVTN:{ *:[v8bf16] } (FDIVv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] })))), (FDIVv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)))
118837 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
118838 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
118839 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
118840 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
118841 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
118842 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
118843 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
118844 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
118845 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
118846 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
118847 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118848 GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/0, /*OpIdx*/2, // Rm
118849 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
118850 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
118851 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118852 GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
118853 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
118854 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
118855 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118856 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
118857 GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/8,
118858 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
118859 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
118860 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118861 GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
118862 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
118863 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118864 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
118865 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118866 GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
118867 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
118868 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
118869 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118870 GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
118871 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
118872 GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
118873 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
118874 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118875 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
118876 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
118877 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
118878 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118879 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
118880 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/4,
118881 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
118882 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN),
118883 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118884 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
118885 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
118886 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFCVTN2),
118887 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
118888 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
118889 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
118890 GIR_RootConstrainSelectedInstOperands,
118891 // GIR_Coverage, 6723,
118892 GIR_EraseRootFromParent_Done,
118893 // Label 6687: @324097
118894 GIM_Try, /*On fail goto*//*Label 6688*/ GIMT_Encode4(325170), // Rule ID 6725 //
118895 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoBF16),
118896 // (strict_fdiv:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (UZP2v8i16:{ *:[v8bf16] } (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FDIVv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), (FDIVv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] })))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FDIVv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FDIVv4f32:{ *:[v4f32] } (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rn, dsub:{ *:[i32] })), (SHLLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8bf16] }:$Rm, dsub:{ *:[i32] }))), 64:{ *:[i32] }, 16:{ *:[i32] })), (BSPv16i8:{ *:[f128] } (FCMEQv4f32:{ *:[f128] } (FDIVv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), (FDIVv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm))), (ADDv4i32:{ *:[f128] } (ADDv4i32:{ *:[f128] } (FDIVv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), (ANDv16i8:{ *:[f128] } (USHRv4i32_shift:{ *:[f128] } V128:{ *:[v8bf16] }:$Rn, 16:{ *:[i32] }), (MOVIv4i32:{ *:[f128] } 1:{ *:[i32] }, 0:{ *:[i32] }))), (MOVIv4s_msl:{ *:[f128] } 127:{ *:[i32] }, 264:{ *:[i32] })), (ORRv4i32:{ *:[f128] } (FDIVv4f32:{ *:[v4f32] } (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rn), (SHLLv8i16:{ *:[v4f32] } V128:{ *:[v8bf16] }:$Rm)), 64:{ *:[i32] }, 16:{ *:[i32] })))
118897 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
118898 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
118899 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
118900 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
118901 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
118902 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s32,
118903 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
118904 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
118905 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
118906 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s16,
118907 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
118908 GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_v4s16,
118909 GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_s128,
118910 GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s128,
118911 GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_v4s32,
118912 GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_v4s32,
118913 GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_v4s16,
118914 GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_v4s32,
118915 GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_v4s16,
118916 GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_s128,
118917 GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_s128,
118918 GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s128,
118919 GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s128,
118920 GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_s128,
118921 GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_v4s32,
118922 GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_v4s32,
118923 GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_v4s16,
118924 GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_v4s32,
118925 GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_v4s16,
118926 GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_s128,
118927 GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_s128,
118928 GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_v4s32,
118929 GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_v4s32,
118930 GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_v4s32,
118931 GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_v4s32,
118932 GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_v4s32,
118933 GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_v4s32,
118934 GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_s128,
118935 GIR_MakeTempReg, /*TempRegID*/38, /*TypeID*/GILLT_s128,
118936 GIR_MakeTempReg, /*TempRegID*/39, /*TypeID*/GILLT_v4s32,
118937 GIR_MakeTempReg, /*TempRegID*/40, /*TypeID*/GILLT_v4s32,
118938 GIR_MakeTempReg, /*TempRegID*/41, /*TypeID*/GILLT_v4s32,
118939 GIR_MakeTempReg, /*TempRegID*/42, /*TypeID*/GILLT_s128,
118940 GIR_MakeTempReg, /*TempRegID*/43, /*TypeID*/GILLT_s128,
118941 GIR_MakeTempReg, /*TempRegID*/44, /*TypeID*/GILLT_s128,
118942 GIR_MakeTempReg, /*TempRegID*/45, /*TypeID*/GILLT_s128,
118943 GIR_MakeTempReg, /*TempRegID*/46, /*TypeID*/GILLT_s128,
118944 GIR_MakeTempReg, /*TempRegID*/47, /*TypeID*/GILLT_v4s32,
118945 GIR_MakeTempReg, /*TempRegID*/48, /*TypeID*/GILLT_v4s32,
118946 GIR_MakeTempReg, /*TempRegID*/49, /*TypeID*/GILLT_v4s32,
118947 GIR_BuildMI, /*InsnID*/50, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
118948 GIR_AddTempRegister, /*InsnID*/50, /*TempRegID*/49, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118949 GIR_Copy, /*NewInsnID*/50, /*OldInsnID*/0, /*OpIdx*/2, // Rm
118950 GIR_ConstrainSelectedInstOperands, /*InsnID*/50,
118951 GIR_BuildMI, /*InsnID*/49, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
118952 GIR_AddTempRegister, /*InsnID*/49, /*TempRegID*/48, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118953 GIR_Copy, /*NewInsnID*/49, /*OldInsnID*/0, /*OpIdx*/1, // Rn
118954 GIR_ConstrainSelectedInstOperands, /*InsnID*/49,
118955 GIR_BuildMI, /*InsnID*/48, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
118956 GIR_AddTempRegister, /*InsnID*/48, /*TempRegID*/47, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118957 GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/48,
118958 GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/49,
118959 GIR_ConstrainSelectedInstOperands, /*InsnID*/48,
118960 GIR_BuildMI, /*InsnID*/47, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
118961 GIR_AddTempRegister, /*InsnID*/47, /*TempRegID*/46, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118962 GIR_AddSimpleTempRegister, /*InsnID*/47, /*TempRegID*/47,
118963 GIR_AddImm8, /*InsnID*/47, /*Imm*/64,
118964 GIR_AddImm8, /*InsnID*/47, /*Imm*/16,
118965 GIR_ConstrainSelectedInstOperands, /*InsnID*/47,
118966 GIR_BuildMI, /*InsnID*/46, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
118967 GIR_AddTempRegister, /*InsnID*/46, /*TempRegID*/45, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118968 GIR_AddImm8, /*InsnID*/46, /*Imm*/127,
118969 GIR_AddImm, /*InsnID*/46, /*Imm*/GIMT_Encode8(264),
118970 GIR_ConstrainSelectedInstOperands, /*InsnID*/46,
118971 GIR_BuildMI, /*InsnID*/45, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
118972 GIR_AddTempRegister, /*InsnID*/45, /*TempRegID*/44, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118973 GIR_AddImm8, /*InsnID*/45, /*Imm*/1,
118974 GIR_AddImm8, /*InsnID*/45, /*Imm*/0,
118975 GIR_ConstrainSelectedInstOperands, /*InsnID*/45,
118976 GIR_BuildMI, /*InsnID*/44, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
118977 GIR_AddTempRegister, /*InsnID*/44, /*TempRegID*/43, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118978 GIR_Copy, /*NewInsnID*/44, /*OldInsnID*/0, /*OpIdx*/1, // Rn
118979 GIR_AddImm8, /*InsnID*/44, /*Imm*/16,
118980 GIR_ConstrainSelectedInstOperands, /*InsnID*/44,
118981 GIR_BuildMI, /*InsnID*/43, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
118982 GIR_AddTempRegister, /*InsnID*/43, /*TempRegID*/42, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118983 GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/43,
118984 GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/44,
118985 GIR_ConstrainSelectedInstOperands, /*InsnID*/43,
118986 GIR_BuildMI, /*InsnID*/42, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
118987 GIR_AddTempRegister, /*InsnID*/42, /*TempRegID*/41, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118988 GIR_Copy, /*NewInsnID*/42, /*OldInsnID*/0, /*OpIdx*/2, // Rm
118989 GIR_ConstrainSelectedInstOperands, /*InsnID*/42,
118990 GIR_BuildMI, /*InsnID*/41, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
118991 GIR_AddTempRegister, /*InsnID*/41, /*TempRegID*/40, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118992 GIR_Copy, /*NewInsnID*/41, /*OldInsnID*/0, /*OpIdx*/1, // Rn
118993 GIR_ConstrainSelectedInstOperands, /*InsnID*/41,
118994 GIR_BuildMI, /*InsnID*/40, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
118995 GIR_AddTempRegister, /*InsnID*/40, /*TempRegID*/39, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
118996 GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/40,
118997 GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/41,
118998 GIR_ConstrainSelectedInstOperands, /*InsnID*/40,
118999 GIR_BuildMI, /*InsnID*/39, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
119000 GIR_AddTempRegister, /*InsnID*/39, /*TempRegID*/38, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119001 GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/39,
119002 GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/42,
119003 GIR_ConstrainSelectedInstOperands, /*InsnID*/39,
119004 GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
119005 GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119006 GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/38,
119007 GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/45,
119008 GIR_ConstrainSelectedInstOperands, /*InsnID*/38,
119009 GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
119010 GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119011 GIR_Copy, /*NewInsnID*/37, /*OldInsnID*/0, /*OpIdx*/2, // Rm
119012 GIR_ConstrainSelectedInstOperands, /*InsnID*/37,
119013 GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
119014 GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119015 GIR_Copy, /*NewInsnID*/36, /*OldInsnID*/0, /*OpIdx*/1, // Rn
119016 GIR_ConstrainSelectedInstOperands, /*InsnID*/36,
119017 GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
119018 GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119019 GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/35,
119020 GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/36,
119021 GIR_ConstrainSelectedInstOperands, /*InsnID*/35,
119022 GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
119023 GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119024 GIR_Copy, /*NewInsnID*/34, /*OldInsnID*/0, /*OpIdx*/2, // Rm
119025 GIR_ConstrainSelectedInstOperands, /*InsnID*/34,
119026 GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(AArch64::SHLLv8i16),
119027 GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119028 GIR_Copy, /*NewInsnID*/33, /*OldInsnID*/0, /*OpIdx*/1, // Rn
119029 GIR_ConstrainSelectedInstOperands, /*InsnID*/33,
119030 GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
119031 GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119032 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/32,
119033 GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/33,
119034 GIR_ConstrainSelectedInstOperands, /*InsnID*/32,
119035 GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
119036 GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119037 GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/31,
119038 GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/34,
119039 GIR_ConstrainSelectedInstOperands, /*InsnID*/31,
119040 GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
119041 GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119042 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/30,
119043 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/37,
119044 GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/46,
119045 GIR_ConstrainSelectedInstOperands, /*InsnID*/30,
119046 GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119047 GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119048 GIR_CopySubReg, /*NewInsnID*/29, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
119049 GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
119050 GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119051 GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
119052 GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119053 GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/28,
119054 GIR_ConstrainSelectedInstOperands, /*InsnID*/28,
119055 GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119056 GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119057 GIR_CopySubReg, /*NewInsnID*/27, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
119058 GIR_ConstrainOperandRC, /*InsnID*/27, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
119059 GIR_ConstrainOperandRC, /*InsnID*/27, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119060 GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
119061 GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119062 GIR_AddSimpleTempRegister, /*InsnID*/26, /*TempRegID*/26,
119063 GIR_ConstrainSelectedInstOperands, /*InsnID*/26,
119064 GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
119065 GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119066 GIR_AddSimpleTempRegister, /*InsnID*/25, /*TempRegID*/25,
119067 GIR_AddSimpleTempRegister, /*InsnID*/25, /*TempRegID*/27,
119068 GIR_ConstrainSelectedInstOperands, /*InsnID*/25,
119069 GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(AArch64::ORRv4i32),
119070 GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119071 GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/24,
119072 GIR_AddImm8, /*InsnID*/24, /*Imm*/64,
119073 GIR_AddImm8, /*InsnID*/24, /*Imm*/16,
119074 GIR_ConstrainSelectedInstOperands, /*InsnID*/24,
119075 GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4s_msl),
119076 GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119077 GIR_AddImm8, /*InsnID*/23, /*Imm*/127,
119078 GIR_AddImm, /*InsnID*/23, /*Imm*/GIMT_Encode8(264),
119079 GIR_ConstrainSelectedInstOperands, /*InsnID*/23,
119080 GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i32),
119081 GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119082 GIR_AddImm8, /*InsnID*/22, /*Imm*/1,
119083 GIR_AddImm8, /*InsnID*/22, /*Imm*/0,
119084 GIR_ConstrainSelectedInstOperands, /*InsnID*/22,
119085 GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
119086 GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119087 GIR_Copy, /*NewInsnID*/21, /*OldInsnID*/0, /*OpIdx*/1, // Rn
119088 GIR_AddImm8, /*InsnID*/21, /*Imm*/16,
119089 GIR_ConstrainSelectedInstOperands, /*InsnID*/21,
119090 GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
119091 GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119092 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/20,
119093 GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/21,
119094 GIR_ConstrainSelectedInstOperands, /*InsnID*/20,
119095 GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119096 GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119097 GIR_CopySubReg, /*NewInsnID*/19, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
119098 GIR_ConstrainOperandRC, /*InsnID*/19, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
119099 GIR_ConstrainOperandRC, /*InsnID*/19, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119100 GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
119101 GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119102 GIR_AddSimpleTempRegister, /*InsnID*/18, /*TempRegID*/18,
119103 GIR_ConstrainSelectedInstOperands, /*InsnID*/18,
119104 GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119105 GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119106 GIR_CopySubReg, /*NewInsnID*/17, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
119107 GIR_ConstrainOperandRC, /*InsnID*/17, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
119108 GIR_ConstrainOperandRC, /*InsnID*/17, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119109 GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
119110 GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119111 GIR_AddSimpleTempRegister, /*InsnID*/16, /*TempRegID*/16,
119112 GIR_ConstrainSelectedInstOperands, /*InsnID*/16,
119113 GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
119114 GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119115 GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/15,
119116 GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/17,
119117 GIR_ConstrainSelectedInstOperands, /*InsnID*/15,
119118 GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
119119 GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119120 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14,
119121 GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/19,
119122 GIR_ConstrainSelectedInstOperands, /*InsnID*/14,
119123 GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
119124 GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119125 GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/13,
119126 GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/22,
119127 GIR_ConstrainSelectedInstOperands, /*InsnID*/13,
119128 GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119129 GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119130 GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
119131 GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
119132 GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119133 GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
119134 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119135 GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11,
119136 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
119137 GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119138 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119139 GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
119140 GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
119141 GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119142 GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
119143 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119144 GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
119145 GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
119146 GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
119147 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119148 GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
119149 GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/10,
119150 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
119151 GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119152 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119153 GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(2), // Rm
119154 GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
119155 GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119156 GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
119157 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119158 GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
119159 GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
119160 GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119161 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119162 GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
119163 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
119164 GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119165 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SHLLv4i16),
119166 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119167 GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
119168 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
119169 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
119170 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119171 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
119172 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/5,
119173 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
119174 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
119175 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119176 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
119177 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/7,
119178 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
119179 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
119180 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119181 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
119182 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/12,
119183 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/23,
119184 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
119185 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
119186 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
119187 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
119188 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/29,
119189 GIR_RootConstrainSelectedInstOperands,
119190 // GIR_Coverage, 6725,
119191 GIR_EraseRootFromParent_Done,
119192 // Label 6688: @325170
119193 GIM_Reject,
119194 // Label 6684: @325171
119195 GIM_Reject,
119196 // Label 6676: @325172
119197 GIM_Reject,
119198 // Label 94: @325173
119199 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6697*/ GIMT_Encode4(336756),
119200 /*GILLT_s16*//*Label 6689*/ GIMT_Encode4(325224),
119201 /*GILLT_s32*//*Label 6690*/ GIMT_Encode4(326657),
119202 /*GILLT_s64*//*Label 6691*/ GIMT_Encode4(328246), GIMT_Encode4(0),
119203 /*GILLT_v2s32*//*Label 6692*/ GIMT_Encode4(329835),
119204 /*GILLT_v2s64*//*Label 6693*/ GIMT_Encode4(331356),
119205 /*GILLT_v4s16*//*Label 6694*/ GIMT_Encode4(332877),
119206 /*GILLT_v4s32*//*Label 6695*/ GIMT_Encode4(334056), GIMT_Encode4(0),
119207 /*GILLT_v8s16*//*Label 6696*/ GIMT_Encode4(335577),
119208 // Label 6689: @325224
119209 GIM_Try, /*On fail goto*//*Label 6698*/ GIMT_Encode4(326656),
119210 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
119211 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
119212 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
119213 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119214 GIM_Try, /*On fail goto*//*Label 6699*/ GIMT_Encode4(325342), // Rule ID 4502 //
119215 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
119216 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
119217 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119218 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
119219 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
119220 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
119221 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
119222 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
119223 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
119224 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
119225 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119226 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119227 GIM_CheckIsSafeToFold, /*NumInsns*/2,
119228 // (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
119229 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
119230 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119231 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119232 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
119233 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
119234 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119235 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
119236 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
119237 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
119238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
119239 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
119240 GIR_RootConstrainSelectedInstOperands,
119241 // GIR_Coverage, 4502,
119242 GIR_EraseRootFromParent_Done,
119243 // Label 6699: @325342
119244 GIM_Try, /*On fail goto*//*Label 6700*/ GIMT_Encode4(325442), // Rule ID 4526 //
119245 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
119246 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
119247 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119248 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
119249 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
119250 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
119251 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
119252 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119253 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
119254 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
119255 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
119256 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119257 GIM_CheckIsSafeToFold, /*NumInsns*/2,
119258 // (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra)) => (FNMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
119259 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
119260 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119261 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119262 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
119263 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
119264 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119265 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
119266 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
119267 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
119268 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
119269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
119270 GIR_RootConstrainSelectedInstOperands,
119271 // GIR_Coverage, 4526,
119272 GIR_EraseRootFromParent_Done,
119273 // Label 6700: @325442
119274 GIM_Try, /*On fail goto*//*Label 6701*/ GIMT_Encode4(325539), // Rule ID 13088 //
119275 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
119276 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
119277 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
119278 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
119279 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
119280 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119281 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
119282 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
119283 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
119284 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
119285 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119286 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119287 GIM_CheckIsSafeToFold, /*NumInsns*/2,
119288 // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
119289 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
119290 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119291 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119292 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rm
119293 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
119294 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119295 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
119296 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
119297 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
119298 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
119299 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
119300 GIR_RootConstrainSelectedInstOperands,
119301 // GIR_Coverage, 13088,
119302 GIR_EraseRootFromParent_Done,
119303 // Label 6701: @325539
119304 GIM_Try, /*On fail goto*//*Label 6702*/ GIMT_Encode4(325639), // Rule ID 13090 //
119305 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
119306 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
119307 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
119308 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
119309 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119310 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
119311 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119312 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
119313 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
119314 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
119315 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
119316 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119317 GIM_CheckIsSafeToFold, /*NumInsns*/2,
119318 // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
119319 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
119320 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119321 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119322 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
119323 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
119324 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119325 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
119326 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
119327 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
119328 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
119329 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
119330 GIR_RootConstrainSelectedInstOperands,
119331 // GIR_Coverage, 13090,
119332 GIR_EraseRootFromParent_Done,
119333 // Label 6702: @325639
119334 GIM_Try, /*On fail goto*//*Label 6703*/ GIMT_Encode4(325739), // Rule ID 4524 //
119335 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
119336 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119337 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
119338 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119339 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
119340 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
119341 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
119342 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
119343 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
119344 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
119345 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
119346 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119347 GIM_CheckIsSafeToFold, /*NumInsns*/2,
119348 // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra)) => (FNMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
119349 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
119350 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119351 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119352 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rm
119353 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
119354 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119355 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
119356 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
119357 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
119358 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
119359 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
119360 GIR_RootConstrainSelectedInstOperands,
119361 // GIR_Coverage, 4524,
119362 GIR_EraseRootFromParent_Done,
119363 // Label 6703: @325739
119364 GIM_Try, /*On fail goto*//*Label 6704*/ GIMT_Encode4(325836), // Rule ID 4500 //
119365 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
119366 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119367 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
119368 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
119369 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
119370 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
119371 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119372 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
119373 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
119374 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
119375 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
119376 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119377 GIM_CheckIsSafeToFold, /*NumInsns*/2,
119378 // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
119379 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
119380 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119381 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119382 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rm
119383 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
119384 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119385 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
119386 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
119387 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
119388 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
119389 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
119390 GIR_RootConstrainSelectedInstOperands,
119391 // GIR_Coverage, 4500,
119392 GIR_EraseRootFromParent_Done,
119393 // Label 6704: @325836
119394 GIM_Try, /*On fail goto*//*Label 6705*/ GIMT_Encode4(325920), // Rule ID 5716 //
119395 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
119396 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
119397 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119398 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
119399 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
119400 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
119401 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
119402 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
119403 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
119404 // MIs[2] Operand 1
119405 // No operand predicates
119406 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
119407 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
119408 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s16,
119409 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119410 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119411 GIM_CheckIsSafeToFold, /*NumInsns*/3,
119412 // (strict_fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
119413 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
119414 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
119415 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
119416 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
119417 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
119418 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
119419 GIR_RootConstrainSelectedInstOperands,
119420 // GIR_Coverage, 5716,
119421 GIR_EraseRootFromParent_Done,
119422 // Label 6705: @325920
119423 GIM_Try, /*On fail goto*//*Label 6706*/ GIMT_Encode4(326001), // Rule ID 5742 //
119424 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
119425 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
119426 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
119427 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
119428 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
119429 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119430 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
119431 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
119432 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
119433 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
119434 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
119435 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
119436 // MIs[3] Operand 1
119437 // No operand predicates
119438 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119439 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119440 GIM_CheckIsSafeToFold, /*NumInsns*/3,
119441 // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
119442 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
119443 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
119444 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
119445 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
119446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
119447 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
119448 GIR_RootConstrainSelectedInstOperands,
119449 // GIR_Coverage, 5742,
119450 GIR_EraseRootFromParent_Done,
119451 // Label 6706: @326001
119452 GIM_Try, /*On fail goto*//*Label 6707*/ GIMT_Encode4(326085), // Rule ID 5768 //
119453 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
119454 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
119455 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
119456 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
119457 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119458 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
119459 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119460 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
119461 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
119462 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
119463 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
119464 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
119465 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
119466 // MIs[3] Operand 1
119467 // No operand predicates
119468 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119469 GIM_CheckIsSafeToFold, /*NumInsns*/3,
119470 // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
119471 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
119472 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
119473 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
119474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
119475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
119476 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
119477 GIR_RootConstrainSelectedInstOperands,
119478 // GIR_Coverage, 5768,
119479 GIR_EraseRootFromParent_Done,
119480 // Label 6707: @326085
119481 GIM_Try, /*On fail goto*//*Label 6708*/ GIMT_Encode4(326166), // Rule ID 5690 //
119482 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
119483 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119484 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
119485 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
119486 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
119487 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
119488 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119489 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
119490 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
119491 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
119492 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
119493 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
119494 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
119495 // MIs[3] Operand 1
119496 // No operand predicates
119497 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119498 GIM_CheckIsSafeToFold, /*NumInsns*/3,
119499 // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), FPR16:{ *:[f16] }:$Rd) => (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
119500 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
119501 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
119502 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
119503 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
119504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
119505 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
119506 GIR_RootConstrainSelectedInstOperands,
119507 // GIR_Coverage, 5690,
119508 GIR_EraseRootFromParent_Done,
119509 // Label 6708: @326166
119510 GIM_Try, /*On fail goto*//*Label 6709*/ GIMT_Encode4(326251), // Rule ID 2385 //
119511 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
119512 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
119513 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119514 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
119515 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
119516 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
119517 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
119518 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119519 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119520 GIM_CheckIsSafeToFold, /*NumInsns*/1,
119521 // (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) => (FMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
119522 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
119523 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119524 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119525 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rn
119526 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
119527 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119528 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
119529 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
119530 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
119531 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
119532 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
119533 GIR_RootConstrainSelectedInstOperands,
119534 // GIR_Coverage, 2385,
119535 GIR_EraseRootFromParent_Done,
119536 // Label 6709: @326251
119537 GIM_Try, /*On fail goto*//*Label 6710*/ GIMT_Encode4(326336), // Rule ID 2383 //
119538 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
119539 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119540 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
119541 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119542 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
119543 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
119544 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
119545 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
119546 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119547 GIM_CheckIsSafeToFold, /*NumInsns*/1,
119548 // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra) => (FMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
119549 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
119550 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119551 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119552 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(7), // Rm
119553 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
119554 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119555 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
119556 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
119557 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
119558 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
119559 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
119560 GIR_RootConstrainSelectedInstOperands,
119561 // GIR_Coverage, 2383,
119562 GIR_EraseRootFromParent_Done,
119563 // Label 6710: @326336
119564 GIM_Try, /*On fail goto*//*Label 6711*/ GIMT_Encode4(326405), // Rule ID 2451 //
119565 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
119566 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
119567 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119568 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
119569 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
119570 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
119571 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
119572 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
119573 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
119574 // MIs[2] Operand 1
119575 // No operand predicates
119576 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119577 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119578 GIM_CheckIsSafeToFold, /*NumInsns*/2,
119579 // (strict_fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rd) => (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
119580 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
119581 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
119582 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
119583 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
119584 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
119585 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
119586 GIR_RootConstrainSelectedInstOperands,
119587 // GIR_Coverage, 2451,
119588 GIR_EraseRootFromParent_Done,
119589 // Label 6711: @326405
119590 GIM_Try, /*On fail goto*//*Label 6712*/ GIMT_Encode4(326474), // Rule ID 5664 //
119591 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
119592 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119593 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
119594 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119595 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
119596 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
119597 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
119598 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
119599 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
119600 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
119601 // MIs[2] Operand 1
119602 // No operand predicates
119603 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119604 GIM_CheckIsSafeToFold, /*NumInsns*/2,
119605 // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd) => (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
119606 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
119607 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
119608 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
119609 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
119610 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
119611 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
119612 GIR_RootConstrainSelectedInstOperands,
119613 // GIR_Coverage, 5664,
119614 GIR_EraseRootFromParent_Done,
119615 // Label 6712: @326474
119616 GIM_Try, /*On fail goto*//*Label 6713*/ GIMT_Encode4(326524), // Rule ID 12546 //
119617 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
119618 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
119619 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
119620 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
119621 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119622 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119623 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119624 GIM_CheckIsSafeToFold, /*NumInsns*/1,
119625 // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
119626 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
119627 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
119628 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
119629 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
119630 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
119631 GIR_RootConstrainSelectedInstOperands,
119632 // GIR_Coverage, 12546,
119633 GIR_EraseRootFromParent_Done,
119634 // Label 6713: @326524
119635 GIM_Try, /*On fail goto*//*Label 6714*/ GIMT_Encode4(326574), // Rule ID 637 //
119636 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
119637 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119638 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
119639 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
119640 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
119641 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119642 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119643 GIM_CheckIsSafeToFold, /*NumInsns*/1,
119644 // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Ra) => (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
119645 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
119646 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
119647 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
119648 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
119649 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
119650 GIR_RootConstrainSelectedInstOperands,
119651 // GIR_Coverage, 637,
119652 GIR_EraseRootFromParent_Done,
119653 // Label 6714: @326574
119654 GIM_Try, /*On fail goto*//*Label 6715*/ GIMT_Encode4(326624), // Rule ID 649 //
119655 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
119656 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119657 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119658 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
119659 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
119660 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
119661 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119662 GIM_CheckIsSafeToFold, /*NumInsns*/1,
119663 // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra)) => (FNMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
119664 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
119665 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
119666 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
119667 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
119668 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra
119669 GIR_RootConstrainSelectedInstOperands,
119670 // GIR_Coverage, 649,
119671 GIR_EraseRootFromParent_Done,
119672 // Label 6715: @326624
119673 GIM_Try, /*On fail goto*//*Label 6716*/ GIMT_Encode4(326655), // Rule ID 631 //
119674 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
119675 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119676 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119677 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
119678 // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra) => (FMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
119679 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
119680 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
119681 GIR_RootConstrainSelectedInstOperands,
119682 // GIR_Coverage, 631,
119683 GIR_Done,
119684 // Label 6716: @326655
119685 GIM_Reject,
119686 // Label 6698: @326656
119687 GIM_Reject,
119688 // Label 6690: @326657
119689 GIM_Try, /*On fail goto*//*Label 6717*/ GIMT_Encode4(328245),
119690 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
119691 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
119692 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
119693 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119694 GIM_Try, /*On fail goto*//*Label 6718*/ GIMT_Encode4(326775), // Rule ID 4506 //
119695 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
119696 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
119697 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119698 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
119699 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
119700 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
119701 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
119702 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
119703 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
119704 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
119705 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119706 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119707 GIM_CheckIsSafeToFold, /*NumInsns*/2,
119708 // (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
119709 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
119710 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119711 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119712 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rn
119713 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
119714 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119715 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
119716 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
119717 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
119718 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
119719 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
119720 GIR_RootConstrainSelectedInstOperands,
119721 // GIR_Coverage, 4506,
119722 GIR_EraseRootFromParent_Done,
119723 // Label 6718: @326775
119724 GIM_Try, /*On fail goto*//*Label 6719*/ GIMT_Encode4(326875), // Rule ID 4530 //
119725 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
119726 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
119727 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119728 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
119729 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
119730 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
119731 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
119732 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119733 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
119734 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
119735 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
119736 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119737 GIM_CheckIsSafeToFold, /*NumInsns*/2,
119738 // (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
119739 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
119740 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119741 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119742 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rn
119743 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
119744 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119745 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
119746 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
119747 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
119748 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
119749 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
119750 GIR_RootConstrainSelectedInstOperands,
119751 // GIR_Coverage, 4530,
119752 GIR_EraseRootFromParent_Done,
119753 // Label 6719: @326875
119754 GIM_Try, /*On fail goto*//*Label 6720*/ GIMT_Encode4(326972), // Rule ID 13092 //
119755 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
119756 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
119757 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
119758 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
119759 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
119760 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119761 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
119762 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
119763 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
119764 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
119765 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119766 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119767 GIM_CheckIsSafeToFold, /*NumInsns*/2,
119768 // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
119769 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
119770 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119771 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119772 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rm
119773 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
119774 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119775 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
119776 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
119777 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
119778 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
119779 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
119780 GIR_RootConstrainSelectedInstOperands,
119781 // GIR_Coverage, 13092,
119782 GIR_EraseRootFromParent_Done,
119783 // Label 6720: @326972
119784 GIM_Try, /*On fail goto*//*Label 6721*/ GIMT_Encode4(327072), // Rule ID 13094 //
119785 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
119786 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
119787 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
119788 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
119789 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119790 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
119791 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119792 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
119793 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
119794 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
119795 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
119796 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119797 GIM_CheckIsSafeToFold, /*NumInsns*/2,
119798 // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
119799 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
119800 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119801 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119802 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rn
119803 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
119804 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119805 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
119806 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
119807 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
119808 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
119809 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
119810 GIR_RootConstrainSelectedInstOperands,
119811 // GIR_Coverage, 13094,
119812 GIR_EraseRootFromParent_Done,
119813 // Label 6721: @327072
119814 GIM_Try, /*On fail goto*//*Label 6722*/ GIMT_Encode4(327172), // Rule ID 4528 //
119815 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
119816 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119817 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
119818 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119819 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
119820 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
119821 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
119822 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
119823 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
119824 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
119825 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
119826 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119827 GIM_CheckIsSafeToFold, /*NumInsns*/2,
119828 // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
119829 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
119830 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119831 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119832 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rm
119833 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
119834 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119835 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
119836 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
119837 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
119838 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
119839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
119840 GIR_RootConstrainSelectedInstOperands,
119841 // GIR_Coverage, 4528,
119842 GIR_EraseRootFromParent_Done,
119843 // Label 6722: @327172
119844 GIM_Try, /*On fail goto*//*Label 6723*/ GIMT_Encode4(327269), // Rule ID 4504 //
119845 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
119846 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119847 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
119848 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
119849 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
119850 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
119851 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119852 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
119853 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
119854 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
119855 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
119856 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119857 GIM_CheckIsSafeToFold, /*NumInsns*/2,
119858 // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
119859 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
119860 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
119861 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
119862 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rm
119863 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
119864 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
119865 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
119866 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
119867 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
119868 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
119869 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
119870 GIR_RootConstrainSelectedInstOperands,
119871 // GIR_Coverage, 4504,
119872 GIR_EraseRootFromParent_Done,
119873 // Label 6723: @327269
119874 GIM_Try, /*On fail goto*//*Label 6724*/ GIMT_Encode4(327347), // Rule ID 5802 //
119875 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
119876 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119877 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
119878 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
119879 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
119880 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
119881 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
119882 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
119883 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
119884 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
119885 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
119886 // MIs[3] Operand 1
119887 // No operand predicates
119888 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119889 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119890 GIM_CheckIsSafeToFold, /*NumInsns*/3,
119891 // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
119892 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
119893 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
119894 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
119895 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
119896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
119897 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
119898 GIR_RootConstrainSelectedInstOperands,
119899 // GIR_Coverage, 5802,
119900 GIR_EraseRootFromParent_Done,
119901 // Label 6724: @327347
119902 GIM_Try, /*On fail goto*//*Label 6725*/ GIMT_Encode4(327431), // Rule ID 5730 //
119903 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
119904 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
119905 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119906 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
119907 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
119908 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
119909 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
119910 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
119911 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
119912 // MIs[2] Operand 1
119913 // No operand predicates
119914 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
119915 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
119916 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
119917 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119918 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119919 GIM_CheckIsSafeToFold, /*NumInsns*/3,
119920 // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
119921 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
119922 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
119923 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
119924 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
119925 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
119926 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
119927 GIR_RootConstrainSelectedInstOperands,
119928 // GIR_Coverage, 5730,
119929 GIR_EraseRootFromParent_Done,
119930 // Label 6725: @327431
119931 GIM_Try, /*On fail goto*//*Label 6726*/ GIMT_Encode4(327512), // Rule ID 5756 //
119932 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
119933 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
119934 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
119935 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
119936 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
119937 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119938 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
119939 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
119940 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
119941 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
119942 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
119943 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
119944 // MIs[3] Operand 1
119945 // No operand predicates
119946 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119947 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119948 GIM_CheckIsSafeToFold, /*NumInsns*/3,
119949 // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
119950 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
119951 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
119952 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
119953 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
119954 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
119955 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
119956 GIR_RootConstrainSelectedInstOperands,
119957 // GIR_Coverage, 5756,
119958 GIR_EraseRootFromParent_Done,
119959 // Label 6726: @327512
119960 GIM_Try, /*On fail goto*//*Label 6727*/ GIMT_Encode4(327596), // Rule ID 5782 //
119961 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
119962 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
119963 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
119964 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
119965 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119966 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
119967 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119968 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
119969 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
119970 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
119971 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
119972 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
119973 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
119974 // MIs[3] Operand 1
119975 // No operand predicates
119976 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119977 GIM_CheckIsSafeToFold, /*NumInsns*/3,
119978 // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
119979 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
119980 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
119981 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
119982 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
119983 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
119984 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
119985 GIR_RootConstrainSelectedInstOperands,
119986 // GIR_Coverage, 5782,
119987 GIR_EraseRootFromParent_Done,
119988 // Label 6727: @327596
119989 GIM_Try, /*On fail goto*//*Label 6728*/ GIMT_Encode4(327674), // Rule ID 5824 //
119990 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
119991 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
119992 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
119993 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
119994 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
119995 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
119996 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
119997 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
119998 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
119999 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
120000 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120001 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
120002 // MIs[3] Operand 1
120003 // No operand predicates
120004 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120005 GIM_CheckIsSafeToFold, /*NumInsns*/3,
120006 // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
120007 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
120008 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120009 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120010 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
120011 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
120012 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
120013 GIR_RootConstrainSelectedInstOperands,
120014 // GIR_Coverage, 5824,
120015 GIR_EraseRootFromParent_Done,
120016 // Label 6728: @327674
120017 GIM_Try, /*On fail goto*//*Label 6729*/ GIMT_Encode4(327755), // Rule ID 5704 //
120018 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
120019 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120020 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
120021 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
120022 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
120023 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
120024 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120025 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
120026 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
120027 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120028 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
120029 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120030 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
120031 // MIs[3] Operand 1
120032 // No operand predicates
120033 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120034 GIM_CheckIsSafeToFold, /*NumInsns*/3,
120035 // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), FPR32:{ *:[f32] }:$Rd) => (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
120036 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
120037 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120038 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120039 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
120040 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
120041 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
120042 GIR_RootConstrainSelectedInstOperands,
120043 // GIR_Coverage, 5704,
120044 GIR_EraseRootFromParent_Done,
120045 // Label 6729: @327755
120046 GIM_Try, /*On fail goto*//*Label 6730*/ GIMT_Encode4(327840), // Rule ID 2389 //
120047 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
120048 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120049 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120050 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
120051 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
120052 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120053 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
120054 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120055 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120056 GIM_CheckIsSafeToFold, /*NumInsns*/1,
120057 // (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) => (FMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
120058 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
120059 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
120060 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
120061 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rn
120062 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
120063 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
120064 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
120065 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
120066 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
120067 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
120068 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
120069 GIR_RootConstrainSelectedInstOperands,
120070 // GIR_Coverage, 2389,
120071 GIR_EraseRootFromParent_Done,
120072 // Label 6730: @327840
120073 GIM_Try, /*On fail goto*//*Label 6731*/ GIMT_Encode4(327925), // Rule ID 2387 //
120074 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
120075 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120076 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
120077 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120078 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
120079 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
120080 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120081 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
120082 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120083 GIM_CheckIsSafeToFold, /*NumInsns*/1,
120084 // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra) => (FMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
120085 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
120086 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
120087 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
120088 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(15), // Rm
120089 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
120090 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
120091 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
120092 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
120093 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
120094 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
120095 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
120096 GIR_RootConstrainSelectedInstOperands,
120097 // GIR_Coverage, 2387,
120098 GIR_EraseRootFromParent_Done,
120099 // Label 6731: @327925
120100 GIM_Try, /*On fail goto*//*Label 6732*/ GIMT_Encode4(327994), // Rule ID 2465 //
120101 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
120102 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120103 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120104 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
120105 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
120106 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120107 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
120108 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120109 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
120110 // MIs[2] Operand 1
120111 // No operand predicates
120112 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120113 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120114 GIM_CheckIsSafeToFold, /*NumInsns*/2,
120115 // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd) => (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
120116 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
120117 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120118 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120119 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
120120 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
120121 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
120122 GIR_RootConstrainSelectedInstOperands,
120123 // GIR_Coverage, 2465,
120124 GIR_EraseRootFromParent_Done,
120125 // Label 6732: @327994
120126 GIM_Try, /*On fail goto*//*Label 6733*/ GIMT_Encode4(328063), // Rule ID 5678 //
120127 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
120128 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120129 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
120130 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120131 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
120132 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
120133 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120134 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
120135 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120136 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
120137 // MIs[2] Operand 1
120138 // No operand predicates
120139 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120140 GIM_CheckIsSafeToFold, /*NumInsns*/2,
120141 // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd) => (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
120142 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
120143 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120144 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120145 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
120146 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
120147 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
120148 GIR_RootConstrainSelectedInstOperands,
120149 // GIR_Coverage, 5678,
120150 GIR_EraseRootFromParent_Done,
120151 // Label 6733: @328063
120152 GIM_Try, /*On fail goto*//*Label 6734*/ GIMT_Encode4(328113), // Rule ID 12548 //
120153 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
120154 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120155 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
120156 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
120157 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120158 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120159 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120160 GIM_CheckIsSafeToFold, /*NumInsns*/1,
120161 // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
120162 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
120163 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
120164 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
120165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
120166 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
120167 GIR_RootConstrainSelectedInstOperands,
120168 // GIR_Coverage, 12548,
120169 GIR_EraseRootFromParent_Done,
120170 // Label 6734: @328113
120171 GIM_Try, /*On fail goto*//*Label 6735*/ GIMT_Encode4(328163), // Rule ID 639 //
120172 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
120173 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120174 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
120175 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
120176 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
120177 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120178 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120179 GIM_CheckIsSafeToFold, /*NumInsns*/1,
120180 // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Ra) => (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
120181 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
120182 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
120183 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
120184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
120185 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
120186 GIR_RootConstrainSelectedInstOperands,
120187 // GIR_Coverage, 639,
120188 GIR_EraseRootFromParent_Done,
120189 // Label 6735: @328163
120190 GIM_Try, /*On fail goto*//*Label 6736*/ GIMT_Encode4(328213), // Rule ID 651 //
120191 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
120192 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120193 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120194 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
120195 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
120196 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
120197 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120198 GIM_CheckIsSafeToFold, /*NumInsns*/1,
120199 // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra)) => (FNMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
120200 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
120201 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
120202 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
120203 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
120204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra
120205 GIR_RootConstrainSelectedInstOperands,
120206 // GIR_Coverage, 651,
120207 GIR_EraseRootFromParent_Done,
120208 // Label 6736: @328213
120209 GIM_Try, /*On fail goto*//*Label 6737*/ GIMT_Encode4(328244), // Rule ID 633 //
120210 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
120211 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120212 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120213 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120214 // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra) => (FMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
120215 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
120216 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
120217 GIR_RootConstrainSelectedInstOperands,
120218 // GIR_Coverage, 633,
120219 GIR_Done,
120220 // Label 6737: @328244
120221 GIM_Reject,
120222 // Label 6717: @328245
120223 GIM_Reject,
120224 // Label 6691: @328246
120225 GIM_Try, /*On fail goto*//*Label 6738*/ GIMT_Encode4(329834),
120226 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
120227 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
120228 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
120229 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120230 GIM_Try, /*On fail goto*//*Label 6739*/ GIMT_Encode4(328364), // Rule ID 4510 //
120231 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
120232 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120233 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120234 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
120235 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
120236 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120237 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
120238 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
120239 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
120240 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
120241 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120242 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120243 GIM_CheckIsSafeToFold, /*NumInsns*/2,
120244 // (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
120245 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
120246 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
120247 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
120248 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
120249 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
120250 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
120251 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
120252 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
120253 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
120254 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
120255 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
120256 GIR_RootConstrainSelectedInstOperands,
120257 // GIR_Coverage, 4510,
120258 GIR_EraseRootFromParent_Done,
120259 // Label 6739: @328364
120260 GIM_Try, /*On fail goto*//*Label 6740*/ GIMT_Encode4(328464), // Rule ID 4534 //
120261 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
120262 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120263 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120264 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
120265 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
120266 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120267 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
120268 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120269 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
120270 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
120271 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
120272 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120273 GIM_CheckIsSafeToFold, /*NumInsns*/2,
120274 // (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
120275 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
120276 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
120277 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
120278 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
120279 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
120280 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
120281 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
120282 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
120283 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
120284 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
120285 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
120286 GIR_RootConstrainSelectedInstOperands,
120287 // GIR_Coverage, 4534,
120288 GIR_EraseRootFromParent_Done,
120289 // Label 6740: @328464
120290 GIM_Try, /*On fail goto*//*Label 6741*/ GIMT_Encode4(328561), // Rule ID 13096 //
120291 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
120292 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120293 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
120294 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
120295 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
120296 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120297 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
120298 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
120299 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120300 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
120301 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120302 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120303 GIM_CheckIsSafeToFold, /*NumInsns*/2,
120304 // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
120305 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
120306 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
120307 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
120308 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rm
120309 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
120310 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
120311 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
120312 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
120313 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
120314 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
120315 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
120316 GIR_RootConstrainSelectedInstOperands,
120317 // GIR_Coverage, 13096,
120318 GIR_EraseRootFromParent_Done,
120319 // Label 6741: @328561
120320 GIM_Try, /*On fail goto*//*Label 6742*/ GIMT_Encode4(328661), // Rule ID 13098 //
120321 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
120322 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120323 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
120324 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
120325 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120326 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
120327 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120328 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
120329 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
120330 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120331 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
120332 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120333 GIM_CheckIsSafeToFold, /*NumInsns*/2,
120334 // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
120335 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
120336 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
120337 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
120338 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
120339 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
120340 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
120341 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
120342 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
120343 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
120344 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
120345 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
120346 GIR_RootConstrainSelectedInstOperands,
120347 // GIR_Coverage, 13098,
120348 GIR_EraseRootFromParent_Done,
120349 // Label 6742: @328661
120350 GIM_Try, /*On fail goto*//*Label 6743*/ GIMT_Encode4(328761), // Rule ID 4532 //
120351 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
120352 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120353 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
120354 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120355 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
120356 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
120357 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120358 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
120359 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
120360 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
120361 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
120362 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120363 GIM_CheckIsSafeToFold, /*NumInsns*/2,
120364 // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
120365 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
120366 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
120367 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
120368 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rm
120369 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
120370 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
120371 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
120372 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
120373 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
120374 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
120375 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
120376 GIR_RootConstrainSelectedInstOperands,
120377 // GIR_Coverage, 4532,
120378 GIR_EraseRootFromParent_Done,
120379 // Label 6743: @328761
120380 GIM_Try, /*On fail goto*//*Label 6744*/ GIMT_Encode4(328858), // Rule ID 4508 //
120381 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
120382 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120383 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
120384 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
120385 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
120386 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
120387 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120388 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
120389 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
120390 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120391 GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
120392 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120393 GIM_CheckIsSafeToFold, /*NumInsns*/2,
120394 // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
120395 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
120396 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
120397 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
120398 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rm
120399 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
120400 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
120401 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
120402 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
120403 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
120404 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
120405 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
120406 GIR_RootConstrainSelectedInstOperands,
120407 // GIR_Coverage, 4508,
120408 GIR_EraseRootFromParent_Done,
120409 // Label 6744: @328858
120410 GIM_Try, /*On fail goto*//*Label 6745*/ GIMT_Encode4(328936), // Rule ID 5806 //
120411 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120412 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120413 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
120414 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
120415 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
120416 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
120417 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
120418 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120419 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
120420 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120421 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
120422 // MIs[3] Operand 1
120423 // No operand predicates
120424 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120425 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120426 GIM_CheckIsSafeToFold, /*NumInsns*/3,
120427 // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
120428 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
120429 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120430 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120431 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
120432 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
120433 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
120434 GIR_RootConstrainSelectedInstOperands,
120435 // GIR_Coverage, 5806,
120436 GIR_EraseRootFromParent_Done,
120437 // Label 6745: @328936
120438 GIM_Try, /*On fail goto*//*Label 6746*/ GIMT_Encode4(329020), // Rule ID 5732 //
120439 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
120440 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120441 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120442 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
120443 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
120444 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120445 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
120446 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120447 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
120448 // MIs[2] Operand 1
120449 // No operand predicates
120450 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
120451 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
120452 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
120453 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120454 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120455 GIM_CheckIsSafeToFold, /*NumInsns*/3,
120456 // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
120457 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
120458 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120459 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120460 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
120461 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
120462 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
120463 GIR_RootConstrainSelectedInstOperands,
120464 // GIR_Coverage, 5732,
120465 GIR_EraseRootFromParent_Done,
120466 // Label 6746: @329020
120467 GIM_Try, /*On fail goto*//*Label 6747*/ GIMT_Encode4(329101), // Rule ID 5758 //
120468 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
120469 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120470 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
120471 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
120472 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
120473 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120474 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
120475 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
120476 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120477 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
120478 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120479 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
120480 // MIs[3] Operand 1
120481 // No operand predicates
120482 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120483 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120484 GIM_CheckIsSafeToFold, /*NumInsns*/3,
120485 // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
120486 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
120487 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120488 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120489 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
120490 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
120491 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
120492 GIR_RootConstrainSelectedInstOperands,
120493 // GIR_Coverage, 5758,
120494 GIR_EraseRootFromParent_Done,
120495 // Label 6747: @329101
120496 GIM_Try, /*On fail goto*//*Label 6748*/ GIMT_Encode4(329185), // Rule ID 5784 //
120497 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
120498 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120499 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
120500 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
120501 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120502 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
120503 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120504 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
120505 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
120506 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120507 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
120508 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120509 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
120510 // MIs[3] Operand 1
120511 // No operand predicates
120512 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120513 GIM_CheckIsSafeToFold, /*NumInsns*/3,
120514 // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
120515 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
120516 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120517 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120518 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
120519 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
120520 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
120521 GIR_RootConstrainSelectedInstOperands,
120522 // GIR_Coverage, 5784,
120523 GIR_EraseRootFromParent_Done,
120524 // Label 6748: @329185
120525 GIM_Try, /*On fail goto*//*Label 6749*/ GIMT_Encode4(329263), // Rule ID 5828 //
120526 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120527 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
120528 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120529 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
120530 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
120531 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
120532 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
120533 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
120534 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120535 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
120536 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120537 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
120538 // MIs[3] Operand 1
120539 // No operand predicates
120540 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120541 GIM_CheckIsSafeToFold, /*NumInsns*/3,
120542 // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
120543 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
120544 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120545 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120546 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
120547 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
120548 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
120549 GIR_RootConstrainSelectedInstOperands,
120550 // GIR_Coverage, 5828,
120551 GIR_EraseRootFromParent_Done,
120552 // Label 6749: @329263
120553 GIM_Try, /*On fail goto*//*Label 6750*/ GIMT_Encode4(329344), // Rule ID 5706 //
120554 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
120555 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120556 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
120557 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
120558 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
120559 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
120560 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120561 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
120562 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
120563 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120564 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
120565 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120566 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
120567 // MIs[3] Operand 1
120568 // No operand predicates
120569 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120570 GIM_CheckIsSafeToFold, /*NumInsns*/3,
120571 // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), FPR64:{ *:[f64] }:$Rd) => (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
120572 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
120573 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120574 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120575 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
120576 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
120577 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
120578 GIR_RootConstrainSelectedInstOperands,
120579 // GIR_Coverage, 5706,
120580 GIR_EraseRootFromParent_Done,
120581 // Label 6750: @329344
120582 GIM_Try, /*On fail goto*//*Label 6751*/ GIMT_Encode4(329429), // Rule ID 2393 //
120583 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
120584 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120585 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120586 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
120587 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
120588 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120589 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
120590 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120591 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120592 GIM_CheckIsSafeToFold, /*NumInsns*/1,
120593 // (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) => (FMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
120594 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
120595 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
120596 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
120597 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rn
120598 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
120599 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
120600 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
120601 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
120602 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
120603 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
120604 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
120605 GIR_RootConstrainSelectedInstOperands,
120606 // GIR_Coverage, 2393,
120607 GIR_EraseRootFromParent_Done,
120608 // Label 6751: @329429
120609 GIM_Try, /*On fail goto*//*Label 6752*/ GIMT_Encode4(329514), // Rule ID 2391 //
120610 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
120611 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120612 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
120613 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120614 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
120615 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
120616 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120617 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
120618 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120619 GIM_CheckIsSafeToFold, /*NumInsns*/1,
120620 // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra) => (FMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
120621 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
120622 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
120623 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
120624 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // Rm
120625 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
120626 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
120627 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
120628 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
120629 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
120630 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
120631 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
120632 GIR_RootConstrainSelectedInstOperands,
120633 // GIR_Coverage, 2391,
120634 GIR_EraseRootFromParent_Done,
120635 // Label 6752: @329514
120636 GIM_Try, /*On fail goto*//*Label 6753*/ GIMT_Encode4(329583), // Rule ID 2467 //
120637 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
120638 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120639 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120640 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
120641 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
120642 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120643 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
120644 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120645 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
120646 // MIs[2] Operand 1
120647 // No operand predicates
120648 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120649 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120650 GIM_CheckIsSafeToFold, /*NumInsns*/2,
120651 // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd) => (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
120652 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
120653 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120654 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120655 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
120656 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
120657 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
120658 GIR_RootConstrainSelectedInstOperands,
120659 // GIR_Coverage, 2467,
120660 GIR_EraseRootFromParent_Done,
120661 // Label 6753: @329583
120662 GIM_Try, /*On fail goto*//*Label 6754*/ GIMT_Encode4(329652), // Rule ID 5680 //
120663 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
120664 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120665 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
120666 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
120667 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
120668 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
120669 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120670 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
120671 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120672 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
120673 // MIs[2] Operand 1
120674 // No operand predicates
120675 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120676 GIM_CheckIsSafeToFold, /*NumInsns*/2,
120677 // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd) => (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
120678 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
120679 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120680 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120681 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
120682 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
120683 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
120684 GIR_RootConstrainSelectedInstOperands,
120685 // GIR_Coverage, 5680,
120686 GIR_EraseRootFromParent_Done,
120687 // Label 6754: @329652
120688 GIM_Try, /*On fail goto*//*Label 6755*/ GIMT_Encode4(329702), // Rule ID 12550 //
120689 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
120690 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120691 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
120692 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
120693 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120694 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120695 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120696 GIM_CheckIsSafeToFold, /*NumInsns*/1,
120697 // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
120698 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
120699 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
120700 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
120701 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
120702 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
120703 GIR_RootConstrainSelectedInstOperands,
120704 // GIR_Coverage, 12550,
120705 GIR_EraseRootFromParent_Done,
120706 // Label 6755: @329702
120707 GIM_Try, /*On fail goto*//*Label 6756*/ GIMT_Encode4(329752), // Rule ID 641 //
120708 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
120709 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120710 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
120711 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
120712 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
120713 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120714 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120715 GIM_CheckIsSafeToFold, /*NumInsns*/1,
120716 // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Ra) => (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
120717 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
120718 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
120719 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
120720 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
120721 GIR_RootToRootCopy, /*OpIdx*/3, // Ra
120722 GIR_RootConstrainSelectedInstOperands,
120723 // GIR_Coverage, 641,
120724 GIR_EraseRootFromParent_Done,
120725 // Label 6756: @329752
120726 GIM_Try, /*On fail goto*//*Label 6757*/ GIMT_Encode4(329802), // Rule ID 653 //
120727 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
120728 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120729 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120730 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
120731 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
120732 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
120733 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120734 GIM_CheckIsSafeToFold, /*NumInsns*/1,
120735 // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra)) => (FNMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
120736 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
120737 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
120738 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
120739 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
120740 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra
120741 GIR_RootConstrainSelectedInstOperands,
120742 // GIR_Coverage, 653,
120743 GIR_EraseRootFromParent_Done,
120744 // Label 6757: @329802
120745 GIM_Try, /*On fail goto*//*Label 6758*/ GIMT_Encode4(329833), // Rule ID 635 //
120746 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
120747 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120748 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120749 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120750 // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra) => (FMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
120751 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
120752 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
120753 GIR_RootConstrainSelectedInstOperands,
120754 // GIR_Coverage, 635,
120755 GIR_Done,
120756 // Label 6758: @329833
120757 GIM_Reject,
120758 // Label 6738: @329834
120759 GIM_Reject,
120760 // Label 6692: @329835
120761 GIM_Try, /*On fail goto*//*Label 6759*/ GIMT_Encode4(331355),
120762 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
120763 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
120764 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
120765 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120766 GIM_Try, /*On fail goto*//*Label 6760*/ GIMT_Encode4(329931), // Rule ID 5786 //
120767 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120768 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
120769 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
120770 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
120771 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
120772 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
120773 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
120774 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120775 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
120776 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120777 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
120778 // MIs[3] Operand 1
120779 // No operand predicates
120780 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120781 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120782 GIM_CheckIsSafeToFold, /*NumInsns*/3,
120783 // (strict_fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
120784 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
120785 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120786 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120787 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
120788 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
120789 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
120790 GIR_RootConstrainSelectedInstOperands,
120791 // GIR_Coverage, 5786,
120792 GIR_EraseRootFromParent_Done,
120793 // Label 6760: @329931
120794 GIM_Try, /*On fail goto*//*Label 6761*/ GIMT_Encode4(330015), // Rule ID 5718 //
120795 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
120796 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120797 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
120798 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
120799 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
120800 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120801 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
120802 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120803 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
120804 // MIs[2] Operand 1
120805 // No operand predicates
120806 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
120807 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
120808 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s32,
120809 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120810 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120811 GIM_CheckIsSafeToFold, /*NumInsns*/3,
120812 // (strict_fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
120813 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
120814 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120815 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120816 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
120817 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
120818 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
120819 GIR_RootConstrainSelectedInstOperands,
120820 // GIR_Coverage, 5718,
120821 GIR_EraseRootFromParent_Done,
120822 // Label 6761: @330015
120823 GIM_Try, /*On fail goto*//*Label 6762*/ GIMT_Encode4(330096), // Rule ID 5744 //
120824 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
120825 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120826 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
120827 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
120828 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
120829 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
120830 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
120831 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
120832 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120833 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
120834 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120835 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
120836 // MIs[3] Operand 1
120837 // No operand predicates
120838 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120839 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120840 GIM_CheckIsSafeToFold, /*NumInsns*/3,
120841 // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
120842 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
120843 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120844 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120845 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
120846 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
120847 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
120848 GIR_RootConstrainSelectedInstOperands,
120849 // GIR_Coverage, 5744,
120850 GIR_EraseRootFromParent_Done,
120851 // Label 6762: @330096
120852 GIM_Try, /*On fail goto*//*Label 6763*/ GIMT_Encode4(330180), // Rule ID 5770 //
120853 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
120854 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120855 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
120856 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
120857 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120858 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
120859 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
120860 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
120861 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
120862 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120863 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
120864 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120865 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
120866 // MIs[3] Operand 1
120867 // No operand predicates
120868 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120869 GIM_CheckIsSafeToFold, /*NumInsns*/3,
120870 // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
120871 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
120872 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120873 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120874 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
120875 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
120876 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
120877 GIR_RootConstrainSelectedInstOperands,
120878 // GIR_Coverage, 5770,
120879 GIR_EraseRootFromParent_Done,
120880 // Label 6763: @330180
120881 GIM_Try, /*On fail goto*//*Label 6764*/ GIMT_Encode4(330258), // Rule ID 5808 //
120882 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120883 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
120884 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
120885 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
120886 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
120887 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
120888 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
120889 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
120890 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120891 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
120892 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120893 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
120894 // MIs[3] Operand 1
120895 // No operand predicates
120896 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120897 GIM_CheckIsSafeToFold, /*NumInsns*/3,
120898 // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
120899 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
120900 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120901 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120902 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
120903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
120904 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
120905 GIR_RootConstrainSelectedInstOperands,
120906 // GIR_Coverage, 5808,
120907 GIR_EraseRootFromParent_Done,
120908 // Label 6764: @330258
120909 GIM_Try, /*On fail goto*//*Label 6765*/ GIMT_Encode4(330339), // Rule ID 5692 //
120910 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
120911 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120912 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
120913 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
120914 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
120915 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
120916 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
120917 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
120918 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
120919 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120920 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
120921 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120922 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
120923 // MIs[3] Operand 1
120924 // No operand predicates
120925 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120926 GIM_CheckIsSafeToFold, /*NumInsns*/3,
120927 // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
120928 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
120929 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120930 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120931 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
120932 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
120933 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
120934 GIR_RootConstrainSelectedInstOperands,
120935 // GIR_Coverage, 5692,
120936 GIR_EraseRootFromParent_Done,
120937 // Label 6765: @330339
120938 GIM_Try, /*On fail goto*//*Label 6766*/ GIMT_Encode4(330408), // Rule ID 2453 //
120939 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
120940 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120941 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
120942 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
120943 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
120944 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120945 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
120946 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120947 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
120948 // MIs[2] Operand 1
120949 // No operand predicates
120950 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120951 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120952 GIM_CheckIsSafeToFold, /*NumInsns*/2,
120953 // (strict_fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
120954 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
120955 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120956 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120957 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
120958 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
120959 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
120960 GIR_RootConstrainSelectedInstOperands,
120961 // GIR_Coverage, 2453,
120962 GIR_EraseRootFromParent_Done,
120963 // Label 6766: @330408
120964 GIM_Try, /*On fail goto*//*Label 6767*/ GIMT_Encode4(330477), // Rule ID 5666 //
120965 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
120966 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120967 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
120968 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
120969 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
120970 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
120971 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
120972 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
120973 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
120974 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
120975 // MIs[2] Operand 1
120976 // No operand predicates
120977 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120978 GIM_CheckIsSafeToFold, /*NumInsns*/2,
120979 // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
120980 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
120981 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
120982 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
120983 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
120984 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
120985 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
120986 GIR_RootConstrainSelectedInstOperands,
120987 // GIR_Coverage, 5666,
120988 GIR_EraseRootFromParent_Done,
120989 // Label 6767: @330477
120990 GIM_Try, /*On fail goto*//*Label 6768*/ GIMT_Encode4(330570), // Rule ID 5790 //
120991 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
120992 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
120993 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
120994 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
120995 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
120996 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
120997 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
120998 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
120999 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121000 GIM_CheckIsSafeToFold, /*NumInsns*/2,
121001 // (strict_fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
121002 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
121003 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
121004 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
121005 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
121006 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
121007 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
121008 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
121009 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
121010 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
121011 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121012 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121013 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
121014 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
121015 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
121016 GIR_RootConstrainSelectedInstOperands,
121017 // GIR_Coverage, 5790,
121018 GIR_EraseRootFromParent_Done,
121019 // Label 6768: @330570
121020 GIM_Try, /*On fail goto*//*Label 6769*/ GIMT_Encode4(330669), // Rule ID 5720 //
121021 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121022 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121023 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
121024 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
121025 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
121026 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
121027 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
121028 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
121029 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121030 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121031 GIM_CheckIsSafeToFold, /*NumInsns*/2,
121032 // (strict_fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
121033 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
121034 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
121035 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
121036 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
121037 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
121038 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
121039 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
121040 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
121041 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
121042 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121043 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
121045 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
121046 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
121047 GIR_RootConstrainSelectedInstOperands,
121048 // GIR_Coverage, 5720,
121049 GIR_EraseRootFromParent_Done,
121050 // Label 6769: @330669
121051 GIM_Try, /*On fail goto*//*Label 6770*/ GIMT_Encode4(330765), // Rule ID 5746 //
121052 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121053 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121054 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
121055 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
121056 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
121057 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
121058 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
121059 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
121060 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121061 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121062 GIM_CheckIsSafeToFold, /*NumInsns*/2,
121063 // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
121064 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
121065 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
121066 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
121067 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
121068 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
121069 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
121070 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
121071 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
121072 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
121073 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121074 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121075 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
121076 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
121077 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
121078 GIR_RootConstrainSelectedInstOperands,
121079 // GIR_Coverage, 5746,
121080 GIR_EraseRootFromParent_Done,
121081 // Label 6770: @330765
121082 GIM_Try, /*On fail goto*//*Label 6771*/ GIMT_Encode4(330864), // Rule ID 5772 //
121083 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121084 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121085 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
121086 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
121087 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121088 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
121089 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
121090 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
121091 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
121092 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121093 GIM_CheckIsSafeToFold, /*NumInsns*/2,
121094 // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
121095 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
121096 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
121097 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
121098 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
121099 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
121100 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
121101 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
121102 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
121103 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
121104 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121105 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121106 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
121107 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
121108 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
121109 GIR_RootConstrainSelectedInstOperands,
121110 // GIR_Coverage, 5772,
121111 GIR_EraseRootFromParent_Done,
121112 // Label 6771: @330864
121113 GIM_Try, /*On fail goto*//*Label 6772*/ GIMT_Encode4(330957), // Rule ID 5812 //
121114 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121115 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
121116 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
121117 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
121118 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
121119 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
121120 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
121121 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
121122 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121123 GIM_CheckIsSafeToFold, /*NumInsns*/2,
121124 // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
121125 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
121126 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
121127 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
121128 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
121129 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
121130 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
121131 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
121132 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
121133 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
121134 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121135 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121136 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
121137 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
121138 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
121139 GIR_RootConstrainSelectedInstOperands,
121140 // GIR_Coverage, 5812,
121141 GIR_EraseRootFromParent_Done,
121142 // Label 6772: @330957
121143 GIM_Try, /*On fail goto*//*Label 6773*/ GIMT_Encode4(331053), // Rule ID 5694 //
121144 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121145 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121146 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
121147 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
121148 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
121149 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
121150 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
121151 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
121152 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
121153 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121154 GIM_CheckIsSafeToFold, /*NumInsns*/2,
121155 // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rd) => (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
121156 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
121157 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
121158 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
121159 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
121160 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
121161 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
121162 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
121163 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
121164 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
121165 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121166 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121167 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
121168 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
121169 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
121170 GIR_RootConstrainSelectedInstOperands,
121171 // GIR_Coverage, 5694,
121172 GIR_EraseRootFromParent_Done,
121173 // Label 6773: @331053
121174 GIM_Try, /*On fail goto*//*Label 6774*/ GIMT_Encode4(331137), // Rule ID 2455 //
121175 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121176 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121177 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
121178 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
121179 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
121180 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121181 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121182 GIM_CheckIsSafeToFold, /*NumInsns*/1,
121183 // (strict_fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
121184 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
121185 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
121186 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
121187 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
121188 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
121189 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
121190 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
121191 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
121192 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
121193 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121194 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121195 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
121196 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
121197 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
121198 GIR_RootConstrainSelectedInstOperands,
121199 // GIR_Coverage, 2455,
121200 GIR_EraseRootFromParent_Done,
121201 // Label 6774: @331137
121202 GIM_Try, /*On fail goto*//*Label 6775*/ GIMT_Encode4(331187), // Rule ID 12580 //
121203 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121204 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121205 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
121206 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
121207 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121208 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121209 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121210 GIM_CheckIsSafeToFold, /*NumInsns*/1,
121211 // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
121212 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f32),
121213 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121214 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121215 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
121216 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
121217 GIR_RootConstrainSelectedInstOperands,
121218 // GIR_Coverage, 12580,
121219 GIR_EraseRootFromParent_Done,
121220 // Label 6775: @331187
121221 GIM_Try, /*On fail goto*//*Label 6776*/ GIMT_Encode4(331271), // Rule ID 5668 //
121222 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121223 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121224 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
121225 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
121226 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
121227 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
121228 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121229 GIM_CheckIsSafeToFold, /*NumInsns*/1,
121230 // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rd) => (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
121231 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
121232 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
121233 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
121234 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
121235 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
121236 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
121237 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
121238 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
121239 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
121240 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121241 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121242 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
121243 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
121244 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
121245 GIR_RootConstrainSelectedInstOperands,
121246 // GIR_Coverage, 5668,
121247 GIR_EraseRootFromParent_Done,
121248 // Label 6776: @331271
121249 GIM_Try, /*On fail goto*//*Label 6777*/ GIMT_Encode4(331321), // Rule ID 1294 //
121250 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121251 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121252 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
121253 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
121254 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
121255 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121256 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121257 GIM_CheckIsSafeToFold, /*NumInsns*/1,
121258 // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rd) => (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
121259 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f32),
121260 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121261 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121262 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
121263 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
121264 GIR_RootConstrainSelectedInstOperands,
121265 // GIR_Coverage, 1294,
121266 GIR_EraseRootFromParent_Done,
121267 // Label 6777: @331321
121268 GIM_Try, /*On fail goto*//*Label 6778*/ GIMT_Encode4(331354), // Rule ID 1284 //
121269 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121270 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121271 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121272 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121273 // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd) => (FMLAv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
121274 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2f32),
121275 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121276 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121277 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
121278 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
121279 GIR_RootConstrainSelectedInstOperands,
121280 // GIR_Coverage, 1284,
121281 GIR_EraseRootFromParent_Done,
121282 // Label 6778: @331354
121283 GIM_Reject,
121284 // Label 6759: @331355
121285 GIM_Reject,
121286 // Label 6693: @331356
121287 GIM_Try, /*On fail goto*//*Label 6779*/ GIMT_Encode4(332876),
121288 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
121289 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
121290 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
121291 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121292 GIM_Try, /*On fail goto*//*Label 6780*/ GIMT_Encode4(331452), // Rule ID 5798 //
121293 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121294 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
121295 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
121296 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
121297 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
121298 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
121299 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
121300 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121301 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
121302 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
121303 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
121304 // MIs[3] Operand 1
121305 // No operand predicates
121306 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121307 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121308 GIM_CheckIsSafeToFold, /*NumInsns*/3,
121309 // (strict_fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
121310 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
121311 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121312 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121313 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
121314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
121315 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
121316 GIR_RootConstrainSelectedInstOperands,
121317 // GIR_Coverage, 5798,
121318 GIR_EraseRootFromParent_Done,
121319 // Label 6780: @331452
121320 GIM_Try, /*On fail goto*//*Label 6781*/ GIMT_Encode4(331536), // Rule ID 5726 //
121321 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121322 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121323 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
121324 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
121325 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
121326 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121327 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
121328 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
121329 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
121330 // MIs[2] Operand 1
121331 // No operand predicates
121332 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
121333 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
121334 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
121335 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121336 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121337 GIM_CheckIsSafeToFold, /*NumInsns*/3,
121338 // (strict_fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
121339 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
121340 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121341 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121342 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
121343 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
121344 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
121345 GIR_RootConstrainSelectedInstOperands,
121346 // GIR_Coverage, 5726,
121347 GIR_EraseRootFromParent_Done,
121348 // Label 6781: @331536
121349 GIM_Try, /*On fail goto*//*Label 6782*/ GIMT_Encode4(331617), // Rule ID 5752 //
121350 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121351 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121352 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
121353 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
121354 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
121355 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
121356 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
121357 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
121358 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121359 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
121360 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
121361 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
121362 // MIs[3] Operand 1
121363 // No operand predicates
121364 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121365 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121366 GIM_CheckIsSafeToFold, /*NumInsns*/3,
121367 // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
121368 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
121369 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121370 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121371 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
121372 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
121373 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
121374 GIR_RootConstrainSelectedInstOperands,
121375 // GIR_Coverage, 5752,
121376 GIR_EraseRootFromParent_Done,
121377 // Label 6782: @331617
121378 GIM_Try, /*On fail goto*//*Label 6783*/ GIMT_Encode4(331701), // Rule ID 5778 //
121379 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121380 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121381 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
121382 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
121383 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121384 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
121385 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
121386 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
121387 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
121388 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121389 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
121390 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
121391 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
121392 // MIs[3] Operand 1
121393 // No operand predicates
121394 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121395 GIM_CheckIsSafeToFold, /*NumInsns*/3,
121396 // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
121397 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
121398 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121399 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121400 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
121401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
121402 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
121403 GIR_RootConstrainSelectedInstOperands,
121404 // GIR_Coverage, 5778,
121405 GIR_EraseRootFromParent_Done,
121406 // Label 6783: @331701
121407 GIM_Try, /*On fail goto*//*Label 6784*/ GIMT_Encode4(331779), // Rule ID 5820 //
121408 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121409 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
121410 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
121411 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
121412 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
121413 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
121414 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
121415 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
121416 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121417 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
121418 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
121419 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
121420 // MIs[3] Operand 1
121421 // No operand predicates
121422 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121423 GIM_CheckIsSafeToFold, /*NumInsns*/3,
121424 // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
121425 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
121426 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121427 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121428 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
121429 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
121430 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
121431 GIR_RootConstrainSelectedInstOperands,
121432 // GIR_Coverage, 5820,
121433 GIR_EraseRootFromParent_Done,
121434 // Label 6784: @331779
121435 GIM_Try, /*On fail goto*//*Label 6785*/ GIMT_Encode4(331860), // Rule ID 5700 //
121436 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121437 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121438 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
121439 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
121440 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
121441 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
121442 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
121443 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
121444 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
121445 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121446 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
121447 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
121448 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
121449 // MIs[3] Operand 1
121450 // No operand predicates
121451 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121452 GIM_CheckIsSafeToFold, /*NumInsns*/3,
121453 // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
121454 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
121455 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121456 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121457 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
121458 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
121459 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
121460 GIR_RootConstrainSelectedInstOperands,
121461 // GIR_Coverage, 5700,
121462 GIR_EraseRootFromParent_Done,
121463 // Label 6785: @331860
121464 GIM_Try, /*On fail goto*//*Label 6786*/ GIMT_Encode4(331929), // Rule ID 2461 //
121465 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121466 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121467 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
121468 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
121469 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
121470 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121471 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
121472 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
121473 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
121474 // MIs[2] Operand 1
121475 // No operand predicates
121476 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121477 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121478 GIM_CheckIsSafeToFold, /*NumInsns*/2,
121479 // (strict_fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
121480 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
121481 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121482 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121483 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
121484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
121485 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
121486 GIR_RootConstrainSelectedInstOperands,
121487 // GIR_Coverage, 2461,
121488 GIR_EraseRootFromParent_Done,
121489 // Label 6786: @331929
121490 GIM_Try, /*On fail goto*//*Label 6787*/ GIMT_Encode4(331998), // Rule ID 5674 //
121491 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121492 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121493 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
121494 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
121495 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
121496 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
121497 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121498 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
121499 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
121500 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
121501 // MIs[2] Operand 1
121502 // No operand predicates
121503 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121504 GIM_CheckIsSafeToFold, /*NumInsns*/2,
121505 // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
121506 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
121507 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121508 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121509 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
121510 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
121511 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
121512 GIR_RootConstrainSelectedInstOperands,
121513 // GIR_Coverage, 5674,
121514 GIR_EraseRootFromParent_Done,
121515 // Label 6787: @331998
121516 GIM_Try, /*On fail goto*//*Label 6788*/ GIMT_Encode4(332091), // Rule ID 5800 //
121517 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121518 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
121519 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
121520 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
121521 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
121522 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
121523 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121524 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121525 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121526 GIM_CheckIsSafeToFold, /*NumInsns*/2,
121527 // (strict_fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } (fneg:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
121528 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
121529 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
121530 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
121531 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
121532 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
121533 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
121534 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
121535 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
121536 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
121537 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121538 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121539 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
121540 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
121541 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
121542 GIR_RootConstrainSelectedInstOperands,
121543 // GIR_Coverage, 5800,
121544 GIR_EraseRootFromParent_Done,
121545 // Label 6788: @332091
121546 GIM_Try, /*On fail goto*//*Label 6789*/ GIMT_Encode4(332190), // Rule ID 5728 //
121547 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121548 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121549 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
121550 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
121551 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121552 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
121553 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
121554 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
121555 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121556 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121557 GIM_CheckIsSafeToFold, /*NumInsns*/2,
121558 // (strict_fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
121559 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
121560 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
121561 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
121562 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
121563 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
121564 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
121565 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
121566 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
121567 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
121568 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121569 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121570 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
121571 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
121572 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
121573 GIR_RootConstrainSelectedInstOperands,
121574 // GIR_Coverage, 5728,
121575 GIR_EraseRootFromParent_Done,
121576 // Label 6789: @332190
121577 GIM_Try, /*On fail goto*//*Label 6790*/ GIMT_Encode4(332286), // Rule ID 5754 //
121578 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121579 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121580 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
121581 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
121582 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
121583 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
121584 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
121585 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121586 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121587 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121588 GIM_CheckIsSafeToFold, /*NumInsns*/2,
121589 // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
121590 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
121591 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
121592 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
121593 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
121594 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
121595 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
121596 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
121597 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
121598 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
121599 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121600 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121601 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
121602 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
121603 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
121604 GIR_RootConstrainSelectedInstOperands,
121605 // GIR_Coverage, 5754,
121606 GIR_EraseRootFromParent_Done,
121607 // Label 6790: @332286
121608 GIM_Try, /*On fail goto*//*Label 6791*/ GIMT_Encode4(332385), // Rule ID 5780 //
121609 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121610 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121611 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
121612 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
121613 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121614 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
121615 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
121616 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
121617 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121618 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121619 GIM_CheckIsSafeToFold, /*NumInsns*/2,
121620 // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
121621 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
121622 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
121623 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
121624 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
121625 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
121626 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
121627 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
121628 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
121629 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
121630 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121631 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121632 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
121633 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
121634 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
121635 GIR_RootConstrainSelectedInstOperands,
121636 // GIR_Coverage, 5780,
121637 GIR_EraseRootFromParent_Done,
121638 // Label 6791: @332385
121639 GIM_Try, /*On fail goto*//*Label 6792*/ GIMT_Encode4(332478), // Rule ID 5822 //
121640 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121641 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
121642 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
121643 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
121644 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
121645 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
121646 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
121647 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121648 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121649 GIM_CheckIsSafeToFold, /*NumInsns*/2,
121650 // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } (fneg:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
121651 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
121652 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
121653 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
121654 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
121655 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
121656 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
121657 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
121658 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
121659 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
121660 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121661 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121662 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
121663 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
121664 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
121665 GIR_RootConstrainSelectedInstOperands,
121666 // GIR_Coverage, 5822,
121667 GIR_EraseRootFromParent_Done,
121668 // Label 6792: @332478
121669 GIM_Try, /*On fail goto*//*Label 6793*/ GIMT_Encode4(332574), // Rule ID 5702 //
121670 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121671 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121672 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
121673 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
121674 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
121675 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
121676 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
121677 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
121678 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121679 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121680 GIM_CheckIsSafeToFold, /*NumInsns*/2,
121681 // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rd) => (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
121682 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
121683 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
121684 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
121685 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
121686 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
121687 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
121688 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
121689 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
121690 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
121691 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121692 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121693 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
121694 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
121695 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
121696 GIR_RootConstrainSelectedInstOperands,
121697 // GIR_Coverage, 5702,
121698 GIR_EraseRootFromParent_Done,
121699 // Label 6793: @332574
121700 GIM_Try, /*On fail goto*//*Label 6794*/ GIMT_Encode4(332658), // Rule ID 2463 //
121701 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121702 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121703 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
121704 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
121705 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121706 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121707 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121708 GIM_CheckIsSafeToFold, /*NumInsns*/1,
121709 // (strict_fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
121710 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
121711 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
121712 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
121713 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
121714 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
121715 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
121716 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
121717 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
121718 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
121719 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121720 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121721 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
121722 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
121723 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
121724 GIR_RootConstrainSelectedInstOperands,
121725 // GIR_Coverage, 2463,
121726 GIR_EraseRootFromParent_Done,
121727 // Label 6794: @332658
121728 GIM_Try, /*On fail goto*//*Label 6795*/ GIMT_Encode4(332708), // Rule ID 12584 //
121729 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121730 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121731 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
121732 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
121733 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121734 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121735 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121736 GIM_CheckIsSafeToFold, /*NumInsns*/1,
121737 // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
121738 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f64),
121739 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121740 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121741 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
121742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
121743 GIR_RootConstrainSelectedInstOperands,
121744 // GIR_Coverage, 12584,
121745 GIR_EraseRootFromParent_Done,
121746 // Label 6795: @332708
121747 GIM_Try, /*On fail goto*//*Label 6796*/ GIMT_Encode4(332792), // Rule ID 5676 //
121748 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121749 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121750 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
121751 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
121752 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
121753 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121754 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121755 GIM_CheckIsSafeToFold, /*NumInsns*/1,
121756 // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rd) => (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
121757 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
121758 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
121759 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
121760 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
121761 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
121762 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
121763 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
121764 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
121765 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
121766 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121767 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121768 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
121769 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
121770 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
121771 GIR_RootConstrainSelectedInstOperands,
121772 // GIR_Coverage, 5676,
121773 GIR_EraseRootFromParent_Done,
121774 // Label 6796: @332792
121775 GIM_Try, /*On fail goto*//*Label 6797*/ GIMT_Encode4(332842), // Rule ID 1298 //
121776 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121777 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121778 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
121779 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
121780 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
121781 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121782 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121783 GIM_CheckIsSafeToFold, /*NumInsns*/1,
121784 // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rd) => (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
121785 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f64),
121786 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121787 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121788 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
121789 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
121790 GIR_RootConstrainSelectedInstOperands,
121791 // GIR_Coverage, 1298,
121792 GIR_EraseRootFromParent_Done,
121793 // Label 6797: @332842
121794 GIM_Try, /*On fail goto*//*Label 6798*/ GIMT_Encode4(332875), // Rule ID 1288 //
121795 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
121796 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121797 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121798 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
121799 // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd) => (FMLAv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
121800 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2f64),
121801 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121802 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121803 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
121804 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
121805 GIR_RootConstrainSelectedInstOperands,
121806 // GIR_Coverage, 1288,
121807 GIR_EraseRootFromParent_Done,
121808 // Label 6798: @332875
121809 GIM_Reject,
121810 // Label 6779: @332876
121811 GIM_Reject,
121812 // Label 6694: @332877
121813 GIM_Try, /*On fail goto*//*Label 6799*/ GIMT_Encode4(334055),
121814 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
121815 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
121816 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
121817 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121818 GIM_Try, /*On fail goto*//*Label 6800*/ GIMT_Encode4(332979), // Rule ID 5712 //
121819 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
121820 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121821 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
121822 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
121823 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
121824 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
121825 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
121826 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
121827 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
121828 // MIs[2] Operand 1
121829 // No operand predicates
121830 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
121831 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
121832 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16,
121833 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121834 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121835 GIM_CheckIsSafeToFold, /*NumInsns*/3,
121836 // (strict_fma:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
121837 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
121838 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121839 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121840 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
121841 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
121842 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
121843 GIR_RootConstrainSelectedInstOperands,
121844 // GIR_Coverage, 5712,
121845 GIR_EraseRootFromParent_Done,
121846 // Label 6800: @332979
121847 GIM_Try, /*On fail goto*//*Label 6801*/ GIMT_Encode4(333060), // Rule ID 5738 //
121848 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
121849 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121850 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
121851 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
121852 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
121853 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
121854 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
121855 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
121856 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
121857 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
121858 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
121859 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
121860 // MIs[3] Operand 1
121861 // No operand predicates
121862 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121863 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121864 GIM_CheckIsSafeToFold, /*NumInsns*/3,
121865 // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
121866 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
121867 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121868 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121869 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
121870 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
121871 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
121872 GIR_RootConstrainSelectedInstOperands,
121873 // GIR_Coverage, 5738,
121874 GIR_EraseRootFromParent_Done,
121875 // Label 6801: @333060
121876 GIM_Try, /*On fail goto*//*Label 6802*/ GIMT_Encode4(333144), // Rule ID 5764 //
121877 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
121878 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121879 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
121880 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
121881 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121882 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
121883 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
121884 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
121885 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
121886 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
121887 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
121888 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
121889 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
121890 // MIs[3] Operand 1
121891 // No operand predicates
121892 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121893 GIM_CheckIsSafeToFold, /*NumInsns*/3,
121894 // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
121895 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
121896 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121897 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121898 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
121899 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
121900 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
121901 GIR_RootConstrainSelectedInstOperands,
121902 // GIR_Coverage, 5764,
121903 GIR_EraseRootFromParent_Done,
121904 // Label 6802: @333144
121905 GIM_Try, /*On fail goto*//*Label 6803*/ GIMT_Encode4(333225), // Rule ID 5686 //
121906 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
121907 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121908 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
121909 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
121910 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
121911 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
121912 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
121913 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
121914 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
121915 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
121916 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
121917 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
121918 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
121919 // MIs[3] Operand 1
121920 // No operand predicates
121921 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121922 GIM_CheckIsSafeToFold, /*NumInsns*/3,
121923 // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
121924 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
121925 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121926 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121927 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
121928 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
121929 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
121930 GIR_RootConstrainSelectedInstOperands,
121931 // GIR_Coverage, 5686,
121932 GIR_EraseRootFromParent_Done,
121933 // Label 6803: @333225
121934 GIM_Try, /*On fail goto*//*Label 6804*/ GIMT_Encode4(333294), // Rule ID 2447 //
121935 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
121936 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121937 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
121938 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
121939 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
121940 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
121941 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
121942 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
121943 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
121944 // MIs[2] Operand 1
121945 // No operand predicates
121946 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121947 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121948 GIM_CheckIsSafeToFold, /*NumInsns*/2,
121949 // (strict_fma:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
121950 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
121951 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121952 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121953 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
121954 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
121955 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
121956 GIR_RootConstrainSelectedInstOperands,
121957 // GIR_Coverage, 2447,
121958 GIR_EraseRootFromParent_Done,
121959 // Label 6804: @333294
121960 GIM_Try, /*On fail goto*//*Label 6805*/ GIMT_Encode4(333363), // Rule ID 5660 //
121961 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
121962 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121963 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
121964 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
121965 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
121966 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
121967 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
121968 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
121969 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
121970 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
121971 // MIs[2] Operand 1
121972 // No operand predicates
121973 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121974 GIM_CheckIsSafeToFold, /*NumInsns*/2,
121975 // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
121976 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
121977 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
121978 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
121979 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
121980 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
121981 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
121982 GIR_RootConstrainSelectedInstOperands,
121983 // GIR_Coverage, 5660,
121984 GIR_EraseRootFromParent_Done,
121985 // Label 6805: @333363
121986 GIM_Try, /*On fail goto*//*Label 6806*/ GIMT_Encode4(333462), // Rule ID 5714 //
121987 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
121988 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
121989 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
121990 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
121991 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
121992 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
121993 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
121994 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
121995 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121996 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
121997 GIM_CheckIsSafeToFold, /*NumInsns*/2,
121998 // (strict_fma:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
121999 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
122000 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
122001 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
122002 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
122003 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
122004 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
122005 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
122006 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
122007 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
122008 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122009 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
122011 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
122012 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
122013 GIR_RootConstrainSelectedInstOperands,
122014 // GIR_Coverage, 5714,
122015 GIR_EraseRootFromParent_Done,
122016 // Label 6806: @333462
122017 GIM_Try, /*On fail goto*//*Label 6807*/ GIMT_Encode4(333558), // Rule ID 5740 //
122018 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
122019 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122020 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
122021 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
122022 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
122023 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
122024 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
122025 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
122026 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
122027 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
122028 GIM_CheckIsSafeToFold, /*NumInsns*/2,
122029 // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
122030 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
122031 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
122032 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
122033 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
122034 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
122035 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
122036 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
122037 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
122038 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
122039 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122040 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122041 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
122042 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
122043 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
122044 GIR_RootConstrainSelectedInstOperands,
122045 // GIR_Coverage, 5740,
122046 GIR_EraseRootFromParent_Done,
122047 // Label 6807: @333558
122048 GIM_Try, /*On fail goto*//*Label 6808*/ GIMT_Encode4(333657), // Rule ID 5766 //
122049 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
122050 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122051 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
122052 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
122053 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
122054 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
122055 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
122056 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
122057 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
122058 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
122059 GIM_CheckIsSafeToFold, /*NumInsns*/2,
122060 // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
122061 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
122062 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
122063 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
122064 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
122065 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
122066 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
122067 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
122068 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
122069 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
122070 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122071 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122072 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
122073 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
122074 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
122075 GIR_RootConstrainSelectedInstOperands,
122076 // GIR_Coverage, 5766,
122077 GIR_EraseRootFromParent_Done,
122078 // Label 6808: @333657
122079 GIM_Try, /*On fail goto*//*Label 6809*/ GIMT_Encode4(333753), // Rule ID 5688 //
122080 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
122081 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
122082 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
122083 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
122084 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
122085 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
122086 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
122087 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
122088 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
122089 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
122090 GIM_CheckIsSafeToFold, /*NumInsns*/2,
122091 // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V64:{ *:[v4f16] }:$Rd) => (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
122092 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
122093 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
122094 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
122095 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
122096 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
122097 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
122098 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
122099 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
122100 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
122101 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122102 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122103 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
122104 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
122105 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
122106 GIR_RootConstrainSelectedInstOperands,
122107 // GIR_Coverage, 5688,
122108 GIR_EraseRootFromParent_Done,
122109 // Label 6809: @333753
122110 GIM_Try, /*On fail goto*//*Label 6810*/ GIMT_Encode4(333837), // Rule ID 2449 //
122111 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
122112 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122113 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
122114 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
122115 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
122116 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
122117 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
122118 GIM_CheckIsSafeToFold, /*NumInsns*/1,
122119 // (strict_fma:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
122120 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
122121 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
122122 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
122123 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
122124 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
122125 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
122126 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
122127 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
122128 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
122129 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122130 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122131 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
122132 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
122133 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
122134 GIR_RootConstrainSelectedInstOperands,
122135 // GIR_Coverage, 2449,
122136 GIR_EraseRootFromParent_Done,
122137 // Label 6810: @333837
122138 GIM_Try, /*On fail goto*//*Label 6811*/ GIMT_Encode4(333887), // Rule ID 12576 //
122139 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
122140 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122141 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
122142 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
122143 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
122144 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
122145 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
122146 GIM_CheckIsSafeToFold, /*NumInsns*/1,
122147 // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
122148 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f16),
122149 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122150 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122151 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
122152 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
122153 GIR_RootConstrainSelectedInstOperands,
122154 // GIR_Coverage, 12576,
122155 GIR_EraseRootFromParent_Done,
122156 // Label 6811: @333887
122157 GIM_Try, /*On fail goto*//*Label 6812*/ GIMT_Encode4(333971), // Rule ID 5662 //
122158 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
122159 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
122160 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
122161 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
122162 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
122163 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
122164 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
122165 GIM_CheckIsSafeToFold, /*NumInsns*/1,
122166 // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rd) => (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
122167 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
122168 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
122169 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
122170 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
122171 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
122172 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
122173 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
122174 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
122175 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
122176 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122177 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122178 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
122179 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
122180 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
122181 GIR_RootConstrainSelectedInstOperands,
122182 // GIR_Coverage, 5662,
122183 GIR_EraseRootFromParent_Done,
122184 // Label 6812: @333971
122185 GIM_Try, /*On fail goto*//*Label 6813*/ GIMT_Encode4(334021), // Rule ID 1290 //
122186 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
122187 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
122188 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
122189 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
122190 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
122191 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
122192 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
122193 GIM_CheckIsSafeToFold, /*NumInsns*/1,
122194 // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rd) => (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
122195 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f16),
122196 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122197 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122198 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
122199 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
122200 GIR_RootConstrainSelectedInstOperands,
122201 // GIR_Coverage, 1290,
122202 GIR_EraseRootFromParent_Done,
122203 // Label 6813: @334021
122204 GIM_Try, /*On fail goto*//*Label 6814*/ GIMT_Encode4(334054), // Rule ID 1280 //
122205 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
122206 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
122207 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
122208 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
122209 // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd) => (FMLAv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
122210 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4f16),
122211 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122212 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122213 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
122214 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
122215 GIR_RootConstrainSelectedInstOperands,
122216 // GIR_Coverage, 1280,
122217 GIR_EraseRootFromParent_Done,
122218 // Label 6814: @334054
122219 GIM_Reject,
122220 // Label 6799: @334055
122221 GIM_Reject,
122222 // Label 6695: @334056
122223 GIM_Try, /*On fail goto*//*Label 6815*/ GIMT_Encode4(335576),
122224 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
122225 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
122226 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
122227 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122228 GIM_Try, /*On fail goto*//*Label 6816*/ GIMT_Encode4(334152), // Rule ID 5792 //
122229 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122230 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
122231 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
122232 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
122233 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
122234 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
122235 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
122236 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122237 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
122238 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
122239 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
122240 // MIs[3] Operand 1
122241 // No operand predicates
122242 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122243 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122244 GIM_CheckIsSafeToFold, /*NumInsns*/3,
122245 // (strict_fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
122246 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
122247 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122248 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122249 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
122250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
122251 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
122252 GIR_RootConstrainSelectedInstOperands,
122253 // GIR_Coverage, 5792,
122254 GIR_EraseRootFromParent_Done,
122255 // Label 6816: @334152
122256 GIM_Try, /*On fail goto*//*Label 6817*/ GIMT_Encode4(334236), // Rule ID 5722 //
122257 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
122258 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122259 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
122260 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
122261 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
122262 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122263 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
122264 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
122265 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
122266 // MIs[2] Operand 1
122267 // No operand predicates
122268 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
122269 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
122270 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
122271 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122272 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122273 GIM_CheckIsSafeToFold, /*NumInsns*/3,
122274 // (strict_fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
122275 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
122276 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122277 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122278 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
122279 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
122280 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
122281 GIR_RootConstrainSelectedInstOperands,
122282 // GIR_Coverage, 5722,
122283 GIR_EraseRootFromParent_Done,
122284 // Label 6817: @334236
122285 GIM_Try, /*On fail goto*//*Label 6818*/ GIMT_Encode4(334317), // Rule ID 5748 //
122286 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
122287 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122288 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
122289 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
122290 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
122291 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
122292 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
122293 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
122294 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122295 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
122296 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
122297 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
122298 // MIs[3] Operand 1
122299 // No operand predicates
122300 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122301 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122302 GIM_CheckIsSafeToFold, /*NumInsns*/3,
122303 // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
122304 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
122305 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122306 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122307 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
122308 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
122309 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
122310 GIR_RootConstrainSelectedInstOperands,
122311 // GIR_Coverage, 5748,
122312 GIR_EraseRootFromParent_Done,
122313 // Label 6818: @334317
122314 GIM_Try, /*On fail goto*//*Label 6819*/ GIMT_Encode4(334401), // Rule ID 5774 //
122315 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
122316 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122317 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
122318 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
122319 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122320 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
122321 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
122322 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
122323 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
122324 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122325 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
122326 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
122327 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
122328 // MIs[3] Operand 1
122329 // No operand predicates
122330 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122331 GIM_CheckIsSafeToFold, /*NumInsns*/3,
122332 // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
122333 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
122334 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122335 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122336 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
122337 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
122338 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
122339 GIR_RootConstrainSelectedInstOperands,
122340 // GIR_Coverage, 5774,
122341 GIR_EraseRootFromParent_Done,
122342 // Label 6819: @334401
122343 GIM_Try, /*On fail goto*//*Label 6820*/ GIMT_Encode4(334479), // Rule ID 5814 //
122344 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122345 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
122346 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
122347 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
122348 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
122349 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
122350 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
122351 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
122352 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122353 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
122354 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
122355 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
122356 // MIs[3] Operand 1
122357 // No operand predicates
122358 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122359 GIM_CheckIsSafeToFold, /*NumInsns*/3,
122360 // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
122361 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
122362 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122363 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122364 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
122365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
122366 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
122367 GIR_RootConstrainSelectedInstOperands,
122368 // GIR_Coverage, 5814,
122369 GIR_EraseRootFromParent_Done,
122370 // Label 6820: @334479
122371 GIM_Try, /*On fail goto*//*Label 6821*/ GIMT_Encode4(334560), // Rule ID 5696 //
122372 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
122373 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122374 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
122375 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
122376 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
122377 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
122378 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
122379 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
122380 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
122381 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122382 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
122383 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
122384 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
122385 // MIs[3] Operand 1
122386 // No operand predicates
122387 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122388 GIM_CheckIsSafeToFold, /*NumInsns*/3,
122389 // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
122390 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
122391 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122392 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122393 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
122394 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
122395 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
122396 GIR_RootConstrainSelectedInstOperands,
122397 // GIR_Coverage, 5696,
122398 GIR_EraseRootFromParent_Done,
122399 // Label 6821: @334560
122400 GIM_Try, /*On fail goto*//*Label 6822*/ GIMT_Encode4(334629), // Rule ID 2457 //
122401 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
122402 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122403 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
122404 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
122405 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
122406 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122407 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
122408 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
122409 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
122410 // MIs[2] Operand 1
122411 // No operand predicates
122412 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122413 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122414 GIM_CheckIsSafeToFold, /*NumInsns*/2,
122415 // (strict_fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
122416 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
122417 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122418 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122419 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
122420 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
122421 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
122422 GIR_RootConstrainSelectedInstOperands,
122423 // GIR_Coverage, 2457,
122424 GIR_EraseRootFromParent_Done,
122425 // Label 6822: @334629
122426 GIM_Try, /*On fail goto*//*Label 6823*/ GIMT_Encode4(334698), // Rule ID 5670 //
122427 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
122428 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122429 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
122430 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
122431 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
122432 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
122433 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122434 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
122435 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
122436 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
122437 // MIs[2] Operand 1
122438 // No operand predicates
122439 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122440 GIM_CheckIsSafeToFold, /*NumInsns*/2,
122441 // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
122442 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
122443 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122444 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122445 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
122446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
122447 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
122448 GIR_RootConstrainSelectedInstOperands,
122449 // GIR_Coverage, 5670,
122450 GIR_EraseRootFromParent_Done,
122451 // Label 6823: @334698
122452 GIM_Try, /*On fail goto*//*Label 6824*/ GIMT_Encode4(334791), // Rule ID 5796 //
122453 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122454 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
122455 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
122456 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
122457 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
122458 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
122459 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
122460 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122461 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122462 GIM_CheckIsSafeToFold, /*NumInsns*/2,
122463 // (strict_fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
122464 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
122465 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
122466 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
122467 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
122468 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
122469 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
122470 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
122471 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
122472 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
122473 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122474 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122475 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
122476 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
122477 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
122478 GIR_RootConstrainSelectedInstOperands,
122479 // GIR_Coverage, 5796,
122480 GIR_EraseRootFromParent_Done,
122481 // Label 6824: @334791
122482 GIM_Try, /*On fail goto*//*Label 6825*/ GIMT_Encode4(334890), // Rule ID 5724 //
122483 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
122484 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122485 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
122486 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
122487 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
122488 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
122489 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
122490 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
122491 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122492 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122493 GIM_CheckIsSafeToFold, /*NumInsns*/2,
122494 // (strict_fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
122495 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
122496 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
122497 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
122498 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
122499 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
122500 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
122501 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
122502 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
122503 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
122504 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122505 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
122507 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
122508 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
122509 GIR_RootConstrainSelectedInstOperands,
122510 // GIR_Coverage, 5724,
122511 GIR_EraseRootFromParent_Done,
122512 // Label 6825: @334890
122513 GIM_Try, /*On fail goto*//*Label 6826*/ GIMT_Encode4(334986), // Rule ID 5750 //
122514 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
122515 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122516 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
122517 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
122518 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
122519 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
122520 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
122521 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
122522 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122523 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122524 GIM_CheckIsSafeToFold, /*NumInsns*/2,
122525 // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
122526 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
122527 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
122528 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
122529 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
122530 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
122531 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
122532 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
122533 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
122534 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
122535 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122536 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122537 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
122538 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
122539 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
122540 GIR_RootConstrainSelectedInstOperands,
122541 // GIR_Coverage, 5750,
122542 GIR_EraseRootFromParent_Done,
122543 // Label 6826: @334986
122544 GIM_Try, /*On fail goto*//*Label 6827*/ GIMT_Encode4(335085), // Rule ID 5776 //
122545 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
122546 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122547 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
122548 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
122549 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122550 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
122551 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
122552 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
122553 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
122554 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122555 GIM_CheckIsSafeToFold, /*NumInsns*/2,
122556 // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
122557 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
122558 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
122559 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
122560 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
122561 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
122562 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
122563 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
122564 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
122565 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
122566 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122567 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
122569 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
122570 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
122571 GIR_RootConstrainSelectedInstOperands,
122572 // GIR_Coverage, 5776,
122573 GIR_EraseRootFromParent_Done,
122574 // Label 6827: @335085
122575 GIM_Try, /*On fail goto*//*Label 6828*/ GIMT_Encode4(335178), // Rule ID 5818 //
122576 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122577 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
122578 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
122579 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
122580 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
122581 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
122582 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
122583 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
122584 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122585 GIM_CheckIsSafeToFold, /*NumInsns*/2,
122586 // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
122587 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
122588 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
122589 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
122590 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
122591 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
122592 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
122593 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
122594 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
122595 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
122596 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122597 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122598 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
122599 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
122600 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
122601 GIR_RootConstrainSelectedInstOperands,
122602 // GIR_Coverage, 5818,
122603 GIR_EraseRootFromParent_Done,
122604 // Label 6828: @335178
122605 GIM_Try, /*On fail goto*//*Label 6829*/ GIMT_Encode4(335274), // Rule ID 5698 //
122606 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
122607 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122608 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
122609 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
122610 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
122611 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
122612 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
122613 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
122614 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
122615 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122616 GIM_CheckIsSafeToFold, /*NumInsns*/2,
122617 // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rd) => (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
122618 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
122619 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
122620 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
122621 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
122622 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
122623 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
122624 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
122625 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
122626 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
122627 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122628 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122629 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
122630 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
122631 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
122632 GIR_RootConstrainSelectedInstOperands,
122633 // GIR_Coverage, 5698,
122634 GIR_EraseRootFromParent_Done,
122635 // Label 6829: @335274
122636 GIM_Try, /*On fail goto*//*Label 6830*/ GIMT_Encode4(335358), // Rule ID 2459 //
122637 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
122638 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122639 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
122640 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
122641 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
122642 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122643 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122644 GIM_CheckIsSafeToFold, /*NumInsns*/1,
122645 // (strict_fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
122646 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
122647 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
122648 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
122649 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
122650 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
122651 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
122652 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
122653 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
122654 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
122655 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122656 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122657 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
122658 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
122659 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
122660 GIR_RootConstrainSelectedInstOperands,
122661 // GIR_Coverage, 2459,
122662 GIR_EraseRootFromParent_Done,
122663 // Label 6830: @335358
122664 GIM_Try, /*On fail goto*//*Label 6831*/ GIMT_Encode4(335408), // Rule ID 12582 //
122665 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
122666 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122667 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
122668 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
122669 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122670 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122671 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122672 GIM_CheckIsSafeToFold, /*NumInsns*/1,
122673 // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
122674 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f32),
122675 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122676 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122677 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
122678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
122679 GIR_RootConstrainSelectedInstOperands,
122680 // GIR_Coverage, 12582,
122681 GIR_EraseRootFromParent_Done,
122682 // Label 6831: @335408
122683 GIM_Try, /*On fail goto*//*Label 6832*/ GIMT_Encode4(335492), // Rule ID 5672 //
122684 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
122685 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122686 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
122687 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
122688 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
122689 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
122690 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122691 GIM_CheckIsSafeToFold, /*NumInsns*/1,
122692 // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rd) => (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
122693 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
122694 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
122695 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
122696 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
122697 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
122698 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
122699 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
122700 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
122701 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
122702 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122703 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122704 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
122705 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
122706 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
122707 GIR_RootConstrainSelectedInstOperands,
122708 // GIR_Coverage, 5672,
122709 GIR_EraseRootFromParent_Done,
122710 // Label 6832: @335492
122711 GIM_Try, /*On fail goto*//*Label 6833*/ GIMT_Encode4(335542), // Rule ID 1296 //
122712 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
122713 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122714 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
122715 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
122716 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
122717 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122718 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122719 GIM_CheckIsSafeToFold, /*NumInsns*/1,
122720 // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rd) => (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
122721 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f32),
122722 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122723 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122724 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
122725 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
122726 GIR_RootConstrainSelectedInstOperands,
122727 // GIR_Coverage, 1296,
122728 GIR_EraseRootFromParent_Done,
122729 // Label 6833: @335542
122730 GIM_Try, /*On fail goto*//*Label 6834*/ GIMT_Encode4(335575), // Rule ID 1286 //
122731 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
122732 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122733 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122734 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122735 // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd) => (FMLAv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
122736 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4f32),
122737 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122738 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122739 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
122740 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
122741 GIR_RootConstrainSelectedInstOperands,
122742 // GIR_Coverage, 1286,
122743 GIR_EraseRootFromParent_Done,
122744 // Label 6834: @335575
122745 GIM_Reject,
122746 // Label 6815: @335576
122747 GIM_Reject,
122748 // Label 6696: @335577
122749 GIM_Try, /*On fail goto*//*Label 6835*/ GIMT_Encode4(336755),
122750 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
122751 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
122752 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
122753 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122754 GIM_Try, /*On fail goto*//*Label 6836*/ GIMT_Encode4(335679), // Rule ID 5708 //
122755 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
122756 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122757 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
122758 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
122759 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
122760 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
122761 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
122762 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
122763 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
122764 // MIs[2] Operand 1
122765 // No operand predicates
122766 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
122767 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
122768 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
122769 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122770 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122771 GIM_CheckIsSafeToFold, /*NumInsns*/3,
122772 // (strict_fma:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
122773 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
122774 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122775 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122776 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
122777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
122778 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
122779 GIR_RootConstrainSelectedInstOperands,
122780 // GIR_Coverage, 5708,
122781 GIR_EraseRootFromParent_Done,
122782 // Label 6836: @335679
122783 GIM_Try, /*On fail goto*//*Label 6837*/ GIMT_Encode4(335760), // Rule ID 5734 //
122784 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
122785 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122786 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
122787 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
122788 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
122789 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
122790 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
122791 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
122792 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
122793 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
122794 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
122795 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
122796 // MIs[3] Operand 1
122797 // No operand predicates
122798 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122799 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122800 GIM_CheckIsSafeToFold, /*NumInsns*/3,
122801 // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
122802 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
122803 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122804 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122805 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
122806 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
122807 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
122808 GIR_RootConstrainSelectedInstOperands,
122809 // GIR_Coverage, 5734,
122810 GIR_EraseRootFromParent_Done,
122811 // Label 6837: @335760
122812 GIM_Try, /*On fail goto*//*Label 6838*/ GIMT_Encode4(335844), // Rule ID 5760 //
122813 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
122814 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122815 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
122816 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
122817 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122818 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
122819 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
122820 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
122821 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
122822 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
122823 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
122824 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
122825 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
122826 // MIs[3] Operand 1
122827 // No operand predicates
122828 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122829 GIM_CheckIsSafeToFold, /*NumInsns*/3,
122830 // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
122831 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
122832 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122833 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122834 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
122835 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
122836 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
122837 GIR_RootConstrainSelectedInstOperands,
122838 // GIR_Coverage, 5760,
122839 GIR_EraseRootFromParent_Done,
122840 // Label 6838: @335844
122841 GIM_Try, /*On fail goto*//*Label 6839*/ GIMT_Encode4(335925), // Rule ID 5682 //
122842 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
122843 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122844 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
122845 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
122846 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
122847 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
122848 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
122849 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
122850 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
122851 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
122852 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
122853 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
122854 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
122855 // MIs[3] Operand 1
122856 // No operand predicates
122857 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122858 GIM_CheckIsSafeToFold, /*NumInsns*/3,
122859 // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
122860 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
122861 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122862 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122863 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
122864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
122865 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
122866 GIR_RootConstrainSelectedInstOperands,
122867 // GIR_Coverage, 5682,
122868 GIR_EraseRootFromParent_Done,
122869 // Label 6839: @335925
122870 GIM_Try, /*On fail goto*//*Label 6840*/ GIMT_Encode4(335994), // Rule ID 2443 //
122871 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
122872 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122873 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
122874 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
122875 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
122876 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
122877 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
122878 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
122879 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
122880 // MIs[2] Operand 1
122881 // No operand predicates
122882 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122883 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122884 GIM_CheckIsSafeToFold, /*NumInsns*/2,
122885 // (strict_fma:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
122886 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
122887 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122888 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122889 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
122890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
122891 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
122892 GIR_RootConstrainSelectedInstOperands,
122893 // GIR_Coverage, 2443,
122894 GIR_EraseRootFromParent_Done,
122895 // Label 6840: @335994
122896 GIM_Try, /*On fail goto*//*Label 6841*/ GIMT_Encode4(336063), // Rule ID 5656 //
122897 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
122898 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122899 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
122900 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
122901 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
122902 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
122903 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
122904 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
122905 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
122906 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
122907 // MIs[2] Operand 1
122908 // No operand predicates
122909 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122910 GIM_CheckIsSafeToFold, /*NumInsns*/2,
122911 // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
122912 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
122913 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122914 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122915 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
122916 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
122917 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
122918 GIR_RootConstrainSelectedInstOperands,
122919 // GIR_Coverage, 5656,
122920 GIR_EraseRootFromParent_Done,
122921 // Label 6841: @336063
122922 GIM_Try, /*On fail goto*//*Label 6842*/ GIMT_Encode4(336162), // Rule ID 5710 //
122923 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
122924 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122925 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
122926 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
122927 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
122928 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
122929 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
122930 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
122931 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122932 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122933 GIM_CheckIsSafeToFold, /*NumInsns*/2,
122934 // (strict_fma:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
122935 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
122936 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
122937 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
122938 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
122939 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
122940 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
122941 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
122942 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
122943 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
122944 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122945 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
122947 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
122948 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
122949 GIR_RootConstrainSelectedInstOperands,
122950 // GIR_Coverage, 5710,
122951 GIR_EraseRootFromParent_Done,
122952 // Label 6842: @336162
122953 GIM_Try, /*On fail goto*//*Label 6843*/ GIMT_Encode4(336258), // Rule ID 5736 //
122954 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
122955 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122956 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
122957 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
122958 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
122959 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
122960 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
122961 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
122962 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122963 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122964 GIM_CheckIsSafeToFold, /*NumInsns*/2,
122965 // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
122966 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
122967 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
122968 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
122969 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
122970 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
122971 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
122972 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
122973 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
122974 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
122975 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
122976 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
122977 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
122978 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
122979 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
122980 GIR_RootConstrainSelectedInstOperands,
122981 // GIR_Coverage, 5736,
122982 GIR_EraseRootFromParent_Done,
122983 // Label 6843: @336258
122984 GIM_Try, /*On fail goto*//*Label 6844*/ GIMT_Encode4(336357), // Rule ID 5762 //
122985 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
122986 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
122987 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
122988 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
122989 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122990 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
122991 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
122992 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
122993 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
122994 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
122995 GIM_CheckIsSafeToFold, /*NumInsns*/2,
122996 // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
122997 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
122998 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
122999 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
123000 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
123001 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
123002 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
123003 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
123004 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
123005 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
123006 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
123007 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
123008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
123009 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
123010 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
123011 GIR_RootConstrainSelectedInstOperands,
123012 // GIR_Coverage, 5762,
123013 GIR_EraseRootFromParent_Done,
123014 // Label 6844: @336357
123015 GIM_Try, /*On fail goto*//*Label 6845*/ GIMT_Encode4(336453), // Rule ID 5684 //
123016 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
123017 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123018 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
123019 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
123020 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
123021 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
123022 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
123023 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
123024 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
123025 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123026 GIM_CheckIsSafeToFold, /*NumInsns*/2,
123027 // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V128:{ *:[v8f16] }:$Rd) => (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
123028 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
123029 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
123030 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
123031 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
123032 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
123033 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
123034 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
123035 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
123036 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
123037 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
123038 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
123039 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
123040 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
123041 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
123042 GIR_RootConstrainSelectedInstOperands,
123043 // GIR_Coverage, 5684,
123044 GIR_EraseRootFromParent_Done,
123045 // Label 6845: @336453
123046 GIM_Try, /*On fail goto*//*Label 6846*/ GIMT_Encode4(336537), // Rule ID 2445 //
123047 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
123048 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
123049 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
123050 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
123051 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
123052 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123053 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123054 GIM_CheckIsSafeToFold, /*NumInsns*/1,
123055 // (strict_fma:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
123056 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
123057 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
123058 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
123059 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
123060 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
123061 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
123062 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
123063 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
123064 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
123065 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
123066 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
123067 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
123068 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
123069 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
123070 GIR_RootConstrainSelectedInstOperands,
123071 // GIR_Coverage, 2445,
123072 GIR_EraseRootFromParent_Done,
123073 // Label 6846: @336537
123074 GIM_Try, /*On fail goto*//*Label 6847*/ GIMT_Encode4(336587), // Rule ID 12578 //
123075 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
123076 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
123077 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
123078 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
123079 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123080 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123081 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123082 GIM_CheckIsSafeToFold, /*NumInsns*/1,
123083 // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
123084 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8f16),
123085 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
123086 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
123087 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
123088 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
123089 GIR_RootConstrainSelectedInstOperands,
123090 // GIR_Coverage, 12578,
123091 GIR_EraseRootFromParent_Done,
123092 // Label 6847: @336587
123093 GIM_Try, /*On fail goto*//*Label 6848*/ GIMT_Encode4(336671), // Rule ID 5658 //
123094 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
123095 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123096 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
123097 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
123098 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
123099 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
123100 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123101 GIM_CheckIsSafeToFold, /*NumInsns*/1,
123102 // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rd) => (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
123103 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
123104 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
123105 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
123106 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
123107 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
123108 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
123109 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
123110 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
123111 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
123112 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
123113 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
123114 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
123115 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
123116 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
123117 GIR_RootConstrainSelectedInstOperands,
123118 // GIR_Coverage, 5658,
123119 GIR_EraseRootFromParent_Done,
123120 // Label 6848: @336671
123121 GIM_Try, /*On fail goto*//*Label 6849*/ GIMT_Encode4(336721), // Rule ID 1292 //
123122 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
123123 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123124 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
123125 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
123126 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
123127 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123128 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123129 GIM_CheckIsSafeToFold, /*NumInsns*/1,
123130 // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rd) => (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
123131 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8f16),
123132 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
123133 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
123134 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
123135 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
123136 GIR_RootConstrainSelectedInstOperands,
123137 // GIR_Coverage, 1292,
123138 GIR_EraseRootFromParent_Done,
123139 // Label 6849: @336721
123140 GIM_Try, /*On fail goto*//*Label 6850*/ GIMT_Encode4(336754), // Rule ID 1282 //
123141 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
123142 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123143 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123144 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123145 // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd) => (FMLAv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
123146 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8f16),
123147 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
123148 GIR_RootToRootCopy, /*OpIdx*/3, // Rd
123149 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
123150 GIR_RootToRootCopy, /*OpIdx*/1, // Rm
123151 GIR_RootConstrainSelectedInstOperands,
123152 // GIR_Coverage, 1282,
123153 GIR_EraseRootFromParent_Done,
123154 // Label 6850: @336754
123155 GIM_Reject,
123156 // Label 6835: @336755
123157 GIM_Reject,
123158 // Label 6697: @336756
123159 GIM_Reject,
123160 // Label 95: @336757
123161 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6859*/ GIMT_Encode4(337056),
123162 /*GILLT_s16*//*Label 6851*/ GIMT_Encode4(336808),
123163 /*GILLT_s32*//*Label 6852*/ GIMT_Encode4(336839),
123164 /*GILLT_s64*//*Label 6853*/ GIMT_Encode4(336870), GIMT_Encode4(0),
123165 /*GILLT_v2s32*//*Label 6854*/ GIMT_Encode4(336901),
123166 /*GILLT_v2s64*//*Label 6855*/ GIMT_Encode4(336932),
123167 /*GILLT_v4s16*//*Label 6856*/ GIMT_Encode4(336963),
123168 /*GILLT_v4s32*//*Label 6857*/ GIMT_Encode4(336994), GIMT_Encode4(0),
123169 /*GILLT_v8s16*//*Label 6858*/ GIMT_Encode4(337025),
123170 // Label 6851: @336808
123171 GIM_Try, /*On fail goto*//*Label 6860*/ GIMT_Encode4(336838), // Rule ID 563 //
123172 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
123173 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
123174 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123175 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123176 // (strict_fsqrt:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (FSQRTHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
123177 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTHr),
123178 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123179 GIR_RootConstrainSelectedInstOperands,
123180 // GIR_Coverage, 563,
123181 GIR_Done,
123182 // Label 6860: @336838
123183 GIM_Reject,
123184 // Label 6852: @336839
123185 GIM_Try, /*On fail goto*//*Label 6861*/ GIMT_Encode4(336869), // Rule ID 565 //
123186 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
123187 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
123188 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
123189 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
123190 // (strict_fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (FSQRTSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
123191 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTSr),
123192 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123193 GIR_RootConstrainSelectedInstOperands,
123194 // GIR_Coverage, 565,
123195 GIR_Done,
123196 // Label 6861: @336869
123197 GIM_Reject,
123198 // Label 6853: @336870
123199 GIM_Try, /*On fail goto*//*Label 6862*/ GIMT_Encode4(336900), // Rule ID 567 //
123200 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
123201 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
123202 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123203 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123204 // (strict_fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (FSQRTDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
123205 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTDr),
123206 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123207 GIR_RootConstrainSelectedInstOperands,
123208 // GIR_Coverage, 567,
123209 GIR_Done,
123210 // Label 6862: @336900
123211 GIM_Reject,
123212 // Label 6854: @336901
123213 GIM_Try, /*On fail goto*//*Label 6863*/ GIMT_Encode4(336931), // Rule ID 946 //
123214 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
123215 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
123216 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123217 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123218 // (strict_fsqrt:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (FSQRTv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
123219 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv2f32),
123220 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123221 GIR_RootConstrainSelectedInstOperands,
123222 // GIR_Coverage, 946,
123223 GIR_Done,
123224 // Label 6863: @336931
123225 GIM_Reject,
123226 // Label 6855: @336932
123227 GIM_Try, /*On fail goto*//*Label 6864*/ GIMT_Encode4(336962), // Rule ID 950 //
123228 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
123229 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
123230 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123231 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123232 // (strict_fsqrt:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn) => (FSQRTv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
123233 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv2f64),
123234 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123235 GIR_RootConstrainSelectedInstOperands,
123236 // GIR_Coverage, 950,
123237 GIR_Done,
123238 // Label 6864: @336962
123239 GIM_Reject,
123240 // Label 6856: @336963
123241 GIM_Try, /*On fail goto*//*Label 6865*/ GIMT_Encode4(336993), // Rule ID 942 //
123242 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
123243 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
123244 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123245 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123246 // (strict_fsqrt:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (FSQRTv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
123247 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv4f16),
123248 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123249 GIR_RootConstrainSelectedInstOperands,
123250 // GIR_Coverage, 942,
123251 GIR_Done,
123252 // Label 6865: @336993
123253 GIM_Reject,
123254 // Label 6857: @336994
123255 GIM_Try, /*On fail goto*//*Label 6866*/ GIMT_Encode4(337024), // Rule ID 948 //
123256 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
123257 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
123258 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123259 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123260 // (strict_fsqrt:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (FSQRTv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
123261 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv4f32),
123262 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123263 GIR_RootConstrainSelectedInstOperands,
123264 // GIR_Coverage, 948,
123265 GIR_Done,
123266 // Label 6866: @337024
123267 GIM_Reject,
123268 // Label 6858: @337025
123269 GIM_Try, /*On fail goto*//*Label 6867*/ GIMT_Encode4(337055), // Rule ID 944 //
123270 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
123271 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
123272 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123273 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123274 // (strict_fsqrt:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (FSQRTv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
123275 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv8f16),
123276 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123277 GIR_RootConstrainSelectedInstOperands,
123278 // GIR_Coverage, 944,
123279 GIR_Done,
123280 // Label 6867: @337055
123281 GIM_Reject,
123282 // Label 6859: @337056
123283 GIM_Reject,
123284 // Label 96: @337057
123285 GIM_Try, /*On fail goto*//*Label 6868*/ GIMT_Encode4(337070), // Rule ID 6122 //
123286 // (trap) => (BRK 1:{ *:[i32] })
123287 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRK),
123288 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
123289 GIR_RootConstrainSelectedInstOperands,
123290 // GIR_Coverage, 6122,
123291 GIR_EraseRootFromParent_Done,
123292 // Label 6868: @337070
123293 GIM_Reject,
123294 // Label 97: @337071
123295 GIM_Try, /*On fail goto*//*Label 6869*/ GIMT_Encode4(337091), // Rule ID 6123 //
123296 // (debugtrap) => (BRK 61440:{ *:[i32] })
123297 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRK),
123298 GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(61440),
123299 GIR_RootConstrainSelectedInstOperands,
123300 // GIR_Coverage, 6123,
123301 GIR_EraseRootFromParent_Done,
123302 // Label 6869: @337091
123303 GIM_Reject,
123304 // Label 98: @337092
123305 GIM_Try, /*On fail goto*//*Label 6870*/ GIMT_Encode4(337116), // Rule ID 6124 //
123306 // MIs[0] kind
123307 GIM_CheckIsImm, /*MI*/0, /*Op*/0,
123308 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_ubsan_trap_imm),
123309 // (ubsantrap (timm:{ *:[i32] })<<P:Predicate_ubsan_trap_imm>><<X:ubsan_trap_xform>>:$kind) => (BRK (ubsan_trap_xform:{ *:[i32] } (timm:{ *:[i32] })<<P:Predicate_ubsan_trap_imm>>:$kind))
123310 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRK),
123311 GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, /*OperandRenderer*/GIMT_Encode2(GICR_renderUbsanTrap), // kind
123312 GIR_RootConstrainSelectedInstOperands,
123313 // GIR_Coverage, 6124,
123314 GIR_EraseRootFromParent_Done,
123315 // Label 6870: @337116
123316 GIM_Reject,
123317 // Label 99: @337117
123318 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 6874*/ GIMT_Encode4(337426),
123319 /*GILLT_s16*//*Label 6871*/ GIMT_Encode4(337140),
123320 /*GILLT_s32*//*Label 6872*/ GIMT_Encode4(337293),
123321 /*GILLT_s64*//*Label 6873*/ GIMT_Encode4(337398),
123322 // Label 6871: @337140
123323 GIM_Try, /*On fail goto*//*Label 6875*/ GIMT_Encode4(337241), // Rule ID 5240 //
123324 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
123325 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
123326 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123327 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123328 // (vecreduce_fadd:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) => (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } (FADDPv8f16:{ *:[f128] } (FADDPv8f16:{ *:[f128] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rn), dsub:{ *:[i32] }))
123329 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
123330 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
123331 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
123332 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FADDPv8f16),
123333 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
123334 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Rn
123335 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Rn
123336 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
123337 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FADDPv8f16),
123338 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
123339 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
123340 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
123341 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
123342 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
123343 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
123344 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
123345 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
123346 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
123347 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i16p),
123348 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
123349 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
123350 GIR_RootConstrainSelectedInstOperands,
123351 // GIR_Coverage, 5240,
123352 GIR_EraseRootFromParent_Done,
123353 // Label 6875: @337241
123354 GIM_Try, /*On fail goto*//*Label 6876*/ GIMT_Encode4(337292), // Rule ID 5241 //
123355 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
123356 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
123357 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123358 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123359 // (vecreduce_fadd:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) => (FADDPv2i16p:{ *:[f16] } (FADDPv4f16:{ *:[i64] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rn))
123360 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
123361 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f16),
123362 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
123363 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
123364 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
123365 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
123366 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i16p),
123367 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
123368 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
123369 GIR_RootConstrainSelectedInstOperands,
123370 // GIR_Coverage, 5241,
123371 GIR_EraseRootFromParent_Done,
123372 // Label 6876: @337292
123373 GIM_Reject,
123374 // Label 6872: @337293
123375 GIM_Try, /*On fail goto*//*Label 6877*/ GIMT_Encode4(337370), // Rule ID 5242 //
123376 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
123377 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
123378 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123379 // (vecreduce_fadd:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) => (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } (FADDPv4f32:{ *:[f128] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rn), dsub:{ *:[i32] }))
123380 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
123381 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
123382 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f32),
123383 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
123384 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
123385 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
123386 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
123387 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
123388 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
123389 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
123390 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
123391 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
123392 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
123393 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
123394 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
123395 GIR_RootConstrainSelectedInstOperands,
123396 // GIR_Coverage, 5242,
123397 GIR_EraseRootFromParent_Done,
123398 // Label 6877: @337370
123399 GIM_Try, /*On fail goto*//*Label 6878*/ GIMT_Encode4(337397), // Rule ID 5243 //
123400 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
123401 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
123402 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123403 // (vecreduce_fadd:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) => (FADDPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
123404 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
123405 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123406 GIR_RootConstrainSelectedInstOperands,
123407 // GIR_Coverage, 5243,
123408 GIR_Done,
123409 // Label 6878: @337397
123410 GIM_Reject,
123411 // Label 6873: @337398
123412 GIM_Try, /*On fail goto*//*Label 6879*/ GIMT_Encode4(337425), // Rule ID 5244 //
123413 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
123414 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123415 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123416 // (vecreduce_fadd:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) => (FADDPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
123417 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i64p),
123418 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123419 GIR_RootConstrainSelectedInstOperands,
123420 // GIR_Coverage, 5244,
123421 GIR_Done,
123422 // Label 6879: @337425
123423 GIM_Reject,
123424 // Label 6874: @337426
123425 GIM_Reject,
123426 // Label 100: @337427
123427 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 6883*/ GIMT_Encode4(337597),
123428 /*GILLT_s16*//*Label 6880*/ GIMT_Encode4(337450),
123429 /*GILLT_s32*//*Label 6881*/ GIMT_Encode4(337511),
123430 /*GILLT_s64*//*Label 6882*/ GIMT_Encode4(337569),
123431 // Label 6880: @337450
123432 GIM_Try, /*On fail goto*//*Label 6884*/ GIMT_Encode4(337480), // Rule ID 1929 //
123433 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
123434 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
123435 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123436 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123437 // (vecreduce_fmax:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) => (FMAXNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
123438 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMVv4i16v),
123439 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123440 GIR_RootConstrainSelectedInstOperands,
123441 // GIR_Coverage, 1929,
123442 GIR_Done,
123443 // Label 6884: @337480
123444 GIM_Try, /*On fail goto*//*Label 6885*/ GIMT_Encode4(337510), // Rule ID 1931 //
123445 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
123446 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
123447 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123448 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123449 // (vecreduce_fmax:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) => (FMAXNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
123450 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMVv8i16v),
123451 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123452 GIR_RootConstrainSelectedInstOperands,
123453 // GIR_Coverage, 1931,
123454 GIR_Done,
123455 // Label 6885: @337510
123456 GIM_Reject,
123457 // Label 6881: @337511
123458 GIM_Try, /*On fail goto*//*Label 6886*/ GIMT_Encode4(337541), // Rule ID 1933 //
123459 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
123460 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
123461 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
123462 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123463 // (vecreduce_fmax:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) => (FMAXNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
123464 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMVv4i32v),
123465 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123466 GIR_RootConstrainSelectedInstOperands,
123467 // GIR_Coverage, 1933,
123468 GIR_Done,
123469 // Label 6886: @337541
123470 GIM_Try, /*On fail goto*//*Label 6887*/ GIMT_Encode4(337568), // Rule ID 5250 //
123471 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
123472 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
123473 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123474 // (vecreduce_fmax:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) => (FMAXNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
123475 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv2i32p),
123476 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123477 GIR_RootConstrainSelectedInstOperands,
123478 // GIR_Coverage, 5250,
123479 GIR_Done,
123480 // Label 6887: @337568
123481 GIM_Reject,
123482 // Label 6882: @337569
123483 GIM_Try, /*On fail goto*//*Label 6888*/ GIMT_Encode4(337596), // Rule ID 5252 //
123484 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
123485 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123486 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123487 // (vecreduce_fmax:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) => (FMAXNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
123488 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv2i64p),
123489 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123490 GIR_RootConstrainSelectedInstOperands,
123491 // GIR_Coverage, 5252,
123492 GIR_Done,
123493 // Label 6888: @337596
123494 GIM_Reject,
123495 // Label 6883: @337597
123496 GIM_Reject,
123497 // Label 101: @337598
123498 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 6892*/ GIMT_Encode4(337768),
123499 /*GILLT_s16*//*Label 6889*/ GIMT_Encode4(337621),
123500 /*GILLT_s32*//*Label 6890*/ GIMT_Encode4(337682),
123501 /*GILLT_s64*//*Label 6891*/ GIMT_Encode4(337740),
123502 // Label 6889: @337621
123503 GIM_Try, /*On fail goto*//*Label 6893*/ GIMT_Encode4(337651), // Rule ID 1941 //
123504 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
123505 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
123506 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123507 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123508 // (vecreduce_fmin:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) => (FMINNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
123509 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMVv4i16v),
123510 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123511 GIR_RootConstrainSelectedInstOperands,
123512 // GIR_Coverage, 1941,
123513 GIR_Done,
123514 // Label 6893: @337651
123515 GIM_Try, /*On fail goto*//*Label 6894*/ GIMT_Encode4(337681), // Rule ID 1943 //
123516 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
123517 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
123518 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123519 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123520 // (vecreduce_fmin:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) => (FMINNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
123521 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMVv8i16v),
123522 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123523 GIR_RootConstrainSelectedInstOperands,
123524 // GIR_Coverage, 1943,
123525 GIR_Done,
123526 // Label 6894: @337681
123527 GIM_Reject,
123528 // Label 6890: @337682
123529 GIM_Try, /*On fail goto*//*Label 6895*/ GIMT_Encode4(337712), // Rule ID 1945 //
123530 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
123531 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
123532 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
123533 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123534 // (vecreduce_fmin:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) => (FMINNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
123535 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMVv4i32v),
123536 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123537 GIR_RootConstrainSelectedInstOperands,
123538 // GIR_Coverage, 1945,
123539 GIR_Done,
123540 // Label 6895: @337712
123541 GIM_Try, /*On fail goto*//*Label 6896*/ GIMT_Encode4(337739), // Rule ID 5258 //
123542 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
123543 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
123544 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123545 // (vecreduce_fmin:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) => (FMINNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
123546 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv2i32p),
123547 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123548 GIR_RootConstrainSelectedInstOperands,
123549 // GIR_Coverage, 5258,
123550 GIR_Done,
123551 // Label 6896: @337739
123552 GIM_Reject,
123553 // Label 6891: @337740
123554 GIM_Try, /*On fail goto*//*Label 6897*/ GIMT_Encode4(337767), // Rule ID 5260 //
123555 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
123556 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123557 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123558 // (vecreduce_fmin:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) => (FMINNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
123559 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv2i64p),
123560 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123561 GIR_RootConstrainSelectedInstOperands,
123562 // GIR_Coverage, 5260,
123563 GIR_Done,
123564 // Label 6897: @337767
123565 GIM_Reject,
123566 // Label 6892: @337768
123567 GIM_Reject,
123568 // Label 102: @337769
123569 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 6901*/ GIMT_Encode4(337939),
123570 /*GILLT_s16*//*Label 6898*/ GIMT_Encode4(337792),
123571 /*GILLT_s32*//*Label 6899*/ GIMT_Encode4(337853),
123572 /*GILLT_s64*//*Label 6900*/ GIMT_Encode4(337911),
123573 // Label 6898: @337792
123574 GIM_Try, /*On fail goto*//*Label 6902*/ GIMT_Encode4(337822), // Rule ID 1935 //
123575 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
123576 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
123577 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123578 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123579 // (vecreduce_fmaximum:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) => (FMAXVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
123580 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXVv4i16v),
123581 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123582 GIR_RootConstrainSelectedInstOperands,
123583 // GIR_Coverage, 1935,
123584 GIR_Done,
123585 // Label 6902: @337822
123586 GIM_Try, /*On fail goto*//*Label 6903*/ GIMT_Encode4(337852), // Rule ID 1937 //
123587 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
123588 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
123589 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123590 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123591 // (vecreduce_fmaximum:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) => (FMAXVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
123592 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXVv8i16v),
123593 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123594 GIR_RootConstrainSelectedInstOperands,
123595 // GIR_Coverage, 1937,
123596 GIR_Done,
123597 // Label 6903: @337852
123598 GIM_Reject,
123599 // Label 6899: @337853
123600 GIM_Try, /*On fail goto*//*Label 6904*/ GIMT_Encode4(337883), // Rule ID 1939 //
123601 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
123602 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
123603 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
123604 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123605 // (vecreduce_fmaximum:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) => (FMAXVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
123606 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXVv4i32v),
123607 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123608 GIR_RootConstrainSelectedInstOperands,
123609 // GIR_Coverage, 1939,
123610 GIR_Done,
123611 // Label 6904: @337883
123612 GIM_Try, /*On fail goto*//*Label 6905*/ GIMT_Encode4(337910), // Rule ID 5254 //
123613 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
123614 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
123615 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123616 // (vecreduce_fmaximum:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) => (FMAXPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
123617 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv2i32p),
123618 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123619 GIR_RootConstrainSelectedInstOperands,
123620 // GIR_Coverage, 5254,
123621 GIR_Done,
123622 // Label 6905: @337910
123623 GIM_Reject,
123624 // Label 6900: @337911
123625 GIM_Try, /*On fail goto*//*Label 6906*/ GIMT_Encode4(337938), // Rule ID 5256 //
123626 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
123627 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123628 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123629 // (vecreduce_fmaximum:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) => (FMAXPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
123630 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv2i64p),
123631 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123632 GIR_RootConstrainSelectedInstOperands,
123633 // GIR_Coverage, 5256,
123634 GIR_Done,
123635 // Label 6906: @337938
123636 GIM_Reject,
123637 // Label 6901: @337939
123638 GIM_Reject,
123639 // Label 103: @337940
123640 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 6910*/ GIMT_Encode4(338110),
123641 /*GILLT_s16*//*Label 6907*/ GIMT_Encode4(337963),
123642 /*GILLT_s32*//*Label 6908*/ GIMT_Encode4(338024),
123643 /*GILLT_s64*//*Label 6909*/ GIMT_Encode4(338082),
123644 // Label 6907: @337963
123645 GIM_Try, /*On fail goto*//*Label 6911*/ GIMT_Encode4(337993), // Rule ID 1947 //
123646 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
123647 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
123648 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123649 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123650 // (vecreduce_fminimum:{ *:[f16] } V64:{ *:[v4f16] }:$Rn) => (FMINVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
123651 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINVv4i16v),
123652 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123653 GIR_RootConstrainSelectedInstOperands,
123654 // GIR_Coverage, 1947,
123655 GIR_Done,
123656 // Label 6911: @337993
123657 GIM_Try, /*On fail goto*//*Label 6912*/ GIMT_Encode4(338023), // Rule ID 1949 //
123658 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
123659 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
123660 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123661 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123662 // (vecreduce_fminimum:{ *:[f16] } V128:{ *:[v8f16] }:$Rn) => (FMINVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
123663 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINVv8i16v),
123664 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123665 GIR_RootConstrainSelectedInstOperands,
123666 // GIR_Coverage, 1949,
123667 GIR_Done,
123668 // Label 6912: @338023
123669 GIM_Reject,
123670 // Label 6908: @338024
123671 GIM_Try, /*On fail goto*//*Label 6913*/ GIMT_Encode4(338054), // Rule ID 1951 //
123672 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
123673 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
123674 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
123675 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123676 // (vecreduce_fminimum:{ *:[f32] } V128:{ *:[v4f32] }:$Rn) => (FMINVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
123677 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINVv4i32v),
123678 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123679 GIR_RootConstrainSelectedInstOperands,
123680 // GIR_Coverage, 1951,
123681 GIR_Done,
123682 // Label 6913: @338054
123683 GIM_Try, /*On fail goto*//*Label 6914*/ GIMT_Encode4(338081), // Rule ID 5262 //
123684 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
123685 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
123686 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123687 // (vecreduce_fminimum:{ *:[f32] } V64:{ *:[v2f32] }:$Rn) => (FMINPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
123688 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINPv2i32p),
123689 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123690 GIR_RootConstrainSelectedInstOperands,
123691 // GIR_Coverage, 5262,
123692 GIR_Done,
123693 // Label 6914: @338081
123694 GIM_Reject,
123695 // Label 6909: @338082
123696 GIM_Try, /*On fail goto*//*Label 6915*/ GIMT_Encode4(338109), // Rule ID 5264 //
123697 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
123698 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123699 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123700 // (vecreduce_fminimum:{ *:[f64] } V128:{ *:[v2f64] }:$Rn) => (FMINPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
123701 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINPv2i64p),
123702 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
123703 GIR_RootConstrainSelectedInstOperands,
123704 // GIR_Coverage, 5264,
123705 GIR_Done,
123706 // Label 6915: @338109
123707 GIM_Reject,
123708 // Label 6910: @338110
123709 GIM_Reject,
123710 // Label 104: @338111
123711 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(4), /*)*//*default:*//*Label 6920*/ GIMT_Encode4(339239),
123712 /*GILLT_s8*//*Label 6916*/ GIMT_Encode4(338138),
123713 /*GILLT_s16*//*Label 6917*/ GIMT_Encode4(338185),
123714 /*GILLT_s32*//*Label 6918*/ GIMT_Encode4(338600),
123715 /*GILLT_s64*//*Label 6919*/ GIMT_Encode4(339053),
123716 // Label 6916: @338138
123717 GIM_Try, /*On fail goto*//*Label 6921*/ GIMT_Encode4(338161), // Rule ID 5507 //
123718 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
123719 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
123720 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123721 // (vecreduce_add:{ *:[i8] } V64:{ *:[v8i8] }:$Rn) => (ADDVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
123722 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i8v),
123723 GIR_RootConstrainSelectedInstOperands,
123724 // GIR_Coverage, 5507,
123725 GIR_Done,
123726 // Label 6921: @338161
123727 GIM_Try, /*On fail goto*//*Label 6922*/ GIMT_Encode4(338184), // Rule ID 5508 //
123728 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
123729 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
123730 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123731 // (vecreduce_add:{ *:[i8] } V128:{ *:[v16i8] }:$Rn) => (ADDVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
123732 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDVv16i8v),
123733 GIR_RootConstrainSelectedInstOperands,
123734 // GIR_Coverage, 5508,
123735 GIR_Done,
123736 // Label 6922: @338184
123737 GIM_Reject,
123738 // Label 6917: @338185
123739 GIM_Try, /*On fail goto*//*Label 6923*/ GIMT_Encode4(338235), // Rule ID 5450 //
123740 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
123741 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123742 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
123743 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
123744 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
123745 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
123746 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
123747 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123748 GIM_CheckIsSafeToFold, /*NumInsns*/1,
123749 // (vecreduce_add:{ *:[i16] } (intrinsic_wo_chain:{ *:[v4i16] } 687:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)) => (UADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn)
123750 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i8v),
123751 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
123752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
123753 GIR_RootConstrainSelectedInstOperands,
123754 // GIR_Coverage, 5450,
123755 GIR_EraseRootFromParent_Done,
123756 // Label 6923: @338235
123757 GIM_Try, /*On fail goto*//*Label 6924*/ GIMT_Encode4(338285), // Rule ID 5452 //
123758 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
123759 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123760 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
123761 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
123762 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
123763 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
123764 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
123765 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123766 GIM_CheckIsSafeToFold, /*NumInsns*/1,
123767 // (vecreduce_add:{ *:[i16] } (intrinsic_wo_chain:{ *:[v8i16] } 687:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)) => (UADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn)
123768 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv16i8v),
123769 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
123770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
123771 GIR_RootConstrainSelectedInstOperands,
123772 // GIR_Coverage, 5452,
123773 GIR_EraseRootFromParent_Done,
123774 // Label 6924: @338285
123775 GIM_Try, /*On fail goto*//*Label 6925*/ GIMT_Encode4(338335), // Rule ID 5460 //
123776 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
123777 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123778 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
123779 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
123780 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
123781 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
123782 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
123783 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123784 GIM_CheckIsSafeToFold, /*NumInsns*/1,
123785 // (vecreduce_add:{ *:[i16] } (intrinsic_wo_chain:{ *:[v4i16] } 622:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)) => (SADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn)
123786 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i8v),
123787 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
123788 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
123789 GIR_RootConstrainSelectedInstOperands,
123790 // GIR_Coverage, 5460,
123791 GIR_EraseRootFromParent_Done,
123792 // Label 6925: @338335
123793 GIM_Try, /*On fail goto*//*Label 6926*/ GIMT_Encode4(338385), // Rule ID 5462 //
123794 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
123795 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123796 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
123797 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
123798 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
123799 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
123800 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
123801 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123802 GIM_CheckIsSafeToFold, /*NumInsns*/1,
123803 // (vecreduce_add:{ *:[i16] } (intrinsic_wo_chain:{ *:[v8i16] } 622:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)) => (SADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn)
123804 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv16i8v),
123805 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
123806 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
123807 GIR_RootConstrainSelectedInstOperands,
123808 // GIR_Coverage, 5462,
123809 GIR_EraseRootFromParent_Done,
123810 // Label 6926: @338385
123811 GIM_Try, /*On fail goto*//*Label 6927*/ GIMT_Encode4(338427), // Rule ID 5459 //
123812 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
123813 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123814 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
123815 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
123816 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
123817 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123818 GIM_CheckIsSafeToFold, /*NumInsns*/1,
123819 // (vecreduce_add:{ *:[i16] } (AArch64saddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)) => (SADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn)
123820 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i8v),
123821 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
123822 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
123823 GIR_RootConstrainSelectedInstOperands,
123824 // GIR_Coverage, 5459,
123825 GIR_EraseRootFromParent_Done,
123826 // Label 6927: @338427
123827 GIM_Try, /*On fail goto*//*Label 6928*/ GIMT_Encode4(338469), // Rule ID 5461 //
123828 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
123829 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123830 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
123831 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
123832 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
123833 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123834 GIM_CheckIsSafeToFold, /*NumInsns*/1,
123835 // (vecreduce_add:{ *:[i16] } (AArch64saddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)) => (SADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn)
123836 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv16i8v),
123837 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
123838 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
123839 GIR_RootConstrainSelectedInstOperands,
123840 // GIR_Coverage, 5461,
123841 GIR_EraseRootFromParent_Done,
123842 // Label 6928: @338469
123843 GIM_Try, /*On fail goto*//*Label 6929*/ GIMT_Encode4(338511), // Rule ID 5449 //
123844 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
123845 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123846 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
123847 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
123848 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
123849 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123850 GIM_CheckIsSafeToFold, /*NumInsns*/1,
123851 // (vecreduce_add:{ *:[i16] } (AArch64uaddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)) => (UADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn)
123852 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i8v),
123853 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
123854 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
123855 GIR_RootConstrainSelectedInstOperands,
123856 // GIR_Coverage, 5449,
123857 GIR_EraseRootFromParent_Done,
123858 // Label 6929: @338511
123859 GIM_Try, /*On fail goto*//*Label 6930*/ GIMT_Encode4(338553), // Rule ID 5451 //
123860 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
123861 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123862 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
123863 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
123864 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
123865 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123866 GIM_CheckIsSafeToFold, /*NumInsns*/1,
123867 // (vecreduce_add:{ *:[i16] } (AArch64uaddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)) => (UADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn)
123868 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv16i8v),
123869 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
123870 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
123871 GIR_RootConstrainSelectedInstOperands,
123872 // GIR_Coverage, 5451,
123873 GIR_EraseRootFromParent_Done,
123874 // Label 6930: @338553
123875 GIM_Try, /*On fail goto*//*Label 6931*/ GIMT_Encode4(338576), // Rule ID 5509 //
123876 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
123877 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123878 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123879 // (vecreduce_add:{ *:[i16] } V64:{ *:[v4i16] }:$Rn) => (ADDVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
123880 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i16v),
123881 GIR_RootConstrainSelectedInstOperands,
123882 // GIR_Coverage, 5509,
123883 GIR_Done,
123884 // Label 6931: @338576
123885 GIM_Try, /*On fail goto*//*Label 6932*/ GIMT_Encode4(338599), // Rule ID 5510 //
123886 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
123887 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
123888 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123889 // (vecreduce_add:{ *:[i16] } V128:{ *:[v8i16] }:$Rn) => (ADDVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
123890 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i16v),
123891 GIR_RootConstrainSelectedInstOperands,
123892 // GIR_Coverage, 5510,
123893 GIR_Done,
123894 // Label 6932: @338599
123895 GIM_Reject,
123896 // Label 6918: @338600
123897 GIM_Try, /*On fail goto*//*Label 6933*/ GIMT_Encode4(338650), // Rule ID 5454 //
123898 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
123899 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
123900 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
123901 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
123902 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
123903 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
123904 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
123905 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123906 GIM_CheckIsSafeToFold, /*NumInsns*/1,
123907 // (vecreduce_add:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 687:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (UADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn)
123908 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i16v),
123909 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
123910 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
123911 GIR_RootConstrainSelectedInstOperands,
123912 // GIR_Coverage, 5454,
123913 GIR_EraseRootFromParent_Done,
123914 // Label 6933: @338650
123915 GIM_Try, /*On fail goto*//*Label 6934*/ GIMT_Encode4(338700), // Rule ID 5456 //
123916 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
123917 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
123918 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
123919 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
123920 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
123921 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
123922 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
123923 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123924 GIM_CheckIsSafeToFold, /*NumInsns*/1,
123925 // (vecreduce_add:{ *:[i32] } (intrinsic_wo_chain:{ *:[v2i32] } 687:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)) => (UADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn)
123926 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i16v),
123927 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
123928 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
123929 GIR_RootConstrainSelectedInstOperands,
123930 // GIR_Coverage, 5456,
123931 GIR_EraseRootFromParent_Done,
123932 // Label 6934: @338700
123933 GIM_Try, /*On fail goto*//*Label 6935*/ GIMT_Encode4(338750), // Rule ID 5464 //
123934 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
123935 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
123936 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
123937 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
123938 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
123939 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
123940 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
123941 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123942 GIM_CheckIsSafeToFold, /*NumInsns*/1,
123943 // (vecreduce_add:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 622:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)) => (SADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn)
123944 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i16v),
123945 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
123946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
123947 GIR_RootConstrainSelectedInstOperands,
123948 // GIR_Coverage, 5464,
123949 GIR_EraseRootFromParent_Done,
123950 // Label 6935: @338750
123951 GIM_Try, /*On fail goto*//*Label 6936*/ GIMT_Encode4(338800), // Rule ID 5466 //
123952 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
123953 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
123954 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
123955 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
123956 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
123957 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
123958 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
123959 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123960 GIM_CheckIsSafeToFold, /*NumInsns*/1,
123961 // (vecreduce_add:{ *:[i32] } (intrinsic_wo_chain:{ *:[v2i32] } 622:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)) => (SADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn)
123962 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i16v),
123963 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
123964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
123965 GIR_RootConstrainSelectedInstOperands,
123966 // GIR_Coverage, 5466,
123967 GIR_EraseRootFromParent_Done,
123968 // Label 6936: @338800
123969 GIM_Try, /*On fail goto*//*Label 6937*/ GIMT_Encode4(338842), // Rule ID 5463 //
123970 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
123971 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
123972 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
123973 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
123974 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
123975 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
123976 GIM_CheckIsSafeToFold, /*NumInsns*/1,
123977 // (vecreduce_add:{ *:[i32] } (AArch64saddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)) => (SADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn)
123978 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i16v),
123979 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
123980 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
123981 GIR_RootConstrainSelectedInstOperands,
123982 // GIR_Coverage, 5463,
123983 GIR_EraseRootFromParent_Done,
123984 // Label 6937: @338842
123985 GIM_Try, /*On fail goto*//*Label 6938*/ GIMT_Encode4(338884), // Rule ID 5465 //
123986 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
123987 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
123988 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
123989 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
123990 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
123991 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
123992 GIM_CheckIsSafeToFold, /*NumInsns*/1,
123993 // (vecreduce_add:{ *:[i32] } (AArch64saddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)) => (SADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn)
123994 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i16v),
123995 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
123996 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
123997 GIR_RootConstrainSelectedInstOperands,
123998 // GIR_Coverage, 5465,
123999 GIR_EraseRootFromParent_Done,
124000 // Label 6938: @338884
124001 GIM_Try, /*On fail goto*//*Label 6939*/ GIMT_Encode4(338926), // Rule ID 5453 //
124002 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
124003 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
124004 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
124005 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
124006 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
124007 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124008 GIM_CheckIsSafeToFold, /*NumInsns*/1,
124009 // (vecreduce_add:{ *:[i32] } (AArch64uaddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)) => (UADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn)
124010 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i16v),
124011 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
124012 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
124013 GIR_RootConstrainSelectedInstOperands,
124014 // GIR_Coverage, 5453,
124015 GIR_EraseRootFromParent_Done,
124016 // Label 6939: @338926
124017 GIM_Try, /*On fail goto*//*Label 6940*/ GIMT_Encode4(338968), // Rule ID 5455 //
124018 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
124019 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
124020 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
124021 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
124022 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
124023 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124024 GIM_CheckIsSafeToFold, /*NumInsns*/1,
124025 // (vecreduce_add:{ *:[i32] } (AArch64uaddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)) => (UADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn)
124026 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i16v),
124027 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
124028 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
124029 GIR_RootConstrainSelectedInstOperands,
124030 // GIR_Coverage, 5455,
124031 GIR_EraseRootFromParent_Done,
124032 // Label 6940: @338968
124033 GIM_Try, /*On fail goto*//*Label 6941*/ GIMT_Encode4(339029), // Rule ID 5511 //
124034 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
124035 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124036 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124037 // (vecreduce_add:{ *:[i32] } V64:{ *:[v2i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (ADDPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), ssub:{ *:[i32] })
124038 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
124039 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i32),
124040 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
124041 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
124042 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
124043 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
124044 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
124045 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
124046 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
124047 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
124048 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
124049 // GIR_Coverage, 5511,
124050 GIR_EraseRootFromParent_Done,
124051 // Label 6941: @339029
124052 GIM_Try, /*On fail goto*//*Label 6942*/ GIMT_Encode4(339052), // Rule ID 5512 //
124053 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
124054 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
124055 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124056 // (vecreduce_add:{ *:[i32] } V128:{ *:[v4i32] }:$Rn) => (ADDVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)
124057 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i32v),
124058 GIR_RootConstrainSelectedInstOperands,
124059 // GIR_Coverage, 5512,
124060 GIR_Done,
124061 // Label 6942: @339052
124062 GIM_Reject,
124063 // Label 6919: @339053
124064 GIM_Try, /*On fail goto*//*Label 6943*/ GIMT_Encode4(339238),
124065 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
124066 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124067 GIM_Try, /*On fail goto*//*Label 6944*/ GIMT_Encode4(339108), // Rule ID 5458 //
124068 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
124069 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
124070 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
124071 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
124072 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
124073 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124074 GIM_CheckIsSafeToFold, /*NumInsns*/1,
124075 // (vecreduce_add:{ *:[i64] } (intrinsic_wo_chain:{ *:[v2i64] } 687:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (UADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn)
124076 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i32v),
124077 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
124078 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
124079 GIR_RootConstrainSelectedInstOperands,
124080 // GIR_Coverage, 5458,
124081 GIR_EraseRootFromParent_Done,
124082 // Label 6944: @339108
124083 GIM_Try, /*On fail goto*//*Label 6945*/ GIMT_Encode4(339151), // Rule ID 5468 //
124084 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
124085 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
124086 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
124087 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
124088 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
124089 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124090 GIM_CheckIsSafeToFold, /*NumInsns*/1,
124091 // (vecreduce_add:{ *:[i64] } (intrinsic_wo_chain:{ *:[v2i64] } 622:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)) => (SADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn)
124092 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i32v),
124093 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
124094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
124095 GIR_RootConstrainSelectedInstOperands,
124096 // GIR_Coverage, 5468,
124097 GIR_EraseRootFromParent_Done,
124098 // Label 6945: @339151
124099 GIM_Try, /*On fail goto*//*Label 6946*/ GIMT_Encode4(339186), // Rule ID 5467 //
124100 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
124101 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
124102 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
124103 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124104 GIM_CheckIsSafeToFold, /*NumInsns*/1,
124105 // (vecreduce_add:{ *:[i64] } (AArch64saddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)) => (SADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn)
124106 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i32v),
124107 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
124108 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
124109 GIR_RootConstrainSelectedInstOperands,
124110 // GIR_Coverage, 5467,
124111 GIR_EraseRootFromParent_Done,
124112 // Label 6946: @339186
124113 GIM_Try, /*On fail goto*//*Label 6947*/ GIMT_Encode4(339221), // Rule ID 5457 //
124114 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
124115 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
124116 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
124117 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124118 GIM_CheckIsSafeToFold, /*NumInsns*/1,
124119 // (vecreduce_add:{ *:[i64] } (AArch64uaddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)) => (UADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn)
124120 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i32v),
124121 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
124122 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
124123 GIR_RootConstrainSelectedInstOperands,
124124 // GIR_Coverage, 5457,
124125 GIR_EraseRootFromParent_Done,
124126 // Label 6947: @339221
124127 GIM_Try, /*On fail goto*//*Label 6948*/ GIMT_Encode4(339237), // Rule ID 5513 //
124128 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124129 // (vecreduce_add:{ *:[i64] } V128:{ *:[v2i64] }:$Rn) => (ADDPv2i64p:{ *:[i64] } V128:{ *:[v2i64] }:$Rn)
124130 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64p),
124131 GIR_RootConstrainSelectedInstOperands,
124132 // GIR_Coverage, 5513,
124133 GIR_Done,
124134 // Label 6948: @339237
124135 GIM_Reject,
124136 // Label 6943: @339238
124137 GIM_Reject,
124138 // Label 6920: @339239
124139 GIM_Reject,
124140 // Label 105: @339240
124141 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 6952*/ GIMT_Encode4(339442),
124142 /*GILLT_s8*//*Label 6949*/ GIMT_Encode4(339263),
124143 /*GILLT_s16*//*Label 6950*/ GIMT_Encode4(339310),
124144 /*GILLT_s32*//*Label 6951*/ GIMT_Encode4(339357),
124145 // Label 6949: @339263
124146 GIM_Try, /*On fail goto*//*Label 6953*/ GIMT_Encode4(339286), // Rule ID 5604 //
124147 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
124148 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
124149 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124150 // (vecreduce_smax:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn) => (SMAXVv8i8v:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)
124151 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv8i8v),
124152 GIR_RootConstrainSelectedInstOperands,
124153 // GIR_Coverage, 5604,
124154 GIR_Done,
124155 // Label 6953: @339286
124156 GIM_Try, /*On fail goto*//*Label 6954*/ GIMT_Encode4(339309), // Rule ID 5605 //
124157 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
124158 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
124159 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124160 // (vecreduce_smax:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn) => (SMAXVv16i8v:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)
124161 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv16i8v),
124162 GIR_RootConstrainSelectedInstOperands,
124163 // GIR_Coverage, 5605,
124164 GIR_Done,
124165 // Label 6954: @339309
124166 GIM_Reject,
124167 // Label 6950: @339310
124168 GIM_Try, /*On fail goto*//*Label 6955*/ GIMT_Encode4(339333), // Rule ID 5606 //
124169 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
124170 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
124171 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124172 // (vecreduce_smax:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn) => (SMAXVv4i16v:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)
124173 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv4i16v),
124174 GIR_RootConstrainSelectedInstOperands,
124175 // GIR_Coverage, 5606,
124176 GIR_Done,
124177 // Label 6955: @339333
124178 GIM_Try, /*On fail goto*//*Label 6956*/ GIMT_Encode4(339356), // Rule ID 5607 //
124179 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
124180 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
124181 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124182 // (vecreduce_smax:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn) => (SMAXVv8i16v:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)
124183 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv8i16v),
124184 GIR_RootConstrainSelectedInstOperands,
124185 // GIR_Coverage, 5607,
124186 GIR_Done,
124187 // Label 6956: @339356
124188 GIM_Reject,
124189 // Label 6951: @339357
124190 GIM_Try, /*On fail goto*//*Label 6957*/ GIMT_Encode4(339380), // Rule ID 5608 //
124191 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
124192 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
124193 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124194 // (vecreduce_smax:{ *:[i32] } V128:{ *:[v4i32] }:$Rn) => (SMAXVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)
124195 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv4i32v),
124196 GIR_RootConstrainSelectedInstOperands,
124197 // GIR_Coverage, 5608,
124198 GIR_Done,
124199 // Label 6957: @339380
124200 GIM_Try, /*On fail goto*//*Label 6958*/ GIMT_Encode4(339441), // Rule ID 5609 //
124201 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
124202 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124203 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124204 // (vecreduce_smax:{ *:[i32] } V64:{ *:[v2i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (SMAXPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), ssub:{ *:[i32] })
124205 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
124206 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv2i32),
124207 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
124208 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
124209 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
124210 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
124211 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
124212 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
124213 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
124214 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
124215 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
124216 // GIR_Coverage, 5609,
124217 GIR_EraseRootFromParent_Done,
124218 // Label 6958: @339441
124219 GIM_Reject,
124220 // Label 6952: @339442
124221 GIM_Reject,
124222 // Label 106: @339443
124223 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 6962*/ GIMT_Encode4(339645),
124224 /*GILLT_s8*//*Label 6959*/ GIMT_Encode4(339466),
124225 /*GILLT_s16*//*Label 6960*/ GIMT_Encode4(339513),
124226 /*GILLT_s32*//*Label 6961*/ GIMT_Encode4(339560),
124227 // Label 6959: @339466
124228 GIM_Try, /*On fail goto*//*Label 6963*/ GIMT_Encode4(339489), // Rule ID 5598 //
124229 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
124230 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
124231 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124232 // (vecreduce_smin:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn) => (SMINVv8i8v:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)
124233 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINVv8i8v),
124234 GIR_RootConstrainSelectedInstOperands,
124235 // GIR_Coverage, 5598,
124236 GIR_Done,
124237 // Label 6963: @339489
124238 GIM_Try, /*On fail goto*//*Label 6964*/ GIMT_Encode4(339512), // Rule ID 5599 //
124239 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
124240 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
124241 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124242 // (vecreduce_smin:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn) => (SMINVv16i8v:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)
124243 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINVv16i8v),
124244 GIR_RootConstrainSelectedInstOperands,
124245 // GIR_Coverage, 5599,
124246 GIR_Done,
124247 // Label 6964: @339512
124248 GIM_Reject,
124249 // Label 6960: @339513
124250 GIM_Try, /*On fail goto*//*Label 6965*/ GIMT_Encode4(339536), // Rule ID 5600 //
124251 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
124252 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
124253 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124254 // (vecreduce_smin:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn) => (SMINVv4i16v:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)
124255 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINVv4i16v),
124256 GIR_RootConstrainSelectedInstOperands,
124257 // GIR_Coverage, 5600,
124258 GIR_Done,
124259 // Label 6965: @339536
124260 GIM_Try, /*On fail goto*//*Label 6966*/ GIMT_Encode4(339559), // Rule ID 5601 //
124261 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
124262 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
124263 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124264 // (vecreduce_smin:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn) => (SMINVv8i16v:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)
124265 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINVv8i16v),
124266 GIR_RootConstrainSelectedInstOperands,
124267 // GIR_Coverage, 5601,
124268 GIR_Done,
124269 // Label 6966: @339559
124270 GIM_Reject,
124271 // Label 6961: @339560
124272 GIM_Try, /*On fail goto*//*Label 6967*/ GIMT_Encode4(339583), // Rule ID 5602 //
124273 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
124274 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
124275 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124276 // (vecreduce_smin:{ *:[i32] } V128:{ *:[v4i32] }:$Rn) => (SMINVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)
124277 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINVv4i32v),
124278 GIR_RootConstrainSelectedInstOperands,
124279 // GIR_Coverage, 5602,
124280 GIR_Done,
124281 // Label 6967: @339583
124282 GIM_Try, /*On fail goto*//*Label 6968*/ GIMT_Encode4(339644), // Rule ID 5603 //
124283 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
124284 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124285 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124286 // (vecreduce_smin:{ *:[i32] } V64:{ *:[v2i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (SMINPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), ssub:{ *:[i32] })
124287 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
124288 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMINPv2i32),
124289 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
124290 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
124291 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
124292 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
124293 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
124294 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
124295 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
124296 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
124297 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
124298 // GIR_Coverage, 5603,
124299 GIR_EraseRootFromParent_Done,
124300 // Label 6968: @339644
124301 GIM_Reject,
124302 // Label 6962: @339645
124303 GIM_Reject,
124304 // Label 107: @339646
124305 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 6972*/ GIMT_Encode4(339848),
124306 /*GILLT_s8*//*Label 6969*/ GIMT_Encode4(339669),
124307 /*GILLT_s16*//*Label 6970*/ GIMT_Encode4(339716),
124308 /*GILLT_s32*//*Label 6971*/ GIMT_Encode4(339763),
124309 // Label 6969: @339669
124310 GIM_Try, /*On fail goto*//*Label 6973*/ GIMT_Encode4(339692), // Rule ID 5592 //
124311 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
124312 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
124313 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124314 // (vecreduce_umax:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn) => (UMAXVv8i8v:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)
124315 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv8i8v),
124316 GIR_RootConstrainSelectedInstOperands,
124317 // GIR_Coverage, 5592,
124318 GIR_Done,
124319 // Label 6973: @339692
124320 GIM_Try, /*On fail goto*//*Label 6974*/ GIMT_Encode4(339715), // Rule ID 5593 //
124321 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
124322 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
124323 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124324 // (vecreduce_umax:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn) => (UMAXVv16i8v:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)
124325 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv16i8v),
124326 GIR_RootConstrainSelectedInstOperands,
124327 // GIR_Coverage, 5593,
124328 GIR_Done,
124329 // Label 6974: @339715
124330 GIM_Reject,
124331 // Label 6970: @339716
124332 GIM_Try, /*On fail goto*//*Label 6975*/ GIMT_Encode4(339739), // Rule ID 5594 //
124333 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
124334 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
124335 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124336 // (vecreduce_umax:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn) => (UMAXVv4i16v:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)
124337 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv4i16v),
124338 GIR_RootConstrainSelectedInstOperands,
124339 // GIR_Coverage, 5594,
124340 GIR_Done,
124341 // Label 6975: @339739
124342 GIM_Try, /*On fail goto*//*Label 6976*/ GIMT_Encode4(339762), // Rule ID 5595 //
124343 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
124344 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
124345 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124346 // (vecreduce_umax:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn) => (UMAXVv8i16v:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)
124347 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv8i16v),
124348 GIR_RootConstrainSelectedInstOperands,
124349 // GIR_Coverage, 5595,
124350 GIR_Done,
124351 // Label 6976: @339762
124352 GIM_Reject,
124353 // Label 6971: @339763
124354 GIM_Try, /*On fail goto*//*Label 6977*/ GIMT_Encode4(339786), // Rule ID 5596 //
124355 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
124356 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
124357 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124358 // (vecreduce_umax:{ *:[i32] } V128:{ *:[v4i32] }:$Rn) => (UMAXVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)
124359 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv4i32v),
124360 GIR_RootConstrainSelectedInstOperands,
124361 // GIR_Coverage, 5596,
124362 GIR_Done,
124363 // Label 6977: @339786
124364 GIM_Try, /*On fail goto*//*Label 6978*/ GIMT_Encode4(339847), // Rule ID 5597 //
124365 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
124366 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124367 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124368 // (vecreduce_umax:{ *:[i32] } V64:{ *:[v2i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (UMAXPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), ssub:{ *:[i32] })
124369 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
124370 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv2i32),
124371 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
124372 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
124373 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
124374 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
124375 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
124376 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
124377 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
124378 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
124379 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
124380 // GIR_Coverage, 5597,
124381 GIR_EraseRootFromParent_Done,
124382 // Label 6978: @339847
124383 GIM_Reject,
124384 // Label 6972: @339848
124385 GIM_Reject,
124386 // Label 108: @339849
124387 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 6982*/ GIMT_Encode4(340051),
124388 /*GILLT_s8*//*Label 6979*/ GIMT_Encode4(339872),
124389 /*GILLT_s16*//*Label 6980*/ GIMT_Encode4(339919),
124390 /*GILLT_s32*//*Label 6981*/ GIMT_Encode4(339966),
124391 // Label 6979: @339872
124392 GIM_Try, /*On fail goto*//*Label 6983*/ GIMT_Encode4(339895), // Rule ID 5586 //
124393 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
124394 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
124395 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124396 // (vecreduce_umin:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn) => (UMINVv8i8v:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)
124397 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINVv8i8v),
124398 GIR_RootConstrainSelectedInstOperands,
124399 // GIR_Coverage, 5586,
124400 GIR_Done,
124401 // Label 6983: @339895
124402 GIM_Try, /*On fail goto*//*Label 6984*/ GIMT_Encode4(339918), // Rule ID 5587 //
124403 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
124404 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
124405 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124406 // (vecreduce_umin:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn) => (UMINVv16i8v:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)
124407 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINVv16i8v),
124408 GIR_RootConstrainSelectedInstOperands,
124409 // GIR_Coverage, 5587,
124410 GIR_Done,
124411 // Label 6984: @339918
124412 GIM_Reject,
124413 // Label 6980: @339919
124414 GIM_Try, /*On fail goto*//*Label 6985*/ GIMT_Encode4(339942), // Rule ID 5588 //
124415 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
124416 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
124417 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124418 // (vecreduce_umin:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn) => (UMINVv4i16v:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)
124419 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINVv4i16v),
124420 GIR_RootConstrainSelectedInstOperands,
124421 // GIR_Coverage, 5588,
124422 GIR_Done,
124423 // Label 6985: @339942
124424 GIM_Try, /*On fail goto*//*Label 6986*/ GIMT_Encode4(339965), // Rule ID 5589 //
124425 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
124426 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
124427 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124428 // (vecreduce_umin:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn) => (UMINVv8i16v:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)
124429 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINVv8i16v),
124430 GIR_RootConstrainSelectedInstOperands,
124431 // GIR_Coverage, 5589,
124432 GIR_Done,
124433 // Label 6986: @339965
124434 GIM_Reject,
124435 // Label 6981: @339966
124436 GIM_Try, /*On fail goto*//*Label 6987*/ GIMT_Encode4(339989), // Rule ID 5590 //
124437 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
124438 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
124439 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124440 // (vecreduce_umin:{ *:[i32] } V128:{ *:[v4i32] }:$Rn) => (UMINVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)
124441 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINVv4i32v),
124442 GIR_RootConstrainSelectedInstOperands,
124443 // GIR_Coverage, 5590,
124444 GIR_Done,
124445 // Label 6987: @339989
124446 GIM_Try, /*On fail goto*//*Label 6988*/ GIMT_Encode4(340050), // Rule ID 5591 //
124447 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
124448 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124449 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124450 // (vecreduce_umin:{ *:[i32] } V64:{ *:[v2i32] }:$Rn) => (EXTRACT_SUBREG:{ *:[i32] } (UMINPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), ssub:{ *:[i32] })
124451 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
124452 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMINPv2i32),
124453 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
124454 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
124455 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
124456 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
124457 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
124458 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
124459 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
124460 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
124461 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
124462 // GIR_Coverage, 5591,
124463 GIR_EraseRootFromParent_Done,
124464 // Label 6988: @340050
124465 GIM_Reject,
124466 // Label 6982: @340051
124467 GIM_Reject,
124468 // Label 109: @340052
124469 GIM_Try, /*On fail goto*//*Label 6989*/ GIMT_Encode4(340191),
124470 GIM_CheckIsImm, /*MI*/0, /*Op*/0,
124471 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
124472 GIM_Try, /*On fail goto*//*Label 6990*/ GIMT_Encode4(340098), // Rule ID 267 //
124473 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
124474 // (AArch64Prefetch (timm:{ *:[i32] }):$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)) => (PRFMroW (timm:{ *:[i32] }):$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
124475 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFMroW),
124476 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
124477 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
124478 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
124479 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
124480 GIR_RootConstrainSelectedInstOperands,
124481 // GIR_Coverage, 267,
124482 GIR_EraseRootFromParent_Done,
124483 // Label 6990: @340098
124484 GIM_Try, /*On fail goto*//*Label 6991*/ GIMT_Encode4(340132), // Rule ID 268 //
124485 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
124486 // (AArch64Prefetch (timm:{ *:[i32] }):$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)) => (PRFMroX (timm:{ *:[i32] }):$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
124487 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFMroX),
124488 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
124489 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
124490 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
124491 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
124492 GIR_RootConstrainSelectedInstOperands,
124493 // GIR_Coverage, 268,
124494 GIR_EraseRootFromParent_Done,
124495 // Label 6991: @340132
124496 GIM_Try, /*On fail goto*//*Label 6992*/ GIMT_Encode4(340161), // Rule ID 283 //
124497 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
124498 // (AArch64Prefetch (timm:{ *:[i32] }):$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)) => (PRFMui (timm:{ *:[i32] }):$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
124499 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFMui),
124500 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
124501 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
124502 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
124503 GIR_RootConstrainSelectedInstOperands,
124504 // GIR_Coverage, 283,
124505 GIR_EraseRootFromParent_Done,
124506 // Label 6992: @340161
124507 GIM_Try, /*On fail goto*//*Label 6993*/ GIMT_Encode4(340190), // Rule ID 304 //
124508 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
124509 // (AArch64Prefetch (timm:{ *:[i32] }):$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)) => (PRFUMi (timm:{ *:[i32] }):$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
124510 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFUMi),
124511 GIR_RootToRootCopy, /*OpIdx*/0, // Rt
124512 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
124513 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
124514 GIR_RootConstrainSelectedInstOperands,
124515 // GIR_Coverage, 304,
124516 GIR_EraseRootFromParent_Done,
124517 // Label 6993: @340190
124518 GIM_Reject,
124519 // Label 6989: @340191
124520 GIM_Reject,
124521 // Label 110: @340192
124522 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(24), /*)*//*default:*//*Label 7006*/ GIMT_Encode4(340731),
124523 /*GILLT_s64*//*Label 6994*/ GIMT_Encode4(340287), GIMT_Encode4(0),
124524 /*GILLT_v2s32*//*Label 6995*/ GIMT_Encode4(340325),
124525 /*GILLT_v2s64*//*Label 6996*/ GIMT_Encode4(340363),
124526 /*GILLT_v4s16*//*Label 6997*/ GIMT_Encode4(340401),
124527 /*GILLT_v4s32*//*Label 6998*/ GIMT_Encode4(340439),
124528 /*GILLT_v8s8*//*Label 6999*/ GIMT_Encode4(340477),
124529 /*GILLT_v8s16*//*Label 7000*/ GIMT_Encode4(340515),
124530 /*GILLT_v16s8*//*Label 7001*/ GIMT_Encode4(340553), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
124531 /*GILLT_nxv2s64*//*Label 7002*/ GIMT_Encode4(340591), GIMT_Encode4(0), GIMT_Encode4(0),
124532 /*GILLT_nxv4s32*//*Label 7003*/ GIMT_Encode4(340626), GIMT_Encode4(0),
124533 /*GILLT_nxv8s16*//*Label 7004*/ GIMT_Encode4(340661), GIMT_Encode4(0),
124534 /*GILLT_nxv16s8*//*Label 7005*/ GIMT_Encode4(340696),
124535 // Label 6994: @340287
124536 GIM_Try, /*On fail goto*//*Label 7007*/ GIMT_Encode4(340324), // Rule ID 4717 //
124537 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
124538 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
124539 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
124540 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124541 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124542 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124543 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124544 // (AArch64bsp:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v1i64] }:$Rn, V64:{ *:[v1i64] }:$Rm) => (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v1i64] }:$Rn, V64:{ *:[v1i64] }:$Rm)
124545 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
124546 GIR_RootConstrainSelectedInstOperands,
124547 // GIR_Coverage, 4717,
124548 GIR_Done,
124549 // Label 7007: @340324
124550 GIM_Reject,
124551 // Label 6995: @340325
124552 GIM_Try, /*On fail goto*//*Label 7008*/ GIMT_Encode4(340362), // Rule ID 4716 //
124553 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
124554 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
124555 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
124556 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124557 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124558 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124559 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124560 // (AArch64bsp:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
124561 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
124562 GIR_RootConstrainSelectedInstOperands,
124563 // GIR_Coverage, 4716,
124564 GIR_Done,
124565 // Label 7008: @340362
124566 GIM_Reject,
124567 // Label 6996: @340363
124568 GIM_Try, /*On fail goto*//*Label 7009*/ GIMT_Encode4(340400), // Rule ID 4721 //
124569 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
124570 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
124571 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
124572 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124573 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124574 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124575 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124576 // (AArch64bsp:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
124577 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
124578 GIR_RootConstrainSelectedInstOperands,
124579 // GIR_Coverage, 4721,
124580 GIR_Done,
124581 // Label 7009: @340400
124582 GIM_Reject,
124583 // Label 6997: @340401
124584 GIM_Try, /*On fail goto*//*Label 7010*/ GIMT_Encode4(340438), // Rule ID 4715 //
124585 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
124586 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
124587 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
124588 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124589 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124590 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124591 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124592 // (AArch64bsp:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
124593 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
124594 GIR_RootConstrainSelectedInstOperands,
124595 // GIR_Coverage, 4715,
124596 GIR_Done,
124597 // Label 7010: @340438
124598 GIM_Reject,
124599 // Label 6998: @340439
124600 GIM_Try, /*On fail goto*//*Label 7011*/ GIMT_Encode4(340476), // Rule ID 4720 //
124601 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
124602 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
124603 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
124604 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124605 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124606 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124607 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124608 // (AArch64bsp:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
124609 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
124610 GIR_RootConstrainSelectedInstOperands,
124611 // GIR_Coverage, 4720,
124612 GIR_Done,
124613 // Label 7011: @340476
124614 GIM_Reject,
124615 // Label 6999: @340477
124616 GIM_Try, /*On fail goto*//*Label 7012*/ GIMT_Encode4(340514), // Rule ID 4714 //
124617 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
124618 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
124619 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
124620 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124621 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124622 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124623 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124624 // (AArch64bsp:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
124625 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
124626 GIR_RootConstrainSelectedInstOperands,
124627 // GIR_Coverage, 4714,
124628 GIR_Done,
124629 // Label 7012: @340514
124630 GIM_Reject,
124631 // Label 7000: @340515
124632 GIM_Try, /*On fail goto*//*Label 7013*/ GIMT_Encode4(340552), // Rule ID 4719 //
124633 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
124634 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
124635 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
124636 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124637 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124638 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124639 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124640 // (AArch64bsp:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
124641 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
124642 GIR_RootConstrainSelectedInstOperands,
124643 // GIR_Coverage, 4719,
124644 GIR_Done,
124645 // Label 7013: @340552
124646 GIM_Reject,
124647 // Label 7001: @340553
124648 GIM_Try, /*On fail goto*//*Label 7014*/ GIMT_Encode4(340590), // Rule ID 4718 //
124649 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
124650 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
124651 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
124652 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124653 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124654 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124655 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124656 // (AArch64bsp:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
124657 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
124658 GIR_RootConstrainSelectedInstOperands,
124659 // GIR_Coverage, 4718,
124660 GIR_Done,
124661 // Label 7014: @340590
124662 GIM_Reject,
124663 // Label 7002: @340591
124664 GIM_Try, /*On fail goto*//*Label 7015*/ GIMT_Encode4(340625), // Rule ID 11540 //
124665 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
124666 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
124667 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
124668 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
124669 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
124670 // (AArch64bsp:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
124671 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
124672 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
124673 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
124674 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
124675 GIR_RootToRootCopy, /*OpIdx*/1, // Op3
124676 GIR_RootConstrainSelectedInstOperands,
124677 // GIR_Coverage, 11540,
124678 GIR_EraseRootFromParent_Done,
124679 // Label 7015: @340625
124680 GIM_Reject,
124681 // Label 7003: @340626
124682 GIM_Try, /*On fail goto*//*Label 7016*/ GIMT_Encode4(340660), // Rule ID 11538 //
124683 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
124684 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
124685 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
124686 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
124687 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
124688 // (AArch64bsp:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
124689 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
124690 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
124691 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
124692 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
124693 GIR_RootToRootCopy, /*OpIdx*/1, // Op3
124694 GIR_RootConstrainSelectedInstOperands,
124695 // GIR_Coverage, 11538,
124696 GIR_EraseRootFromParent_Done,
124697 // Label 7016: @340660
124698 GIM_Reject,
124699 // Label 7004: @340661
124700 GIM_Try, /*On fail goto*//*Label 7017*/ GIMT_Encode4(340695), // Rule ID 11536 //
124701 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
124702 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
124703 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
124704 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
124705 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
124706 // (AArch64bsp:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
124707 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
124708 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
124709 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
124710 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
124711 GIR_RootToRootCopy, /*OpIdx*/1, // Op3
124712 GIR_RootConstrainSelectedInstOperands,
124713 // GIR_Coverage, 11536,
124714 GIR_EraseRootFromParent_Done,
124715 // Label 7017: @340695
124716 GIM_Reject,
124717 // Label 7005: @340696
124718 GIM_Try, /*On fail goto*//*Label 7018*/ GIMT_Encode4(340730), // Rule ID 11534 //
124719 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2orSME),
124720 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
124721 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
124722 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
124723 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
124724 // (AArch64bsp:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
124725 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
124726 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
124727 GIR_RootToRootCopy, /*OpIdx*/2, // Op1
124728 GIR_RootToRootCopy, /*OpIdx*/3, // Op2
124729 GIR_RootToRootCopy, /*OpIdx*/1, // Op3
124730 GIR_RootConstrainSelectedInstOperands,
124731 // GIR_Coverage, 11534,
124732 GIR_EraseRootFromParent_Done,
124733 // Label 7018: @340730
124734 GIM_Reject,
124735 // Label 7006: @340731
124736 GIM_Reject,
124737 // Label 111: @340732
124738 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(12), /*)*//*default:*//*Label 7027*/ GIMT_Encode4(342822),
124739 /*GILLT_s64*//*Label 7019*/ GIMT_Encode4(340779), GIMT_Encode4(0),
124740 /*GILLT_v2s32*//*Label 7020*/ GIMT_Encode4(340974),
124741 /*GILLT_v2s64*//*Label 7021*/ GIMT_Encode4(341221),
124742 /*GILLT_v4s16*//*Label 7022*/ GIMT_Encode4(341468),
124743 /*GILLT_v4s32*//*Label 7023*/ GIMT_Encode4(341878),
124744 /*GILLT_v8s8*//*Label 7024*/ GIMT_Encode4(342125),
124745 /*GILLT_v8s16*//*Label 7025*/ GIMT_Encode4(342270),
124746 /*GILLT_v16s8*//*Label 7026*/ GIMT_Encode4(342680),
124747 // Label 7019: @340779
124748 GIM_Try, /*On fail goto*//*Label 7028*/ GIMT_Encode4(340973),
124749 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
124750 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124751 GIM_Try, /*On fail goto*//*Label 7029*/ GIMT_Encode4(340838), // Rule ID 6013 //
124752 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
124753 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
124754 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
124755 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
124756 // MIs[1] Rn
124757 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
124758 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
124759 GIM_CheckIsSafeToFold, /*NumInsns*/1,
124760 // (AArch64dup:{ *:[v1i64] } (ld:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv1d:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn)
124761 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv1d),
124762 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
124763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
124764 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
124765 GIR_RootConstrainSelectedInstOperands,
124766 // GIR_Coverage, 6013,
124767 GIR_EraseRootFromParent_Done,
124768 // Label 7029: @340838
124769 GIM_Try, /*On fail goto*//*Label 7030*/ GIMT_Encode4(340885), // Rule ID 6024 //
124770 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
124771 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
124772 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
124773 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
124774 // MIs[1] Rn
124775 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
124776 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
124777 GIM_CheckIsSafeToFold, /*NumInsns*/1,
124778 // (AArch64dup:{ *:[v1f64] } (ld:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv1d:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn)
124779 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv1d),
124780 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
124781 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
124782 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
124783 GIR_RootConstrainSelectedInstOperands,
124784 // GIR_Coverage, 6024,
124785 GIR_EraseRootFromParent_Done,
124786 // Label 7030: @340885
124787 GIM_Try, /*On fail goto*//*Label 7031*/ GIMT_Encode4(340932), // Rule ID 12449 //
124788 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
124789 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
124790 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
124791 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
124792 // MIs[1] Rn
124793 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
124794 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
124795 GIM_CheckIsSafeToFold, /*NumInsns*/1,
124796 // (AArch64dup:{ *:[v1i64] } (ld:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv1d:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn)
124797 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv1d),
124798 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
124799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
124800 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
124801 GIR_RootConstrainSelectedInstOperands,
124802 // GIR_Coverage, 12449,
124803 GIR_EraseRootFromParent_Done,
124804 // Label 7031: @340932
124805 GIM_Try, /*On fail goto*//*Label 7032*/ GIMT_Encode4(340952), // Rule ID 5266 //
124806 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
124807 // (AArch64dup:{ *:[v1i64] } GPR64:{ *:[i64] }:$Rn) => (COPY_TO_REGCLASS:{ *:[v1i64] } GPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i32] })
124808 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
124809 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
124810 // GIR_Coverage, 5266,
124811 GIR_Done,
124812 // Label 7032: @340952
124813 GIM_Try, /*On fail goto*//*Label 7033*/ GIMT_Encode4(340972), // Rule ID 5267 //
124814 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124815 // (AArch64dup:{ *:[v1f64] } FPR64:{ *:[f64] }:$Rn) => (COPY_TO_REGCLASS:{ *:[v1f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[i32] })
124816 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
124817 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
124818 // GIR_Coverage, 5267,
124819 GIR_Done,
124820 // Label 7033: @340972
124821 GIM_Reject,
124822 // Label 7028: @340973
124823 GIM_Reject,
124824 // Label 7020: @340974
124825 GIM_Try, /*On fail goto*//*Label 7034*/ GIMT_Encode4(341220),
124826 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
124827 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124828 GIM_Try, /*On fail goto*//*Label 7035*/ GIMT_Encode4(341033), // Rule ID 6010 //
124829 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
124830 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
124831 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
124832 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
124833 // MIs[1] Rn
124834 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
124835 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
124836 GIM_CheckIsSafeToFold, /*NumInsns*/1,
124837 // (AArch64dup:{ *:[v2i32] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv2s:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn)
124838 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2s),
124839 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
124840 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
124841 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
124842 GIR_RootConstrainSelectedInstOperands,
124843 // GIR_Coverage, 6010,
124844 GIR_EraseRootFromParent_Done,
124845 // Label 7035: @341033
124846 GIM_Try, /*On fail goto*//*Label 7036*/ GIMT_Encode4(341080), // Rule ID 6021 //
124847 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
124848 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
124849 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
124850 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
124851 // MIs[1] Rn
124852 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
124853 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
124854 GIM_CheckIsSafeToFold, /*NumInsns*/1,
124855 // (AArch64dup:{ *:[v2f32] } (ld:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv2s:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn)
124856 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2s),
124857 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
124858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
124859 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
124860 GIR_RootConstrainSelectedInstOperands,
124861 // GIR_Coverage, 6021,
124862 GIR_EraseRootFromParent_Done,
124863 // Label 7036: @341080
124864 GIM_Try, /*On fail goto*//*Label 7037*/ GIMT_Encode4(341127), // Rule ID 12446 //
124865 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
124866 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
124867 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
124868 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
124869 // MIs[1] Rn
124870 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
124871 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
124872 GIM_CheckIsSafeToFold, /*NumInsns*/1,
124873 // (AArch64dup:{ *:[v2i32] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv2s:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn)
124874 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2s),
124875 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
124876 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
124877 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
124878 GIR_RootConstrainSelectedInstOperands,
124879 // GIR_Coverage, 12446,
124880 GIR_EraseRootFromParent_Done,
124881 // Label 7037: @341127
124882 GIM_Try, /*On fail goto*//*Label 7038*/ GIMT_Encode4(341146), // Rule ID 1903 //
124883 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
124884 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
124885 // (AArch64dup:{ *:[v2i32] } GPR32:{ *:[i32] }:$Rn) => (DUPv2i32gpr:{ *:[v2i32] } GPR32:{ *:[i32] }:$Rn)
124886 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i32gpr),
124887 GIR_RootConstrainSelectedInstOperands,
124888 // GIR_Coverage, 1903,
124889 GIR_Done,
124890 // Label 7038: @341146
124891 GIM_Try, /*On fail goto*//*Label 7039*/ GIMT_Encode4(341219), // Rule ID 5268 //
124892 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
124893 // (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rn) => (DUPv2i32lane:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rn, ssub:{ *:[i32] }), 0:{ *:[i64] })
124894 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
124895 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
124896 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
124897 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
124898 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
124899 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
124900 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
124901 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
124902 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
124903 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
124904 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
124905 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
124906 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
124907 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i32lane),
124908 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
124909 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
124910 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
124911 GIR_RootConstrainSelectedInstOperands,
124912 // GIR_Coverage, 5268,
124913 GIR_EraseRootFromParent_Done,
124914 // Label 7039: @341219
124915 GIM_Reject,
124916 // Label 7034: @341220
124917 GIM_Reject,
124918 // Label 7021: @341221
124919 GIM_Try, /*On fail goto*//*Label 7040*/ GIMT_Encode4(341467),
124920 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
124921 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
124922 GIM_Try, /*On fail goto*//*Label 7041*/ GIMT_Encode4(341280), // Rule ID 6012 //
124923 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
124924 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
124925 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
124926 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
124927 // MIs[1] Rn
124928 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
124929 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
124930 GIM_CheckIsSafeToFold, /*NumInsns*/1,
124931 // (AArch64dup:{ *:[v2i64] } (ld:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv2d:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)
124932 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2d),
124933 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
124934 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
124935 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
124936 GIR_RootConstrainSelectedInstOperands,
124937 // GIR_Coverage, 6012,
124938 GIR_EraseRootFromParent_Done,
124939 // Label 7041: @341280
124940 GIM_Try, /*On fail goto*//*Label 7042*/ GIMT_Encode4(341327), // Rule ID 6023 //
124941 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
124942 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
124943 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
124944 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
124945 // MIs[1] Rn
124946 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
124947 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
124948 GIM_CheckIsSafeToFold, /*NumInsns*/1,
124949 // (AArch64dup:{ *:[v2f64] } (ld:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv2d:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn)
124950 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2d),
124951 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
124952 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
124953 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
124954 GIR_RootConstrainSelectedInstOperands,
124955 // GIR_Coverage, 6023,
124956 GIR_EraseRootFromParent_Done,
124957 // Label 7042: @341327
124958 GIM_Try, /*On fail goto*//*Label 7043*/ GIMT_Encode4(341374), // Rule ID 12448 //
124959 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
124960 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
124961 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
124962 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
124963 // MIs[1] Rn
124964 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
124965 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
124966 GIM_CheckIsSafeToFold, /*NumInsns*/1,
124967 // (AArch64dup:{ *:[v2i64] } (ld:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv2d:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)
124968 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2d),
124969 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
124970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
124971 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
124972 GIR_RootConstrainSelectedInstOperands,
124973 // GIR_Coverage, 12448,
124974 GIR_EraseRootFromParent_Done,
124975 // Label 7043: @341374
124976 GIM_Try, /*On fail goto*//*Label 7044*/ GIMT_Encode4(341393), // Rule ID 1905 //
124977 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
124978 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
124979 // (AArch64dup:{ *:[v2i64] } GPR64:{ *:[i64] }:$Rn) => (DUPv2i64gpr:{ *:[v2i64] } GPR64:{ *:[i64] }:$Rn)
124980 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64gpr),
124981 GIR_RootConstrainSelectedInstOperands,
124982 // GIR_Coverage, 1905,
124983 GIR_Done,
124984 // Label 7044: @341393
124985 GIM_Try, /*On fail goto*//*Label 7045*/ GIMT_Encode4(341466), // Rule ID 5270 //
124986 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
124987 // (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rn) => (DUPv2i64lane:{ *:[v2f64] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
124988 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
124989 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
124990 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
124991 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
124992 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
124993 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
124994 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
124995 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
124996 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
124997 GIR_AddImm8, /*InsnID*/1, /*Imm*/2,
124998 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
124999 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
125000 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
125001 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64lane),
125002 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125003 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
125004 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
125005 GIR_RootConstrainSelectedInstOperands,
125006 // GIR_Coverage, 5270,
125007 GIR_EraseRootFromParent_Done,
125008 // Label 7045: @341466
125009 GIM_Reject,
125010 // Label 7040: @341467
125011 GIM_Reject,
125012 // Label 7022: @341468
125013 GIM_Try, /*On fail goto*//*Label 7046*/ GIMT_Encode4(341522), // Rule ID 6025 //
125014 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
125015 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
125016 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
125017 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
125018 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
125019 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
125020 // MIs[1] Rn
125021 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
125022 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
125023 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125024 // (AArch64dup:{ *:[v4f16] } (ld:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv4h:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn)
125025 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4h),
125026 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
125027 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
125028 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
125029 GIR_RootConstrainSelectedInstOperands,
125030 // GIR_Coverage, 6025,
125031 GIR_EraseRootFromParent_Done,
125032 // Label 7046: @341522
125033 GIM_Try, /*On fail goto*//*Label 7047*/ GIMT_Encode4(341576), // Rule ID 6027 //
125034 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
125035 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
125036 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
125037 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
125038 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
125039 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
125040 // MIs[1] Rn
125041 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
125042 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
125043 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125044 // (AArch64dup:{ *:[v4bf16] } (ld:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv4h:{ *:[v4bf16] } GPR64sp:{ *:[i64] }:$Rn)
125045 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4h),
125046 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
125047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
125048 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
125049 GIR_RootConstrainSelectedInstOperands,
125050 // GIR_Coverage, 6027,
125051 GIR_EraseRootFromParent_Done,
125052 // Label 7047: @341576
125053 GIM_Try, /*On fail goto*//*Label 7048*/ GIMT_Encode4(341630), // Rule ID 12444 //
125054 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
125055 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
125056 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
125057 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
125058 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
125059 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
125060 // MIs[1] Rn
125061 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
125062 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
125063 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125064 // (AArch64dup:{ *:[v4i16] } (ld:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv4h:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn)
125065 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4h),
125066 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
125067 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
125068 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
125069 GIR_RootConstrainSelectedInstOperands,
125070 // GIR_Coverage, 12444,
125071 GIR_EraseRootFromParent_Done,
125072 // Label 7048: @341630
125073 GIM_Try, /*On fail goto*//*Label 7049*/ GIMT_Encode4(341691), // Rule ID 6008 //
125074 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
125075 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
125076 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
125077 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
125078 GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
125079 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
125080 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
125081 // MIs[1] Rn
125082 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
125083 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
125084 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125085 // (AArch64dup:{ *:[v4i16] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>) => (LD1Rv4h:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn)
125086 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4h),
125087 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
125088 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
125089 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
125090 GIR_RootConstrainSelectedInstOperands,
125091 // GIR_Coverage, 6008,
125092 GIR_EraseRootFromParent_Done,
125093 // Label 7049: @341691
125094 GIM_Try, /*On fail goto*//*Label 7050*/ GIMT_Encode4(341717), // Rule ID 1901 //
125095 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
125096 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
125097 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
125098 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
125099 // (AArch64dup:{ *:[v4i16] } GPR32:{ *:[i32] }:$Rn) => (DUPv4i16gpr:{ *:[v4i16] } GPR32:{ *:[i32] }:$Rn)
125100 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i16gpr),
125101 GIR_RootConstrainSelectedInstOperands,
125102 // GIR_Coverage, 1901,
125103 GIR_Done,
125104 // Label 7050: @341717
125105 GIM_Try, /*On fail goto*//*Label 7051*/ GIMT_Encode4(341797), // Rule ID 5271 //
125106 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
125107 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
125108 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
125109 // (AArch64dup:{ *:[v4f16] } FPR16:{ *:[f16] }:$Rn) => (DUPv4i16lane:{ *:[v4f16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] }), 0:{ *:[i64] })
125110 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
125111 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
125112 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
125113 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
125114 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
125115 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
125116 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
125117 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
125118 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
125119 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
125120 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
125121 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
125122 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
125123 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i16lane),
125124 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125125 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
125126 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
125127 GIR_RootConstrainSelectedInstOperands,
125128 // GIR_Coverage, 5271,
125129 GIR_EraseRootFromParent_Done,
125130 // Label 7051: @341797
125131 GIM_Try, /*On fail goto*//*Label 7052*/ GIMT_Encode4(341877), // Rule ID 5272 //
125132 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
125133 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
125134 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
125135 // (AArch64dup:{ *:[v4bf16] } FPR16:{ *:[bf16] }:$Rn) => (DUPv4i16lane:{ *:[v4bf16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), FPR16:{ *:[bf16] }:$Rn, hsub:{ *:[i32] }), 0:{ *:[i64] })
125136 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
125137 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
125138 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
125139 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
125140 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
125141 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
125142 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
125143 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
125144 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
125145 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
125146 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
125147 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
125148 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
125149 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i16lane),
125150 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125151 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
125152 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
125153 GIR_RootConstrainSelectedInstOperands,
125154 // GIR_Coverage, 5272,
125155 GIR_EraseRootFromParent_Done,
125156 // Label 7052: @341877
125157 GIM_Reject,
125158 // Label 7023: @341878
125159 GIM_Try, /*On fail goto*//*Label 7053*/ GIMT_Encode4(342124),
125160 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
125161 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125162 GIM_Try, /*On fail goto*//*Label 7054*/ GIMT_Encode4(341937), // Rule ID 6011 //
125163 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
125164 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
125165 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
125166 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
125167 // MIs[1] Rn
125168 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
125169 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
125170 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125171 // (AArch64dup:{ *:[v4i32] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv4s:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)
125172 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4s),
125173 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
125174 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
125175 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
125176 GIR_RootConstrainSelectedInstOperands,
125177 // GIR_Coverage, 6011,
125178 GIR_EraseRootFromParent_Done,
125179 // Label 7054: @341937
125180 GIM_Try, /*On fail goto*//*Label 7055*/ GIMT_Encode4(341984), // Rule ID 6022 //
125181 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
125182 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
125183 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
125184 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
125185 // MIs[1] Rn
125186 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
125187 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
125188 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125189 // (AArch64dup:{ *:[v4f32] } (ld:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv4s:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn)
125190 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4s),
125191 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
125192 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
125193 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
125194 GIR_RootConstrainSelectedInstOperands,
125195 // GIR_Coverage, 6022,
125196 GIR_EraseRootFromParent_Done,
125197 // Label 7055: @341984
125198 GIM_Try, /*On fail goto*//*Label 7056*/ GIMT_Encode4(342031), // Rule ID 12447 //
125199 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
125200 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
125201 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
125202 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
125203 // MIs[1] Rn
125204 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
125205 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
125206 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125207 // (AArch64dup:{ *:[v4i32] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv4s:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)
125208 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4s),
125209 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
125210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
125211 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
125212 GIR_RootConstrainSelectedInstOperands,
125213 // GIR_Coverage, 12447,
125214 GIR_EraseRootFromParent_Done,
125215 // Label 7056: @342031
125216 GIM_Try, /*On fail goto*//*Label 7057*/ GIMT_Encode4(342050), // Rule ID 1904 //
125217 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
125218 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
125219 // (AArch64dup:{ *:[v4i32] } GPR32:{ *:[i32] }:$Rn) => (DUPv4i32gpr:{ *:[v4i32] } GPR32:{ *:[i32] }:$Rn)
125220 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i32gpr),
125221 GIR_RootConstrainSelectedInstOperands,
125222 // GIR_Coverage, 1904,
125223 GIR_Done,
125224 // Label 7057: @342050
125225 GIM_Try, /*On fail goto*//*Label 7058*/ GIMT_Encode4(342123), // Rule ID 5269 //
125226 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
125227 // (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rn) => (DUPv4i32lane:{ *:[v4f32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rn, ssub:{ *:[i32] }), 0:{ *:[i64] })
125228 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
125229 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
125230 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
125231 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
125232 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
125233 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
125234 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
125235 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
125236 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
125237 GIR_AddImm8, /*InsnID*/1, /*Imm*/15,
125238 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
125239 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
125240 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
125241 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i32lane),
125242 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125243 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
125244 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
125245 GIR_RootConstrainSelectedInstOperands,
125246 // GIR_Coverage, 5269,
125247 GIR_EraseRootFromParent_Done,
125248 // Label 7058: @342123
125249 GIM_Reject,
125250 // Label 7053: @342124
125251 GIM_Reject,
125252 // Label 7024: @342125
125253 GIM_Try, /*On fail goto*//*Label 7059*/ GIMT_Encode4(342182), // Rule ID 12442 //
125254 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
125255 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
125256 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
125257 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
125258 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
125259 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
125260 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
125261 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125262 GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
125263 // (AArch64dup:{ *:[v8i8] } (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn))<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv8b:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn)
125264 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv8b),
125265 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
125266 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
125267 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
125268 GIR_RootConstrainSelectedInstOperands,
125269 // GIR_Coverage, 12442,
125270 GIR_EraseRootFromParent_Done,
125271 // Label 7059: @342182
125272 GIM_Try, /*On fail goto*//*Label 7060*/ GIMT_Encode4(342243), // Rule ID 6006 //
125273 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
125274 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
125275 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
125276 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
125277 GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
125278 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
125279 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
125280 // MIs[1] Rn
125281 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
125282 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
125283 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125284 // (AArch64dup:{ *:[v8i8] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>) => (LD1Rv8b:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn)
125285 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv8b),
125286 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
125287 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
125288 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
125289 GIR_RootConstrainSelectedInstOperands,
125290 // GIR_Coverage, 6006,
125291 GIR_EraseRootFromParent_Done,
125292 // Label 7060: @342243
125293 GIM_Try, /*On fail goto*//*Label 7061*/ GIMT_Encode4(342269), // Rule ID 1899 //
125294 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
125295 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
125296 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
125297 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
125298 // (AArch64dup:{ *:[v8i8] } GPR32:{ *:[i32] }:$Rn) => (DUPv8i8gpr:{ *:[v8i8] } GPR32:{ *:[i32] }:$Rn)
125299 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i8gpr),
125300 GIR_RootConstrainSelectedInstOperands,
125301 // GIR_Coverage, 1899,
125302 GIR_Done,
125303 // Label 7061: @342269
125304 GIM_Reject,
125305 // Label 7025: @342270
125306 GIM_Try, /*On fail goto*//*Label 7062*/ GIMT_Encode4(342324), // Rule ID 6026 //
125307 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
125308 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125309 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
125310 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
125311 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
125312 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
125313 // MIs[1] Rn
125314 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
125315 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
125316 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125317 // (AArch64dup:{ *:[v8f16] } (ld:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv8h:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn)
125318 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv8h),
125319 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
125320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
125321 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
125322 GIR_RootConstrainSelectedInstOperands,
125323 // GIR_Coverage, 6026,
125324 GIR_EraseRootFromParent_Done,
125325 // Label 7062: @342324
125326 GIM_Try, /*On fail goto*//*Label 7063*/ GIMT_Encode4(342378), // Rule ID 6028 //
125327 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
125328 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125329 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
125330 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
125331 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
125332 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
125333 // MIs[1] Rn
125334 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
125335 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
125336 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125337 // (AArch64dup:{ *:[v8bf16] } (ld:{ *:[bf16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv8h:{ *:[v8bf16] } GPR64sp:{ *:[i64] }:$Rn)
125338 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv8h),
125339 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
125340 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
125341 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
125342 GIR_RootConstrainSelectedInstOperands,
125343 // GIR_Coverage, 6028,
125344 GIR_EraseRootFromParent_Done,
125345 // Label 7063: @342378
125346 GIM_Try, /*On fail goto*//*Label 7064*/ GIMT_Encode4(342432), // Rule ID 12445 //
125347 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
125348 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125349 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
125350 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
125351 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
125352 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
125353 // MIs[1] Rn
125354 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
125355 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
125356 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125357 // (AArch64dup:{ *:[v8i16] } (ld:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv8h:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)
125358 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv8h),
125359 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
125360 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
125361 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
125362 GIR_RootConstrainSelectedInstOperands,
125363 // GIR_Coverage, 12445,
125364 GIR_EraseRootFromParent_Done,
125365 // Label 7064: @342432
125366 GIM_Try, /*On fail goto*//*Label 7065*/ GIMT_Encode4(342493), // Rule ID 6009 //
125367 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
125368 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125369 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
125370 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
125371 GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
125372 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
125373 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
125374 // MIs[1] Rn
125375 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
125376 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
125377 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125378 // (AArch64dup:{ *:[v8i16] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>) => (LD1Rv8h:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)
125379 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv8h),
125380 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
125381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
125382 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
125383 GIR_RootConstrainSelectedInstOperands,
125384 // GIR_Coverage, 6009,
125385 GIR_EraseRootFromParent_Done,
125386 // Label 7065: @342493
125387 GIM_Try, /*On fail goto*//*Label 7066*/ GIMT_Encode4(342519), // Rule ID 1902 //
125388 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
125389 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
125390 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125391 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
125392 // (AArch64dup:{ *:[v8i16] } GPR32:{ *:[i32] }:$Rn) => (DUPv8i16gpr:{ *:[v8i16] } GPR32:{ *:[i32] }:$Rn)
125393 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i16gpr),
125394 GIR_RootConstrainSelectedInstOperands,
125395 // GIR_Coverage, 1902,
125396 GIR_Done,
125397 // Label 7066: @342519
125398 GIM_Try, /*On fail goto*//*Label 7067*/ GIMT_Encode4(342599), // Rule ID 5273 //
125399 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
125400 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125401 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
125402 // (AArch64dup:{ *:[v8f16] } FPR16:{ *:[f16] }:$Rn) => (DUPv8i16lane:{ *:[v8f16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] }), 0:{ *:[i64] })
125403 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
125404 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
125405 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
125406 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
125407 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
125408 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
125409 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
125410 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
125411 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
125412 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
125413 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
125414 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
125415 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
125416 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i16lane),
125417 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125418 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
125419 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
125420 GIR_RootConstrainSelectedInstOperands,
125421 // GIR_Coverage, 5273,
125422 GIR_EraseRootFromParent_Done,
125423 // Label 7067: @342599
125424 GIM_Try, /*On fail goto*//*Label 7068*/ GIMT_Encode4(342679), // Rule ID 5274 //
125425 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
125426 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125427 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
125428 // (AArch64dup:{ *:[v8bf16] } FPR16:{ *:[bf16] }:$Rn) => (DUPv8i16lane:{ *:[v8bf16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), FPR16:{ *:[bf16] }:$Rn, hsub:{ *:[i32] }), 0:{ *:[i64] })
125429 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
125430 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
125431 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
125432 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
125433 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
125434 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
125435 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
125436 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
125437 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
125438 GIR_AddImm8, /*InsnID*/1, /*Imm*/7,
125439 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
125440 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
125441 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
125442 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i16lane),
125443 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125444 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
125445 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
125446 GIR_RootConstrainSelectedInstOperands,
125447 // GIR_Coverage, 5274,
125448 GIR_EraseRootFromParent_Done,
125449 // Label 7068: @342679
125450 GIM_Reject,
125451 // Label 7026: @342680
125452 GIM_Try, /*On fail goto*//*Label 7069*/ GIMT_Encode4(342734), // Rule ID 12443 //
125453 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
125454 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125455 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
125456 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
125457 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
125458 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
125459 // MIs[1] Rn
125460 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
125461 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
125462 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125463 // (AArch64dup:{ *:[v16i8] } (ld:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>) => (LD1Rv16b:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)
125464 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv16b),
125465 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
125466 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
125467 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
125468 GIR_RootConstrainSelectedInstOperands,
125469 // GIR_Coverage, 12443,
125470 GIR_EraseRootFromParent_Done,
125471 // Label 7069: @342734
125472 GIM_Try, /*On fail goto*//*Label 7070*/ GIMT_Encode4(342795), // Rule ID 6007 //
125473 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
125474 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125475 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
125476 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
125477 GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
125478 GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
125479 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
125480 // MIs[1] Rn
125481 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
125482 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
125483 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125484 // (AArch64dup:{ *:[v16i8] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>) => (LD1Rv16b:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)
125485 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv16b),
125486 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
125487 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
125488 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
125489 GIR_RootConstrainSelectedInstOperands,
125490 // GIR_Coverage, 6007,
125491 GIR_EraseRootFromParent_Done,
125492 // Label 7070: @342795
125493 GIM_Try, /*On fail goto*//*Label 7071*/ GIMT_Encode4(342821), // Rule ID 1900 //
125494 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
125495 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
125496 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125497 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
125498 // (AArch64dup:{ *:[v16i8] } GPR32:{ *:[i32] }:$Rn) => (DUPv16i8gpr:{ *:[v16i8] } GPR32:{ *:[i32] }:$Rn)
125499 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv16i8gpr),
125500 GIR_RootConstrainSelectedInstOperands,
125501 // GIR_Coverage, 1900,
125502 GIR_Done,
125503 // Label 7071: @342821
125504 GIM_Reject,
125505 // Label 7027: @342822
125506 GIM_Reject,
125507 // Label 112: @342823
125508 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(11), /*)*//*default:*//*Label 7074*/ GIMT_Encode4(343143),
125509 /*GILLT_v4s16*//*Label 7072*/ GIMT_Encode4(342850), GIMT_Encode4(0), GIMT_Encode4(0),
125510 /*GILLT_v8s16*//*Label 7073*/ GIMT_Encode4(342967),
125511 // Label 7072: @342850
125512 GIM_Try, /*On fail goto*//*Label 7075*/ GIMT_Encode4(342966),
125513 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
125514 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
125515 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
125516 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125517 GIM_Try, /*On fail goto*//*Label 7076*/ GIMT_Encode4(342903), // Rule ID 1909 //
125518 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
125519 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
125520 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
125521 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
125522 // MIs[1] Operand 1
125523 // No operand predicates
125524 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125525 // (AArch64duplane16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) => (DUPv4i16lane:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx)
125526 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i16lane),
125527 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125528 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
125529 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
125530 GIR_RootConstrainSelectedInstOperands,
125531 // GIR_Coverage, 1909,
125532 GIR_EraseRootFromParent_Done,
125533 // Label 7076: @342903
125534 GIM_Try, /*On fail goto*//*Label 7077*/ GIMT_Encode4(342934), // Rule ID 5275 //
125535 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
125536 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
125537 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
125538 // MIs[1] Operand 1
125539 // No operand predicates
125540 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125541 // (AArch64duplane16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm) => (DUPv4i16lane:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)
125542 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i16lane),
125543 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125544 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
125545 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
125546 GIR_RootConstrainSelectedInstOperands,
125547 // GIR_Coverage, 5275,
125548 GIR_EraseRootFromParent_Done,
125549 // Label 7077: @342934
125550 GIM_Try, /*On fail goto*//*Label 7078*/ GIMT_Encode4(342965), // Rule ID 5277 //
125551 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
125552 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
125553 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
125554 // MIs[1] Operand 1
125555 // No operand predicates
125556 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125557 // (AArch64duplane16:{ *:[v4bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm) => (DUPv4i16lane:{ *:[v4bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)
125558 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i16lane),
125559 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125560 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
125561 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
125562 GIR_RootConstrainSelectedInstOperands,
125563 // GIR_Coverage, 5277,
125564 GIR_EraseRootFromParent_Done,
125565 // Label 7078: @342965
125566 GIM_Reject,
125567 // Label 7075: @342966
125568 GIM_Reject,
125569 // Label 7073: @342967
125570 GIM_Try, /*On fail goto*//*Label 7079*/ GIMT_Encode4(343142),
125571 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
125572 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
125573 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125574 GIM_Try, /*On fail goto*//*Label 7080*/ GIMT_Encode4(343033), // Rule ID 6017 //
125575 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
125576 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
125577 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
125578 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
125579 // MIs[1] Rn
125580 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
125581 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
125582 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
125583 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125584 // (AArch64duplane16:{ *:[v8i16] } (ld:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (LD1Rv8h:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)
125585 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv8h),
125586 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
125587 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
125588 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
125589 GIR_RootConstrainSelectedInstOperands,
125590 // GIR_Coverage, 6017,
125591 GIR_EraseRootFromParent_Done,
125592 // Label 7080: @343033
125593 GIM_Try, /*On fail goto*//*Label 7081*/ GIMT_Encode4(343071), // Rule ID 1910 //
125594 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
125595 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125596 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
125597 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
125598 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
125599 // MIs[1] Operand 1
125600 // No operand predicates
125601 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125602 // (AArch64duplane16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx) => (DUPv8i16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx)
125603 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i16lane),
125604 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125605 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
125606 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
125607 GIR_RootConstrainSelectedInstOperands,
125608 // GIR_Coverage, 1910,
125609 GIR_EraseRootFromParent_Done,
125610 // Label 7081: @343071
125611 GIM_Try, /*On fail goto*//*Label 7082*/ GIMT_Encode4(343106), // Rule ID 5276 //
125612 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125613 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
125614 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
125615 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
125616 // MIs[1] Operand 1
125617 // No operand predicates
125618 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125619 // (AArch64duplane16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm) => (DUPv8i16lane:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)
125620 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i16lane),
125621 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125622 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
125623 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
125624 GIR_RootConstrainSelectedInstOperands,
125625 // GIR_Coverage, 5276,
125626 GIR_EraseRootFromParent_Done,
125627 // Label 7082: @343106
125628 GIM_Try, /*On fail goto*//*Label 7083*/ GIMT_Encode4(343141), // Rule ID 5278 //
125629 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125630 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
125631 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
125632 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
125633 // MIs[1] Operand 1
125634 // No operand predicates
125635 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125636 // (AArch64duplane16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm) => (DUPv8i16lane:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)
125637 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i16lane),
125638 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125639 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
125640 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
125641 GIR_RootConstrainSelectedInstOperands,
125642 // GIR_Coverage, 5278,
125643 GIR_EraseRootFromParent_Done,
125644 // Label 7083: @343141
125645 GIM_Reject,
125646 // Label 7079: @343142
125647 GIM_Reject,
125648 // Label 7074: @343143
125649 GIM_Reject,
125650 // Label 113: @343144
125651 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(9), /*)*//*default:*//*Label 7086*/ GIMT_Encode4(343398),
125652 /*GILLT_v2s32*//*Label 7084*/ GIMT_Encode4(343171), GIMT_Encode4(0), GIMT_Encode4(0),
125653 /*GILLT_v4s32*//*Label 7085*/ GIMT_Encode4(343257),
125654 // Label 7084: @343171
125655 GIM_Try, /*On fail goto*//*Label 7087*/ GIMT_Encode4(343256),
125656 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
125657 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
125658 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
125659 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125660 GIM_Try, /*On fail goto*//*Label 7088*/ GIMT_Encode4(343224), // Rule ID 1907 //
125661 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
125662 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
125663 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
125664 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
125665 // MIs[1] Operand 1
125666 // No operand predicates
125667 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125668 // (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) => (DUPv2i32lane:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx)
125669 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i32lane),
125670 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125671 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
125672 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
125673 GIR_RootConstrainSelectedInstOperands,
125674 // GIR_Coverage, 1907,
125675 GIR_EraseRootFromParent_Done,
125676 // Label 7088: @343224
125677 GIM_Try, /*On fail goto*//*Label 7089*/ GIMT_Encode4(343255), // Rule ID 5279 //
125678 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
125679 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
125680 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
125681 // MIs[1] Operand 1
125682 // No operand predicates
125683 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125684 // (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm) => (DUPv2i32lane:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)
125685 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i32lane),
125686 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125687 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
125688 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
125689 GIR_RootConstrainSelectedInstOperands,
125690 // GIR_Coverage, 5279,
125691 GIR_EraseRootFromParent_Done,
125692 // Label 7089: @343255
125693 GIM_Reject,
125694 // Label 7087: @343256
125695 GIM_Reject,
125696 // Label 7085: @343257
125697 GIM_Try, /*On fail goto*//*Label 7090*/ GIMT_Encode4(343397),
125698 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
125699 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
125700 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125701 GIM_Try, /*On fail goto*//*Label 7091*/ GIMT_Encode4(343323), // Rule ID 6019 //
125702 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
125703 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
125704 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
125705 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
125706 // MIs[1] Rn
125707 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
125708 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
125709 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
125710 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125711 // (AArch64duplane32:{ *:[v4i32] } (ld:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (LD1Rv4s:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)
125712 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4s),
125713 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
125714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
125715 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
125716 GIR_RootConstrainSelectedInstOperands,
125717 // GIR_Coverage, 6019,
125718 GIR_EraseRootFromParent_Done,
125719 // Label 7091: @343323
125720 GIM_Try, /*On fail goto*//*Label 7092*/ GIMT_Encode4(343361), // Rule ID 1908 //
125721 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
125722 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125723 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
125724 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
125725 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
125726 // MIs[1] Operand 1
125727 // No operand predicates
125728 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125729 // (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx) => (DUPv4i32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx)
125730 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i32lane),
125731 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125732 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
125733 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
125734 GIR_RootConstrainSelectedInstOperands,
125735 // GIR_Coverage, 1908,
125736 GIR_EraseRootFromParent_Done,
125737 // Label 7092: @343361
125738 GIM_Try, /*On fail goto*//*Label 7093*/ GIMT_Encode4(343396), // Rule ID 5280 //
125739 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125740 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
125741 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
125742 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
125743 // MIs[1] Operand 1
125744 // No operand predicates
125745 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125746 // (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm) => (DUPv4i32lane:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)
125747 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i32lane),
125748 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125749 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
125750 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
125751 GIR_RootConstrainSelectedInstOperands,
125752 // GIR_Coverage, 5280,
125753 GIR_EraseRootFromParent_Done,
125754 // Label 7093: @343396
125755 GIM_Reject,
125756 // Label 7090: @343397
125757 GIM_Reject,
125758 // Label 7086: @343398
125759 GIM_Reject,
125760 // Label 114: @343399
125761 GIM_Try, /*On fail goto*//*Label 7094*/ GIMT_Encode4(343544),
125762 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
125763 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
125764 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
125765 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125766 GIM_Try, /*On fail goto*//*Label 7095*/ GIMT_Encode4(343468), // Rule ID 6020 //
125767 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
125768 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
125769 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
125770 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
125771 // MIs[1] Rn
125772 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
125773 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
125774 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
125775 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125776 // (AArch64duplane64:{ *:[v2i64] } (ld:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (LD1Rv2d:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)
125777 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2d),
125778 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
125779 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
125780 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
125781 GIR_RootConstrainSelectedInstOperands,
125782 // GIR_Coverage, 6020,
125783 GIR_EraseRootFromParent_Done,
125784 // Label 7095: @343468
125785 GIM_Try, /*On fail goto*//*Label 7096*/ GIMT_Encode4(343543),
125786 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125787 GIM_Try, /*On fail goto*//*Label 7097*/ GIMT_Encode4(343511), // Rule ID 1906 //
125788 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
125789 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
125790 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
125791 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
125792 // MIs[1] Operand 1
125793 // No operand predicates
125794 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125795 // (AArch64duplane64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx) => (DUPv2i64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$idx)
125796 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64lane),
125797 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125798 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
125799 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
125800 GIR_RootConstrainSelectedInstOperands,
125801 // GIR_Coverage, 1906,
125802 GIR_EraseRootFromParent_Done,
125803 // Label 7097: @343511
125804 GIM_Try, /*On fail goto*//*Label 7098*/ GIMT_Encode4(343542), // Rule ID 5281 //
125805 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
125806 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
125807 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
125808 // MIs[1] Operand 1
125809 // No operand predicates
125810 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125811 // (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$imm) => (DUPv2i64lane:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$imm)
125812 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64lane),
125813 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125814 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
125815 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
125816 GIR_RootConstrainSelectedInstOperands,
125817 // GIR_Coverage, 5281,
125818 GIR_EraseRootFromParent_Done,
125819 // Label 7098: @343542
125820 GIM_Reject,
125821 // Label 7096: @343543
125822 GIM_Reject,
125823 // Label 7094: @343544
125824 GIM_Reject,
125825 // Label 115: @343545
125826 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(12), /*)*//*default:*//*Label 7101*/ GIMT_Encode4(343723),
125827 /*GILLT_v8s8*//*Label 7099*/ GIMT_Encode4(343568), GIMT_Encode4(0),
125828 /*GILLT_v16s8*//*Label 7100*/ GIMT_Encode4(343617),
125829 // Label 7099: @343568
125830 GIM_Try, /*On fail goto*//*Label 7102*/ GIMT_Encode4(343616), // Rule ID 1911 //
125831 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
125832 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
125833 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
125834 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
125835 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125836 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
125837 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
125838 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
125839 // MIs[1] Operand 1
125840 // No operand predicates
125841 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125842 // (AArch64duplane8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx) => (DUPv8i8lane:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx)
125843 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i8lane),
125844 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125845 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
125846 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
125847 GIR_RootConstrainSelectedInstOperands,
125848 // GIR_Coverage, 1911,
125849 GIR_EraseRootFromParent_Done,
125850 // Label 7102: @343616
125851 GIM_Reject,
125852 // Label 7100: @343617
125853 GIM_Try, /*On fail goto*//*Label 7103*/ GIMT_Encode4(343722),
125854 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
125855 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
125856 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125857 GIM_Try, /*On fail goto*//*Label 7104*/ GIMT_Encode4(343683), // Rule ID 6015 //
125858 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
125859 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
125860 GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
125861 GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
125862 // MIs[1] Rn
125863 GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
125864 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
125865 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
125866 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125867 // (AArch64duplane8:{ *:[v16i8] } (ld:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] }) => (LD1Rv16b:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)
125868 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv16b),
125869 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
125870 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
125871 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
125872 GIR_RootConstrainSelectedInstOperands,
125873 // GIR_Coverage, 6015,
125874 GIR_EraseRootFromParent_Done,
125875 // Label 7104: @343683
125876 GIM_Try, /*On fail goto*//*Label 7105*/ GIMT_Encode4(343721), // Rule ID 1912 //
125877 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
125878 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
125879 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
125880 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
125881 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
125882 // MIs[1] Operand 1
125883 // No operand predicates
125884 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125885 // (AArch64duplane8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx) => (DUPv16i8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx)
125886 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv16i8lane),
125887 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125888 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
125889 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
125890 GIR_RootConstrainSelectedInstOperands,
125891 // GIR_Coverage, 1912,
125892 GIR_EraseRootFromParent_Done,
125893 // Label 7105: @343721
125894 GIM_Reject,
125895 // Label 7103: @343722
125896 GIM_Reject,
125897 // Label 7101: @343723
125898 GIM_Reject,
125899 // Label 116: @343724
125900 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(24), /*)*//*default:*//*Label 7115*/ GIMT_Encode4(344594),
125901 /*GILLT_s64*//*Label 7106*/ GIMT_Encode4(343819), GIMT_Encode4(0),
125902 /*GILLT_v2s32*//*Label 7107*/ GIMT_Encode4(343902),
125903 /*GILLT_v2s64*//*Label 7108*/ GIMT_Encode4(343985),
125904 /*GILLT_v4s16*//*Label 7109*/ GIMT_Encode4(344068),
125905 /*GILLT_v4s32*//*Label 7110*/ GIMT_Encode4(344180),
125906 /*GILLT_v8s8*//*Label 7111*/ GIMT_Encode4(344263),
125907 /*GILLT_v8s16*//*Label 7112*/ GIMT_Encode4(344349),
125908 /*GILLT_v16s8*//*Label 7113*/ GIMT_Encode4(344461), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
125909 /*GILLT_nxv16s8*//*Label 7114*/ GIMT_Encode4(344547),
125910 // Label 7106: @343819
125911 GIM_Try, /*On fail goto*//*Label 7116*/ GIMT_Encode4(343901),
125912 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
125913 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
125914 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
125915 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
125916 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
125917 GIM_Try, /*On fail goto*//*Label 7117*/ GIMT_Encode4(343871), // Rule ID 5105 //
125918 // MIs[0] imm
125919 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
125920 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
125921 // MIs[1] Operand 1
125922 // No operand predicates
125923 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125924 // (AArch64ext:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, V64:{ *:[v1i64] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, V64:{ *:[v1i64] }:$Rm, (imm:{ *:[i32] }):$imm)
125925 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
125926 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125927 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
125928 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
125929 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
125930 GIR_RootConstrainSelectedInstOperands,
125931 // GIR_Coverage, 5105,
125932 GIR_EraseRootFromParent_Done,
125933 // Label 7117: @343871
125934 GIM_Try, /*On fail goto*//*Label 7118*/ GIMT_Encode4(343900), // Rule ID 5110 //
125935 // MIs[0] imm
125936 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
125937 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
125938 // MIs[1] Operand 1
125939 // No operand predicates
125940 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125941 // (AArch64ext:{ *:[v1f64] } V64:{ *:[v1f64] }:$Rn, V64:{ *:[v1f64] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v1f64] } V64:{ *:[v1f64] }:$Rn, V64:{ *:[v1f64] }:$Rm, (imm:{ *:[i32] }):$imm)
125942 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
125943 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125944 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
125945 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
125946 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
125947 GIR_RootConstrainSelectedInstOperands,
125948 // GIR_Coverage, 5110,
125949 GIR_EraseRootFromParent_Done,
125950 // Label 7118: @343900
125951 GIM_Reject,
125952 // Label 7116: @343901
125953 GIM_Reject,
125954 // Label 7107: @343902
125955 GIM_Try, /*On fail goto*//*Label 7119*/ GIMT_Encode4(343984),
125956 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
125957 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
125958 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
125959 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
125960 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
125961 GIM_Try, /*On fail goto*//*Label 7120*/ GIMT_Encode4(343954), // Rule ID 5095 //
125962 // MIs[0] imm
125963 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
125964 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
125965 // MIs[1] Operand 1
125966 // No operand predicates
125967 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125968 // (AArch64ext:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, (imm:{ *:[i32] }):$imm)
125969 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
125970 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125971 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
125972 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
125973 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
125974 GIR_RootConstrainSelectedInstOperands,
125975 // GIR_Coverage, 5095,
125976 GIR_EraseRootFromParent_Done,
125977 // Label 7120: @343954
125978 GIM_Try, /*On fail goto*//*Label 7121*/ GIMT_Encode4(343983), // Rule ID 5100 //
125979 // MIs[0] imm
125980 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
125981 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
125982 // MIs[1] Operand 1
125983 // No operand predicates
125984 GIM_CheckIsSafeToFold, /*NumInsns*/1,
125985 // (AArch64ext:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, (imm:{ *:[i32] }):$imm)
125986 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
125987 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
125988 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
125989 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
125990 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
125991 GIR_RootConstrainSelectedInstOperands,
125992 // GIR_Coverage, 5100,
125993 GIR_EraseRootFromParent_Done,
125994 // Label 7121: @343983
125995 GIM_Reject,
125996 // Label 7119: @343984
125997 GIM_Reject,
125998 // Label 7108: @343985
125999 GIM_Try, /*On fail goto*//*Label 7122*/ GIMT_Encode4(344067),
126000 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
126001 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
126002 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126003 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126004 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126005 GIM_Try, /*On fail goto*//*Label 7123*/ GIMT_Encode4(344037), // Rule ID 5106 //
126006 // MIs[0] imm
126007 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
126008 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
126009 // MIs[1] Operand 1
126010 // No operand predicates
126011 GIM_CheckIsSafeToFold, /*NumInsns*/1,
126012 // (AArch64ext:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, (imm:{ *:[i32] }):$imm)
126013 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
126014 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126015 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
126016 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
126017 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
126018 GIR_RootConstrainSelectedInstOperands,
126019 // GIR_Coverage, 5106,
126020 GIR_EraseRootFromParent_Done,
126021 // Label 7123: @344037
126022 GIM_Try, /*On fail goto*//*Label 7124*/ GIMT_Encode4(344066), // Rule ID 5111 //
126023 // MIs[0] imm
126024 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
126025 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
126026 // MIs[1] Operand 1
126027 // No operand predicates
126028 GIM_CheckIsSafeToFold, /*NumInsns*/1,
126029 // (AArch64ext:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i32] }):$imm)
126030 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
126031 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126032 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
126033 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
126034 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
126035 GIR_RootConstrainSelectedInstOperands,
126036 // GIR_Coverage, 5111,
126037 GIR_EraseRootFromParent_Done,
126038 // Label 7124: @344066
126039 GIM_Reject,
126040 // Label 7122: @344067
126041 GIM_Reject,
126042 // Label 7109: @344068
126043 GIM_Try, /*On fail goto*//*Label 7125*/ GIMT_Encode4(344179),
126044 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
126045 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
126046 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126047 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126048 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126049 GIM_Try, /*On fail goto*//*Label 7126*/ GIMT_Encode4(344120), // Rule ID 5080 //
126050 // MIs[0] imm
126051 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
126052 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
126053 // MIs[1] Operand 1
126054 // No operand predicates
126055 GIM_CheckIsSafeToFold, /*NumInsns*/1,
126056 // (AArch64ext:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, (imm:{ *:[i32] }):$imm)
126057 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
126058 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126059 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
126060 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
126061 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
126062 GIR_RootConstrainSelectedInstOperands,
126063 // GIR_Coverage, 5080,
126064 GIR_EraseRootFromParent_Done,
126065 // Label 7126: @344120
126066 GIM_Try, /*On fail goto*//*Label 7127*/ GIMT_Encode4(344149), // Rule ID 5085 //
126067 // MIs[0] imm
126068 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
126069 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
126070 // MIs[1] Operand 1
126071 // No operand predicates
126072 GIM_CheckIsSafeToFold, /*NumInsns*/1,
126073 // (AArch64ext:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, (imm:{ *:[i32] }):$imm)
126074 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
126075 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126076 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
126077 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
126078 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
126079 GIR_RootConstrainSelectedInstOperands,
126080 // GIR_Coverage, 5085,
126081 GIR_EraseRootFromParent_Done,
126082 // Label 7127: @344149
126083 GIM_Try, /*On fail goto*//*Label 7128*/ GIMT_Encode4(344178), // Rule ID 5090 //
126084 // MIs[0] imm
126085 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
126086 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
126087 // MIs[1] Operand 1
126088 // No operand predicates
126089 GIM_CheckIsSafeToFold, /*NumInsns*/1,
126090 // (AArch64ext:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm, (imm:{ *:[i32] }):$imm)
126091 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
126092 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126093 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
126094 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
126095 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
126096 GIR_RootConstrainSelectedInstOperands,
126097 // GIR_Coverage, 5090,
126098 GIR_EraseRootFromParent_Done,
126099 // Label 7128: @344178
126100 GIM_Reject,
126101 // Label 7125: @344179
126102 GIM_Reject,
126103 // Label 7110: @344180
126104 GIM_Try, /*On fail goto*//*Label 7129*/ GIMT_Encode4(344262),
126105 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
126106 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
126107 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126108 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126109 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126110 GIM_Try, /*On fail goto*//*Label 7130*/ GIMT_Encode4(344232), // Rule ID 5096 //
126111 // MIs[0] imm
126112 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
126113 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
126114 // MIs[1] Operand 1
126115 // No operand predicates
126116 GIM_CheckIsSafeToFold, /*NumInsns*/1,
126117 // (AArch64ext:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i32] }):$imm)
126118 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
126119 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126120 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
126121 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
126122 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
126123 GIR_RootConstrainSelectedInstOperands,
126124 // GIR_Coverage, 5096,
126125 GIR_EraseRootFromParent_Done,
126126 // Label 7130: @344232
126127 GIM_Try, /*On fail goto*//*Label 7131*/ GIMT_Encode4(344261), // Rule ID 5101 //
126128 // MIs[0] imm
126129 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
126130 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
126131 // MIs[1] Operand 1
126132 // No operand predicates
126133 GIM_CheckIsSafeToFold, /*NumInsns*/1,
126134 // (AArch64ext:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i32] }):$imm)
126135 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
126136 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126137 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
126138 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
126139 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
126140 GIR_RootConstrainSelectedInstOperands,
126141 // GIR_Coverage, 5101,
126142 GIR_EraseRootFromParent_Done,
126143 // Label 7131: @344261
126144 GIM_Reject,
126145 // Label 7129: @344262
126146 GIM_Reject,
126147 // Label 7111: @344263
126148 GIM_Try, /*On fail goto*//*Label 7132*/ GIMT_Encode4(344348),
126149 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
126150 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
126151 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126152 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126153 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126154 GIM_Try, /*On fail goto*//*Label 7133*/ GIMT_Encode4(344318), // Rule ID 1855 //
126155 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126156 // MIs[0] imm
126157 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
126158 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
126159 // MIs[1] Operand 1
126160 // No operand predicates
126161 GIM_CheckIsSafeToFold, /*NumInsns*/1,
126162 // (AArch64ext:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm)
126163 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
126164 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126165 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
126166 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
126167 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
126168 GIR_RootConstrainSelectedInstOperands,
126169 // GIR_Coverage, 1855,
126170 GIR_EraseRootFromParent_Done,
126171 // Label 7133: @344318
126172 GIM_Try, /*On fail goto*//*Label 7134*/ GIMT_Encode4(344347), // Rule ID 5075 //
126173 // MIs[0] imm
126174 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
126175 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
126176 // MIs[1] Operand 1
126177 // No operand predicates
126178 GIM_CheckIsSafeToFold, /*NumInsns*/1,
126179 // (AArch64ext:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm)
126180 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
126181 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126182 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
126183 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
126184 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
126185 GIR_RootConstrainSelectedInstOperands,
126186 // GIR_Coverage, 5075,
126187 GIR_EraseRootFromParent_Done,
126188 // Label 7134: @344347
126189 GIM_Reject,
126190 // Label 7132: @344348
126191 GIM_Reject,
126192 // Label 7112: @344349
126193 GIM_Try, /*On fail goto*//*Label 7135*/ GIMT_Encode4(344460),
126194 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
126195 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
126196 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126197 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126198 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126199 GIM_Try, /*On fail goto*//*Label 7136*/ GIMT_Encode4(344401), // Rule ID 5081 //
126200 // MIs[0] imm
126201 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
126202 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
126203 // MIs[1] Operand 1
126204 // No operand predicates
126205 GIM_CheckIsSafeToFold, /*NumInsns*/1,
126206 // (AArch64ext:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, (imm:{ *:[i32] }):$imm)
126207 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
126208 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126209 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
126210 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
126211 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
126212 GIR_RootConstrainSelectedInstOperands,
126213 // GIR_Coverage, 5081,
126214 GIR_EraseRootFromParent_Done,
126215 // Label 7136: @344401
126216 GIM_Try, /*On fail goto*//*Label 7137*/ GIMT_Encode4(344430), // Rule ID 5086 //
126217 // MIs[0] imm
126218 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
126219 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
126220 // MIs[1] Operand 1
126221 // No operand predicates
126222 GIM_CheckIsSafeToFold, /*NumInsns*/1,
126223 // (AArch64ext:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i32] }):$imm)
126224 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
126225 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126226 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
126227 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
126228 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
126229 GIR_RootConstrainSelectedInstOperands,
126230 // GIR_Coverage, 5086,
126231 GIR_EraseRootFromParent_Done,
126232 // Label 7137: @344430
126233 GIM_Try, /*On fail goto*//*Label 7138*/ GIMT_Encode4(344459), // Rule ID 5091 //
126234 // MIs[0] imm
126235 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
126236 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
126237 // MIs[1] Operand 1
126238 // No operand predicates
126239 GIM_CheckIsSafeToFold, /*NumInsns*/1,
126240 // (AArch64ext:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm, (imm:{ *:[i32] }):$imm)
126241 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
126242 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126243 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
126244 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
126245 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
126246 GIR_RootConstrainSelectedInstOperands,
126247 // GIR_Coverage, 5091,
126248 GIR_EraseRootFromParent_Done,
126249 // Label 7138: @344459
126250 GIM_Reject,
126251 // Label 7135: @344460
126252 GIM_Reject,
126253 // Label 7113: @344461
126254 GIM_Try, /*On fail goto*//*Label 7139*/ GIMT_Encode4(344546),
126255 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
126256 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
126257 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126258 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126259 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126260 GIM_Try, /*On fail goto*//*Label 7140*/ GIMT_Encode4(344516), // Rule ID 1856 //
126261 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126262 // MIs[0] imm
126263 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
126264 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
126265 // MIs[1] Operand 1
126266 // No operand predicates
126267 GIM_CheckIsSafeToFold, /*NumInsns*/1,
126268 // (AArch64ext:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm)
126269 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
126270 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126271 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
126272 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
126273 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
126274 GIR_RootConstrainSelectedInstOperands,
126275 // GIR_Coverage, 1856,
126276 GIR_EraseRootFromParent_Done,
126277 // Label 7140: @344516
126278 GIM_Try, /*On fail goto*//*Label 7141*/ GIMT_Encode4(344545), // Rule ID 5076 //
126279 // MIs[0] imm
126280 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
126281 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
126282 // MIs[1] Operand 1
126283 // No operand predicates
126284 GIM_CheckIsSafeToFold, /*NumInsns*/1,
126285 // (AArch64ext:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm) => (EXTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm)
126286 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
126287 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126288 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
126289 GIR_RootToRootCopy, /*OpIdx*/2, // Rm
126290 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
126291 GIR_RootConstrainSelectedInstOperands,
126292 // GIR_Coverage, 5076,
126293 GIR_EraseRootFromParent_Done,
126294 // Label 7141: @344545
126295 GIM_Reject,
126296 // Label 7139: @344546
126297 GIM_Reject,
126298 // Label 7114: @344547
126299 GIM_Try, /*On fail goto*//*Label 7142*/ GIMT_Encode4(344593), // Rule ID 2636 //
126300 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
126301 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
126302 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
126303 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
126304 // MIs[0] Op3
126305 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
126306 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
126307 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255),
126308 // MIs[1] Operand 1
126309 // No operand predicates
126310 GIM_CheckIsSafeToFold, /*NumInsns*/1,
126311 // (AArch64ext:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$Op3) => (EXT_ZZI:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$Op3)
126312 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXT_ZZI),
126313 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
126314 GIR_RootToRootCopy, /*OpIdx*/1, // Op1
126315 GIR_RootToRootCopy, /*OpIdx*/2, // Op2
126316 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // Op3
126317 GIR_RootConstrainSelectedInstOperands,
126318 // GIR_Coverage, 2636,
126319 GIR_EraseRootFromParent_Done,
126320 // Label 7142: @344593
126321 GIM_Reject,
126322 // Label 7115: @344594
126323 GIM_Reject,
126324 // Label 117: @344595
126325 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 7150*/ GIMT_Encode4(344933),
126326 /*GILLT_s32*//*Label 7143*/ GIMT_Encode4(344642),
126327 /*GILLT_s64*//*Label 7144*/ GIMT_Encode4(344680), GIMT_Encode4(0),
126328 /*GILLT_v2s32*//*Label 7145*/ GIMT_Encode4(344743),
126329 /*GILLT_v2s64*//*Label 7146*/ GIMT_Encode4(344781),
126330 /*GILLT_v4s16*//*Label 7147*/ GIMT_Encode4(344819),
126331 /*GILLT_v4s32*//*Label 7148*/ GIMT_Encode4(344857), GIMT_Encode4(0),
126332 /*GILLT_v8s16*//*Label 7149*/ GIMT_Encode4(344895),
126333 // Label 7143: @344642
126334 GIM_Try, /*On fail goto*//*Label 7151*/ GIMT_Encode4(344679), // Rule ID 1609 //
126335 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126336 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
126337 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
126338 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
126339 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
126340 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
126341 // (AArch64fcmeq:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FCMEQ32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
126342 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQ32),
126343 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126344 GIR_RootConstrainSelectedInstOperands,
126345 // GIR_Coverage, 1609,
126346 GIR_Done,
126347 // Label 7151: @344679
126348 GIM_Reject,
126349 // Label 7144: @344680
126350 GIM_Try, /*On fail goto*//*Label 7152*/ GIMT_Encode4(344742),
126351 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
126352 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
126353 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126354 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126355 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126356 GIM_Try, /*On fail goto*//*Label 7153*/ GIMT_Encode4(344722), // Rule ID 1608 //
126357 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126358 // (AArch64fcmeq:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FCMEQ64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
126359 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQ64),
126360 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126361 GIR_RootConstrainSelectedInstOperands,
126362 // GIR_Coverage, 1608,
126363 GIR_Done,
126364 // Label 7153: @344722
126365 GIM_Try, /*On fail goto*//*Label 7154*/ GIMT_Encode4(344741), // Rule ID 4860 //
126366 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126367 // (AArch64fcmeq:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FCMEQ64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
126368 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQ64),
126369 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126370 GIR_RootConstrainSelectedInstOperands,
126371 // GIR_Coverage, 4860,
126372 GIR_Done,
126373 // Label 7154: @344741
126374 GIM_Reject,
126375 // Label 7152: @344742
126376 GIM_Reject,
126377 // Label 7145: @344743
126378 GIM_Try, /*On fail goto*//*Label 7155*/ GIMT_Encode4(344780), // Rule ID 1197 //
126379 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126380 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
126381 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
126382 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126383 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126384 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126385 // (AArch64fcmeq:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FCMEQv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
126386 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv2f32),
126387 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126388 GIR_RootConstrainSelectedInstOperands,
126389 // GIR_Coverage, 1197,
126390 GIR_Done,
126391 // Label 7155: @344780
126392 GIM_Reject,
126393 // Label 7146: @344781
126394 GIM_Try, /*On fail goto*//*Label 7156*/ GIMT_Encode4(344818), // Rule ID 1199 //
126395 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126396 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
126397 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
126398 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126399 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126400 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126401 // (AArch64fcmeq:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FCMEQv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
126402 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv2f64),
126403 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126404 GIR_RootConstrainSelectedInstOperands,
126405 // GIR_Coverage, 1199,
126406 GIR_Done,
126407 // Label 7156: @344818
126408 GIM_Reject,
126409 // Label 7147: @344819
126410 GIM_Try, /*On fail goto*//*Label 7157*/ GIMT_Encode4(344856), // Rule ID 1195 //
126411 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
126412 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
126413 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
126414 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126415 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126416 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126417 // (AArch64fcmeq:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FCMEQv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
126418 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f16),
126419 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126420 GIR_RootConstrainSelectedInstOperands,
126421 // GIR_Coverage, 1195,
126422 GIR_Done,
126423 // Label 7157: @344856
126424 GIM_Reject,
126425 // Label 7148: @344857
126426 GIM_Try, /*On fail goto*//*Label 7158*/ GIMT_Encode4(344894), // Rule ID 1198 //
126427 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126428 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
126429 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
126430 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126431 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126432 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126433 // (AArch64fcmeq:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FCMEQv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
126434 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
126435 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126436 GIR_RootConstrainSelectedInstOperands,
126437 // GIR_Coverage, 1198,
126438 GIR_Done,
126439 // Label 7158: @344894
126440 GIM_Reject,
126441 // Label 7149: @344895
126442 GIM_Try, /*On fail goto*//*Label 7159*/ GIMT_Encode4(344932), // Rule ID 1196 //
126443 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
126444 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
126445 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
126446 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126447 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126448 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126449 // (AArch64fcmeq:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCMEQv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
126450 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv8f16),
126451 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126452 GIR_RootConstrainSelectedInstOperands,
126453 // GIR_Coverage, 1196,
126454 GIR_Done,
126455 // Label 7159: @344932
126456 GIM_Reject,
126457 // Label 7150: @344933
126458 GIM_Reject,
126459 // Label 118: @344934
126460 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(11), /*)*//*default:*//*Label 7166*/ GIMT_Encode4(345163),
126461 /*GILLT_s64*//*Label 7160*/ GIMT_Encode4(344977), GIMT_Encode4(0),
126462 /*GILLT_v2s32*//*Label 7161*/ GIMT_Encode4(345008),
126463 /*GILLT_v2s64*//*Label 7162*/ GIMT_Encode4(345039),
126464 /*GILLT_v4s16*//*Label 7163*/ GIMT_Encode4(345070),
126465 /*GILLT_v4s32*//*Label 7164*/ GIMT_Encode4(345101), GIMT_Encode4(0),
126466 /*GILLT_v8s16*//*Label 7165*/ GIMT_Encode4(345132),
126467 // Label 7160: @344977
126468 GIM_Try, /*On fail goto*//*Label 7167*/ GIMT_Encode4(345007), // Rule ID 2435 //
126469 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126470 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
126471 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126472 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126473 // (AArch64fcmeqz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) => (FCMEQv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
126474 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv1i64rz),
126475 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126476 GIR_RootConstrainSelectedInstOperands,
126477 // GIR_Coverage, 2435,
126478 GIR_Done,
126479 // Label 7167: @345007
126480 GIM_Reject,
126481 // Label 7161: @345008
126482 GIM_Try, /*On fail goto*//*Label 7168*/ GIMT_Encode4(345038), // Rule ID 760 //
126483 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126484 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
126485 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126486 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126487 // (AArch64fcmeqz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCMEQv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
126488 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv2i32rz),
126489 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126490 GIR_RootConstrainSelectedInstOperands,
126491 // GIR_Coverage, 760,
126492 GIR_Done,
126493 // Label 7168: @345038
126494 GIM_Reject,
126495 // Label 7162: @345039
126496 GIM_Try, /*On fail goto*//*Label 7169*/ GIMT_Encode4(345069), // Rule ID 762 //
126497 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126498 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
126499 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126500 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126501 // (AArch64fcmeqz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCMEQv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
126502 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv2i64rz),
126503 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126504 GIR_RootConstrainSelectedInstOperands,
126505 // GIR_Coverage, 762,
126506 GIR_Done,
126507 // Label 7169: @345069
126508 GIM_Reject,
126509 // Label 7163: @345070
126510 GIM_Try, /*On fail goto*//*Label 7170*/ GIMT_Encode4(345100), // Rule ID 758 //
126511 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
126512 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
126513 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126514 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126515 // (AArch64fcmeqz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCMEQv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
126516 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4i16rz),
126517 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126518 GIR_RootConstrainSelectedInstOperands,
126519 // GIR_Coverage, 758,
126520 GIR_Done,
126521 // Label 7170: @345100
126522 GIM_Reject,
126523 // Label 7164: @345101
126524 GIM_Try, /*On fail goto*//*Label 7171*/ GIMT_Encode4(345131), // Rule ID 761 //
126525 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126526 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
126527 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126528 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126529 // (AArch64fcmeqz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCMEQv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
126530 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4i32rz),
126531 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126532 GIR_RootConstrainSelectedInstOperands,
126533 // GIR_Coverage, 761,
126534 GIR_Done,
126535 // Label 7171: @345131
126536 GIM_Reject,
126537 // Label 7165: @345132
126538 GIM_Try, /*On fail goto*//*Label 7172*/ GIMT_Encode4(345162), // Rule ID 759 //
126539 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
126540 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
126541 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126542 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126543 // (AArch64fcmeqz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCMEQv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
126544 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv8i16rz),
126545 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126546 GIR_RootConstrainSelectedInstOperands,
126547 // GIR_Coverage, 759,
126548 GIR_Done,
126549 // Label 7172: @345162
126550 GIM_Reject,
126551 // Label 7166: @345163
126552 GIM_Reject,
126553 // Label 119: @345164
126554 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 7180*/ GIMT_Encode4(345827),
126555 /*GILLT_s32*//*Label 7173*/ GIMT_Encode4(345211),
126556 /*GILLT_s64*//*Label 7174*/ GIMT_Encode4(345249), GIMT_Encode4(0),
126557 /*GILLT_v2s32*//*Label 7175*/ GIMT_Encode4(345312),
126558 /*GILLT_v2s64*//*Label 7176*/ GIMT_Encode4(345415),
126559 /*GILLT_v4s16*//*Label 7177*/ GIMT_Encode4(345518),
126560 /*GILLT_v4s32*//*Label 7178*/ GIMT_Encode4(345621), GIMT_Encode4(0),
126561 /*GILLT_v8s16*//*Label 7179*/ GIMT_Encode4(345724),
126562 // Label 7173: @345211
126563 GIM_Try, /*On fail goto*//*Label 7181*/ GIMT_Encode4(345248), // Rule ID 1611 //
126564 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126565 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
126566 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
126567 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
126568 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
126569 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
126570 // (AArch64fcmge:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FCMGE32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
126571 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGE32),
126572 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126573 GIR_RootConstrainSelectedInstOperands,
126574 // GIR_Coverage, 1611,
126575 GIR_Done,
126576 // Label 7181: @345248
126577 GIM_Reject,
126578 // Label 7174: @345249
126579 GIM_Try, /*On fail goto*//*Label 7182*/ GIMT_Encode4(345311),
126580 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
126581 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
126582 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126583 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126584 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126585 GIM_Try, /*On fail goto*//*Label 7183*/ GIMT_Encode4(345291), // Rule ID 1610 //
126586 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126587 // (AArch64fcmge:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FCMGE64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
126588 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGE64),
126589 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126590 GIR_RootConstrainSelectedInstOperands,
126591 // GIR_Coverage, 1610,
126592 GIR_Done,
126593 // Label 7183: @345291
126594 GIM_Try, /*On fail goto*//*Label 7184*/ GIMT_Encode4(345310), // Rule ID 4861 //
126595 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126596 // (AArch64fcmge:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FCMGE64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
126597 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGE64),
126598 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126599 GIR_RootConstrainSelectedInstOperands,
126600 // GIR_Coverage, 4861,
126601 GIR_Done,
126602 // Label 7184: @345310
126603 GIM_Reject,
126604 // Label 7182: @345311
126605 GIM_Reject,
126606 // Label 7175: @345312
126607 GIM_Try, /*On fail goto*//*Label 7185*/ GIMT_Encode4(345414),
126608 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
126609 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
126610 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126611 GIM_Try, /*On fail goto*//*Label 7186*/ GIMT_Encode4(345386), // Rule ID 1159 //
126612 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126613 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
126614 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
126615 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
126616 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126617 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
126618 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
126619 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
126620 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126621 GIM_CheckIsSafeToFold, /*NumInsns*/2,
126622 // (AArch64fcmge:{ *:[v2i32] } (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm)) => (FACGEv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
126623 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv2f32),
126624 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
126626 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
126627 GIR_RootConstrainSelectedInstOperands,
126628 // GIR_Coverage, 1159,
126629 GIR_EraseRootFromParent_Done,
126630 // Label 7186: @345386
126631 GIM_Try, /*On fail goto*//*Label 7187*/ GIMT_Encode4(345413), // Rule ID 1202 //
126632 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126633 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126634 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126635 // (AArch64fcmge:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FCMGEv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
126636 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv2f32),
126637 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126638 GIR_RootConstrainSelectedInstOperands,
126639 // GIR_Coverage, 1202,
126640 GIR_Done,
126641 // Label 7187: @345413
126642 GIM_Reject,
126643 // Label 7185: @345414
126644 GIM_Reject,
126645 // Label 7176: @345415
126646 GIM_Try, /*On fail goto*//*Label 7188*/ GIMT_Encode4(345517),
126647 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
126648 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
126649 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126650 GIM_Try, /*On fail goto*//*Label 7189*/ GIMT_Encode4(345489), // Rule ID 1163 //
126651 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126652 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
126653 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
126654 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
126655 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126656 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
126657 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
126658 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
126659 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126660 GIM_CheckIsSafeToFold, /*NumInsns*/2,
126661 // (AArch64fcmge:{ *:[v2i64] } (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm)) => (FACGEv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
126662 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv2f64),
126663 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126664 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
126665 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
126666 GIR_RootConstrainSelectedInstOperands,
126667 // GIR_Coverage, 1163,
126668 GIR_EraseRootFromParent_Done,
126669 // Label 7189: @345489
126670 GIM_Try, /*On fail goto*//*Label 7190*/ GIMT_Encode4(345516), // Rule ID 1204 //
126671 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126672 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126673 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126674 // (AArch64fcmge:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FCMGEv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
126675 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv2f64),
126676 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126677 GIR_RootConstrainSelectedInstOperands,
126678 // GIR_Coverage, 1204,
126679 GIR_Done,
126680 // Label 7190: @345516
126681 GIM_Reject,
126682 // Label 7188: @345517
126683 GIM_Reject,
126684 // Label 7177: @345518
126685 GIM_Try, /*On fail goto*//*Label 7191*/ GIMT_Encode4(345620),
126686 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
126687 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
126688 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126689 GIM_Try, /*On fail goto*//*Label 7192*/ GIMT_Encode4(345592), // Rule ID 1155 //
126690 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
126691 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
126692 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
126693 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
126694 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126695 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
126696 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
126697 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
126698 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126699 GIM_CheckIsSafeToFold, /*NumInsns*/2,
126700 // (AArch64fcmge:{ *:[v4i16] } (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm)) => (FACGEv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
126701 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv4f16),
126702 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126703 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
126704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
126705 GIR_RootConstrainSelectedInstOperands,
126706 // GIR_Coverage, 1155,
126707 GIR_EraseRootFromParent_Done,
126708 // Label 7192: @345592
126709 GIM_Try, /*On fail goto*//*Label 7193*/ GIMT_Encode4(345619), // Rule ID 1200 //
126710 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
126711 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126712 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126713 // (AArch64fcmge:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FCMGEv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
126714 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv4f16),
126715 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126716 GIR_RootConstrainSelectedInstOperands,
126717 // GIR_Coverage, 1200,
126718 GIR_Done,
126719 // Label 7193: @345619
126720 GIM_Reject,
126721 // Label 7191: @345620
126722 GIM_Reject,
126723 // Label 7178: @345621
126724 GIM_Try, /*On fail goto*//*Label 7194*/ GIMT_Encode4(345723),
126725 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
126726 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
126727 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126728 GIM_Try, /*On fail goto*//*Label 7195*/ GIMT_Encode4(345695), // Rule ID 1161 //
126729 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126730 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
126731 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
126732 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
126733 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126734 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
126735 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
126736 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
126737 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126738 GIM_CheckIsSafeToFold, /*NumInsns*/2,
126739 // (AArch64fcmge:{ *:[v4i32] } (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm)) => (FACGEv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
126740 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv4f32),
126741 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
126743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
126744 GIR_RootConstrainSelectedInstOperands,
126745 // GIR_Coverage, 1161,
126746 GIR_EraseRootFromParent_Done,
126747 // Label 7195: @345695
126748 GIM_Try, /*On fail goto*//*Label 7196*/ GIMT_Encode4(345722), // Rule ID 1203 //
126749 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126750 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126751 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126752 // (AArch64fcmge:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FCMGEv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
126753 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv4f32),
126754 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126755 GIR_RootConstrainSelectedInstOperands,
126756 // GIR_Coverage, 1203,
126757 GIR_Done,
126758 // Label 7196: @345722
126759 GIM_Reject,
126760 // Label 7194: @345723
126761 GIM_Reject,
126762 // Label 7179: @345724
126763 GIM_Try, /*On fail goto*//*Label 7197*/ GIMT_Encode4(345826),
126764 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
126765 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
126766 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126767 GIM_Try, /*On fail goto*//*Label 7198*/ GIMT_Encode4(345798), // Rule ID 1157 //
126768 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
126769 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
126770 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
126771 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
126772 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126773 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
126774 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
126775 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
126776 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126777 GIM_CheckIsSafeToFold, /*NumInsns*/2,
126778 // (AArch64fcmge:{ *:[v8i16] } (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm)) => (FACGEv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
126779 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv8f16),
126780 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126781 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
126782 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
126783 GIR_RootConstrainSelectedInstOperands,
126784 // GIR_Coverage, 1157,
126785 GIR_EraseRootFromParent_Done,
126786 // Label 7198: @345798
126787 GIM_Try, /*On fail goto*//*Label 7199*/ GIMT_Encode4(345825), // Rule ID 1201 //
126788 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
126789 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126790 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126791 // (AArch64fcmge:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCMGEv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
126792 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv8f16),
126793 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126794 GIR_RootConstrainSelectedInstOperands,
126795 // GIR_Coverage, 1201,
126796 GIR_Done,
126797 // Label 7199: @345825
126798 GIM_Reject,
126799 // Label 7197: @345826
126800 GIM_Reject,
126801 // Label 7180: @345827
126802 GIM_Reject,
126803 // Label 120: @345828
126804 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(11), /*)*//*default:*//*Label 7206*/ GIMT_Encode4(346057),
126805 /*GILLT_s64*//*Label 7200*/ GIMT_Encode4(345871), GIMT_Encode4(0),
126806 /*GILLT_v2s32*//*Label 7201*/ GIMT_Encode4(345902),
126807 /*GILLT_v2s64*//*Label 7202*/ GIMT_Encode4(345933),
126808 /*GILLT_v4s16*//*Label 7203*/ GIMT_Encode4(345964),
126809 /*GILLT_v4s32*//*Label 7204*/ GIMT_Encode4(345995), GIMT_Encode4(0),
126810 /*GILLT_v8s16*//*Label 7205*/ GIMT_Encode4(346026),
126811 // Label 7200: @345871
126812 GIM_Try, /*On fail goto*//*Label 7207*/ GIMT_Encode4(345901), // Rule ID 4891 //
126813 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126814 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
126815 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126816 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126817 // (AArch64fcmgez:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) => (FCMGEv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
126818 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv1i64rz),
126819 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126820 GIR_RootConstrainSelectedInstOperands,
126821 // GIR_Coverage, 4891,
126822 GIR_Done,
126823 // Label 7207: @345901
126824 GIM_Reject,
126825 // Label 7201: @345902
126826 GIM_Try, /*On fail goto*//*Label 7208*/ GIMT_Encode4(345932), // Rule ID 765 //
126827 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126828 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
126829 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126830 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126831 // (AArch64fcmgez:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCMGEv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
126832 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv2i32rz),
126833 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126834 GIR_RootConstrainSelectedInstOperands,
126835 // GIR_Coverage, 765,
126836 GIR_Done,
126837 // Label 7208: @345932
126838 GIM_Reject,
126839 // Label 7202: @345933
126840 GIM_Try, /*On fail goto*//*Label 7209*/ GIMT_Encode4(345963), // Rule ID 767 //
126841 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126842 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
126843 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126844 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126845 // (AArch64fcmgez:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCMGEv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
126846 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv2i64rz),
126847 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126848 GIR_RootConstrainSelectedInstOperands,
126849 // GIR_Coverage, 767,
126850 GIR_Done,
126851 // Label 7209: @345963
126852 GIM_Reject,
126853 // Label 7203: @345964
126854 GIM_Try, /*On fail goto*//*Label 7210*/ GIMT_Encode4(345994), // Rule ID 763 //
126855 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
126856 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
126857 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126858 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126859 // (AArch64fcmgez:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCMGEv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
126860 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv4i16rz),
126861 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126862 GIR_RootConstrainSelectedInstOperands,
126863 // GIR_Coverage, 763,
126864 GIR_Done,
126865 // Label 7210: @345994
126866 GIM_Reject,
126867 // Label 7204: @345995
126868 GIM_Try, /*On fail goto*//*Label 7211*/ GIMT_Encode4(346025), // Rule ID 766 //
126869 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126870 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
126871 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126872 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126873 // (AArch64fcmgez:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCMGEv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
126874 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv4i32rz),
126875 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126876 GIR_RootConstrainSelectedInstOperands,
126877 // GIR_Coverage, 766,
126878 GIR_Done,
126879 // Label 7211: @346025
126880 GIM_Reject,
126881 // Label 7205: @346026
126882 GIM_Try, /*On fail goto*//*Label 7212*/ GIMT_Encode4(346056), // Rule ID 764 //
126883 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
126884 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
126885 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126886 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126887 // (AArch64fcmgez:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCMGEv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
126888 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv8i16rz),
126889 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126890 GIR_RootConstrainSelectedInstOperands,
126891 // GIR_Coverage, 764,
126892 GIR_Done,
126893 // Label 7212: @346056
126894 GIM_Reject,
126895 // Label 7206: @346057
126896 GIM_Reject,
126897 // Label 121: @346058
126898 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 7220*/ GIMT_Encode4(346721),
126899 /*GILLT_s32*//*Label 7213*/ GIMT_Encode4(346105),
126900 /*GILLT_s64*//*Label 7214*/ GIMT_Encode4(346143), GIMT_Encode4(0),
126901 /*GILLT_v2s32*//*Label 7215*/ GIMT_Encode4(346206),
126902 /*GILLT_v2s64*//*Label 7216*/ GIMT_Encode4(346309),
126903 /*GILLT_v4s16*//*Label 7217*/ GIMT_Encode4(346412),
126904 /*GILLT_v4s32*//*Label 7218*/ GIMT_Encode4(346515), GIMT_Encode4(0),
126905 /*GILLT_v8s16*//*Label 7219*/ GIMT_Encode4(346618),
126906 // Label 7213: @346105
126907 GIM_Try, /*On fail goto*//*Label 7221*/ GIMT_Encode4(346142), // Rule ID 1613 //
126908 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126909 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
126910 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
126911 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
126912 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
126913 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
126914 // (AArch64fcmgt:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm) => (FCMGT32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
126915 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGT32),
126916 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126917 GIR_RootConstrainSelectedInstOperands,
126918 // GIR_Coverage, 1613,
126919 GIR_Done,
126920 // Label 7221: @346142
126921 GIM_Reject,
126922 // Label 7214: @346143
126923 GIM_Try, /*On fail goto*//*Label 7222*/ GIMT_Encode4(346205),
126924 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
126925 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
126926 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126927 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126928 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126929 GIM_Try, /*On fail goto*//*Label 7223*/ GIMT_Encode4(346185), // Rule ID 1612 //
126930 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126931 // (AArch64fcmgt:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm) => (FCMGT64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
126932 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGT64),
126933 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126934 GIR_RootConstrainSelectedInstOperands,
126935 // GIR_Coverage, 1612,
126936 GIR_Done,
126937 // Label 7223: @346185
126938 GIM_Try, /*On fail goto*//*Label 7224*/ GIMT_Encode4(346204), // Rule ID 4862 //
126939 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126940 // (AArch64fcmgt:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm) => (FCMGT64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
126941 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGT64),
126942 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126943 GIR_RootConstrainSelectedInstOperands,
126944 // GIR_Coverage, 4862,
126945 GIR_Done,
126946 // Label 7224: @346204
126947 GIM_Reject,
126948 // Label 7222: @346205
126949 GIM_Reject,
126950 // Label 7215: @346206
126951 GIM_Try, /*On fail goto*//*Label 7225*/ GIMT_Encode4(346308),
126952 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
126953 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
126954 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126955 GIM_Try, /*On fail goto*//*Label 7226*/ GIMT_Encode4(346280), // Rule ID 1169 //
126956 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126957 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
126958 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
126959 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
126960 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126961 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
126962 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
126963 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
126964 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126965 GIM_CheckIsSafeToFold, /*NumInsns*/2,
126966 // (AArch64fcmgt:{ *:[v2i32] } (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm)) => (FACGTv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
126967 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv2f32),
126968 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
126969 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
126970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
126971 GIR_RootConstrainSelectedInstOperands,
126972 // GIR_Coverage, 1169,
126973 GIR_EraseRootFromParent_Done,
126974 // Label 7226: @346280
126975 GIM_Try, /*On fail goto*//*Label 7227*/ GIMT_Encode4(346307), // Rule ID 1207 //
126976 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126977 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126978 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
126979 // (AArch64fcmgt:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (FCMGTv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
126980 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv2f32),
126981 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
126982 GIR_RootConstrainSelectedInstOperands,
126983 // GIR_Coverage, 1207,
126984 GIR_Done,
126985 // Label 7227: @346307
126986 GIM_Reject,
126987 // Label 7225: @346308
126988 GIM_Reject,
126989 // Label 7216: @346309
126990 GIM_Try, /*On fail goto*//*Label 7228*/ GIMT_Encode4(346411),
126991 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
126992 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
126993 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
126994 GIM_Try, /*On fail goto*//*Label 7229*/ GIMT_Encode4(346383), // Rule ID 1173 //
126995 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
126996 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
126997 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
126998 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
126999 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127000 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
127001 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
127002 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
127003 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127004 GIM_CheckIsSafeToFold, /*NumInsns*/2,
127005 // (AArch64fcmgt:{ *:[v2i64] } (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm)) => (FACGTv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
127006 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv2f64),
127007 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
127008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
127009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
127010 GIR_RootConstrainSelectedInstOperands,
127011 // GIR_Coverage, 1173,
127012 GIR_EraseRootFromParent_Done,
127013 // Label 7229: @346383
127014 GIM_Try, /*On fail goto*//*Label 7230*/ GIMT_Encode4(346410), // Rule ID 1209 //
127015 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127016 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127017 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127018 // (AArch64fcmgt:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (FCMGTv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
127019 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv2f64),
127020 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127021 GIR_RootConstrainSelectedInstOperands,
127022 // GIR_Coverage, 1209,
127023 GIR_Done,
127024 // Label 7230: @346410
127025 GIM_Reject,
127026 // Label 7228: @346411
127027 GIM_Reject,
127028 // Label 7217: @346412
127029 GIM_Try, /*On fail goto*//*Label 7231*/ GIMT_Encode4(346514),
127030 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
127031 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
127032 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127033 GIM_Try, /*On fail goto*//*Label 7232*/ GIMT_Encode4(346486), // Rule ID 1165 //
127034 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
127035 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
127036 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
127037 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
127038 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127039 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
127040 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
127041 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
127042 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127043 GIM_CheckIsSafeToFold, /*NumInsns*/2,
127044 // (AArch64fcmgt:{ *:[v4i16] } (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm)) => (FACGTv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
127045 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv4f16),
127046 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
127047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
127048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
127049 GIR_RootConstrainSelectedInstOperands,
127050 // GIR_Coverage, 1165,
127051 GIR_EraseRootFromParent_Done,
127052 // Label 7232: @346486
127053 GIM_Try, /*On fail goto*//*Label 7233*/ GIMT_Encode4(346513), // Rule ID 1205 //
127054 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
127055 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127056 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127057 // (AArch64fcmgt:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (FCMGTv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
127058 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv4f16),
127059 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127060 GIR_RootConstrainSelectedInstOperands,
127061 // GIR_Coverage, 1205,
127062 GIR_Done,
127063 // Label 7233: @346513
127064 GIM_Reject,
127065 // Label 7231: @346514
127066 GIM_Reject,
127067 // Label 7218: @346515
127068 GIM_Try, /*On fail goto*//*Label 7234*/ GIMT_Encode4(346617),
127069 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
127070 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
127071 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127072 GIM_Try, /*On fail goto*//*Label 7235*/ GIMT_Encode4(346589), // Rule ID 1171 //
127073 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127074 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
127075 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
127076 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
127077 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127078 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
127079 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
127080 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
127081 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127082 GIM_CheckIsSafeToFold, /*NumInsns*/2,
127083 // (AArch64fcmgt:{ *:[v4i32] } (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm)) => (FACGTv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
127084 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv4f32),
127085 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
127086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
127087 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
127088 GIR_RootConstrainSelectedInstOperands,
127089 // GIR_Coverage, 1171,
127090 GIR_EraseRootFromParent_Done,
127091 // Label 7235: @346589
127092 GIM_Try, /*On fail goto*//*Label 7236*/ GIMT_Encode4(346616), // Rule ID 1208 //
127093 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127094 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127095 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127096 // (AArch64fcmgt:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (FCMGTv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
127097 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv4f32),
127098 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127099 GIR_RootConstrainSelectedInstOperands,
127100 // GIR_Coverage, 1208,
127101 GIR_Done,
127102 // Label 7236: @346616
127103 GIM_Reject,
127104 // Label 7234: @346617
127105 GIM_Reject,
127106 // Label 7219: @346618
127107 GIM_Try, /*On fail goto*//*Label 7237*/ GIMT_Encode4(346720),
127108 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
127109 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
127110 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127111 GIM_Try, /*On fail goto*//*Label 7238*/ GIMT_Encode4(346692), // Rule ID 1167 //
127112 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
127113 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
127114 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
127115 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
127116 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127117 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
127118 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
127119 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
127120 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127121 GIM_CheckIsSafeToFold, /*NumInsns*/2,
127122 // (AArch64fcmgt:{ *:[v8i16] } (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm)) => (FACGTv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
127123 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv8f16),
127124 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
127125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
127126 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
127127 GIR_RootConstrainSelectedInstOperands,
127128 // GIR_Coverage, 1167,
127129 GIR_EraseRootFromParent_Done,
127130 // Label 7238: @346692
127131 GIM_Try, /*On fail goto*//*Label 7239*/ GIMT_Encode4(346719), // Rule ID 1206 //
127132 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
127133 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127134 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127135 // (AArch64fcmgt:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (FCMGTv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
127136 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv8f16),
127137 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127138 GIR_RootConstrainSelectedInstOperands,
127139 // GIR_Coverage, 1206,
127140 GIR_Done,
127141 // Label 7239: @346719
127142 GIM_Reject,
127143 // Label 7237: @346720
127144 GIM_Reject,
127145 // Label 7220: @346721
127146 GIM_Reject,
127147 // Label 122: @346722
127148 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(11), /*)*//*default:*//*Label 7246*/ GIMT_Encode4(346951),
127149 /*GILLT_s64*//*Label 7240*/ GIMT_Encode4(346765), GIMT_Encode4(0),
127150 /*GILLT_v2s32*//*Label 7241*/ GIMT_Encode4(346796),
127151 /*GILLT_v2s64*//*Label 7242*/ GIMT_Encode4(346827),
127152 /*GILLT_v4s16*//*Label 7243*/ GIMT_Encode4(346858),
127153 /*GILLT_v4s32*//*Label 7244*/ GIMT_Encode4(346889), GIMT_Encode4(0),
127154 /*GILLT_v8s16*//*Label 7245*/ GIMT_Encode4(346920),
127155 // Label 7240: @346765
127156 GIM_Try, /*On fail goto*//*Label 7247*/ GIMT_Encode4(346795), // Rule ID 4892 //
127157 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127158 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
127159 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127160 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127161 // (AArch64fcmgtz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) => (FCMGTv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
127162 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv1i64rz),
127163 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127164 GIR_RootConstrainSelectedInstOperands,
127165 // GIR_Coverage, 4892,
127166 GIR_Done,
127167 // Label 7247: @346795
127168 GIM_Reject,
127169 // Label 7241: @346796
127170 GIM_Try, /*On fail goto*//*Label 7248*/ GIMT_Encode4(346826), // Rule ID 770 //
127171 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127172 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
127173 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127174 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127175 // (AArch64fcmgtz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCMGTv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
127176 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv2i32rz),
127177 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127178 GIR_RootConstrainSelectedInstOperands,
127179 // GIR_Coverage, 770,
127180 GIR_Done,
127181 // Label 7248: @346826
127182 GIM_Reject,
127183 // Label 7242: @346827
127184 GIM_Try, /*On fail goto*//*Label 7249*/ GIMT_Encode4(346857), // Rule ID 772 //
127185 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127186 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
127187 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127188 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127189 // (AArch64fcmgtz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCMGTv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
127190 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv2i64rz),
127191 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127192 GIR_RootConstrainSelectedInstOperands,
127193 // GIR_Coverage, 772,
127194 GIR_Done,
127195 // Label 7249: @346857
127196 GIM_Reject,
127197 // Label 7243: @346858
127198 GIM_Try, /*On fail goto*//*Label 7250*/ GIMT_Encode4(346888), // Rule ID 768 //
127199 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
127200 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
127201 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127202 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127203 // (AArch64fcmgtz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCMGTv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
127204 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv4i16rz),
127205 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127206 GIR_RootConstrainSelectedInstOperands,
127207 // GIR_Coverage, 768,
127208 GIR_Done,
127209 // Label 7250: @346888
127210 GIM_Reject,
127211 // Label 7244: @346889
127212 GIM_Try, /*On fail goto*//*Label 7251*/ GIMT_Encode4(346919), // Rule ID 771 //
127213 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127214 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
127215 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127216 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127217 // (AArch64fcmgtz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCMGTv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
127218 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv4i32rz),
127219 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127220 GIR_RootConstrainSelectedInstOperands,
127221 // GIR_Coverage, 771,
127222 GIR_Done,
127223 // Label 7251: @346919
127224 GIM_Reject,
127225 // Label 7245: @346920
127226 GIM_Try, /*On fail goto*//*Label 7252*/ GIMT_Encode4(346950), // Rule ID 769 //
127227 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
127228 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
127229 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127230 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127231 // (AArch64fcmgtz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCMGTv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
127232 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv8i16rz),
127233 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127234 GIR_RootConstrainSelectedInstOperands,
127235 // GIR_Coverage, 769,
127236 GIR_Done,
127237 // Label 7252: @346950
127238 GIM_Reject,
127239 // Label 7246: @346951
127240 GIM_Reject,
127241 // Label 123: @346952
127242 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(11), /*)*//*default:*//*Label 7259*/ GIMT_Encode4(347181),
127243 /*GILLT_s64*//*Label 7253*/ GIMT_Encode4(346995), GIMT_Encode4(0),
127244 /*GILLT_v2s32*//*Label 7254*/ GIMT_Encode4(347026),
127245 /*GILLT_v2s64*//*Label 7255*/ GIMT_Encode4(347057),
127246 /*GILLT_v4s16*//*Label 7256*/ GIMT_Encode4(347088),
127247 /*GILLT_v4s32*//*Label 7257*/ GIMT_Encode4(347119), GIMT_Encode4(0),
127248 /*GILLT_v8s16*//*Label 7258*/ GIMT_Encode4(347150),
127249 // Label 7253: @346995
127250 GIM_Try, /*On fail goto*//*Label 7260*/ GIMT_Encode4(347025), // Rule ID 4893 //
127251 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127252 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
127253 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127254 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127255 // (AArch64fcmlez:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) => (FCMLEv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
127256 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMLEv1i64rz),
127257 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127258 GIR_RootConstrainSelectedInstOperands,
127259 // GIR_Coverage, 4893,
127260 GIR_Done,
127261 // Label 7260: @347025
127262 GIM_Reject,
127263 // Label 7254: @347026
127264 GIM_Try, /*On fail goto*//*Label 7261*/ GIMT_Encode4(347056), // Rule ID 775 //
127265 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127266 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
127267 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127268 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127269 // (AArch64fcmlez:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCMLEv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
127270 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMLEv2i32rz),
127271 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127272 GIR_RootConstrainSelectedInstOperands,
127273 // GIR_Coverage, 775,
127274 GIR_Done,
127275 // Label 7261: @347056
127276 GIM_Reject,
127277 // Label 7255: @347057
127278 GIM_Try, /*On fail goto*//*Label 7262*/ GIMT_Encode4(347087), // Rule ID 777 //
127279 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127280 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
127281 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127282 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127283 // (AArch64fcmlez:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCMLEv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
127284 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMLEv2i64rz),
127285 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127286 GIR_RootConstrainSelectedInstOperands,
127287 // GIR_Coverage, 777,
127288 GIR_Done,
127289 // Label 7262: @347087
127290 GIM_Reject,
127291 // Label 7256: @347088
127292 GIM_Try, /*On fail goto*//*Label 7263*/ GIMT_Encode4(347118), // Rule ID 773 //
127293 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
127294 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
127295 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127296 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127297 // (AArch64fcmlez:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCMLEv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
127298 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMLEv4i16rz),
127299 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127300 GIR_RootConstrainSelectedInstOperands,
127301 // GIR_Coverage, 773,
127302 GIR_Done,
127303 // Label 7263: @347118
127304 GIM_Reject,
127305 // Label 7257: @347119
127306 GIM_Try, /*On fail goto*//*Label 7264*/ GIMT_Encode4(347149), // Rule ID 776 //
127307 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127308 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
127309 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127310 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127311 // (AArch64fcmlez:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCMLEv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
127312 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMLEv4i32rz),
127313 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127314 GIR_RootConstrainSelectedInstOperands,
127315 // GIR_Coverage, 776,
127316 GIR_Done,
127317 // Label 7264: @347149
127318 GIM_Reject,
127319 // Label 7258: @347150
127320 GIM_Try, /*On fail goto*//*Label 7265*/ GIMT_Encode4(347180), // Rule ID 774 //
127321 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
127322 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
127323 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127324 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127325 // (AArch64fcmlez:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCMLEv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
127326 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMLEv8i16rz),
127327 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127328 GIR_RootConstrainSelectedInstOperands,
127329 // GIR_Coverage, 774,
127330 GIR_Done,
127331 // Label 7265: @347180
127332 GIM_Reject,
127333 // Label 7259: @347181
127334 GIM_Reject,
127335 // Label 124: @347182
127336 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(11), /*)*//*default:*//*Label 7272*/ GIMT_Encode4(347411),
127337 /*GILLT_s64*//*Label 7266*/ GIMT_Encode4(347225), GIMT_Encode4(0),
127338 /*GILLT_v2s32*//*Label 7267*/ GIMT_Encode4(347256),
127339 /*GILLT_v2s64*//*Label 7268*/ GIMT_Encode4(347287),
127340 /*GILLT_v4s16*//*Label 7269*/ GIMT_Encode4(347318),
127341 /*GILLT_v4s32*//*Label 7270*/ GIMT_Encode4(347349), GIMT_Encode4(0),
127342 /*GILLT_v8s16*//*Label 7271*/ GIMT_Encode4(347380),
127343 // Label 7266: @347225
127344 GIM_Try, /*On fail goto*//*Label 7273*/ GIMT_Encode4(347255), // Rule ID 4894 //
127345 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127346 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
127347 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127348 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127349 // (AArch64fcmltz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn) => (FCMLTv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
127350 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMLTv1i64rz),
127351 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127352 GIR_RootConstrainSelectedInstOperands,
127353 // GIR_Coverage, 4894,
127354 GIR_Done,
127355 // Label 7273: @347255
127356 GIM_Reject,
127357 // Label 7267: @347256
127358 GIM_Try, /*On fail goto*//*Label 7274*/ GIMT_Encode4(347286), // Rule ID 780 //
127359 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127360 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
127361 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127362 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127363 // (AArch64fcmltz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn) => (FCMLTv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
127364 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMLTv2i32rz),
127365 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127366 GIR_RootConstrainSelectedInstOperands,
127367 // GIR_Coverage, 780,
127368 GIR_Done,
127369 // Label 7274: @347286
127370 GIM_Reject,
127371 // Label 7268: @347287
127372 GIM_Try, /*On fail goto*//*Label 7275*/ GIMT_Encode4(347317), // Rule ID 782 //
127373 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127374 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
127375 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127376 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127377 // (AArch64fcmltz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn) => (FCMLTv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
127378 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMLTv2i64rz),
127379 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127380 GIR_RootConstrainSelectedInstOperands,
127381 // GIR_Coverage, 782,
127382 GIR_Done,
127383 // Label 7275: @347317
127384 GIM_Reject,
127385 // Label 7269: @347318
127386 GIM_Try, /*On fail goto*//*Label 7276*/ GIMT_Encode4(347348), // Rule ID 778 //
127387 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
127388 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
127389 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127390 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127391 // (AArch64fcmltz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn) => (FCMLTv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
127392 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMLTv4i16rz),
127393 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127394 GIR_RootConstrainSelectedInstOperands,
127395 // GIR_Coverage, 778,
127396 GIR_Done,
127397 // Label 7276: @347348
127398 GIM_Reject,
127399 // Label 7270: @347349
127400 GIM_Try, /*On fail goto*//*Label 7277*/ GIMT_Encode4(347379), // Rule ID 781 //
127401 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127402 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
127403 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127404 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127405 // (AArch64fcmltz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn) => (FCMLTv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
127406 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMLTv4i32rz),
127407 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127408 GIR_RootConstrainSelectedInstOperands,
127409 // GIR_Coverage, 781,
127410 GIR_Done,
127411 // Label 7277: @347379
127412 GIM_Reject,
127413 // Label 7271: @347380
127414 GIM_Try, /*On fail goto*//*Label 7278*/ GIMT_Encode4(347410), // Rule ID 779 //
127415 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
127416 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
127417 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127418 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127419 // (AArch64fcmltz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn) => (FCMLTv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
127420 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMLTv8i16rz),
127421 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
127422 GIR_RootConstrainSelectedInstOperands,
127423 // GIR_Coverage, 779,
127424 GIR_Done,
127425 // Label 7278: @347410
127426 GIM_Reject,
127427 // Label 7272: @347411
127428 GIM_Reject,
127429 // Label 125: @347412
127430 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(12), /*)*//*default:*//*Label 7281*/ GIMT_Encode4(347489),
127431 /*GILLT_v8s8*//*Label 7279*/ GIMT_Encode4(347435), GIMT_Encode4(0),
127432 /*GILLT_v16s8*//*Label 7280*/ GIMT_Encode4(347462),
127433 // Label 7279: @347435
127434 GIM_Try, /*On fail goto*//*Label 7282*/ GIMT_Encode4(347461), // Rule ID 963 //
127435 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127436 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
127437 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127438 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127439 // (AArch64rev16:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (REV16v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
127440 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
127441 GIR_RootConstrainSelectedInstOperands,
127442 // GIR_Coverage, 963,
127443 GIR_Done,
127444 // Label 7282: @347461
127445 GIM_Reject,
127446 // Label 7280: @347462
127447 GIM_Try, /*On fail goto*//*Label 7283*/ GIMT_Encode4(347488), // Rule ID 964 //
127448 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127449 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
127450 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127451 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127452 // (AArch64rev16:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (REV16v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
127453 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
127454 GIR_RootConstrainSelectedInstOperands,
127455 // GIR_Coverage, 964,
127456 GIR_Done,
127457 // Label 7283: @347488
127458 GIM_Reject,
127459 // Label 7281: @347489
127460 GIM_Reject,
127461 // Label 126: @347490
127462 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 7288*/ GIMT_Encode4(347689),
127463 /*GILLT_v4s16*//*Label 7284*/ GIMT_Encode4(347521), GIMT_Encode4(0),
127464 /*GILLT_v8s8*//*Label 7285*/ GIMT_Encode4(347578),
127465 /*GILLT_v8s16*//*Label 7286*/ GIMT_Encode4(347605),
127466 /*GILLT_v16s8*//*Label 7287*/ GIMT_Encode4(347662),
127467 // Label 7284: @347521
127468 GIM_Try, /*On fail goto*//*Label 7289*/ GIMT_Encode4(347577),
127469 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
127470 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127471 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127472 GIM_Try, /*On fail goto*//*Label 7290*/ GIMT_Encode4(347552), // Rule ID 967 //
127473 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127474 // (AArch64rev32:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) => (REV32v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
127475 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
127476 GIR_RootConstrainSelectedInstOperands,
127477 // GIR_Coverage, 967,
127478 GIR_Done,
127479 // Label 7290: @347552
127480 GIM_Try, /*On fail goto*//*Label 7291*/ GIMT_Encode4(347564), // Rule ID 4612 //
127481 // (AArch64rev32:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (REV32v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
127482 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
127483 GIR_RootConstrainSelectedInstOperands,
127484 // GIR_Coverage, 4612,
127485 GIR_Done,
127486 // Label 7291: @347564
127487 GIM_Try, /*On fail goto*//*Label 7292*/ GIMT_Encode4(347576), // Rule ID 4614 //
127488 // (AArch64rev32:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn) => (REV32v4i16:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn)
127489 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
127490 GIR_RootConstrainSelectedInstOperands,
127491 // GIR_Coverage, 4614,
127492 GIR_Done,
127493 // Label 7292: @347576
127494 GIM_Reject,
127495 // Label 7289: @347577
127496 GIM_Reject,
127497 // Label 7285: @347578
127498 GIM_Try, /*On fail goto*//*Label 7293*/ GIMT_Encode4(347604), // Rule ID 965 //
127499 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127500 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
127501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127502 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127503 // (AArch64rev32:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (REV32v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
127504 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i8),
127505 GIR_RootConstrainSelectedInstOperands,
127506 // GIR_Coverage, 965,
127507 GIR_Done,
127508 // Label 7293: @347604
127509 GIM_Reject,
127510 // Label 7286: @347605
127511 GIM_Try, /*On fail goto*//*Label 7294*/ GIMT_Encode4(347661),
127512 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
127513 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127514 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127515 GIM_Try, /*On fail goto*//*Label 7295*/ GIMT_Encode4(347636), // Rule ID 968 //
127516 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127517 // (AArch64rev32:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) => (REV32v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
127518 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
127519 GIR_RootConstrainSelectedInstOperands,
127520 // GIR_Coverage, 968,
127521 GIR_Done,
127522 // Label 7295: @347636
127523 GIM_Try, /*On fail goto*//*Label 7296*/ GIMT_Encode4(347648), // Rule ID 4616 //
127524 // (AArch64rev32:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (REV32v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
127525 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
127526 GIR_RootConstrainSelectedInstOperands,
127527 // GIR_Coverage, 4616,
127528 GIR_Done,
127529 // Label 7296: @347648
127530 GIM_Try, /*On fail goto*//*Label 7297*/ GIMT_Encode4(347660), // Rule ID 4618 //
127531 // (AArch64rev32:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (REV32v8i16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn)
127532 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
127533 GIR_RootConstrainSelectedInstOperands,
127534 // GIR_Coverage, 4618,
127535 GIR_Done,
127536 // Label 7297: @347660
127537 GIM_Reject,
127538 // Label 7294: @347661
127539 GIM_Reject,
127540 // Label 7287: @347662
127541 GIM_Try, /*On fail goto*//*Label 7298*/ GIMT_Encode4(347688), // Rule ID 966 //
127542 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127543 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
127544 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127545 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127546 // (AArch64rev32:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (REV32v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
127547 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v16i8),
127548 GIR_RootConstrainSelectedInstOperands,
127549 // GIR_Coverage, 966,
127550 GIR_Done,
127551 // Label 7298: @347688
127552 GIM_Reject,
127553 // Label 7288: @347689
127554 GIM_Reject,
127555 // Label 127: @347690
127556 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(12), /*)*//*default:*//*Label 7305*/ GIMT_Encode4(347987),
127557 /*GILLT_v2s32*//*Label 7299*/ GIMT_Encode4(347729), GIMT_Encode4(0),
127558 /*GILLT_v4s16*//*Label 7300*/ GIMT_Encode4(347774),
127559 /*GILLT_v4s32*//*Label 7301*/ GIMT_Encode4(347831),
127560 /*GILLT_v8s8*//*Label 7302*/ GIMT_Encode4(347876),
127561 /*GILLT_v8s16*//*Label 7303*/ GIMT_Encode4(347903),
127562 /*GILLT_v16s8*//*Label 7304*/ GIMT_Encode4(347960),
127563 // Label 7299: @347729
127564 GIM_Try, /*On fail goto*//*Label 7306*/ GIMT_Encode4(347773),
127565 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
127566 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127567 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127568 GIM_Try, /*On fail goto*//*Label 7307*/ GIMT_Encode4(347760), // Rule ID 973 //
127569 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127570 // (AArch64rev64:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn) => (REV64v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
127571 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
127572 GIR_RootConstrainSelectedInstOperands,
127573 // GIR_Coverage, 973,
127574 GIR_Done,
127575 // Label 7307: @347760
127576 GIM_Try, /*On fail goto*//*Label 7308*/ GIMT_Encode4(347772), // Rule ID 4620 //
127577 // (AArch64rev64:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn) => (REV64v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
127578 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
127579 GIR_RootConstrainSelectedInstOperands,
127580 // GIR_Coverage, 4620,
127581 GIR_Done,
127582 // Label 7308: @347772
127583 GIM_Reject,
127584 // Label 7306: @347773
127585 GIM_Reject,
127586 // Label 7300: @347774
127587 GIM_Try, /*On fail goto*//*Label 7309*/ GIMT_Encode4(347830),
127588 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
127589 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127590 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127591 GIM_Try, /*On fail goto*//*Label 7310*/ GIMT_Encode4(347805), // Rule ID 971 //
127592 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127593 // (AArch64rev64:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn) => (REV64v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
127594 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
127595 GIR_RootConstrainSelectedInstOperands,
127596 // GIR_Coverage, 971,
127597 GIR_Done,
127598 // Label 7310: @347805
127599 GIM_Try, /*On fail goto*//*Label 7311*/ GIMT_Encode4(347817), // Rule ID 4613 //
127600 // (AArch64rev64:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn) => (REV64v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
127601 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
127602 GIR_RootConstrainSelectedInstOperands,
127603 // GIR_Coverage, 4613,
127604 GIR_Done,
127605 // Label 7311: @347817
127606 GIM_Try, /*On fail goto*//*Label 7312*/ GIMT_Encode4(347829), // Rule ID 4615 //
127607 // (AArch64rev64:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn) => (REV64v4i16:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn)
127608 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
127609 GIR_RootConstrainSelectedInstOperands,
127610 // GIR_Coverage, 4615,
127611 GIR_Done,
127612 // Label 7312: @347829
127613 GIM_Reject,
127614 // Label 7309: @347830
127615 GIM_Reject,
127616 // Label 7301: @347831
127617 GIM_Try, /*On fail goto*//*Label 7313*/ GIMT_Encode4(347875),
127618 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
127619 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127620 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127621 GIM_Try, /*On fail goto*//*Label 7314*/ GIMT_Encode4(347862), // Rule ID 974 //
127622 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127623 // (AArch64rev64:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn) => (REV64v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
127624 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
127625 GIR_RootConstrainSelectedInstOperands,
127626 // GIR_Coverage, 974,
127627 GIR_Done,
127628 // Label 7314: @347862
127629 GIM_Try, /*On fail goto*//*Label 7315*/ GIMT_Encode4(347874), // Rule ID 4621 //
127630 // (AArch64rev64:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn) => (REV64v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
127631 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
127632 GIR_RootConstrainSelectedInstOperands,
127633 // GIR_Coverage, 4621,
127634 GIR_Done,
127635 // Label 7315: @347874
127636 GIM_Reject,
127637 // Label 7313: @347875
127638 GIM_Reject,
127639 // Label 7302: @347876
127640 GIM_Try, /*On fail goto*//*Label 7316*/ GIMT_Encode4(347902), // Rule ID 969 //
127641 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127642 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
127643 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127644 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127645 // (AArch64rev64:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn) => (REV64v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
127646 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
127647 GIR_RootConstrainSelectedInstOperands,
127648 // GIR_Coverage, 969,
127649 GIR_Done,
127650 // Label 7316: @347902
127651 GIM_Reject,
127652 // Label 7303: @347903
127653 GIM_Try, /*On fail goto*//*Label 7317*/ GIMT_Encode4(347959),
127654 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
127655 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127656 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127657 GIM_Try, /*On fail goto*//*Label 7318*/ GIMT_Encode4(347934), // Rule ID 972 //
127658 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127659 // (AArch64rev64:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn) => (REV64v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
127660 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
127661 GIR_RootConstrainSelectedInstOperands,
127662 // GIR_Coverage, 972,
127663 GIR_Done,
127664 // Label 7318: @347934
127665 GIM_Try, /*On fail goto*//*Label 7319*/ GIMT_Encode4(347946), // Rule ID 4617 //
127666 // (AArch64rev64:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn) => (REV64v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
127667 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
127668 GIR_RootConstrainSelectedInstOperands,
127669 // GIR_Coverage, 4617,
127670 GIR_Done,
127671 // Label 7319: @347946
127672 GIM_Try, /*On fail goto*//*Label 7320*/ GIMT_Encode4(347958), // Rule ID 4619 //
127673 // (AArch64rev64:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn) => (REV64v8i16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn)
127674 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
127675 GIR_RootConstrainSelectedInstOperands,
127676 // GIR_Coverage, 4619,
127677 GIR_Done,
127678 // Label 7320: @347958
127679 GIM_Reject,
127680 // Label 7317: @347959
127681 GIM_Reject,
127682 // Label 7304: @347960
127683 GIM_Try, /*On fail goto*//*Label 7321*/ GIMT_Encode4(347986), // Rule ID 970 //
127684 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127685 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
127686 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127687 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127688 // (AArch64rev64:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn) => (REV64v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
127689 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
127690 GIR_RootConstrainSelectedInstOperands,
127691 // GIR_Coverage, 970,
127692 GIR_Done,
127693 // Label 7321: @347986
127694 GIM_Reject,
127695 // Label 7305: @347987
127696 GIM_Reject,
127697 // Label 128: @347988
127698 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(11), /*)*//*default:*//*Label 7328*/ GIMT_Encode4(348193),
127699 /*GILLT_s64*//*Label 7322*/ GIMT_Encode4(348031), GIMT_Encode4(0),
127700 /*GILLT_v2s32*//*Label 7323*/ GIMT_Encode4(348058),
127701 /*GILLT_v2s64*//*Label 7324*/ GIMT_Encode4(348085),
127702 /*GILLT_v4s16*//*Label 7325*/ GIMT_Encode4(348112),
127703 /*GILLT_v4s32*//*Label 7326*/ GIMT_Encode4(348139), GIMT_Encode4(0),
127704 /*GILLT_v8s16*//*Label 7327*/ GIMT_Encode4(348166),
127705 // Label 7322: @348031
127706 GIM_Try, /*On fail goto*//*Label 7329*/ GIMT_Encode4(348057), // Rule ID 995 //
127707 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127708 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
127709 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127710 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127711 // (AArch64saddlp_n:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn) => (SADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn)
127712 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv2i32_v1i64),
127713 GIR_RootConstrainSelectedInstOperands,
127714 // GIR_Coverage, 995,
127715 GIR_Done,
127716 // Label 7329: @348057
127717 GIM_Reject,
127718 // Label 7323: @348058
127719 GIM_Try, /*On fail goto*//*Label 7330*/ GIMT_Encode4(348084), // Rule ID 991 //
127720 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127721 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
127722 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127723 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127724 // (AArch64saddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn) => (SADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)
127725 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv4i16_v2i32),
127726 GIR_RootConstrainSelectedInstOperands,
127727 // GIR_Coverage, 991,
127728 GIR_Done,
127729 // Label 7330: @348084
127730 GIM_Reject,
127731 // Label 7324: @348085
127732 GIM_Try, /*On fail goto*//*Label 7331*/ GIMT_Encode4(348111), // Rule ID 997 //
127733 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127734 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
127735 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127736 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127737 // (AArch64saddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn) => (SADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)
127738 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv4i32_v2i64),
127739 GIR_RootConstrainSelectedInstOperands,
127740 // GIR_Coverage, 997,
127741 GIR_Done,
127742 // Label 7331: @348111
127743 GIM_Reject,
127744 // Label 7325: @348112
127745 GIM_Try, /*On fail goto*//*Label 7332*/ GIMT_Encode4(348138), // Rule ID 987 //
127746 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127747 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
127748 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127749 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127750 // (AArch64saddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn) => (SADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)
127751 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv8i8_v4i16),
127752 GIR_RootConstrainSelectedInstOperands,
127753 // GIR_Coverage, 987,
127754 GIR_Done,
127755 // Label 7332: @348138
127756 GIM_Reject,
127757 // Label 7326: @348139
127758 GIM_Try, /*On fail goto*//*Label 7333*/ GIMT_Encode4(348165), // Rule ID 993 //
127759 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127760 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
127761 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127762 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127763 // (AArch64saddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn) => (SADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)
127764 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv8i16_v4i32),
127765 GIR_RootConstrainSelectedInstOperands,
127766 // GIR_Coverage, 993,
127767 GIR_Done,
127768 // Label 7333: @348165
127769 GIM_Reject,
127770 // Label 7327: @348166
127771 GIM_Try, /*On fail goto*//*Label 7334*/ GIMT_Encode4(348192), // Rule ID 989 //
127772 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
127773 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
127774 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127775 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127776 // (AArch64saddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn) => (SADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)
127777 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv16i8_v8i16),
127778 GIR_RootConstrainSelectedInstOperands,
127779 // GIR_Coverage, 989,
127780 GIR_Done,
127781 // Label 7334: @348192
127782 GIM_Reject,
127783 // Label 7328: @348193
127784 GIM_Reject,
127785 // Label 129: @348194
127786 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(9), /*)*//*default:*//*Label 7337*/ GIMT_Encode4(348514),
127787 /*GILLT_v2s64*//*Label 7335*/ GIMT_Encode4(348217), GIMT_Encode4(0),
127788 /*GILLT_v4s32*//*Label 7336*/ GIMT_Encode4(348277),
127789 // Label 7335: @348217
127790 GIM_Try, /*On fail goto*//*Label 7338*/ GIMT_Encode4(348276), // Rule ID 5488 //
127791 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
127792 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127793 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127794 // (AArch64saddlv:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn) => (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (SADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn), dsub:{ *:[i32] })
127795 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
127796 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i32v),
127797 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
127798 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
127799 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
127800 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
127801 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
127802 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
127803 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
127804 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
127805 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
127806 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
127807 // GIR_Coverage, 5488,
127808 GIR_EraseRootFromParent_Done,
127809 // Label 7338: @348276
127810 GIM_Reject,
127811 // Label 7336: @348277
127812 GIM_Try, /*On fail goto*//*Label 7339*/ GIMT_Encode4(348336), // Rule ID 5484 //
127813 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
127814 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127815 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127816 // (AArch64saddlv:{ *:[v4i32] } V64:{ *:[v8i8] }:$Rn) => (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (SADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn), hsub:{ *:[i32] })
127817 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
127818 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i8v),
127819 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
127820 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
127821 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
127822 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
127823 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
127824 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
127825 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
127826 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
127827 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
127828 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
127829 // GIR_Coverage, 5484,
127830 GIR_EraseRootFromParent_Done,
127831 // Label 7339: @348336
127832 GIM_Try, /*On fail goto*//*Label 7340*/ GIMT_Encode4(348395), // Rule ID 5485 //
127833 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
127834 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127835 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127836 // (AArch64saddlv:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn) => (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (SADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn), ssub:{ *:[i32] })
127837 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
127838 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i16v),
127839 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
127840 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
127841 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
127842 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
127843 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
127844 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
127845 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
127846 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
127847 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
127848 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
127849 // GIR_Coverage, 5485,
127850 GIR_EraseRootFromParent_Done,
127851 // Label 7340: @348395
127852 GIM_Try, /*On fail goto*//*Label 7341*/ GIMT_Encode4(348454), // Rule ID 5486 //
127853 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
127854 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127855 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127856 // (AArch64saddlv:{ *:[v4i32] } V128:{ *:[v16i8] }:$Rn) => (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (SADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn), hsub:{ *:[i32] })
127857 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
127858 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv16i8v),
127859 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
127860 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
127861 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
127862 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
127863 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
127864 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
127865 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
127866 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
127867 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
127868 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
127869 // GIR_Coverage, 5486,
127870 GIR_EraseRootFromParent_Done,
127871 // Label 7341: @348454
127872 GIM_Try, /*On fail goto*//*Label 7342*/ GIMT_Encode4(348513), // Rule ID 5487 //
127873 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
127874 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127875 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127876 // (AArch64saddlv:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn) => (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (SADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn), ssub:{ *:[i32] })
127877 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
127878 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i16v),
127879 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
127880 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
127881 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
127882 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
127883 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
127884 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
127885 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
127886 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
127887 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
127888 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
127889 // GIR_Coverage, 5487,
127890 GIR_EraseRootFromParent_Done,
127891 // Label 7342: @348513
127892 GIM_Reject,
127893 // Label 7337: @348514
127894 GIM_Reject,
127895 // Label 130: @348515
127896 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(20), /*)*//*default:*//*Label 7347*/ GIMT_Encode4(348884),
127897 /*GILLT_v2s32*//*Label 7343*/ GIMT_Encode4(348586), GIMT_Encode4(0), GIMT_Encode4(0),
127898 /*GILLT_v4s32*//*Label 7344*/ GIMT_Encode4(348706), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
127899 /*GILLT_nxv2s64*//*Label 7345*/ GIMT_Encode4(348826), GIMT_Encode4(0), GIMT_Encode4(0),
127900 /*GILLT_nxv4s32*//*Label 7346*/ GIMT_Encode4(348855),
127901 // Label 7343: @348586
127902 GIM_Try, /*On fail goto*//*Label 7348*/ GIMT_Encode4(348705),
127903 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
127904 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
127905 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
127906 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127907 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127908 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127909 GIM_Try, /*On fail goto*//*Label 7349*/ GIMT_Encode4(348685), // Rule ID 26 //
127910 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
127911 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
127912 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
127913 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
127914 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
127915 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
127916 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
127917 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
127918 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127919 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
127920 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
127921 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
127922 // MIs[3] Operand 1
127923 // No operand predicates
127924 GIM_CheckIsSafeToFold, /*NumInsns*/3,
127925 // (AArch64sdot:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, (bitconvert:{ *:[v8i8] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SDOTlanev8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
127926 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDOTlanev8i8),
127927 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
127928 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
127929 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
127930 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
127931 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
127932 GIR_RootConstrainSelectedInstOperands,
127933 // GIR_Coverage, 26,
127934 GIR_EraseRootFromParent_Done,
127935 // Label 7349: @348685
127936 GIM_Try, /*On fail goto*//*Label 7350*/ GIMT_Encode4(348704), // Rule ID 22 //
127937 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
127938 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
127939 // (AArch64sdot:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SDOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
127940 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SDOTv8i8),
127941 GIR_RootConstrainSelectedInstOperands,
127942 // GIR_Coverage, 22,
127943 GIR_Done,
127944 // Label 7350: @348704
127945 GIM_Reject,
127946 // Label 7348: @348705
127947 GIM_Reject,
127948 // Label 7344: @348706
127949 GIM_Try, /*On fail goto*//*Label 7351*/ GIMT_Encode4(348825),
127950 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
127951 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
127952 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
127953 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127954 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127955 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127956 GIM_Try, /*On fail goto*//*Label 7352*/ GIMT_Encode4(348805), // Rule ID 27 //
127957 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
127958 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
127959 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
127960 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
127961 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
127962 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
127963 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
127964 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
127965 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127966 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
127967 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
127968 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
127969 // MIs[3] Operand 1
127970 // No operand predicates
127971 GIM_CheckIsSafeToFold, /*NumInsns*/3,
127972 // (AArch64sdot:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, (bitconvert:{ *:[v16i8] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (SDOTlanev16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
127973 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDOTlanev16i8),
127974 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
127975 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
127976 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
127977 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
127978 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
127979 GIR_RootConstrainSelectedInstOperands,
127980 // GIR_Coverage, 27,
127981 GIR_EraseRootFromParent_Done,
127982 // Label 7352: @348805
127983 GIM_Try, /*On fail goto*//*Label 7353*/ GIMT_Encode4(348824), // Rule ID 23 //
127984 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
127985 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
127986 // (AArch64sdot:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (SDOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
127987 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SDOTv16i8),
127988 GIR_RootConstrainSelectedInstOperands,
127989 // GIR_Coverage, 23,
127990 GIR_Done,
127991 // Label 7353: @348824
127992 GIM_Reject,
127993 // Label 7351: @348825
127994 GIM_Reject,
127995 // Label 7345: @348826
127996 GIM_Try, /*On fail goto*//*Label 7354*/ GIMT_Encode4(348854), // Rule ID 2911 //
127997 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
127998 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
127999 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
128000 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
128001 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
128002 // (AArch64sdot:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (SDOT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
128003 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SDOT_ZZZ_D),
128004 GIR_RootConstrainSelectedInstOperands,
128005 // GIR_Coverage, 2911,
128006 GIR_Done,
128007 // Label 7354: @348854
128008 GIM_Reject,
128009 // Label 7346: @348855
128010 GIM_Try, /*On fail goto*//*Label 7355*/ GIMT_Encode4(348883), // Rule ID 2910 //
128011 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128012 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
128013 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
128014 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
128015 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
128016 // (AArch64sdot:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (SDOT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
128017 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SDOT_ZZZ_S),
128018 GIR_RootConstrainSelectedInstOperands,
128019 // GIR_Coverage, 2910,
128020 GIR_Done,
128021 // Label 7355: @348883
128022 GIM_Reject,
128023 // Label 7347: @348884
128024 GIM_Reject,
128025 // Label 131: @348885
128026 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 7359*/ GIMT_Encode4(349001),
128027 /*GILLT_s16*//*Label 7356*/ GIMT_Encode4(348908),
128028 /*GILLT_s32*//*Label 7357*/ GIMT_Encode4(348939),
128029 /*GILLT_s64*//*Label 7358*/ GIMT_Encode4(348970),
128030 // Label 7356: @348908
128031 GIM_Try, /*On fail goto*//*Label 7360*/ GIMT_Encode4(348938), // Rule ID 1645 //
128032 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
128033 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
128034 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
128035 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
128036 // (AArch64sitof:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (SCVTFv1i16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
128037 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i16),
128038 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
128039 GIR_RootConstrainSelectedInstOperands,
128040 // GIR_Coverage, 1645,
128041 GIR_Done,
128042 // Label 7360: @348938
128043 GIM_Reject,
128044 // Label 7357: @348939
128045 GIM_Try, /*On fail goto*//*Label 7361*/ GIMT_Encode4(348969), // Rule ID 1644 //
128046 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
128047 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
128048 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
128049 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
128050 // (AArch64sitof:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (SCVTFv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
128051 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
128052 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
128053 GIR_RootConstrainSelectedInstOperands,
128054 // GIR_Coverage, 1644,
128055 GIR_Done,
128056 // Label 7361: @348969
128057 GIM_Reject,
128058 // Label 7358: @348970
128059 GIM_Try, /*On fail goto*//*Label 7362*/ GIMT_Encode4(349000), // Rule ID 1643 //
128060 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
128061 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
128062 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128063 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128064 // (AArch64sitof:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (SCVTFv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
128065 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
128066 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
128067 GIR_RootConstrainSelectedInstOperands,
128068 // GIR_Coverage, 1643,
128069 GIR_Done,
128070 // Label 7362: @349000
128071 GIM_Reject,
128072 // Label 7359: @349001
128073 GIM_Reject,
128074 // Label 132: @349002
128075 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(11), /*)*//*default:*//*Label 7366*/ GIMT_Encode4(349522),
128076 /*GILLT_v2s64*//*Label 7363*/ GIMT_Encode4(349033), GIMT_Encode4(0),
128077 /*GILLT_v4s32*//*Label 7364*/ GIMT_Encode4(349238), GIMT_Encode4(0),
128078 /*GILLT_v8s16*//*Label 7365*/ GIMT_Encode4(349443),
128079 // Label 7363: @349033
128080 GIM_Try, /*On fail goto*//*Label 7367*/ GIMT_Encode4(349237),
128081 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
128082 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
128083 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128084 GIM_Try, /*On fail goto*//*Label 7368*/ GIMT_Encode4(349087), // Rule ID 1728 //
128085 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128086 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
128087 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
128088 // (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)) => (SMULLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
128089 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i32_v2i64),
128090 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
128091 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
128092 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
128093 GIR_RootConstrainSelectedInstOperands,
128094 // GIR_Coverage, 1728,
128095 GIR_EraseRootFromParent_Done,
128096 // Label 7368: @349087
128097 GIM_Try, /*On fail goto*//*Label 7369*/ GIMT_Encode4(349150), // Rule ID 12746 //
128098 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128099 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
128100 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
128101 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
128102 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
128103 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128104 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
128105 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
128106 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
128107 // MIs[2] Operand 1
128108 // No operand predicates
128109 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128110 GIM_CheckIsSafeToFold, /*NumInsns*/2,
128111 // (AArch64smull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn) => (SMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
128112 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv2i32_indexed),
128113 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
128114 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
128115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
128116 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
128117 GIR_RootConstrainSelectedInstOperands,
128118 // GIR_Coverage, 12746,
128119 GIR_EraseRootFromParent_Done,
128120 // Label 7369: @349150
128121 GIM_Try, /*On fail goto*//*Label 7370*/ GIMT_Encode4(349213), // Rule ID 2040 //
128122 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128123 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128124 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
128125 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
128126 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
128127 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
128128 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128129 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
128130 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
128131 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
128132 // MIs[2] Operand 1
128133 // No operand predicates
128134 GIM_CheckIsSafeToFold, /*NumInsns*/2,
128135 // (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (SMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
128136 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv2i32_indexed),
128137 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
128138 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
128139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
128140 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
128141 GIR_RootConstrainSelectedInstOperands,
128142 // GIR_Coverage, 2040,
128143 GIR_EraseRootFromParent_Done,
128144 // Label 7370: @349213
128145 GIM_Try, /*On fail goto*//*Label 7371*/ GIMT_Encode4(349236), // Rule ID 1727 //
128146 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128147 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128148 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128149 // (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (SMULLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
128150 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMULLv2i32_v2i64),
128151 GIR_RootConstrainSelectedInstOperands,
128152 // GIR_Coverage, 1727,
128153 GIR_Done,
128154 // Label 7371: @349236
128155 GIM_Reject,
128156 // Label 7367: @349237
128157 GIM_Reject,
128158 // Label 7364: @349238
128159 GIM_Try, /*On fail goto*//*Label 7372*/ GIMT_Encode4(349442),
128160 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
128161 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
128162 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128163 GIM_Try, /*On fail goto*//*Label 7373*/ GIMT_Encode4(349292), // Rule ID 1726 //
128164 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128165 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
128166 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
128167 // (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)) => (SMULLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
128168 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv8i16_v4i32),
128169 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
128170 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
128171 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
128172 GIR_RootConstrainSelectedInstOperands,
128173 // GIR_Coverage, 1726,
128174 GIR_EraseRootFromParent_Done,
128175 // Label 7373: @349292
128176 GIM_Try, /*On fail goto*//*Label 7374*/ GIMT_Encode4(349355), // Rule ID 12743 //
128177 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128178 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
128179 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
128180 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
128181 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
128182 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
128183 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
128184 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
128185 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
128186 // MIs[2] Operand 1
128187 // No operand predicates
128188 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128189 GIM_CheckIsSafeToFold, /*NumInsns*/2,
128190 // (AArch64smull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn) => (SMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
128191 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i16_indexed),
128192 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
128193 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
128194 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
128195 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
128196 GIR_RootConstrainSelectedInstOperands,
128197 // GIR_Coverage, 12743,
128198 GIR_EraseRootFromParent_Done,
128199 // Label 7374: @349355
128200 GIM_Try, /*On fail goto*//*Label 7375*/ GIMT_Encode4(349418), // Rule ID 2037 //
128201 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128202 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128203 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
128204 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
128205 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
128206 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
128207 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
128208 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
128209 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
128210 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
128211 // MIs[2] Operand 1
128212 // No operand predicates
128213 GIM_CheckIsSafeToFold, /*NumInsns*/2,
128214 // (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (SMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
128215 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i16_indexed),
128216 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
128217 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
128218 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
128219 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
128220 GIR_RootConstrainSelectedInstOperands,
128221 // GIR_Coverage, 2037,
128222 GIR_EraseRootFromParent_Done,
128223 // Label 7375: @349418
128224 GIM_Try, /*On fail goto*//*Label 7376*/ GIMT_Encode4(349441), // Rule ID 1725 //
128225 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128226 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128227 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128228 // (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (SMULLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
128229 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i16_v4i32),
128230 GIR_RootConstrainSelectedInstOperands,
128231 // GIR_Coverage, 1725,
128232 GIR_Done,
128233 // Label 7376: @349441
128234 GIM_Reject,
128235 // Label 7372: @349442
128236 GIM_Reject,
128237 // Label 7365: @349443
128238 GIM_Try, /*On fail goto*//*Label 7377*/ GIMT_Encode4(349521),
128239 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
128240 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
128241 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128242 GIM_Try, /*On fail goto*//*Label 7378*/ GIMT_Encode4(349497), // Rule ID 1724 //
128243 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128244 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
128245 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
128246 // (AArch64smull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)) => (SMULLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
128247 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv16i8_v8i16),
128248 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
128249 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
128250 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
128251 GIR_RootConstrainSelectedInstOperands,
128252 // GIR_Coverage, 1724,
128253 GIR_EraseRootFromParent_Done,
128254 // Label 7378: @349497
128255 GIM_Try, /*On fail goto*//*Label 7379*/ GIMT_Encode4(349520), // Rule ID 1723 //
128256 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128257 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128258 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128259 // (AArch64smull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (SMULLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
128260 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMULLv8i8_v8i16),
128261 GIR_RootConstrainSelectedInstOperands,
128262 // GIR_Coverage, 1723,
128263 GIR_Done,
128264 // Label 7379: @349520
128265 GIM_Reject,
128266 // Label 7377: @349521
128267 GIM_Reject,
128268 // Label 7366: @349522
128269 GIM_Reject,
128270 // Label 133: @349523
128271 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 7398*/ GIMT_Encode4(350347),
128272 /*GILLT_v2s32*//*Label 7380*/ GIMT_Encode4(349610),
128273 /*GILLT_v2s64*//*Label 7381*/ GIMT_Encode4(349665),
128274 /*GILLT_v4s16*//*Label 7382*/ GIMT_Encode4(349720),
128275 /*GILLT_v4s32*//*Label 7383*/ GIMT_Encode4(349790),
128276 /*GILLT_v8s8*//*Label 7384*/ GIMT_Encode4(349845),
128277 /*GILLT_v8s16*//*Label 7385*/ GIMT_Encode4(349879),
128278 /*GILLT_v16s8*//*Label 7386*/ GIMT_Encode4(349949), GIMT_Encode4(0),
128279 /*GILLT_nxv2s1*//*Label 7387*/ GIMT_Encode4(349983),
128280 /*GILLT_nxv2s16*//*Label 7388*/ GIMT_Encode4(350009),
128281 /*GILLT_nxv2s32*//*Label 7389*/ GIMT_Encode4(350035),
128282 /*GILLT_nxv2s64*//*Label 7390*/ GIMT_Encode4(350061),
128283 /*GILLT_nxv4s1*//*Label 7391*/ GIMT_Encode4(350108),
128284 /*GILLT_nxv4s16*//*Label 7392*/ GIMT_Encode4(350134),
128285 /*GILLT_nxv4s32*//*Label 7393*/ GIMT_Encode4(350160),
128286 /*GILLT_nxv8s1*//*Label 7394*/ GIMT_Encode4(350207),
128287 /*GILLT_nxv8s16*//*Label 7395*/ GIMT_Encode4(350233),
128288 /*GILLT_nxv16s1*//*Label 7396*/ GIMT_Encode4(350295),
128289 /*GILLT_nxv16s8*//*Label 7397*/ GIMT_Encode4(350321),
128290 // Label 7380: @349610
128291 GIM_Try, /*On fail goto*//*Label 7399*/ GIMT_Encode4(349664),
128292 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
128293 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
128294 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128295 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128296 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128297 GIM_Try, /*On fail goto*//*Label 7400*/ GIMT_Encode4(349648), // Rule ID 1861 //
128298 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128299 // (AArch64trn1:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (TRN1v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
128300 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v2i32),
128301 GIR_RootConstrainSelectedInstOperands,
128302 // GIR_Coverage, 1861,
128303 GIR_Done,
128304 // Label 7400: @349648
128305 GIM_Try, /*On fail goto*//*Label 7401*/ GIMT_Encode4(349663), // Rule ID 2427 //
128306 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128307 // (AArch64trn1:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (TRN1v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
128308 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v2i32),
128309 GIR_RootConstrainSelectedInstOperands,
128310 // GIR_Coverage, 2427,
128311 GIR_Done,
128312 // Label 7401: @349663
128313 GIM_Reject,
128314 // Label 7399: @349664
128315 GIM_Reject,
128316 // Label 7381: @349665
128317 GIM_Try, /*On fail goto*//*Label 7402*/ GIMT_Encode4(349719),
128318 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
128319 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
128320 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128321 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128322 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128323 GIM_Try, /*On fail goto*//*Label 7403*/ GIMT_Encode4(349703), // Rule ID 1863 //
128324 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128325 // (AArch64trn1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (TRN1v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
128326 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v2i64),
128327 GIR_RootConstrainSelectedInstOperands,
128328 // GIR_Coverage, 1863,
128329 GIR_Done,
128330 // Label 7403: @349703
128331 GIM_Try, /*On fail goto*//*Label 7404*/ GIMT_Encode4(349718), // Rule ID 2429 //
128332 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128333 // (AArch64trn1:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (TRN1v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
128334 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v2i64),
128335 GIR_RootConstrainSelectedInstOperands,
128336 // GIR_Coverage, 2429,
128337 GIR_Done,
128338 // Label 7404: @349718
128339 GIM_Reject,
128340 // Label 7402: @349719
128341 GIM_Reject,
128342 // Label 7382: @349720
128343 GIM_Try, /*On fail goto*//*Label 7405*/ GIMT_Encode4(349789),
128344 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
128345 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
128346 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128347 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128348 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128349 GIM_Try, /*On fail goto*//*Label 7406*/ GIMT_Encode4(349758), // Rule ID 1859 //
128350 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128351 // (AArch64trn1:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (TRN1v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
128352 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v4i16),
128353 GIR_RootConstrainSelectedInstOperands,
128354 // GIR_Coverage, 1859,
128355 GIR_Done,
128356 // Label 7406: @349758
128357 GIM_Try, /*On fail goto*//*Label 7407*/ GIMT_Encode4(349773), // Rule ID 2423 //
128358 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128359 // (AArch64trn1:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (TRN1v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
128360 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v4i16),
128361 GIR_RootConstrainSelectedInstOperands,
128362 // GIR_Coverage, 2423,
128363 GIR_Done,
128364 // Label 7407: @349773
128365 GIM_Try, /*On fail goto*//*Label 7408*/ GIMT_Encode4(349788), // Rule ID 2424 //
128366 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128367 // (AArch64trn1:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) => (TRN1v4i16:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm)
128368 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v4i16),
128369 GIR_RootConstrainSelectedInstOperands,
128370 // GIR_Coverage, 2424,
128371 GIR_Done,
128372 // Label 7408: @349788
128373 GIM_Reject,
128374 // Label 7405: @349789
128375 GIM_Reject,
128376 // Label 7383: @349790
128377 GIM_Try, /*On fail goto*//*Label 7409*/ GIMT_Encode4(349844),
128378 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
128379 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
128380 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128381 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128382 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128383 GIM_Try, /*On fail goto*//*Label 7410*/ GIMT_Encode4(349828), // Rule ID 1862 //
128384 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128385 // (AArch64trn1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (TRN1v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
128386 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v4i32),
128387 GIR_RootConstrainSelectedInstOperands,
128388 // GIR_Coverage, 1862,
128389 GIR_Done,
128390 // Label 7410: @349828
128391 GIM_Try, /*On fail goto*//*Label 7411*/ GIMT_Encode4(349843), // Rule ID 2428 //
128392 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128393 // (AArch64trn1:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (TRN1v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
128394 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v4i32),
128395 GIR_RootConstrainSelectedInstOperands,
128396 // GIR_Coverage, 2428,
128397 GIR_Done,
128398 // Label 7411: @349843
128399 GIM_Reject,
128400 // Label 7409: @349844
128401 GIM_Reject,
128402 // Label 7384: @349845
128403 GIM_Try, /*On fail goto*//*Label 7412*/ GIMT_Encode4(349878), // Rule ID 1857 //
128404 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128405 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
128406 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
128407 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128408 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128409 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128410 // (AArch64trn1:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (TRN1v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
128411 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v8i8),
128412 GIR_RootConstrainSelectedInstOperands,
128413 // GIR_Coverage, 1857,
128414 GIR_Done,
128415 // Label 7412: @349878
128416 GIM_Reject,
128417 // Label 7385: @349879
128418 GIM_Try, /*On fail goto*//*Label 7413*/ GIMT_Encode4(349948),
128419 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
128420 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
128421 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128422 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128423 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128424 GIM_Try, /*On fail goto*//*Label 7414*/ GIMT_Encode4(349917), // Rule ID 1860 //
128425 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128426 // (AArch64trn1:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (TRN1v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
128427 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v8i16),
128428 GIR_RootConstrainSelectedInstOperands,
128429 // GIR_Coverage, 1860,
128430 GIR_Done,
128431 // Label 7414: @349917
128432 GIM_Try, /*On fail goto*//*Label 7415*/ GIMT_Encode4(349932), // Rule ID 2425 //
128433 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128434 // (AArch64trn1:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (TRN1v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
128435 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v8i16),
128436 GIR_RootConstrainSelectedInstOperands,
128437 // GIR_Coverage, 2425,
128438 GIR_Done,
128439 // Label 7415: @349932
128440 GIM_Try, /*On fail goto*//*Label 7416*/ GIMT_Encode4(349947), // Rule ID 2426 //
128441 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128442 // (AArch64trn1:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (TRN1v8i16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm)
128443 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v8i16),
128444 GIR_RootConstrainSelectedInstOperands,
128445 // GIR_Coverage, 2426,
128446 GIR_Done,
128447 // Label 7416: @349947
128448 GIM_Reject,
128449 // Label 7413: @349948
128450 GIM_Reject,
128451 // Label 7386: @349949
128452 GIM_Try, /*On fail goto*//*Label 7417*/ GIMT_Encode4(349982), // Rule ID 1858 //
128453 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128454 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
128455 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
128456 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128457 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128458 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128459 // (AArch64trn1:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (TRN1v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
128460 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v16i8),
128461 GIR_RootConstrainSelectedInstOperands,
128462 // GIR_Coverage, 1858,
128463 GIR_Done,
128464 // Label 7417: @349982
128465 GIM_Reject,
128466 // Label 7387: @349983
128467 GIM_Try, /*On fail goto*//*Label 7418*/ GIMT_Encode4(350008), // Rule ID 8646 //
128468 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128469 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
128470 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
128471 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
128472 // (AArch64trn1:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2) => (TRN1_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
128473 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_D),
128474 GIR_RootConstrainSelectedInstOperands,
128475 // GIR_Coverage, 8646,
128476 GIR_Done,
128477 // Label 7418: @350008
128478 GIM_Reject,
128479 // Label 7388: @350009
128480 GIM_Try, /*On fail goto*//*Label 7419*/ GIMT_Encode4(350034), // Rule ID 8620 //
128481 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128482 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
128483 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
128484 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
128485 // (AArch64trn1:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2) => (TRN1_ZZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$Op1, ?:{ *:[nxv2f16] }:$Op2)
128486 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_D),
128487 GIR_RootConstrainSelectedInstOperands,
128488 // GIR_Coverage, 8620,
128489 GIR_Done,
128490 // Label 7419: @350034
128491 GIM_Reject,
128492 // Label 7389: @350035
128493 GIM_Try, /*On fail goto*//*Label 7420*/ GIMT_Encode4(350060), // Rule ID 8621 //
128494 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128495 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
128496 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
128497 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
128498 // (AArch64trn1:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2) => (TRN1_ZZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$Op1, ?:{ *:[nxv2f32] }:$Op2)
128499 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_D),
128500 GIR_RootConstrainSelectedInstOperands,
128501 // GIR_Coverage, 8621,
128502 GIR_Done,
128503 // Label 7420: @350060
128504 GIM_Reject,
128505 // Label 7390: @350061
128506 GIM_Try, /*On fail goto*//*Label 7421*/ GIMT_Encode4(350107),
128507 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
128508 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
128509 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
128510 GIM_Try, /*On fail goto*//*Label 7422*/ GIMT_Encode4(350091), // Rule ID 8616 //
128511 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128512 // (AArch64trn1:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (TRN1_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
128513 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_D),
128514 GIR_RootConstrainSelectedInstOperands,
128515 // GIR_Coverage, 8616,
128516 GIR_Done,
128517 // Label 7422: @350091
128518 GIM_Try, /*On fail goto*//*Label 7423*/ GIMT_Encode4(350106), // Rule ID 8622 //
128519 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128520 // (AArch64trn1:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (TRN1_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
128521 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_D),
128522 GIR_RootConstrainSelectedInstOperands,
128523 // GIR_Coverage, 8622,
128524 GIR_Done,
128525 // Label 7423: @350106
128526 GIM_Reject,
128527 // Label 7421: @350107
128528 GIM_Reject,
128529 // Label 7391: @350108
128530 GIM_Try, /*On fail goto*//*Label 7424*/ GIMT_Encode4(350133), // Rule ID 8645 //
128531 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128532 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
128533 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
128534 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
128535 // (AArch64trn1:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2) => (TRN1_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
128536 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_S),
128537 GIR_RootConstrainSelectedInstOperands,
128538 // GIR_Coverage, 8645,
128539 GIR_Done,
128540 // Label 7424: @350133
128541 GIM_Reject,
128542 // Label 7392: @350134
128543 GIM_Try, /*On fail goto*//*Label 7425*/ GIMT_Encode4(350159), // Rule ID 8618 //
128544 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128545 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
128546 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
128547 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
128548 // (AArch64trn1:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2) => (TRN1_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$Op1, ?:{ *:[nxv4f16] }:$Op2)
128549 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_S),
128550 GIR_RootConstrainSelectedInstOperands,
128551 // GIR_Coverage, 8618,
128552 GIR_Done,
128553 // Label 7425: @350159
128554 GIM_Reject,
128555 // Label 7393: @350160
128556 GIM_Try, /*On fail goto*//*Label 7426*/ GIMT_Encode4(350206),
128557 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
128558 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
128559 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
128560 GIM_Try, /*On fail goto*//*Label 7427*/ GIMT_Encode4(350190), // Rule ID 8615 //
128561 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128562 // (AArch64trn1:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (TRN1_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
128563 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_S),
128564 GIR_RootConstrainSelectedInstOperands,
128565 // GIR_Coverage, 8615,
128566 GIR_Done,
128567 // Label 7427: @350190
128568 GIM_Try, /*On fail goto*//*Label 7428*/ GIMT_Encode4(350205), // Rule ID 8619 //
128569 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128570 // (AArch64trn1:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (TRN1_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
128571 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_S),
128572 GIR_RootConstrainSelectedInstOperands,
128573 // GIR_Coverage, 8619,
128574 GIR_Done,
128575 // Label 7428: @350205
128576 GIM_Reject,
128577 // Label 7426: @350206
128578 GIM_Reject,
128579 // Label 7394: @350207
128580 GIM_Try, /*On fail goto*//*Label 7429*/ GIMT_Encode4(350232), // Rule ID 8644 //
128581 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128582 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
128583 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
128584 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
128585 // (AArch64trn1:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2) => (TRN1_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
128586 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_H),
128587 GIR_RootConstrainSelectedInstOperands,
128588 // GIR_Coverage, 8644,
128589 GIR_Done,
128590 // Label 7429: @350232
128591 GIM_Reject,
128592 // Label 7395: @350233
128593 GIM_Try, /*On fail goto*//*Label 7430*/ GIMT_Encode4(350294),
128594 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
128595 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
128596 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
128597 GIM_Try, /*On fail goto*//*Label 7431*/ GIMT_Encode4(350263), // Rule ID 8614 //
128598 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128599 // (AArch64trn1:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (TRN1_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
128600 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_H),
128601 GIR_RootConstrainSelectedInstOperands,
128602 // GIR_Coverage, 8614,
128603 GIR_Done,
128604 // Label 7431: @350263
128605 GIM_Try, /*On fail goto*//*Label 7432*/ GIMT_Encode4(350278), // Rule ID 8617 //
128606 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128607 // (AArch64trn1:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (TRN1_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
128608 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_H),
128609 GIR_RootConstrainSelectedInstOperands,
128610 // GIR_Coverage, 8617,
128611 GIR_Done,
128612 // Label 7432: @350278
128613 GIM_Try, /*On fail goto*//*Label 7433*/ GIMT_Encode4(350293), // Rule ID 8623 //
128614 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128615 // (AArch64trn1:{ *:[nxv8bf16] } nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2) => (TRN1_ZZZ_H:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2)
128616 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_H),
128617 GIR_RootConstrainSelectedInstOperands,
128618 // GIR_Coverage, 8623,
128619 GIR_Done,
128620 // Label 7433: @350293
128621 GIM_Reject,
128622 // Label 7430: @350294
128623 GIM_Reject,
128624 // Label 7396: @350295
128625 GIM_Try, /*On fail goto*//*Label 7434*/ GIMT_Encode4(350320), // Rule ID 2354 //
128626 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128627 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
128628 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
128629 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
128630 // (AArch64trn1:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (TRN1_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
128631 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_B),
128632 GIR_RootConstrainSelectedInstOperands,
128633 // GIR_Coverage, 2354,
128634 GIR_Done,
128635 // Label 7434: @350320
128636 GIM_Reject,
128637 // Label 7397: @350321
128638 GIM_Try, /*On fail goto*//*Label 7435*/ GIMT_Encode4(350346), // Rule ID 8613 //
128639 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128640 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
128641 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
128642 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
128643 // (AArch64trn1:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (TRN1_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
128644 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_B),
128645 GIR_RootConstrainSelectedInstOperands,
128646 // GIR_Coverage, 8613,
128647 GIR_Done,
128648 // Label 7435: @350346
128649 GIM_Reject,
128650 // Label 7398: @350347
128651 GIM_Reject,
128652 // Label 134: @350348
128653 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 7454*/ GIMT_Encode4(351172),
128654 /*GILLT_v2s32*//*Label 7436*/ GIMT_Encode4(350435),
128655 /*GILLT_v2s64*//*Label 7437*/ GIMT_Encode4(350490),
128656 /*GILLT_v4s16*//*Label 7438*/ GIMT_Encode4(350545),
128657 /*GILLT_v4s32*//*Label 7439*/ GIMT_Encode4(350615),
128658 /*GILLT_v8s8*//*Label 7440*/ GIMT_Encode4(350670),
128659 /*GILLT_v8s16*//*Label 7441*/ GIMT_Encode4(350704),
128660 /*GILLT_v16s8*//*Label 7442*/ GIMT_Encode4(350774), GIMT_Encode4(0),
128661 /*GILLT_nxv2s1*//*Label 7443*/ GIMT_Encode4(350808),
128662 /*GILLT_nxv2s16*//*Label 7444*/ GIMT_Encode4(350834),
128663 /*GILLT_nxv2s32*//*Label 7445*/ GIMT_Encode4(350860),
128664 /*GILLT_nxv2s64*//*Label 7446*/ GIMT_Encode4(350886),
128665 /*GILLT_nxv4s1*//*Label 7447*/ GIMT_Encode4(350933),
128666 /*GILLT_nxv4s16*//*Label 7448*/ GIMT_Encode4(350959),
128667 /*GILLT_nxv4s32*//*Label 7449*/ GIMT_Encode4(350985),
128668 /*GILLT_nxv8s1*//*Label 7450*/ GIMT_Encode4(351032),
128669 /*GILLT_nxv8s16*//*Label 7451*/ GIMT_Encode4(351058),
128670 /*GILLT_nxv16s1*//*Label 7452*/ GIMT_Encode4(351120),
128671 /*GILLT_nxv16s8*//*Label 7453*/ GIMT_Encode4(351146),
128672 // Label 7436: @350435
128673 GIM_Try, /*On fail goto*//*Label 7455*/ GIMT_Encode4(350489),
128674 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
128675 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
128676 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128677 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128678 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128679 GIM_Try, /*On fail goto*//*Label 7456*/ GIMT_Encode4(350473), // Rule ID 1868 //
128680 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128681 // (AArch64trn2:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (TRN2v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
128682 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v2i32),
128683 GIR_RootConstrainSelectedInstOperands,
128684 // GIR_Coverage, 1868,
128685 GIR_Done,
128686 // Label 7456: @350473
128687 GIM_Try, /*On fail goto*//*Label 7457*/ GIMT_Encode4(350488), // Rule ID 5119 //
128688 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128689 // (AArch64trn2:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (TRN2v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
128690 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v2i32),
128691 GIR_RootConstrainSelectedInstOperands,
128692 // GIR_Coverage, 5119,
128693 GIR_Done,
128694 // Label 7457: @350488
128695 GIM_Reject,
128696 // Label 7455: @350489
128697 GIM_Reject,
128698 // Label 7437: @350490
128699 GIM_Try, /*On fail goto*//*Label 7458*/ GIMT_Encode4(350544),
128700 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
128701 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
128702 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128703 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128704 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128705 GIM_Try, /*On fail goto*//*Label 7459*/ GIMT_Encode4(350528), // Rule ID 1870 //
128706 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128707 // (AArch64trn2:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (TRN2v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
128708 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v2i64),
128709 GIR_RootConstrainSelectedInstOperands,
128710 // GIR_Coverage, 1870,
128711 GIR_Done,
128712 // Label 7459: @350528
128713 GIM_Try, /*On fail goto*//*Label 7460*/ GIMT_Encode4(350543), // Rule ID 5121 //
128714 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128715 // (AArch64trn2:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (TRN2v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
128716 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v2i64),
128717 GIR_RootConstrainSelectedInstOperands,
128718 // GIR_Coverage, 5121,
128719 GIR_Done,
128720 // Label 7460: @350543
128721 GIM_Reject,
128722 // Label 7458: @350544
128723 GIM_Reject,
128724 // Label 7438: @350545
128725 GIM_Try, /*On fail goto*//*Label 7461*/ GIMT_Encode4(350614),
128726 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
128727 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
128728 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128729 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128730 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128731 GIM_Try, /*On fail goto*//*Label 7462*/ GIMT_Encode4(350583), // Rule ID 1866 //
128732 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128733 // (AArch64trn2:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (TRN2v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
128734 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v4i16),
128735 GIR_RootConstrainSelectedInstOperands,
128736 // GIR_Coverage, 1866,
128737 GIR_Done,
128738 // Label 7462: @350583
128739 GIM_Try, /*On fail goto*//*Label 7463*/ GIMT_Encode4(350598), // Rule ID 5115 //
128740 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128741 // (AArch64trn2:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (TRN2v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
128742 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v4i16),
128743 GIR_RootConstrainSelectedInstOperands,
128744 // GIR_Coverage, 5115,
128745 GIR_Done,
128746 // Label 7463: @350598
128747 GIM_Try, /*On fail goto*//*Label 7464*/ GIMT_Encode4(350613), // Rule ID 5116 //
128748 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128749 // (AArch64trn2:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) => (TRN2v4i16:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm)
128750 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v4i16),
128751 GIR_RootConstrainSelectedInstOperands,
128752 // GIR_Coverage, 5116,
128753 GIR_Done,
128754 // Label 7464: @350613
128755 GIM_Reject,
128756 // Label 7461: @350614
128757 GIM_Reject,
128758 // Label 7439: @350615
128759 GIM_Try, /*On fail goto*//*Label 7465*/ GIMT_Encode4(350669),
128760 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
128761 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
128762 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128763 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128764 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128765 GIM_Try, /*On fail goto*//*Label 7466*/ GIMT_Encode4(350653), // Rule ID 1869 //
128766 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128767 // (AArch64trn2:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (TRN2v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
128768 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v4i32),
128769 GIR_RootConstrainSelectedInstOperands,
128770 // GIR_Coverage, 1869,
128771 GIR_Done,
128772 // Label 7466: @350653
128773 GIM_Try, /*On fail goto*//*Label 7467*/ GIMT_Encode4(350668), // Rule ID 5120 //
128774 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128775 // (AArch64trn2:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (TRN2v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
128776 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v4i32),
128777 GIR_RootConstrainSelectedInstOperands,
128778 // GIR_Coverage, 5120,
128779 GIR_Done,
128780 // Label 7467: @350668
128781 GIM_Reject,
128782 // Label 7465: @350669
128783 GIM_Reject,
128784 // Label 7440: @350670
128785 GIM_Try, /*On fail goto*//*Label 7468*/ GIMT_Encode4(350703), // Rule ID 1864 //
128786 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128787 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
128788 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
128789 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128790 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128791 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
128792 // (AArch64trn2:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (TRN2v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
128793 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v8i8),
128794 GIR_RootConstrainSelectedInstOperands,
128795 // GIR_Coverage, 1864,
128796 GIR_Done,
128797 // Label 7468: @350703
128798 GIM_Reject,
128799 // Label 7441: @350704
128800 GIM_Try, /*On fail goto*//*Label 7469*/ GIMT_Encode4(350773),
128801 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
128802 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
128803 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128804 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128805 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128806 GIM_Try, /*On fail goto*//*Label 7470*/ GIMT_Encode4(350742), // Rule ID 1867 //
128807 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128808 // (AArch64trn2:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (TRN2v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
128809 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v8i16),
128810 GIR_RootConstrainSelectedInstOperands,
128811 // GIR_Coverage, 1867,
128812 GIR_Done,
128813 // Label 7470: @350742
128814 GIM_Try, /*On fail goto*//*Label 7471*/ GIMT_Encode4(350757), // Rule ID 5117 //
128815 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128816 // (AArch64trn2:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (TRN2v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
128817 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v8i16),
128818 GIR_RootConstrainSelectedInstOperands,
128819 // GIR_Coverage, 5117,
128820 GIR_Done,
128821 // Label 7471: @350757
128822 GIM_Try, /*On fail goto*//*Label 7472*/ GIMT_Encode4(350772), // Rule ID 5118 //
128823 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128824 // (AArch64trn2:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (TRN2v8i16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm)
128825 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v8i16),
128826 GIR_RootConstrainSelectedInstOperands,
128827 // GIR_Coverage, 5118,
128828 GIR_Done,
128829 // Label 7472: @350772
128830 GIM_Reject,
128831 // Label 7469: @350773
128832 GIM_Reject,
128833 // Label 7442: @350774
128834 GIM_Try, /*On fail goto*//*Label 7473*/ GIMT_Encode4(350807), // Rule ID 1865 //
128835 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
128836 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
128837 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
128838 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128839 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128840 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
128841 // (AArch64trn2:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (TRN2v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
128842 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v16i8),
128843 GIR_RootConstrainSelectedInstOperands,
128844 // GIR_Coverage, 1865,
128845 GIR_Done,
128846 // Label 7473: @350807
128847 GIM_Reject,
128848 // Label 7443: @350808
128849 GIM_Try, /*On fail goto*//*Label 7474*/ GIMT_Encode4(350833), // Rule ID 8649 //
128850 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128851 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
128852 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
128853 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
128854 // (AArch64trn2:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2) => (TRN2_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
128855 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_D),
128856 GIR_RootConstrainSelectedInstOperands,
128857 // GIR_Coverage, 8649,
128858 GIR_Done,
128859 // Label 7474: @350833
128860 GIM_Reject,
128861 // Label 7444: @350834
128862 GIM_Try, /*On fail goto*//*Label 7475*/ GIMT_Encode4(350859), // Rule ID 8631 //
128863 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128864 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
128865 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
128866 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
128867 // (AArch64trn2:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2) => (TRN2_ZZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$Op1, ?:{ *:[nxv2f16] }:$Op2)
128868 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_D),
128869 GIR_RootConstrainSelectedInstOperands,
128870 // GIR_Coverage, 8631,
128871 GIR_Done,
128872 // Label 7475: @350859
128873 GIM_Reject,
128874 // Label 7445: @350860
128875 GIM_Try, /*On fail goto*//*Label 7476*/ GIMT_Encode4(350885), // Rule ID 8632 //
128876 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128877 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
128878 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
128879 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
128880 // (AArch64trn2:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2) => (TRN2_ZZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$Op1, ?:{ *:[nxv2f32] }:$Op2)
128881 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_D),
128882 GIR_RootConstrainSelectedInstOperands,
128883 // GIR_Coverage, 8632,
128884 GIR_Done,
128885 // Label 7476: @350885
128886 GIM_Reject,
128887 // Label 7446: @350886
128888 GIM_Try, /*On fail goto*//*Label 7477*/ GIMT_Encode4(350932),
128889 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
128890 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
128891 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
128892 GIM_Try, /*On fail goto*//*Label 7478*/ GIMT_Encode4(350916), // Rule ID 8627 //
128893 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128894 // (AArch64trn2:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (TRN2_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
128895 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_D),
128896 GIR_RootConstrainSelectedInstOperands,
128897 // GIR_Coverage, 8627,
128898 GIR_Done,
128899 // Label 7478: @350916
128900 GIM_Try, /*On fail goto*//*Label 7479*/ GIMT_Encode4(350931), // Rule ID 8633 //
128901 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128902 // (AArch64trn2:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (TRN2_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
128903 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_D),
128904 GIR_RootConstrainSelectedInstOperands,
128905 // GIR_Coverage, 8633,
128906 GIR_Done,
128907 // Label 7479: @350931
128908 GIM_Reject,
128909 // Label 7477: @350932
128910 GIM_Reject,
128911 // Label 7447: @350933
128912 GIM_Try, /*On fail goto*//*Label 7480*/ GIMT_Encode4(350958), // Rule ID 8648 //
128913 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128914 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
128915 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
128916 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
128917 // (AArch64trn2:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2) => (TRN2_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
128918 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_S),
128919 GIR_RootConstrainSelectedInstOperands,
128920 // GIR_Coverage, 8648,
128921 GIR_Done,
128922 // Label 7480: @350958
128923 GIM_Reject,
128924 // Label 7448: @350959
128925 GIM_Try, /*On fail goto*//*Label 7481*/ GIMT_Encode4(350984), // Rule ID 8629 //
128926 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128927 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
128928 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
128929 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
128930 // (AArch64trn2:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2) => (TRN2_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$Op1, ?:{ *:[nxv4f16] }:$Op2)
128931 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_S),
128932 GIR_RootConstrainSelectedInstOperands,
128933 // GIR_Coverage, 8629,
128934 GIR_Done,
128935 // Label 7481: @350984
128936 GIM_Reject,
128937 // Label 7449: @350985
128938 GIM_Try, /*On fail goto*//*Label 7482*/ GIMT_Encode4(351031),
128939 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
128940 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
128941 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
128942 GIM_Try, /*On fail goto*//*Label 7483*/ GIMT_Encode4(351015), // Rule ID 8626 //
128943 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128944 // (AArch64trn2:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (TRN2_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
128945 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_S),
128946 GIR_RootConstrainSelectedInstOperands,
128947 // GIR_Coverage, 8626,
128948 GIR_Done,
128949 // Label 7483: @351015
128950 GIM_Try, /*On fail goto*//*Label 7484*/ GIMT_Encode4(351030), // Rule ID 8630 //
128951 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128952 // (AArch64trn2:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (TRN2_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
128953 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_S),
128954 GIR_RootConstrainSelectedInstOperands,
128955 // GIR_Coverage, 8630,
128956 GIR_Done,
128957 // Label 7484: @351030
128958 GIM_Reject,
128959 // Label 7482: @351031
128960 GIM_Reject,
128961 // Label 7450: @351032
128962 GIM_Try, /*On fail goto*//*Label 7485*/ GIMT_Encode4(351057), // Rule ID 8647 //
128963 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128964 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
128965 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
128966 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
128967 // (AArch64trn2:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2) => (TRN2_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
128968 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_H),
128969 GIR_RootConstrainSelectedInstOperands,
128970 // GIR_Coverage, 8647,
128971 GIR_Done,
128972 // Label 7485: @351057
128973 GIM_Reject,
128974 // Label 7451: @351058
128975 GIM_Try, /*On fail goto*//*Label 7486*/ GIMT_Encode4(351119),
128976 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
128977 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
128978 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
128979 GIM_Try, /*On fail goto*//*Label 7487*/ GIMT_Encode4(351088), // Rule ID 8625 //
128980 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128981 // (AArch64trn2:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (TRN2_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
128982 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_H),
128983 GIR_RootConstrainSelectedInstOperands,
128984 // GIR_Coverage, 8625,
128985 GIR_Done,
128986 // Label 7487: @351088
128987 GIM_Try, /*On fail goto*//*Label 7488*/ GIMT_Encode4(351103), // Rule ID 8628 //
128988 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128989 // (AArch64trn2:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (TRN2_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
128990 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_H),
128991 GIR_RootConstrainSelectedInstOperands,
128992 // GIR_Coverage, 8628,
128993 GIR_Done,
128994 // Label 7488: @351103
128995 GIM_Try, /*On fail goto*//*Label 7489*/ GIMT_Encode4(351118), // Rule ID 8634 //
128996 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
128997 // (AArch64trn2:{ *:[nxv8bf16] } nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2) => (TRN2_ZZZ_H:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2)
128998 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_H),
128999 GIR_RootConstrainSelectedInstOperands,
129000 // GIR_Coverage, 8634,
129001 GIR_Done,
129002 // Label 7489: @351118
129003 GIM_Reject,
129004 // Label 7486: @351119
129005 GIM_Reject,
129006 // Label 7452: @351120
129007 GIM_Try, /*On fail goto*//*Label 7490*/ GIMT_Encode4(351145), // Rule ID 2358 //
129008 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
129009 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
129010 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
129011 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
129012 // (AArch64trn2:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (TRN2_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
129013 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_B),
129014 GIR_RootConstrainSelectedInstOperands,
129015 // GIR_Coverage, 2358,
129016 GIR_Done,
129017 // Label 7490: @351145
129018 GIM_Reject,
129019 // Label 7453: @351146
129020 GIM_Try, /*On fail goto*//*Label 7491*/ GIMT_Encode4(351171), // Rule ID 8624 //
129021 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
129022 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
129023 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
129024 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
129025 // (AArch64trn2:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (TRN2_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
129026 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_B),
129027 GIR_RootConstrainSelectedInstOperands,
129028 // GIR_Coverage, 8624,
129029 GIR_Done,
129030 // Label 7491: @351171
129031 GIM_Reject,
129032 // Label 7454: @351172
129033 GIM_Reject,
129034 // Label 135: @351173
129035 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(11), /*)*//*default:*//*Label 7498*/ GIMT_Encode4(351378),
129036 /*GILLT_s64*//*Label 7492*/ GIMT_Encode4(351216), GIMT_Encode4(0),
129037 /*GILLT_v2s32*//*Label 7493*/ GIMT_Encode4(351243),
129038 /*GILLT_v2s64*//*Label 7494*/ GIMT_Encode4(351270),
129039 /*GILLT_v4s16*//*Label 7495*/ GIMT_Encode4(351297),
129040 /*GILLT_v4s32*//*Label 7496*/ GIMT_Encode4(351324), GIMT_Encode4(0),
129041 /*GILLT_v8s16*//*Label 7497*/ GIMT_Encode4(351351),
129042 // Label 7492: @351216
129043 GIM_Try, /*On fail goto*//*Label 7499*/ GIMT_Encode4(351242), // Rule ID 1056 //
129044 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129045 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
129046 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129047 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129048 // (AArch64uaddlp_n:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn) => (UADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn)
129049 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv2i32_v1i64),
129050 GIR_RootConstrainSelectedInstOperands,
129051 // GIR_Coverage, 1056,
129052 GIR_Done,
129053 // Label 7499: @351242
129054 GIM_Reject,
129055 // Label 7493: @351243
129056 GIM_Try, /*On fail goto*//*Label 7500*/ GIMT_Encode4(351269), // Rule ID 1052 //
129057 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129058 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
129059 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129060 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129061 // (AArch64uaddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn) => (UADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)
129062 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv4i16_v2i32),
129063 GIR_RootConstrainSelectedInstOperands,
129064 // GIR_Coverage, 1052,
129065 GIR_Done,
129066 // Label 7500: @351269
129067 GIM_Reject,
129068 // Label 7494: @351270
129069 GIM_Try, /*On fail goto*//*Label 7501*/ GIMT_Encode4(351296), // Rule ID 1058 //
129070 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129071 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
129072 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129073 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129074 // (AArch64uaddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn) => (UADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)
129075 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv4i32_v2i64),
129076 GIR_RootConstrainSelectedInstOperands,
129077 // GIR_Coverage, 1058,
129078 GIR_Done,
129079 // Label 7501: @351296
129080 GIM_Reject,
129081 // Label 7495: @351297
129082 GIM_Try, /*On fail goto*//*Label 7502*/ GIMT_Encode4(351323), // Rule ID 1048 //
129083 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129084 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
129085 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129086 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129087 // (AArch64uaddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn) => (UADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)
129088 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv8i8_v4i16),
129089 GIR_RootConstrainSelectedInstOperands,
129090 // GIR_Coverage, 1048,
129091 GIR_Done,
129092 // Label 7502: @351323
129093 GIM_Reject,
129094 // Label 7496: @351324
129095 GIM_Try, /*On fail goto*//*Label 7503*/ GIMT_Encode4(351350), // Rule ID 1054 //
129096 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129097 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
129098 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129099 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129100 // (AArch64uaddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn) => (UADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)
129101 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv8i16_v4i32),
129102 GIR_RootConstrainSelectedInstOperands,
129103 // GIR_Coverage, 1054,
129104 GIR_Done,
129105 // Label 7503: @351350
129106 GIM_Reject,
129107 // Label 7497: @351351
129108 GIM_Try, /*On fail goto*//*Label 7504*/ GIMT_Encode4(351377), // Rule ID 1050 //
129109 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129110 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
129111 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129112 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129113 // (AArch64uaddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn) => (UADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)
129114 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv16i8_v8i16),
129115 GIR_RootConstrainSelectedInstOperands,
129116 // GIR_Coverage, 1050,
129117 GIR_Done,
129118 // Label 7504: @351377
129119 GIM_Reject,
129120 // Label 7498: @351378
129121 GIM_Reject,
129122 // Label 136: @351379
129123 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(9), /*)*//*default:*//*Label 7507*/ GIMT_Encode4(352159),
129124 /*GILLT_v2s64*//*Label 7505*/ GIMT_Encode4(351402), GIMT_Encode4(0),
129125 /*GILLT_v4s32*//*Label 7506*/ GIMT_Encode4(351610),
129126 // Label 7505: @351402
129127 GIM_Try, /*On fail goto*//*Label 7508*/ GIMT_Encode4(351609),
129128 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
129129 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129130 GIM_Try, /*On fail goto*//*Label 7509*/ GIMT_Encode4(351489), // Rule ID 5474 //
129131 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
129132 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
129133 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
129134 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
129135 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
129136 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129137 GIM_CheckIsSafeToFold, /*NumInsns*/1,
129138 // (AArch64uaddlv:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v4i32] } 687:{ *:[iPTR] }, V128:{ *:[v8i16] }:$op)) => (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (UADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$op), ssub:{ *:[i32] })
129139 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
129140 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i16v),
129141 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
129142 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // op
129143 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
129144 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
129145 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
129146 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
129147 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
129148 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
129149 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
129150 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
129151 // GIR_Coverage, 5474,
129152 GIR_EraseRootFromParent_Done,
129153 // Label 7509: @351489
129154 GIM_Try, /*On fail goto*//*Label 7510*/ GIMT_Encode4(351556), // Rule ID 5473 //
129155 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
129156 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
129157 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
129158 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129159 GIM_CheckIsSafeToFold, /*NumInsns*/1,
129160 // (AArch64uaddlv:{ *:[v2i64] } (AArch64uaddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$op)) => (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (UADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$op), ssub:{ *:[i32] })
129161 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
129162 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i16v),
129163 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
129164 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // op
129165 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
129166 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
129167 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
129168 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
129169 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
129170 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
129171 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
129172 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
129173 // GIR_Coverage, 5473,
129174 GIR_EraseRootFromParent_Done,
129175 // Label 7510: @351556
129176 GIM_Try, /*On fail goto*//*Label 7511*/ GIMT_Encode4(351608), // Rule ID 5483 //
129177 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129178 // (AArch64uaddlv:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn) => (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (UADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn), dsub:{ *:[i32] })
129179 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
129180 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i32v),
129181 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
129182 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
129183 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
129184 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
129185 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
129186 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
129187 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
129188 GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
129189 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
129190 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
129191 // GIR_Coverage, 5483,
129192 GIR_EraseRootFromParent_Done,
129193 // Label 7511: @351608
129194 GIM_Reject,
129195 // Label 7508: @351609
129196 GIM_Reject,
129197 // Label 7506: @351610
129198 GIM_Try, /*On fail goto*//*Label 7512*/ GIMT_Encode4(351692), // Rule ID 5476 //
129199 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
129200 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129201 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
129202 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
129203 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
129204 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
129205 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
129206 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129207 GIM_CheckIsSafeToFold, /*NumInsns*/1,
129208 // (AArch64uaddlv:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v8i16] } 687:{ *:[iPTR] }, V128:{ *:[v16i8] }:$op)) => (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$op), hsub:{ *:[i32] })
129209 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
129210 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv16i8v),
129211 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
129212 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // op
129213 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
129214 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
129215 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
129216 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
129217 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
129218 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
129219 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
129220 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
129221 // GIR_Coverage, 5476,
129222 GIR_EraseRootFromParent_Done,
129223 // Label 7512: @351692
129224 GIM_Try, /*On fail goto*//*Label 7513*/ GIMT_Encode4(351774), // Rule ID 5478 //
129225 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
129226 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129227 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
129228 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
129229 GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
129230 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
129231 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
129232 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129233 GIM_CheckIsSafeToFold, /*NumInsns*/1,
129234 // (AArch64uaddlv:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 687:{ *:[iPTR] }, V64:{ *:[v8i8] }:$op)) => (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$op), hsub:{ *:[i32] })
129235 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
129236 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i8v),
129237 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
129238 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // op
129239 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
129240 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
129241 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
129242 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
129243 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
129244 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
129245 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
129246 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
129247 // GIR_Coverage, 5478,
129248 GIR_EraseRootFromParent_Done,
129249 // Label 7513: @351774
129250 GIM_Try, /*On fail goto*//*Label 7514*/ GIMT_Encode4(351848), // Rule ID 5475 //
129251 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
129252 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129253 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
129254 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
129255 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
129256 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129257 GIM_CheckIsSafeToFold, /*NumInsns*/1,
129258 // (AArch64uaddlv:{ *:[v4i32] } (AArch64uaddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$op)) => (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$op), hsub:{ *:[i32] })
129259 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
129260 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv16i8v),
129261 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
129262 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // op
129263 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
129264 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
129265 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
129266 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
129267 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
129268 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
129269 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
129270 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
129271 // GIR_Coverage, 5475,
129272 GIR_EraseRootFromParent_Done,
129273 // Label 7514: @351848
129274 GIM_Try, /*On fail goto*//*Label 7515*/ GIMT_Encode4(351922), // Rule ID 5477 //
129275 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
129276 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129277 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
129278 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
129279 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
129280 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129281 GIM_CheckIsSafeToFold, /*NumInsns*/1,
129282 // (AArch64uaddlv:{ *:[v4i32] } (AArch64uaddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$op)) => (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$op), hsub:{ *:[i32] })
129283 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
129284 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i8v),
129285 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
129286 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // op
129287 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
129288 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
129289 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
129290 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
129291 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
129292 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
129293 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
129294 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
129295 // GIR_Coverage, 5477,
129296 GIR_EraseRootFromParent_Done,
129297 // Label 7515: @351922
129298 GIM_Try, /*On fail goto*//*Label 7516*/ GIMT_Encode4(351981), // Rule ID 5479 //
129299 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
129300 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129301 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129302 // (AArch64uaddlv:{ *:[v4i32] } V64:{ *:[v8i8] }:$Rn) => (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn), hsub:{ *:[i32] })
129303 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
129304 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i8v),
129305 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
129306 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
129307 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
129308 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
129309 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
129310 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
129311 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
129312 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
129313 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
129314 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
129315 // GIR_Coverage, 5479,
129316 GIR_EraseRootFromParent_Done,
129317 // Label 7516: @351981
129318 GIM_Try, /*On fail goto*//*Label 7517*/ GIMT_Encode4(352040), // Rule ID 5480 //
129319 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
129320 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129321 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129322 // (AArch64uaddlv:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn) => (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn), ssub:{ *:[i32] })
129323 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
129324 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i16v),
129325 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
129326 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
129327 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
129328 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
129329 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
129330 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
129331 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
129332 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
129333 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
129334 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
129335 // GIR_Coverage, 5480,
129336 GIR_EraseRootFromParent_Done,
129337 // Label 7517: @352040
129338 GIM_Try, /*On fail goto*//*Label 7518*/ GIMT_Encode4(352099), // Rule ID 5481 //
129339 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
129340 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129341 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129342 // (AArch64uaddlv:{ *:[v4i32] } V128:{ *:[v16i8] }:$Rn) => (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn), hsub:{ *:[i32] })
129343 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
129344 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv16i8v),
129345 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
129346 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
129347 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
129348 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
129349 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
129350 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
129351 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
129352 GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
129353 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
129354 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
129355 // GIR_Coverage, 5481,
129356 GIR_EraseRootFromParent_Done,
129357 // Label 7518: @352099
129358 GIM_Try, /*On fail goto*//*Label 7519*/ GIMT_Encode4(352158), // Rule ID 5482 //
129359 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
129360 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129361 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129362 // (AArch64uaddlv:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn) => (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn), ssub:{ *:[i32] })
129363 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
129364 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i16v),
129365 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
129366 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
129367 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
129368 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
129369 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
129370 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
129371 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
129372 GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
129373 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
129374 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
129375 // GIR_Coverage, 5482,
129376 GIR_EraseRootFromParent_Done,
129377 // Label 7519: @352158
129378 GIM_Reject,
129379 // Label 7507: @352159
129380 GIM_Reject,
129381 // Label 137: @352160
129382 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(20), /*)*//*default:*//*Label 7524*/ GIMT_Encode4(352529),
129383 /*GILLT_v2s32*//*Label 7520*/ GIMT_Encode4(352231), GIMT_Encode4(0), GIMT_Encode4(0),
129384 /*GILLT_v4s32*//*Label 7521*/ GIMT_Encode4(352351), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
129385 /*GILLT_nxv2s64*//*Label 7522*/ GIMT_Encode4(352471), GIMT_Encode4(0), GIMT_Encode4(0),
129386 /*GILLT_nxv4s32*//*Label 7523*/ GIMT_Encode4(352500),
129387 // Label 7520: @352231
129388 GIM_Try, /*On fail goto*//*Label 7525*/ GIMT_Encode4(352350),
129389 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
129390 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
129391 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
129392 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129393 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129394 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129395 GIM_Try, /*On fail goto*//*Label 7526*/ GIMT_Encode4(352330), // Rule ID 28 //
129396 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
129397 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
129398 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
129399 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
129400 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
129401 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
129402 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
129403 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
129404 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129405 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
129406 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
129407 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
129408 // MIs[3] Operand 1
129409 // No operand predicates
129410 GIM_CheckIsSafeToFold, /*NumInsns*/3,
129411 // (AArch64udot:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, (bitconvert:{ *:[v8i8] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (UDOTlanev8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
129412 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDOTlanev8i8),
129413 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
129414 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
129415 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
129416 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
129417 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
129418 GIR_RootConstrainSelectedInstOperands,
129419 // GIR_Coverage, 28,
129420 GIR_EraseRootFromParent_Done,
129421 // Label 7526: @352330
129422 GIM_Try, /*On fail goto*//*Label 7527*/ GIMT_Encode4(352349), // Rule ID 24 //
129423 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
129424 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129425 // (AArch64udot:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UDOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
129426 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UDOTv8i8),
129427 GIR_RootConstrainSelectedInstOperands,
129428 // GIR_Coverage, 24,
129429 GIR_Done,
129430 // Label 7527: @352349
129431 GIM_Reject,
129432 // Label 7525: @352350
129433 GIM_Reject,
129434 // Label 7521: @352351
129435 GIM_Try, /*On fail goto*//*Label 7528*/ GIMT_Encode4(352470),
129436 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
129437 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
129438 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
129439 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129440 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129441 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129442 GIM_Try, /*On fail goto*//*Label 7529*/ GIMT_Encode4(352450), // Rule ID 29 //
129443 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
129444 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
129445 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
129446 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
129447 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
129448 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
129449 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
129450 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
129451 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129452 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
129453 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
129454 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
129455 // MIs[3] Operand 1
129456 // No operand predicates
129457 GIM_CheckIsSafeToFold, /*NumInsns*/3,
129458 // (AArch64udot:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, (bitconvert:{ *:[v16i8] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))) => (UDOTlanev16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
129459 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDOTlanev16i8),
129460 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
129461 GIR_RootToRootCopy, /*OpIdx*/1, // Rd
129462 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
129463 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
129464 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
129465 GIR_RootConstrainSelectedInstOperands,
129466 // GIR_Coverage, 29,
129467 GIR_EraseRootFromParent_Done,
129468 // Label 7529: @352450
129469 GIM_Try, /*On fail goto*//*Label 7530*/ GIMT_Encode4(352469), // Rule ID 25 //
129470 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
129471 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129472 // (AArch64udot:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UDOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
129473 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UDOTv16i8),
129474 GIR_RootConstrainSelectedInstOperands,
129475 // GIR_Coverage, 25,
129476 GIR_Done,
129477 // Label 7530: @352469
129478 GIM_Reject,
129479 // Label 7528: @352470
129480 GIM_Reject,
129481 // Label 7522: @352471
129482 GIM_Try, /*On fail goto*//*Label 7531*/ GIMT_Encode4(352499), // Rule ID 7313 //
129483 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
129484 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
129485 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
129486 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
129487 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
129488 // (AArch64udot:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3) => (UDOT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
129489 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UDOT_ZZZ_D),
129490 GIR_RootConstrainSelectedInstOperands,
129491 // GIR_Coverage, 7313,
129492 GIR_Done,
129493 // Label 7531: @352499
129494 GIM_Reject,
129495 // Label 7523: @352500
129496 GIM_Try, /*On fail goto*//*Label 7532*/ GIMT_Encode4(352528), // Rule ID 7312 //
129497 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
129498 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
129499 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
129500 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
129501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
129502 // (AArch64udot:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3) => (UDOT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
129503 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UDOT_ZZZ_S),
129504 GIR_RootConstrainSelectedInstOperands,
129505 // GIR_Coverage, 7312,
129506 GIR_Done,
129507 // Label 7532: @352528
129508 GIM_Reject,
129509 // Label 7524: @352529
129510 GIM_Reject,
129511 // Label 138: @352530
129512 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 7536*/ GIMT_Encode4(352646),
129513 /*GILLT_s16*//*Label 7533*/ GIMT_Encode4(352553),
129514 /*GILLT_s32*//*Label 7534*/ GIMT_Encode4(352584),
129515 /*GILLT_s64*//*Label 7535*/ GIMT_Encode4(352615),
129516 // Label 7533: @352553
129517 GIM_Try, /*On fail goto*//*Label 7537*/ GIMT_Encode4(352583), // Rule ID 1656 //
129518 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
129519 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
129520 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
129521 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
129522 // (AArch64uitof:{ *:[f16] } FPR16:{ *:[f16] }:$Rn) => (UCVTFv1i16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
129523 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i16),
129524 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
129525 GIR_RootConstrainSelectedInstOperands,
129526 // GIR_Coverage, 1656,
129527 GIR_Done,
129528 // Label 7537: @352583
129529 GIM_Reject,
129530 // Label 7534: @352584
129531 GIM_Try, /*On fail goto*//*Label 7538*/ GIMT_Encode4(352614), // Rule ID 1655 //
129532 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
129533 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
129534 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
129535 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
129536 // (AArch64uitof:{ *:[f32] } FPR32:{ *:[f32] }:$Rn) => (UCVTFv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
129537 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
129538 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
129539 GIR_RootConstrainSelectedInstOperands,
129540 // GIR_Coverage, 1655,
129541 GIR_Done,
129542 // Label 7538: @352614
129543 GIM_Reject,
129544 // Label 7535: @352615
129545 GIM_Try, /*On fail goto*//*Label 7539*/ GIMT_Encode4(352645), // Rule ID 1654 //
129546 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
129547 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
129548 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129549 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129550 // (AArch64uitof:{ *:[f64] } FPR64:{ *:[f64] }:$Rn) => (UCVTFv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
129551 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
129552 GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
129553 GIR_RootConstrainSelectedInstOperands,
129554 // GIR_Coverage, 1654,
129555 GIR_Done,
129556 // Label 7539: @352645
129557 GIM_Reject,
129558 // Label 7536: @352646
129559 GIM_Reject,
129560 // Label 139: @352647
129561 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(11), /*)*//*default:*//*Label 7543*/ GIMT_Encode4(353167),
129562 /*GILLT_v2s64*//*Label 7540*/ GIMT_Encode4(352678), GIMT_Encode4(0),
129563 /*GILLT_v4s32*//*Label 7541*/ GIMT_Encode4(352883), GIMT_Encode4(0),
129564 /*GILLT_v8s16*//*Label 7542*/ GIMT_Encode4(353088),
129565 // Label 7540: @352678
129566 GIM_Try, /*On fail goto*//*Label 7544*/ GIMT_Encode4(352882),
129567 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
129568 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
129569 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129570 GIM_Try, /*On fail goto*//*Label 7545*/ GIMT_Encode4(352732), // Rule ID 1818 //
129571 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129572 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
129573 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
129574 // (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)) => (UMULLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
129575 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i32_v2i64),
129576 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
129577 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
129578 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
129579 GIR_RootConstrainSelectedInstOperands,
129580 // GIR_Coverage, 1818,
129581 GIR_EraseRootFromParent_Done,
129582 // Label 7545: @352732
129583 GIM_Try, /*On fail goto*//*Label 7546*/ GIMT_Encode4(352795), // Rule ID 12776 //
129584 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129585 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
129586 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
129587 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
129588 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
129589 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129590 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
129591 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
129592 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
129593 // MIs[2] Operand 1
129594 // No operand predicates
129595 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129596 GIM_CheckIsSafeToFold, /*NumInsns*/2,
129597 // (AArch64umull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn) => (UMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
129598 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv2i32_indexed),
129599 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
129600 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
129601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
129602 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
129603 GIR_RootConstrainSelectedInstOperands,
129604 // GIR_Coverage, 12776,
129605 GIR_EraseRootFromParent_Done,
129606 // Label 7546: @352795
129607 GIM_Try, /*On fail goto*//*Label 7547*/ GIMT_Encode4(352858), // Rule ID 2092 //
129608 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129609 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129610 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
129611 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
129612 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
129613 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
129614 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129615 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
129616 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
129617 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
129618 // MIs[2] Operand 1
129619 // No operand predicates
129620 GIM_CheckIsSafeToFold, /*NumInsns*/2,
129621 // (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)) => (UMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
129622 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv2i32_indexed),
129623 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
129624 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
129625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
129626 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
129627 GIR_RootConstrainSelectedInstOperands,
129628 // GIR_Coverage, 2092,
129629 GIR_EraseRootFromParent_Done,
129630 // Label 7547: @352858
129631 GIM_Try, /*On fail goto*//*Label 7548*/ GIMT_Encode4(352881), // Rule ID 1817 //
129632 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129633 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129634 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129635 // (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UMULLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
129636 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMULLv2i32_v2i64),
129637 GIR_RootConstrainSelectedInstOperands,
129638 // GIR_Coverage, 1817,
129639 GIR_Done,
129640 // Label 7548: @352881
129641 GIM_Reject,
129642 // Label 7544: @352882
129643 GIM_Reject,
129644 // Label 7541: @352883
129645 GIM_Try, /*On fail goto*//*Label 7549*/ GIMT_Encode4(353087),
129646 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
129647 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
129648 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129649 GIM_Try, /*On fail goto*//*Label 7550*/ GIMT_Encode4(352937), // Rule ID 1816 //
129650 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129651 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
129652 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
129653 // (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)) => (UMULLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
129654 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv8i16_v4i32),
129655 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
129656 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
129657 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
129658 GIR_RootConstrainSelectedInstOperands,
129659 // GIR_Coverage, 1816,
129660 GIR_EraseRootFromParent_Done,
129661 // Label 7550: @352937
129662 GIM_Try, /*On fail goto*//*Label 7551*/ GIMT_Encode4(353000), // Rule ID 12773 //
129663 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129664 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
129665 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
129666 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
129667 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
129668 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
129669 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
129670 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
129671 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
129672 // MIs[2] Operand 1
129673 // No operand predicates
129674 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129675 GIM_CheckIsSafeToFold, /*NumInsns*/2,
129676 // (AArch64umull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn) => (UMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
129677 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i16_indexed),
129678 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
129679 GIR_RootToRootCopy, /*OpIdx*/2, // Rn
129680 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
129681 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
129682 GIR_RootConstrainSelectedInstOperands,
129683 // GIR_Coverage, 12773,
129684 GIR_EraseRootFromParent_Done,
129685 // Label 7551: @353000
129686 GIM_Try, /*On fail goto*//*Label 7552*/ GIMT_Encode4(353063), // Rule ID 2089 //
129687 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129688 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129689 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
129690 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
129691 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
129692 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
129693 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
129694 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
129695 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
129696 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
129697 // MIs[2] Operand 1
129698 // No operand predicates
129699 GIM_CheckIsSafeToFold, /*NumInsns*/2,
129700 // (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)) => (UMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
129701 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i16_indexed),
129702 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
129703 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
129704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
129705 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
129706 GIR_RootConstrainSelectedInstOperands,
129707 // GIR_Coverage, 2089,
129708 GIR_EraseRootFromParent_Done,
129709 // Label 7552: @353063
129710 GIM_Try, /*On fail goto*//*Label 7553*/ GIMT_Encode4(353086), // Rule ID 1815 //
129711 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129712 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129713 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129714 // (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UMULLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
129715 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i16_v4i32),
129716 GIR_RootConstrainSelectedInstOperands,
129717 // GIR_Coverage, 1815,
129718 GIR_Done,
129719 // Label 7553: @353086
129720 GIM_Reject,
129721 // Label 7549: @353087
129722 GIM_Reject,
129723 // Label 7542: @353088
129724 GIM_Try, /*On fail goto*//*Label 7554*/ GIMT_Encode4(353166),
129725 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
129726 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
129727 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129728 GIM_Try, /*On fail goto*//*Label 7555*/ GIMT_Encode4(353142), // Rule ID 1814 //
129729 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129730 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
129731 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
129732 // (AArch64umull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)) => (UMULLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
129733 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv16i8_v8i16),
129734 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
129735 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
129736 GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
129737 GIR_RootConstrainSelectedInstOperands,
129738 // GIR_Coverage, 1814,
129739 GIR_EraseRootFromParent_Done,
129740 // Label 7555: @353142
129741 GIM_Try, /*On fail goto*//*Label 7556*/ GIMT_Encode4(353165), // Rule ID 1813 //
129742 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129743 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129744 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129745 // (AArch64umull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UMULLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
129746 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMULLv8i8_v8i16),
129747 GIR_RootConstrainSelectedInstOperands,
129748 // GIR_Coverage, 1813,
129749 GIR_Done,
129750 // Label 7556: @353165
129751 GIM_Reject,
129752 // Label 7554: @353166
129753 GIM_Reject,
129754 // Label 7543: @353167
129755 GIM_Reject,
129756 // Label 140: @353168
129757 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 7575*/ GIMT_Encode4(353992),
129758 /*GILLT_v2s32*//*Label 7557*/ GIMT_Encode4(353255),
129759 /*GILLT_v2s64*//*Label 7558*/ GIMT_Encode4(353310),
129760 /*GILLT_v4s16*//*Label 7559*/ GIMT_Encode4(353365),
129761 /*GILLT_v4s32*//*Label 7560*/ GIMT_Encode4(353435),
129762 /*GILLT_v8s8*//*Label 7561*/ GIMT_Encode4(353490),
129763 /*GILLT_v8s16*//*Label 7562*/ GIMT_Encode4(353524),
129764 /*GILLT_v16s8*//*Label 7563*/ GIMT_Encode4(353594), GIMT_Encode4(0),
129765 /*GILLT_nxv2s1*//*Label 7564*/ GIMT_Encode4(353628),
129766 /*GILLT_nxv2s16*//*Label 7565*/ GIMT_Encode4(353654),
129767 /*GILLT_nxv2s32*//*Label 7566*/ GIMT_Encode4(353680),
129768 /*GILLT_nxv2s64*//*Label 7567*/ GIMT_Encode4(353706),
129769 /*GILLT_nxv4s1*//*Label 7568*/ GIMT_Encode4(353753),
129770 /*GILLT_nxv4s16*//*Label 7569*/ GIMT_Encode4(353779),
129771 /*GILLT_nxv4s32*//*Label 7570*/ GIMT_Encode4(353805),
129772 /*GILLT_nxv8s1*//*Label 7571*/ GIMT_Encode4(353852),
129773 /*GILLT_nxv8s16*//*Label 7572*/ GIMT_Encode4(353878),
129774 /*GILLT_nxv16s1*//*Label 7573*/ GIMT_Encode4(353940),
129775 /*GILLT_nxv16s8*//*Label 7574*/ GIMT_Encode4(353966),
129776 // Label 7557: @353255
129777 GIM_Try, /*On fail goto*//*Label 7576*/ GIMT_Encode4(353309),
129778 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
129779 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
129780 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129781 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129782 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129783 GIM_Try, /*On fail goto*//*Label 7577*/ GIMT_Encode4(353293), // Rule ID 1875 //
129784 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129785 // (AArch64uzp1:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UZP1v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
129786 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v2i32),
129787 GIR_RootConstrainSelectedInstOperands,
129788 // GIR_Coverage, 1875,
129789 GIR_Done,
129790 // Label 7577: @353293
129791 GIM_Try, /*On fail goto*//*Label 7578*/ GIMT_Encode4(353308), // Rule ID 5126 //
129792 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129793 // (AArch64uzp1:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (UZP1v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
129794 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v2i32),
129795 GIR_RootConstrainSelectedInstOperands,
129796 // GIR_Coverage, 5126,
129797 GIR_Done,
129798 // Label 7578: @353308
129799 GIM_Reject,
129800 // Label 7576: @353309
129801 GIM_Reject,
129802 // Label 7558: @353310
129803 GIM_Try, /*On fail goto*//*Label 7579*/ GIMT_Encode4(353364),
129804 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
129805 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
129806 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129807 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129808 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129809 GIM_Try, /*On fail goto*//*Label 7580*/ GIMT_Encode4(353348), // Rule ID 1877 //
129810 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129811 // (AArch64uzp1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UZP1v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
129812 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v2i64),
129813 GIR_RootConstrainSelectedInstOperands,
129814 // GIR_Coverage, 1877,
129815 GIR_Done,
129816 // Label 7580: @353348
129817 GIM_Try, /*On fail goto*//*Label 7581*/ GIMT_Encode4(353363), // Rule ID 5128 //
129818 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129819 // (AArch64uzp1:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (UZP1v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
129820 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v2i64),
129821 GIR_RootConstrainSelectedInstOperands,
129822 // GIR_Coverage, 5128,
129823 GIR_Done,
129824 // Label 7581: @353363
129825 GIM_Reject,
129826 // Label 7579: @353364
129827 GIM_Reject,
129828 // Label 7559: @353365
129829 GIM_Try, /*On fail goto*//*Label 7582*/ GIMT_Encode4(353434),
129830 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
129831 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
129832 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129833 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129834 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129835 GIM_Try, /*On fail goto*//*Label 7583*/ GIMT_Encode4(353403), // Rule ID 1873 //
129836 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129837 // (AArch64uzp1:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UZP1v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
129838 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i16),
129839 GIR_RootConstrainSelectedInstOperands,
129840 // GIR_Coverage, 1873,
129841 GIR_Done,
129842 // Label 7583: @353403
129843 GIM_Try, /*On fail goto*//*Label 7584*/ GIMT_Encode4(353418), // Rule ID 5122 //
129844 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129845 // (AArch64uzp1:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (UZP1v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
129846 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i16),
129847 GIR_RootConstrainSelectedInstOperands,
129848 // GIR_Coverage, 5122,
129849 GIR_Done,
129850 // Label 7584: @353418
129851 GIM_Try, /*On fail goto*//*Label 7585*/ GIMT_Encode4(353433), // Rule ID 5123 //
129852 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129853 // (AArch64uzp1:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) => (UZP1v4i16:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm)
129854 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i16),
129855 GIR_RootConstrainSelectedInstOperands,
129856 // GIR_Coverage, 5123,
129857 GIR_Done,
129858 // Label 7585: @353433
129859 GIM_Reject,
129860 // Label 7582: @353434
129861 GIM_Reject,
129862 // Label 7560: @353435
129863 GIM_Try, /*On fail goto*//*Label 7586*/ GIMT_Encode4(353489),
129864 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
129865 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
129866 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129867 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129868 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129869 GIM_Try, /*On fail goto*//*Label 7587*/ GIMT_Encode4(353473), // Rule ID 1876 //
129870 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129871 // (AArch64uzp1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UZP1v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
129872 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i32),
129873 GIR_RootConstrainSelectedInstOperands,
129874 // GIR_Coverage, 1876,
129875 GIR_Done,
129876 // Label 7587: @353473
129877 GIM_Try, /*On fail goto*//*Label 7588*/ GIMT_Encode4(353488), // Rule ID 5127 //
129878 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129879 // (AArch64uzp1:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (UZP1v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
129880 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i32),
129881 GIR_RootConstrainSelectedInstOperands,
129882 // GIR_Coverage, 5127,
129883 GIR_Done,
129884 // Label 7588: @353488
129885 GIM_Reject,
129886 // Label 7586: @353489
129887 GIM_Reject,
129888 // Label 7561: @353490
129889 GIM_Try, /*On fail goto*//*Label 7589*/ GIMT_Encode4(353523), // Rule ID 1871 //
129890 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129891 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
129892 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
129893 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129894 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129895 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
129896 // (AArch64uzp1:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UZP1v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
129897 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v8i8),
129898 GIR_RootConstrainSelectedInstOperands,
129899 // GIR_Coverage, 1871,
129900 GIR_Done,
129901 // Label 7589: @353523
129902 GIM_Reject,
129903 // Label 7562: @353524
129904 GIM_Try, /*On fail goto*//*Label 7590*/ GIMT_Encode4(353593),
129905 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
129906 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
129907 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129908 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129909 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129910 GIM_Try, /*On fail goto*//*Label 7591*/ GIMT_Encode4(353562), // Rule ID 1874 //
129911 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129912 // (AArch64uzp1:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UZP1v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
129913 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v8i16),
129914 GIR_RootConstrainSelectedInstOperands,
129915 // GIR_Coverage, 1874,
129916 GIR_Done,
129917 // Label 7591: @353562
129918 GIM_Try, /*On fail goto*//*Label 7592*/ GIMT_Encode4(353577), // Rule ID 5124 //
129919 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129920 // (AArch64uzp1:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (UZP1v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
129921 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v8i16),
129922 GIR_RootConstrainSelectedInstOperands,
129923 // GIR_Coverage, 5124,
129924 GIR_Done,
129925 // Label 7592: @353577
129926 GIM_Try, /*On fail goto*//*Label 7593*/ GIMT_Encode4(353592), // Rule ID 5125 //
129927 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129928 // (AArch64uzp1:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (UZP1v8i16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm)
129929 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v8i16),
129930 GIR_RootConstrainSelectedInstOperands,
129931 // GIR_Coverage, 5125,
129932 GIR_Done,
129933 // Label 7593: @353592
129934 GIM_Reject,
129935 // Label 7590: @353593
129936 GIM_Reject,
129937 // Label 7563: @353594
129938 GIM_Try, /*On fail goto*//*Label 7594*/ GIMT_Encode4(353627), // Rule ID 1872 //
129939 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
129940 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
129941 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
129942 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129943 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129944 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
129945 // (AArch64uzp1:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UZP1v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
129946 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v16i8),
129947 GIR_RootConstrainSelectedInstOperands,
129948 // GIR_Coverage, 1872,
129949 GIR_Done,
129950 // Label 7594: @353627
129951 GIM_Reject,
129952 // Label 7564: @353628
129953 GIM_Try, /*On fail goto*//*Label 7595*/ GIMT_Encode4(353653), // Rule ID 8640 //
129954 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
129955 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
129956 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
129957 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
129958 // (AArch64uzp1:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2) => (UZP1_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
129959 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_D),
129960 GIR_RootConstrainSelectedInstOperands,
129961 // GIR_Coverage, 8640,
129962 GIR_Done,
129963 // Label 7595: @353653
129964 GIM_Reject,
129965 // Label 7565: @353654
129966 GIM_Try, /*On fail goto*//*Label 7596*/ GIMT_Encode4(353679), // Rule ID 8598 //
129967 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
129968 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
129969 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
129970 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
129971 // (AArch64uzp1:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2) => (UZP1_ZZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$Op1, ?:{ *:[nxv2f16] }:$Op2)
129972 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_D),
129973 GIR_RootConstrainSelectedInstOperands,
129974 // GIR_Coverage, 8598,
129975 GIR_Done,
129976 // Label 7596: @353679
129977 GIM_Reject,
129978 // Label 7566: @353680
129979 GIM_Try, /*On fail goto*//*Label 7597*/ GIMT_Encode4(353705), // Rule ID 8599 //
129980 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
129981 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
129982 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
129983 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
129984 // (AArch64uzp1:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2) => (UZP1_ZZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$Op1, ?:{ *:[nxv2f32] }:$Op2)
129985 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_D),
129986 GIR_RootConstrainSelectedInstOperands,
129987 // GIR_Coverage, 8599,
129988 GIR_Done,
129989 // Label 7597: @353705
129990 GIM_Reject,
129991 // Label 7567: @353706
129992 GIM_Try, /*On fail goto*//*Label 7598*/ GIMT_Encode4(353752),
129993 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
129994 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
129995 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
129996 GIM_Try, /*On fail goto*//*Label 7599*/ GIMT_Encode4(353736), // Rule ID 8594 //
129997 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
129998 // (AArch64uzp1:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (UZP1_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
129999 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_D),
130000 GIR_RootConstrainSelectedInstOperands,
130001 // GIR_Coverage, 8594,
130002 GIR_Done,
130003 // Label 7599: @353736
130004 GIM_Try, /*On fail goto*//*Label 7600*/ GIMT_Encode4(353751), // Rule ID 8600 //
130005 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130006 // (AArch64uzp1:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (UZP1_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
130007 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_D),
130008 GIR_RootConstrainSelectedInstOperands,
130009 // GIR_Coverage, 8600,
130010 GIR_Done,
130011 // Label 7600: @353751
130012 GIM_Reject,
130013 // Label 7598: @353752
130014 GIM_Reject,
130015 // Label 7568: @353753
130016 GIM_Try, /*On fail goto*//*Label 7601*/ GIMT_Encode4(353778), // Rule ID 8639 //
130017 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130018 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
130019 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
130020 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
130021 // (AArch64uzp1:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2) => (UZP1_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
130022 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_S),
130023 GIR_RootConstrainSelectedInstOperands,
130024 // GIR_Coverage, 8639,
130025 GIR_Done,
130026 // Label 7601: @353778
130027 GIM_Reject,
130028 // Label 7569: @353779
130029 GIM_Try, /*On fail goto*//*Label 7602*/ GIMT_Encode4(353804), // Rule ID 8596 //
130030 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130031 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
130032 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
130033 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
130034 // (AArch64uzp1:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2) => (UZP1_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$Op1, ?:{ *:[nxv4f16] }:$Op2)
130035 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_S),
130036 GIR_RootConstrainSelectedInstOperands,
130037 // GIR_Coverage, 8596,
130038 GIR_Done,
130039 // Label 7602: @353804
130040 GIM_Reject,
130041 // Label 7570: @353805
130042 GIM_Try, /*On fail goto*//*Label 7603*/ GIMT_Encode4(353851),
130043 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
130044 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
130045 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
130046 GIM_Try, /*On fail goto*//*Label 7604*/ GIMT_Encode4(353835), // Rule ID 8593 //
130047 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130048 // (AArch64uzp1:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (UZP1_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
130049 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_S),
130050 GIR_RootConstrainSelectedInstOperands,
130051 // GIR_Coverage, 8593,
130052 GIR_Done,
130053 // Label 7604: @353835
130054 GIM_Try, /*On fail goto*//*Label 7605*/ GIMT_Encode4(353850), // Rule ID 8597 //
130055 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130056 // (AArch64uzp1:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (UZP1_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
130057 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_S),
130058 GIR_RootConstrainSelectedInstOperands,
130059 // GIR_Coverage, 8597,
130060 GIR_Done,
130061 // Label 7605: @353850
130062 GIM_Reject,
130063 // Label 7603: @353851
130064 GIM_Reject,
130065 // Label 7571: @353852
130066 GIM_Try, /*On fail goto*//*Label 7606*/ GIMT_Encode4(353877), // Rule ID 8638 //
130067 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130068 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
130069 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
130070 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
130071 // (AArch64uzp1:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2) => (UZP1_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
130072 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_H),
130073 GIR_RootConstrainSelectedInstOperands,
130074 // GIR_Coverage, 8638,
130075 GIR_Done,
130076 // Label 7606: @353877
130077 GIM_Reject,
130078 // Label 7572: @353878
130079 GIM_Try, /*On fail goto*//*Label 7607*/ GIMT_Encode4(353939),
130080 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
130081 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
130082 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
130083 GIM_Try, /*On fail goto*//*Label 7608*/ GIMT_Encode4(353908), // Rule ID 8592 //
130084 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130085 // (AArch64uzp1:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (UZP1_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
130086 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_H),
130087 GIR_RootConstrainSelectedInstOperands,
130088 // GIR_Coverage, 8592,
130089 GIR_Done,
130090 // Label 7608: @353908
130091 GIM_Try, /*On fail goto*//*Label 7609*/ GIMT_Encode4(353923), // Rule ID 8595 //
130092 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130093 // (AArch64uzp1:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (UZP1_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
130094 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_H),
130095 GIR_RootConstrainSelectedInstOperands,
130096 // GIR_Coverage, 8595,
130097 GIR_Done,
130098 // Label 7609: @353923
130099 GIM_Try, /*On fail goto*//*Label 7610*/ GIMT_Encode4(353938), // Rule ID 8601 //
130100 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130101 // (AArch64uzp1:{ *:[nxv8bf16] } nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2) => (UZP1_ZZZ_H:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2)
130102 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_H),
130103 GIR_RootConstrainSelectedInstOperands,
130104 // GIR_Coverage, 8601,
130105 GIR_Done,
130106 // Label 7610: @353938
130107 GIM_Reject,
130108 // Label 7607: @353939
130109 GIM_Reject,
130110 // Label 7573: @353940
130111 GIM_Try, /*On fail goto*//*Label 7611*/ GIMT_Encode4(353965), // Rule ID 2346 //
130112 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130113 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
130114 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
130115 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
130116 // (AArch64uzp1:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (UZP1_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
130117 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_B),
130118 GIR_RootConstrainSelectedInstOperands,
130119 // GIR_Coverage, 2346,
130120 GIR_Done,
130121 // Label 7611: @353965
130122 GIM_Reject,
130123 // Label 7574: @353966
130124 GIM_Try, /*On fail goto*//*Label 7612*/ GIMT_Encode4(353991), // Rule ID 8591 //
130125 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130126 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
130127 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
130128 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
130129 // (AArch64uzp1:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (UZP1_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
130130 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_B),
130131 GIR_RootConstrainSelectedInstOperands,
130132 // GIR_Coverage, 8591,
130133 GIR_Done,
130134 // Label 7612: @353991
130135 GIM_Reject,
130136 // Label 7575: @353992
130137 GIM_Reject,
130138 // Label 141: @353993
130139 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 7631*/ GIMT_Encode4(354817),
130140 /*GILLT_v2s32*//*Label 7613*/ GIMT_Encode4(354080),
130141 /*GILLT_v2s64*//*Label 7614*/ GIMT_Encode4(354135),
130142 /*GILLT_v4s16*//*Label 7615*/ GIMT_Encode4(354190),
130143 /*GILLT_v4s32*//*Label 7616*/ GIMT_Encode4(354260),
130144 /*GILLT_v8s8*//*Label 7617*/ GIMT_Encode4(354315),
130145 /*GILLT_v8s16*//*Label 7618*/ GIMT_Encode4(354349),
130146 /*GILLT_v16s8*//*Label 7619*/ GIMT_Encode4(354419), GIMT_Encode4(0),
130147 /*GILLT_nxv2s1*//*Label 7620*/ GIMT_Encode4(354453),
130148 /*GILLT_nxv2s16*//*Label 7621*/ GIMT_Encode4(354479),
130149 /*GILLT_nxv2s32*//*Label 7622*/ GIMT_Encode4(354505),
130150 /*GILLT_nxv2s64*//*Label 7623*/ GIMT_Encode4(354531),
130151 /*GILLT_nxv4s1*//*Label 7624*/ GIMT_Encode4(354578),
130152 /*GILLT_nxv4s16*//*Label 7625*/ GIMT_Encode4(354604),
130153 /*GILLT_nxv4s32*//*Label 7626*/ GIMT_Encode4(354630),
130154 /*GILLT_nxv8s1*//*Label 7627*/ GIMT_Encode4(354677),
130155 /*GILLT_nxv8s16*//*Label 7628*/ GIMT_Encode4(354703),
130156 /*GILLT_nxv16s1*//*Label 7629*/ GIMT_Encode4(354765),
130157 /*GILLT_nxv16s8*//*Label 7630*/ GIMT_Encode4(354791),
130158 // Label 7613: @354080
130159 GIM_Try, /*On fail goto*//*Label 7632*/ GIMT_Encode4(354134),
130160 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
130161 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
130162 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130163 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130164 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130165 GIM_Try, /*On fail goto*//*Label 7633*/ GIMT_Encode4(354118), // Rule ID 1882 //
130166 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130167 // (AArch64uzp2:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (UZP2v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
130168 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v2i32),
130169 GIR_RootConstrainSelectedInstOperands,
130170 // GIR_Coverage, 1882,
130171 GIR_Done,
130172 // Label 7633: @354118
130173 GIM_Try, /*On fail goto*//*Label 7634*/ GIMT_Encode4(354133), // Rule ID 5133 //
130174 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130175 // (AArch64uzp2:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (UZP2v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
130176 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v2i32),
130177 GIR_RootConstrainSelectedInstOperands,
130178 // GIR_Coverage, 5133,
130179 GIR_Done,
130180 // Label 7634: @354133
130181 GIM_Reject,
130182 // Label 7632: @354134
130183 GIM_Reject,
130184 // Label 7614: @354135
130185 GIM_Try, /*On fail goto*//*Label 7635*/ GIMT_Encode4(354189),
130186 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
130187 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
130188 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130189 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130190 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130191 GIM_Try, /*On fail goto*//*Label 7636*/ GIMT_Encode4(354173), // Rule ID 1884 //
130192 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130193 // (AArch64uzp2:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (UZP2v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
130194 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v2i64),
130195 GIR_RootConstrainSelectedInstOperands,
130196 // GIR_Coverage, 1884,
130197 GIR_Done,
130198 // Label 7636: @354173
130199 GIM_Try, /*On fail goto*//*Label 7637*/ GIMT_Encode4(354188), // Rule ID 5135 //
130200 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130201 // (AArch64uzp2:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (UZP2v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
130202 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v2i64),
130203 GIR_RootConstrainSelectedInstOperands,
130204 // GIR_Coverage, 5135,
130205 GIR_Done,
130206 // Label 7637: @354188
130207 GIM_Reject,
130208 // Label 7635: @354189
130209 GIM_Reject,
130210 // Label 7615: @354190
130211 GIM_Try, /*On fail goto*//*Label 7638*/ GIMT_Encode4(354259),
130212 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
130213 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
130214 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130215 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130216 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130217 GIM_Try, /*On fail goto*//*Label 7639*/ GIMT_Encode4(354228), // Rule ID 1880 //
130218 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130219 // (AArch64uzp2:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (UZP2v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
130220 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i16),
130221 GIR_RootConstrainSelectedInstOperands,
130222 // GIR_Coverage, 1880,
130223 GIR_Done,
130224 // Label 7639: @354228
130225 GIM_Try, /*On fail goto*//*Label 7640*/ GIMT_Encode4(354243), // Rule ID 5129 //
130226 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130227 // (AArch64uzp2:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (UZP2v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
130228 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i16),
130229 GIR_RootConstrainSelectedInstOperands,
130230 // GIR_Coverage, 5129,
130231 GIR_Done,
130232 // Label 7640: @354243
130233 GIM_Try, /*On fail goto*//*Label 7641*/ GIMT_Encode4(354258), // Rule ID 5130 //
130234 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130235 // (AArch64uzp2:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) => (UZP2v4i16:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm)
130236 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i16),
130237 GIR_RootConstrainSelectedInstOperands,
130238 // GIR_Coverage, 5130,
130239 GIR_Done,
130240 // Label 7641: @354258
130241 GIM_Reject,
130242 // Label 7638: @354259
130243 GIM_Reject,
130244 // Label 7616: @354260
130245 GIM_Try, /*On fail goto*//*Label 7642*/ GIMT_Encode4(354314),
130246 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
130247 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
130248 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130249 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130250 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130251 GIM_Try, /*On fail goto*//*Label 7643*/ GIMT_Encode4(354298), // Rule ID 1883 //
130252 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130253 // (AArch64uzp2:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (UZP2v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
130254 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i32),
130255 GIR_RootConstrainSelectedInstOperands,
130256 // GIR_Coverage, 1883,
130257 GIR_Done,
130258 // Label 7643: @354298
130259 GIM_Try, /*On fail goto*//*Label 7644*/ GIMT_Encode4(354313), // Rule ID 5134 //
130260 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130261 // (AArch64uzp2:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (UZP2v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
130262 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i32),
130263 GIR_RootConstrainSelectedInstOperands,
130264 // GIR_Coverage, 5134,
130265 GIR_Done,
130266 // Label 7644: @354313
130267 GIM_Reject,
130268 // Label 7642: @354314
130269 GIM_Reject,
130270 // Label 7617: @354315
130271 GIM_Try, /*On fail goto*//*Label 7645*/ GIMT_Encode4(354348), // Rule ID 1878 //
130272 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130273 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
130274 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
130275 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130276 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130277 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130278 // (AArch64uzp2:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (UZP2v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
130279 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i8),
130280 GIR_RootConstrainSelectedInstOperands,
130281 // GIR_Coverage, 1878,
130282 GIR_Done,
130283 // Label 7645: @354348
130284 GIM_Reject,
130285 // Label 7618: @354349
130286 GIM_Try, /*On fail goto*//*Label 7646*/ GIMT_Encode4(354418),
130287 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
130288 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
130289 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130290 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130291 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130292 GIM_Try, /*On fail goto*//*Label 7647*/ GIMT_Encode4(354387), // Rule ID 1881 //
130293 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130294 // (AArch64uzp2:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (UZP2v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
130295 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
130296 GIR_RootConstrainSelectedInstOperands,
130297 // GIR_Coverage, 1881,
130298 GIR_Done,
130299 // Label 7647: @354387
130300 GIM_Try, /*On fail goto*//*Label 7648*/ GIMT_Encode4(354402), // Rule ID 5131 //
130301 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130302 // (AArch64uzp2:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (UZP2v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
130303 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
130304 GIR_RootConstrainSelectedInstOperands,
130305 // GIR_Coverage, 5131,
130306 GIR_Done,
130307 // Label 7648: @354402
130308 GIM_Try, /*On fail goto*//*Label 7649*/ GIMT_Encode4(354417), // Rule ID 5132 //
130309 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130310 // (AArch64uzp2:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (UZP2v8i16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm)
130311 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
130312 GIR_RootConstrainSelectedInstOperands,
130313 // GIR_Coverage, 5132,
130314 GIR_Done,
130315 // Label 7649: @354417
130316 GIM_Reject,
130317 // Label 7646: @354418
130318 GIM_Reject,
130319 // Label 7619: @354419
130320 GIM_Try, /*On fail goto*//*Label 7650*/ GIMT_Encode4(354452), // Rule ID 1879 //
130321 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130322 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
130323 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
130324 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130325 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130326 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130327 // (AArch64uzp2:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (UZP2v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
130328 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v16i8),
130329 GIR_RootConstrainSelectedInstOperands,
130330 // GIR_Coverage, 1879,
130331 GIR_Done,
130332 // Label 7650: @354452
130333 GIM_Reject,
130334 // Label 7620: @354453
130335 GIM_Try, /*On fail goto*//*Label 7651*/ GIMT_Encode4(354478), // Rule ID 8643 //
130336 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130337 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
130338 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
130339 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
130340 // (AArch64uzp2:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2) => (UZP2_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
130341 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_D),
130342 GIR_RootConstrainSelectedInstOperands,
130343 // GIR_Coverage, 8643,
130344 GIR_Done,
130345 // Label 7651: @354478
130346 GIM_Reject,
130347 // Label 7621: @354479
130348 GIM_Try, /*On fail goto*//*Label 7652*/ GIMT_Encode4(354504), // Rule ID 8609 //
130349 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130350 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
130351 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
130352 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
130353 // (AArch64uzp2:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2) => (UZP2_ZZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$Op1, ?:{ *:[nxv2f16] }:$Op2)
130354 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_D),
130355 GIR_RootConstrainSelectedInstOperands,
130356 // GIR_Coverage, 8609,
130357 GIR_Done,
130358 // Label 7652: @354504
130359 GIM_Reject,
130360 // Label 7622: @354505
130361 GIM_Try, /*On fail goto*//*Label 7653*/ GIMT_Encode4(354530), // Rule ID 8610 //
130362 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130363 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
130364 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
130365 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
130366 // (AArch64uzp2:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2) => (UZP2_ZZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$Op1, ?:{ *:[nxv2f32] }:$Op2)
130367 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_D),
130368 GIR_RootConstrainSelectedInstOperands,
130369 // GIR_Coverage, 8610,
130370 GIR_Done,
130371 // Label 7653: @354530
130372 GIM_Reject,
130373 // Label 7623: @354531
130374 GIM_Try, /*On fail goto*//*Label 7654*/ GIMT_Encode4(354577),
130375 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
130376 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
130377 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
130378 GIM_Try, /*On fail goto*//*Label 7655*/ GIMT_Encode4(354561), // Rule ID 8605 //
130379 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130380 // (AArch64uzp2:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (UZP2_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
130381 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_D),
130382 GIR_RootConstrainSelectedInstOperands,
130383 // GIR_Coverage, 8605,
130384 GIR_Done,
130385 // Label 7655: @354561
130386 GIM_Try, /*On fail goto*//*Label 7656*/ GIMT_Encode4(354576), // Rule ID 8611 //
130387 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130388 // (AArch64uzp2:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (UZP2_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
130389 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_D),
130390 GIR_RootConstrainSelectedInstOperands,
130391 // GIR_Coverage, 8611,
130392 GIR_Done,
130393 // Label 7656: @354576
130394 GIM_Reject,
130395 // Label 7654: @354577
130396 GIM_Reject,
130397 // Label 7624: @354578
130398 GIM_Try, /*On fail goto*//*Label 7657*/ GIMT_Encode4(354603), // Rule ID 8642 //
130399 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130400 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
130401 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
130402 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
130403 // (AArch64uzp2:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2) => (UZP2_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
130404 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_S),
130405 GIR_RootConstrainSelectedInstOperands,
130406 // GIR_Coverage, 8642,
130407 GIR_Done,
130408 // Label 7657: @354603
130409 GIM_Reject,
130410 // Label 7625: @354604
130411 GIM_Try, /*On fail goto*//*Label 7658*/ GIMT_Encode4(354629), // Rule ID 8607 //
130412 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130413 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
130414 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
130415 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
130416 // (AArch64uzp2:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2) => (UZP2_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$Op1, ?:{ *:[nxv4f16] }:$Op2)
130417 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_S),
130418 GIR_RootConstrainSelectedInstOperands,
130419 // GIR_Coverage, 8607,
130420 GIR_Done,
130421 // Label 7658: @354629
130422 GIM_Reject,
130423 // Label 7626: @354630
130424 GIM_Try, /*On fail goto*//*Label 7659*/ GIMT_Encode4(354676),
130425 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
130426 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
130427 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
130428 GIM_Try, /*On fail goto*//*Label 7660*/ GIMT_Encode4(354660), // Rule ID 8604 //
130429 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130430 // (AArch64uzp2:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (UZP2_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
130431 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_S),
130432 GIR_RootConstrainSelectedInstOperands,
130433 // GIR_Coverage, 8604,
130434 GIR_Done,
130435 // Label 7660: @354660
130436 GIM_Try, /*On fail goto*//*Label 7661*/ GIMT_Encode4(354675), // Rule ID 8608 //
130437 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130438 // (AArch64uzp2:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (UZP2_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
130439 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_S),
130440 GIR_RootConstrainSelectedInstOperands,
130441 // GIR_Coverage, 8608,
130442 GIR_Done,
130443 // Label 7661: @354675
130444 GIM_Reject,
130445 // Label 7659: @354676
130446 GIM_Reject,
130447 // Label 7627: @354677
130448 GIM_Try, /*On fail goto*//*Label 7662*/ GIMT_Encode4(354702), // Rule ID 8641 //
130449 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130450 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
130451 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
130452 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
130453 // (AArch64uzp2:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2) => (UZP2_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
130454 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_H),
130455 GIR_RootConstrainSelectedInstOperands,
130456 // GIR_Coverage, 8641,
130457 GIR_Done,
130458 // Label 7662: @354702
130459 GIM_Reject,
130460 // Label 7628: @354703
130461 GIM_Try, /*On fail goto*//*Label 7663*/ GIMT_Encode4(354764),
130462 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
130463 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
130464 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
130465 GIM_Try, /*On fail goto*//*Label 7664*/ GIMT_Encode4(354733), // Rule ID 8603 //
130466 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130467 // (AArch64uzp2:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (UZP2_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
130468 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_H),
130469 GIR_RootConstrainSelectedInstOperands,
130470 // GIR_Coverage, 8603,
130471 GIR_Done,
130472 // Label 7664: @354733
130473 GIM_Try, /*On fail goto*//*Label 7665*/ GIMT_Encode4(354748), // Rule ID 8606 //
130474 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130475 // (AArch64uzp2:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (UZP2_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
130476 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_H),
130477 GIR_RootConstrainSelectedInstOperands,
130478 // GIR_Coverage, 8606,
130479 GIR_Done,
130480 // Label 7665: @354748
130481 GIM_Try, /*On fail goto*//*Label 7666*/ GIMT_Encode4(354763), // Rule ID 8612 //
130482 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130483 // (AArch64uzp2:{ *:[nxv8bf16] } nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2) => (UZP2_ZZZ_H:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2)
130484 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_H),
130485 GIR_RootConstrainSelectedInstOperands,
130486 // GIR_Coverage, 8612,
130487 GIR_Done,
130488 // Label 7666: @354763
130489 GIM_Reject,
130490 // Label 7663: @354764
130491 GIM_Reject,
130492 // Label 7629: @354765
130493 GIM_Try, /*On fail goto*//*Label 7667*/ GIMT_Encode4(354790), // Rule ID 2350 //
130494 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130495 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
130496 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
130497 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
130498 // (AArch64uzp2:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (UZP2_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
130499 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_B),
130500 GIR_RootConstrainSelectedInstOperands,
130501 // GIR_Coverage, 2350,
130502 GIR_Done,
130503 // Label 7667: @354790
130504 GIM_Reject,
130505 // Label 7630: @354791
130506 GIM_Try, /*On fail goto*//*Label 7668*/ GIMT_Encode4(354816), // Rule ID 8602 //
130507 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
130508 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
130509 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
130510 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
130511 // (AArch64uzp2:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (UZP2_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
130512 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_B),
130513 GIR_RootConstrainSelectedInstOperands,
130514 // GIR_Coverage, 8602,
130515 GIR_Done,
130516 // Label 7668: @354816
130517 GIM_Reject,
130518 // Label 7631: @354817
130519 GIM_Reject,
130520 // Label 142: @354818
130521 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(12), /*)*//*default:*//*Label 7677*/ GIMT_Encode4(355515),
130522 /*GILLT_s64*//*Label 7669*/ GIMT_Encode4(354865), GIMT_Encode4(0),
130523 /*GILLT_v2s32*//*Label 7670*/ GIMT_Encode4(354976),
130524 /*GILLT_v2s64*//*Label 7671*/ GIMT_Encode4(355053),
130525 /*GILLT_v4s16*//*Label 7672*/ GIMT_Encode4(355130),
130526 /*GILLT_v4s32*//*Label 7673*/ GIMT_Encode4(355207),
130527 /*GILLT_v8s8*//*Label 7674*/ GIMT_Encode4(355284),
130528 /*GILLT_v8s16*//*Label 7675*/ GIMT_Encode4(355361),
130529 /*GILLT_v16s8*//*Label 7676*/ GIMT_Encode4(355438),
130530 // Label 7669: @354865
130531 GIM_Try, /*On fail goto*//*Label 7678*/ GIMT_Encode4(354975),
130532 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
130533 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130534 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130535 GIM_Try, /*On fail goto*//*Label 7679*/ GIMT_Encode4(354906), // Rule ID 4898 //
130536 // MIs[0] Operand 2
130537 GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(63),
130538 // (AArch64vashr:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, 63:{ *:[i32] }) => (CMLTv1i64rz:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn)
130539 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv1i64rz),
130540 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130541 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130542 GIR_RootConstrainSelectedInstOperands,
130543 // GIR_Coverage, 4898,
130544 GIR_EraseRootFromParent_Done,
130545 // Label 7679: @354906
130546 GIM_Try, /*On fail goto*//*Label 7680*/ GIMT_Encode4(354940), // Rule ID 2105 //
130547 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130548 // MIs[0] imm
130549 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
130550 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
130551 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
130552 // MIs[1] Operand 1
130553 // No operand predicates
130554 GIM_CheckIsSafeToFold, /*NumInsns*/1,
130555 // (AArch64vashr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (SSHRd:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
130556 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHRd),
130557 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130558 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130559 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
130560 GIR_RootConstrainSelectedInstOperands,
130561 // GIR_Coverage, 2105,
130562 GIR_EraseRootFromParent_Done,
130563 // Label 7680: @354940
130564 GIM_Try, /*On fail goto*//*Label 7681*/ GIMT_Encode4(354974), // Rule ID 5880 //
130565 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130566 // MIs[0] imm
130567 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
130568 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
130569 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
130570 // MIs[1] Operand 1
130571 // No operand predicates
130572 GIM_CheckIsSafeToFold, /*NumInsns*/1,
130573 // (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (SSHRd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
130574 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHRd),
130575 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130576 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130577 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
130578 GIR_RootConstrainSelectedInstOperands,
130579 // GIR_Coverage, 5880,
130580 GIR_EraseRootFromParent_Done,
130581 // Label 7681: @354974
130582 GIM_Reject,
130583 // Label 7678: @354975
130584 GIM_Reject,
130585 // Label 7670: @354976
130586 GIM_Try, /*On fail goto*//*Label 7682*/ GIMT_Encode4(355052),
130587 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
130588 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130589 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130590 GIM_Try, /*On fail goto*//*Label 7683*/ GIMT_Encode4(355017), // Rule ID 4552 //
130591 // MIs[0] Operand 2
130592 GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(31),
130593 // (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, 31:{ *:[i32] }) => (CMLTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
130594 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i32rz),
130595 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130596 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130597 GIR_RootConstrainSelectedInstOperands,
130598 // GIR_Coverage, 4552,
130599 GIR_EraseRootFromParent_Done,
130600 // Label 7683: @355017
130601 GIM_Try, /*On fail goto*//*Label 7684*/ GIMT_Encode4(355051), // Rule ID 2212 //
130602 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130603 // MIs[0] imm
130604 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
130605 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
130606 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
130607 // MIs[1] Operand 1
130608 // No operand predicates
130609 GIM_CheckIsSafeToFold, /*NumInsns*/1,
130610 // (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SSHRv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
130611 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHRv2i32_shift),
130612 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130613 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130614 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
130615 GIR_RootConstrainSelectedInstOperands,
130616 // GIR_Coverage, 2212,
130617 GIR_EraseRootFromParent_Done,
130618 // Label 7684: @355051
130619 GIM_Reject,
130620 // Label 7682: @355052
130621 GIM_Reject,
130622 // Label 7671: @355053
130623 GIM_Try, /*On fail goto*//*Label 7685*/ GIMT_Encode4(355129),
130624 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
130625 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130626 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130627 GIM_Try, /*On fail goto*//*Label 7686*/ GIMT_Encode4(355094), // Rule ID 4556 //
130628 // MIs[0] Operand 2
130629 GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(63),
130630 // (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, 63:{ *:[i32] }) => (CMLTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
130631 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i64rz),
130632 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130633 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130634 GIR_RootConstrainSelectedInstOperands,
130635 // GIR_Coverage, 4556,
130636 GIR_EraseRootFromParent_Done,
130637 // Label 7686: @355094
130638 GIM_Try, /*On fail goto*//*Label 7687*/ GIMT_Encode4(355128), // Rule ID 2214 //
130639 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130640 // MIs[0] imm
130641 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
130642 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
130643 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
130644 // MIs[1] Operand 1
130645 // No operand predicates
130646 GIM_CheckIsSafeToFold, /*NumInsns*/1,
130647 // (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (SSHRv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
130648 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHRv2i64_shift),
130649 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130650 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130651 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
130652 GIR_RootConstrainSelectedInstOperands,
130653 // GIR_Coverage, 2214,
130654 GIR_EraseRootFromParent_Done,
130655 // Label 7687: @355128
130656 GIM_Reject,
130657 // Label 7685: @355129
130658 GIM_Reject,
130659 // Label 7672: @355130
130660 GIM_Try, /*On fail goto*//*Label 7688*/ GIMT_Encode4(355206),
130661 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
130662 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130663 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130664 GIM_Try, /*On fail goto*//*Label 7689*/ GIMT_Encode4(355171), // Rule ID 4551 //
130665 // MIs[0] Operand 2
130666 GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(15),
130667 // (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, 15:{ *:[i32] }) => (CMLTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
130668 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i16rz),
130669 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130670 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130671 GIR_RootConstrainSelectedInstOperands,
130672 // GIR_Coverage, 4551,
130673 GIR_EraseRootFromParent_Done,
130674 // Label 7689: @355171
130675 GIM_Try, /*On fail goto*//*Label 7690*/ GIMT_Encode4(355205), // Rule ID 2210 //
130676 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130677 // MIs[0] imm
130678 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
130679 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
130680 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
130681 // MIs[1] Operand 1
130682 // No operand predicates
130683 GIM_CheckIsSafeToFold, /*NumInsns*/1,
130684 // (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (SSHRv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
130685 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHRv4i16_shift),
130686 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130687 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130688 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
130689 GIR_RootConstrainSelectedInstOperands,
130690 // GIR_Coverage, 2210,
130691 GIR_EraseRootFromParent_Done,
130692 // Label 7690: @355205
130693 GIM_Reject,
130694 // Label 7688: @355206
130695 GIM_Reject,
130696 // Label 7673: @355207
130697 GIM_Try, /*On fail goto*//*Label 7691*/ GIMT_Encode4(355283),
130698 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
130699 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130700 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130701 GIM_Try, /*On fail goto*//*Label 7692*/ GIMT_Encode4(355248), // Rule ID 4555 //
130702 // MIs[0] Operand 2
130703 GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(31),
130704 // (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, 31:{ *:[i32] }) => (CMLTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
130705 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i32rz),
130706 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130707 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130708 GIR_RootConstrainSelectedInstOperands,
130709 // GIR_Coverage, 4555,
130710 GIR_EraseRootFromParent_Done,
130711 // Label 7692: @355248
130712 GIM_Try, /*On fail goto*//*Label 7693*/ GIMT_Encode4(355282), // Rule ID 2213 //
130713 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130714 // MIs[0] imm
130715 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
130716 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
130717 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
130718 // MIs[1] Operand 1
130719 // No operand predicates
130720 GIM_CheckIsSafeToFold, /*NumInsns*/1,
130721 // (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (SSHRv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
130722 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHRv4i32_shift),
130723 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130724 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130725 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
130726 GIR_RootConstrainSelectedInstOperands,
130727 // GIR_Coverage, 2213,
130728 GIR_EraseRootFromParent_Done,
130729 // Label 7693: @355282
130730 GIM_Reject,
130731 // Label 7691: @355283
130732 GIM_Reject,
130733 // Label 7674: @355284
130734 GIM_Try, /*On fail goto*//*Label 7694*/ GIMT_Encode4(355360),
130735 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
130736 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130737 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130738 GIM_Try, /*On fail goto*//*Label 7695*/ GIMT_Encode4(355325), // Rule ID 4550 //
130739 // MIs[0] Operand 2
130740 GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(7),
130741 // (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, 7:{ *:[i32] }) => (CMLTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
130742 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i8rz),
130743 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130744 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130745 GIR_RootConstrainSelectedInstOperands,
130746 // GIR_Coverage, 4550,
130747 GIR_EraseRootFromParent_Done,
130748 // Label 7695: @355325
130749 GIM_Try, /*On fail goto*//*Label 7696*/ GIMT_Encode4(355359), // Rule ID 2208 //
130750 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130751 // MIs[0] imm
130752 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
130753 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
130754 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
130755 // MIs[1] Operand 1
130756 // No operand predicates
130757 GIM_CheckIsSafeToFold, /*NumInsns*/1,
130758 // (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm) => (SSHRv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
130759 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHRv8i8_shift),
130760 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130761 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130762 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
130763 GIR_RootConstrainSelectedInstOperands,
130764 // GIR_Coverage, 2208,
130765 GIR_EraseRootFromParent_Done,
130766 // Label 7696: @355359
130767 GIM_Reject,
130768 // Label 7694: @355360
130769 GIM_Reject,
130770 // Label 7675: @355361
130771 GIM_Try, /*On fail goto*//*Label 7697*/ GIMT_Encode4(355437),
130772 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
130773 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130774 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130775 GIM_Try, /*On fail goto*//*Label 7698*/ GIMT_Encode4(355402), // Rule ID 4554 //
130776 // MIs[0] Operand 2
130777 GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(15),
130778 // (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, 15:{ *:[i32] }) => (CMLTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
130779 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i16rz),
130780 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130781 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130782 GIR_RootConstrainSelectedInstOperands,
130783 // GIR_Coverage, 4554,
130784 GIR_EraseRootFromParent_Done,
130785 // Label 7698: @355402
130786 GIM_Try, /*On fail goto*//*Label 7699*/ GIMT_Encode4(355436), // Rule ID 2211 //
130787 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130788 // MIs[0] imm
130789 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
130790 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
130791 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
130792 // MIs[1] Operand 1
130793 // No operand predicates
130794 GIM_CheckIsSafeToFold, /*NumInsns*/1,
130795 // (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (SSHRv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
130796 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHRv8i16_shift),
130797 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130798 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130799 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
130800 GIR_RootConstrainSelectedInstOperands,
130801 // GIR_Coverage, 2211,
130802 GIR_EraseRootFromParent_Done,
130803 // Label 7699: @355436
130804 GIM_Reject,
130805 // Label 7697: @355437
130806 GIM_Reject,
130807 // Label 7676: @355438
130808 GIM_Try, /*On fail goto*//*Label 7700*/ GIMT_Encode4(355514),
130809 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
130810 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130811 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130812 GIM_Try, /*On fail goto*//*Label 7701*/ GIMT_Encode4(355479), // Rule ID 4553 //
130813 // MIs[0] Operand 2
130814 GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(7),
130815 // (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, 7:{ *:[i32] }) => (CMLTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
130816 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv16i8rz),
130817 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130818 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130819 GIR_RootConstrainSelectedInstOperands,
130820 // GIR_Coverage, 4553,
130821 GIR_EraseRootFromParent_Done,
130822 // Label 7701: @355479
130823 GIM_Try, /*On fail goto*//*Label 7702*/ GIMT_Encode4(355513), // Rule ID 2209 //
130824 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130825 // MIs[0] imm
130826 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
130827 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
130828 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
130829 // MIs[1] Operand 1
130830 // No operand predicates
130831 GIM_CheckIsSafeToFold, /*NumInsns*/1,
130832 // (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm) => (SSHRv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
130833 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHRv16i8_shift),
130834 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130835 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130836 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
130837 GIR_RootConstrainSelectedInstOperands,
130838 // GIR_Coverage, 2209,
130839 GIR_EraseRootFromParent_Done,
130840 // Label 7702: @355513
130841 GIM_Reject,
130842 // Label 7700: @355514
130843 GIM_Reject,
130844 // Label 7677: @355515
130845 GIM_Reject,
130846 // Label 143: @355516
130847 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(12), /*)*//*default:*//*Label 7711*/ GIMT_Encode4(355971),
130848 /*GILLT_s64*//*Label 7703*/ GIMT_Encode4(355563), GIMT_Encode4(0),
130849 /*GILLT_v2s32*//*Label 7704*/ GIMT_Encode4(355649),
130850 /*GILLT_v2s64*//*Label 7705*/ GIMT_Encode4(355695),
130851 /*GILLT_v4s16*//*Label 7706*/ GIMT_Encode4(355741),
130852 /*GILLT_v4s32*//*Label 7707*/ GIMT_Encode4(355787),
130853 /*GILLT_v8s8*//*Label 7708*/ GIMT_Encode4(355833),
130854 /*GILLT_v8s16*//*Label 7709*/ GIMT_Encode4(355879),
130855 /*GILLT_v16s8*//*Label 7710*/ GIMT_Encode4(355925),
130856 // Label 7703: @355563
130857 GIM_Try, /*On fail goto*//*Label 7712*/ GIMT_Encode4(355648),
130858 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
130859 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130860 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130861 GIM_Try, /*On fail goto*//*Label 7713*/ GIMT_Encode4(355613), // Rule ID 2114 //
130862 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130863 // MIs[0] imm
130864 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
130865 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
130866 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
130867 // MIs[1] Operand 1
130868 // No operand predicates
130869 GIM_CheckIsSafeToFold, /*NumInsns*/1,
130870 // (AArch64vlshr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (USHRd:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (imm:{ *:[i32] }):$imm)
130871 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHRd),
130872 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130873 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130874 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
130875 GIR_RootConstrainSelectedInstOperands,
130876 // GIR_Coverage, 2114,
130877 GIR_EraseRootFromParent_Done,
130878 // Label 7713: @355613
130879 GIM_Try, /*On fail goto*//*Label 7714*/ GIMT_Encode4(355647), // Rule ID 5886 //
130880 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130881 // MIs[0] imm
130882 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
130883 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
130884 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
130885 // MIs[1] Operand 1
130886 // No operand predicates
130887 GIM_CheckIsSafeToFold, /*NumInsns*/1,
130888 // (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (USHRd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
130889 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHRd),
130890 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130891 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130892 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
130893 GIR_RootConstrainSelectedInstOperands,
130894 // GIR_Coverage, 5886,
130895 GIR_EraseRootFromParent_Done,
130896 // Label 7714: @355647
130897 GIM_Reject,
130898 // Label 7712: @355648
130899 GIM_Reject,
130900 // Label 7704: @355649
130901 GIM_Try, /*On fail goto*//*Label 7715*/ GIMT_Encode4(355694), // Rule ID 2271 //
130902 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130903 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
130904 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130905 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130906 // MIs[0] imm
130907 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
130908 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
130909 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
130910 // MIs[1] Operand 1
130911 // No operand predicates
130912 GIM_CheckIsSafeToFold, /*NumInsns*/1,
130913 // (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (USHRv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i32] }):$imm)
130914 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHRv2i32_shift),
130915 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130916 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130917 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
130918 GIR_RootConstrainSelectedInstOperands,
130919 // GIR_Coverage, 2271,
130920 GIR_EraseRootFromParent_Done,
130921 // Label 7715: @355694
130922 GIM_Reject,
130923 // Label 7705: @355695
130924 GIM_Try, /*On fail goto*//*Label 7716*/ GIMT_Encode4(355740), // Rule ID 2273 //
130925 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130926 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
130927 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130928 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130929 // MIs[0] imm
130930 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
130931 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
130932 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
130933 // MIs[1] Operand 1
130934 // No operand predicates
130935 GIM_CheckIsSafeToFold, /*NumInsns*/1,
130936 // (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm) => (USHRv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm)
130937 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHRv2i64_shift),
130938 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130939 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130940 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
130941 GIR_RootConstrainSelectedInstOperands,
130942 // GIR_Coverage, 2273,
130943 GIR_EraseRootFromParent_Done,
130944 // Label 7716: @355740
130945 GIM_Reject,
130946 // Label 7706: @355741
130947 GIM_Try, /*On fail goto*//*Label 7717*/ GIMT_Encode4(355786), // Rule ID 2269 //
130948 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130949 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
130950 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130951 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130952 // MIs[0] imm
130953 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
130954 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
130955 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
130956 // MIs[1] Operand 1
130957 // No operand predicates
130958 GIM_CheckIsSafeToFold, /*NumInsns*/1,
130959 // (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (USHRv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i32] }):$imm)
130960 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i16_shift),
130961 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130962 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130963 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
130964 GIR_RootConstrainSelectedInstOperands,
130965 // GIR_Coverage, 2269,
130966 GIR_EraseRootFromParent_Done,
130967 // Label 7717: @355786
130968 GIM_Reject,
130969 // Label 7707: @355787
130970 GIM_Try, /*On fail goto*//*Label 7718*/ GIMT_Encode4(355832), // Rule ID 2272 //
130971 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130972 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
130973 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130974 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
130975 // MIs[0] imm
130976 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
130977 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
130978 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
130979 // MIs[1] Operand 1
130980 // No operand predicates
130981 GIM_CheckIsSafeToFold, /*NumInsns*/1,
130982 // (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm) => (USHRv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm)
130983 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
130984 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
130985 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
130986 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
130987 GIR_RootConstrainSelectedInstOperands,
130988 // GIR_Coverage, 2272,
130989 GIR_EraseRootFromParent_Done,
130990 // Label 7718: @355832
130991 GIM_Reject,
130992 // Label 7708: @355833
130993 GIM_Try, /*On fail goto*//*Label 7719*/ GIMT_Encode4(355878), // Rule ID 2267 //
130994 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
130995 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
130996 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130997 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
130998 // MIs[0] imm
130999 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
131000 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
131001 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
131002 // MIs[1] Operand 1
131003 // No operand predicates
131004 GIM_CheckIsSafeToFold, /*NumInsns*/1,
131005 // (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm) => (USHRv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i32] }):$imm)
131006 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHRv8i8_shift),
131007 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
131008 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
131009 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
131010 GIR_RootConstrainSelectedInstOperands,
131011 // GIR_Coverage, 2267,
131012 GIR_EraseRootFromParent_Done,
131013 // Label 7719: @355878
131014 GIM_Reject,
131015 // Label 7709: @355879
131016 GIM_Try, /*On fail goto*//*Label 7720*/ GIMT_Encode4(355924), // Rule ID 2270 //
131017 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131018 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
131019 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131020 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131021 // MIs[0] imm
131022 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
131023 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
131024 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
131025 // MIs[1] Operand 1
131026 // No operand predicates
131027 GIM_CheckIsSafeToFold, /*NumInsns*/1,
131028 // (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm) => (USHRv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm)
131029 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHRv8i16_shift),
131030 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
131031 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
131032 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
131033 GIR_RootConstrainSelectedInstOperands,
131034 // GIR_Coverage, 2270,
131035 GIR_EraseRootFromParent_Done,
131036 // Label 7720: @355924
131037 GIM_Reject,
131038 // Label 7710: @355925
131039 GIM_Try, /*On fail goto*//*Label 7721*/ GIMT_Encode4(355970), // Rule ID 2268 //
131040 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131041 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
131042 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131043 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131044 // MIs[0] imm
131045 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
131046 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
131047 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
131048 // MIs[1] Operand 1
131049 // No operand predicates
131050 GIM_CheckIsSafeToFold, /*NumInsns*/1,
131051 // (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm) => (USHRv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm)
131052 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHRv16i8_shift),
131053 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
131054 GIR_RootToRootCopy, /*OpIdx*/1, // Rn
131055 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
131056 GIR_RootConstrainSelectedInstOperands,
131057 // GIR_Coverage, 2268,
131058 GIR_EraseRootFromParent_Done,
131059 // Label 7721: @355970
131060 GIM_Reject,
131061 // Label 7711: @355971
131062 GIM_Reject,
131063 // Label 144: @355972
131064 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 7740*/ GIMT_Encode4(356796),
131065 /*GILLT_v2s32*//*Label 7722*/ GIMT_Encode4(356059),
131066 /*GILLT_v2s64*//*Label 7723*/ GIMT_Encode4(356114),
131067 /*GILLT_v4s16*//*Label 7724*/ GIMT_Encode4(356169),
131068 /*GILLT_v4s32*//*Label 7725*/ GIMT_Encode4(356239),
131069 /*GILLT_v8s8*//*Label 7726*/ GIMT_Encode4(356294),
131070 /*GILLT_v8s16*//*Label 7727*/ GIMT_Encode4(356328),
131071 /*GILLT_v16s8*//*Label 7728*/ GIMT_Encode4(356398), GIMT_Encode4(0),
131072 /*GILLT_nxv2s1*//*Label 7729*/ GIMT_Encode4(356432),
131073 /*GILLT_nxv2s16*//*Label 7730*/ GIMT_Encode4(356458),
131074 /*GILLT_nxv2s32*//*Label 7731*/ GIMT_Encode4(356484),
131075 /*GILLT_nxv2s64*//*Label 7732*/ GIMT_Encode4(356510),
131076 /*GILLT_nxv4s1*//*Label 7733*/ GIMT_Encode4(356557),
131077 /*GILLT_nxv4s16*//*Label 7734*/ GIMT_Encode4(356583),
131078 /*GILLT_nxv4s32*//*Label 7735*/ GIMT_Encode4(356609),
131079 /*GILLT_nxv8s1*//*Label 7736*/ GIMT_Encode4(356656),
131080 /*GILLT_nxv8s16*//*Label 7737*/ GIMT_Encode4(356682),
131081 /*GILLT_nxv16s1*//*Label 7738*/ GIMT_Encode4(356744),
131082 /*GILLT_nxv16s8*//*Label 7739*/ GIMT_Encode4(356770),
131083 // Label 7722: @356059
131084 GIM_Try, /*On fail goto*//*Label 7741*/ GIMT_Encode4(356113),
131085 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
131086 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
131087 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
131088 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
131089 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
131090 GIM_Try, /*On fail goto*//*Label 7742*/ GIMT_Encode4(356097), // Rule ID 1889 //
131091 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131092 // (AArch64zip1:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (ZIP1v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
131093 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v2i32),
131094 GIR_RootConstrainSelectedInstOperands,
131095 // GIR_Coverage, 1889,
131096 GIR_Done,
131097 // Label 7742: @356097
131098 GIM_Try, /*On fail goto*//*Label 7743*/ GIMT_Encode4(356112), // Rule ID 5140 //
131099 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131100 // (AArch64zip1:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (ZIP1v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
131101 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v2i32),
131102 GIR_RootConstrainSelectedInstOperands,
131103 // GIR_Coverage, 5140,
131104 GIR_Done,
131105 // Label 7743: @356112
131106 GIM_Reject,
131107 // Label 7741: @356113
131108 GIM_Reject,
131109 // Label 7723: @356114
131110 GIM_Try, /*On fail goto*//*Label 7744*/ GIMT_Encode4(356168),
131111 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
131112 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
131113 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131114 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131115 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131116 GIM_Try, /*On fail goto*//*Label 7745*/ GIMT_Encode4(356152), // Rule ID 1891 //
131117 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131118 // (AArch64zip1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ZIP1v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
131119 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v2i64),
131120 GIR_RootConstrainSelectedInstOperands,
131121 // GIR_Coverage, 1891,
131122 GIR_Done,
131123 // Label 7745: @356152
131124 GIM_Try, /*On fail goto*//*Label 7746*/ GIMT_Encode4(356167), // Rule ID 5142 //
131125 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131126 // (AArch64zip1:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (ZIP1v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
131127 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v2i64),
131128 GIR_RootConstrainSelectedInstOperands,
131129 // GIR_Coverage, 5142,
131130 GIR_Done,
131131 // Label 7746: @356167
131132 GIM_Reject,
131133 // Label 7744: @356168
131134 GIM_Reject,
131135 // Label 7724: @356169
131136 GIM_Try, /*On fail goto*//*Label 7747*/ GIMT_Encode4(356238),
131137 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
131138 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
131139 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
131140 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
131141 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
131142 GIM_Try, /*On fail goto*//*Label 7748*/ GIMT_Encode4(356207), // Rule ID 1887 //
131143 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131144 // (AArch64zip1:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (ZIP1v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
131145 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v4i16),
131146 GIR_RootConstrainSelectedInstOperands,
131147 // GIR_Coverage, 1887,
131148 GIR_Done,
131149 // Label 7748: @356207
131150 GIM_Try, /*On fail goto*//*Label 7749*/ GIMT_Encode4(356222), // Rule ID 5136 //
131151 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131152 // (AArch64zip1:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (ZIP1v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
131153 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v4i16),
131154 GIR_RootConstrainSelectedInstOperands,
131155 // GIR_Coverage, 5136,
131156 GIR_Done,
131157 // Label 7749: @356222
131158 GIM_Try, /*On fail goto*//*Label 7750*/ GIMT_Encode4(356237), // Rule ID 5137 //
131159 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131160 // (AArch64zip1:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) => (ZIP1v4i16:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm)
131161 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v4i16),
131162 GIR_RootConstrainSelectedInstOperands,
131163 // GIR_Coverage, 5137,
131164 GIR_Done,
131165 // Label 7750: @356237
131166 GIM_Reject,
131167 // Label 7747: @356238
131168 GIM_Reject,
131169 // Label 7725: @356239
131170 GIM_Try, /*On fail goto*//*Label 7751*/ GIMT_Encode4(356293),
131171 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
131172 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
131173 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131174 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131175 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131176 GIM_Try, /*On fail goto*//*Label 7752*/ GIMT_Encode4(356277), // Rule ID 1890 //
131177 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131178 // (AArch64zip1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ZIP1v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
131179 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v4i32),
131180 GIR_RootConstrainSelectedInstOperands,
131181 // GIR_Coverage, 1890,
131182 GIR_Done,
131183 // Label 7752: @356277
131184 GIM_Try, /*On fail goto*//*Label 7753*/ GIMT_Encode4(356292), // Rule ID 5141 //
131185 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131186 // (AArch64zip1:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (ZIP1v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
131187 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v4i32),
131188 GIR_RootConstrainSelectedInstOperands,
131189 // GIR_Coverage, 5141,
131190 GIR_Done,
131191 // Label 7753: @356292
131192 GIM_Reject,
131193 // Label 7751: @356293
131194 GIM_Reject,
131195 // Label 7726: @356294
131196 GIM_Try, /*On fail goto*//*Label 7754*/ GIMT_Encode4(356327), // Rule ID 1885 //
131197 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131198 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
131199 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
131200 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
131201 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
131202 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
131203 // (AArch64zip1:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ZIP1v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
131204 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v8i8),
131205 GIR_RootConstrainSelectedInstOperands,
131206 // GIR_Coverage, 1885,
131207 GIR_Done,
131208 // Label 7754: @356327
131209 GIM_Reject,
131210 // Label 7727: @356328
131211 GIM_Try, /*On fail goto*//*Label 7755*/ GIMT_Encode4(356397),
131212 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
131213 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
131214 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131215 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131216 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131217 GIM_Try, /*On fail goto*//*Label 7756*/ GIMT_Encode4(356366), // Rule ID 1888 //
131218 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131219 // (AArch64zip1:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ZIP1v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
131220 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v8i16),
131221 GIR_RootConstrainSelectedInstOperands,
131222 // GIR_Coverage, 1888,
131223 GIR_Done,
131224 // Label 7756: @356366
131225 GIM_Try, /*On fail goto*//*Label 7757*/ GIMT_Encode4(356381), // Rule ID 5138 //
131226 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131227 // (AArch64zip1:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (ZIP1v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
131228 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v8i16),
131229 GIR_RootConstrainSelectedInstOperands,
131230 // GIR_Coverage, 5138,
131231 GIR_Done,
131232 // Label 7757: @356381
131233 GIM_Try, /*On fail goto*//*Label 7758*/ GIMT_Encode4(356396), // Rule ID 5139 //
131234 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131235 // (AArch64zip1:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (ZIP1v8i16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm)
131236 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v8i16),
131237 GIR_RootConstrainSelectedInstOperands,
131238 // GIR_Coverage, 5139,
131239 GIR_Done,
131240 // Label 7758: @356396
131241 GIM_Reject,
131242 // Label 7755: @356397
131243 GIM_Reject,
131244 // Label 7728: @356398
131245 GIM_Try, /*On fail goto*//*Label 7759*/ GIMT_Encode4(356431), // Rule ID 1886 //
131246 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131247 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
131248 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
131249 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131250 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131251 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131252 // (AArch64zip1:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ZIP1v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
131253 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v16i8),
131254 GIR_RootConstrainSelectedInstOperands,
131255 // GIR_Coverage, 1886,
131256 GIR_Done,
131257 // Label 7759: @356431
131258 GIM_Reject,
131259 // Label 7729: @356432
131260 GIM_Try, /*On fail goto*//*Label 7760*/ GIMT_Encode4(356457), // Rule ID 3259 //
131261 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131262 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
131263 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
131264 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
131265 // (AArch64zip1:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2) => (ZIP1_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
131266 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_D),
131267 GIR_RootConstrainSelectedInstOperands,
131268 // GIR_Coverage, 3259,
131269 GIR_Done,
131270 // Label 7760: @356457
131271 GIM_Reject,
131272 // Label 7730: @356458
131273 GIM_Try, /*On fail goto*//*Label 7761*/ GIMT_Encode4(356483), // Rule ID 2804 //
131274 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131275 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
131276 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
131277 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
131278 // (AArch64zip1:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2) => (ZIP1_ZZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$Op1, ?:{ *:[nxv2f16] }:$Op2)
131279 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_D),
131280 GIR_RootConstrainSelectedInstOperands,
131281 // GIR_Coverage, 2804,
131282 GIR_Done,
131283 // Label 7761: @356483
131284 GIM_Reject,
131285 // Label 7731: @356484
131286 GIM_Try, /*On fail goto*//*Label 7762*/ GIMT_Encode4(356509), // Rule ID 2805 //
131287 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131288 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
131289 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
131290 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
131291 // (AArch64zip1:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2) => (ZIP1_ZZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$Op1, ?:{ *:[nxv2f32] }:$Op2)
131292 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_D),
131293 GIR_RootConstrainSelectedInstOperands,
131294 // GIR_Coverage, 2805,
131295 GIR_Done,
131296 // Label 7762: @356509
131297 GIM_Reject,
131298 // Label 7732: @356510
131299 GIM_Try, /*On fail goto*//*Label 7763*/ GIMT_Encode4(356556),
131300 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
131301 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
131302 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
131303 GIM_Try, /*On fail goto*//*Label 7764*/ GIMT_Encode4(356540), // Rule ID 2800 //
131304 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131305 // (AArch64zip1:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (ZIP1_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
131306 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_D),
131307 GIR_RootConstrainSelectedInstOperands,
131308 // GIR_Coverage, 2800,
131309 GIR_Done,
131310 // Label 7764: @356540
131311 GIM_Try, /*On fail goto*//*Label 7765*/ GIMT_Encode4(356555), // Rule ID 2806 //
131312 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131313 // (AArch64zip1:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (ZIP1_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
131314 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_D),
131315 GIR_RootConstrainSelectedInstOperands,
131316 // GIR_Coverage, 2806,
131317 GIR_Done,
131318 // Label 7765: @356555
131319 GIM_Reject,
131320 // Label 7763: @356556
131321 GIM_Reject,
131322 // Label 7733: @356557
131323 GIM_Try, /*On fail goto*//*Label 7766*/ GIMT_Encode4(356582), // Rule ID 3258 //
131324 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131325 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
131326 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
131327 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
131328 // (AArch64zip1:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2) => (ZIP1_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
131329 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_S),
131330 GIR_RootConstrainSelectedInstOperands,
131331 // GIR_Coverage, 3258,
131332 GIR_Done,
131333 // Label 7766: @356582
131334 GIM_Reject,
131335 // Label 7734: @356583
131336 GIM_Try, /*On fail goto*//*Label 7767*/ GIMT_Encode4(356608), // Rule ID 2802 //
131337 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131338 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
131339 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
131340 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
131341 // (AArch64zip1:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2) => (ZIP1_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$Op1, ?:{ *:[nxv4f16] }:$Op2)
131342 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_S),
131343 GIR_RootConstrainSelectedInstOperands,
131344 // GIR_Coverage, 2802,
131345 GIR_Done,
131346 // Label 7767: @356608
131347 GIM_Reject,
131348 // Label 7735: @356609
131349 GIM_Try, /*On fail goto*//*Label 7768*/ GIMT_Encode4(356655),
131350 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
131351 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
131352 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
131353 GIM_Try, /*On fail goto*//*Label 7769*/ GIMT_Encode4(356639), // Rule ID 2799 //
131354 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131355 // (AArch64zip1:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (ZIP1_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
131356 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_S),
131357 GIR_RootConstrainSelectedInstOperands,
131358 // GIR_Coverage, 2799,
131359 GIR_Done,
131360 // Label 7769: @356639
131361 GIM_Try, /*On fail goto*//*Label 7770*/ GIMT_Encode4(356654), // Rule ID 2803 //
131362 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131363 // (AArch64zip1:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (ZIP1_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
131364 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_S),
131365 GIR_RootConstrainSelectedInstOperands,
131366 // GIR_Coverage, 2803,
131367 GIR_Done,
131368 // Label 7770: @356654
131369 GIM_Reject,
131370 // Label 7768: @356655
131371 GIM_Reject,
131372 // Label 7736: @356656
131373 GIM_Try, /*On fail goto*//*Label 7771*/ GIMT_Encode4(356681), // Rule ID 3257 //
131374 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131375 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
131376 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
131377 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
131378 // (AArch64zip1:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2) => (ZIP1_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
131379 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_H),
131380 GIR_RootConstrainSelectedInstOperands,
131381 // GIR_Coverage, 3257,
131382 GIR_Done,
131383 // Label 7771: @356681
131384 GIM_Reject,
131385 // Label 7737: @356682
131386 GIM_Try, /*On fail goto*//*Label 7772*/ GIMT_Encode4(356743),
131387 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
131388 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
131389 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
131390 GIM_Try, /*On fail goto*//*Label 7773*/ GIMT_Encode4(356712), // Rule ID 2798 //
131391 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131392 // (AArch64zip1:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (ZIP1_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
131393 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_H),
131394 GIR_RootConstrainSelectedInstOperands,
131395 // GIR_Coverage, 2798,
131396 GIR_Done,
131397 // Label 7773: @356712
131398 GIM_Try, /*On fail goto*//*Label 7774*/ GIMT_Encode4(356727), // Rule ID 2801 //
131399 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131400 // (AArch64zip1:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (ZIP1_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
131401 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_H),
131402 GIR_RootConstrainSelectedInstOperands,
131403 // GIR_Coverage, 2801,
131404 GIR_Done,
131405 // Label 7774: @356727
131406 GIM_Try, /*On fail goto*//*Label 7775*/ GIMT_Encode4(356742), // Rule ID 2807 //
131407 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131408 // (AArch64zip1:{ *:[nxv8bf16] } nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2) => (ZIP1_ZZZ_H:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2)
131409 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_H),
131410 GIR_RootConstrainSelectedInstOperands,
131411 // GIR_Coverage, 2807,
131412 GIR_Done,
131413 // Label 7775: @356742
131414 GIM_Reject,
131415 // Label 7772: @356743
131416 GIM_Reject,
131417 // Label 7738: @356744
131418 GIM_Try, /*On fail goto*//*Label 7776*/ GIMT_Encode4(356769), // Rule ID 2338 //
131419 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131420 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
131421 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
131422 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
131423 // (AArch64zip1:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (ZIP1_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
131424 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_B),
131425 GIR_RootConstrainSelectedInstOperands,
131426 // GIR_Coverage, 2338,
131427 GIR_Done,
131428 // Label 7776: @356769
131429 GIM_Reject,
131430 // Label 7739: @356770
131431 GIM_Try, /*On fail goto*//*Label 7777*/ GIMT_Encode4(356795), // Rule ID 2797 //
131432 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131433 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
131434 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
131435 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
131436 // (AArch64zip1:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (ZIP1_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
131437 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_B),
131438 GIR_RootConstrainSelectedInstOperands,
131439 // GIR_Coverage, 2797,
131440 GIR_Done,
131441 // Label 7777: @356795
131442 GIM_Reject,
131443 // Label 7740: @356796
131444 GIM_Reject,
131445 // Label 145: @356797
131446 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 7796*/ GIMT_Encode4(357621),
131447 /*GILLT_v2s32*//*Label 7778*/ GIMT_Encode4(356884),
131448 /*GILLT_v2s64*//*Label 7779*/ GIMT_Encode4(356939),
131449 /*GILLT_v4s16*//*Label 7780*/ GIMT_Encode4(356994),
131450 /*GILLT_v4s32*//*Label 7781*/ GIMT_Encode4(357064),
131451 /*GILLT_v8s8*//*Label 7782*/ GIMT_Encode4(357119),
131452 /*GILLT_v8s16*//*Label 7783*/ GIMT_Encode4(357153),
131453 /*GILLT_v16s8*//*Label 7784*/ GIMT_Encode4(357223), GIMT_Encode4(0),
131454 /*GILLT_nxv2s1*//*Label 7785*/ GIMT_Encode4(357257),
131455 /*GILLT_nxv2s16*//*Label 7786*/ GIMT_Encode4(357283),
131456 /*GILLT_nxv2s32*//*Label 7787*/ GIMT_Encode4(357309),
131457 /*GILLT_nxv2s64*//*Label 7788*/ GIMT_Encode4(357335),
131458 /*GILLT_nxv4s1*//*Label 7789*/ GIMT_Encode4(357382),
131459 /*GILLT_nxv4s16*//*Label 7790*/ GIMT_Encode4(357408),
131460 /*GILLT_nxv4s32*//*Label 7791*/ GIMT_Encode4(357434),
131461 /*GILLT_nxv8s1*//*Label 7792*/ GIMT_Encode4(357481),
131462 /*GILLT_nxv8s16*//*Label 7793*/ GIMT_Encode4(357507),
131463 /*GILLT_nxv16s1*//*Label 7794*/ GIMT_Encode4(357569),
131464 /*GILLT_nxv16s8*//*Label 7795*/ GIMT_Encode4(357595),
131465 // Label 7778: @356884
131466 GIM_Try, /*On fail goto*//*Label 7797*/ GIMT_Encode4(356938),
131467 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
131468 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
131469 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
131470 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
131471 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
131472 GIM_Try, /*On fail goto*//*Label 7798*/ GIMT_Encode4(356922), // Rule ID 1896 //
131473 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131474 // (AArch64zip2:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm) => (ZIP2v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
131475 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v2i32),
131476 GIR_RootConstrainSelectedInstOperands,
131477 // GIR_Coverage, 1896,
131478 GIR_Done,
131479 // Label 7798: @356922
131480 GIM_Try, /*On fail goto*//*Label 7799*/ GIMT_Encode4(356937), // Rule ID 5147 //
131481 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131482 // (AArch64zip2:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm) => (ZIP2v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
131483 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v2i32),
131484 GIR_RootConstrainSelectedInstOperands,
131485 // GIR_Coverage, 5147,
131486 GIR_Done,
131487 // Label 7799: @356937
131488 GIM_Reject,
131489 // Label 7797: @356938
131490 GIM_Reject,
131491 // Label 7779: @356939
131492 GIM_Try, /*On fail goto*//*Label 7800*/ GIMT_Encode4(356993),
131493 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
131494 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
131495 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131496 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131497 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131498 GIM_Try, /*On fail goto*//*Label 7801*/ GIMT_Encode4(356977), // Rule ID 1898 //
131499 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131500 // (AArch64zip2:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm) => (ZIP2v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
131501 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v2i64),
131502 GIR_RootConstrainSelectedInstOperands,
131503 // GIR_Coverage, 1898,
131504 GIR_Done,
131505 // Label 7801: @356977
131506 GIM_Try, /*On fail goto*//*Label 7802*/ GIMT_Encode4(356992), // Rule ID 5149 //
131507 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131508 // (AArch64zip2:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm) => (ZIP2v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
131509 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v2i64),
131510 GIR_RootConstrainSelectedInstOperands,
131511 // GIR_Coverage, 5149,
131512 GIR_Done,
131513 // Label 7802: @356992
131514 GIM_Reject,
131515 // Label 7800: @356993
131516 GIM_Reject,
131517 // Label 7780: @356994
131518 GIM_Try, /*On fail goto*//*Label 7803*/ GIMT_Encode4(357063),
131519 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
131520 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
131521 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
131522 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
131523 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
131524 GIM_Try, /*On fail goto*//*Label 7804*/ GIMT_Encode4(357032), // Rule ID 1894 //
131525 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131526 // (AArch64zip2:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm) => (ZIP2v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
131527 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v4i16),
131528 GIR_RootConstrainSelectedInstOperands,
131529 // GIR_Coverage, 1894,
131530 GIR_Done,
131531 // Label 7804: @357032
131532 GIM_Try, /*On fail goto*//*Label 7805*/ GIMT_Encode4(357047), // Rule ID 5143 //
131533 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131534 // (AArch64zip2:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm) => (ZIP2v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
131535 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v4i16),
131536 GIR_RootConstrainSelectedInstOperands,
131537 // GIR_Coverage, 5143,
131538 GIR_Done,
131539 // Label 7805: @357047
131540 GIM_Try, /*On fail goto*//*Label 7806*/ GIMT_Encode4(357062), // Rule ID 5144 //
131541 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131542 // (AArch64zip2:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm) => (ZIP2v4i16:{ *:[v4bf16] } V64:{ *:[v4bf16] }:$Rn, V64:{ *:[v4bf16] }:$Rm)
131543 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v4i16),
131544 GIR_RootConstrainSelectedInstOperands,
131545 // GIR_Coverage, 5144,
131546 GIR_Done,
131547 // Label 7806: @357062
131548 GIM_Reject,
131549 // Label 7803: @357063
131550 GIM_Reject,
131551 // Label 7781: @357064
131552 GIM_Try, /*On fail goto*//*Label 7807*/ GIMT_Encode4(357118),
131553 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
131554 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
131555 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131556 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131557 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131558 GIM_Try, /*On fail goto*//*Label 7808*/ GIMT_Encode4(357102), // Rule ID 1897 //
131559 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131560 // (AArch64zip2:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm) => (ZIP2v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
131561 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v4i32),
131562 GIR_RootConstrainSelectedInstOperands,
131563 // GIR_Coverage, 1897,
131564 GIR_Done,
131565 // Label 7808: @357102
131566 GIM_Try, /*On fail goto*//*Label 7809*/ GIMT_Encode4(357117), // Rule ID 5148 //
131567 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131568 // (AArch64zip2:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm) => (ZIP2v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
131569 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v4i32),
131570 GIR_RootConstrainSelectedInstOperands,
131571 // GIR_Coverage, 5148,
131572 GIR_Done,
131573 // Label 7809: @357117
131574 GIM_Reject,
131575 // Label 7807: @357118
131576 GIM_Reject,
131577 // Label 7782: @357119
131578 GIM_Try, /*On fail goto*//*Label 7810*/ GIMT_Encode4(357152), // Rule ID 1892 //
131579 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131580 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
131581 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
131582 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
131583 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
131584 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
131585 // (AArch64zip2:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm) => (ZIP2v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
131586 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v8i8),
131587 GIR_RootConstrainSelectedInstOperands,
131588 // GIR_Coverage, 1892,
131589 GIR_Done,
131590 // Label 7810: @357152
131591 GIM_Reject,
131592 // Label 7783: @357153
131593 GIM_Try, /*On fail goto*//*Label 7811*/ GIMT_Encode4(357222),
131594 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
131595 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
131596 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131597 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131598 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131599 GIM_Try, /*On fail goto*//*Label 7812*/ GIMT_Encode4(357191), // Rule ID 1895 //
131600 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131601 // (AArch64zip2:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm) => (ZIP2v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
131602 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v8i16),
131603 GIR_RootConstrainSelectedInstOperands,
131604 // GIR_Coverage, 1895,
131605 GIR_Done,
131606 // Label 7812: @357191
131607 GIM_Try, /*On fail goto*//*Label 7813*/ GIMT_Encode4(357206), // Rule ID 5145 //
131608 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131609 // (AArch64zip2:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm) => (ZIP2v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
131610 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v8i16),
131611 GIR_RootConstrainSelectedInstOperands,
131612 // GIR_Coverage, 5145,
131613 GIR_Done,
131614 // Label 7813: @357206
131615 GIM_Try, /*On fail goto*//*Label 7814*/ GIMT_Encode4(357221), // Rule ID 5146 //
131616 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131617 // (AArch64zip2:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm) => (ZIP2v8i16:{ *:[v8bf16] } V128:{ *:[v8bf16] }:$Rn, V128:{ *:[v8bf16] }:$Rm)
131618 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v8i16),
131619 GIR_RootConstrainSelectedInstOperands,
131620 // GIR_Coverage, 5146,
131621 GIR_Done,
131622 // Label 7814: @357221
131623 GIM_Reject,
131624 // Label 7811: @357222
131625 GIM_Reject,
131626 // Label 7784: @357223
131627 GIM_Try, /*On fail goto*//*Label 7815*/ GIMT_Encode4(357256), // Rule ID 1893 //
131628 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
131629 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
131630 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
131631 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131632 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131633 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
131634 // (AArch64zip2:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm) => (ZIP2v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
131635 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v16i8),
131636 GIR_RootConstrainSelectedInstOperands,
131637 // GIR_Coverage, 1893,
131638 GIR_Done,
131639 // Label 7815: @357256
131640 GIM_Reject,
131641 // Label 7785: @357257
131642 GIM_Try, /*On fail goto*//*Label 7816*/ GIMT_Encode4(357282), // Rule ID 8637 //
131643 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131644 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
131645 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
131646 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
131647 // (AArch64zip2:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2) => (ZIP2_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
131648 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_D),
131649 GIR_RootConstrainSelectedInstOperands,
131650 // GIR_Coverage, 8637,
131651 GIR_Done,
131652 // Label 7816: @357282
131653 GIM_Reject,
131654 // Label 7786: @357283
131655 GIM_Try, /*On fail goto*//*Label 7817*/ GIMT_Encode4(357308), // Rule ID 8587 //
131656 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131657 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
131658 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
131659 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
131660 // (AArch64zip2:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2) => (ZIP2_ZZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$Op1, ?:{ *:[nxv2f16] }:$Op2)
131661 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_D),
131662 GIR_RootConstrainSelectedInstOperands,
131663 // GIR_Coverage, 8587,
131664 GIR_Done,
131665 // Label 7817: @357308
131666 GIM_Reject,
131667 // Label 7787: @357309
131668 GIM_Try, /*On fail goto*//*Label 7818*/ GIMT_Encode4(357334), // Rule ID 8588 //
131669 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131670 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
131671 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
131672 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
131673 // (AArch64zip2:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2) => (ZIP2_ZZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$Op1, ?:{ *:[nxv2f32] }:$Op2)
131674 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_D),
131675 GIR_RootConstrainSelectedInstOperands,
131676 // GIR_Coverage, 8588,
131677 GIR_Done,
131678 // Label 7818: @357334
131679 GIM_Reject,
131680 // Label 7788: @357335
131681 GIM_Try, /*On fail goto*//*Label 7819*/ GIMT_Encode4(357381),
131682 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
131683 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
131684 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
131685 GIM_Try, /*On fail goto*//*Label 7820*/ GIMT_Encode4(357365), // Rule ID 8583 //
131686 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131687 // (AArch64zip2:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2) => (ZIP2_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
131688 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_D),
131689 GIR_RootConstrainSelectedInstOperands,
131690 // GIR_Coverage, 8583,
131691 GIR_Done,
131692 // Label 7820: @357365
131693 GIM_Try, /*On fail goto*//*Label 7821*/ GIMT_Encode4(357380), // Rule ID 8589 //
131694 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131695 // (AArch64zip2:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2) => (ZIP2_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
131696 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_D),
131697 GIR_RootConstrainSelectedInstOperands,
131698 // GIR_Coverage, 8589,
131699 GIR_Done,
131700 // Label 7821: @357380
131701 GIM_Reject,
131702 // Label 7819: @357381
131703 GIM_Reject,
131704 // Label 7789: @357382
131705 GIM_Try, /*On fail goto*//*Label 7822*/ GIMT_Encode4(357407), // Rule ID 8636 //
131706 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131707 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
131708 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
131709 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
131710 // (AArch64zip2:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2) => (ZIP2_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
131711 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_S),
131712 GIR_RootConstrainSelectedInstOperands,
131713 // GIR_Coverage, 8636,
131714 GIR_Done,
131715 // Label 7822: @357407
131716 GIM_Reject,
131717 // Label 7790: @357408
131718 GIM_Try, /*On fail goto*//*Label 7823*/ GIMT_Encode4(357433), // Rule ID 8585 //
131719 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131720 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
131721 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
131722 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
131723 // (AArch64zip2:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2) => (ZIP2_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$Op1, ?:{ *:[nxv4f16] }:$Op2)
131724 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_S),
131725 GIR_RootConstrainSelectedInstOperands,
131726 // GIR_Coverage, 8585,
131727 GIR_Done,
131728 // Label 7823: @357433
131729 GIM_Reject,
131730 // Label 7791: @357434
131731 GIM_Try, /*On fail goto*//*Label 7824*/ GIMT_Encode4(357480),
131732 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
131733 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
131734 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
131735 GIM_Try, /*On fail goto*//*Label 7825*/ GIMT_Encode4(357464), // Rule ID 8582 //
131736 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131737 // (AArch64zip2:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2) => (ZIP2_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
131738 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_S),
131739 GIR_RootConstrainSelectedInstOperands,
131740 // GIR_Coverage, 8582,
131741 GIR_Done,
131742 // Label 7825: @357464
131743 GIM_Try, /*On fail goto*//*Label 7826*/ GIMT_Encode4(357479), // Rule ID 8586 //
131744 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131745 // (AArch64zip2:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2) => (ZIP2_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
131746 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_S),
131747 GIR_RootConstrainSelectedInstOperands,
131748 // GIR_Coverage, 8586,
131749 GIR_Done,
131750 // Label 7826: @357479
131751 GIM_Reject,
131752 // Label 7824: @357480
131753 GIM_Reject,
131754 // Label 7792: @357481
131755 GIM_Try, /*On fail goto*//*Label 7827*/ GIMT_Encode4(357506), // Rule ID 8635 //
131756 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131757 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
131758 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
131759 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
131760 // (AArch64zip2:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2) => (ZIP2_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
131761 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_H),
131762 GIR_RootConstrainSelectedInstOperands,
131763 // GIR_Coverage, 8635,
131764 GIR_Done,
131765 // Label 7827: @357506
131766 GIM_Reject,
131767 // Label 7793: @357507
131768 GIM_Try, /*On fail goto*//*Label 7828*/ GIMT_Encode4(357568),
131769 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
131770 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
131771 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
131772 GIM_Try, /*On fail goto*//*Label 7829*/ GIMT_Encode4(357537), // Rule ID 8581 //
131773 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131774 // (AArch64zip2:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2) => (ZIP2_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
131775 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_H),
131776 GIR_RootConstrainSelectedInstOperands,
131777 // GIR_Coverage, 8581,
131778 GIR_Done,
131779 // Label 7829: @357537
131780 GIM_Try, /*On fail goto*//*Label 7830*/ GIMT_Encode4(357552), // Rule ID 8584 //
131781 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131782 // (AArch64zip2:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2) => (ZIP2_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
131783 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_H),
131784 GIR_RootConstrainSelectedInstOperands,
131785 // GIR_Coverage, 8584,
131786 GIR_Done,
131787 // Label 7830: @357552
131788 GIM_Try, /*On fail goto*//*Label 7831*/ GIMT_Encode4(357567), // Rule ID 8590 //
131789 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131790 // (AArch64zip2:{ *:[nxv8bf16] } nxv8bf16:{ *:[nxv8bf16] }:$Op1, nxv8bf16:{ *:[nxv8bf16] }:$Op2) => (ZIP2_ZZZ_H:{ *:[nxv8bf16] } ?:{ *:[nxv8bf16] }:$Op1, ?:{ *:[nxv8bf16] }:$Op2)
131791 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_H),
131792 GIR_RootConstrainSelectedInstOperands,
131793 // GIR_Coverage, 8590,
131794 GIR_Done,
131795 // Label 7831: @357567
131796 GIM_Reject,
131797 // Label 7828: @357568
131798 GIM_Reject,
131799 // Label 7794: @357569
131800 GIM_Try, /*On fail goto*//*Label 7832*/ GIMT_Encode4(357594), // Rule ID 2342 //
131801 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131802 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
131803 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
131804 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
131805 // (AArch64zip2:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm) => (ZIP2_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
131806 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_B),
131807 GIR_RootConstrainSelectedInstOperands,
131808 // GIR_Coverage, 2342,
131809 GIR_Done,
131810 // Label 7832: @357594
131811 GIM_Reject,
131812 // Label 7795: @357595
131813 GIM_Try, /*On fail goto*//*Label 7833*/ GIMT_Encode4(357620), // Rule ID 8580 //
131814 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVEorSME),
131815 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
131816 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
131817 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
131818 // (AArch64zip2:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2) => (ZIP2_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
131819 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_B),
131820 GIR_RootConstrainSelectedInstOperands,
131821 // GIR_Coverage, 8580,
131822 GIR_Done,
131823 // Label 7833: @357620
131824 GIM_Reject,
131825 // Label 7796: @357621
131826 GIM_Reject,
131827 // Label 146: @357622
131828 GIM_Reject,
131829 }; // Size: 357623 bytes
131830 return MatchTable0;
131831}
131832#undef GIMT_Encode2
131833#undef GIMT_Encode4
131834#undef GIMT_Encode8
131835
131836#endif // ifdef GET_GLOBALISEL_IMPL
131837
131838#ifdef GET_GLOBALISEL_PREDICATES_DECL
131839PredicateBitset AvailableModuleFeatures;
131840mutable PredicateBitset AvailableFunctionFeatures;
131841PredicateBitset getAvailableFeatures() const {
131842 return AvailableModuleFeatures | AvailableFunctionFeatures;
131843}
131844PredicateBitset
131845computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const;
131846PredicateBitset
131847computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget,
131848 const MachineFunction *MF) const;
131849void setupGeneratedPerFunctionState(MachineFunction &MF) override;
131850#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
131851#ifdef GET_GLOBALISEL_PREDICATES_INIT
131852AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
131853AvailableFunctionFeatures()
131854#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
131855